ISL6625A [RENESAS]
Synchronous Rectified Buck MOSFET Drivers;
| 型号： | ISL6625A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Synchronous Rectified Buck MOSFET Drivers |
| 文件： | 总10页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL6625A
Synchronous Rectified Buck MOSFET Drivers
FN7978
Rev 0.00
September 19, 2012
The ISL6625A is a high frequency MOSFET driver designed to
drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology.
Features
• Dual MOSFET drives for synchronous rectified bridge
• Advanced adaptive zero shoot-through protection
- PHASE detection
In ISL6625A, the upper and lower gates are both driven to an
externally applied voltage. This provides the capability to
optimize applications involving trade-offs between gate charge
and conduction losses.
- LGATE detection
- Auto-Zero of r
DS(ON)
conduction offset effect
An advanced adaptive shoot-through protection is integrated to
prevent both the upper and lower MOSFETs from conducting
simultaneously and to minimize dead time. The ISL6625A has
a 10kΩ integrated high-side gate-to-source resistor to prevent
self turn-on due to high input bus dV/dt.
• Low standby bias current
• 36V internal bootstrap switcher
• Bootstrap capacitor overcharging prevention
• Integrated high-side gate-to-source resistor to prevent from
self turn-on due to high input bus dV/dt
This driver also has an overvoltage protection feature, which is
operational while VCC is below the POR threshold. The PHASE
node is connected to the gate of the low-side MOSFET (LGATE)
via a 30kΩ resistor, limiting the output voltage of the converter
close to the gate threshold of the low-side MOSFET. This is
dependent on the current being shunted, which provides some
protection to the load should the upper MOSFET(s) become
shorted.
• Pre-POR overvoltage protection for start-up and shutdown
• Power rails undervoltage protection
• Expandable bottom copper pad for enhanced heat sinking
• Dual flat no-lead (DFN) package
- Near chip-scale package footprint; improves PCB
efficiency and thinner in profile
• Pb-Free (RoHS compliant)
Applications
• High light load efficiency voltage regulators
• Core regulators for advanced microprocessors
• High current DC/DC converters
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck Regulators”
VCC
BOOT
PIN 6
UGATE
10k
POR/
CONTROL
LOGIC
+5V
30.4k
32k
PHASE
SHOOT-
PWM
30k
PINS 6 AND 7 MUST BE
TIED TOGETHER
THROUGH
PROTECTION
VCC
PIN 7
LGATE
GND
FIGURE 1. BLOCK DIAGRAM
FN7978 Rev 0.00
Page 1 of 10
September 19, 2012
ISL6625A
Ordering Information
PART NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
(Notes 1, 2, 3)
ISL6625ACRZ-T
ISL6625AIRZ-T
NOTES:
5AZ
25A
0 to +70
8 Ld 2x2 DFN
8 Ld 2x2 DFN
L8.2x2D
L8.2x2D
-40 to +85
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6625A. For more information on MSL please see tech brief TB363
Pin Configuration
Functional Pin Descriptions
ISL6625A
PIN
(8 LD 2x2 DFN)
TOP VIEW
PIN # SYMBOL
FUNCTION
1
UGATE Upper gate drive output. Connect to gate of high-side
power N-Channel MOSFET.
1
8
7
PHASE
VCC
UGATE
BOOT
PWM
2
BOOT
Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin
and the PHASE pin. The bootstrap capacitor provides
the charge to turn on the upper MOSFET. See
“Internal Bootstrap Device” on page 6 for guidance in
choosing the capacitor value.
2
3
4
GND
6
5
VCC
GND
LGATE
3
4
PWM
GND
The PWM signal is the control input for the driver. The
PWM signal can enter three distinct states during
operation, see the three-state PWM Input section for
further details. Connect this pin to the PWM output of
the controller.
Bias and reference ground. All signals are referenced
to this node. It is also the power ground return of the
driver.
5
LGATE Lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
6,7
VCC
These two pins must tie to each other. Connect them
to 12V bias supply. Place a high quality low ESR
ceramic capacitor from this pin to GND.
8
-
PHASE Connect this pin to the SOURCE of the upper MOSFET
and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
PAD
Connect this pad to the power ground plane (GND) via
thermally enhanced connection.
FN7978 Rev 0.00
September 19, 2012
Page 2 of 10
ISL6625A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Thermal Resistance
2x2 DFN Package (Notes 4, 5) . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
(°C/W)
90
(°C/W)
25
JA
JC
BOOT Voltage (V
Input Voltage (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
PWM
BOOT - GND
UGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
- 0.3V to V
+ 0.3V
+ 0.3V
+ 0.3V
+ 0.3V
PHASE
- 3.5V (<100ns Pulse Width, 2µJ) to V
DC
BOOT
BOOT
V
PHASE
LGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V
DC
VCC
Recommended Operating Conditions
GND - 5V (<100ns Pulse Width, 2µJ) to V
VCC
PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 25V
Ambient Temperature Range (ISL6625AIRZ). . . . . . . . . . .-40°C to +85°C
Ambient Temperature Range (ISL6625ACRZ) . . . . . . . . . . . .0°C to +70°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V to 13.2V
DC
DC
<36V)
GND - 8V (<400ns, 20µJ) to 30V (<200ns, V
BOOT - GND
ESD Rating
Human Body Model (Tested per Class I JEDEC STD) . . . . . . . . . . . .2.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended operating conditions, unless otherwise noted.
MIN
MAX
PARAMETER
VCC SUPPLY CURRENT (Note 6)
No Load Switching Supply Current
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6) UNITS
I
I
V
V
= 12V, F = 300kHz
PWM
-
-
7.56
0.72
-
-
mA
mA
VCC
VCC
VCC
= 12V, PWM = 2.5V
VCC
POWER-ON RESET
VCC Rising Threshold
-
-
4.64
4.17
-
-
V
V
VCC Falling Threshold
PWM INPUT (See “TIMING DIAGRAM” on page 4)
Input Current
I
V
V
= 5V
= 0V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
124
-141
2.77
3.23
1.20
1.50
31
-
-
-
-
-
-
-
-
-
-
-
-
-
-
µA
µA
V
PWM
PWM
PWM
Three-State Upper Gate Rising Threshold
Three-State Upper Gate Falling Threshold
Three-State Lower Gate Rising Threshold
Three-State Lower Gate Falling Threshold
UGATE Rise Time
VCC = 12V
VCC = 12V
VCC = 12V
VCC = 12V
V
V
V
t
V
V
V
V
V
V
V
V
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 10% to 90%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, 90% to 10%
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load
ns
ns
ns
ns
ns
ns
ns
ns
RU
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
LGATE Rise Time
t
28
RL
UGATE Fall Time
t
18
FU
LGATE Fall Time
t
16
FL
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
t
16
PDHU
t
38
PDHL
t
21
PDLU
t
= 12V, 3nF Load
23
PDLL
FN7978 Rev 0.00
Page 3 of 10
September 19, 2012
ISL6625A
Electrical Specifications Recommended operating conditions, unless otherwise noted. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6) UNITS
OUTPUT
Upper Drive Source Impedance
Upper Drive Sink Impedance
Lower Drive Source Impedance
Lower Drive Sink Impedance
NOTE:
R
20mA Source Current
-
-
-
-
3.9
1.4
2.7
0.9
-
-
-
-
Ω
Ω
Ω
Ω
U_SOURCE
R
20mA Sink Current
20mA Source Current
20mA Sink Current
U_SINK
R
L_SOURCE
R
L_SINK
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
1.5V<PWM<3.2V
1.0V<PWM<2.6V
PWM
t
t
PDLU
PDHU
t
UG_OFF_DB
t
PDTS
t
PDTS
t
FU
UGATE
LGATE
t
RU
t
PDHL
t
RL
t
FL
t
t
TSSHD
PDLL
t
t
PDUFLR
PDLFUR
FIGURE 2. TIMING DIAGRAM
FN7978 Rev 0.00
September 19, 2012
Page 4 of 10
ISL6625A
Typical Application Circuit
VIN
+5V
+12V
BOOT
UGATE
VCC
ISL6625A
PHASE
GND
PWM
COMP VCC
FB
LGATE
PWM1
ISEN1-
ISEN1+
PSICOMP
HFCOMP
VIN
+12V
VSEN
BOOT
RGND
UGATE
PHASE
GND
EN_VTT
VTT
VCC
ISL6625A
SVALERT#
SVDATA
SVCLK
PWM
PWM2
ISEN2-
ISEN2+
LGATE
VR_RDY
VR_RDYS
VIN
VR_HOT#
VIN
+12V
BOOT
ISL6364A
UGATE
PHASE
GND
VCC
ISL6625A
EN_PWR_OVP
VIN
PWM
LGATE
PWM3
ISEN3-
ISEN3+
CPU
OVP
LOAD
RAMP_ADJ
IMON
VIN
+12V
BOOT
UGATE
IMONS
VCC
ISL6625A
PHASE
GND
FS_DRP
FSS_DRPS
+5V
PWM
LGATE
PWM4
ISEN4-
ISEN4+
+5V
BTS_DES_TCOMPS
VIN
+5V
+12V
BOOT
BT_FDVID_TCOMP
UGATE
+5V
ADDR_IMAXS_TMAX
VCC
ISL6625A
PHASE
GND
GND
PWM
GPU
LOAD
LGATE
PWMS
ISENS-
NPSI_DE_IMAX
+5V
ISENS+
TMS
+5V
NTC
RGNDS
VSENS
TM
NTC
AUTO
HFCOMPS/DVCS
FBS
RSET
COMPS
NTC: Beta = ~ 3477
FN7978 Rev 0.00
Page 5 of 10
September 19, 2012
ISL6625A
Power-On Reset (POR) Function
Description
Operation and Adaptive Shoot-through
Protection
Designed for high speed switching, the ISL6625A MOSFET driver
controls both high-side and low-side N-Channel FETs from one
externally provided PWM signal.
During initial start-up, the VCC voltage rise is monitored. Once the
rising VCC voltage exceeds rising POR threshold, operation of the
driver is enabled and the PWM input signal takes control of the
gate drives. If VCC drops below the POR falling threshold,
operation of the driver is disabled.
Pre-POR Overvoltage Protection
A rising transition on PWM initiates the turn-off of the lower
While VCC is below its POR level, the upper gate is held low and
LGATE is connected to the PHASE pin via an internal 30kΩ
(typically) resistor. By connecting the PHASE node to the gate of
the low side MOSFET, the driver offers some passive protection to
the load if the upper MOSFET(s) is or becomes shorted. If the
PHASE node goes higher than the gate threshold of the lower
MOSFET, it results in the progressive turn-on of the device and
the effective clamping of the PHASE node’s rise. The actual
PHASE node clamping level depends on the lower MOSFET’s
electrical characteristics, as well as the characteristics of the
input supply and the path connecting it to the respective PHASE
node.
MOSFET (see Figure 2). After a short propagation delay [t
], the
PDLL
lower gate begins to fall. Typical fall time [t ] is provided in the
FL
“Electrical Specifications” on page 3. Following a 25ns blanking
period, adaptive shoot-through circuitry monitors the LGATE
voltage and turns on the upper gate following a short delay time
[t
] after the LGATE voltage drops below ~1.75V. The upper
PDHU
gate drive then begins to rise [t ] and the upper MOSFET turns on.
RU
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short propagation
delay [t
] is encountered before the upper gate begins to fall
PDLU
[t ]. The adaptive shoot-through circuitry monitors the
FU
UGATE-PHASE voltage and turns on the lower MOSFET a short
Internal Bootstrap Device
delay time [t
] after the upper MOSFET’s PHASE voltage drops
PDHL
below +0.8V or 40ns after the upper MOSFET’s gate voltage
[UGATE-PHASE] drops below ~1.75V. The lower gate then rises
The ISL6625A features an internal bootstrap Schottky diode
equivalent circuit implemented by swichers with typical on
resistance of 40Ωand no typical diode forward voltage drop.
Simply adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit. The bootstrap function is
also designed to prevent the bootstrap capacitor from
overcharging due to the large negative swing at the trailing-edge
of the PHASE node. This reduces the voltage stress on the BOOT
to PHASE pins.
[t ], turning on the lower MOSFET. These methods prevent both
RL
the lower and upper MOSFETs from conducting simultaneously
(shoot-through), while adapting the dead time to the gate charge
characteristics of the MOSFETs being used.
This driver is optimized for voltage regulators with large step down
ratio. The lower MOSFET is usually sized larger compared to the
upper MOSFET because the lower MOSFET conducts for a longer
time during a switching period. The lower gate driver is therefore
sized much larger to meet this application requirement. The 0.8Ω
ON-resistance and 3A sink current capability enable the lower gate
driver to absorb the current injected into the lower gate through
the drain-to-gate capacitor of the lower MOSFET and help prevent
shoot-through caused by the self turn-on of the lower MOSFET due
to high dV/dt of the switching node.
The bootstrap capacitor must have a maximum voltage rating
well above the maximum voltage intended for UVCC. Its
minimum capacitance value can be estimated from Equation 1:
Q
UGATE
-------------------------------------
C
BOOT_CAP
V
BOOT_CAP
(EQ. 1)
Q
UVCC
G1
-----------------------------------
Q
=
N
Q1
Three-State PWM Input
UGATE
V
GS1
A unique feature of ISL6625A and other Intersil drivers is the
addition of a three-state shutdown window to the PWM input. If
the PWM signal enters and remains within the shutdown window
for a set holdoff time, the driver outputs are disabled and both
MOSFET gates are pulled and held low. The shutdown state is
removed when the PWM signal moves outside the shutdown
window. Otherwise, the PWM rising and falling thresholds
outlined in the “Electrical Specifications” on page 3 determine
when the lower and upper gates are enabled. This feature helps
prevent a negative transient on the output voltage when the
output is shut down, eliminating the Schottky diode that is used
in some systems for protecting the load from reversed output
voltage events.
Where Q is the amount of gate charge per upper MOSFET at
G1
V
gate-source voltage and N is the number of control
GS1
MOSFETs. The V
Q1
term is defined as the allowable
BOOT_CAP
droop in the rail of the upper gate drive. Select results are
exemplified in Figure 4.
FN7978 Rev 0.00
Page 6 of 10
September 19, 2012
ISL6625A
.
The total gate drive power losses are dissipated among the
resistive components along the transition path, as outlined in
Equation 4. The drive resistance dissipates a portion of the total
gate drive power losses, the rest will be dissipated by the external
1.6
1.4
1.2
1.0
0.8
0.6
0.4
gate resistors (R and R ) and the internal gate resistors (R
G1 G2 GI1
and R ) of MOSFETs. Figures 4 and 5 show the typical upper and
GI2
lower gate drives turn-on current paths.
P
P
= P
+ P
+ I VCC
(EQ. 4)
DR
DR_UP
DR_LOW
Q
Q
= 100nC
UGATE
R
R
P
Qg_Q1
HI1
LO1
-------------------------------------- --------------------------------------- ---------------------
=
+
DR_UP
R
+ R
R
+ R
EXT1
2
HI1
EXT1
LO1
50nC
0.2
0.0
20nC
R
R
P
Qg_Q2
HI2
LO2
-------------------------------------- --------------------------------------- ---------------------
P
R
=
+
DR_LOW
R
+ R
R
+ R
EXT2
2
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DV (V)
HI2
EXT2
LO2
BOOT_CAP
R
R
GI1
GI2
-------------
-------------
= R
+
R
= R +
G2
FIGURE 3. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
EXT1
G1
EXT2
N
N
Q1
Q2
Power Dissipation
Package power dissipation is mainly a function of the switching
VCC
BOOT
frequency (F ), the output drive impedance, the layout
SW
D
resistance, and the selected MOSFET’s internal gate resistance
C
R
and total gate charge (Q ). Calculating the power dissipation in the
GD
G
driver for a desired application is critical to ensure safe operation.
Exceeding the maximum allowable power dissipation level may
push the IC beyond the maximum recommended operating
junction temperature. The DFN package is more suitable for high
frequency applications. See “Layout Considerations” on page 8
for thermal impedance improvement suggestions. The total gate
drive power losses due to the gate charge of MOSFETs and the
driver’s internal circuitry and their corresponding average driver
current can be estimated using Equations 2 and 3, respectively:
R
HI1
G
C
DS
R
LO1
R
GI1
C
G1
GS
Q1
S
PHASE
FIGURE 4. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
(EQ. 2)
P
= P
+ P
+ I VCC
Q
Qg_TOT
Qg_Q1
Qg_Q2
2
LVCC
Q
UVCC
D
G1
---------------------------------------
P
=
=
F
N
Qg_Q1
SW
Q1
V
GS1
C
GD
2
R
Q
LVCC
HI2
G
G2
C
--------------------------------------
P
F
N
DS
Qg_Q2
SW
Q2
V
GS2
R
R
LO2
R
GI2
G2
C
GS
Q2
Q
UVCC N
Q
LVCC N
G2 Q2
G1
Q1
----------------------------------------------------- ----------------------------------------------------
I
=
+
F
+ I
Q
S
DR
SW
V
V
GS2
GS1
(EQ. 3)
FIGURE 5. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Where the gate charge (Q and Q ) is defined at a particular
G1
G2
gate to source voltage (V
and V
) in the corresponding
GS1
GS2
MOSFET datasheet; I is the driver’s total quiescent current with
Q
no load at both drive outputs; N and N are number of upper
Q1 Q2
and lower MOSFETs, respectively; UVCC and LVCC are the drive
voltages for both upper and lower FETs, respectively. The I VCC
Q*
product is the quiescent power of the driver without a load.
FN7978 Rev 0.00
Page 7 of 10
September 19, 2012
ISL6625A
Upper MOSFET Self Turn-On Effect at
Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high dV/dt
rate while the driver outputs are floating, due to self-coupling via
Application Information
Layout Considerations
During switching of the devices, the parasitic inductances of the
PCB and the power devices’ packaging (both upper and lower
MOSFETs) leads to ringing, possibly in excess of the absolute
maximum rating of the devices. Careful layout can help minimize
such unwanted stress. The following advice is meant to lead to
an optimized layout:
the internal C of the MOSFET, the gate of the upper MOSFET
GD
could momentarily rise up to a level greater than the threshold
voltage of the device, potentially turning on the upper switch.
Therefore, if such a situation could conceivably be encountered,
it is a common practice to place a resistor (R
gate and source of the upper MOSFET to suppress the Miller
coupling effect. The value of the resistor depends mainly on the
) across the
UGPH
• Keep decoupling loops (VCC-GND and BOOT-PHASE) as short
as possible.
• Minimize trace inductance, especially low-impedance lines: all
power traces (UGATE, PHASE, LGATE, GND) should be short
and wide, as much as possible.
input voltage’s rate of rise, the C /C ratio, as well as the
gate-source threshold of the upper MOSFET. A higher dV/dt, a
GD GS
lower C /C ratio, and a lower gate-source threshold upper
DS GS
FET will require a smaller resistor to diminish the effect of the
internal capacitive coupling. For most applications, the
integrated 20kΩ resistor is sufficient, not affecting normal
performance and efficiency.
• Minimize the inductance of the PHASE node: ideally, the
source of the upper and the drain of the lower MOSFET should
be as close as thermally allowable.
• Minimize the input current loop: connect the source of the
lower MOSFET to ground as close to the transistor pin as
feasible; input capacitors (especially ceramic decoupling)
should be placed as close to the drain of upper and source of
lower MOSFETs as possible.
–V
DS
---------------------------------
dV
-------
R C
dV
dt
iss
dt
-------
V
=
R C
1 – e
(EQ. 5)
GS_MILLER
rss
In addition, for improved heat dissipation, place copper
C
= C
+ C
GD GS
C
= C
R = R
+ R
GI
iss
rss
GD
UGPH
underneath the IC whether it has an exposed pad or not. The
copper area can be extended beyond the bottom area of the IC
and/or connected to buried power ground plane(s) with thermal
vias. This combination of vias for vertical heat escape, extended
surface copper islands, and buried planes combine to allow the
IC and the power switches to achieve their full thermal potential.
The coupling effect can be roughly estimated with Equation 5,
which assumes a fixed linear input ramp and neglects the
clamping effect of the body diode of the upper drive and the
bootstrap capacitor. Other parasitic components such as lead
inductances and PCB capacitances are also not taken into
account. Figure 6 provides a visual reference for this
phenomenon and its potential solution.
VCC
VIN
BOOT
C
BOOT
G
D
C
G
GD
UGATE
C
DS
R
C
GS
Q
S
UPPER
10k
PHASE
FIGURE 6. GATE TO SOURCE RESISTOR TO REDUCE UPPER
MOSFET MILLER COUPLING
FN7978 Rev 0.00
Page 8 of 10
September 19, 2012
ISL6625A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN7978.0
CHANGE
September 19, 2012
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: ISL6625A
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
© Copyright Intersil Americas LLC 2012. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7978 Rev 0.00
Page 9 of 10
September 19, 2012
ISL6625A
Package Outline Drawing
L8.2x2D
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH EXPOSED PAD
Rev 0, 3/11
2.00
6
A
PIN #1
6
B
INDEX AREA
PIN 1
INDEX AREA
8
1
6x 0.50
1.55±0.10
(4X)
0.15
0.22
0.10M C AB
( 8x0.30 )
4
TOP VIEW
0.90±0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0 . 2 REF
0.10
C
C
0.90±0.10
BASE PLANE
0 . 00 MIN.
0 . 05 MAX.
SEATING PLANE
0.08
C
SIDE VIEW
DETAIL "X"
( 8x0.20 )
( 8x0.30 )
PACKAGE
OUTLINE
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
( 6x0.50 )
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
1.55
2.00
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
( 8x0.22 )
5.
6.
0.90
2.00
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
TYPICAL RECOMMENDED LAND PATTERN
FN7978 Rev 0.00
Page 10 of 10
September 19, 2012
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