ISL6721AAVZ-T13 [RENESAS]
Switching Controller;
| 型号： | ISL6721AAVZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Switching Controller 开关 |
| 文件： | 总24页 (文件大小：669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6721A
Data Sheet
August 23, 2011
FN6797.0
Flexible Single-ended Current Mode PWM
Controller
Features
• 1A MOSFET Gate Driver
• 100µA Startup Current
The ISL6721A is a low power, single-ended pulse width
modulating (PWM) current mode controller designed for a
wide range of DC/DC conversion applications including
boost, flyback, and isolated output configurations. Peak
current mode control effectively handles power transients
and provides inherent overcurrent protection. Other features
include a low power mode where the supply current drops to
less than 200µA during overvoltage and overcurrent
shutdown faults. It differs from the ISL6721 in that the UVLO
and UV thresholds have been modified.
• Fast Transient Response with Peak Current Mode Control
• Adjustable Switching Frequency up to 1MHz
• Bidirectional Synchronization
• Low Power Disable Mode
• Delayed Restart from OV and OC Shutdown Faults
• Adjustable Slope Compensation
• Adjustable Soft-start
This advanced BiCMOS design features low operating
current, adjustable operating frequency up to 1MHz,
adjustable soft-start, and a bidirectional SYNC signal that
allows the oscillator to be locked to an external clock for
noise sensitive applications.
• Adjustable Overcurrent Shutdown Delay
• Adjustable UV and OV Monitors
• Leading Edge Blanking
• Integrated Thermal Shutdown
Applications
• 1% Tolerance Voltage Reference
• Pb-Free (RoHS Compliant)
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
• Isolated Buck and Flyback Regulators
• Boost Regulators
Pinouts
ISL6721A
(16 LD TSSOP)
TOP VIEW
ISL6721A
(16 LD QFN)
TOP VIEW
GATE
ISENSE
SYNC
SLOPE
UV
1
2
3
4
5
6
7
8
16 VC
15 PGND
14 VCC
13 VREF
12 LGND
11 SS
16
15
14
13
SYNC
SLOPE
UV
1
2
3
4
12 VCC
11 VREF
OV
10
9
LGND
SS
RTCT
ISET
10 COMP
9 FB
OV
5
6
7
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2003-2005, 2007, 2008, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
1
All other trademarks mentioned are the property of their respective owners.
ISL6721A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP RANGE (°C)
-40 to +105
PACKAGE
16 Ld QFN
16 Ld TSSOP
PKG. DWG. #
L16.3x3B
M16.173
ISL6721AARZ
ISL6721AAVZ
NOTES:
21AZ
6721A AVZ
-40 to +105
1. *Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6721A. For more information on MSL please see
Tech Brief TB363.
FN6797.0
August 23, 2011
2
ISL6721A
Functional Block Diagram
VREF
5.00 V
1 %
VCC
VREF
START/STOP
UV COMPARATOR
SOFT-START
CHARGE
CURRENT
70µA
ON
+
-
ENABLE
+
BG
-
SS CHARGE
VOLTAGE CLAMP
SS
15µA
LGND
THERMAL
PROTECTION
25µA
ON
OC
FAULT
SS CHARGED
+
-
RESTART
DELAY
4.375V
OC
ISET
SS DCHG
0.8
ISENSE
OVERCURRENT
SHUTDOWN
DELAY
5k
-
OC DETECT
+
+
VREF
Σ
+
SHTDN
SS CHG
53µA
0.1
OVERCURRENT
COMPARATOR
100mV
SLOPE
-
SS LOW
+
270mV
SS LOW
COMPARATOR
FAULT
LATCH
SS
SS CLAMP
S
Q
+
-
COMP
R
Q
PWM
VREF
SET DOMINANT
COMPARATOR
ERROR
AMPLIFIE
R
+
-
VREF
UV COMPARATOR
2.5V
+
4.65V
-
-
VFB
+
START
BG
1/3
100nS
BLANKING
OV
UV
+
-
VREF
2.50V
-
20K
30K
3.0V
1.5V
+
12k
BLANKING
COMPARATOR
1.93V
3.0V
ON
-
+
OSCILLATOR
COMPARATOR
VC
S
R
Q
Q
-
Bi-Directional
Synchronization
RTCT
+
1mA
ON
GATE
OSC IN
VREF
36k
CLK OUT
+
-
NO EXT SYNC
4V
2V
-
EXT SYNC BLANKING
+
PGND
SYNC IN
VREF
SYNC OUT
100
SYNC
4.5k
FN6797.0
August 23, 2011
3
ISL6721A
Typical Application - 48V Input Dual
Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A
SP1
SP2
CR5
T1
+3.3V
+1.8V
ISOLATION
XFMR
C21
+
C15
+ C16
R21
VIN+ P9
C18
R24
CR4
+
C22
C19
+
C20
C17
C2
CR2
C5
RETURN
CR6
R1
R16
R17
36-75V
R18
C6
R19
C1
C3
TP1
U2
Q1
C14
R2
R4
R3
R15
R22
C13
R23
C4
U3
VIN-
R20
TP2
R25
U4
Q2
VC
PGND
VCC
GATE
D1
TP3
ISENSE
SYNC
SYNC
R14
VREF
SLOPE
LGND
UV
OV
R5
SS
COMP
VFB
TP4
R26
R6
TP5
RTCT
ISET
D2
R27
Q3
C12
R8
C11
R10
C7
C8
C9
VR1
R12
R7
R13
R11
R9
C10
FN6797.0
August 23, 2011
4
ISL6721A
Typical Boost Converter Application
Schematic
CR1
R12
L1
+VOUT
VIN+
+
C2
C3
C12
RETURN
Q1
R8
R1
R2
R3
R4
C11
C1
VIN+
R10
C4
U1
C10
GATE
VC
PGND
VCC
ISENSE
SYNC
SLOPE VREF
UV
OV
LGND
SS
RTCT COMP
R9
ISET
VFB
R5
R11
C8
C5
C6
C7
R6
C9
R7
VIN-
FN6797.0
August 23, 2011
5
ISL6721A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
V
. . . . . . . . . . . . . . . . .GND -0.3V to +20.0V
Thermal Resistance (Typical)
θ
(°C/W)
θ (°C/W)
JC
CC,
C
JA
GATE . . . . . . . . . . . . . . . . GND - 0.3V to Gate Output Limit Voltage
PGND to LGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.3V
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
16 Ld QFN (Notes 5, 6) . . . . . . . . . . . .
16 Ld TSSOP (Notes 7, 8) . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
44
105
4
33
Operating Conditions
Temperature Range
ISL6721Axx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical, Note 4) . . . . . . . . 9VDC to 18VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. All voltages are with respect to GND.
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
8. For θ , the “case temp” location is taken at the package top center.
JC
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic on page 3 and page 4. 9V < V
= V < 20V, RT = 11kΩ, CT = 330 pF. Typical values are at
C
CC
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C.
T
A
MIN
(Note 9)
MAX
(Note 9)
PARAMETER
UNDERVOLTAGE LOCKOUT
START Threshold
TEST CONDITIONS
TYP
UNITS
6.40
6.80
6.20
0.60
100
200
4.5
6.90
6.30
1.00
175
V
V
STOP Threshold
5.85
Hysteresis
0.50
V
Start-Up Current, I
CC
V
< START Threshold
-
-
-
-
µA
µA
mA
mA
CC
OC/OV Fault Operating Current, I
300
CC
Operating Current, I
(Note 11)
10.0
12.0
CC
Operating Supply Current, I
REFERENCE VOLTAGE
Overall Accuracy
Includes 1nF GATE loading
8.0
C
Line, load, 0°C to +105°C
Line, load, -40°C to +105°C
4.95
4.90
-
5.00
5.00
5
5.05
5.05
-
V
V
Long Term Stability
Fault Voltage
T = +125°C, 1000 hours (Note 10)
mV
V
A
4.50
4.65
75
4.65
4.80
165
-
4.75
4.95
250
-
VREF Good Voltage
Hysteresis
V
mV
mA
mA
Operational Current
Current Limit
-10
-20
-
-
CURRENT SENSE
Input Impedance
Offset Voltage
-
0.08
0
5
0.10
-
-
kΩ
V
0.11
1.5
Input Voltage Range
V
FN6797.0
August 23, 2011
6
ISL6721A
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic on page 3 and page 4. 9V < V
= V < 20V, RT = 11kΩ, CT = 330 pF. Typical values are at
C
CC
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
T
A
MIN
(Note 9)
MAX
(Note 9)
PARAMETER
TEST CONDITIONS
(Note 10)
TYP
60
UNITS
ns
Blanking Time
Gain, A
30
100
V
V
A
= 0V, V = 2.3V,
FB
0.77
0.79
0.81
V/V
CS
SLOPE
= 0.35V, 1.5V
ISET
= ΔISET/ΔISENSE
CS
ERROR AMPLIFIER
Open Loop Voltage Gain
Gain-Bandwidth Product
Reference Voltage Initial Accuracy
(Note 10)
(Note 10)
60
-
90
15
-
-
dB
MHz
V
V
= COMP, T = +25°C
2.465
2.515
2.565
FB
(Note 10)
A
Reference Voltage
V
= COMP
2.44
0.31
0.51
-2
2.515
0.33
0.75
0.1
2.590
0.35
0.88
2
V
V/V
V
FB
COMP to PWM Gain, A
COMP to PWM Offset
FB Input Bias Current
COMP Sink Current
COMP Source Current
COMP VOH
COMP = 4V, T = +25°C
A
COMP
COMP = 4V (Note 10)
V
= 0V
µA
mA
mA
V
FB
COMP = 1.5V, V = 2.7V
2
6
-
FB
COMP = 1.5V, V = 2.3V
-0.25
4.25
0.4
-0.5
4.4
-
FB
V
V
= 2.3V
= 2.7V
5.0
1.2
-
FB
FB
COMP VOL
0.8
V
PSRR
Frequency = 120Hz (Note 10)
SS = 2.5V, V = 0V, ISET = 2V
60
80
dB
V
SS Clamp, V
2.4
2.5
2.6
COMP
FB
OSCILLATOR
Frequency Accuracy
289
318
347
kHz
%
Frequency Variation with V
T = +105°C (f
- f )/f
20V 9V 9V
-f )/f
-
2
2
3
3
CC
T = -40°C (f
(Note 10)
(Note 12)
20V 9V 9V
Temperature Stability
Maximum Duty Cycle
-
68
-
8
-
81
-
%
%
V
75
Comparator High Threshold - Free Running
Comparator High Threshold - with External SYNC
Comparator Low Threshold
3.00
4.00
1.50
(Note 10)
-
-
V
-
-
V
Discharge Current
0°C to +105°C
-40°C to +105°C
0.75
0.70
1.0
1.0
1.2
1.2
mA
SYNCHRONIZATION
Input High Threshold
Input Pulse Width
-
-
-
-
2.5
-
V
ns
25
Input Frequency Range
(Note 10)
0.65 x Free
Running
(Period)
1.0
MHz
Input Impedance
VOH
-
2.5
-
4.5
-
-
-
kΩ
V
R
R
= 4.5kΩ
LOAD
VOL
= open
-
0.1
55
V
LOAD
SYNC Advance
SYNC rising edge to GATE falling
edge, C = C = 100pF
-
25
ns
GATE
SYNC
FN6797.0
August 23, 2011
7
ISL6721A
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic on page 3 and page 4. 9V < V
= V < 20V, RT = 11kΩ, CT = 330 pF. Typical values are at
C
CC
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
T
A
MIN
(Note 9)
MAX
(Note 9)
PARAMETER
TEST CONDITIONS
TYP
UNITS
Output Pulse Width
SOFT-START
C
= 100pF
50
-
-
ns
SYNC
Charging Current
SS = 2V
-40
4.26
30
-55
4.50
40
-70
4.74
55
µA
V
Charged Threshold Voltage
Initial Overcurrent Discharge Current
Sustained OC Threshold < SS <
Charged Threshold
µA
Overcurrent Shutdown Threshold Voltage
Charged Threshold minus,
0.095
0.125
0.155
V
T
= +25°C
A
Fault Discharge Current
Reset Threshold Voltage
SLOPE COMPENSATION
Charge Current
SS = 2V
= +25°C
0.25
1.0
-
mA
V
T
0.22
0.27
0.31
A
SLOPE = 2V, 0°C to +105°C
-40°C to +105°C
-45
-41
-53
-53
-65
-65
µA
V/V
V/V
V
Slope Compensation Gain
Fraction of slope voltage added to
0.097
0.082
-
-
0.103
0.118
0.2
I
, T = +25°C
SENSE
A
Fraction of slope voltage added to
-
I
SENSE
Discharge Voltage
GATE OUTPUT
V
= 4.5V
0.1
RTCT
Gate Output Limit Voltage
V
= 20V, C
= 0mA
= 1nF,
GATE
11.0
13.5
1.5
16.0
2.2
V
V
V
C
I
OUT
Gate VOH
Gate VOL
V
- GATE, V = 10V,
= 150mA
-
-
C
C
I
OUT
GATE - PGND, IOUT = 150mA
IOUT = 10mA
1.2
0.6
1.5
0.8
Peak Output Current
Output “Faulted” Leakage
Rise Time
V
V
V
= 20V, C
= 1nF (Note 10)
-
1.2
-
1.0
2.6
60
-
-
A
C
C
C
GATE
= 20V, UV = 0V, GATE = 2V
mA
ns
= 20V, C
= 1nF
= 1nF
100
GATE
1V < GATE < 9V
Fall Time
V
= 20V, C
-
-
15
-
40
ns
ns
C
GATE
1V < GATE < 9V
Minimum ON time
ISET = 0.5V; V = 0V; VC = 11V
FB
110
ISENSE to GATE w/10:1 Divider
RTCT = 4.75V through 1kΩ
(Note 10)
OVERCURRENT PROTECTION
Minimum ISET Voltage
Maximum ISET Voltage
ISET Bias Current
-
-
0.35
-
V
V
1.2
-1.0
150
-
-
V
= 1.00V
1.0
445
µA
ms
ISET
Restart Delay
T
= +25°C
295
A
OV AND UV VOLTAGE MONITOR
Overvoltage Threshold
Undervoltage Fault Threshold
2.4
2.5
2.6
V
V
1.89
1.93
2.00
FN6797.0
August 23, 2011
8
ISL6721A
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic on page 3 and page 4. 9V < V
= V < 20V, RT = 11kΩ, CT = 330 pF. Typical values are at
C
CC
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
T
A
MIN
(Note 9)
MAX
(Note 9)
PARAMETER
Undervoltage Clear Threshold
TEST CONDITIONS
TYP
2.01
50
-
UNITS
V
1.96
20
2.10
100
1.0
Undervoltage Hysteresis Voltage
UV Bias Current
mV
µA
V
V
= 2.10 V
-1.0
-1.0
UV
OV
OV Bias Current
= 2.00 V
-
1.0
µA
THERMAL PROTECTION
Thermal Shutdown
Thermal Shutdown Clear
Hysteresis
(Note 10)
(Note 10)
(Note 10)
120
105
-
130
120
10
140
135
-
°C
°C
°C
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at 25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. This parameter, although guaranteed by characterization or correlation testing, is not 100% tested in production.
11. This is the V
CC
current consumed when the device is active but not switching. Does not include gate drive current.
12. This is the maximum duty cycle achievable using the specified values of RT and CT. Larger or smaller maximum duty cycles may be obtained
using other values for RT and CT. See Equations 1, 2, 3 and 4.
Typical Performance Curves
1.002
1.002
1.000
1.000
0.998
0.998
0.995
0.995
0.993
0.993
0.991
0.991
-40
-10
20
50
80
110
-40
-10
20
50
80
110
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 1. EA REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. VREF REFERENCE VOLTAGE vs TEMPERATURE
3
1.002
0.996
0.989
0.983
0.976
0.970
10
100pF
100
220pF
330pF
470pF
680pF
1000pF
10
10 20 30 40 50 60 70 80 90 100
2000pF
-40
-10
20
50
80
110
RT (kΩ)
TEMPERATURE (°C)
FIGURE 3. OSCILLATOR FREQUENCY vs TEMPERATURE
FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN
FN6797.0
August 23, 2011
9
ISL6721A
UV - Undervoltage monitor input pin. This signal is
compared to an internal 1.45V reference to detect an
undervoltage condition.
Pin Descriptions
SLOPE - Means by which the ISENSE ramp slope may be
increased for improved noise immunity or improved control
loop stability for duty cycles greater than 50%. An internal
current source charges an external capacitor to GND during
each switching cycle. The resulting ramp is scaled and
added to the ISENSE signal.
ISENSE - This is the input to the current sense comparators.
The IC has two current sensing comparators, a PWM
comparator for peak current mode control, and an
overcurrent protection comparator. The overcurrent
comparator threshold is adjustable through the ISET pin.
SYNC - A bidirectional synchronization signal used to
coordinate the switching frequency of multiple units.
Synchronization may be achieved by connecting the SYNC
signal of each unit together or by using an external master
clock signal. The oscillator timing capacitor, C , is still
required, even if an external clock is used. The first unit to
assert this signal assumes control.
Exceeding the overcurrent threshold will start a delayed
shutdown sequence. Once an overcurrent condition is
detected, the soft-start charge current source is disabled and
a discharge current source is enabled. The soft-start capacitor
begins discharging, and if it discharges to less than 4.375V
(sustained overcurrent threshold), a shutdown condition
occurs and the GATE output is forced low. At this point a
reduced discharge current takes over until the soft-start
voltage reaches 0.27V (reset threshold). The GATE output
remains low until the reset threshold is attained. At this point,
a soft-start cycle begins.
T
RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
connecting a resistor, R , between V
and this pin and a
T
REF
timing capacitor, C , from this pin to LGND. The oscillator
T
produces a sawtooth waveform with a programmable
frequency range of 100kHz to 1.0MHz. The charge time, t ,
If the overcurrent condition ceases, and then an additional
50µs period elapses before the shutdown threshold is
reached, no shutdown occurs and the soft-start voltage is
allowed to recharge.
C
the discharge time, t , the switching frequency, f , and the
D
sw
maximum duty cycle, Dmax, can be calculated from
Equations 1, 2, 3 and 4:
(EQ. 1)
t
≈ 0.655 • R • C
S
C
T
T
LGND - LGND is a small signal reference ground for all
analog functions on this device.
0.001 • R – 3.6
⎛
⎝
⎞
⎠
T
------------------------------------------
(EQ. 2)
(EQ. 3)
(EQ. 4)
t
f
≈ –R • C • LN
S
PGND - This pin provides a dedicated ground for the output
gate driver. The LGND and PGND pins should be connected
externally using a short printed circuit board trace close to
the IC. This is imperative to prevent large, high frequency
switching currents flowing through the ground metallization
D
T
T
0.001 • R – 1.9
T
1
+ t
C
-----------------
D
=
Hz
sw
t
Dmax = t • f
inside the IC. (Decouple V to PGND with a low ESR 0.1µF
C
sw
C
or larger capacitor.)
Figure 4 may be used as a guideline in selecting the
GATE - This is the device output. It is a high current power
driver capable of driving the gate of a power MOSFET with
peak currents of 1.0A. This GATE output is actively held low
capacitor and resistor values required for a given frequency.
COMP - COMP is the output of the error amplifier and the
input of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
when V
CC
is below the UVLO threshold.
The output high voltage is clamped to ~13.5V. Voltages
exceeding this clamp value should not be applied to the
GATE pin. The output stage provides very low impedance to
overshoot and undershoot.
The ISL6721A features a built-in full cycle soft-start.
Soft-start is implemented as a clamp on the maximum
COMP voltage.
V
- This pin is for separate collector supply to the output
C
FB - Feedback voltage input connected to the inverting input
of the error amplifier. The non-inverting input of the error
amplifier is internally tied to a reference voltage. Current
sense leading edge blanking is disabled when the FB input
is less than 2.0V.
gate drive. Separate V and PGND helps decouple the IC’s
analog circuitry from the high power gate drive noise.
C
(Decouple V to PGND with a low ESR 0.1µF or larger
C
capacitor.)
V
- V is the power connection for the device. Although
CC
CC
OV - Overvoltage monitor input pin. This signal is compared
to an internal 2.5V reference to detect an overvoltage
condition.
quiescent current, I , is low, it is dependent on the
CC
frequency of operation. To optimize noise immunity, bypass
V
to LGND with a ceramic capacitor as close to the V
CC
CC
and LGND pins as possible.
FN6797.0
August 23, 2011
10
ISL6721A
The total supply current (I plus I ) will be higher,
CC
SYNC assumes control of the SYNC signal. An external
C
depending on the load applied to GATE. Total current is the
sum of the quiescent current and the average gate current.
SYNC pulse is ignored if it occurs during the first 1/3 of the
switching cycle.
Knowing the operating frequency, f , and the MOSFET
sw
gate charge, Qg, the average GATE output current can be
calculated in Equation 5:
During normal operation the RTCT voltage charges from
1.5V to 3.0V and back during each cycle. Clock and SYNC
signals are generated when the 3.0V threshold is reached. If
an external clock signal is detected during the latter 2/3 of
the charging cycle, the oscillator switches to external
synchronization mode and relies upon the external SYNC
signal to terminate the oscillator cycle. The generation of a
SYNC signal is inhibited in this mode. If the RTCT voltage
exceeds 4.0V (i.e. no external SYNC signal terminates the
cycle), the oscillator reverts to the internal clock mode and a
SYNC signal is generated.
Igate = Qg • f
A
(EQ. 5)
sw
VREF - The 5V reference voltage output. Bypass to LGND
with a 0.01µF or larger capacitor to filter this output as
needed. Using capacitance less than this value may result in
unstable operation.
SS - Connect the soft-start capacitor between this pin and
LGND to control the duration of soft-start. The value of the
capacitor determines both the rate of increase of the duty
cycle during start-up, and also controls the overcurrent
shutdown delay.
Soft-Start Operation
The ISL6721A features soft-start using an external capacitor
in conjunction with an internal current source. Soft-start is
used to reduce voltage stresses and surge currents during
start up.
ISET - A DC voltage between 0.35V and 1.2V applied to this
input sets the pulse-by-pulse overcurrent threshold. When
overcurrent inception occurs, the SS capacitor begins to
discharge and starts the overcurrent delayed shutdown
cycle.
Upon start up, the soft-start circuitry clamps the error amplifier
output (COMP pin) to a value proportional to the soft-start
voltage. The error amplifier output rises as the soft-start
capacitor voltage rises. This has the effect of increasing the
output pulse width from zero to the steady state operating duty
cycle during the soft-start period. When the soft-start voltage
exceeds the error amplifier voltage, soft-start is completed.
Soft-start forces a controlled output voltage rise. Soft-start
occurs during start-up and after recovery from a fault condition
or overcurrent shutdown. The soft-start voltage is clamped to
4.5V.
Thermal Pad (QFN Package Only) - The thermal pad
located on the bottom of the QFN package is electrically
isolated. It is recommended that it be connected to signal
ground.
Functional Description
Features
The ISL6721A current mode PWMs make an ideal choice for
low-cost flyback and forward topology applications requiring
enhanced control and supervisory capability. With adjustable
overvoltage and undervoltage thresholds, overcurrent
threshold, and hic-cup delay, a highly flexible design with
minimal external components is possible. Other features
include peak current mode control, adjustable soft-start,
slope compensation, adjustable oscillator frequency and a
bi-directional synchronization clock input.
Gate Drive
The ISL6721A is capable of sourcing and sinking 1A peak
current. Separate collector supply (V ) and power ground
C
(PGnd) pins help isolate the IC’s analog circuitry from the
high power gate drive noise. To limit the peak current
through the IC, an external resistor may be placed between
the totem-pole output of the IC (GATE pin) and the gate of
the MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance.
Oscillator
The ISL6721A have a sawtooth oscillator with a
programmable frequency range to 1MHz, which can be
programmed with a resistor and capacitor on the RTCT pin.
(Please refer to Figure 4 for the resistance and capacitance
required for a given frequency.)
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability. Slope compensation is a technique in
which the current feedback signal is modified by adding
additional slope to it. The minimum amount of slope
compensation required corresponds to 1/2 the inductor
Implementing Synchronization
The oscillator can be synchronized to an external clock
applied at the SYNC pin or by connecting the SYNC pins of
multiple ICs together. If an external master clock signal is
used, it must be at least 65% of the free running frequency of
the oscillator for proper synchronization. The external
master clock signal should have a pulse width greater than
20ns. If no master clock is used, the first device to assert
FN6797.0
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ISL6721A
downslope. However, adding excessive slope compensation
results in a control loop that behaves more as a voltage
mode controller than as current mode controller (Figure 5).
Otherwise another shutdown cycle occurs. A UV condition
also results in a shutdown fault, but the device does not
enter the low power mode and no restart delay occurs when
the fault clears.
DOWNSLOPE
CURRENT SENSE SIGNAL
A resistor divider between V and LGND to each input
IN
determines the operational thresholds. The UV threshold
has a fixed hysteresis of 75mV nominal.
Overcurrent Operation
The overcurrent threshold level is set by the voltage applied
at the ISET pin. Setting the overcurrent level may be
accomplished by using a resistor divider network from VREF
to LGND. The ISET threshold should be set at a level that
corresponds to the desired peak output inductor current plus
the additive effects of slope compensation.
TIME
FIGURE 5. SLOPE COMPENSATION
The minimum amount of capacitance to place at the SLOPE
pin is calculated in Equation 6:
t
–6
Overcurrent delayed shutdown is enabled once the soft-start
cycle is complete. If an overcurrent condition is detected, the
soft-start charging current source is disabled and the
discharging current source is enabled. The soft-start
capacitor is discharged at a rate of 40µA. At the same time,
a 50µs retriggerable one-shot timer is activated and it
remains active for 50µs after the overcurrent condition stops.
The soft-start discharge cycle cannot be reset until the one-
shot timer becomes inactive. If the soft-start capacitor
discharges by more than 0.125V to 4.375V, the output is
disabled and the soft-start capacitor is discharged. The
ON
(EQ. 6)
----------------------
C
= 4.24×10
•
F
SLOPE
V
SLOPE
where t
is the On time and V
voltage to be added as slope compensation to the current
feedback signal. In general, the amount of slope
is the amount of
ON
SLOPE
compensation added is 2 to 3 times the minimum required.
Example:
Assume the inductor current signal presented at the ISENSE
pin decreases 125mV during the Off period, and:
output remains disabled and I
drops to 200µA for
CC
Switching Frequency, f = 250kHz
sw
approximately 295ms. A new soft-start cycle is then initiated.
The shutdown and restart behavior of the OC protection is
often referred to as hic-cup operation due to its repetitive
start-up and shutdown characteristic.
Duty Cycle, D = 60%
t
t
= D/f = 0.6/250E3 = 2.4µs
sw
ON
= (1 - D)/fsw = 1.6µs
OFF
If the overcurrent condition ceases at least 50µs prior to the
soft-start voltage reaching 4.375V, the soft-start charging
and discharging currents revert to normal operation and the
soft-start voltage is allowed to recover.
Determine the downslope:
Downslope = 0.125V/1.6µs = 78mV/µs. Now determine the
amount of voltage that must be added to the current sense
signal by the end of the On time (Equation 7).
1
Hiccup OC protection may be defeated by setting ISET to a
voltage that exceeds the Error Amplifier current control
voltage, or about 1.5V.
--
V
=
• 0.078 • 2.4 = 94mV
(EQ. 7)
SLOPE
2
Leading Edge Blanking
Therefore (Equation 8),
The initial 100ns of the current feedback signal input at
ISENSE is removed by the leading edge blanking circuitry.
The blanking period begins when the GATE output leading
edge exceeds 3.0V. Leading edge blanking prevents current
spikes from parasitic elements in the power supply from
causing false trips of the PWM comparator and the
overcurrent comparator.
–6
–6
2.4×10
-----------------------
≈ 110pF
(EQ. 8)
C
= 4.24×10
•
SLOPE(MIN)
0.094
An appropriate slope compensation capacitance for this
example would be 1/2 to 1/3 the calculated value, or
between 68pF and 33pF.
Overvoltage and Undervoltage Monitor
Fault Conditions
The OV and UV signals are inputs to a window comparator
used to monitor the input voltage level to the converter. If the
voltage falls outside of the user designated operating range,
a shutdown fault occurs. For OV faults, the supply current,
, is reduced to 200µA for ~295ms at which time recovery
is attempted. If the fault is cleared, a soft-start cycle begins.
A Fault condition occurs if VREF falls below 4.65V, the OV
input exceeds 2.50V, the UV input falls below 1.45V, or the
junction temperature of the die exceeds ~+130°C. When a
Fault is detected the GATE output is disabled, and the
soft-start capacitor is quickly discharged. When the Fault
I
CC
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12
ISL6721A
condition clears and the soft-start voltage is below the reset
threshold, a soft-start cycle begins.
V
V
P
: 1.8V @ 1.0A
OUT(2)
: 12V @ 50mA
OUT(BIAS)
Ground Plane Requirements
: 10W
OUT
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. Power ground
(PGND) can be separated from the logic ground (LGND) and
Efficiency: 70%
Maximum Duty Cycle, D
: 0.45
MAX
Transformer Design
connected at a single point. V should be bypassed directly
The design of a flyback transformer is a non-trivial affair. It is
an iterative process which requires a great deal of
experience to achieve the desired result. It is a process of
many compromises, and even experienced designers will
produce different designs when presented with identical
requirements. The iterative design process is not presented
here for clarity.
C
to PGND with good high frequency capacitors. The return
connection for input power and the bulk input capacitor
should be connected to the PGND ground plane.
Reference Design
The Typical Application Schematic on page 4 features the
ISL6721A in a conventional dual output 10W discontinuous
mode flyback DC/DC converter. The ISL6721EVAL1
demonstration unit implements this design and is available
for evaluation.
The abbreviated design process follows:
• Select a core geometry suitable for the application.
Constraints of height, footprint, mounting preference, and
operating environment will affect the choice.
The input voltage range is from 36VDC to 75VDC, and the
two outputs are 3.3V @ 2.5A and 1.8V @ 1.0A. Cross
regulation is achieved using the weighted sum of the two
outputs.
• Select suitable core material(s).
• Select maximum flux density desired for operation.
• Select core size. Core size will be dictated by the
capability of the core structure to store the required
energy, the number of turns that have to be wound, and
the wire gauge needed. Often the window area (the space
used for the windings) and power loss determine the final
core size. For flyback transformers, the ability to store
energy is the critical factor in determining the core size.
The cross sectional area of the core and the length of the
air gap in the magnetic path determine the energy storage
capability.
Circuit Element Descriptions
The converter design may be broken down into the following
functional blocks:
Input Storage and Filtering Capacitance: C , C , C
3
1
2
Isolation Transformer: T1
Primary voltage Clamp: C , R , C
R6 24 18
Start Bias Regulator: R , R , R , Q , V
R1
1
2
6
3
• Determine maximum desired flux density. Depending on
the frequency of operation, the core material selected, and
the operating environment, the allowed flux density must
be determined. The decision of what flux density to allow
is often difficult to determine initially. Usually the highest
flux density that produces an acceptable design is used,
but often the winding geometry dictates a larger core than
is required based on flux density and energy storage
calculations.
Operating Bias and Regulator: R , Q , D , C , C , D
25 R2
2
1
5
2
Main MOSFET Power Switch: Q
1
Current Sense Network: R , R , R , C
23 4
4
3
Feedback Network:, R , R , R , R , R , R , R
13 15 16 17 18 19 20
,
R
, R , C , C , U , U
26 27 13 14
2
3
Control Circuit:C , C , C , C , C , C , R , R , R , R ,
10 11 12
7
8
9
5
6
8
9
• Determine the number of primary turns.
• Determine the turns ratio.
R
, R , R , R , R
10 11 12 14 22
Output Rectification and Filtering: C , C , C , C , C
,
R4 R5 15 16 19
• Select the wire gauge for each winding.
• Determine winding order and insulation requirements.
• Verify the design.
C
, C , C
20 21 22
Secondary Snubber: R , C
21 17
Design Criteria
Input Power:
The following design requirements were selected:
P
/Efficiency = 14.3W (use 15W)
Switching Frequency, f : 200kHz
sw
OUT
Max ON time: t
ON(MAX)
= D
/f = 2.25µs
V
: 36V to 75V
MAX sw
IN
Average Input Current: I
= P /V = 0.42A
IN IN(MIN)
V : 3.3V @ 2.5A
OUT(1)
AVG(IN)
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August 23, 2011
13
ISL6721A
-3
Peak Primary Current (Equation 9):
lg = 1.56 • 10
m
2 • I
The flux density ΔB is only 0.069T or 690 gauss, a relatively
low value.
AVG(IN)
----------------------------------------
(EQ. 9)
I
=
= 1.87
A
PPK
f
• t
sw ON(MAX)
Since (Equation 13):
Maximum Primary Inductance (Equation 10):
2
V
• t
IN(MIN) ON(MAX)
μ
• N • Aeff
o
p
(EQ. 13)
---------------------------------------------------------
Lp(max) =
= 43.3
μH
(EQ. 10)
----------------------------------------
L
=
μH
I
p
PPK
lg
the number of primary turns, N , may be calculated. The
Choose desired primary inductance to be 40µH.
p
result is N = 40 turns. The secondary turns may be
calculated as follows (Equation 14):
p
The core structure must be able to deliver a certain amount
of energy to the secondary on each switching cycle in order
to maintain the specified output power (Equation 11).
Ig • 〈 Vout + Vd〉 • tr
(EQ. 14)
-------------------------------------------------------
N ≤
s
N
• Ippk • μ • Aeff
p
o
〈 V
+ Vd〉
OUT
-----------------------------------
Δw = P
•
joules
OUT
(EQ. 11)
f
• V
OUT
where tr is the time required to reset the core. Since
sw
discontinuous MMF mode operation is desired, the core
must completely reset during the off time. To maintain
discontinuous mode operation, the maximum time allowed to
where Δw is the amount of energy required to be transferred
each cycle and Vd is the drop across the output rectifier.
reset the core is t - t
where t = 1/f . The
sw ON(MAX)
sw sw
The capacity of a gapped ferrite core structure to store
energy is dependent on the volume of the airgap and can be
expressed in Equation 12:
minimum time is application dependent and at the designers
discretion knowing that the secondary winding RMS current
and ripple current stress in the output capacitors increases
(EQ. 12)
2 • μ • Δw
o
with decreasing reset time. The calculation for maximum N
3
s
-----------------------------
Vg = Aeff • lg =
m
2
for the 3.3 V output using t = t - t
sw ON (MAX)
= 2.75µs is 5.52
ΔB
turns.
where Aeff is the effective cross sectional area of the core in
2
The determination of the number of secondary turns is also
dependent on the number of outputs and the required turns
ratios required to generate them. If Schottky output rectifiers
are used and we assume a forward voltage drop of 0.45V,
the required turns ratio for the two output voltages, 3.3V and
1.8V, is 5:3.
m , lg is the length of the airgap in meters, µ is the
o
-7
permeability of free space (4π • 10 ), and ΔB is the change
in flux density in Tesla.
A core structure having less airgap volume than calculated will
be incapable of providing the full output power over some
portion of its operating range. On the other hand, if the length
of the airgap becomes large, magnetic field fringing around
the gap occurs. This has the effect of increasing the airgap
volume. Some fringing is usually acceptable, but excessive
fringing can cause increased losses in the windings around
the gap resulting in excessive heating. Once a suitable core
and gap combination are found, the iterative design cycle
begins. A design is developed and checked for ease of
assembly and thermal performance. If the core does not allow
adequate space for the windings, then a core with a larger
window area is required. If the transformer runs hot, it may be
necessary to lower the flux density (more primary turns, lower
operating frequency), select a less lossy core material,
change the geometry of the windings (winding order), use
heavier gauge wire or multi-filar windings, and/or change the
type of wire used (Litz wire, for example).
With a turns ratio of 5:3 for the secondary windings, we will
use N = 5 turns and N = 3 turns. Checking the reset time
s1 s2
using these values for the number of secondary turns yields
a duration of Tr = 2.33µs or about 47% of the switching
period, an acceptable result.
The bias winding turns may be calculated similarly, only a
diode forward drop of 0.7V is used. The rounded off result is
17 turns for a 12V bias.
The next step is to determine the wire gauge. The RMS
current in the primary winding may be calculated using
Equation 15:
t
ON(MAX)
I
= I
•
PPK
--------------------------
A
(EQ. 15)
P(RMS)
3 • t
sw
The peak and RMS current values in the remaining windings
may be calculated using Equations 16 and 17:
For simplicity, only the final design is further described.
An EPCOS EFD 20/10/7 core using N87 material gapped to
2
2 • I
• t
OUT sw
Tr
------------------------------------
(EQ. 16)
I
=
A
SPK
an A value of 25nH/N was chosen. It has more than the
L
required air gap volume to store the energy required, but
was needed for the window area it provides.
t
sw
I
= 2 • I
•
OUT
--------------
3 • Tr
A
(EQ. 17)
-6
Aeff = 31 • 10
2
RMS
m
FN6797.0
August 23, 2011
14
ISL6721A
The RMS current for the primary winding is 0.72A, for the
3.3V output, 4.23A, for the 1.8V output, 1.69A, and for the
bias winding, 85mA.
conduction losses is complicated by the variation of r
DS(ON)
with temperature. As junction temperature increases, so
does r , which increases losses and raises the
DS(ON)
junction temperature more, and so on. It is possible for the
device to enter a thermal runaway situation without proper
heatsinking. As a general rule of thumb, doubling the +25°C
To minimize the transformer leakage inductance, the primary
was split into two sections connected in parallel and
positioned such that the other windings were sandwiched
between them. The output windings were configured so that
the 1.8V winding is a tap off of the 3.3V winding. Tapping the
1.8V output requires that the shared portion of the
r
specification yields a reasonable value for
DS(ON)
estimating the conduction losses at +125°C junction
temperature.
secondary conduct the combined current of both outputs.
The secondary wire gauge must be selected accordingly.
The switching losses have two components: capacitive
switching losses and voltage/current overlap losses. The
capacitive losses occur during turn on of the device and may
be calculated in Equation 19:
The determination of current carrying capacity of wire is a
compromise between performance, size, and cost. It is
affected by many design constraints such as operating
frequency (harmonic content of the waveform) and the
winding proximity/geometry. It generally ranges between 250
and 1000 circular mils per ampere. A circular mil is defined
as the area of a circle 0.001” (1 mil) in diameter. As the
frequency of operation increases, the AC resistance of the
wire increases due to skin and proximity effects. Using
heavier gauge wire may not alleviate the problem. Instead
multiple strands of wire in parallel must be used. In some
cases, Litz wire is required.
2
1
2
--
Pswcap = • Cfet • Vin • f
W
(EQ. 19)
sw
where Cfet is the equivalent output capacitance of the
MOSFET. Device output capacitance is specified on
datasheets as Coss and is non-linear with applied voltage.
To find the equivalent discrete capacitance, Cfet, a charge
model is used. Using a known current source, the time
required to charge the MOSFET drain to the desired
operating voltage is determined and the equivalent
capacitance may be calculated in Equation 20:
Ichg • t
(EQ. 20)
The winding configuration selected is:
Primary #1: 40T, 2 #30 bifilar
-------------------
Cfet =
F
V
The other component of the switching loss is due to the
overlap of voltage and current during the switching
transition. A switching transition occurs when the MOSFET
is in the process of either turning on or off. Since the load is
inductive, there is no overlap of voltage and current during
the turn on transition, so only the turn off transition is of
significance. The power dissipation may be estimated using
Equation 21:
Secondary: 5T, 0.003” (3 mil) copper foil tapped at 3T
Bias: 17T #32
Primary #2: 40T, 2 #30 bifilar
The internal spacing and insulation system was designed for
1500VDC dielectric withstand rating between the primary
and secondary windings.
1
x
--
(EQ. 21)
P
≈
• I
• V • t • f
IN OL sw
sw
PPK
Power MOSFET Selection
Selection of the main switching MOSFET requires
consideration of the voltage and current stresses that will be
encountered in the application, the power dissipated by the
device, its size, and its cost.
where t is the duration of the overlap period and x ranges
OL
from about 3 through 6 in typical applications and depends
on where the waveforms intersect. This estimate may predict
higher dissipation than is realized because a portion of the
turn off drain current is attributable to the charging of the
device output capacitance (Coss) and is not dissipative
during this portion of the switching cycle (Figure 6).
The input voltage range of the converter is 36VDC to
75VDC. This suggests a MOSFET with a voltage rating of
150V is required due to the flyback voltage likely to be seen
on the primary of the isolation transformer.
The losses associated with MOSFET operation may be
divided into three categories: conduction, switching, and
gate drive.
The conduction losses are due to the MOSFET’s ON
resistance (Equation 18).
2
Pcond = r
• Iprms
W
(EQ. 18)
DS(ON)
where r
is the ON resistance of the MOSFET and
DS(ON)
Iprms is the RMS primary current. Determining the
FN6797.0
August 23, 2011
15
ISL6721A
1.8V output: 50mV total output ripple and noise
ESR: 30mV
Ippk
Capacitor ΔQ: 5mV
ESL: 15mV
For the 3.3V output (Equation 23):
VD-S
ΔV
--------------------------------
0.060
10.73 – 2.5
(EQ. 23)
----------------------------
= 7.3mΩ
ESR ≤
=
I
– I
SPK
OUT
Tol
FIGURE 6. SWITCHING CYCLE
The change in voltage due to the change in charge of the
output capacitor, ΔQ, determines how much capacitance is
The final component of MOSFET loss is caused by the
charging of the gate capacitance through the device gate
resistance. Depending on the relative value of any external
resistance in the gate drive circuit, a portion of this power will
be dissipated externally (Equation 22).
required on the output (Equation 24).
–6
(Ispk – Iout) • Tr
(10.73 – 2.5) • 2.33×10
---------------------------------------------
------------------------------------------------------------------
C ≥
=
= 960μF
(EQ. 24)
2 • ΔV
2 • 0.010
(EQ. 22)
Pgate = Qg • Vg • f
W
sw
ESL adds to the ripple and noise voltage in proportion to the
rate of change of current into the capacitor (V = L • di/dt)
(Equation 25).
Once the losses are known, the device package must be
selected and the heatsinking method designed. Since the
design requires a small surface mount part, a 8 Ld SOIC
package was selected. A Fairchild FDS2570 MOSFET was
selected based on these criteria. The overall losses are
estimated at 400mW.
–9
V • dt
di
0.030 • 200×10
--------------
---------------------------------------------
= 0.56nH
(EQ. 25)
L ≤
=
10.73
Capacitors having high capacitance usually do not have
sufficiently low ESL. High frequency capacitors such as
surface mount ceramic or film are connected in parallel with
the high capacitance capacitors to address the effects of
ESL. A combination of high frequency and high ripple
capability capacitors is used to achieve the desired overall
performance. The analysis of the 1.8V output is similar to
that of the 3.3V output and is omitted for brevity. Two
OSCON 4SEP560M (560µF) electrolytic capacitors and a
22µF X5R ceramic 1210 capacitor were selected for both the
3.3 and 1.8V outputs. The 4SEP560M electrolytic capacitors
are each rated at 4520mA ripple current and 13mΩ of ESR.
The ripple current rating of just one of these capacitors is
adequate, but two are needed to meet the minimum ESR
and capacitance values.
Output Filter Design
In a flyback design, the primary concern for the design of the
output filter is the capacitor ripple current stress and the
ripple and noise specification of the output.
The current flowing in and out of the output capacitors is the
difference between the winding current and the output current.
The peak secondary current, I
, is 10.73A for the 3.3V
SPK
output and 4.29A for the 1.8V output. The current flowing into
the output filter capacitor is the difference between the winding
current and the output current. Looking at the 3.3V output, the
= 10.73A. The capacitor must
store this amount minus the output current of 2.5A, or 8.23A.
The RMS ripple current in the 3.3V output capacitor is about
peak winding current is I
SPK
The bias output is of such low power and current that it
places negligible stress on its filter capacitor. A single 0.1µF
ceramic capacitor was selected.
3.5A
is about 1.4A
. The RMS ripple current in the 1.8V output capacitor
RMS
.
RMS
Voltage deviation on the output during the switching cycle
(ripple and noise) is caused by the change in charge of the
output capacitance, the equivalent series resistance (ESR),
and equivalent series inductance (ESL). Each of these
components must be assigned a portion of the total ripple
and noise specification. How much to allow for each
contributor is dependent on the capacitor technology used.
Control Loop Design
The major components of the feedback control loop are a
programmable shunt regulator, an opto-coupler, and the
inverting amplifier of the ISL6721A. The opto-coupler is used
to transfer the error signal across the isolation barrier. The
opto-coupler offers a convenient means to cross the
isolation barrier, but it adds complexity to the feedback
control loop. It adds a pole at about 10kHz and a significant
amount of gain variation due the current transfer ratio (CTR).
The CTR of the opto-coupler varies with initial tolerance,
temperature, forward current, and age.
For purposes of this discussion, we will assume the following:
3.3V output: 100mV total output ripple and noise
ESR: 60mV
Capacitor ΔQ: 10mV
ESL: 30mV
FN6797.0
August 23, 2011
16
ISL6721A
A block diagram of the feedback control loop is shown in
Figure 7.
signal in the control IC must be taken into account. The
maximum peak primary current was determined earlier to be
1.87A, so a choice of 2.25A peak primary current for current
PRIMARY SIDE AMPLIFIER
limit is reasonable. A current gain, A
, of 0.5V/A was
EXT
+
-
REF
selected to achieve this (Equation 26).
POWER
STAGE
V
OUT
PWM
Z
3
(EQ. 26)
ISET = 2.25 • 0.8 • 0.5 + 0.100 = 1.00
V
Z
The control to output transfer function may be represented as
4
ERROR AMPLIFIER
shown in Equation 27:
s
------
1 +
Z
2
ISOLATION
v
ω
R
• L • f
o
z
o
s sw
-----
----------------
= K • --------------------------------- •
(EQ. 27)
v
c
s
2
------
1 +
-
Z
1
ω
p
REF
+
If we ignore the current feedback sampled-data effects
(Equations 28 through 35):
FIGURE 7. FEEDBACK CONTROL LOOP
I
spk(max)
-------------------------
(EQ. 28)
K =
The loop compensation is placed around the Error Amplifier
(EA) on the secondary side of the converter. The primary
side amplifier located in the control IC is used as a unity gain
inverting amplifier and provides no loop compensation. A
Type 2 error amplifier configuration was selected as a
precaution in case operation in continuous mode should
occur at some operating point (Figure 8).
V
c(max)
R
o
= LoadResistance
(EQ. 29)
(EQ. 30)
(EQ. 31)
(EQ. 32)
(EQ. 33)
(EQ. 34)
(EQ. 35)
L
= SecondaryInductance
s
2
• C
1
--------------------
-----------------------------
ω
ω
C
=
=
or
or
f
=
p
p
z
o
c
R
π • R • C
o
o
o
o
V
1
1
OUT
-------------------
--------------------------------------
=
f
z
R • C
2 • π • R • C
c
o
c o
= OutputCapacitance
-
R
V
= OutputCapacitanceESR
= ControlVoltageRange
V
ERROR
+
REF
c(max)
FIGURE 8. TYPE 2 ERROR AMPLIFIER
The value of K may be determined by assuming all of the
output power is delivered by the 3.3V output at the threshold
of current limit. The maximum power allowed was
Development of a small signal model for current mode
control is rather complex. The method of reference was
1
determined earlier as 15W, therefore (Equations 36, 37):
selected for its ability to accurately predict loop behavior. To
further simplify the analysis, the converter will be modeled as
a single output supply with all of the output capacitance
reflected to the 3.3V output. Once the “single” output system
is compensated, adjustments to the compensation will be
required based on actual loop measurements.
P
out
–6
15
3.3
-----------
2 •
• t
sw
-------
2 •
• 5×10
V
out
Tr
-----------------------------------
-----------------------------------------
I
=
=
= 19.5
= 2.93
A
spk(max)
–6
2.33×10
(EQ. 36)
1
--------------------
v
= V
• A
• A •
CS
V
c(max)
ISENSE
EXT
A
The first parameter to determine is the peak current
feedback loop gain. Since this application is low power, a
resistor in series with the source of the power switching
MOSFET is used for the current feedback signal. For higher
power applications, a resistor would dissipate too much
power and current transformer would be used instead.
COMP
(EQ. 37)
where A
EXT
is the external gain of the current feedback
is the IC internal gain, and A is the gain
network, A
CS
COMP
between the error amplifier and the PWM comparator.
The Type 2 compensation configuration has two poles and
one zero. The first pole is at the origin, and provides the
integration characteristic which results in excellent DC
regulation. Referring to the Typical Application Schematic on
There is limited flexibility to adjust the current loop behavior
due to the need to provide overcurrent protection. Current
limit and the current loop gain are determined by the current
sense resistor and the ISET threshold. ISET was set at 1.0V,
near its maximum, to minimize noise effects. When
determining ISET, the internal gain and offset of the ISENSE
FN6797.0
August 23, 2011
17
ISL6721A
page 4, the remaining pole and zero for the compensator are
located at (Equations 38, 39):
A Bode plot of the closed loop system at low line, max load
appears in Figures 9A and 9B.
C
+ C
14
50
40
30
20
10
0
1
13
------------------------------------------------------------ --------------------------------------------
f
=
≈
(EQ. 38)
pc
2 • π • R • C • C
2 • π • R • C
15 14
15
14
13
1
--------------------------------------------
f
=
(EQ. 39)
zc
2 • π • R • C
15
13
-10
-20
The ratio of R to the parallel combination of R and R
15 17
determine the mid band gain of the error amplifier
18
-30
-40
-50
10k
(Equation 40).
100k
1M
10M
100M
R
• (R + R
)
18
FREQUENCY (Hz)
15
17
-----------------------------------------------
A
=
(EQ. 40)
midband
R
• R
18
17
FIGURE 9A. GAIN
From Equation 27, it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitance, and
the output capacitance ESR. These variations must be
considered when compensating the control loop. The worst
case small signal operating point for the converter is at
200
150
100
50
minimum V , maximum load, maximum C
, and
OUT
IN
0
minimum ESR.
-50
-100
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the bandwidth
10k
100k
1M
10M
100M
FREQUENCY (Hz)
to about f /4. For this example, the bandwidth will be further
sw
FIGURE 9B. PHASE MARGIN
limited due to the low GBWP of the LM431-based Error
Amplifier and the opto-coupler. A bandwidth of approximately
5kHz was selected.
Regulation Performance
TABLE 1. OUTPUT LOAD REGULATION, V = 48V
IN
For the EA compensation, the first pole is placed at the
I
(A), 3.3V
0
I
(A), 1.8V
V
(V), 3.3V
V
(V), 1.8V
origin by default (C is an integrating capacitor). The first
zero is placed below the crossover frequency, f , usually
co
OUT
OUT
OUT
OUT
14
0.030
0.030
0.030
0.030
0.030
0.030
0030
0.030
0.52
3.351
1.825
around 1/3 f . The second pole is placed at the lower of the
co
0.39
0.88
1.38
1.87
2.39
2.89
3.37
0
3.281
3.251
3.223
3.204
3.185
3.168
3.153
3.471
3.283
3.254
3.233
3.218
3.203
3.191
3.619
3.290
1.956
1.988
2.014
2.029
2.057
2.084
2.103
1.497
1.800
1.836
1.848
1.855
1.859
1.862
1.347
1.730
ESR zero or at one half of the switching frequency. The
midband gain is then adjusted to obtain the desired
crossover frequency. If the phase margin is not adequate,
the crossover frequency may have to be reduced.
Using this technique to determine the compensation, the
following values for the EA components were selected.
R
R
C
C
= R = R = 1kΩ
18 15
17
20
13
14
= open
= 100nF
= 100pF
0.39
0.88
1.38
1.87
2.39
2.89
0
0.52
0.52
0.52
0.52
0.52
0.52
1.05
0.39
1.05
FN6797.0
August 23, 2011
18
ISL6721A
TABLE 1. OUTPUT LOAD REGULATION, V = 48V (Continued)
Waveforms
IN
Typical waveforms can be found in Figures 10 through 12.
Figure 10 shows the steady state operation of the sawtooth
oscillator waveform at RTCT (Trace 2), the SYNC output
pulse (Trace 1), and the GATE output to the converter FET
(Trace 3). Figure 11 shows the converter behavior while
operating in an overcurrent fault condition. Trace 1 is the
soft-start voltage, which increases from 0V to 4.5V, at which
point the OC fault function is enabled. The OC condition is
detected and the soft-start capacitor is discharged to the
4.375V OC fault threshold at which point the IC enters the
fault shutdown mode. Trace 2 shows the behavior of the
timing capacitor voltage during a shutdown fault. Most of the
functions of the IC are de-powered during a fault, and the
oscillator is among those functions. During a fault, the IC is
turned off until the restart delay has timed out. After the
delay, power is restored and the IC resumes normal
operation. Trace 3 is the GATE output during the soft-start
cycle and OC fault.
I
(A), 3.3V
0.88
1.38
1.87
2.39
0
I
(A), 1.8V
1.05
1.05
1.05
1.05
1.55
1.55
1.55
1.55
1.55
2.07
2.07
2.07
2.07
2.62
2.62
2.62
3.14
3.14
V
(V), 3.3V
V
(V), 1.8V
OUT
OUT
OUT
OUT
3.254
1.785
3.235
3.220
3.207
3.699
3.306
3.260
3.239
3.224
3.762
3.329
3.270
3.245
3.819
3.355
3.282
3.869
3.383
1.805
1.814
1.820
1.265
1.682
1.750
1.776
1.789
1.201
1.645
1.722
1.752
1.142
1.612
1.697
1.091
1.581
0.39
0.88
1.38
1.87
0
0.39
0.88
1.38
0
0.39
0.88
0
0.39
NOTE:
Trace 1: SYNC Output
Trace 2: RTCT Sawtooth
Trace 3: GATE Output
FIGURE 10. TYPICAL WAVEFORMS
FN6797.0
August 23, 2011
19
ISL6721A
NOTE:
Trace 1: SS
Trace 2: RTCT Sawtooth
Trace 3: GATE Output
NOTE:
Trace 1: V
Trace 3: V
D-S
G-S
FIGURE 12. GATE AND DRAIN-SOURCE WAVEFORMS
FIGURE 11. SOFT-START WITH OVERCURRENT FAULT
Figure 12 shows the switching FET waveforms during
steady state operation. Trace 1 is drain-source voltage and
Trace 2 is gate-source voltage.
FN6797.0
August 23, 2011
20
ISL6721A
Component List
REFERENCE DESIGNATOR
VALUE
1.0µF
DESCRIPTION
C , C , C
3
Capacitor, 1812, X7R, 100V, 20%
Capacitor, 0603, X7R, 25V, 10%
1
2
C , C
0.1µF
5
13
C
, C , C , C
560µF
470pF
0.01µF
22µF
Capacitor, Radial, SANYO 4SEP560M
Capacitor, 0603, COG, 50V, 5%
Capacitor, 0805, X7R, 50V, 10%
Capacitor, 1210, X5R, 10V, 20%
Capacitor, 0603, COG, 50V, 5%
Capacitor, Disc, Murata DE1E3KX152MA5BA01
0Ω Jumper, 0603
15 16 19 20
C
17
18
C
C
, C
21 22
C , C
100pF
1500pF
4
14
C
C
C
6
7
8
330pF
Capacitor, 0603, COG, 50V, 5%
Capacitor, 0603, X7R, 16V, 10%
Diode, Fairchild ES1C
C , C , C , C
10 11 12
0.22µF
9
C , C
R2 R6
C
, C
R4 R5
Diode, IR 12CWQ03FN
Zener, 18V, Zetex BZX84C18
Diode, Schottky, BAT54C
FET, Fairchild FDS2570
Transistor, Zetex FMMT491A
Transistor, ON MJD31C
Resistor, 1206, 1%
D
D
1
2
Q
Q
Q
1
2
3
R , R
1.00k
20.0k
10.0k
38.3k
1.00k
10
1
2
R
Resistor, 0603, 1%
10
R , R , R , R , R
11 26 27
Resistor, 0603, 1%
7
9
R
Resistor, 0603, 1%
12
R
, R , R , R , R , R
Resistor, 0603, 1%
13 15 17 18 19 25
R
R
R
R
R
Resistor, 0603, 1%
14
16
21
22
24
165
Resistor, 0603, 1%
10.0
5.11
Resistor, 1206, 1%
Resistor, 0603, 1%
3.92k
100
Resistor, 2512, 1%
R , R
Resistor, 0603, 1%
3
23
R
R
R
1.00
221k
75.0k
Resistor, 2512, 1%
4
5
6
Resistor, 0603, 1%
Resistor, 0603, 1%
R , R
OMIT
8
20
T
Transformer, MIDCOM 31555
Opto-coupler, NEC PS2801-1
Shunt Reference, National LM431BIM3
PWM, Intersil ISL6721IB
Zener, 15V, Zetex BZX84C15
1
U
U
U
2
3
4
V
R1
FN6797.0
August 23, 2011
21
ISL6721A
References
1. Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power Electronics,
Vol. 6, No. 2, April 1991.
2. Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode
Power Supply Design Seminar, SEM-700, 1990.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6797.0
August 23, 2011
22
ISL6721A
Package Outline Drawing
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.09-0.20
0.65
TOP VIEW
END VIEW
1.00 REF
-
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25 +0.05/-0.06
0.25
5
0.10
C B A
M
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153.
FN6797.0
August 23, 2011
23
ISL6721A
L16.3x3B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 4/07
4X
1.5
3.00
0.50
12X
A
6
B
PIN #1 INDEX AREA
16
13
6
PIN 1
INDEX AREA
12
1
4
+
0.10
1 .70
- 0.15
9
(4X)
0.15
5
8
0.10 M C A B
+
0.07
4
16X 0.23
TOP VIEW
- 0.05
16X 0.40 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 90 ± 0.1
BASE PLANE
SEATING PLANE
0.08
( 2. 80 TYP )
(
C
SIDE VIEW
1. 70 )
( 12X 0 . 5 )
( 16X 0 . 23 )
( 16X 0 . 60)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6797.0
August 23, 2011
24
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