ISL6840IUZ-T7 [RENESAS]
Switching Controller;
| 型号： | ISL6840IUZ-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Switching Controller 开关 |
| 文件： | 总14页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6840, ISL6841, ISL6842,
ISL6843, ISL6844, ISL6845
Data Sheet
February 18, 2015
FN9124.13
Improved Industry Standard Single-Ended
Current Mode PWM Controller
Features
• 1A MOSFET Gate Driver
The ISL6840, ISL6841, ISL6842, ISL6843, ISL6844,
ISL6845 family of adjustable frequency, low power, pulse
width modulating (PWM) current mode controllers is
designed for a wide range of power conversion applications
including boost, flyback, and isolated output configurations.
Peak current mode control effectively handles power
transients and provides inherent overcurrent protection.
• 60µA Start-up Current, 100µA Maximum
• 25ns Propagation Delay Current Sense to Output
• Fast Transient Response with Peak Current Mode Control
• Adjustable Switching Frequency to 2MHz
• 20ns Rise and Fall Times with 1nF Output Load
This advanced BiCMOS design is pin compatible with the
industry standard 384x family of controllers and offers
significantly improved performance. Features include low
operating current, 60µA start-up current, adjustable
operating frequency to 2MHz, and high peak current drive
capability with 20ns rise and fall times.
• Trimmed Timing Capacitor Discharge Current for Accurate
Deadtime/Maximum Duty Cycle Control
• High Bandwidth Error Amplifier
• Tight Tolerance Voltage Reference Over Line, Load, and
Temperature
• Tight Tolerance Current Limit Threshold
• Pb-Free Available (RoHS Compliant)
PART NUMBER
ISL6840
RISING UVLO (V) MAX. DUTY CYCLE (%)
7.0
7.0
100
50
ISL6841
Applications
ISL6842
14.4
8.4
100
100
50
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
ISL6843
ISL6844
14.4
8.4
ISL6845
50
• Industrial Power Systems
• PC Power Supplies
Pinouts
• Isolated Buck and Flyback Regulators
• Boost Regulators
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
(8 LD SOIC, MSOP)
TOP VIEW
COMP
FB
1
2
3
4
8
7
VREF
VDD
OUT
GND
CS
6
5
RTCT
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
(8 LD DFN)
TOP VIEW
COMP
VREF
1
2
3
4
8
7
6
5
FB
CS
VDD
OUT
GND
RTCT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2004, 2005, 2007, 2008, 2012, 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
1
All other trademarks mentioned are the property of their respective owners.
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Ordering Information
PART NUMBER
(Note 4)
TEMP RANGE
(°C)
PART MARKING
PACKAGE
8 Ld 2x3 DFN (Pb-free)
8 Ld MSOP (Pb-free)
8 Ld MSOP (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld 2x3 DFN (Pb-free)
PKG. DWG. #
L8.2x3
ISL6840IRZ-T (Notes 2, 3)
ISL6840IUZ (Notes 1, 3)
ISL6841IUZ (Notes 1, 3)
ISL6842IBZ (Notes 1, 3)
40Z
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
6840Z
M8.118
M8.118
M8.15
6841Z
6842 IBZ
ISL6842IRZ-T (Notes 2, 3) (No longer 42Z
available, recommended
L8.2x3
replacement: ISL6842IBZ-T)
ISL6842IUZ (Notes 1, 3) (No longer 6842Z
available, recommended
-40 to +105
8 Ld MSOP (Pb-free)
M8.118
replacement: ISL6842IBZ)
ISL6843IBZ (Notes 1, 3)
6843 IBZ
-40 to +105
-40 to +105
8 Ld SOIC (Pb-free)
8 Ld MSOP
M8.15
ISL6843IU-T (No longer available,
recommended replacement:
ISL6843IUZ-T)
6843
M8.118
ISL6843IUZ (Notes 1, 3)
6843Z
-40 to +105
-40 to +105
8 Ld MSOP (Pb-free)
8 Ld SOIC (Pb-free)
M8.118
M8.15
ISL6844IBZ (Notes 1, 3) (No longer 6844 IBZ
available, recommended
replacement: ISL8844AABZ)
ISL6845IBZ (Notes 1, 3) (No longer 6845 IBZ
available, recommended
-40 to +105
8 Ld SOIC (Pb-free)
M8.15
replacement: ISL8845AABZ)
ISL6841EVAL3Z
NOTES:
Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Contact Factory for Availability.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845.For more
information on MSL please see tech brief TB363.
FN9124.13
February 18, 2015
2
Functional Block Diagram
V
VREF
VDD
REF
5.00V
UVLO
COMPARATOR
ENABLE
V
OK
DD
+
-
-
VREF FAULT
+
+
BG
-
VREF
UV COMPARATOR
4.65V 4.80V
GND
A
BG
2.5V
A = 0.5
PWM
COMPARATOR
CS
+
-
100mV
ERROR
AMPLIFIER
ISL6841/ISL6844/ISL6845
ONLY
2R
1.1V
CLAMP
+
-
FB
Q
T
R
Q
COMP
OUT
VREF
S
R
Q
Q
2.6V
0.7V
RESET
DOMINANT
ON
OSCILLATOR
COMPARATOR
-
RTCT
+
CLOCK
UVLO ON/OFF
7.0/6.6V
14.3/8.8V
P/N
8.4mA
ON
-40, -41
-42, -44
-43, -45
8.4/7.2V
Typical Application - 48V Input Dual Output Flyback
CR5
+3.3V
+1.8V
C21
+ C15
+ C16
T1
R21
VIN+
C4
R3
CR4
+
C20
C22
+
C17
C6
C2
C19
CR2
C5
RETURN
CR6
R1
36V TO 75V
R17
R19
C14
R18
R16
U2
C1
C3
Q1
R4
R15
R22
C13
U3
VIN-
R27
R20
U4
COMP
R26
VREF
V
CS
FB
DD
OUT
RTCT
GND
ISL684x
R6
R10
CR1
Q3
C12
C8
VR1
C11
R13
Typical Application - Boost Converter
R8
C10
CR1
L1
VIN+
+VOUT
+
C2
C3
R4
RETURN
Q1
R5
C9
C1
R1
R2
U1
R7
VIN+
VREF
VDD
OUT
COMP
C8
R6
FB
CS
C4
RTCT
GND
R3
C5
C6
C7
VIN-
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
Thermal Resistance (Typical)
(°C/W)
(°C/W)
JC
DD
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V
JA
+ 0.3V
DD
DFN Package (Notes 5, 6). . . . . . . . . .
SOIC Package (Note 5) . . . . . . . . . . . .
MSOP Package (Notes 5, 7) . . . . . . . .
77
100
165
6
N/A
62
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
ISL684xIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
ISL684xCx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage Range (Typical, Note 8)
ISL6840, ISL6841. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V to 14V
ISL6843, ISL6845. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 16V
ISL6842, ISL6844. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V to 18V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
6. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. For , the “case temp” location is taken at the package top center.
JC
8. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” and
“Typical Application” schematic on pages 3 and 4. V
= 15V (Note 12), R = 10k, C = 3.3nF,
DD
= -40°C to +105°C (Industrial) or T = 0°C to +70°C (Commercial), Typical values are at T = +25°C.
t t
T
A
A
A
Boldface limits apply over the operating temperature range, -40°C to +105°C or 0°C to +70°C.
MIN
MAX
PARAMETER
TEST CONDITIONS
(Note 9) TYP
(Note 9)
UNITS
UNDERVOLTAGE LOCKOUT
START Threshold (ISL6840, ISL6841)
START Threshold (ISL6843, ISL6845)
START Threshold (ISL6842, ISL6844)
STOP Threshold (ISL6840, ISL6841)
STOP Threshold (ISL6843, ISL6845)
STOP Threshold (ISL6843C Only)
STOP Threshold (ISL6842, ISL6844)
Hysteresis (ISL6840, ISL6841)
6.5
7.8
13.3
6.1
6.7
6.6
8.0
-
7.0
8.4
14.3
6.6
7.2
7.2
8.8
0.4
0.8
5.4
60
7.5
9.0
15.3
6.9
7.7
7.8
9.6
-
V
V
V
V
V
V
V
V
Hysteresis (ISL6843, ISL6845)
-
-
V
Hysteresis (ISL6842, ISL6844)
-
-
V
Start-up Current, I
V
< START Threshold
-
100
4.0
5.5
µA
mA
mA
DD
DD
(Note 10)
Includes 1nF GATE loading
Operating Current, I
-
3.3
4.1
DD
Operating Supply Current, I
REFERENCE VOLTAGE
Overall Accuracy
-
D
Over line (V
= 12V to 18V), load, temperature
4.925
4.82
-
5.000
5.000
5
5.050
5.18
-
V
V
DD
Overall Accuracy (ISL6843C Only)
Long Term Stability
Fault Voltage
T
= +125°C, 1000 hours (Note 11)
mV
V
A
4.40
4.60
50
4.65
4.85
VREF Good Voltage
Hysteresis
4.80 VREF - 0.05
165 250
V
mV
FN9124.13
February 18, 2015
6
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” and
“Typical Application” schematic on pages 3 and 4. V
= 15V (Note 12), R = 10k, C = 3.3nF,
DD
= -40°C to +105°C (Industrial) or T = 0°C to +70°C (Commercial), Typical values are at T = +25°C.
t t
T
A
A
A
Boldface limits apply over the operating temperature range, -40°C to +105°C or 0°C to +70°C. (Continued)
MIN
MAX
PARAMETER
Current Limit, Sourcing
TEST CONDITIONS
(Note 9) TYP
(Note 9)
UNITS
mA
-20
5
-
-
-
-
Current Limit, Sinking
mA
CURRENT SENSE
Input Bias Current
V
V
V
= 1V
-1.0
95
-
1.0
105
1.30
1.03
1.07
3.5
µA
mV
V
CS
CS
CS
CS Offset Voltage
= 0V (Note 11)
= 0V (Note 11)
100
1.15
0.97
0.97
3.0
COMP to PWM Comparator Offset Voltage
Input Signal, Maximum
0.80
0.91
0.9
2.5
-
V
Input Signal, Maximum (ISL6843C Only)
V
Gain, A
= V
/V
0 < V < 910mV, V = 0V (Note 11)
CS FB
V/V
ns
ns
CS
COMP
CS
CS to OUT Delay
(Note 11)
(Note 11)
25
40
CS to OUT Delay (ISL6843C Only)
ERROR AMPLIFIER
Open Loop Voltage Gain
Open Loop Voltage Gain (ISL6843C Only)
Unity Gain Bandwidth
Reference Voltage
70
(Note 11)
(Note 11)
60
55
90
-
dB
dB
MHz
V
(Note 11)
3.5
5
-
2.55
1.0
-
V
V
V
V
V
V
= V
COMP
2.475
-1.0
1.0
2.514
FB
FB
FB Input Bias Current
COMP Sink Current
COMP Source Current
COMP VOH
= 0V
-0.2
µA
mA
mA
V
= 1.5V, V = 2.7V
FB
-
-
COMP
COMP
= 1.5V, V = 2.3V
FB
-0.4
4.80
0.4
-
= 2.3V
-
VREF
1.0
-
FB
FB
COMP VOL
= 2.7V
-
V
PSRR
Frequency = 120Hz, V
= 12V to 18V (Note 11)
60
80
dB
DD
OSCILLATOR
Frequency Accuracy
Initial, T = +25°C
49
52
0.2
-
55
1.0
5
kHz
%
J
Frequency Variation with V
Temperature Stability
Amplitude, Peak-to-Peak
RTCT Discharge Voltage
Discharge Current
OUTPUT
T = +25°C (f
(Note 11)
- f
)/f
-
DD
18V 12V 12V
-
-
%
1.9
0.7
8.4
-
V
-
-
V
RTCT = 2.0V
7.2
9.5
mA
Gate VOH
V
to OUT, I
OUT
= -200mA
= 200mA
-
-
-
-
-
1.0
1.0
1.0
20
2.0
2.0
-
V
V
DD
Gate VOL
OUT to GND, I
OUT
Peak Output Current
Rise Time
C
C
C
= 1nF (Note 11)
= 1nF (Note 11)
= 1nF (Note 11)
A
OUT
OUT
OUT
40
40
ns
ns
Fall Time
20
PWM
FN9124.13
February 18, 2015
7
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” and
“Typical Application” schematic on pages 3 and 4. V
= 15V (Note 12), R = 10k, C = 3.3nF,
DD
= -40°C to +105°C (Industrial) or T = 0°C to +70°C (Commercial), Typical values are at T = +25°C.
t t
T
A
A
A
Boldface limits apply over the operating temperature range, -40°C to +105°C or 0°C to +70°C. (Continued)
MIN
MAX
PARAMETER
Maximum Duty Cycle
TEST CONDITIONS
ISL6840, ISL6842, ISL6843
(Note 9) TYP
(Note 9)
UNITS
%
94
47
-
96
48
-
-
-
ISL6841, ISL6844, ISL6845
ISL6840, ISL6842, ISL6843
ISL6841, ISL6844, ISL6845
%
Minimum Duty Cycle
0
0
%
-
-
%
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. This is the V
DD
current consumed when the device is active but not switching. Does not include gate drive current.
11. Limits established by characterization and are not production tested.
12. Adjust V above the start threshold and then lower to 15V.
DD
Typical Performance Curves
1.001
1.000
0.999
1.02
1.01
1.00
0.99
0.98
0.97
0.998
0.997
0.996
0.995
-40
-10
20
50
80
110
-40 -25 -10
5
20 35 50 65 80 95 110
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 1. FREQUENCY vs TEMPERATURE
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
3
1.002
10
1.000
0.998
0.996
100pF
100
10
1
220pF
330pF
470pF
1.0nF
2.2nF
3.3nF
4.7nF
0.994
-40 -25 -10
5
20 35 50 65 80 95 110
10
20 30 40
50 60
70 80 90 100
TEMPERATURE (°C)
RT (kΩ)
FIGURE 3. EA REFERENCE vs TEMPERATURE
FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN
FN9124.13
February 18, 2015
8
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Functional Description
Pin Descriptions
RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
connecting a resistor, RT, between VREF and this pin and a
timing capacitor, CT, from this pin to GND. The oscillator
produces a sawtooth waveform with a programmable
Features
The ISL684x current mode PWMs make an ideal choice for
low-cost flyback and forward topology applications. With its
greatly improved performance over industry standard parts,
it is the obvious choice for new designs or existing designs
which require updating.
frequency range up to 2.0MHz. The charge time, t , the
C
discharge time, t , the switching frequency, f, and the
D
Oscillator
maximum duty cycle, Dmax, can be calculated from
Equations 1, 2, 3 and 4:
The ISL684x family of controllers have a sawtooth oscillator
with a programmable frequency range to 2MHz, which can
be programmed with a resistor from VREF and a capacitor to
GND on the RTCT pin. (Please refer to Figure 4 for the
resistor and capacitance required for a given frequency.)
(EQ. 1)
(EQ. 2)
t
0.583 RT CT
C
0.0083 RT – 4.3
----------------------------------------------
t
–RT CT ln
D
0.0083 RT – 2.4
Soft-Start Operation
f = 1 t + t
(EQ. 3)
(EQ. 4)
C
D
Soft-start must be implemented externally. One method,
illustrated in Figure 5, clamps the voltage on COMP.
D = t f
C
Figure 4 may be used as a guideline in selecting the
capacitor and resistor values required for a given frequency.
VREF
COMP
GND
COMP - COMP is the output of the error amplifier and the
input of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
FB - The output voltage feedback is connected to the
inverting input of the error amplifier through this pin. The
non-inverting input of the error amplifier is internally tied to a
reference voltage.
FIGURE 5. SOFT-START
CS - This is the current sense input to the PWM comparator.
The range of the input signal is nominally 0V to 1.0V and has
an internal offset of 100mV.
Gate Drive
The ISL684x family are capable of sourcing and sinking 1A
peak current. To limit the peak current through the IC, an
optional external resistor may be placed between the
totem-pole output of the IC (OUT pin) and the gate of the
MOSFET. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance.
GND - GND is the power and small signal reference ground
for all functions.
OUT - This is the drive output to the power switching device.
It is a high current output capable of driving the gate of a
power MOSFET with peak currents of 1.0A.
VDD - V
DD
is the power connection for the device. The total
supply current will depend on the load applied to OUT. Total
current is the sum of the operating current and the
average output current. Knowing the operating frequency, f,
and the MOSFET gate charge, Qg, the average output
current can be calculated in Equation 5:
Slope Compensation
I
DD
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability. The minimum amount of slope
I
= Qg f
(EQ. 5)
OUT
To optimize noise immunity, bypass V
DD
to GND with a
ceramic capacitor as close to the VDD and GND pins as
possible.
compensation required corresponds to 1/2 the inductor
downslope. Adding excessive slope compensation,
however, results in a control loop that behaves more as a
voltage mode controller than as a current mode controller.
VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 3.3µF capacitor to filter this output as
needed.
Slope compensation may be added to the CS signal shown
in Figure 7.
FN9124.13
February 18, 2015
9
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
DOWNSLOPE
CURRENT SENSE SIGNAL
TIME
FIGURE 6. CURRENT SENSE DOWNSLOPE
RTCT
VREF
CS
FIGURE 7. SLOPE COMPENSATION
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When a
Fault is detected, OUT is disabled. When VREF exceeds
4.80V, the Fault condition clears, and OUT is enabled.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. V
should be
bypassed directly to GND with good high frequency capacitors.
DD
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
February 18, 2016
FN9124.13 -Updated Ordering Information table on page 2.
September 29, 2015 FN9124.12 - Updated Ordering Information Table on page 2.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD L8.2X3 to latest revision changes are as follow:
-Revision 1 to Revision 2 Changes:
Tiebar Note 5 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or
ends).
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FN9124.13
February 18, 2015
11
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN9124.13
February 18, 2015
12
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
8
DETAIL "X"
D
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.36
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN9124.13
February 18, 2015
13
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844, ISL6845
Package Outline Drawing
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 3/15
2.00
A
2X 1.50
PIN 1
INDEX AREA
6X 0.50
B
1
6
PIN #1
INDEX AREA
1.80 +0.10/-0.15
(4X)
0.15
8
4
8X 0.25 +0.07/-0.05
8X 0.40 ±0.10
0.10 M C A B
TOP VIEW
1.65 +0.10/-0.15
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.90 ±0.10
(1.65)
(1.50)
C
BASE PLANE
SEATING PLANE
0.08 C
(8X 0.60)
0.05 MAX
SIDE VIEW
0.20 REF
(1.80)
(2.80)
C
(6X 0.50)
0.05 MAX
DETAIL "X"
(8X 0.25)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6.
7. Compies to JEDEC MO-229 VCED-2.
FN9124.13
February 18, 2015
14
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