ISL80030 [RENESAS]
3A Synchronous Buck Converter in 2x2 DFN Package;
| 型号： | ISL80030 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 3A Synchronous Buck Converter in 2x2 DFN Package |
| 文件： | 总20页 (文件大小：1308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL80030, ISL80030A, ISL80031, ISL80031A
3A Synchronous Buck Converter in 2x2 DFN Package
FN8766
Rev.2.00
Nov 16, 2017
The ISL80030, ISL80030A, ISL80031, and ISL80031A are highly
Features
efficient, monolithic, synchronous step-down DC/DC converters
that can deliver up to 3A of continuous output current from a 2.7V
to 5.5V input supply. They use peak current mode control
architecture to allow very low duty cycle operation. These devices
operate at either a 1MHz or 2MHz switching frequency, thereby
providing superior transient response and allowing for the use of
small inductors. They also have excellent stability.
• V range 2.7V to 5.5V
IN
• Up to 3A of output current
• Switching frequency of 1MHz or 2MHz (see Table 1 on page 3)
• 35µA quiescent current (ISL80031 and ISL80031A)
• Overcurrent and short-circuit protection
• Over-temperature/thermal protection
• Negative current protection
The ISL80030, ISL80030A, ISL80031, and ISL80031A integrate
very low r
MOSFETs to maximize efficiency. In addition,
DS(ON)
because the high-side MOSFET is a PMOS, the need for a Boot
capacitor is eliminated, thereby reducing external component
count. The devices can operate at 100% duty cycle.
• Power-good and enable
• 100% duty cycle
The ISL80030 and ISL80030A are configured for PWM pulse
width modulation operation and provide a fast transient
response, which helps reduce the output noise and RF
interference.
• Internal soft-start and soft-stop
• V undervoltage lockout and V
IN
overvoltage protection
OUT
• Up to 95% peak efficiency
The ISL80031 and ISL80031A are configured for PFM
discontinuous conduction operation and provide high
efficiency by reducing switching losses at light loads.
Applications
• General purpose POL
• Industrial, instrumentation, and medical equipment
• Telecom and networking equipment
• Game consoles
These devices are offered in a space saving 8 Ld 2mmx2mm
DFN Pb-free package with exposed pad for improved thermal
performance. The complete converter occupies an area less
2
than 64mm .
Related Literature
• For a full list of related documents, visit our website
- ISL80030, ISL80030A, ISL80031, ISL80031A product
pages
100
ISL80030/ISL80031
V
= 3.3V
OUT
L1
+2.7 TO +5.5V
+1.8V/3A
1
2
3
4
8
7
VIN
VOUT
GND
VIN
VIN
EN
PHASE
PGND
PGND
FB
93
87
80
73
67
60
C2
22µF
C1
22µF
GND
EPAD
C3
22pF
6
EN
PG
V
= 1.8V
R1
OUT
200k 1%
5
0.6V
PG
R2
100k1%
V
= 2.5V
OUT
9
V
O
(EQ. 1)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
LOAD (A)
------------
R
= R
– 1
1
2
VFB
FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION
FIGURE 2. EFFICIENCY vs LOAD, ISL80031,
= 5V, T = +25°C
V
IN
A
FN8766 Rev.2.00
Nov 16, 2017
Page 1 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PFM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Short-Circuit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Negative Current Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Enable, Disable and Soft-Start Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FN8766 Rev.2.00
Nov 16, 2017
Page 2 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
TABLE 1. SUMMARY OF KEY DIFFERENCES
f
V
RANGE
(V)
I
(MAX)
PACKAGE
SIZE
SW
IN
OUT
(A)
PART#
ISL80030
PWM/PFM MODE
(MHz)
PWM
PWM
PFM
PFM
1
2
1
2
ISL80030A
ISL80031
ISL80031A
2.7 to 5.5
3
8 pin 2mmx2mm DFN
NOTE: In this datasheet, the parts in this table are collectively called “device”.
TABLE 2. COMPONENT VALUE SELECTION TABLE
V
C
C
C
L
R
R
2
OUT
1
2
3
1
1
(V)
0.8
1.2
1.5
1.8
2.5
3.3
(µF)
22
22
22
22
22
22
(µF)
22
22
22
22
22
22
(pF)
22
22
22
22
22
22
(µH)
(kΩ)
(kΩ)
100
100
100
100
100
100
1.0~2.2
1.0~2.2
1.0~2.2
1.0~3.3
1.5~3.3
1.5~4.7
33
100
150
200
316
450
FN8766 Rev.2.00
Nov 16, 2017
Page 3 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Pin Configuration
ISL80030, ISL80030A, ISL80031, ISL80031A
(8 LD 2x2 DFN)
TOP VIEW
VIN
VIN
EN
1
2
3
4
8
7
6
5
PHASE
PGND
PGND
EPAD
(GND)
PG
FB
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1, 2
VIN
The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides
bias for the IC. Place a minimum of 10µF ceramic capacitance from VIN to GND and as close as possible to the IC for
decoupling.
3
EN
Device enable input. When the voltage on this pin rises above 1.4V, the device is enabled. The device is disabled when
the pin is pulled to ground. When the device is disabled, a 100Ω resistor discharges the output through the PHASE pin.
See Figure 3, “Functional Block Diagram” on page 5 for details.
4
5
PG
FB
The power-good output is pulled to ground during the soft-start interval and also when the output voltage is below
regulation limits. This pin has an internal 5MΩ internal pull-up resistor.
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. The output voltage is set by
an external resistor divider connected to FB. In addition, the power-good PWM regulator’s power-good and undervoltage
protection circuits use FB to monitor the output voltage.
6, 7
8
PGND
Power and analog ground connections. Connect directly to the board GROUND plane.
PHASE
Power stage switching node for output voltage regulation. Connect to the output inductor. This pin is discharged by a
100Ω resistor when the device is disabled. See Figure 3, “Functional Block Diagram” on page 5 for details.
-
EPAD
The exposed pad must be connected to the PGND pin for proper electrical performance. Place as many vias as possible
under the pad connecting to the PGND plane for optimal thermal performance.
FN8766 Rev.2.00
Nov 16, 2017
Page 4 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Functional Block Diagram
27pF
SOFT-
SHUTDOWN
START
200kΩ
+
VIN
OSCILLATOR
+
EN
VREF
BANDGAP
+
EAMP
COMP
-
P
N
-
PWM/PFM
LOGIC
SHUTDOWN
PHASE
PGND
CONTROLLER
PROTECTION
HS DRIVER
3pF
+
FB
SLOPE
COMP
1.15*VREF
6kΩ
+
-
-
CSA
OV
+
+
-
OCP
SKIP
-
0.85*VREF
VIN
5MΩ
+
UV
+
-
PG
1ms
DELAY
NEG CURRENT
SENSING
ZERO-CROSS
SENSING
-
SCP
+
0.3V
100Ω
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN8766 Rev.2.00
Nov 16, 2017
Page 5 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TAPE AND REEL
QUANTITY
PART
MARKING
TECHNICAL
SPECIFICATIONS
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL80030FRZ-T
1000
250
030
030
30A
30A
031
031
31A
31A
1MHz, PWM
1MHz, PWM
2MHz, PWM
2MHz, PWM
1MHz, PFM
1MHz, PFM
2MHz, PFM
2MHz, PFM
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
8 Ld DFN
8 Ld DFN
8 Ld DFN
8 Ld DFN
8 Ld DFN
8 Ld DFN
8 Ld DFN
8 Ld DFN
L8.2x2E
ISL80030FRZ-T7A
ISL80030AFRZ-T
ISL80030AFRZ-T7A
ISL80031FRZ-T
L8.2x2E
L8.2x2E
L8.2x2E
L8.2x2E
L8.2x2E
L8.2x2E
L8.2x2E
1000
250
1000
250
ISL80031FRZ-T7A
ISL80031AFRZ-T
ISL80031AFRZ-T7A
1000
250
ISL80030DEMO1Z Demonstration Board for the ISL80030
ISL80031DEMO1Z Demonstration Board for the ISL80031
ISL80030ADEMO1Z Demonstration Board for the ISL80030A
ISL80031ADEMO1Z Demonstration Board for the ISL80031A
NOTES:
1. Refer to TB347 for details on tape and reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), refer to the ISL80030, ISL80030A, ISL80031, ISL80031A product information pages. For more information on
MSL, refer to TB363.
FN8766 Rev.2.00
Nov 16, 2017
Page 6 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Absolute Maximum Ratings
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
PHASE . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6V (DC) or 7V (20ms)
EN, PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
ESD Rating
Human Body Model (Tested per JESD22-JS-001). . . . . . . . . . . . . . . . 4kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . . 2kV
Latch-Up (Tested per JESD78D, Class 2, Level A). . . . ±100mA at +125°C
Thermal Resistance (Typical, Notes 4, 5)
2x2 DFN Package . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Junction Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
(°C/W)
70
(°C/W)
7
JA
JC
Recommended Operating Conditions
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
IN
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379
JA
for details.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications T = -40°C to +125°C, V = 2.7V to 5.5V, unless otherwise noted. Typical values are at T = +25°C. Boldface
A
IN
A
limits apply across the junction operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
INPUT SUPPLY
Undervoltage Lockout Threshold
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
V
V
Rising, no load
2.5
2.4
35
7
2.7
V
IN
UVLO
Falling, no load
2.2
V
Quiescent Supply Current
I
ISL80031A, no load at the output
ISL80030, no load at the output
ISL80030A, no load at the output
60
15
22
10
µA
mA
mA
µA
VIN
10
1.2
Shutdown Supply Current
OUTPUT REGULATION
Feedback Voltage
I
ISL80031, ISL80031A, V = 5.5V, EN = low
IN
SD
V
T = -40°C to +85°C
0.594
0.589
-120
0.600
0.606
0.606
350
V
V
FB
J
T = -40°C to +125°C
J
VFB Bias Current
Line Regulation
I
V
= 2.7V. T = -40°C to +125°C
50
nA
%/V
VFB
FB
IN
J
V
= V + 0.5V to 5.5V (minimal 2.7V)
-0.32
-0.05
0.28
O
Nominal = 3.6V
Soft-Start Ramp Time Cycle
PROTECTIONS
V
= 5.5V
0.39
1
1.36
ms
IN
Positive Peak Current Limit
Peak Skip Limit
I
3.6
4.5
5.4
A
PLIMIT
I
ISL80031, ISL80031A
= 3.6, V = 1.8V (See “Applications
450
mA
SKIP
V
IN
OUT
Information” on page 17 for details)
Zero Cross Threshold
Negative Current Limit
Thermal Shutdown
ISL80031, ISL80031A
-170
-2.6
-70
-2
30
-1
mA
A
I
NLIMIT
Temperature rising
Temperature falling
150
25
°C
°C
Thermal Shutdown Hysteresis
FN8766 Rev.2.00
Nov 16, 2017
Page 7 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Electrical Specifications T = -40°C to +125°C, V = 2.7V to 5.5V, unless otherwise noted. Typical values are at T = +25°C. Boldface
A
IN
A
limits apply across the junction operating temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
COMPENSATION
SYMBOL
RT
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
Error Amplifier Transconductance
Transresistance
40
µA/V
0.20
0.25
0.30
Ω
PHASE
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
PHASE Maximum Duty Cycle
PHASE Minimum On-Time
OSCILLATOR
V
V
= 5V, I = 200mA
70
60
mΩ
mΩ
IN
O
= 5V, I = 200mA
IN
O
100
60
ISL80030, ISL80030A
80
ns
Nominal Switching Frequency
f
ISL80030, ISL80031
850
1000
2000
1150
2300
kHz
kHz
SW
ISL80030A, ISL80031A
1700
PG
Output Low Voltage
Delay Time (Rising Edge)
PGOOD Delay Time (Falling Edge)
PG Pin Leakage Current
OVP PG Rising Threshold
OVP PG Hysteresis
UVP PG Rising Threshold
UVP PG Hysteresis
EN LOGIC
1mA sinking current
0.3
2
V
ms
µs
µA
%
0.5
1
5
PG = V
0.01
117
2
0.1
IN
110
80
125
%
85
2
90
%
%
Logic Input Low
0.4
1
V
V
Logic Input High
1.4
Logic Input Leakage Current
I
Pulled up to 5.5V
0.1
µA
EN
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN8766 Rev.2.00
Nov 16, 2017
Page 8 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves
100
90
80
70
60
50
40
100
93
87
80
V
= 1.2V
OUT
V
= 1.2V
OUT
V
= 1.5V
OUT
V
= 1.8V
V
= 1.5V
73
67
60
OUT
OUT
V
= 1.8V
OUT
V
= 2.5V
OUT
V
= 2.5V
OUT
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
LOAD (A)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD (ISL80031A)
FIGURE 5. EFFICIENCY vs LOAD (ISL80030A)
f
= 2MHz, V = 3.3V, PFM, T = +25°C
f
= 2MHz, V = 3.3V, PWM, T = +25°C
SW
IN
A
SW
IN
A
100
93
87
80
73
67
60
100
90
80
70
60
50
40
V
= 1.2V
OUT
V
= 1.5V
OUT
V
= 1.2V
OUT
V
= 1.8V
OUT
V
= 1.5V
OUT
V
= 1.8V
OUT
V
= 2.5V
OUT
V
= 2.5V
OUT
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
LOAD (A)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
LOAD (A)
3.0
FIGURE 6. EFFICIENCY vs LOAD (ISL80031)
FIGURE 7. EFFICIENCY vs LOAD (ISL80030)
f
= 1MHz, V = 3.3V, PFM, T = +25°C
f
= 1MHz, V = 3.3V, PWM, T = +25°C
SW
IN
A
SW
IN
A
100
93
87
80
73
67
60
100
93
80
67
53
40
V
= 3.3V
OUT
V
= 3.3V
OUT
V
= 1.2V
OUT
V
= 1.2V
OUT
V
= 1.5V
V
OUT
V
= 1.5V
= 1.8V
OUT
OUT
V
= 1.8V
OUT
V
= 2.5V
OUT
V
= 2.5V
OUT
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
LOAD (A)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
LOAD (A)
FIGURE 9. EFFICIENCY vs LOAD (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
FIGURE 8. EFFICIENCY vs LOAD (ISL80031A)
f
f
= 2MHz, V = 5V, PFM, T = +25°C
SW
IN
A
SW
IN
A
FN8766 Rev.2.00
Nov 16, 2017
Page 9 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves (Continued)
100
100
90
80
70
60
50
40
V
= 3.3V
OUT
V
= 3.3V
OUT
93
87
80
73
67
60
V
= 1.2V
OUT
V
= 1.5V
OUT
V
= 1.8V
V
= 1.2V
OUT
OUT
V
= 1.5V
OUT
V
= 1.8V
OUT
V
= 2.5V
OUT
V
= 2.5V
OUT
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
LOAD (A)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
LOAD (A)
FIGURE 11. EFFICIENCY vs LOAD (ISL80030)
FIGURE 10. EFFICIENCY vs LOAD (ISL80031)
= 1MHz, V = 5V, PFM, T = +25°C
f
= 1MHz, V = 5V, PWM, T = +25°C
f
SW
IN
A
SW
IN
A
1.876
1.872
1.867
1.863
1.859
1.854
1.850
1.828
1.827
1.826
1.825
1.824
1.823
1.822
3.3V PWM
IN
5V PFM
IN
3.3V PFM
IN
5V PWM
IN
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
OUTPUT LOAD (A)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
OUTPUT LOAD (A)
FIGURE 12. V
REGULATION vs LOAD (ISL80031)
= 1MHz, V = 1.8V, PFM, T = +25°C
OUT
FIGURE 13. V
OUT
REGULATION vs LOAD (ISL80030)
= 1.8V, PWM, T = +25°C
OUT
f
f
= 1MHz, V
SW
A
SW
OUT
A
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
OUT
V
1V/DIV
OUT
VEN 5V/DIV
PG 5V/DIV
VEN 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 15. START-UP AT NO LOAD (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
FIGURE 14. START-UP AT NO LOAD (ISL80031A)
= 2MHz, V = 5V, PFM, T = +25°C
f
f
SW
IN
A
SW
IN
A
FN8766 Rev.2.00
Nov 16, 2017
Page 10 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
V
1V/DIV
OUT
OUT
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 16. SHUTDOWN AT NO LOAD (ISL80031A)
= 2MHz, V = 5V, PFM, T = +25°C
FIGURE 17. SHUTDOWN AT NO LOAD (ISL80030A)
f
f
= 2MHz, V = 5V, PWM, T = +25°C
SW
IN
A
SW
IN
A
VEN 5V/DIV
VEN 5V/DIV
V
1V/DIV
OUT
V
1V/DIV
OUT
I
2A/DIV
L
I
2A/DIV
L
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 19. SHUTDOWN AT 3A LOAD (ISL80030A)
FIGURE 18. START-UP AT 3A LOAD (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
f
= 2MHz, V = 5V, PWM, T = +25°C
f
SW
IN
A
SW
IN
A
VEN 5V/DIV
VEN 5V/DIV
V
1V/DIV
OUT
V
1V/DIV
OUT
I
2A/DIV
L
I
2A/DIV
L
PG 5V/DIV
PG 5V/DIV
500µs/DIV
1ms/DIV
FIGURE 21. SHUTDOWN AT 3A LOAD (ISL80031A)
= 2MHz, V = 5V, PFM, T = +25°C
FIGURE 20. START-UP AT 3A LOAD (ISL80031A)
= 2MHz, V = 5V, PFM, T = +25°C
f
f
SW
IN
A
SW
IN
A
FN8766 Rev.2.00
Nov 16, 2017
Page 11 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves (Continued)
V
V
I
5V/DIV
V
V
5V/DIV
IN
IN
1V/DIV
1V/DIV
OUT
OUT
2A/DIV
I
2A/DIV
L
L
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 22. START-UP V AT 3A LOAD (ISL80031A)
IN
FIGURE 23. START-UP V AT 3A LOAD (ISL80030A)
IN
f
= 2MHz, V = 5V, PFM, T = +25°C
f
= 2MHz, V = 5V, PWM, T = +25°C
SW
IN
A
SW
IN
A
PHASE 5V/DIV
PHASE 5V/DIV
V
V
1V/DIV
OUT
V
V
1V/DIV
OUT
5V/DIV
IN
5V/DIV
IN
PG 5V/DIV
PG 5V/DIV
100µs/DIV
20µs/DIV
FIGURE 25. SHUTDOWN V AT 3A LOAD (ISL80030A)
IN
FIGURE 24. SHUTDOWN V AT 3A LOAD (ISL80031A)
IN
f
= 2MHz, V = 5V, PWM, T = +25°C
f
= 2MHz, V = 5V, PFM, T = +25°C
SW
IN
A
SW
IN
A
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
OUT
V
1V/DIV
OUT
V
5V/DIV
IN
V
5V/DIV
IN
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 27. START-UP V AT NO LOAD (ISL80030A)
IN
FIGURE 26. START-UP V AT NO LOAD (ISL80031A)
IN
f
= 2MHz, V = 5V, PWM, T = +25°C
f
= 2MHz, V = 5V, PFM, T = +25°C
SW
IN
A
SW
IN
A
FN8766 Rev.2.00
Nov 16, 2017
Page 12 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
OUT
V
V
1V/DIV
OUT
5V/DIV
IN
V
5V/DIV
IN
PG 5V/DIV
PG 5V/DIV
2ms/DIV
5ms/DIV
FIGURE 29. SHUTDOWN V AT NO LOAD (ISL80030A)
IN
FIGURE 28. SHUTDOWN V AT NO LOAD (ISL80031A)
IN
f
= 2MHz, V = 5V, PWM, T = +25°C
f
= 2MHz, V = 5V, PFM, T = +25°C
SW
IN
A
SW
IN
A
PHASE 1V/DIV
PHASE 1V/DIV
10ns/DIV
10ns/DIV
FIGURE 31. JITTER AT FULL LOAD (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
FIGURE 30. JITTER AT NO LOAD (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
f
f
SW
IN
A
SW
IN
A
PHASE 5V/DIV
PHASE 5V/DIV
V
20mV/DIV
OUT
V
10mV/DIV
OUT
I
0.5A/DIV
L
I
0.5A/DIV
L
50ms/DIV
200ns/DIV
FIGURE 32. STEADY STATE AT NO LOAD (ISL80031A)
= 2MHz, V = 5V, PFM, T = +25°C
FIGURE 33. STEADY STATE AT NO LOAD (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
f
f
SW
IN
A
SW
IN
A
FN8766 Rev.2.00
Nov 16, 2017
Page 13 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
V
10mV/DIV
OUT
V
10mV/DIV
OUT
I
2A/DIV
L
I
2A/DIV
L
500ns/DIV
500ns/DIV
FIGURE 34. STEADY STATE AT 3A LOAD (ISL80031A)
= 2MHz, V = 5V, PFM, T = +25°C
FIGURE 35. STEADY STATE AT 3A LOAD (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
f
f
SW
SW
IN
A
IN
A
V
RIPPLE 50mV/DIV
OUT
V
RIPPLE 50mV/DIV
OUT
I
1A/DIV
L
I
1A/DIV
L
200µs/DIV
200µs/DIV
FIGURE 36. LOAD TRANSIENT (ISL80031A)
= 2MHz, V = 5V, PFM, T = +25°C
FIGURE 37. LOAD TRANSIENT (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
f
f
SW
SW
IN
A
IN
A
PHASE 5V/DIV
V
1V/DIV
OUT
I
2A/DIV
L
I
2A/DIV
L
V
1V/DIV
OUT
PG 5V/DIV
PG 5V/DIV
5µs/DIV
500µs/DIV
FIGURE 39. OVERCURRENT PROTECTION (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
FIGURE 38. OUTPUT SHORT-CIRCUIT (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
f
f
SW
IN
A
SW
IN
A
FN8766 Rev.2.00
Nov 16, 2017
Page 14 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Typical Performance Curves (Continued)
PHASE 5V/DIV
V
0.5V/DIV
OUT
I
2A/DIV
L
PG 2V/DIV
V
2V/DIV
OUT
PG 5V/DIV
1ms/DIV
200µs/DIV
FIGURE 41. OVER-TEMPERATURE PROTECTION
= 2MHz, V = 5V, PWM, T = +150°C
FIGURE 40. OVERVOLTAGE PROTECTION (ISL80030A)
= 2MHz, V = 5V, PWM, T = +25°C
f
f
SW
IN
A
SW
IN
A
Theory of Operation
V
EAMP
The device is a step-down switching regulator optimized for battery
powered applications. It operates at a high switching frequency
(1MHz or 2MHz), which enables the use of smaller inductors
resulting in a small form factor, while also providing excellent
efficiency. The quiescent current is typically only 1.2µA when the
regulator is shut down.
V
CSA
DUTY
CYCLE
I
L
PWM Control Scheme
The ISL80030 and ISL80030A employ the current-mode
V
OUT
Pulse-Width Modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting (see “Functional Block
Diagram” on page 5). The current loop consists of the oscillator,
PWM comparator, current sensing circuit, and the slope
FIGURE 42. PWM OPERATION WAVEFORMS
compensation for current loop stability. The slope compensation is
900mV/Ts, which changes with frequency. The gain for the current
sensing circuit is typically 250mV/A. The control reference for the
current loop comes from the error amplifier's (EAMP) output.
The reference voltage is 0.6V, which is used by feedback to
adjust the output of the error amplifier, V . The error
amplifier is a transconductance amplifier that converts the
voltage error signal to a current output. The voltage loop is
internally compensated with the 27pF and 200kΩ RC network.
The maximum EAMP voltage output is precisely clamped to 1.6V.
EAMP
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-channel MOSFET. The N-FET stays on until
the end of the PWM cycle. Figure 42 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate
the sum of the slope compensation ramp and the current-sense
amplifier’s CSA output.
PFM Operation
The ISL80031 and ISL80031A employ a pulse-skipping mode to
minimize the switching loss at light load by reducing the
switching frequency. Figure 43 on page 16 illustrates the
skip-mode operation. A zero-cross sensing circuit shown in
Figure 43 monitors the N-FET current for zero crossing. When
16 consecutive cycles of the inductor current crossing zero are
detected, the regulator enters the skip mode. During the eight
detecting cycles, the current in the inductor is allowed to become
negative. The counter is reset to zero when the current in any
cycle does not cross zero.
FN8766 Rev.2.00
Nov 16, 2017
Page 15 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
PWM
PFM
PWM
CLOCK
16 CYCLES
PFM CURRENT LIMIT
LOAD CURRENT
I
L
0
NOMINAL +1.5%
V
OUT
NOMINAL -1.5%
NOMINAL
FIGURE 43. PFM MODE OPERATION WAVEFORMS
When the device enters skip mode, the SKIP comparator starts
controlling pulse modulation as shown in the “Functional Block
Diagram” on page 5. Each pulse cycle is still synchronized by the
PWM clock. The P-FET is turned on at the clock's rising edge and
turned off when the output is higher than 1.5% of the nominal
regulation or when its current reaches the peak skip current limit
value. Then, the inductor current discharges to 0A and stays at
zero. The internal clock is disabled. The output voltage reduces
gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal voltage,
the P-FET will be turned on again at the rising edge of the internal
clock as it repeats the previous operations.
Negative Current Protection
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the low-side N-FET, as
shown in the “Functional Block Diagram” on page 5. When the
valley point of the inductor current reaches -2A for two consecutive
cycles, both P-FET and N-FET shut off. The 100Ω in parallel to the
N-FET will activate discharging the output into regulation. The
control will begin to switch when output is within regulation. The
regulator will be in PFM for 20µs before switching to PWM if
necessary.
PG
PG is an output of a window comparator that continuously monitors
the buck regulator output voltage. PG is actively held low when EN is
low and during the buck regulator soft-start period. After a 1ms
delay of the soft-start period, PG becomes high impedance as long
as the output voltage is within nominal regulation voltage set by
VFB. When VFB drops 15% below or raises 15% above the nominal
regulation voltage, the device pulls PG low. Any fault condition forces
PG low until the fault condition is cleared by attempts to soft-start.
There is an internal 5MΩ pull-up resistor to fit most applications. An
external resistor can be added from PG to VIN for more pull-up
strength.
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in the “Functional
Block Diagram” on page 5. The current sensing circuit has a gain
of 300mV/A, from the P-FET current to the CSA output. When the
CSA output reaches a threshold, the OCP comparator is tripped to
turn off the P-FET immediately. The overcurrent function protects
the switching converter from a shorted output by monitoring the
current flowing through the upper MOSFET.
Upon detection of overcurrent condition, the upper MOSFET will
be immediately turned off and will not be turned on again until
the next switching cycle. If the overcurrent condition goes away,
the output will resume back into the regulation point.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the regulator is disabled.
Short-Circuit Protection
Enable, Disable and Soft-Start Up
The Short-Circuit Protection (SCP) comparator monitors the VFB
pin voltage for output short-circuit protection. When the VFB is
lower than 0.3V, the SCP comparator forces the PWM oscillator
frequency to drop to 1/3 of the normal operation value. This
comparator is effective during start-up or an output short-circuit
event.
After the VIN pin exceeds its rising POR trip point (nominal 2.5V),
the device begins operation. If the EN pin is held low externally,
nothing happens until this pin is released. When the EN is
released and above the logic threshold, the internal default
soft-start time is 1ms.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN UVLO is set,
the outputs discharge to GND through an internal 100Ω switch.
FN8766 Rev.2.00
Nov 16, 2017
Page 16 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
100% Duty Cycle
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
The device features 100% duty cycle operation to maximize the
battery life. When the battery voltage drops below a level at
which the device can no longer maintain the regulation at the
output, the regulator completely turns on the P-FET. The
maximum dropout voltage under the 100% duty cycle operation
is the product of the load current and the ON-resistance of the
P-FET.
V
= 5V, OLFM
IN
Thermal Shutdown
The device has built-in thermal protection. When the internal
temperature reaches +150°C, the regulator is completely shut
down. As the temperature drops to +125°C, the device resumes
operation by stepping through the soft-start.
50
60
70
80
90
100
110
120
130
TEMPERATURE (°C)
Power Derating Characteristics
FIGURE 44. DERATING CURVE vs TEMPERATURE
To prevent the device from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 2:
Applications Information
Output Inductor and Capacitor Selection
(EQ. 2)
T
= PD
JA
To consider steady state and transient operations, the device
typically requires a 1µH output inductor. Higher or lower inductor
values can be used to optimize the total converter system
performance. For example, for higher output voltage 3.3V
applications, to decrease the inductor ripple current and output
voltage ripple, the output inductor value can be increased. It is
recommended to set the inductor ripple current to approximately
30% of the maximum output current for optimized performance.
The inductor ripple current can be expressed as shown in
Equation 4:
RISE
where PD is the power dissipated by the regulator and θ is the
JA
thermal resistance from the junction of the die to the ambient
temperature. The junction temperature, T , is given by
J
Equation 3:
(EQ. 3)
T = T + T
RISE
j
A
where T is the ambient temperature. For the DFN package, the
A
θ
is +70°C/W.
JA
V
O
---------
V
1 –
O
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C when considering
the thermal design.
(EQ. 4)
V
IN
--------------------------------------
I =
L f
SW
The inductor’s saturation current rating needs to be larger than
the peak current.
The device delivers full current at ambient temperatures up to
+85°C; if the thermal impedance from the thermal pad
maintains the junction temperature below the thermal shutdown
level, depending on the input voltage/output voltage
combination and the switching frequency. The device power
dissipation must be reduced to maintain the junction
temperature at or below the thermal shutdown level. Figure 44
illustrates the approximate output current derating versus
ambient temperature for the ISL80030EVAL1Z board.
The device uses an internal compensation network and the
output capacitor value is dependent on the output voltage. An
X5R or X7R ceramic capacitor is recommended.
Output Voltage Selection
The output voltage of the regulator can be programmed from an
external resistor divider that scales the output voltage relative to the
internal reference voltage and feeds it back to the inverting input of
the error amplifier.
The output voltage programming resistor, R , will depend on the
1
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 10kΩ and 100kΩas shown in Equation 5.
V
O
(EQ. 5)
------------
R
= R
– 1
1
2
VFB
If the output voltage desired is 0.6V, then R is left unpopulated
2
and R is shorted. There is a leakage current from VIN to LX. It is
1
recommended to preload the output with 10µA minimum. For
better performance, add 22pF in parallel with R
1
FN8766 Rev.2.00
Nov 16, 2017
Page 17 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
To determine transient response needs, a good starting point is
to determine the allowable overshoot in V if the load is
Input Capacitor Selection
OUT
suddenly removed. In this case, energy stored in the inductor will
be transferred to C causing its voltage to rise. After
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. At least two 22µF X5R or X7R ceramic capacitors are
a good starting point for the input capacitor selection.
OUT
calculating capacitance required for both ripple and transient
needs, choose the larger of the calculated values. The following
equation determines the required output capacitor value to
achieve a desired overshoot relative to the regulated voltage.
Output Capacitor Selection
2
I
L
*
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are two critical
factors when considering output capacitance choice. The current
mode control loop allows for the usage of low ESR ceramic
capacitors and thus smaller board layout. Electrolytic and
polymer capacitors can also be used.
OUT
--------------------------------------------------------------------------------------------
=
C
(EQ. 8)
OUT
2
2
V
V
V
– 1
*
OUT
OUTMAX
OUT
where V is the relative maximum overshoot
/V
OUTMAX OUT
allowed during the removal of the load. For an overshoot of 5%,
Equation 9 becomes as follows:
2
Although ceramic capacitors offer excellent overall performance
and reliability, the actual in-circuit capacitance must be
considered. Ceramic capacitors are rated using large peak-to-
peak voltage swings and with no DC bias. In the DC/DC converter
application, these conditions do not reflect reality. As a result, the
actual capacitance may be considerably lower than the
advertised value. Consult the manufacturer’s datasheet to
determine the actual in-application capacitance. Most
manufacturers publish capacitance vs DC bias so this effect can
be easily accommodated. The effects of AC voltage are not
frequently published, but an assumption of ~20% further
reduction will generally suffice. The result of these
I
L
*
OUT
-----------------------------------------------------
=
C
OUT
(EQ. 9)
2
2
V
1.05 – 1
*
OUT
Layout Considerations
PCB layout is a very important converter design step to make
sure the designed converter works well. The power loop is
composed of the output inductor Ls, the output capacitor C
,
OUT
the PHASE’s pins, and the PGND pin. Make the power loop as
small as possible and the connecting traces among them direct,
short, and wide. The switching node of the converter, the PHASE
pins, and the traces connected to the node are very noisy, so
keep the voltage feedback trace away from these noisy traces.
The input capacitor should be placed as closely as possible to the
VIN pin and the ground of the input and output capacitors should
be connected as closely as possible. The heat of the IC is mainly
dissipated through the thermal pad. Maximizing the copper area
connected to the thermal pad is preferable. In addition, a solid
ground plane is helpful for better EMI performance. It is
recommended to add at least four vias ground connection within
the pad for the best thermal relief.
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
Use the following equations to calculate the required
capacitance to meet a desired ripple voltage level. Additional
capacitance can be used.
For the ceramic capacitors (low ESR):
I
------------------------------------
(EQ. 6)
V
=
OUTripple
C
OUT
8 f
SW
where I is the inductor’s peak-to-peak ripple current, f
SW
is the
switching frequency and C
is the output capacitor.
OUT
If using electrolytic capacitors:
V
= I*ESR
(EQ. 7)
OUTripple
FN8766 Rev.2.00
Nov 16, 2017
Page 18 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
Nov 16, 2017
FN8766.2 Added Related Literature section on page 1.
Added the ISL80030ADEMO1Z and ISL80031ADEMO1Z to Ordering Information on page 6.
Added test conditions, minimum value, and maximum value for the Soft-Start Ramp Time Cycle specification on
page 7.
Applied new header/footer.
Dec 24, 2015
Jul 20, 2015
FN8766.1 Added Related Literature section on page 1.
Added Demonstration boards to the ordering information on page 6.
Feedback Voltage parameter on page 7.
-Added test conditions “TJ = -40°C to +85°C” to the first line and unbolded the min and max specs.
-The second line (TJ = -40°C to +125°C) bolded the min and max specs.
VFB Bias Current parameter on page 7, bolded the min and max specs.
FN8766.0 Initial release
About Intersil
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For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
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FN8766 Rev.2.00
Nov 16, 2017
Page 19 of 20
ISL80030, ISL80030A, ISL80031, ISL80031A
Package Outline Drawing
For the most recent package outline drawing, see L8.2x2E.
L8.2x2E
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH E-PAD
Rev 0, 5/15
2.00
6
A
PIN #1 INDEX AREA
6
B
PIN 1
INDEX AREA
8
1
0.50
1.45±0.050
Exp.DAP
(4X)
0.15
0.25
( 8x0.30 )
0.10
C A B
M
TOP VIEW
0.80±0.050
Exp.DAP
BOTTOM VIEW
(8x0.20)
(8x0.30)
Package Outline
SEE DETAIL "X"
(6x0.50)
C
0.10
C
0.90 ±0.10
1.45
2.00
BASE PLANE
SEATING PLANE
0.08
C
SIDE VIEW
(8x0.25)
0.80
2.00
TYPICAL RECOMMENDED LAND PATTERN
0.2 REF
C
0.00 MIN.
0.05 MAX.
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8766 Rev.2.00
Nov 16, 2017
Page 20 of 20
相关型号：
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