ISL80101IRAJZ-T7 [RENESAS]
ADJUSTABLE POSITIVE LDO REGULATOR;
| 型号： | ISL80101IRAJZ-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | ADJUSTABLE POSITIVE LDO REGULATOR |
| 文件： | 总12页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
High Performance 1A LDO
ISL80101-ADJ
Features
The ISL80101-ADJ is a low voltage, high current, single output
LDO specified at 1A output current. This LDO operates from
input voltages from 2.2V to 6V, and is capable of providing
output voltages from 0.8V to 5V. The ISL80101-ADJ features
an adjustable output. For the fixed output version of the
ISL80101-ADJ, please refer to the ISL80101 datasheet.
• ±1.8% V
accuracy guaranteed over line, load and
T = -40°C to +125°C
OUT
J
• Very low 130mV dropout voltage at V
• Very fast transient response
• Programmable soft-starting
• Power-good output
= 2.5V
OUT
A submicron BiCMOS process is utilized for this product family
to deliver the best in class analog performance and overall
value. This CMOS LDO will consume significantly lower
quiescent current as a function of load compared to bipolar
LDOs, which translates into higher efficiency and packages
with smaller footprints. State of the art internal compensation
achieves a very fast load transient response. An external
capacitor on the soft-start pin provides an adjustable
soft-starting ramp. The ENABLE feature allows the part to be
placed into a low quiescent current shutdown mode. A
Power-good logic output signals a fault condition.
• Excellent 65dB PSRR
• Current limit protection
• Thermal shutdown function
• Available in a 10 Ld DFN package
• Pb-Free (RoHS compliant)
Applications
• DSP, FPGA and µP core power supplies
• Noise-sensitive instrumentation systems
Table 1 shows the differences between the ISL80101-ADJ and
others in its family:
• Post regulation of switched mode power supplies
• Industrial systems
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PROGRAMMABLE
I
ADJ OR FIXED
LIMIT
• Medical equipment
PART NUMBER
ISL80101-ADJ
ISL80101
I
(DEFAULT)
V
LIMIT
No
OUT
• Telecommunications and networking equipment
• Servers
1.75A
ADJ
No
1.75A
1.8V, 2.5V,
3.3V, 5.0V
• Hard disk drives (HD/HDD)
ISL80101A
ISL80121-5
Yes
Yes
1.62A
0.75A
ADJ
Related Literature
• AN1592, “ISL80101 High Performance 1A LDO Evaluation
Board User Guide”
5.0V
2.5V ± 10%
10µF
1.8V
140
120
100
80
1
10
9
V
V
V
V
IN
OUT
10µF
2
IN
OUT
C
C
OUT
IN
2.61k
82pF
R
C
2
PB
3
10k
R
100k
ADJ
ISL80101-ADJ
3
R
PG
1.00k
R
1
60
4
7
6
40
ENABLE
SS
PG
20
0
V
= 2.5V
OUT
0.01µF
GND
C
0
0.2
0.4
0.6
0.8
1.0
SS
5
OUTPUT CURRENT (A)
FIGURE 2. DROPOUT vs LOAD CURRENT
FIGURE 1. TYPICAL APPLICATION CIRCUIT
August 26, 2015
FN7834.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC. 2011, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL80101-ADJ
Block Diagram
V
IN
EN
PG
CONTROL
LOGIC
FET DRIVER
WITH CURRENT
LIMIT
-
EA
+
REFERENCE
+
SOFT-START
THERMAL
SENSOR
VOUT
SS
ADJ
+
-
PG
GND
Ordering Information
PART NUMBER
(Notes 3, 4)
PART
MARKING
V
VOLTAGE
(Note 2)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
OUT
PKG DWG. #
L10.3x3
ISL80101IRAJZ (Note 1)
ISL80101EVAL2Z
NOTES:
DZAB
Evaluation Board
ADJ
-40 to +125
10 Ld 3x3 DFN
1. Add “-T*” for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for ISL80101-ADJ. For more information on MSL please see techbrief
TB363.
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2
ISL80101-ADJ
Pin Configurations
ISL80101-ADJ
(10 LD 3x3 DFN)
TOP VIEW
V
V
V
V
1
2
3
4
5
10
9
OUT
OUT
IN
IN
ADJ
PG
NC
8
EPAD
7
ENABLE
SS
GND
6
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
V
Regulated output voltage. A X5R/X7R output capacitor is required for stability. See “External Capacitor
Requirements” on page 8 for more details.
OUT
3
4
ADJ
PG
This pin is connected to the feedback resistor divider and provides voltage feedback signals for the LDO to set the
output voltage. In addition, the PGOOD circuit uses this input to monitor the output voltage status.
This is an open-drain logic output used to indicate the status of the output voltage. Logic low indicates V
in regulation. Must be grounded if not used.
is not
OUT
5
6
GND
SS
Ground
External capacitor on this pin adjusts start-up ramp and controls inrush current.
7
ENABLE
NC
V
independent chip enable. TTL and CMOS compatible.
IN
8
No connection; Leave floating.
9, 10
V
Input supply; A minimum of 10µF X5R/X7R input capacitor is required for proper operation. See “External
Capacitor Requirements” on page 8 for more details.
IN
-
EPAD
EPAD at ground potential. It is recommended to solder the EPAD to the ground plane.
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ISL80101-ADJ
Absolute Maximum Ratings
Thermal Information
V
V
Relative to GND (Note 5). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Typical)
10 Ld DFN Package (Notes 6, 7) . . . . . . . .
JA (°C/W)
48
JC (°C/W)
IN
OUT
7
PG, ENABLE, ADJ, SS
Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
ESD Rating
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Human Body Model (Tested per JESD22 A114F) . . . . . . . . . . . . . . .2.5kV
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 2kV
Latch-up (Tested per JESD78C, Class 2, Level A) . . . . ±100mA at +125°C
Recommended Operating Conditions (Notes 8, 9)
Junction Temperature Range (TJ) (Note 8) . . . . . . . . . . . .-40°C to +125°C
V
V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
IN
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V
OUT
PG, ENABLE, ADJ, SS relative to GND . . . . . . . . . . . . . . . . . . . . . . . 0V to 6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
6. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
7. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
8. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions
define limits where specifications are guaranteed.
9. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current.
Electrical Specifications Unless otherwise noted, 2.2V < V < 6V, V
= 0.5V, T = +25°C. Applications must follow thermal guidelines
J
of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 8 and Tech Brief TB379.
IN
OUT
Boldface limits apply across the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
DC CHARACTERISTICS
SYMBOL
TEST CONDITIONS
(Note 10)
TYP
500
(Note 10)
UNITS
Feedback Pin (ADJ Option Only)
DC Input Line Regulation
V
V
V
+ 0.4V < V < 6V, V
IN OUT
= 2.5V, 0A < I < 1A
LOAD
491
-1
509
1
mV
%
ADJ
OUT
(V
OUT
low line -
+ 0.4V < V < 6V, V = 2.5V
IN OUT
OUT
V
high
OUT
line)/V
low
OUT
line
DC Output Load Regulation
(V
OUT
no load- 0A < I
< 1A, V
OUT
= 2.5V
-1
1
%
LOAD
V
high
OUT
load)/ V
no
OUT
load
Feedback Input Current
Ground Pin Current
V
= 0.5V
0.01
3
1
5
µA
mA
mA
µA
mV
A
ADJ
I
I
I
= 0A, V
+ 0.4V < V < 6V, V
IN
= 2.5V
= 2.5V
Q
LOAD
LOAD
OUT
OUT
OUT
= 1A, V
+ 0.4V < V < 6V, V
IN
5
7
OUT
Ground Pin Current in Shutdown
Dropout Voltage (Note 11)
Output Short Circuit Current
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
AC CHARACTERISTICS
I
ENABLE Pin = 0.2V, V = 6V
IN
0.2
130
1.75
160
30
12
212
SHDN
V
I
= 1A, V
= 2.5V
OUT
DO
LOAD
OCP
TSD
V
OUT
= 0V
°C
°C
TSDn
Input Supply Ripple Rejection
PSRR
f = 1kHz, I
LOAD
= 1A; V = 2.2V, V
IN OUT
= 1.8V
= 1.8V
58
65
53
dB
dB
f = 120Hz, I
LOAD
= 1A; V = 2.2V, V
IN OUT
Output Noise Voltage
I
= 1A, BW = 100Hz < f < 100kHz, V = 2.2V,
IN
µV
RMS
LOAD
V
= 1.8V
OUT
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ISL80101-ADJ
Electrical Specifications Unless otherwise noted, 2.2V < V < 6V, V
= 0.5V, T = +25°C. Applications must follow thermal guidelines
J
of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 8 and Tech Brief TB379.
IN
OUT
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
SYMBOL
TEST CONDITIONS
(Note 10)
TYP
(Note 10)
UNITS
0.5
10
0.8
80
1
V
Hysteresis
200
mV
µs
ENABLE Pin Turn-on Delay
ENABLE Pin Leakage Current
SOFT-START CHARACTERISTICS
SS Pin Currents (Note 12)
C
= 10µF, I
= 1A
LOAD
100
OUT
V
= 6V, ENABLE = 2.8V
1
µA
IN
IPD
V
= 3.5V, ENABLE = 0V, SS = 1V
0.5
1
1.3
mA
µA
IN
ICHG
-3.3
-2
-0.8
PG PIN CHARACTERISTICS
V
V
PG Flag Threshold
PG Flag Hysteresis
75
85
4
92
%V
OUT
OUT
%
OUT
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
V
V
= 3V, I
= 500µA
100
1
mV
µA
IN
SINK
= 6V, PG = 6V
IN
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
11. Dropout is defined as the difference in supply V and V when the supply produces a 2% drop in V from its nominal voltage.
IN OUT OUT
12. I is the internal pull down current that discharges the external SS capacitor on disable. I
is the current from the SS pin that charges the external
PD
CHG
SS capacitor during start-up.
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ISL80101-ADJ
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A.
IN
OUT
IN
OUT J L
200
1.8
1.2
V
= 2.5V
OUT
180
160
140
120
100
80
I
= 1.0A
OUT
0.6
0
I
= 0.5A
= 0.1A
OUT
-0.6
-1.2
-1.8
60
I
OUT
40
20
0
-50
-25
0
25
50
75
100
125
150
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 3. DROPOUT VOLTAGE vs TEMPERATURE
FIGURE 4. V
OUT
vs TEMPERATURE
1.8
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.2
0.6
0
+25°C
+125°C
+25°C
-40°C
-40°C
-0.6
-1.2
-1.8
+125°C
0
1
2
3
4
5
6
0.25
0
0.50
OUTPUT CURRENT (A)
0.75
1.00
SUPPLY VOLTAGE (V)
FIGURE 5. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
FIGURE 6. OUTPUT VOLTAGE vs OUTPUT CURRENT
3.5
5
3.0
2.5
2.0
1.5
1.0
0.5
0
4
3
2
1
0
+25°C
+125°C
-40°C
0
0.2
0.4
0.6
0.8
1.0
2
3
4
5
6
INPUT VOLTAGE (V)
LOAD CURRENT (A)
FIGURE 7. GROUND CURRENT vs LOAD CURRENT
FIGURE 8. GROUND CURRENT vs SUPPLY VOLTAGE
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ISL80101-ADJ
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A. (Continued)
IN
OUT
IN
OUT J L
3.5
2.5
2.0
1.5
1.0
0.5
0
V
= 6V
IN
VOLTAGE RAILS AT 50mV/DIV
V
= 2.2V
IN
V
= 3.7V, V
= 3.3V, C
= 10µF, C = 100pF
PB
IN
OUT
OUT
OUT
V
= 2.9V, V
= 2.5V, C
= 1.8V, C
= 1.5V, C
= 1.2V, C
= 10µF, C = 82pF
PB
IN
OUT
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
V
= 2.5V, V
= 10µF, C = 82pF
PB
FIGURE 10. CURRENT LIMIT vs TEMPERATURE (V
= 0V)
OUT
IN
OUT
OUT
V
= 2.5V, V
= 22µF, C = 150pF
PB
IN
OUT
OUT
OUT
OUT
ENABLE
(2V/DIV)
V
= 2.5V, V
= 47µF, C = 270pF
PB
IN
OUT
VOUT (1V/DIV)
V
= 2.5V, V
= 1.0V, C
= 47µF, C = 220pF
PB
IN
OUT
SS (1V/DIV)
PG (1V/DIV)
1A
1mA
(500µs/DIV)
di/dt = 4A/µs
TIME (20µs/DIV)
FIGURE 9. LOAD TRANSIENT RESPONSE
FIGURE 11. ENABLE START-UP (C = 2.2nF)
SS
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
C
= 10µF, C
= 82pF
OUT
PB
500mA
1A
C
= 100µF
OUT
0mA
100mA
C
= 82pF
PB
100
1k
10k
100k
1M
100
1k
10k
FREQUENCY (Hz)
100k
1M
FREQUENCY (Hz)
FIGURE 12. PSRR vs FREQUENCY FOR VARIOUS LOAD CURRENTS
FIGURE 13. PSRR vs FREQUENCY FOR VARIOUS OUTPUT
CAPACITORS (I = 100mA)
OUT
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ISL80101-ADJ
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A. (Continued)
IN
OUT
IN
OUT
J
L
10
V
= 3.8V
IN
V
(2V/DIV)
V
= 2.25V
IN
IN
1
0.1
0.01
V
V
C
= 2.2V
IN
= 1.8
= 10µF
OUT
OUT
V
(5mV/DIV)
OUT
I
= 1A
OUT
10
100
1k
10k
100k
FREQUENCY (Hz)
TIME (200µs/DIV)
FIGURE 14. LINE TRANSIENT RESPONSE
FIGURE 15. OUTPUT NOISE SPECTRAL DENSITY
C
x0.5
SS
2A
Applications Information
(EQ. 1)
-----------------------
=
T
start
Input Voltage Requirements
ISL80101-ADJ is capable of delivering output voltages from 0.8V
Equation 2 determines the C required for a specific start-up
SS
in-rush current, where V
is the output voltage, C is the
OUT
OUT
total capacitance on the output and I
current.
is the desired in-rush
(EQ. 2)
to 5.0V. Due to the nature of an LDO, V must be some margin
INRUSH
IN
higher than V
OUT
plus dropout at the maximum rated current of
the application if active filtering (PSRR) is expected from V to
V
xC
x2A
OUT
IN
OUT
---------------------------------------------------
=
C
V
. The very low dropout specification of this family of LDOs
SS
OUT
I
x0.5V
INRUSH
allows applications to design for a level of efficiency that can
accommodate profiles smaller than the TO220/263.
The external capacitor is always discharged to ground at the
beginning of start-up or enabling.
Enable Operation
The Enable turn-on threshold is typically 800mV with 80mV of
hysteresis. This pin must not be left floating, and should be tied
Output Voltage Selection
An external resistor divider, R and R as referenced in Figure 1
1
2
on page 1, is used to scale the output voltage relative to the
internal reference voltage. The output voltage can be
programmed to any level between 0.8V and 5V. The
to V if not used. A 1kΩ to 10kΩ pull-up resistor is required for
IN
applications that use open collector or open-drain outputs to
control the Enable pin. An internal pull-up or pull-down resistor to
change these values is available upon request. The Enable pin
recommended value for R is 500Ω to 5kΩ. R is then chosen to
2
1
satisfy Equation 3.
may be connected directly to V for applications with outputs
IN
that are always on.
R
2
(EQ. 3)
------
V
= 0.5V
+ 1
OUT
R
1
Power-Good Operation
PG is a logic output that indicates the status of V . The PG flag
is an open-drain NMOS that can sink up to 10mA. It requires an
External Capacitor Requirements
External capacitors are required for proper operation. Careful
attention must be paid to the layout guidelines and selection of
capacitor type and value to ensure optimal performance.
OUT
external pull-up resistor typically connected to the V
pin. The
PG pin should not be pulled up to a voltage source greater than
OUT
V . PG goes low when the output voltage drops below 84% of the
IN
nominal output voltage or if the part is disabled. The PG comparator
functions during current limit and thermal shutdown. For applications
not using this feature, connect this pin to ground.
OUTPUT CAPACITOR
The ISL80101-ADJ applies state-of-the-art internal compensation
to keep the selection of the output capacitor simple for the
customer. Stable operation over full temperature, V range,
IN
Soft-Start Operation
V
range and load extremes are guaranteed for all capacitor
OUT
types and values assuming the minimum recommended ceramic
The soft-start circuit controls the rate at which the output voltage
rises up to regulation at power-up or LDO enable. This start-up
ramp time can be set by adding an external capacitor from the
SS pin to ground. An internal 2µA current source charges up this
capacitor is used for local bypass on V . There is a growing
OUT
trend to use very-low ESR multilayer ceramic capacitors (MLCC)
because they can support fast load transients and also bypass
very high frequency noise from other sources. However, the
effective capacitance of MLCCs drops with applied voltage, age,
C
and the feedback reference voltage is clamped to the
SS
voltage across it. The start-up time is set by Equation 1.
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ISL80101-ADJ
and temperature. X7R and X5R dielectric ceramic capacitors are
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions” on page 4. The power
dissipation can be calculated by using Equation 5:
strongly recommended as they typically maintain a capacitance
range within ±20% of nominal voltage over full operating ratings
of temperature and voltage. This output capacitor must be
connected to the V
and GND pins of the LDO with PCB traces
OUT
(EQ. 5)
P
= V – V
I
+ V I
OUT IN GND
no longer than 0.5cm.
D
IN
OUT
Additional capacitors of any value in ceramic, POSCAP,
alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC
The maximum allowable junction temperature, T
maximum expected ambient temperature, T
A(MAX)
maximum allowable power dissipation, as shown in Equation 6:
and the
determine the
J(MAX)
output voltage tolerances. The use of C (see following section)
PB
(EQ. 6)
is recommended when only the minimum recommended
ceramic capacitor is used on the output. Please refer to Table 2
for these minimum conditions for various output voltages.
P
= T
– T
JMAX A JA
DMAX
is the junction-to-ambient thermal resistance.
JA
For safe operation, ensure that the power dissipation P ,
D
Phase Boost Capacitor
calculated from Equation 5, is less than the maximum allowable
power dissipation P
.
A small phase boost capacitor, C , can be placed across the top
D(MAX)
PB
resistor, R , in the feedback resistor divider network in order to
2
place a zero at:
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for effective heat dissipation. Figure 16 shows a curve
1
(EQ. 4)
---------------------------------
F
=
z
2xR xC
for the of the DFN package for different copper area sizes.
2
PB
JA
49
47
45
43
41
39
37
This zero increases the crossover frequency of the LDO and
provides additional phase resulting in faster load transient
response.
It is important to note that LDO stability and load transient
performance are affected by the type of output capacitor used.
For optimal result, empirical tuning of C is suggested for each
PB
specific application. It is recommended to not use C when high
PB
ESR capacitors such as Aluminum Electrolytic or Tantalum are
used on the output.
Table 2 shows the recommended minimum ceramic C
and
OUT
corresponding C , R and R for different output voltages.
PB
2
1
2
4
6
8
10 12 14 16 18 20 22 24
2
TABLE 2. RECOMMENDED C FOR DIFFERENT V
AND C
OUT
PB OUT
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
FIGURE 16. 3mmx3mm 10-PIN DFN ON 4-LAYER PCB WITH
V
R
R
C
C
PB
OUT
2
1
OUT
THERMAL VIAS vs EPAD-MOUNT COPPER LAND
JA
(V)
5.0
3.3
2.5
1.8
1.5
1.5
1.2
1.2
1.0
0.8
(kΩ)
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
(kΩ)
0.287
0.464
0.649
1.0
(µF)
10
10
10
10
10
22
22
47
47
47
(pF)
100
100
82
AREA ON PCB
Thermal Fault Protection
The power level and the thermal impedance of the package
(+45°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the
die temperature exceeds around +160°C, the output of the LDO will
shut down until the die temperature cools down to about +130°C.
82
1.3
68
1.3
150
120
270
220
220
Current Limit Protection
1.87
1.87
2.61
4.32
The ISL80101-ADJ LDO incorporates protection against overcurrent
due to any short or overload condition applied to the output pin. The
LDO performs as a constant current source when the output current
exceeds the current limit threshold noted in the “Electrical
Specifications” table on page 4. If the short or overload condition is
removed from V , then the output returns to normal voltage
OUT
INPUT CAPACITOR
regulation mode. In the event of an overload condition, the LDO may
begin to cycle on and off due to the die temperature exceeding
thermal fault condition and subsequently cooling down after the
power device is turned off.
For proper operation, a minimum capacitance of 10µF X5R/X7R
is required at the input. This ceramic input capacitor must be
connected to the V and GND pins of the LDO with PCB traces no
IN
longer than 0.5cm.
FN7834.3
August 26, 2015
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9
ISL80101-ADJ
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN7834.3
CHANGE
August 26, 2015
Added Related Literature to page 1.
Removed 1st bullet in Features on page 1 which read ±0.2% initial VOUT accuracy.
Changed 7th bullet in Features on page 1 from Excellent 58dB PSRR at 1kHz to Excellent 65dB PSRR
Updated the EA amp in the “Block Diagram” on page 2 by switching the + and - terminals. The positive
terminal is now connected to the ADJ pin. Removed “SENSE” pin Reference in diagram
“Pin Descriptions” on page 3 - Removed “minimum 10µF” from 1st sentence in V
OUT
description.
“Absolute Maximum Ratings” on page 4 - Removed Machine Model and changed latch up from +85°C to
+125°C.
Removed "SENSE" from “ADJ” in "‘Recommended Operating Conditions" on page 4.
Added “V =” to values in Figure 10 on page 7
IN
Changed Title of Figure 3 on page 6 from Dropout vs Temperature to Dropout Voltage vs Temperature
Changed Title in Figure 12 on page 7 from PSRR vs Frequency and Load Current to PSRR vs Frequency for
various load currents
Changed Title in Figure 13 on page 7 from PSRR vs Frequency and Output Capacitance (I
OUT
= 100mA) to
PSRR vs Frequency for various output capacitors (I
=100mA)
OUT
Electrical Spec changes:
Electrical Spec Table conditions on page 4 changed: V = V
IN OUT
+ 0.4V, V
OUT
= 1.8V, C = C = 2.2µF, to:
IN OUT
2.2V < V < 6V, V
= 0.5V
IN OUT
“Feedback Pin (ADJ Option Only)” Test Conditions changed from: 2.2V V 6V, 0A < I
IN LOAD
< 1A to: V +
OUT
0.4V < V < 6V, V
= 2.5V, 0A < I
< 1A
IN OUT
LOAD
"DC Input Line Regulation" on page 4 - changed symbol from V
/V to V
IN OUT
low line - V
OUT
IN OUT
high
+ 0.4V
OUT
line)/V
OUT
low line and added MIN -1. Test Conditions changed from: V
+ 0.5V < V < 5V to: V
OUT
< V < 6V, V
= 2.5V
IN OUT
“DC Output Load Regulation” on page 4 - changed symbol from V
/I
to V
no load-V
high load)/
< 1A, All voltage options to: 0A <
OUT
OUT
OUT
OUT
V
no load and added MAX 1. Test Conditions changed from: 0A < I
LOAD
OUT
I
< 1A, V = 2.5V
LOAD
OUT
Ground Pin Current Test Conditions changed from:
I
I
= 0A, 2.2V < V < 6V to: I
= 1A, 2.2V < V < 6V to: I
IN
= 0A, V
= 1A, V
+ 0.4V < V < 6V, V
+ 0.4V < V < 6V, V
IN
= 2.5V
= 2.5V
LOAD
LOAD
IN
LOAD
LOAD
OUT
OUT
IN
OUT
OUT
Output Short Circuit Current Test Conditions changed from: V
OUT
= 0V, 2.2V < V < 6V to: V = 0V
IN OUT
Thermal Shutdown Temperature, Thermal Shutdown Hysteresis, Turn-on Threshold and Hysteresis - Removed
Test Conditions
Removed “Rising Threshold” from ““Thermal Shutdown Hysteresis” on page 4 and from “Hysteresis” on page 5
“AC CHARACTERISTICS” on page 4 in PSRR - changed TYP from "72" to "65" for f = 120Hz. Added to Test
Conditions: V
OUT
= 1.8V
Output Noise Voltage in test conditions changed “10Hz” to “100Hz”, added V = 2.2V, V
IN
= 1.8V. Changed
OUT
TYP from “63” to “53”
“PG Flag Low Voltage” on page 5 changed in test conditions - V = 2.5V TO V = 3V
IN IN
“Turn-on Threshold” on page 5 changed MIN from: 0.3; to: 0.5
“Hysteresis” on page 5 changed in test conditions from: 2.2V < V
+ 0.4V < 6V, to: 2.2V < V < 6V
IN
OUT
“ENABLE Pin Leakage Current” on page 5 changed “Enable = 3V” to “Enable = 2.8V”
-------------------------------------------------
Updated Output Spectral Noise Density (Figure 15 on page 8) and changed I = 1A to I
L
= 1A
OUT
Updated POD L10.3x3 to most recent revision with changes as follows:
Added missing dimension 0.415 in Typical Recommended land pattern.
Shortened the e-pad rectangle on both the recommended land pattern and the package bottom view to line
up with the centers of the corner pins.
Tiebar Note 4 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
FN7834.3
August 26, 2015
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10
ISL80101-ADJ
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision. (Continued)
DATE
REVISION
FN7834.2
CHANGE
July 31, 2014
Updated the “Block Diagram” on page 2 reversed the + and - terminals on the EA amp. The inverting terminal
is now connected to the Adj/Sense pin.
Updated About Intersil verbiage to new standard.
Updated “Package Outline Drawing” on page 12 to latest revision.
August 3, 2011
FN7834.1
PAGE 1
1. Introduction, paragraph 1: Last two sentences removed, and replaced with: "The ISL80101-ADJ features
an adjustable output. For the fixed output version of the ISL80101, please refer to the ISL80101 datasheet."
2. Table 1: Replaced Table 1 with Table 1 from FN6931 to include the "ADJ or Fixed VOUT" column and
"ISL80101-ADJ" row.
3. Features: "Available in a 10 Ld DFN Package" has "TO220-5, TO263-5 and SOT223-5 to follow soon"
removed.
PAGE 5
1. Enable Pin Characteristics
a. "Enable Pin Turn-on Delay" changed to "ENABLE Pin Turn-on Delay"
b. "Enable Pin Leakage Current" changed to "ENABLE Pin Leakage Current"
PAGE 7
Figure 9: Timescale changed from "20µs/DIV" to "TIME (20µs/DIV)"
PAGE 8
2. Equation 1 - Parentheses deleted.
3. Equation 2 - Parentheses deleted.
March 31, 2011
FN7834.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7834.3
August 26, 2015
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11
ISL80101-ADJ
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 11, 3/15
5
3.00
A
B
PIN #1 INDEX AREA
1
2
5
PIN 1
INDEX AREA
10 x 0.23
(4X)
0.10
1.60
10x 0.35
TOP VIEW
BOTTOM VIEW
A B
C
M
0.10
(4X)
0.415
0.23
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
0.415
4
0.20 REF
0.05
C
1.60
2.85 TYP
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7834.3
August 26, 2015
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12
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