ISL80103IR18Z-T7A [RENESAS]
Fixed Positive LDO Regulator;
| 型号： | ISL80103IR18Z-T7A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Fixed Positive LDO Regulator 输出元件 调节器 |
| 文件： | 总16页 (文件大小：764K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
High Performance 2A and 3A Linear Regulators
ISL80102, ISL80103
The ISL80102 and ISL80103 are low voltage, high-current, single
output LDOs specified for 2A and 3A output current, respectively.
These LDOs operate from the input voltages of 2.2V to 6V and
are capable of providing the output voltages of 0.8V to 5.5V on
Features
• Stable with ceramic capacitors (Note 11)
• 2A and 3A output current ratings
• 2.2V to 6V input voltage range
the adjustable V
available in 1.8V, 2.5V. Other custom voltage options available
upon request.
versions. Fixed output voltage options are
• ±1.8% V
OUT
accuracy guaranteed over line, load and
OUT
T = -40°C to +125°C
J
• Very low 120mV dropout voltage at 3A (ISL80103)
For applications that demand in-rush current less than the
current limit, an external capacitor on the soft-start pin provides
adjustment. The ENABLE feature allows the part to be placed into
a low quiescent current shutdown mode. A submicron BiCMOS
process is utilized for this product family to deliver the
best-in-class analog performance and overall value.
• Fixed and adjustable V
OUT
versions
• Very fast transient response
• Excellent 62dB PSRR
• 49µV
output noise
RMS
• Power-good output
These CMOS (LDOs) will consume significantly lower quiescent
current as a function of load over bipolar LDOs, which translates
into higher efficiency and the ability to consider packages with
smaller footprints. The quiescent current has been modestly
compromised to enable a leading class fast load transient
response, and hence a lower total AC regulation band for an LDO
in this category.
• Adjustable in-rush current limiting
• Short-circuit and over-temperature protection
• Available in a 10 Ld DFN
Applications
• Servers
• Telecommunications and networking
• Medical equipment
• Instrumentation systems
• Routers and switchers
ISL80102, ISL80103
2.5V ±10%
1.8V ±1.8%
1
2
9
V
OUT
V
V
V
V
V
IN
OUT
IN
IN
C
10
OUT
C
IN
10µF
OUT
10µF
R
PG
100kΩ
ON
3
4
SENSE
PG
7
6
ENABLE
SS
OFF
PGOOD
*C
SS
GND
5
*CSS is optional, (see Note 12 on page 5).
FIGURE 1. TYPICAL APPLICATION FOR FIXED OUTPUT VOLTAGE VERSION
April 8, 2016
FN6660.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009-2013, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL80102, ISL80103
ISL80102, ISL80103
1.8V
2.5V ±10%
1
9
V
V
V
V
OUT
OUT
OUT
IN
V
V
IN
C
2
OUT
C
10
IN
IN
10µF
10µF
R
PG
100kΩ
R
1
10kΩ
4
PGOOD
PG
7
6
ENABLE
SS
EN
OPEN DRAIN COMPATIBLE
**C
PB
R
3
2.61kΩ
47pF
3
ADJ
*C
SS
GND
R
4
5
1.0kΩ
*CSS is optional, (see Note 12 on page 5).
**C is optional. See “Functional Description” on page 12 for more information.
PB
FIGURE 2. TYPICAL APPLICATION DIAGRAM FOR ADJUSTABLE OUTPUT VOLTAGE VERSION
Pin Descriptions
TABLE 1. COMPONENTS VALUE SELECTION
PIN
PIN
V
R
R
C
(pF)
C
OUT
OUT
TOP
BOTTOM
(Ω)
PB
NUMBER NAME
DESCRIPTION
(V)
5.0
3.3
2.5
(kΩ)
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
(µF)
10
10
10
10
22
22
47
47
47
1, 2
3
V
Output voltage pin
287
464
47
OUT
SENSE/ Remote voltage sense for internally fixed V
47
OUT
ADJ
PG
options. ADJ pin for externally set V .
OUT
649
47
4
V
V
in regulation signal. Logic low defines when
is not in regulation. Must be grounded if not
OUT
OUT
*
1.8
1.8
1.0k
1.0k
1.3k
1.87k
2.61k
4.32k
47
*
used.
82
5
6
GND
SS
GND pin
1.5
1.2
1.0
0.8
82
External cap adjusts in-rush current. Leave this pin
open if not used.
150
150
150
7
8
ENABLE
DNC
V
independent chip enable. TTL and CMOS
IN
compatible.
NOTE: *Either option could be used depending on cost/performance
requirements
Do not connect this pin to ground or supply. Leave
floating.
9, 10
V
Input supply pin
IN
Pin Configuration
EPAD EPAD must be connected to copper plane with as
many vias as possible for proper electrical and
optimal thermal performance.
ISL80102, ISL80103
(10 LD 3x3 DFN)
TOP VIEW
V
V
V
V
1
2
3
4
5
10
9
OUT
IN
IN
OUT
SENSE/ADJ
PG
DNC
8
EPAD
7
ENABLE
SS
GND
6
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ISL80102, ISL80103
Block Diagram
V
V
IN
R
5
IL/10,000
M4
10µA
10µA
M5
M3
M1
POWER PMOS
IL
OUT
+
-
R
R
8
9
M6
R
1
R
EN
EN
SENSE
7
-
500mV
+
R
2
R
4
EN
ADJ
PG
+
EN
-
ENABLE
SS
M7
M8
-
+
-
M2
500mV
+
V TO I
+
-
*R
485mV
3
EN
GND
*R is open for ADJ versions.
3
Ordering Information
PART NUMBER
(Notes 3, 4)
PART
MARKING VOLTAGE
V
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant) DWG. #
PKG
OUT
ISL80102IRAJZ (Note 1)
ISL80102IR18Z (Note 2)
DZJA
ADJ
-40 to +125 10 Ld 3x3 DFN
-40 to +125 10 Ld 3x3 DFN
L10.3x3
L10.3x3
DZNA
1.8V
(No longer available, recommended replacement: ISL80102IRAJZ)
ISL80102IR25Z (Note 2)
DZPA
2.5V
-40 to +125 10 Ld 3x3 DFN
L10.3x3
(No longer available, recommended replacement: ISL80102IRAJZ)
ISL80103IRAJZ (Note 1)
DZAA
DZEA
ADJ
-40 to +125 10 Ld 3x3 DFN
-40 to +125 10 Ld 3x3 DFN
L10.3x3
L10.3x3
ISL80103IR18Z (Note 2)
1.8V
(No longer available, recommended replacement: ISL80103IRAJZ)
ISL80103IR25Z (Note 2)
DZFA
2.5V
-40 to +125 10 Ld 3x3 DFN
L10.3x3
(No longer available, recommended replacement: ISL80103IRAJZ)
ISL80102EVAL2Z
ISL80103EVAL2Z
NOTES:
Evaluation Board
Evaluation Board
1. Add “-T” suffix for 6k unit, “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel
specifications.
2. Add “-T” suffix for 6k unit or “-TK” suffix for 1k unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL80102, ISL80103. For more information on MSL please see tech brief
TB363.
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ISL80102, ISL80103
Absolute Maximum Ratings (Note 7)
Thermal Information
V
V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Typical)
10 Ld 3x3 DFN Package (Notes 5, 6). . . . .
JA (°C/W)
45
JC (°C/W)
IN
OUT
4
PG, ENABLE, SENSE/ADJ, SS, Relative to GND. . . . . . . . . . . -0.3V to +6.5V
ESD Rating
Human Body Model (Tested per JESD22 A114F) . . . . . . . . . . . . . . .2.2kV
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 1kV
Latch-up (Tested per JESD78C, Class 2, Level A) . . . . . ±100mA at +85°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions (Note 8)
Junction Temperature Range (T ) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
J
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
V
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .800mV to 5.5V
OUT
PG, ENABLE, SENSE/ADJ, SS Relative to GND . . . . . . . . . . . . . . . . 0V to 6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
6. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
8. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current.
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions:
2.2V < V < 6V, V
IN OUT
= 0.5V, T = +25°C, I = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
LOAD
J
temperature. Please refer to “Functional Description” on page 12 and Tech Brief TB379. Boldface limits apply across the operating temperature range,
-40°C to +125°C. Pulse load techniques used by ATE to ensure T = T defines established limits.
J
A
MIN
MAX
PARAMETER
DC CHARACTERISTICS
SYMBOL
TEST CONDITIONS
(Note 9) TYP (Note 9) UNITS
DC Output Voltage Accuracy
V
V
options: 1.8V.
0.5
0.5
%
%
%
%
OUT
OUT
2.2V < V < 6V; I
= 0A
LOAD
IN
LOAD
options: 1.8V.
V
-1.8
-1.8
1.8
OUT
2.2V < V < 6V; 0A < I
< 3A
IN
V
options: 2.5V
OUT
6V < V < 6V; I
= 0A
LOAD
IN LOAD
V
options: 2.5V
-1.8
OUT
6V < V < 6V; 0A < I
< full load
IN
Feedback Pin (ADJ Version)
DC Input Line Regulation
V
0A < I
< full load
491
-0.4
-0.8
500
0.1
0.1
509
0.4
0.8
mV
%
ADJ
LOAD
2.2V < V < 3.6V, V
OUT
(V
(V
Low Line - V
High Line)/
= 1.8V
= 2.5V
OUT
OUT
OUT
IN
2.9V < V < 6V, V
IN
%
OUT
V
Low Line
OUT
DC Output Load Regulation
No Load - V
ISL80103. 0A < I
< 3A,
-0.8
-0.2
0.8
%
OUT
LOAD
High Load)/
No Load
2.9V < V < 6V; V
= 2.5V for adjustable version.
IN OUT
V
V
= 1.8V and 2.5V for fixed version.
OUT
OUT
ISL80102. 0A < I
< 2A
-0.6
-0.2
0.6
%
LOAD
2.9V < V < 6V; V
= 2.5V for adjustable version.
IN OUT
V
= 1.8V and 2.5V for fixed version.
OUT
Feedback Input Current
Ground Pin Current
V
= 0.5V
0.01
7.5
1
9
µA
ADJ
I
I
= 0A, V
OUT
+ 0.4V < V < 6V for all options.
IN
mA
Q
LOAD
V
= 2.5V for adjustable option.
OUT
I
= 3A, V
OUT
+ 0.4V < V < 6V for all options.
IN
8.5
12
mA
LOAD
V
= 2.5V for adjustable option.
OUT
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ISL80102, ISL80103
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions:
2.2V < V < 6V, V
IN OUT
= 0.5V, T = +25°C, I = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
LOAD
J
temperature. Please refer to “Functional Description” on page 12 and Tech Brief TB379. Boldface limits apply across the operating temperature range,
-40°C to +125°C. Pulse load techniques used by ATE to ensure T = T defines established limits. (Continued)
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 9) TYP (Note 9) UNITS
Ground Pin Current in Shutdown
I
EN = 0V, V = 5V
0.4
3.3
120
81
µA
µA
mV
mV
mV
mV
A
SHDN
IN
EN = 0V, V = 6V
16
IN
Dropout Voltage (Note 10)
V
ISL80103, I
ISL80102, I
ISL80103, I
ISL80102, I
= 3A, V
= 2A, V
= 3A, V
= 2A, V
= 0V
= 2.5V
= 2.5V
= 5.5V
= 5.5V
185
125
244
121
DO
LOAD
LOAD
LOAD
LOAD
OUT
OUT
OUT
OUT
120
60
Output Short Circuit Current
(3A Version)
ISC
ISL80103, V
5.0
OUT
Output Short Circuit Current
(2A Version)
ISL80102, V
= 0V
2.8
A
OUT
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
AC CHARACTERISTICS
TSD
160
15
°C
°C
TSDn
Input Supply Ripple Rejection
PSRR
f = 1kHz, I
LOAD
= 1A; V = 2.2V
IN
55
62
49
dB
dB
f = 120Hz, I
= 1A; V = 2.2V
IN
LOAD
Output Noise Voltage
V
= 2.2V, V
= 1.8V, I
LOAD
= 3A,
µV
RMS
IN
OUT
BW = 100Hz < f < 100kHz
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
V
2.9V < V < 6V for 2.5V for fixed output option.
IN
0.616
0.463
0.8
0.6
0.95
V
V
EN(HIGH)
2.2V < V < 6V for adjustable and 1.8V
IN
Turn-off Threshold
Hysteresis
V
2.9V < V < 6V for 2.5V fixed output option.
IN
EN(LOW)
2.2V < V < 6V for adjustable and 1.8V
IN
V
2.9V < V < 6V for 2.5V fixed output option.
IN
135
150
mV
EN(HYS)
2.2V < V < 6V for adjustable and 1.8V
IN
Enable Pin Turn-on Delay
Enable Pin Leakage Current
SOFT-START CHARACTERISTICS
Reset Pull-Down resistance
Soft-Start Charge Current
PG PIN CHARACTERISTICS
t
C
= 10µF, I
= 1A
µs
EN
OUT
LOAD
V
= 6V, EN = 3V
1
µA
IN
RPD
323
-4.5
Ω
ICHG
-7
-2
µA
V
V
PG Flag Threshold
PG Flag Hysteresis
75
84
4
92
%V
OUT
OUT
%
OUT
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
I
= 500µA
47
100
1
mV
µA
SINK
V
= 6V, PG = 6V
0.05
IN
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
10. Dropout is defined by the difference in supply V and V when the supply produces a 2% drop in V from its nominal value.
IN OUT OUT
11. Minimum cap of 10µF X5R/X7R on V and V
IN OUT
required for stability.
12. If the current limit for in-rush current is acceptable in application, do not use this feature (leave SS pin open). Used only when large bulk capacitance
required on V for application.
OUT
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ISL80102, ISL80103
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF, T = +25°C,
IN
OUT
IN
OUT
J
I = 0A.
L
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
1.2
0.6
0
+125°C
+25°C
-40°C
-0.6
-1.2
-1.8
-50
-25
0
25
50
75
100
125
150
0
1
2
3
4
5
6
JUNCTION TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
FIGURE 3. V
OUT
vs TEMPERATURE
FIGURE 4. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
1.8
9
8
7
6
5
4
3
2
1
0
1.2
0.6
+25°C
0.0
-0.6
-1.2
-1.8
-40°C
+125°C
0
0.5
1.0
1.5
2.0
2.5
3.0
2
3
4
5
6
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
FIGURE 5. V
OUT
vs OUTPUT CURRENT
FIGURE 6. GROUND CURRENT vs SUPPLY VOLTAGE
12.0
9.1
8.9
8.7
8.5
8.3
8.1
7.9
7.7
7.5
11.5
11.0
10.5
10.0
9.5
-40°C
-40°C
+25°C
9.0
+125°C
+125°C
8.5
+25°C
2.0
8.0
7.5
0
0.5
1.0
1.5
2.0
2.5
3.0
0.8
1.4
2.6
3.2
3.8
4.4
5.0
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
FIGURE 8. GROUND CURRENT vs OUTPUT VOLTAGE (V = V
IN OUT
+ V
)
DO
FIGURE 7. GROUND CURRENT vs OUTPUT CURRENT
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ISL80102, ISL80103
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF, T = +25°C,
IN
OUT
IN
OUT
J
I = 0A. (Continued)
L
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
12
11
10
9
8
7
6
5
4
3
2
V
= 5V
IN
V
= 6V
IN
1
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 9. GROUND CURRENT IN SHUTDOWN vs TEMPERATURE
FIGURE 10. GROUND CURRENT IN SHUTDOWN vs TEMPERATURE
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
150
140
130
120
110
100
90
80
70
60
50
2A
3A
40
30
20
10
1A
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT CURRENT (A)
FIGURE 11. DROPOUT VOLTAGE vs TEMPERATURE
FIGURE 12. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 13. ENABLE THRESHOLD VOLTAGE vs TEMPERATURE
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ISL80102, ISL80103
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF, T = +25°C,
IN
OUT
IN
OUT
J
I = 0A. (Continued)
L
EN (1V/DIV)
SS (500mV/DIV)
EN (1V/DIV)
V
(500mV/DIV)
OUT
SS (500mV/DIV)
V
(500mV/DIV)
OUT
PG (1V/DIV)
PG (1V/DIV)
TIME (6.4ms/DIV)
TIME (100µs/DIV)
FIGURE 14. ENABLE START-UP SS CAP 1nF
FIGURE 15. ENABLE SHUTDOWN SS CAP 1nF
EN (1V/DIV)
EN (1V/DIV)
SS (500mV/DIV)
V
(500mV/DIV)
OUT
SS (1V/DIV)
V
(1V/DIV)
OUT
PG (1V/DIV)
PG (1V/DIV)
TIME (50µs/DIV)
TIME (100µs/DIV)
FIGURE 16. ENABLE START-UP SS CAP 100nF
FIGURE 17. ENABLE START-UP (NO SS CAP)
300
250
200
150
100
50
EN (1V/DIV)
SS (1V/DIV)
V
(1V/DIV)
OUT
PG (1V/DIV)
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
TIME (5ms/DIV)
INPUT VOLTAGE (V)
FIGURE 18. ENABLE SHUTDOWN (NO SS CAP)
FIGURE 19. START-UP TIME vs SUPPLY VOLTAGE
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ISL80102, ISL80103
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF, T = +25°C,
IN
OUT
IN
OUT
J
I = 0A. (Continued)
L
300
250
200
150
100
50
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
ISL80103
ISL80102
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 20. START-UP TIME vs TEMPERATURE
FIGURE 21. CURRENT LIMIT vs TEMPERATURE
7.0
I
(1A/DIV)
OUT
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
ISL80103
ISL80102
V
(1V/DIV)
OUT
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
INPUT VOLTAGE(V)
6.0
TIME (10ms/DIV)
FIGURE 22. CURRENT LIMIT vs SUPPLY VOLTAGE
FIGURE 23. CURRENT LIMIT RESPONSE (ISL80102)
EN (1V/DIV)
I
(2A/DIV)
OUT
I
(2A/DIV)
INRUSH
V
(1V/DIV)
OUT
V
(1V/DIV)
OUT
PG (1V/DIV)
TIME (5ms/DIV)
TIME (200µs/DIV)
FIGURE 24. CURRENT LIMIT RESPONSE (ISL80103)
FIGURE 25. IN-RUSH CURRENT WITH NO SOFT-START CAPACITOR,
= 1000µF
C
OUT
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ISL80102, ISL80103
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF, T = +25°C,
IN
OUT
IN
OUT
J
I = 0A. (Continued)
L
EN (1V/DIV)
V
(50mV/DIV)
OUT
I
(1A/DIV)
INRUSH
V
(1V/DIV)
OUT
I
(2A/DIV)
OUT
PG (1V/DIV)
di/dt = 30A/µs
TIME (1ms/DIV)
TIME (200µs/DIV)
FIGURE 26. IN-RUSH WITH 22nF SOFT-START CAPACITOR,
= 1000µF
FIGURE 27. LOAD TRANSIENT 0A TO 3A, C
= 10µF CERAMIC
OUT
C
OUT
V
(50mV/DIV)
OUT
V
(50mV/DIV)
OUT
I
(2A/DIV)
I
OUT
(2A/DIV)
OUT
di/dt = 30A/µs
di/dt = 30A/µs
TIME (200µs/DIV)
TIME (200µs/DIV)
FIGURE 28. LOAD TRANSIENT 0A TO 3A, C
CERAMIC + 100µF OSCON
= 10µF
FIGURE 29. LOAD TRANSIENT 1A TO 3A, C
= 10µF CERAMIC
OUT
OUT
V
(20mV/DIV)
OUT
V
(50mV/DIV)
OUT
I
(2A/DIV)
OUT
I
(2A/DIV)
OUT
di/dt = 30A/µs
di/dt = 3A/µs
TIME (50µs/DIV)
TIME (200µs/DIV)
FIGURE 30. LOAD TRANSIENT 1A TO 3A, C
CERAMIC + 100µF OSCON
= 10µF
FIGURE 31. LOAD TRANSIENT 0A TO 3A, C
= 10µF CERAMIC,
OUT
OUT
NO C (ADJ VERSION)
PB
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ISL80102, ISL80103
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF, T = +25°C,
IN
OUT
IN
OUT
J
I = 0A. (Continued)
L
3.2V
2.2V
V
(20mV/DIV)
OUT
V
(1V/DIV)
IN
(2A/DIV)
I
OUT
V
(10mV/DIV)
OUT
di/dt = 3A/µs
TIME (50µs/DIV)
TIME (200µs/DIV)
FIGURE 32. LOAD TRANSIENT 0A TO 3A, C
= 10µF CERAMIC,
FIGURE 33. LINE TRANSIENT
OUT
= 1500pF (ADJ VERSION)
C
PB
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
NO LOAD
100mA
100mA
NO LOAD
1000mA
1000mA
300mA
300mA
100k
10
100
1k
10k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 34. PSRR vs FREQUENCY FOR V
= 1.0V, V = 2.5V;
IN
FIGURE 35. PSRR vs FREQUENCY FOR V
= 1.2V; V = 2.5V;
IN
OUT
OUT
C
= 47µF, C = 150pF
C
= 47µF, C = 150pF
OUT
PB
OUT PB
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
1000mA
2000mA
300mA
100mA
100mA
NO LOAD
NO LOAD
2000mA
1000mA
3000mA
300mA
100k
10
100
1k
10k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 36. PSRR vs FREQUENCY FOR V
OUT
= 1.5V, V = 2.5V;
IN
FIGURE 37. PSRR vs FREQUENCY FOR V
OUT
= 1.8V, V = 2.5V;
IN
C
= 22µF, C = 82pF
C
= 22µF, C = 82pF
OUT
PB
OUT PB
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ISL80102, ISL80103
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF, T = +25°C,
IN
OUT
IN
OUT
J
I = 0A. (Continued)
L
90
10
100mA
80
70
60
50
40
30
20
10
0
300mA
1
1000mA
NO LOAD
2000mA
0.1
0.01
3000mA
I
= 3A
L
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 38. PSRR vs FREQUENCY FOR V
OUT
= 2.5V, V = 3.3V;
IN
FIGURE 39. SPECTRAL NOISE DENSITY vs FREQUENCY
C
= 10µF, C = 47pF
OUT
PB
Soft-Start Operation (Optional)
If the current limit for in-rush current is acceptable in the
application, do not use this feature (leave SS pin open). The
Functional Description
Input Voltage Requirements
soft-start circuit controls the rate at which the output voltage
comes up to regulation at power-up or LDO enable. The external
soft-start capacitor always gets discharged to ground pin
potential at the beginning of start-up or enabling. After the
capacitor discharges, it will immediately begin charging by a
constant current source. The discharge rate is the RC time
constant of R and C . See Figures 14 through 18 in the
Despite other output voltages offered, this family of LDOs is
optimized for a true 2.5V to 1.8V conversion where the input
supply can have a tolerance of as much as ±10% for conditions
noted in the “Electrical Specifications” table on page 4. Minimum
guaranteed input voltage is 2.2V, however, due to the nature of
an LDO, V must be some margin higher than the output voltage
IN
plus dropout at the maximum rated current of the application if
PD
SS
“Typical Operating Performance Curves” beginning on page 8.
is the ON-resistance of the pull-down MOSFET, M8. R is
active filtering (PSRR) is expected from V to V . The dropout
IN OUT
R
spec of this family of LDOs has been generously specified in
order to allow applications to design for a level of efficiency that
can accommodate the smaller outline package.
PD
PD
323Ω typically.
The soft-start feature effectively reduces the in-rush current at
power-up or LDO enable until V
reaches regulation. The
OUT
Enable Operation
in-rush current can be an issue for applications that require large,
external bulk capacitances on V where high levels of charging
The Enable turn-on threshold is typically 800mV with a hysteresis of
135mV. An internal pull-up or pull-down resistor is available upon
request. As a result, this pin must not be left floating. This pin must
be tied to VIN if it is not used. A 1kΩ to 10kΩ pull-up resistor is
required for applications that use open collector or open drain
outputs to control the Enable pin. The Enable pin may be connected
directly to VIN for applications that are always on.
OUT
current can be seen for a significant period of time. The in-rush
currents can cause V to drop below minimum which could
IN
to shutdown. Figure 26 shows the relationship
cause V
OUT
between in-rush current and C with a C
of 1000µF.
SS
OUT
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Power-Good Operation
Applications not using this feature must connect this pin to
ground. The PGOOD flag is an open-drain NMOS that can sink up
to 10mA during a fault condition. The PGOOD pin requires an
external pull-up resistor, which is typically connected to the VOUT
pin. The PGOOD pin should not be pulled up to a voltage source
greater than V . The PGOOD fault can be caused by the output
IN
voltage going below 84% of the nominal output voltage, or the
current limit fault, or low input voltage. The PGOOD does not
function during thermal shutdown.
0
20
40
60
(nF)
80
100
C
SS
FIGURE 40. IN-RUSH CURRENT vs SOFT-START CAPACITANCE
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ISL80102, ISL80103
Output Voltage Selection
Current Limit Protection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
The ISL80102 and ISL80103 family of LDOs incorporates
protection against overcurrent due to short, overload condition
applied to the output and the in-rush current that occurs at
start-up. The LDO performs as a constant current source when
the output current exceeds the current limit threshold noted in
the “Electrical Specifications” table on page 4. If the short or
programmed to any level between 0.8V and 5.5V. An external
resistor divider, R and R , is used to set the output voltage as
3
4
shown in Equation 1. The recommended value for R is 500Ω to
4
1kΩR is then chosen according to Equation 2:
overload condition is removed from V , then the output returns
3
OUT
to normal voltage mode regulation. In the event of an overload
condition, the LDO might begin to cycle on and off due to the die
temperature exceeding the thermal fault condition.
R
3
(EQ. 1)
(EQ. 2)
------
V
= 0.5V
+ 1
OUT
R
4
V
OUT
0.5V
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions (Note 8)” on page 4.
The power dissipation can be calculated by using Equation 3:
---------------
R
= R
4
– 1
3
External Capacitor Requirements
External capacitors are required for proper operation. To ensure
optimal performance careful attention must be paid to the layout
guidelines and selection of capacitor type and value.
P
= V – V
I
+ V I
OUT IN GND
(EQ. 3)
D
IN
OUT
The maximum allowable junction temperature, T
J(MAX)
and the
maximum expected ambient temperature, T
determine the maximum allowable power dissipation as shown
in Equation 4:
will
A(MAX)
OUTPUT CAPACITOR
The ISL80102 and ISL80103 applies state-of-the-art internal
compensation to keep selection of the output capacitor simple
for the customer. Stable operation over full temperature, V
(EQ. 4)
P
= T
– T
JMAX A JA
DMAX
IN
range, V
range and load extremes are guaranteed for all
ceramic capacitors and values assuming a 10µF X5R/X7R is
OUT
Where is the junction-to-ambient thermal resistance.
JA
For safe operation, please make sure that power dissipation
calculated in Equation 3, P , be less than the maximum
used for local bypass on V . This minimum capacitor (see
OUT
Table 1 components value selection) must be connected to V
and Ground pins of the LDO with PCB traces no longer than
0.5cm.
D
OUT
allowable power dissipation P
.
D(MAX)
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for heat sinking. Figure 41 shows a curve for the
Lower cost Y5V and Z5U type ceramic capacitors are acceptable
if the size of the capacitor is larger to compensate for the
significantly lower tolerance over X5R/X7R types. Additional
capacitors of any value in Ceramic, POSCAP or Alum/Tantalum
Electrolytic types may be placed in parallel to improve PSRR at
higher frequencies and/or load transient AC output voltage
tolerances.
JA
of the DFN package for different copper area sizes.
46
44
42
40
38
36
34
INPUT CAPACITOR
The minimum input capacitor required for proper operation is
10µF having a ceramic dielectric. This minimum capacitor must
be connected to V and ground pins of the LDO with PCB traces
IN
no longer than 0.5cm.
Phase Boost Capacitor (Optional)
The ISL80102 and ISL80103 are designed to be stable with
10µF or larger ceramic capacitor.
2
4
6
8
10
12
14
16
18
20 22
2
24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
FIGURE 41. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
Applications using the ADJ versions may see improved
performance with the addition of a small ceramic capacitor C
as shown in Figure 2, on page 2. The conditions where C may
PB
THERMAL VIAS vs EPAD-MOUNT COPPER LAND
JA
PB
AREA ON PCB
be beneficial are: (1) V
>1.5V, (2) C = 10µF, and (3) tight
OUT
OUT
Thermal Fault Protection
AC voltage regulation band.
introduces phase lead with the product of R and C that
In the event the die temperature exceeds typically +160°C, then
the output of the LDO will shut down until the die temperature
can cool down to typically +145°C. The level of power combined
with the thermal impedance of the package (+48°C/W for DFN)
will determine if the junction temperature exceeds the thermal
shutdown temperature.
C
PB
3
PB
results in increasing the bandwidth of the LDO. Typical R x C
should be less than 0.4μs (400ns).
3
PB
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ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have
the latest Rev.
DATE
REVISION
CHANGE
April 8, 2016
FN6660.7 Updated Ordering Information table (on page 3), Note 1 to include quantities for tape and reel options.
Changed VOUT range upper limit from “5V to 5.5V” on page 1, in the “Recommended Operating Conditions
(Note 7)” on page 4 and in the “Output Voltage Selection” on page 12
Electrical Spec table test conditions changed from: V = V
+ 0.4V, V
= 1.8V, C = C
= 10µF, T = +25°C,
IN
OUT
OUT
IN
OUT J
I
= 0A, to: 2.2V < V < 6V, V
IN OUT
= 0,5V, T = +25°C, I
= 0A
LOAD
J
LOAD
Changed Test conditions in “Output Noise Voltage” on page 5 from: ILOAD = 10mA, BW = 300Hz <f< 300kHz; to:
VIN = 2.2V, VOUT = 1.8V, ILOAD = 3A, BW = 100Hz<f<100kHz and changed TYP from: 100; to: 49
Added two rows to “Dropout Voltage (Note 9)” on page 5 to show parameters for 5.5V V
Updated verbiage for “About Intersil” on page 16.
conditions.
OUT
Updated POD L10.3x3 to most updated revision with changes as follows:
Added missing dimension 0.415 in Typical Recommended land pattern.
Shortened the e-pad rectangle on both the recommended land pattern and the package bottom view to line up
with the centers of the corner pins.
Changed Tiebar note 4, from: Tiebar shown (if present) is a non-functional feature.
to: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
May 23, 2013
FN6660.6 Pin Descriptions on page page 2, updated EPAD section From: EPAD at ground potential. Soldering it directly to
GND plane is optional. To: EPAD must be connected to copper plane with as many vias as possible for proper
electrical and optimal thermal performance.
Removed obsolete part numbers: ISL80102IR33Z, ISL80102IR50Z, ISL80103IR33Z, ISL80103IR50Z from
ordering information table on page 3.
Added evaluation boards to ordering information table on page 3: ISL80103IR50Z and ISL80103EVAL2Z.
Features on page 1: Removed 5 Ld TO220 and 5 Ld TO263.
Input Voltage Requirements on page 12: Removed the sentence “those applications that cannot accommodate
the profile of the TO220/TO263”.
June 14, 2012
FN6660.5 In “Thermal Information” on page 4, corrected from 48 to 45.
JA
February 14, 2012
FN6660.4 Increased “VEN(HIGH)” minimum limit from 0.4V to 0.616 and added the “VEN(LOW)” spec for clarity on page 5.
December 14, 2011 FN6660.3 Increased “Turn-on Threshold” minimum limit on page 5 from 0.3V to 0.4V.
Updated “Package Outline Drawing” on page 16 as follows:
Removed package outline and included center to center distance between lands on recommended land pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm
from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly.
March 4, 2011
FN6660.2 Converted to new template
On page 1 - first paragraph, changed "Fixed output voltage options are available in 1.5V, 1.8V, 2.5V, 3.3V and 5V"
to "Fixed output voltage options are available in 1.8V, 2.5V, 3.3V and 5V"
In “Ordering Information” table on page 2, removed ISL80102IR15Z and ISL80103IR15Z.
In Note 3 on page 2, below the “Ordering Information” table , removed '1.5V', so it reads “The 3.3V and 5V fixed
output voltages will be released in the future. Please contact Intersil Marketing for more details.”
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ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have
the latest Rev. (Continued)
DATE
REVISION
CHANGE
March 4, 2010
FN6660.1 Corrected Features on page 1 as follows:
-Changed bullet "• 185mV Dropout @ 3A, 125mV Dropout @ 2A" to "• Very Low 120mV Dropout at 3A"
-Changed bullet "• 65dB Typical PSRR" to "• 62dB Typical PSRR"
-Deleted 0.5% Initial VOUT Accuracy
Modified Figure 1 and placed as “TYPICAL APPLICATION” on page 1.
Moved Pinout to page 3
In “Block Diagram” on page 2, corrected resistor associated with M5 from R4 to R5
Updated “Block Diagram” on page 2 as follows”
- Added M8 from SS to ground.
Updated Figure 1 on page 1 as follows:
-Corrected Pin 6 from SS to IRSET
-Removed Note 11 callout "Minimum cap on VIN and VOUT required for stability." Added Note "*CSS is optional.
See Note 12 on Page 5." and “** CPB is optional. See “Functional Description” on page 12 for more information.”
Added "The 1.5V, 3.3V and 5V fixed output voltages will be released in the future." to Note 3 on page 2.
In “Thermal Information” on page 4, updated Theta JA from 45 to 48.
In “Soft-Start Operation (Optional)” on page 12:
-Changed "The external capacitor always gets discharged to 0V at start-up of after coming out of a chip disable.
"The external capacitor always gets discharged to ground pin potential at start-up or enabling."
-Changed "The soft-start function effectively limits the amount of in-rush current below the programmed current
limit during start-up or an enable sequence to avoid an overcurrent fault condition." to "The soft-start feature
effectively reduces the in-rush current at power-up or LDO enable until VOUT reaches regulation."
-Added "See Figures 25 through 27 in the “Typical Operating Performance Curves” beginning on page 6."
-Added “RPD is the on resistance of the pull-down MOSFET, M8. RPD is 300Ω typically.”
March 4, 2010
Added “Phase Boost Capacitor (Optional)” on page 13.
In “Typical Operating Performance” on page 11, revised figure "PSRR vs VIN" which had 3 curves with “SPECTRAL
NOISE DENSITY vs FREQUENCY” which has one curve.
Added "Figure 33. “LOAD TRANSIENT 0A TO 3A, C
= 10µF CERAMIC, NO CPB (ADJ VERSION)” and "Figure 34.
OUT
= 10µF CERAMIC, CPB = 1500pF (ADJ VERSION)”
“LOAD TRANSIENT 0A TO 3A, C
OUT
September 30, 2009 FN6660.0 Initial Release.
About Intersil
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL80102, ISL80103
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 11, 3/15
5
3.00
A
B
PIN #1 INDEX AREA
1
2
5
PIN 1
INDEX AREA
10 x 0.23
(4X)
0.10
1.60
10x 0.35
TOP VIEW
BOTTOM VIEW
A B
C
M
0.10
(4X)
0.415
0.23
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
0.415
4
0.20 REF
0.05
C
1.60
2.85 TYP
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6660.7
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