ISL8023A [RENESAS]
Compact Synchronous Buck Regulator;
| 型号： | ISL8023A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Compact Synchronous Buck Regulator |
| 文件： | 总20页 (文件大小：1045K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL8023, ISL8024
Compact Synchronous Buck Regulator
FN7812
Rev 3.00
March 24, 2014
The ISL8023, ISL8024 are highly efficient, monolithic,
Features
synchronous step-down DC/DC converters that can deliver 3A
(ISL8023) or 4A (ISL8024) of continuous output current from a
2.7V to 5.5V input supply. The devices use current mode control
architecture to deliver very low duty cycle operation at high
frequency with fast transient response and excellent loop stability.
• 2.7V to 5.5V input voltage range
• Very low on-resistance FET’s - P-Channel 45mΩ and
N-Channel 19mΩ typical values
• High efficiency synchronous buck regulator with up to 95%
efficiency
The ISL8023 and ISL8024 integrate a very low On-resistance
P-Channel (45mΩ) high side FET and N-Channel (19mΩ) low
side FET to maximize efficiency and minimize external
component count. The 100% duty-cycle operation allows less
than 200mV dropout voltage at 4A output current. The
operation frequency of the pulse-width modulator (PWM) is
adjustable from 500kHz to 4MHz. The default switching
frequency of 1MHz is set by connecting the FS pin high, which
allows for the use of small external components.
• 0.8% reference accuracy over-temperature/load/line
• Complete BOM with as few as 3 external parts
• Start-up with pre-biased output
• Internal soft-start - 1ms or adjustable
• Soft-stop output discharge during disabled
• Adjustable frequency from 500kHz to 4MHz - default at
1MHz (8023/24), 2MHz (8023A/24A)
The ISL8023, ISL8024 can be configured for discontinuous or
forced continuous operation at light load. Forced continuous
operation reduces noise and RF interference while
discontinuous mode provides higher efficiency by reducing
switching losses at light loads.
• External synchronization up to 4MHz
• Over-temperature, Overcurrent, Overvoltage and negative
overcurrent protection
• Tiny 3x3 QFN package
Fault protection is provided by internal hiccup mode current
limiting during short circuit and overcurrent conditions. Other
protection, such as overvoltage and over-temperature are also
integrated into the device. A power-good output voltage
monitor indicates when the output is in regulation.
Applications
• DC/DC POL modules
• μC/µP, FPGA and DSP power
• Plug-in DC/DC modules for routers and switchers
• Portable instruments
The ISL8023, ISL8024 offer a 1ms Power-Good (PG) timer at
power-up. When in shutdown, ISL8023, ISL8024 discharges
the output capacitor through an internal soft-stop switch. Other
features include internal fixed or adjustable soft-start and
internal/external compensation.
• Test and measurement systems
• Li-ion battery powered devices
The ISL8023 and ISL8024 are offered in a space saving 16 Ld
3x3 Pb-free QFN package with an exposed pad for improved
thermal performance and 1mm maximum height. The
Related Literature
• See AN1759, “3A/4A Low Quiescent Current High Efficiency
Synchronous Buck Regulator”
2
complete converter occupies less than 0.22 in area.
Various fixed output voltages are available upon request. See
the “Ordering Information” on page 4 for more details.
100
90
3.3V
3.3V
PFM
OUT
80
70
60
50
40
PWM
OUT
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
(A)
I
OUT
FIGURE 1. EFFICIENCY T = +25°C, V = 5V
IN
FN7812 Rev 3.00
March 24, 2014
Page 1 of 20
ISL8023, ISL8024
NOTE: Full solution in size board. The full schematic and Gerber files are available for down load from Intersil.com.
FN7812 Rev 3.00
March 24, 2014
Page 2 of 20
ISL8023, ISL8024
Pin Configuration
ISL8023, ISL8024
(16 LD TQFN)
TOP VIEW
16
14
15
13
VIN
PGND
PGND
1
2
3
4
12
11
10
9
VDD
PG
SGND
FB
SYNC
7
8
6
5
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1, 16
VIN
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
Input supply voltage for the logic. Connect VIN PIN.
2
3
VDD
PG
Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connecting between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation.
4
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case
of SYNIN pin float.
SYNC
5
6
EN
FS
Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output
capacitor when driven to low. There is an internal 1MΩ pull-down resistor to prevent an undefined logic
state in case of EN pin float.
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
7
SS
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from
SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
8, 9
COMP, FB
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if FS resistor is used. Otherwise COMP is disconnected
thru a MOSFET for internal compensation. Recommend connecting COMP to SGND in internal
compensation mode. The output voltage is set by an external resistor divider connected to VFB. With
a properly selected divider, the output voltage can be set to any voltage between the power rail
(reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a
typical application. Additional external network across COMP and SGND might be required to improve
the loop compensation of the amplifier operation.
In addition, the regulator power-good and undervoltage protection circuitry use VFB to monitor the
regulator output voltage.
10
SGND
PGND
PHASE
-
Signal ground.
11, 12
Power ground.
13, 14, 15
Exposed Pad
Switching node connection. Connect to one terminal of the inductor.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as
much vias as possible under the pad connecting to SGND plane for optimal thermal performance.
FN7812 Rev 3.00
March 24, 2014
Page 3 of 20
ISL8023, ISL8024
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
OUTPUT VOLTAGE
(V)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL8023IRTAJZ
023A
024A
23AA
24AA
Adjustable
-40 to +85
-40 to +85
-40 to +85
-40 to +85
16 Ld 3x3 TQFN
L16.3x3D
L16.3x3D
L16.3x3D
L16.3x3D
ISL8024IRTAJZ
ISL8023AIRTAJZ
ISL8024AIRTAJZ
ISL8023EVAL3Z
ISL8024EVAL3Z
ISL8023AEVAL3Z
ISL8024AEVAL3Z
NOTES:
Adjustable
Adjustable
Adjustable
16 Ld 3x3 TQFN
16 Ld 3x3 TQFN
16 Ld 3x3 TQFN
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8023, ISL8024. For more information on MSL, please see tech brief
TB363.
Typical Application Diagram
OUTPUT
1.8V/4A
L
1µH
INPUT
2.7V TO 5.5V
VIN
VDD
EN
PHASE
PGND
C2
2 x 22µF
C1
22µF
C3*
4.7pF
R2
200k
R1
100k
PG
R3
100k
ISL8023, ISL8024
SGND
SYNC
FS
VFB
COMP
SS
VIN
SGND
* C3 is optional. Recommend to
put a placeholder for it. Check
loop analysis first before use.
FIGURE 2. TYPICAL APPLICATION DIAGRAM
TABLE 1. COMPONENT SELECTION TABLE
V
0.8V
22µF
1.2V
1.5V
22µF
1.8V
22µF
2.5V
22µF
3.3V
3.6
OUT
C1
C2
C3
L1
R2
R3
22µF
22µF
2 x 22µF
4.7pF
22µF
2 x 22µF
4.7pF
4X22µF
4.7pF
2 x 22µF
4.7pF
2 x 22µF
4.7pF
2 x 22µF
4.7pF
2 x 22µF
4.7pF
0.47~1µH
33k
0.47~1µH
100k
0.47~1µH
150k
0.68~1.5µH
200k
0.68~1.5µH
316k
1~2.2µH
450k
1~2.2µH
500k
100k
100k
100k
100k
100k
100k
100k
FN7812 Rev 3.00
March 24, 2014
Page 4 of 20
ISL8023, ISL8024
COMP
55pF
FS
SYNC
SS
SOFT
START
SHUTDOWN
VDD
SHUTDOWN
100kΩ
+
+
VIN
EN
OSCILLATOR
VREF
3pF
BANDGAP
+
EAMP
COMP
P
-
-
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
PHASE
PGND
LS
DRIVER
N
+
VFB
SLOPE
COMP
6k
+
0.6V
-
CSA
-
+
-
OV
+
OCP
-
0.85*VREF
ISET
THRESHOLD
+
UV
+
SKIP
-
PG
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
-
SCP
+
0.5V
100Ω
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN7812 Rev 3.00
March 24, 2014
Page 5 of 20
ISL8023, ISL8024
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V (DC) or 7V (20ms)
EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3V (100ns)/(DC) to 6.5V (DC)
COMP, SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Thermal Resistance
16 LD TQFN Package (Notes 4, 5) . . . . . . .
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(°C/W)
45
(°C/W)
6.5
JA
JC
Recommended Operating Conditions
VIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. , “case temperature” location is at the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specification are measured at the following conditions: T = -40°C to +85°C, V = 3.6V, EN = V , unless otherwise noted. Typical values are
A
IN
IN
at T = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
INPUT SUPPLY
Undervoltage Lockout Threshold
V
V
Rising, no load
2.5
2.4
50
2.7
V
V
IN
UVLO
Falling, no load
2.2
Quiescent Supply Current
I
SYNC = GND, no load at the output
µA
µA
VIN
SYNC = GND, no load at the output and no
switches switching
50
60
SYNC = V , F = 1MHz, no load at the output
IN
8
5
15
7
mA
µA
S
Shutdown Supply Current
I
SYNC = GND, V = 5.5V, EN = low
IN
SD
OUTPUT REGULATION
Reference Voltage - ISL8023IRZ, ISL8024IRZ
VFB Bias Current - ISL8023IRZ, ISL8024IRZ
Line Regulation
V
0.595
0.600
0.01
0.2
0.605
V
REF
I
VFB = 0.75V
µA
VFB
V
= V + 0.5V to 5.5V (minimal 2.7V)
%/V
ms
µA
IN
SS = SGND
= 0.1V
O
Soft-Start Ramp Time Cycle
Soft-Start Charging Current
OVERCURRENT PROTECTION
Current Limit Blanking Time
1
I
V
1.2
1.6
2.0
SS
SS
t
17
Clock
OCON
pulses
Overcurrent and Auto Restart Period
Positive Peak Current Limit
t
8
SS cycle
OCOFF
I
4A application
5.2
3.9
6.5
4.8
1.2
0.9
7.8
5.9
A
A
PLIMIT
3A application
Peak Skip Limit
I
4A application (test at 3.6V)
3A application (test at 3.6V)
0.9
1.5
A
SKIP
0.65
-200
-3.0
1.15
200
-1.8
A
Zero Cross Threshold
Negative Current Limit
mA
A
I
-2.4
NLIMIT
FN7812 Rev 3.00
March 24, 2014
Page 6 of 20
ISL8023, ISL8024
Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specification are measured at the following conditions: T = -40°C to +85°C, V = 3.6V, EN = V , unless otherwise noted. Typical values are
A
IN
IN
at T = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C (Continued)
A
MIN
MAX
PARAMETER
COMPENSATION
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
Error Amplifier Trans-Conductance
FS = VIN
FS with Resistor
80
150
0.2
µA/V
µA/V
Ω
Trans-Resistance
RT
0.15
0.25
PHASE
P-Channel MOSFET ON-Resistance
V
V
V
V
= 5V, I = 200mA
35
50
12
20
45
70
55
90
25
37
mΩ
mΩ
mΩ
mΩ
IN
IN
IN
IN
O
= 2.7V, I = 200mA
O
N-Channel MOSFET ON-Resistance
= 5V, I = 200mA
19
O
= 2.7V, I = 200mA
28
O
PHASE Maximum Duty Cycle
PHASE Minimum On-Time
OSCILLATOR
100
SYNC = High
140
ns
Nominal Switching Frequency
Fsw
FS = VIN
800
1000
490
1200
kHz
kHz
kHz
V
FS with RS = 402kΩ
FS with RS = 42.2kΩ
4200
0.75
0.15
3.6
SYNC Logic Low to High Transition Range
SYNC Hysteresis
0.70
0.80
5
V
SYNC Logic Input Leakage Current
PG
V
= 3.6V
µA
IN
Output Low Voltage
0.3
2
V
ms
µA
V
Delay Time (Rising Edge)
PG Pin Leakage Current
OVP PG Rising Threshold
UVP PG Rising Threshold
UVP PG Hysteresis
0.5
80
1
0.01
0.80
85
0.1
90
%
5
%
PGOOD Delay Time (Falling Edge)
EN
15
µs
Logic Input Low
0.4
1
V
Logic Input High
0.9
V
EN Logic Input Leakage Current
Thermal Shutdown
0.1
150
25
µA
°C
°C
Thermal Shutdown Hysteresis
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7812 Rev 3.00
March 24, 2014
Page 7 of 20
ISL8023, ISL8024
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
VIN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 4A.
IN
1
2
OUT
100
100
90
80
70
60
50
40
90
80
70
60
50
40
1.2V
OUT
1.2V
OUT
1.5V
1.5V
OUT
OUT
1.8V
OUT
1.8V
OUT
2.5V
2.5V
OUT
OUT
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
4.0
I
I
OUT
OUT
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 V PWM)
IN
FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3 V PFM)
IN
100
100
90
80
70
60
50
40
90
80
70
60
50
40
1.5V
OUT
1.2V
1.8V
OUT
1.5V
OUT
OUT
1.8V
OUT
2.5V
2.5V
OUT
1.2V
OUT
OUT
3.3V
OUT
3.3V
OUT
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
4.0
I
OUT
I
OUT
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5V PWM)
IN
FIGURE 7. EFFICIENCY vs LOAD (1MHz 5V PFM
IN
)
1.08
0.90
0.72
0.54
0.36
0.18
0
1.244
1.238
1.232
1.226
1.220
1.214
1.208
3.3V PWM MODE
IN
3.3V PFM MODE
IN
5V PWM MODE
IN
5V PFM MODE
IN
3.3V PWM MODE
IN
5V PWM MODE
IN
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
I
2.0
(A)
2.5
3.0
3.5
4.0
I
OUT
OUT
FIGURE 8. POWER DISSIPATION vs LOAD (1MHz, V
= 1.8V)
FIGURE 9. V
OUT
REGULATION vs LOAD (1MHz, V
= 1.2V)
OUT
OUT
FN7812 Rev 3.00
March 24, 2014
Page 8 of 20
ISL8023, ISL8024
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
VIN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 4A. (Continued)
IN
1
2
OUT
1.529
1.830
1.824
1.818
1.812
1.806
1.800
1.794
3.3V PFM MODE
IN
1.524
1.519
1.514
1.509
1.504
1.499
5V PFM MODE
IN
3.3V PFM MODE
IN
5V PFM MODE
IN
3.3V PWM MODE
IN
3.3V PWM MODE
IN
5V PWM MODE
IN
5V PWM MODE
IN
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
4.0
I
I
OUT
OUT
FIGURE 11. V
REGULATION vs LOAD (1MHz, V
= 1.8V)
OUT
FIGURE 10. V
REGULATION vs LOAD (1MHz, V
= 1.5V)
OUT
OUT
OUT
2.540
2.532
2.524
2.516
2.508
2.500
3.354
3.345
3.336
3.327
3.318
3.309
3.3V PFM MODE
IN
5V PFM MODE
IN
5V PFM MODE
IN
3.3V PWM MODE
IN
5V PWM MODE
IN
5V PWM MODE
IN
2.492
3.300
0.0
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
4.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
4.0
I
I
OUT
OUT
FIGURE 12. V
REGULATION vs LOAD (1MHz, V
= 2.5V)
OUT
FIGURE 13. V
REGULATION vs LOAD (1MHz, V
= 3.3V)
OUT
OUT
OUT
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.836
1.828
1.820
1.812
1.804
1.796
1.788
0A LOAD
0A LOAD
2A LOAD
4A LOAD
2A LOAD
4A LOAD
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
6.0
V
V
IN
IN
FIGURE 15. OUTPUT VOLTAGE REGULATION vs V (PFM V
IN OUT
= 1.8V)
FIGURE 14. OUTPUT VOLTAGE REGULATION vs V (PWM V
IN
= 1.8 )
OUT
FN7812 Rev 3.00
March 24, 2014
Page 9 of 20
ISL8023, ISL8024
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
VIN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 4A. (Continued)
IN
1
2
OUT
PHASE 2V/DIV
PHASE 2V/DIV
V
RIPPLE 20mV/DIV
V
L
RIPPLE 20mV/DIV
OUT
OUT
I
1A/DIV
L
I
1A/DIV
FIGURE 16. STEADY STATE OPERATION AT NO LOAD (PWM)
FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PFM)
V
RIPPLE 50mV/DIV
OUT
PHASE 2V/DIV
I
2A/DIV
L
I
2A/DIV
L
V
RIPPLE 20mV/DIV
OUT
FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD
FIGURE 19. LOAD TRANSIENT (PWM)
V
RIPPLE 50mV/DIV
OUT
EN 2V/DIV
V
1V/DIV
OUT
I
1A/DIV
L
I
2A/DIV
L
PG 5V/DIV
FIGURE 21. SOFT-START WITH NO LOAD (PWM)
FIGURE 20. LOAD TRANSIENT (PFM)
FN7812 Rev 3.00
March 24, 2014
Page 10 of 20
ISL8023, ISL8024
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
VIN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 4A. (Continued)
IN
1
2
OUT
EN 2V/DIV
EN 2V/DIV
V
1V/DIV
OUT
V
1V/DIV
OUT
I
1A/DIV
I
1A/DIV
L
L
PG 2V/DIV
PG 5V/DIV
FIGURE 22. SOFT-START AT NO LOAD (PFM)
FIGURE 23. SOFT-START WITH PRE-BIASED 1V
EN 2V/DIV
EN 2V/DIV
V
1V/DIV
OUT
V
1V/DIV
OUT
I
1A/DIV
L
I
2A/DIV
L
PG 5V/DIV
PG 5V/DIV
FIGURE 24. SOFT-START AT FULL LOAD
FIGURE 25. SOFT-DISCHARGE SHUTDOWN
PHASE 5V/DIV
PHASE 5V/DIV
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT
OUT
I
0.5A/DIV
L
I
2A/DIV
L
SYNC 5V/DIV
SYNC 5V/DIV
FIGURE 26. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 2MHz
FIGURE 27. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 2MHz
FN7812 Rev 3.00
March 24, 2014
Page 11 of 20
ISL8023, ISL8024
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
VIN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 4A. (Continued)
IN
1
2
OUT
PHASE 5V/DIV
PHASE 5V/DIV
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT
OUT
I
1A/DIV
L
I
0.2A/DIV
L
SYNC 5V/DIV
SYNC 5V/DIV
FIGURE 29. STEADY STATE OPERATION AT FULL LOAD (PWM) WITH
FREQUENCY = 4MHz
FIGURE 28. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 4MHz
PHASE 5V/DIV
PHASE 5V/DIV
I
2A/DIV
L
V
1V/DIV
2A/DIV
OUT
V
1V/DIV
I
OUT
L
SYNC 5V/DIV
SYNC 5V/DIV
FIGURE 30. OUTPUT SHORT CIRCUIT
FIGURE 31. OUTPUT SHORT CIRCUIT RECOVERY
Typical Operating Performance for A Part Unless otherwise noted, operating conditions are:
T
= +25°C, V
VIN
= 5V, EN = V , SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 4A.
OUT
A
IN
IN
1
2
PHASE 2V/DIV
PHASE 2V/DIV
V
RIPPLE 20mV/DIV
V
L
RIPPLE 20mV/DIV
OUT
OUT
I
0.5A/DIV
L
I
1A/DIV
FIGURE 32. STEADY STATE OPERATION AT NO LOAD (PWM)
FIGURE 33. STEADY STATE OPERATION AT NO LOAD (PFM)
FN7812 Rev 3.00
March 24, 2014
Page 12 of 20
ISL8023, ISL8024
Typical Operating Performance for A Part Unless otherwise noted, operating conditions are:
T
= +25°C, V
VIN
= 5V, EN = V , SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 4A. (Continued)
OUT
A
IN
IN
1
2
EN 2V/DIV
PHASE 2V/DIV
V
1V/DIV
OUT
I
2A/DIV
L
I
1A/DIV
V
RIPPLE 20mV/DIV
L
OUT
PG 5V/DIV
FIGURE 35. SOFT-START WITH NO LOAD (PWM)
FIGURE 34. STEADY STATE OPERATION WITH FULL LOAD
EN 2V/DIV
EN 2V/DIV
V
1V/DIV
V
1V/DIV
OUT
OUT
I
1A/DIV
L
I
1A/DIV
L
PG 5V/DIV
PG 5V/DIV
FIGURE 36. SOFT-START AT NO LOAD (PFM)
FIGURE 37. SOFT-START AT FULL LOAD
EN 2V/DIV
V
1V/DIV
OUT
I
1A/DIV
L
PG 5V/DIV
FIGURE 38. SOFT-DISCHARGE SHUTDOWN
FN7812 Rev 3.00
March 24, 2014
Page 13 of 20
ISL8023, ISL8024
Theory of Operation
V
EAMP
The ISL8023, ISL8024 is a step-down switching regulator
optimized for battery-powered handheld applications. The
regulator operates at 1MHz fixed default switching frequency,
when FS is connected to VIN, under heavy load conditions to
allow smaller external inductors and capacitors to be used for
minimal printed-circuit board (PCB) area. By connecting a
resistor from FS to SGND, the operational frequency adjustable
range is 500kHz to 4MHz. At light load, the regulator reduces the
switching frequency, unless forced to the fixed frequency, to
minimize the switching loss and to maximize the battery life. The
quiescent current when the output is not loaded is typically only
50µA. The supply current is typically only 5µA when the regulator
is shutdown.
V
CSA
DUTY
CYCLE
I
L
V
OUT
FIGURE 39. PWM OPERATION WAVEFORMS
PWM Control Scheme
SKIP Mode
Pulling the SYNC pin HI (>0.8V) forces the converter into PWM
mode, regardless of output current. The ISL8023, ISL8024
employs the current-mode pulse-width modulation (PWM) control
scheme for fast transient response and pulse-by-pulse current
limiting. Figure 3 on page 5 shows the Functional Block Diagram.
The current loop consists of the oscillator, the PWM comparator,
current sensing circuit and the slope compensation for the
current loop stability. The slope compensation is 440mV/Ts,
which changes with frequency. The gain for the current sensing
circuit is typically 200mV/A. The control reference for the current
loops comes from the error amplifier's (EAMP) output.
Pulling the SYNC pin LO (<0.4V) forces the converter into PFM
mode. The ISL8023, ISL8024 enters a pulse-skipping mode at
light load to minimize the switching loss by reducing the
switching frequency. Figure 40 illustrates the skip-mode
operation. A zero-cross sensing circuit shown in Figure 3 on
page 5 monitors the N-FET current for zero crossing. When 8
consecutive cycles of the inductor current crossing zero are
detected, the regulator enters the skip mode. During the eight
detecting cycles, the current in the inductor is allowed to become
negative. The counter is reset to zero when the current in any
cycle does not cross zero.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-Channel MOSFET. The N-FET stays on
until the end of the PWM cycle. Figure 39 shows the typical
operating waveforms during the PWM operation. The dotted lines
illustrate the sum of the slope compensation ramp and the
current-sense amplifier’s CSA output.
Once the skip mode is entered, the pulse modulation starts being
controlled by the SKIP comparator shown in Figure 3 on page 5.
Each pulse cycle is still synchronized by the PWM clock. The
P-FET is turned on at the clock's rising edge and turned off when
the output is higher than 1.5% of the nominal regulation or when
its current reaches the peak Skip current limit value. Then the
inductor current is discharging to 0A and stays at zero. The
internal clock is disabled. The output voltage reduces gradually
due to the load current discharging the output capacitor. When
the output voltage drops to the nominal voltage, the P-FET will be
turned on again at the rising edge of the internal clock as it
repeats the previous operations.
The output voltage is regulated by controlling the V
EAMP
voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 55pF and 100kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 1.6V.
The regulator resumes normal PWM mode operation when the
output voltage drops 1.5% below the nominal voltage.
FN7812 Rev 3.00
March 24, 2014
Page 14 of 20
ISL8023, ISL8024
PWM
PFM
PWM
CLOCK
8 CYCLES
PFM CURRENT LIMIT
LOAD CURRENT
I
L
0
NOMINAL +1.5%
V
OUT
NOMINAL -1.5%
NOMINAL
FIGURE 40. SKIP MODE OPERATION WAVEFORMS
Frequency Adjust
Negative Current Protection
The frequency of operation is fixed at 1MHz and internal
compensation when FS is tied to VIN. Adjustable frequency range
from 500kHz to 4MHz via simple resistor connecting FS to SGND
according to Equation 1:
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the low-side N-FET, as
shown in Figure 3 on page 5. When the valley point of the inductor
current reaches -3A for 4 consecutive cycles, both P-FET and N-FET
are off. The 100Ω in parallel to the N-FET will activate discharging
the output into regulation. The control will begin to switch when
output is within regulation. The regulator will be in PFM for 20µs
before switching to PWM if necessary.
3
220 10
------------------------------
R k =
– 14
(EQ. 1)
T
f
kHz
OSC
Overcurrent Protection
PG
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 3. The current
sensing circuit has a gain of 200mV/A, from the P-FET current to
the CSA output. When the CSA output reaches the threshold, the
OCP comparator is trippled to turn off the P-FET immediately. The
overcurrent function protects the switching converter from a
shorted output by monitoring the current flowing through the
upper MOSFET.
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. After 1ms delay of the soft-start period, PG
becomes high impedance as long as the output voltage is within
nominal regulation voltage set by VFB. When VFB drops 15% below
or raises 0.8V above the nominal regulation voltage, the ISL8023,
ISL8024 pulls PG low. Any fault condition forces PG low until the
fault condition is cleared by attempts to soft-start. For logic level
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. Upon detection of the initial
overcurrent condition, the overcurrent fault counter is set to 1. If,
on the subsequent cycle, another overcurrent condition is
detected, the OC fault counter will be incremented. If there are
17 sequential OC fault detections, the regulator will be shutdown
under an overcurrent fault condition. An overcurrent fault
condition will result in the regulator attempting to restart in a
hiccup mode within the delay of eight soft-start periods. At the
end of the eight soft-start wait period, the fault counters are reset
and soft-start is attempted again. If the overcurrent condition
goes away during the delay of eight soft-start periods, the output
will resume back into regulation point after hiccup mode expires.
output voltages, connect an external pull-up resistor, R , between
PG and VIN. A 100k resistor works well in most applications.
1
UVLO
When the input voltage is below the undervoltage lock-out (UVLO)
threshold, the regulator is disabled.
FN7812 Rev 3.00
March 24, 2014
Page 15 of 20
ISL8023, ISL8024
Soft Start-Up
Applications Information
Output Inductor and Capacitor Selection
To consider steady state and transient operations, ISL8023,
ISL8024 typically uses a 1.0µH output inductor. The higher or
lower inductor value can be used to optimize the total converter
system performance. For example, for higher output voltage 3.3V
application, in order to decrease the inductor current ripple and
output voltage ripple, the output inductor value can be increased.
It is recommended to set the ripple inductor current
The soft start-up reduces the in-rush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed so that the output voltage rises
in a controlled fashion. When VFB is less than 0.1V at the
beginning of the soft-start, the switching frequency is reduced to
200kHz so that the output can start-up smoothly at light load
condition. During soft-start, the IC operates in the SKIP mode to
support pre-biased output condition.
approximately 30% of the maximum output current for optimized
performance. The inductor ripple current can be expressed as
shown in Equation 3:
Tie SS to SGND for internal soft-start approximately 1ms.
Connect a capacitor from SS to SGND to adjust the soft-start
time. This capacitor, along with an internal 1.6µA current source,
V
sets the soft-start interval of the converter, T as shown by
O
SS
---------
V
1 –
(EQ. 3)
O
V
Equation 2.
IN
--------------------------------------
I =
L f
S
C
F = 3.33 T s
SS
(EQ. 2)
SS
The inductor’s saturation current rating needs to be at least
larger than the peak current. The ISL8023, ISL8024 protects the
typical peak current 4.8A/6.5A. The saturation current needs be
over 7A for maximum output current application.
C
must be less than 33nF to insure proper soft-start reset after
ss
fault condition.
Enable
ISL8023, ISL8024 uses internal compensation network and the
output capacitor value is dependent on the output voltage. The
ceramic capacitor is recommended to be X5R or X7R. The
recommended X5R or X7R minimum output capacitor values are
shown in Table 1.
The enable (EN) input allows the user to control the turning on or
off the regulator for purposes such as power-up sequencing.
When the regulator is enabled, there is typically a 600µs delay
for waking up the bandgap reference and then the soft-start-up
begins.
In Table 1, the minimum output capacitor value is given for the
different output voltage to make sure that the whole converter
system is stable. Additional output capacitance should be added
for better performances in applications where high load transient
or low output ripple is required. It is recommended to check the
system level performance along with the simulation model.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN UVLO is
set, the outputs discharge to GND through an internal 100
switch.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-FET is typically 45m and the
ON-resistance for the N-FET is typically 19m.
Output Voltage Selection
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier. Refer to Figure 2.
100% Duty Cycle
The ISL8023, ISL8024 features 100% duty cycle operation to
maximize the battery life. When the battery voltage drops to a
level that the ISL8023, ISL8024 can no longer maintain the
regulation at the output, the regulator completely turns on the
P-FET. The maximum dropout voltage under the 100% duty-cycle
operation is the product of the load current and the
ON-resistance of the P-FET.
The output voltage programming resistor, R , will depend on the
2
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 10k and 100kas shown in Equation 4.
V
O
-----------
– 1
(EQ. 4)
R
= R
2
3
VFB
If the output voltage desired is 0.6V, then R is left unpopulated
3
Thermal Shut-Down
and R is shorted. There is a leakage current from VIN to PHASE.
2
It is recommended to preload the output with 10µA minimum.
The ISL8023, ISL8024 has built-in thermal protection. When the
internal temperature reaches +150°C, the regulator is completely
shutdown. As the temperature drops to +125°C, the ISL8023,
ISL8024 resumes operation by stepping through the soft-start.
For better performance, add 15pF in parallel with R (100k
2
Check loop analysis before use in application.
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. At least two 22µF X5R or X7R ceramic capacitors are
a good starting point for the input capacitor selection.
FN7812 Rev 3.00
March 24, 2014
Page 16 of 20
ISL8023, ISL8024
Loop Compensation Design
Power Stage Transfer Functions
When there is an external resistor connected from FS to SGND,
the COMP pin is active for external loop compensation. The
ISL8023, ISL8024 uses constant frequency peak current mode
control architecture to achieve fast loop transient response. An
accurate current sensing pilot device in parallel with the upper
MOSFET is used for peak current control signal and overcurrent
protection. The inductor is not considered as a state variable
since its peak current is constant, and the system becomes
single order system. It is much easier to design a type II
compensator to stabilize the loop than to implement voltage
mode control. Peak current mode control has inherent input
voltage feed-forward function to achieve good line regulation.
Figure 41 shows the small signal model of the synchronous buck
regulator.
Transfer function F (S) from control to output voltage is:
1
S
-----------
1 +
ˆ
v
esr
o
(EQ. 8)
------
ˆ
--------------------------------------
F S =
= V
1
in
2
d
S
S
------ --------------
+
+ 1
2
o
Q
o
p
C
1
1
o
--------------
------------------
=
,Q R ------ , =
Where
esr
p
o
o
R C
L
L C
c
o
P
P
o
Transfer function F (S) from control to inductor current is given
2
by Equation 9:
S
------
1 +
ˆ
V
I
o
in
z
(EQ. 9)
----
ˆ
------------------------ --------------------------------------
F S =
=
2
2
R
+ R
LP
d
o
S
S
------ --------------
+
+ 1
2
o
Q
^
o
p
^
^
L
R
LP
i
P
i
L
v
in
o
1
--------------
^
d
=
where
.
V
z
in
R C
^
^
1:D
o
o
I d
V
L
in
Rc
Co
Current loop gain T (S) is expressed as Equation 10:
i
+
R
T
Ro
T S = R F F SH S
(EQ. 10)
i
t
m
2
e
The voltage loop gain with open current loop is Equation 11:
T (S)
i
^
d
T S = KF F SA S
(EQ. 11)
v
m
1
v
K
Fm
The Voltage loop gain with current loop closed is given by
Equation 12:
T (S)
+
v
He(S)
T S
v
^
(EQ. 12)
-----------------------
L S =
v
comp
v
1 + T S
-Av(S)
i
V
FB
----------
K =
, V
FB
FIGURE 41. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
Where
is the feedback voltage of the voltage
V
error amplifiero. If T (S)>>1, then Equation 12 can be simplified as
i
Equation 13:
PWM Comparator Gain F :
m
S
-----------
1 +
The PWM comparator gain F for peak current mode control is
given by Equation 5:
V
R
+ R
A S
esr v
m
1
FB
o
LP
-----------------------------------------------------------------------
--------------
(EQ. 13)
L S=
,
p
v
V
R
S
H S
R C
o o
o
t
e
------
1 +
ˆ
d
1
(EQ. 5)
p
----------------
-------------------------------
F
=
=
m
ˆ
S + S T
s
v
e
n
comp
Equation 13 shows that the system is a single order system,
p
which has a single pole located at
before the half switching
Where S is the slew rate of the slope compensation and S is
given by Equation 6:
e
n
frequency. Therefore, a simple type II compensator can be easily
used to stabilize the system.
V
– V
(EQ. 6)
in
o
---------------------
S
= R
n
t
L
P
where R is trans-resistance, which is the gain of the current
t
amplifier.
CURRENT SAMPLING TRANSFER FUNCTION H (S):
e
In current loop, the current signal is sampled every switching
cycle. It has the following transfer function in Equation 7:
2
(EQ. 7)
S
S
------ --------------
+
H S=
+ 1
e
2
n
Q
n
n
2
--
where Q and are given by
Q
= – = f
n
n
n
n
s
FN7812 Rev 3.00
March 24, 2014
Page 17 of 20
ISL8023, ISL8024
Example: V = 5V, V = 1.8V, I = 4A, f = 1MHz,
IN
o
o
s
Vo
C = 2X22µF/3m, L = 1µH, GM = 150µs, R = 0.20V/A,
o
FB
t
5
V
= 0.6V, S = 440mV/µs, S = 6.410 V/s, f = 100kHz, then
e n c
compensator resistance R = 100k.
R2
C3
6
V
FB
Put the compensator zero at 8kHz, and put the compensator pole
at either half of switching frequency or ESR zero. We choose
500kHz here, then the compensator capacitors are:
-
V
COMP
R3
GM
V
REF
+
C = 220pF, C = 3pF (There is approximately 3pF parasitic
6
7
R6
capacitance from V
to GND; Therefore, C optional).
C7
COMP
7
C6
Figure 43 shows the simulated voltage loop gain. It is shown that
it has 90kHz loop bandwidth with 70° phase margin and 10dB
gain margin.
60
45
30
15
0
FIGURE 42. TYPE II COMPENSATOR
Figure 42 shows the type II compensator and its transfer function
is expressed as Equation 14:
S
S
------------
------------
1 +
1 +
ˆ
v
(EQ. 14)
GM
comp
cz1
cz2
---------------- -------------------- ---------------------------------------------------------
A S=
=
v
ˆ
C
+ C
S
v
6
7
FB
---------
S 1 +
cp
where,
-15
-30
C
+ C
7
1
1
6
--------------
--------------
----------------------
=
=
,
=
cp
cz1
cz2
R C
R C
R C C
6 6 7
6
6
2
3
100
1k
10k
100k
1M
f (fi)
Compensator design goal:
High DC gain
1
1
180
-- ------
to
f
Loop bandwidth f :
c
s
4
10
150
120
90
60
30
0
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is as follows:
1
--------------
= 1to3
cz1
Put compensator zero
R C
o
o
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower. An
optional zero can boost the phase margin. CZ2 is a zero due to
R and C
100
1k
10k
100k
1M
2
3
1
f (fi)
--------------
= 5to8
cz2
Put compensator zero
R C
2
3
FIGURE 43. SIMULATED LOOP GAIN
The loop gain T (S) at crossover frequency of f has unity gain.
v
c
Therefore, the compensator resistance R is determined by
6
Equation 15.
2f V C R
o o t
(EQ. 15)
c
---------------------------------
=
R
6
GM V
FB
where GM is the sum of the trans-conductance, g , of the
m
voltage error amplifier in each phase. Compensator capacitor C6
is then given by Equation 16.
1
R
1
--------------------
------------------------
C
=
, C
=
7
(EQ. 16)
6
2R f
6
cz1
6 esr
FN7812 Rev 3.00
March 24, 2014
Page 18 of 20
ISL8023, ISL8024
feedback trace away from these noisy traces. The input capacitor
should be placed as close as possible to the VIN pin. The ground
of input and output capacitors should be connected as closely as
possible. The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. It is recommended to add at
least 5 vias ground connection within the pad for the best
thermal relief.
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For ISL8023, ISL8024,
the power loop is composed of the output inductor L’s, the output
capacitor C , the PHASE’s pins, and the PGND pin. It is
OUT
necessary to make the power loop as small as possible and the
connecting traces among them should be direct, short and wide.
The switching node of the converter, the PHASE pins, and the
traces connected to the node are very noisy, so keep the voltage
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN7812.3
CHANGE
March 24, 2014
Electrical spec table: “OUTPUT REGULATION” on page 6, under VFB Bias Current section, changed the typical
value from 0.1µA to 0.01µA.
Added ISL8023EVAL3Z, ISL8024EVAL3Z and ISL8023AEVAL3Z, ISL8024AEVAL3Z Evaluation Boards to
Ordering Information table on page 4.
May 7, 2012
FN7812.2
Page 2: Updated with new silkscreen to show the correct placement of U1-Pin1.
Page 3: Pin Descriptions , COMP, FB Changed the description from "Must connect COMP to SGND in internal
compensation mode " to "Recommend connect COMP to SGND in internal compensation mode".
Updated Figure 2 to show the COMP pin tied to GND
Page 18: Put compensator zero cz2 = (5to8) R0C0" changed to "..... R2C3"
Figure 43, Simulated Loop Gain: Added Y-axis title to the top graph: GAIN (VLOOP(S(fi)))
February 15, 2012
February 1, 2012
December 22, 2011
FN7812.1
FN7812.0
In the “Absolute Maximum Ratings” on page 6, changed “VIN” from “-0.3V” to “-0.3V to 6.5V (DC) or 7V (20ms)"
Revised description, Features and Applications on page 1. Added Figure 2.
Initial Release.
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FN7812 Rev 3.00
March 24, 2014
Page 19 of 20
ISL8023, ISL8024
Package Outline Drawing
L16.3x3D
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 1.50
3.00
6
A
12X 0.50
PIN #1
INDEX AREA
B
13
16
6
PIN 1
INDEX AREA
12
1
1.60 SQ
4
9
(4X)
0.15
0.10 M C A B
16X 0.23±0.05
8
5
16X 0.40±0.10
BOTTOM VIEW
TOP VIEW
4
SEE DETAIL “X”
0.10 C
C
0.75 ±0.05
0.08 C
SIDE VIEW
(12X 0.50)
(2.80 TYP) ( 1.60)
(16X 0.23)
5
0 . 2 REF
C
(16X 0.60)
0 . 02 NOM.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
JEDEC reference drawing: MO-220 WEED.
7.
FN7812 Rev 3.00
March 24, 2014
Page 20 of 20
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Compact Synchronous Buck Regulator; TQFN16; Temp Range: -40° to 85°C
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