ISL8105ACBZ_技术文档

ISL8105, ISL8105A

®

Data Sheet

June 6, 2006

FN6306.0

5V or 12V Single Synchronous Buck

Features

Pulse-Width Modulation (PWM) Controller

• Operates from +5V or +12V Supply Voltage (for bias)

- 1.0V to 12V V Input Range

The ISL8105 makes simple work out of implementing a

complete control and protection scheme for a DC/DC

stepdown converter driving N-channel MOSFETs in a

synchronous buck topology. Since it can work with either 5V

or 12V supplies, this one IC can be used in a wide variety of

applications within a system. The ISL8105 integrates the

control, gate drivers, output adjustment, monitoring and

protection functions into a single 8 Ld SOIC package.

IN

- 0.6V to V Output Range

IN

- Integrated Gate Drivers use V

(5V - 12V)

CC

- 0.6V Internal Reference; ±1.0% tolerance

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

- Drives N-Channel MOSFETs

• Fast Transient Response

The ISL8105 provides single feedback loop, voltage-mode

control with fast transient response. The output voltage can

be precisely regulated to as low as 0.6V, with a maximum

tolerance of ±1.0% over temperature and line voltage

variations. A selectable fixed frequency oscillator (ISL8105

for 300kHz; ISL8105A for 600kHz) reduces design

complexity, while balancing typical application cost and

efficiency.

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Cycle

• Lossless, Programmable Overcurrent Protection

- Uses Lower MOSFET’s r

DS(ON)

• Small Converter Size in 8 Ld SOIC

- 300kHz or 600kHz Fixed Frequency Oscillator

- Fixed Internal Soft-Start, Capable into a Pre-biased

Load

The error amplifier features a 20MHz gain-bandwidth

product and 9V/μs slew rate which enables high converter

bandwidth for fast transient performance. The resulting

PWM duty cycles range from 0% to 100%.

- Integrated Boot Diode

- Enable/Shutdown Function on COMP/SD Pin

- Output Current Sourcing and Sinking

Protection from overcurrent conditions is provided by

• Pb-Free Plus Anneal Available (RoHS Compliant)

monitoring the r

of the lower MOSFET to inhibit PWM

DS(ON)

operation appropriately. This approach simplifies the

implementation and improves efficiency by eliminating the

need for a current sense resistor.

Applications

• Power Supplies for Microprocessors or Peripherals

- PCs, Embedded Controllers, Memory Supplies

- DSP and Core Communications Processor Supplies

Ordering Information

PART NUMBER

(Note)

PART

TEMP.

PACKAGE PKG.

• Subsystem Power Supplies

MARKING RANGE (°C) (Pb-Free) DWG. #

- PCI, AGP; Graphics Cards; Digital TV

ISL8105CBZ

(300kHz)

8105CBZ

0 to 70

8 Ld SOIC M8.15

- SSTL-2 and DDR/DDR2/DDR3 SDRAM Bus

Termination Supply

ISL8105ACBZ 8105ACBZ

(600kHz)

• Cable Modems, Set Top Boxes, and DSL Modems

• Industrial Power Supplies; General Purpose Supplies

• 5V or 12V-Input DC/DC Regulators

ISL8105IBZ

(300kHz)

8105IBZ

-40 to 85 8 Ld SOIC M8.15

ISL8105AIBZ

(600kHz)

8105AIBZ

• Low-Voltage Distributed Power Supplies

ISL8105EVAL1 Evaluation Board

Pinout

ISL8105 (SOIC)

TOP VIEW

Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

BOOT

UGATE

1

2

3

4

8

7

6

5

PHASE

COMP/SD

FB

GND

LGATE/OCSET

VCC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL8105, ISL8105A

Block Diagram

VCC

D

BOOT

INTERNAL

POR AND

BOOT

+

SAMPLE

AND

HOLD

REGULATOR

SOFT-START

-

OC

UGATE

COMPARATOR

5V int.

21.5μA

PHASE

20kΩ

ERROR

AMP

PWM

COMPARATOR

INHIBIT

TO

GATE

CONTROL

LOGIC

LGATE/OCSET

0.6V

+

-

+

-

PWM

DIS

VCC

FB

LGATE/OCSET

5V int.

0.4V

DIS

+

-

OSCILLATOR

20μA

COMP/SD

FIXED 300 (or 600)kHz

GND

Typical Application

V

CC

5V or 12V

IN

1V-12V

C

BULK

C

HF

VCC

C

DCPL

BOOT

5

1

C

BOOT

PHASE

UGATE

ISL8105

8

2

COMP/SD

7

L

OUT

C

+V

O

R

F

C

LGATE/OCSET

I

4

6

3

OUT

C

F

GND

FB

R

OCSET

Type II

compensation

shown

R

OFFSET

R

S

FN6306.0

June 6, 2006

2

ISL8105, ISL8105A

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V

. . . . . . . . . . . . . . . . . . . . GND - 0.3V to 36V

Thermal Resistance

θ

(°C/W)

95

CC

JA

BOOT Voltage, V

BOOT

SOIC Package (Note 1) . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature

(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature

UGATE Voltage V

. . . . . . . . V

- 0.3V to V

GND - 0.3V to V

+ 0.3V

UGATE

LGATE/OCSET Voltage, V

PHASE

BOOT

LGATE/OCSET

. . . . . . . . . .GND - 0.3V to V

CC

PHASE Voltage, V

PHASE

Upper Driver Supply Voltage, V

BOOT

- V

. . . . . . . . . . . . .15V

BOOT

. . . . . . . . . . . . . . . . . . . . . . . . . . .24V

PHASE

Clamp Voltage, V

- V

BOOT

CC

(Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

FB, COMP/SD Voltage. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6V

ESD Classification, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV

ESD Classification, MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150V

ESD Classification, CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV

Operating Conditions

Supply Voltage, V

. . . . +5V ±10%, +12V ±20%, or 6.5V to 14.4V

CC

Ambient Temperature Range

ISL8105C, ISL8105AC. . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

ISL8105I, ISL8105AI . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. Guaranteed by design; not production tested

Electrical Specifications Test Conditions: V = 12V, T = 0 to 85°C, Unless Otherwise Noted.

CC

J

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V

SUPPLY CURRENT

CC

Input Bias Supply Current

I

V

= 12V; disabled

CC

4

5.2

7

mA

VCC

POWER-ON RESET

Rising V

POR Threshold

V

3.9

4.1

4.3

V

CC

POR

V

POR Threshold Hysteresis

0.30

0.35

0.40

CC

OSCILLATOR

Switching Frequency

f

ISL8105C

ISL8105I

270

240

540

510

300

600

1.5

330

660

kHz

OSC

ISL8105AC

ISL8105AI

Ramp Amplitude (Note 2)

REFERENCE

ΔV

V

P-P

OSC

Reference Voltage Tolerance

ISL8105C

ISL8105I

-1.0

-1.5

-

+1.0

+1.5

%

V

Nominal Reference Voltage

ERROR AMPLIFIER

V

0.600

REF

DC Gain (Note 2)

GAIN

GBWP

SR

-

96

20

9

-

dB

Gain-Bandwidth Product (Note 2)

Slew Rate (Note 2)

MHz

V/μs

GATE DRIVERS

Upper Gate Source Impedance

Upper Gate Sink Impedance

Lower Gate Source Impedance

Lower Gate Sink Impedance

Upper Gate Source Impedance

R

V

= 14.5V; I = 50mA

= 4.25V; I = 50mA

-

3.0

2.7

2.4

2.0

3.5

-

Ω

UG-SRCh

CC

UG-SNKh

R

LG-SRCh

LG-SNKh

R

UG-SRCl

FN6306.0

June 6, 2006

3

ISL8105, ISL8105A

Electrical Specifications Test Conditions: V = 12V, T = 0 to 85°C, Unless Otherwise Noted. (Continued)

CC

J

PARAMETER

Upper Gate Sink Impedance

Lower Gate Source Impedance

Lower Gate Sink Impedance

PROTECTION/DISABLE

OCSET Current Source

SYMBOL

TEST CONDITIONS

MIN

TYP

2.7

MAX

UNITS

R

V

= 4.25V; I = 50mA

-

Ω

UG-SNKl

CC

R

V

2.75

2.1

LG-SRCl

LG-SNKl

R

I

ISL8105C; LGATE/OCSET = 0V

ISL8105I; LGATE/OCSET = 0V

19.5

18.0

21.5

23.5

μA

V

OCSET

Disable Threshold (COMP/SD pin)

V

0.375

0.400

0.425

DISABLE

Use COMP/SD, in combination with the FB pin, to compensate

the voltage-control feedback loop of the converter.

Functional Pin Description

V

(Pin 5)

CC

Pulling COMP/SD low (V

= 0.4V nominal) will

DISABLE

This pin provides the bias supply for the ISL8105, as well as

the lower MOSFET’s gate, and the BOOT voltage for the

upper MOSFET’s gate. An internal 5V regulator will supply

shut-down (disable) the controller, which causes the

oscillator to stop, the LGATE and UGATE outputs to be held

low, and the soft-start circuitry to re-arm. The external pull-

down device will initially need to overcome up to 5mA of

COMP/SD output current. However, once the IC is disabled,

the COMP output will also be disabled, so only a 20µA

current source will continue to draw current.

bias if V

rises above 6.5V (but the LGATE/OCSET and

CC

BOOT will still be sourced by V ). Connect a well-

CC

decoupled 5V or 12V supply to this pin.

FB (Pin 6)

This pin is the inverting input of the internal error amplifier.

Use FB, in combination with the COMP/SD pin, to

compensate the voltage-control feedback loop of the

converter. A resistor divider from the output to GND is used

to set the regulation voltage.

When the pull-down device is released, the COMP/SD pin

will start to rise, at a rate determined by the 20µA charging

up the capacitance on the COMP/SD pin. When the

COMP/SD pin rises above the V

trip point, the

DISABLE

ISL8105 will begin a new Initialization and soft-start cycle.

GND (Pin 3)

LGATE/OCSET (Pin 4)

This pin represents the signal and power ground for the IC.

Tie this pin to the ground island/plane through the lowest

impedance connection available.

Connect this pin to the gate of the lower MOSFET; it provides

the PWM-controlled gate drive (from V ). This pin is also

CC

monitored by the adaptive shoot-through protection circuitry to

determine when the lower MOSFET has turned off.

PHASE (Pin 8)

Connect this pin to the source of the upper MOSFET, and

the drain of the lower MOSFET. It is used as the sink for the

UGATE driver, and to monitor the voltage drop across the

lower MOSFET for overcurrent protection. This pin is also

monitored by the adaptive shoot-through protection circuitry

to determine when the upper MOSFET has turned off.

During a short period of time following Power-On Reset

(POR) or shut-down release, this pin is also used to

determine the overcurrent threshold of the converter.

Connect a resistor (R

) from this pin to GND. See the

OCSET

Overcurrent Protection section for equations. An

overcurrent trip cycles the soft-start function, after two

dummy soft-start time-outs. Some of the text describing the

LGATE function may leave off the OCSET part of the name,

when it is not relevant to the discussion.

UGATE (Pin 2)

Connect this pin to the gate of upper MOSFET; it provides

the PWM-controlled gate drive. It is also monitored by the

adaptive shoot-through protection circuitry to determine

when the upper MOSFET has turned off.

Functional Description

Initialization (POR and OCP sampling)

BOOT (Pin 1)

Figure 1 shows a simplified timing diagram. The Power-On-

Reset (POR) function continually monitors the bias voltage at

This pin provides ground referenced bias voltage to the

upper MOSFET driver. A bootstrap circuit is used to create a

voltage suitable to drive an N-channel MOSFET (equal to

the V

pin. Once the rising POR threshold is exceeded

CC

~4V nominal), the POR function initiates the

(V

POR

V

minus the on-chip BOOT diode voltage drop), with

CC

Overcurrent Protection (OCP) sample and hold operation

(while COMP/SD is ~1V). When the sampling is complete,

respect to PHASE.

V

begins the soft-start ramp.

OUT

COMP/SD (Pin 7)

This is a multiplexed pin. During soft-start and normal converter

operation, this pin represents the output of the error amplifier.

FN6306.0

June 6, 2006

4

ISL8105, ISL8105A

If the COMP/SD pin is held low during power-up, that will just

delay the initialization until it is released, and the COMP/SD

sets up a voltage that will represent the OCSET trip point. At

T2, there is a variable time period for the OCP sample and hold

operation (0 to 3.4ms nominal; the longer time occurs with the

higher overcurrent setting). The sample and hold uses a digital

counter and DAC to save the voltage, so the stored value does

voltage is above the V

DISABLE

trip point.

V

(2V/DIV)

not degrade, for as long as the V

is above V . See the

CC

POR

Overcurrent Protection section for more details on the

equations and variables. Upon the completion of sample and

hold at T3, the soft-start operation is initiated, and the output

voltage ramps up between T4 and T5.

Soft-Start and Pre-Biased Outputs

~4V POR

Functionally, the soft-start internally ramps the reference on the

non-inverting terminal of the error amp from zero to 0.6V in a

nominal 6.8ms The output voltage will thus follow the ramp,

from zero to final value, in the same 6.8ms (the actual ramp

V

(1V/DIV)

OUT

COMP/SD (1V/DIV)

seen on the V

will be less than the nominal time, due to

OUT

GND>

ND

some initialization timing, between T3 and T4).

The ramp is created digitally, so there will be 64 small discrete

steps. There is no simple way to change this ramp rate

externally, and it is the same for either frequency version of the

IC (300kHz or 600kHz).

FIGURE 1. POR AND SOFT-START OPERATION

Figure 2 shows a typical power-up sequence in more detail.

The initialization starts at T0, when either V rises above

CC

, or the COMP/SD pin is released (after POR). The

V

After an initialization period (T3 to T4), the error amplifier

(COMP/SD pin) is enabled, and begins to regulate the

converter’s output voltage during soft-start. The oscillator’s

triangular waveform is compared to the ramping error amplifier

voltage. This generates PHASE pulses of increasing width that

charge the output capacitors. When the internally generated

soft-start voltage exceeds the reference voltage (0.6V), the soft-

start is complete, and the output should be in regulation at the

expected voltage. This method provides a rapid and controlled

output voltage rise; there is no large inrush current charging the

output capacitors. The entire start-up sequence from POR

typically takes up to 17ms; up to 10.2ms for the delay and OCP

sample, and 6.8ms for the soft-start ramp.

POR

COMP/SD will be pulled up by an internal 20µA current

source, but the timing will not begin until the COMP/SD

exceeds the V

trip point (at T1). The external

DISABLE

capacitance of the disabling device, as well as the

compensation capacitors, will determine how quickly the

20µA current source will charge the COMP/SD pin. With

typical values, it should add a small delay compared to the

soft-start times. The COMP/SD will continue to ramp to ~1V.

LGATE

STARTS

SWITCHING

Figure 3 shows the normal curve in blue; initialization begins

at T0, and the output ramps between T1 and T2. If the output

is pre-biased to a voltage less than the expected value, as

shown by the magenta curve, the ISL8105 will detect that

condition. Neither MOSFET will turn on until the soft-start

COMP/SD (0.25V/DIV)

0.4V

ramp voltage exceeds the output; V

starts seamlessly

OUT

ramping from there. If the output is pre-biased to a voltage

above the expected value, as in the red curve, neither

MOSFET will turn on until the end of the soft-start, at which

time it will pull the output voltage down to the final value. Any

resistive load connected to the output will help pull down the

voltage (at the RC rate of the R of the load and the C of the

output capacitance).

V

LGATE/OCSET (0.25V/DIV)

OUT

(0.5V/DIV)

GND>

ND

3.4ms

0 - 3.4ms

6.8ms

T0 T1

T2

T3 T4

T5

FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION

From T1, there is a nominal 6.8ms delay, which allows the V

pin to exceed 6.5V (if rising up towards 12V), so that the

CC

internal bias regulator can turn on cleanly. At the same time, the

LGATE/OCSET pin is initialized, by disabling the LGATE driver

and drawing I

OCSET

(nominal 21.5μA) through R

. This

OCSET

FN6306.0

June 6, 2006

5

ISL8105, ISL8105A

source to develop a voltage across R

. The ISL8105

OCSET

samples this voltage (which is referenced to the GND pin) at

the LGATE/OCSET pin, and holds it in a counter and DAC

combination. This sampled voltage is held internally as the

Overcurrent Set Point, for as long as power is applied, or

until a new sample is taken after coming out of a shut-down.

V

OVER-CHARGED

OUT

The actual monitoring of the lower MOSFET’s on-resistance

starts 200ns (nominal) after the edge of the internal PWM

logic signal (that creates the rising external LGATE signal).

This is done to allow the gate transition noise and ringing on

the PHASE pin to settle out before monitoring. The monitoring

ends when the internal PWM edge (and thus LGATE) goes

low. The OCP can be detected anywhere within the above

window.

PRE-BIASED

NORMAL

V

OUT

GND>

If the regulator is running at high UGATE duty cycles (around

75% for 600kHz or 87% for 300kHz operation), then the

LGATE pulse width may not be wide enough for the OCP to

T0

T1

T2

FIGURE 3. SOFT-START WITH PRE-BIAS

properly sample the r

. For those cases, if the LGATE

DS(ON)

If the V to the upper MOSFET drain is from a different

IN

is too narrow (or not there at all) for 3 consecutive pulses,

then the third pulse will be stretched and/or inserted to the

425ns minimum width. This allows for OCP monitoring every

third pulse under this condition. This can introduce a small

pulse-width error on the output voltage, which will be

corrected on the next pulse; and the output ripple voltage will

have an unusual 3-clock pattern, which may look like jitter. If

the OCP is disabled (by choosing a too-high value of

supply that comes up after V , the soft-start would go

CC

through its cycle, but with no output voltage ramp. When V

IN

turns on, the output would follow the ramp of the V (at

IN

close to 100% duty cycle, with COMP/SD pin >4V), from

zero up to the final expected voltage. If V is too fast, there

IN

may be excessive inrush current charging the output

capacitors (only the beginning of the ramp, from zero to

V

matters here). If this is not acceptable, then consider

R

, or no resistor at all), then the pulse stretching

OUT

OCSET

changing the sequencing of the power supplies, or sharing

the same supply, or adding sequencing logic to the

feature is also disabled. Figure 4 illustrates the LGATE pulse

width stretching, as the width gets smaller.

COMP/SD pin to delay the soft-start until the V supply is

IN

> 425 ns

ready (see Input Voltage Considerations).

If the IC is disabled after soft-start (by pulling COMP/SD pin

low), and then enabled (by releasing the COMP/SD pin),

then the full initialization (including OCP sample) will take

place. However, that there is no new OCP sampling during

overcurrent retries.

= 425 ns

< 425 ns

<< 425 ns

If the output is shorted to GND during soft-start, the OCP will

handle it, as described in the next section.

Overcurrent Protection (OCP)

The overcurrent function protects the converter from a shorted

output by using the lower MOSFET’s on-resistance, r

,

DS(ON)

to monitor the current. A resistor (R ) programs the

OCSET

FIGURE 4. LGATE PULSE STRETCHING

overcurrent trip level (see Typical Application diagram). This

method enhances the converter’s efficiency and reduces cost

by eliminating a current sensing resistor. If overcurrent is

detected, the output immediately shuts off, it cycles the soft-

start function in a hiccup mode (2 dummy soft-start time-outs,

then up to one real one) to provide fault protection. If the

shorted condition is not removed, this cycle will continue

indefinitely.

The overcurrent function will trip at a peak inductor current

(I

determined by:

PEAK)

2 × I

xR

OCSET

r

I

= ----------------------------------------------------------

PEAK

DS(ON)

where I

is the internal OCSET current source (21.5μA

OCSET

Following POR (and 6.8ms delay), the ISL8105 initiates the

Overcurrent Protection sample and hold operation. The

LGATE driver is disabled to allow an internal 21.5μA current

typical). The scale factor of 2 doubles the trip point of the

MOSFET voltage drop, compared to the setting on the

FN6306.0

June 6, 2006

6

ISL8105, ISL8105A

R

resistor. The OC trip point varies in a system mainly

OCSET

due to the MOSFET’s r

variations (over process,

DS(ON)

current and temperature). To avoid overcurrent tripping in

the normal operating load range, find the R

from the equation above with:

resistor

OCSET

internal soft-start ramp

1. The maximum r

temperature.

at the highest junction

DS(ON)

V

OUT

(0.5V/DIV)

2. The minimum I

3. Determine I

from the specification table.

OCSET

(ΔI)

2

I

> I

+ ----------

,

OUT(MAX)

for

PEAK

where ΔI is the output inductor ripple current.

For an equation for the ripple current see Output Inductor

Selection.

GND>

6.8ms

0 - 6.8ms

6.8ms

The range of allowable voltages detected (2 * I

*

OCSET

R

) is 0 to 475mV; but the practical range for typical

OCSET

MOSFETs is typically in the 20 to 120mV ballpark (500 to

3000Ω). If the voltage drop across R is set too low,

T0

T1

T2

T0

T1

FIGURE 5. OVERCURRENT RETRY OPERATION

OCSET

that can cause almost continuous OCP tripping and retry. It

would also be very sensitive to system noise and inrush

current spikes, so it should be avoided. The maximum

Figure 5 shows the output response during a retry of an

output shorted to GND. At time T0, the output has been

turned off, due to sensing an overcurrent condition. There

are two internal soft-start delay cycles (T1 and T2) to allow

the MOSFETs to cool down, to keep the average power

dissipation in retry at an acceptable level. At time T2, the

output starts a normal soft-start cycle, and the output tries to

ramp. If the short is still applied, and the current reaches the

OCSET trip point any time during soft-start ramp period, the

output will shut off, and return to time T0 for another delay

cycle. The retry period is thus two dummy soft-start cycles

plus one variable one (which depends on how long it takes to

trip the sensor each time). Figure 5 shows an example

where the output gets about half-way up before shutting

down; therefore, the retry (or hiccup) time will be around

17ms. The minimum should be nominally 13.6ms and the

maximum 20.4ms. If the short condition is finally removed,

the output should ramp up normally on the next T2 cycle.

usable setting is around 0.2V across R

(0.4V across

OCSET

the MOSFET); values above that might disable the

protection. Any voltage drop across R that is greater

OCSET

than 0.3V (0.6V MOSFET trip point) will disable the OCP.

The preferred method to disable OCP is simply to remove

the resistor; that will be detected that as no OCP.

Note that conditions during power-up or during a retry may

look different than normal operation. During power-up in a

12V system, the IC starts operation just above 4V; if the

supply ramp is slow, the soft-start ramp might be over well

before 12V is reached. So with lower gate drive voltages, the

r

of the MOSFETs will be higher during power-up,

DS(ON)

effectively lowering the OCP trip. In addition, the ripple

current will likely be different at lower input voltage.

Another factor is the digital nature of the soft-start ramp. On

each discrete voltage step, there is in effect a small load

transient, and a current spike to charge the output

capacitors. The height of the current spike is not controlled; it

is affected by the step size of the output, the value of the

output capacitors, as well as the IC error amp compensation.

So it is possible to trip the overcurrent with inrush current, in

addition to the normal load and ripple considerations.

Starting up into a shorted load looks the same as a retry into

that same shorted load. In both cases, OCP is always

enabled during soft-start; once it trips, it will go into retry

(hiccup) mode. The retry cycle will always have two dummy

time-outs, plus whatever fraction of the real soft-start time

passes before the detection and shutoff; at that point, the

logic immediately starts a new two dummy cycle time-out.

FN6306.0

June 6, 2006

7

ISL8105, ISL8105A

change the sequencing of the supplies, or use the

COMP/SD pin to disable V until both supplies are ready.

Output Voltage Selection

OUT

The output voltage can be programmed to any level between

the 0.6V internal reference, up to the V supply. The

ISL8105 can run at near 100% duty cycle at zero load, but

IN

Figure 6 shows a simple sequencer for this situation. If V

CC

will turn

powers up first, Q1 will be off, and R3 pulling to V

CC

the r

of the upper MOSFET will effectively limit it to

DS(ON)

Q2 on, keeping the ISL8105 in shut-down. When V turns

IN

something less as the load current increases. In addition, the

OCP (if enabled) will also limit the maximum effective duty

cycle.

on, the resistor divider R1 and R2 determines when Q1 turns

on, which will turn off Q2, and release the shut-down. If V

IN

powers up first, Q1 will be on, turning Q2 off; so the ISL8105

will start-up as soon as V comes up. The V trip

CC DISABLE

An external resistor divider is used to scale the output

voltage relative to the internal reference voltage, and feed it

back to the inverting input of the error amp. See the Typical

point is 0.4V nominal, so a wide variety of NFET’s or NPN’s

or even some logic IC’s can be used as Q1 or Q2; but Q2

must be low leakage when off (open-drain or open-collector)

so as not to interfere with the COMP output. Q2 should also

be placed near the COMP/SD pin.

Application schematic on page 2 for more detail; R is the

S

upper resistor; R

(shortened to R below) is the

OFFSET

O

lower one. The recommended value for R is 1 - 5kΩ (±1%

S

for accuracy) and then R

is chosen according to the

OFFSET

V

CC

IN

equation below. Since R is part of the compensation circuit

S

(see Feedback Compensation section), it is often easier to

R

3

R

change R

to change the output voltage; that way the

1

OFFSET

to COMP/SD

compensation calculations do not need to be repeated. If

= 0.6V, then R can be left open. Output

voltages less than 0.6V are not available.

V

OUT

OFFSET

R

2

Q

2

Q

1

(R + R

)

O

S

---------------------------

= 0.6V •

V

R

OUT

FIGURE 6. SEQUENCER CIRCUIT

R

O

R

• 0.6V

S

= ----------------------------------

The V range can be as low as ~1V (for V

IN

as low as the

OUT

O

V

– 0.6V

OUT

0.6V reference). It can be as high as 20V (for V

just

OUT

below V ). There are some restrictions for running high V

voltage.

IN

Input Voltage Considerations

The Typical Application diagram on page 2 shows a

The first consideration for high V is the maximum BOOT

IN

standard configuration where V

is either 5V (±10%) or

CC

12V (±20%); in each case, the gate drivers use the V

voltage of 36V. The V (as seen on PHASE) plus V

(boot

IN

CC

voltage - minus the diode drop), plus any ringing (or other

transients) on the BOOT pin must be less than 36V. If V is

voltage for LGATE and BOOT/UGATE. In addition, V

allowed to work anywhere from 6.5V up to the 14.4V

is

IN

20V, that limits V

CC

plus ringing to 16V.

maximum. The V

range between 5.5V and 6.5V is NOT

CC

The second consideration for high V is the maximum

IN

allowed for long-term reliability reasons, but transitions

through it to voltages above 6.5V are acceptable.

(BOOT - V ) voltage; this must be less than 24V. Since

CC

BOOT = V + V

IN CC

must be <24V. So based on typical circuits, a 20V maximum

+ ringing, that reduces to (V + ringing)

IN

There is an internal 5V regulator for bias; it turns on between

5.5 and 6.5V; some of the delay after POR is there to allow a

typical power supply to ramp up past 6.5V before the soft-

start ramps begins. This prevents a disturbance on the

output, due to the internal regulator turning on or off. If the

transition is slow (not a step change), the disturbance should

be minimal. So while the recommendation is to not have the

output enabled during the transition through this region, it

may be acceptable. The user should monitor the output for

their application, to see if there is any problem.

V

is a good starting assumption; the user should verify the

IN

ringing in their particular application.

Another consideration for high V is duty cycle. Very low

IN

duty cycles (such as 20V in to 1.0V out, for 5% duty cycle)

require component selection compatible with that choice

(such as low r

lower MOSFET, and a good LC output

DS(ON)

filter). At the other extreme (for example, 20V in to 12V out),

the upper MOSFET needs to be low r . In addition, if

DS(ON)

the duty cycle gets too high, it can affect the overcurrent

sample time. In all cases, the input and output capacitors

and both MOSFETs must be rated for the voltages present.

The V to the upper MOSFET can share the same supply

IN

as V , but can also run off a separate supply or other

CC

sources, such as outputs of other regulators. If V

CC

powers

up first, and the V is not present by the time the

IN

initialization is done, then the soft-start will not be able to

ramp the output, and the output will later follow part of the

V

ramp when it is applied. If this is not desired, then

IN

FN6306.0

June 6, 2006

8

ISL8105, ISL8105A

Switching Frequency

V

IN

The switching frequency is either a fixed 300 or 600kHz,

depending on the part number chosen (ISL8105 is 300kHz;

ISL8105A is 600kHz; the generic name “ISL8105” may apply

to either in the rest of this document, except when choosing

the frequency). However, all of the other timing mentioned

(POR delay, OCP sample, soft-start, etc.) is independent of

the clock frequency (unless otherwise noted).

ISL8105

UGATE

Q

1

L

O

V

OUT

PHASE

C

IN

2

LGATE/OCSET

C

O

BOOT Refresh

In the event that the UGATE is on for an extended period of

time, the charge on the boot capacitor can start to sag,

RETURN

FIGURE 7. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

raising the r

of the upper MOSFET. The ISL8105 has

DS(ON)

a circuit that detects a long UGATE on-time (nominal 100µs),

and forces the LGATE to go high for one clock cycle, which

will allow the boot capacitor some time to recharge.

Separately, the OCP circuit has an LGATE pulse stretcher

(to be sure the sample time is long enough), which can also

help refresh the boot. But if OCP is disabled (no current

sense resistor), the regular boot refresh circuit will still be

active.

Figure 7 shows the critical power components of the converter.

To minimize the voltage overshoot, the interconnecting wires

indicated by heavy lines should be part of a ground or power

plane in a printed circuit board. The components shown should

be located as close together as possible. Please note that the

capacitors C and C may each represent numerous physical

IN

O

capacitors. For best results, locate the ISL8105 within 1 inch of

the MOSFETs, Q and Q . The circuit traces for the MOSFET

gate and source connections from the ISL8105 must be sized

1

2

Current Sinking

The ISL8105 incorporates a MOSFET shoot-through

protection method which allows a converter to sink current

as well as source current. Care should be exercised when

designing a converter with the ISL8105 when it is known that

the converter may sink current.

to handle up to 1A peak current.

+V

IN

BOOT

Q

1

L

O

C

BOOT

V

OUT

PHASE

VCC

When the converter is sinking current, it is behaving as a

boost converter that is regulating its input voltage. This

ISL8105

C

O

+V

Q

2

CC

means that the converter is boosting current into the V

CC

LGATE/OCSET

rail, which supplies the bias voltage to the ISL8105. If there

is nowhere for this current to go, such as to other distributed

C

VCC

GND

loads on the V

device, or other methods, the capacitance on the V

CC

rail, through a voltage limiting protection

bus

CC

will absorb the current. This situation will allow voltage level

of the V rail to increase. If the voltage level of the rail is

FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

CC

boosted to a level that exceeds the maximum voltage rating

of the ISL8105, then the IC will experience an irreversible

failure and the converter will no longer be operational.

Ensuring that there is a path for the current to follow other

than the capacitance on the rail will prevent this failure

mode.

Figure 8 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

current paths on the COMP/SD pin and locate the resistor,

R

close to the COMP/SD pin because the internal

OSCET

current source is only 20μA. Provide local V

decoupling

CC

and GND pins. Locate the capacitor, C

Application Guidelines

between V

CC

BOOT

as close as practical to the BOOT and PHASE pins. All

components used for feedback compensation (not shown)

should be located as close to the IC as practical.

Layout Considerations

As in any high frequency switching converter, layout is very

important. Switching current from one power device to another

can generate voltage transients across the impedances of the

interconnecting bond wires and circuit traces. These

interconnecting impedances should be minimized by using

wide, short printed circuit traces. The critical components

should be located as close together as possible, using ground

plane construction or single point grounding.

Feedback Compensation

This section highlights the design consideration for a voltage-

mode controller requiring external compensation. To address a

broad range of applications, a type-3 feedback network is

recommended, as shown in the top part of Figure 9.

FN6306.0

June 6, 2006

9

ISL8105, ISL8105A

Figure 9 also highlights the voltage-mode control loop for a

synchronous-rectified buck converter, applicable to the

ISL8105 circuit. The output voltage (V ) is regulated to the

between the closed loop phase at F and 180°. The

0dB

equations that follow relate the compensation network’s poles,

zeros and gain to the components (R1, R2, R3, C1, C2, and

C3) in Figure 9. Use the following guidelines for locating the

poles and zeros of the compensation network:

OUT

. The error amplifier output (COMP pin

reference voltage, V

REF

voltage) is compared with the oscillator (OSC) modified saw-

tooth wave to provide a pulse-width modulated wave with an

4. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate

amplitude of V at the PHASE node. The PWM wave is

IN

value for R2 for desired converter bandwidth (F ). If

0

smoothed by the output filter (L and C). The output filter

capacitor bank’s equivalent series resistance is represented by

the series resistor E.

setting the output voltage via an offset resistor connected

to the FB pin, Ro in Figure 9, the design procedure can

be followed as presented.

V

⋅ R1 ⋅ F

0

OSC

R2 = ---------------------------------------------

⋅ V ⋅ F

LC

d

C2

MAX

IN

5. Calculate C1 such that F is placed at a fraction of the F

,

Z1 LC

C3

R3

at 0.1 to 0.75 of F (to adjust, change the 0.5 factor to

LC

R2

C1

COMP

desired number). The higher the quality factor of the output

filter and/or the higher the ratio F /F , the lower the F

CE LC Z1

-

frequency (to maximize phase boost at F ).

LC

R1

FB

+

Ro

E/A

1

C1 = -----------------------------------------------

2π ⋅ R2 ⋅ 0.5 ⋅ F

LC

VREF

6. Calculate C2 such that F is placed at F

P1

.

CE

C1

C2 = ---------------------------------------------------------

V

OSCILLATOR

2π ⋅ R2 ⋅ C1 ⋅ F

– 1

OUT

CE

V

IN

7. Calculate R3 such that F is placed at F . Calculate C3

V

Z2

LC

OSC

PWM

CIRCUIT

such that F is placed below F

(typically, 0.5 to 1.0

P2 SW

times F ). F

represents the switching frequency.

SW

Change the numerical factor to reflect desired placement

L

D

UGATE

PHASE

LGATE

HALF-BRIDGE

DRIVE

of this pole. Placement of F lower in frequency helps

P2

reduce the gain of the compensation network at high

frequency, in turn reducing the HF ripple component at

the COMP pin and minimizing resultant duty cycle jitter.

C

E

R1

R3 = ---------------------

1

C3 = -------------------------------------------------

F

SW

2π ⋅ R3 ⋅ 0.7 ⋅ F

------------ – 1

SW

F

ISL8105

EXTERNAL CIRCUIT

LC

FIGURE 9. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

It is recommended a mathematical model is used to plot the

loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. The following equations describe the

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

OUT COMP

gain, given by d /V

frequency response of the modulator (G

), feedback

MOD

V

, and shaped by the output

MAX IN OSC

filter, with a double pole break frequency at F and a zero at

compensation (G ) and closed-loop response (G ):

FB

CL

LC

. For the purpose of this analysis, L and D represent the

F

d

⋅ V

CE

1 + s(f) ⋅ E ⋅ C

MAX

V

IN

----------------------------- ----------------------------------------------------------------------------------------

G

(f) =

MOD

⋅

channel inductance and its DCR, while C and E represent the

total output capacitance and its equivalent series resistance.

2

OSC

1 + s(f) ⋅ (E + D) ⋅ C + s (f) ⋅ L ⋅ C

1 + s(f) ⋅ R2 ⋅ C1

------------------------------------------------------

1

G

(f) =

⋅

F

= ---------------------------

F

= -----------------------

FB

s(f) ⋅ R1 ⋅ (C1 + C2)

1 + s(f) ⋅ (R1 + R3) ⋅ C3

LC

CE

2π ⋅ C ⋅ E

2π ⋅ L ⋅ C

----------------------------------------------------------------------------------------------------------------------------

⋅

C1 ⋅ C2

C1 + C2

⎛

⎞⎞

----------------------

(1 + s(f) ⋅ R3 ⋅ C3) ⋅ 1 + s(f) ⋅ R2 ⋅

The compensation network consists of the error amplifier

(internal to the ISL8105) and the external R1-R3, C1-C3

components. The goal of the compensation network is to

provide a closed loop transfer function with high 0dB crossing

⎝

⎠⎠

G

(f) = G

(f) ⋅ G (f)

MOD FB

where, s(f) = 2π ⋅ f ⋅ j

CL

frequency (F ; typically 0.1 to 0.3 of F ) and adequate phase

0

SW

margin (better than 45°). Phase margin is the difference

FN6306.0

June 6, 2006

10

ISL8105, ISL8105A

COMPENSATION BREAK FREQUENCY EQUATIONS

(attempting to combine two different capacitors types into

one composite component model may not work properly; a

special tool may be needed; contact your local Intersil

person for assistance).

1

F

= ----------------------------------------------

F

= -------------------------------

P1

Z1

C1 ⋅ C2

2π ⋅ R2 ⋅ C1

----------------------

2π ⋅ R2 ⋅

C1 + C2

1

F

= ---------------------------------------------------

F

= -------------------------------

Z2

P2

Component Selection Guidelines

2π ⋅ (R1 + R3) ⋅ C3

2π ⋅ R3 ⋅ C3

Output Capacitor Selection

Figure 10 shows an asymptotic plot of the DC/DC converter’s

gain vs. frequency. The actual Modulator Gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown. Using the above guidelines should yield a

compensation gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

compensation gain at F against the capabilities of the error

P2

amplifier. The closed loop gain, G , is constructed on the log-

CL

log graph of Figure 10 by adding the modulator gain, G

(in

Modern components and loads are capable of producing

transient load rates above 1A/ns. High frequency capacitors

initially supply the transient and slow the current load rate

seen by the bulk capacitors. The bulk filter capacitor values

are generally determined by the ESR (Effective Series

Resistance) and voltage rating requirements rather than

actual capacitance requirements.

MOD

dB), to the feedback compensation gain, G (in dB). This is

FB

equivalent to multiplying the modulator transfer function and the

compensation transfer function and then plotting the resulting

gain.

MODULATOR GAIN

COMPENSATION GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

F

P1

F

Z1 Z2

P2

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

R2

-------

⎛

⎝

⎞

⎠

20log

d

⋅ V

IN

R1

MAX

20log---------------------------------

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor’s ESR value is related to the

case size with lower ESR available in larger case sizes.

However, the Equivalent Series Inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

V

0

OSC

G

FB

G

CL

G

MOD

LOG

F

0

FREQUENCY

LC

CE

FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin. The mathematical model presented makes a

number of approximations and is generally not accurate at

frequencies approaching or exceeding half the switching

frequency. When designing compensation networks, select

target crossover frequencies in the range of 10% to 30% of

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

the switching frequency, F

.

SW

This is just one method to calculate compensation

components; there are variations of the above equations.

The error amp is similar to that on other Intersil regulators,

so existing tools can be used here as well. Special

consideration is needed if the size of a ceramic output

capacitance in parallel with bulk capacitors gets too large;

the calculation needs to model them both separately

V

- V

V

OUT

IN

OUT

ΔV

= ΔI x ESR

ΔI =

x

OUT

Fs x L

V

IN

FN6306.0

June 6, 2006

11

ISL8105, ISL8105A

Increasing the value of inductance reduces the ripple current

MOSFET Selection/Considerations

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

The ISL8105 requires 2 N-Channel power MOSFETs. These

should be selected based upon r

, gate supply

DS(ON)

requirements, and thermal management requirements.

One of the parameters limiting the converter’s response to

a load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL8105 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss components;

conduction loss and switching loss. The conduction losses are

the largest component of power dissipation for both the upper

and the lower MOSFETs. These losses are distributed between

the two MOSFETs according to duty factor. The switching

losses seen when sourcing current will be different from the

switching losses seen when sinking current. When sourcing

current, the upper MOSFET realizes most of the switching

losses. The lower switch realizes most of the switching

losses when the converter is sinking current (see the

equations below). These equations assume linear voltage-

current transitions and do not adequately model power loss

due the reverse-recovery of the upper and lower MOSFET’s

body diode. The gate-charge losses are dissipated by the

ISL8105 and don't heat the MOSFETs. However, large gate-

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

L x I

TRAN

OUT

TRAN

V

OUT

t

=

t

=

FALL

RISE

V

- V

IN

charge increases the switching interval, t

which increases

SW

where: I

is the transient load current step, t

is the

TRAN

RISE

is the

the MOSFET switching losses. Ensure that both MOSFETs

are within their maximum junction temperature at high ambient

temperature by calculating the temperature rise according to

package thermal-resistance specifications. A separate heatsink

may be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

response time to the application of load, and t

response time to the removal of load. The worst case

response time can be either at the application or removal of

load. Be sure to check both of these equations at the

minimum and maximum output levels for the worst case

response time.

FALL

Losses while Sourcing Current

Input Capacitor Selection

2

1

2

--

× D + ⋅ Io × V × t

P

= Io × r

× F

SW

UPPER

DS(ON)

IN

S

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

2

P

= Io x r

x (1 - D)

DS(ON)

LOWER

Losses while Sinking Current

to supply the current needed each time Q turns on. Place the

1

2

P

= Io x r

2

x D

DS(ON)

UPPER

small ceramic capacitors physically close to the MOSFETs

and between the drain of Q and the source of Q .

1

2

--

× (1 – D) + ⋅ Io × V × t

1

2

P

= Io × r

× F

SW S

LOWER

DS(ON)

IN

Where: D is the duty cycle = V

/ V ,

IN

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 the DC load current.

OUT

t

is the combined switch ON and OFF time, and

SW

F

is the switching frequency.

S

When operating with a 12V power supply for V

(or down

CC

to a minimum supply voltage of 6.5V), a wide variety of N-

MOSFETs can be used. Check the absolute maximum V

GS

rating for both MOSFETs; it needs to be above the highest

voltage allowed in the system; that usually means a

V

CC

20V V

rating (which typically correlates with a 30V V

GS

DS

maximum rating). Low threshold transistors (around 1V or

below) are not recommended, for the reasons explained in

the next paragraph.

For a through hole design, several electrolytic capacitors may

be needed. For surface mount designs, solid tantalum

capacitors can also be used, but caution must be exercised

with regard to the capacitor surge current rating. These

capacitors must be capable of handling the surge current at

power-up. Some capacitor series available from reputable

manufacturers are surge current tested.

For 5V only operation, given the reduced available gate bias

voltage (5V), logic-level transistors should be used for both

N-MOSFETs. Look for r

ratings at 4.5V. Caution

DS(ON)

should be exercised with devices exhibiting very low

characteristics. The shoot-through protection

V

GS(ON)

FN6306.0

June 6, 2006

12

ISL8105, ISL8105A

present aboard the ISL8105 may be circumvented by these

BOOTSTRAP Considerations

MOSFETs if they have large parasitic impedences and/or

capacitances that would inhibit the gate of the MOSFET from

being discharged below its threshold level before the

complementary MOSFET is turned on. Also avoid MOSFETs

with excessive switching times; the circuitry is expecting

transitions to occur in under 50ns or so.

Figure 11 shows the upper gate drive (BOOT pin) supplied by

a bootstrap circuit from V . The boot capacitor, C

,

CC BOOT

develops a floating supply voltage referenced to the PHASE

pin. The supply is refreshed to a voltage of V less the boot

CC

diode drop (V ) each time the lower MOSFET, Q , turns on.

D

2

Check that the voltage rating of the capacitor is above the

maximum V voltage in the system; a 16V rating should be

CC

+V

IN

CC

sufficient for a 12V system. A value of 0.1µF is typical for

many systems driving single MOSFETs.

VCC

+ V

-

D

If V

CC

is 12V, but V is lower (such as 5V), then another

IN

BOOT

option is to connect the BOOT pin to 12V, and remove the

BOOT cap (although, you may want to add a local cap from

C

BOOT

ISL8105

Q1

Q2

UGATE

PHASE

BOOT to GND). This will make the UGATE V

GS

voltage

V

_G-S≈ V - V

CC D

equal to (12V - 5V = 7V). That should be high enough to

drive most MOSFETs, and low enough to improve the

efficiency slightly. Do NOT leave the BOOT pin open, and try

VCC

-

+

to get the same effect by driving BOOT through V

internal diode; this path is not designed for the high current

pulses that will result.

and the

LGATE/OCSET

CC

V

_G-S≈ V

CC

GND

For low V

voltage applications where efficiency is very

CC

FIGURE 11. UPPER GATE DRIVE BOOTSTRAP

important, an external BOOT diode (in parallel with the

internal one) may be considered. The external diode drop

has to be lower than the internal one; the resulting higher

V

of the upper FET will lower its r . The modest

G-S

DS(ON)

gain in efficiency should be balanced against the extra cost

and area of the external diode.

For information on the Application circuit, including a

complete Bill-of-Materials and circuit board description, can

be found in Application Note AN1258.

FN6306.0

June 6, 2006

13

ISL8105, ISL8105A

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

8

7

NOTES:

0°

8°

0°

8°

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6306.0

June 6, 2006

14


型号：	ISL8105ACBZ
厂家：	RENESAS TECHNOLOGY CORP
描述：	SWITCHING CONTROLLER, 660kHz SWITCHING FREQ-MAX, PDSO8, ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8 开关光电二极管
文件：	总14页 (文件大小：250K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL8105ACBZ [RENESAS]

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