ISL8484IR-T
更新时间：2024-09-18 18:31:35
品牌：RENESAS
描述：DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO10, 3 X 3 MM, PLASTIC, MO-229WEED-3, TDFN-10
概述
规格参数
数据手册ISL8484IR-T 概述
DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO10, 3 X 3 MM, PLASTIC, MO-229WEED-3, TDFN-10 复用器或开关
ISL8484IR-T 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | SON | 包装说明： | 3 X 3 MM, PLASTIC, MO-229WEED-3, TDFN-10 |
| 针数： | 10 | Reach Compliance Code： | not_compliant |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.35 |
| 模拟集成电路 - 其他类型： | SPDT | JESD-30 代码： | S-PDSO-N10 |
| JESD-609代码： | e0 | 长度： | 3 mm |
| 湿度敏感等级： | 1 | 信道数量： | 1 |
| 功能数量： | 2 | 端子数量： | 10 |
| 标称断态隔离度： | 68 dB | 通态电阻匹配规范： | 0.03 Ω |
| 最大通态电阻 (Ron)： | 0.4 Ω | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 输出： | SEPARATE OUTPUT |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | HVSON |
| 封装等效代码： | SOLCC10,.12,20 | 封装形状： | SQUARE |
| 封装形式： | SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE | 峰值回流温度（摄氏度）： | 240 |
| 电源： | 1.8/4.3 V | 认证状态： | Not Qualified |
| 座面最大高度： | 0.8 mm | 子类别： | Multiplexer or Switches |
| 最大供电电压 (Vsup)： | 4.5 V | 最小供电电压 (Vsup)： | 1.65 V |
| 标称供电电压 (Vsup)： | 3 V | 表面贴装： | YES |
| 最长断开时间： | 25 ns | 最长接通时间： | 30 ns |
| 切换： | BREAK-BEFORE-MAKE | 技术： | CMOS |
| 温度等级： | INDUSTRIAL | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | NO LEAD | 端子节距： | 0.5 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 3 mm | Base Number Matches： | 1 |
ISL8484IR-T 数据手册
通过下载ISL8484IR-T数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载DATASHEET
ISL8484
FN6128
Rev 5.00
May 12, 2008
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog
Switch
The Intersil ISL8484 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
Features
• Pin Compatible Replacement for the MAX4684 and
MAX4685
analog switch designed to operate from a single +1.65V to
+4.5V supply. Targeted applications include battery powered
equipment that benefit from low r
(0.29 and fast
• ON-Resistance (r )
ON
ON
switching speeds (t
input is 1.8V logic-compatible when using a single +3V supply.
= 40ns, t
= 20ns). The digital logic
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55
ON
OFF
With a supply voltage of 4.2V and logic high voltage of 2.85V
at both logic inputs, the part draws only 12µA max of I+
current.
• r
Matching Between Channels . . . . . . . . . . . . . . . . .0.06
Flatness Across Signal Range . . . . . . . . . . . . . . . .0.03
ON
ON
• r
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL8484 is offered in small form factor packages, alleviating
board space limitations.
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (P ) . . . . . . . . . . . . . . .<0.45µW
D
• Fast Switching Action (V+ = +4.3V)
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
OFF
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >8kV
• Guaranteed Break-Before-Make
The ISL8484 is a committed dual single-pole/double-throw
(SPDT) that consist of two normally open (NO) and two
normally closed (NC) switches. This configuration can be
used as a dual 2-to-1 multi-plexer. The ISL8484 is pin
compatible with the MAX4684 and MAX4685.
• 1.8V Logic Compatible (+3V supply)
• Low I+ Current when V H is not at the V+ Rail
IN
• Available in 10 Ld 3x3 TDFN and 10 Ld MSOP
• Pb-Free Available (RoHS Compliant)
TABLE 1. FEATURES AT A GLANCE
ISL8484
NUMBER OF SWITCHES
SW
2
SPDT or 2-1 MUX
0.29
Applications
• Battery-powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
4.3V r
ON
- Pagers
4.3V t /t
ON OFF
40ns/20ns
- Laptops, Notebooks, Palmtops
3V r
0.33
ON
• Portable Test and Measurement
• Medical Equipment
3V t /t
50ns/27ns
ON OFF
1.8V r
0.55
ON
1.8V t /t
• Audio and Video Switching
70ns/54ns
ON OFF
Packages
10 Ld 3x3 Thin DFN, 10 Ld MSOP
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
FN6128 Rev 5.00
May 12, 2008
Page 1 of 13
ISL8484
Truth Table
Pinout (Note 1)
ISL8484
(10 LD TDFN, MSOP)
TOP VIEW
LOGIC
NC1 and NC2
NO1 and NO2
0
1
ON
OFF
ON
OFF
V+
1
2
3
4
5
10 NO2
NOTE: Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
9
8
7
6
NO1
COM1
IN1
COM2
IN2
Pin Descriptions
NC2
GND
PIN
FUNCTION
System Power Supply Input (+1.65V to +4.5V)
Ground Connection
NC1
V+
GND
INx
NOTE:
Digital Control Input
1. Switches Shown for Logic “0” Input.
COMx Analog Switch Common Pin
NOx
NCx
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
Ordering Information
TEMP. RANGE
(°C)
PKG.
DWG. #
PART NUMBER
ISL8484IR*
PART MARKING
PACKAGE
484
-40 to +85
-40 to +85
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL8484IU*
8484
484Z
10 Ld MSOP
M10.118
ISL8484IRZ*
(Note)
10 Ld 3x3 TDFN
(Pb-free)
L10.3x3A
ISL8484IUZ*
(Note)
8484Z
-40 to +85
10 Ld MSOP
(Pb-free)
M10.118
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN6128 Rev 5.00
May 12, 2008
Page 2 of 13
ISL8484
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA
Peak Current NO, NC, or COM
Thermal Resistance (Typical)
(°C/W)
(°C/W)
JC
JA
10 Ld 3x3 TDFN Package (Notes 3, 4)
10 Ld MSOP Package (Note 5) . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
52
140
11
N/A
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 500mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
4. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
5. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V
Unless otherwise specified.
= 1.4V, V
= 0.5V (Note 6),
INL
INH
TEMP
(°C)
MIN
(Notes 7, 11)
MAX
PARAMETER
TEST CONDITIONS
TYP
(Notes 7, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
V+
0.5
V
ON-Resistance, r
V+ = 3.9V, I
= 100mA, V
or V
NC
= 0V to V+
= Voltage
= 0V to V+
-
0.30
0.35
0.06
0.08
0.03
0.04
-
ON
COM
(Figure 5, Note 9)
NO
NO
NO
Full
25
-
0.7
r
Matching Between Channels, V+ = 3.9V, I
= 100mA, V
(Note 9, 10)
ON
or V
-
-
0.07
0.08
0.15
0.15
100
195
100
195
ON
r
COM
NC
NC
at max R
ON
Full
25
r
Flatness, r
V+ = 3.9V, I
(Note 8, 9)
= 100mA, V
COM
or V
-
ON
FLAT(ON)
Full
25
-
NO or NC OFF Leakage Current, V+ = 4.5V, V
= 0.3V, 3V, V
NO
or V = 3V, 0.3V
NC
-100
-195
-100
-195
nA
nA
nA
nA
COM
I
or I
NO(OFF)
NC(OFF)
Full
25
-
COM ON Leakage Current,
V = 4.5V, V
3V, or Floating
= 0.3V, 3V, or V
or V
= 0.3V,
NC
-
COM
NO
I
COM(ON)
Full
-
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 3.9V, V
(Figure 1)
or V = 3.0V, R = 50, C = 35pF
NC
25
Full
25
-
-
-
-
-
40
50
20
30
8
-
-
-
-
-
ns
ns
ns
ns
ns
ON
NO
L
L
Turn-OFF Time, t
V+ = 3.9V, V
(Figure 1)
or V = 3.0V, R = 50, C = 35pF
NC
OFF
NO
L
L
Full
Full
Break-Before-Make Time Delay, t
V+ = 4.5V, V
(Figure 3)
or V = 3.0V, R = 50, C = 35pF
D
NO
NC
L
L
Charge Injection, Q
OFF Isolation
C
= 1.0nF, V = 0V, R = 0Figure 2)
25
25
-
-
170
62
-
-
pC
dB
L
L
G
G
R
= 50, C = 5pF, f = 100kHz, V
= 1V
L
COM
RMS
RMS
(Figure 4)
Crosstalk (Channel-to-Channel)
R
= 50, C = 5pF, f = 100kHz, V
= 1V
25
-
-85
-
dB
L
L
COM
(Figure 6)
FN6128 Rev 5.00
May 12, 2008
Page 3 of 13
ISL8484
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V
Unless otherwise specified.
= 1.4V, V
= 0.5V (Note 6),
INL
INH
TEMP
(°C)
MIN
(Notes 7, 11)
MAX
PARAMETER
TEST CONDITIONS
f = 20Hz to 20kHz, V = 2V , R = 600
TYP
0.005
62
(Notes 7, 11) UNITS
Total Harmonic Distortion
25
25
25
-
-
-
-
-
-
%
pF
pF
COM
P-P
L
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
= V
= 0V (Figure 7)
= 0V (Figure 7)
OFF
NO
NO
NC
NC
COM
COM
COM ON Capacitance, C
or V
= V
176
COM(ON)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
1.65
-
-
-
-
4.5
0.1
1
V
Positive Supply Current, I+
V+ = +4.5V, V = 0V or V+
IN
-
-
-
µA
µA
µA
Full
25
Positive Supply Current, I+
V+ = +4.2V, V = 2.85V
IN
12
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.5
-
V
V
INL
Input Voltage High, V
1.4
-0.5
INH
Input Current, I
, I
INH INL
V+ = 4.5V, V = 0V or V+ (Note 9)
0.5
µA
IN
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
Unless otherwise specified.
= 1.4V, V
= 0.5V (Note 6),
INL
INH
TEMP
(°C)
MIN
(Notes 7, 11)
MAX
PARAMETER
TEST CONDITIONS
TYP
(Notes 7, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal range, V
ANALOG
Full
25
0
-
-
-
-
-
-
-
-
-
-
-
0.35
-
V+
0.5
0.7
0.07
0.08
0.15
0.15
-
V
ON-Resistance, r
V+ = 2.7V, I
(Figure 5)
= 100mA, V
or V
NC
= 0V to V+
= Voltage
ON
COM
COM
COM
NO
Full
25
r
Matching Between Channels, V+ = 2.7V, I
= 100mA, V
or V
NC
0.06
-
ON
r
NO
NO
at max R
(Note 10)
ON
ON
Full
25
r
Flatness, r
V+ = 2.7V, I
(Note 8)
= 100mA, V
or V = 0V to V+
NC
0.03
-
ON
FLAT(ON)
Full
25
NO or NC OFF Leakage Current,
or I
V+ = 3.3V, V
= 0.3V, 3V, V
NO
or V = 3V, 0.3V
NC
0.9
30
0.8
30
nA
nA
nA
nA
COM
I
NO(OFF)
NC(OFF)
Full
25
-
COM ON Leakage Current,
V = 3.3V, V
3V, or Floating
= 0.3V, 3V, or V
NO
or V = 0.3V,
NC
-
COM
I
COM(ON)
Full
-
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 2.7V, V
(Figure 1)
or V = 1.5V, R = 50, C = 35pF
NC
25
Full
25
-
-
-
-
-
50
60
27
35
9
-
-
-
-
-
ns
ns
ns
ns
ns
ON
NO
L
L
Turn-OFF Time, t
V+ = 2.7V, V or V = 1.5V, R = 50, C = 35pF
NO NC
(Figure 1)
OFF
L
L
Full
Full
Break-Before-Make Time Delay, t
V+ = 3.3V, V or V = 1.5V, R = 50, C = 35pF
D
NO
NC
L
L
(Figure 3)
Charge Injection, Q
OFF Isolation
C
= 1.0nF, V = 0V, R = 0Figure 2)
25
25
-
-
94
62
-
-
pC
dB
L
G
G
R = 50, C = 5pF, f = 100kHz, V
= 1V
RMS
L
L
COM
(Figure 4)
Crosstalk (Channel-to-Channel)
Total Harmonic Distortion
R = 50, C = 5pF, f = 100kHz, V
(Figure 6)
= 1V ,
RMS
25
25
-
-
-85
-
-
dB
%
L
L
COM
f = 20Hz to 20kHz, V
= 2V , R = 600
P-P
0.005
COM
L
FN6128 Rev 5.00
May 12, 2008
Page 4 of 13
ISL8484
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
Unless otherwise specified. (Continued)
= 1.4V, V
= 0.5V (Note 6),
INL
INH
TEMP
(°C)
MIN
(Notes 7, 11)
MAX
PARAMETER
TEST CONDITIONS
TYP
65
(Notes 7, 11) UNITS
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V (Figure 7)
= 0V (Figure 7)
25
25
-
-
-
-
pF
pF
OFF
NO
NO
NC
COM
COM
COM ON Capacitance, C
181
COM(ON)
NC
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = +3.6V, V = 0V or V+
25
-
-
0.01
0.52
-
-
µA
µA
IN
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
25
25
-
-
-
-
0.5
-
V
V
INL
Input Voltage High, V
1.4
-0.5
INH
Input Current, I
, I
INH INL
V+ = 3.3V, V = 0V or V+ (Note 9)
IN
Full
0.5
µA
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 6),
Unless otherwise specified.
TEMP
(°C)
MIN
(Notes 7, 11)
MAX
(Notes 7, 11) UNITS
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
0.7
-
V+
0.8
V
ON-Resistance, r
V+ = 1.65V, I
(Figure 5)
= 100mA, V
COM NO
or V = 0V to V+
NC
ON
Full
-
0.85
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 1.65V, V or V = 1.0V, R = 50, C = 35pF
NO NC
(Figure 1)
25
Full
25
-
-
-
-
-
70
80
54
65
10
-
-
-
-
-
ns
ns
ns
ns
ns
ON
L
L
Turn-OFF Time, t
V+ = 1.65V, V or V = 1.0V, R = 50, C = 35pF
NO NC
OFF
L
L
(Figure 1)
Full
Full
Break-Before-Make Time Delay, t
Charge Injection, Q
V+ = 2.0V, V
(Figure 3)
or V = 1.0V, R = 50, C = 35pF
D
NO
NC
L
L
C
= 1.0nF, V = 0V, R = 0Figure 2)
25
25
25
-
-
-
42
70
-
-
-
pC
pF
pF
L
G
NO
NO
G
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
= V
= 0V (Figure 7)
= 0V (Figure 7)
OFF
NC
NC
COM
COM
COM ON Capacitance, C
or V
= V
186
COM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
25
25
-
-
-
-
0.4
-
V
V
INL
Input Voltage High, V
1.0
-0.5
INH
Input Current, I
NOTES:
, I
INH INL
V+ = 2.0V, V = 0V or V+ (Note 9)
IN
Full
0.5
µA
6. V = input voltage to perform proper function.
IN
7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
9. Limits established by characterization and are not production tested.
10. R
matching between channels is calculated by subtracting the channel with the highest max r
value from the channel with lowest max r
ON ON
ON
value, between NC1 and NC2 or between NO1 and NO2.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN6128 Rev 5.00
May 12, 2008
Page 5 of 13
ISL8484
Test Circuits and Waveforms
V+
C
V+
t < 5ns
r
t < 5ns
f
LOGIC
INPUT
50%
0V
NO
0V
V
OUT
t
NO OR NC
IN
OFF
SWITCH
INPUT
COM
SWITCH
INPUT
V
V
OUT
90%
90%
C
L
35pF
R
50
LOGIC
INPUT
L
GND
SWITCH
OUTPUT
t
ON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. C includes fixture and stray
L
capacitance.
r
L
-------------------------
V
= V
OUT
(NO or NC)
r
+ r
ON
L
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
V
R
OUT
G
COM
NO OR NC
GND
SWITCH
OUTPUT
V
OUT
V
OUT
V
IN
G
C
L
V+
0V
ON
ON
LOGIC
INPUT
LOGIC
INPUT
OFF
Q = V
x C
L
OUT
Repeat test for all switches.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
V+
0V
NO
LOGIC
INPUT
V
V
OUT
NX
COM
NC
C
R
L
L
50
35pF
IN
GND
90%
LOGIC
INPUT
SWITCH
OUTPUT
V
OUT
0V
t
D
Repeat test for all switches. C includes fixture and stray
L
capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
FN6128 Rev 5.00
May 12, 2008
Page 6 of 13
ISL8484
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
R
= V /100mA
1
ON
NO OR NC
NO OR NC
V
NX
IN
0V OR V+
0V OR V+
100mA
IN
V
1
COM
ANALYZER
GND
COM
R
L
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
FIGURE 5. r
TEST CIRCUIT
ON
V+
C
V+
C
SIGNAL
GENERATOR
50
NO OR NC
COM
NO OR NC
IN
1
0V OR V+
IN
0V OR V+
IMPEDANCE
ANALYZER
NC or NO
COM
COM
ANALYZER
N C
GND
GND
R
L
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from the
V+ power supply to ground. This will result in a significant
amount of current flow in the IC which can potentially create a
latch-up state or permanently damage the IC. The external V+
resistor limits the current during this over-stress situation and
has been found to prevent latch-up or destructive damage for
many overvoltage transient events.
Detailed Description
The ISL8484 is a bidirectional, dual single pole/double throw
(SPDT) analog switch that offers precise switching capability
from a single 1.65V to 4.5V supply with low on-resistance
(0.29) and high speed operation (t
The device is especially well suited for portable
battery-powered equipment due to its low operating supply
voltage (1.65V), low power consumption (4.5µW max), low
leakage currents (195nA max), and the tiny DFN and MSOP
= 40ns, t = 20ns).
ON
OFF
packages. The ultra low on-resistance and r
flatness
ON
provide very low insertion loss and distortion to applications
that require signal reproduction.
Under normal operation the sub-microamp I
current of the
DD
IC produces an insignificant voltage drop across the 100
series resistor resulting in no impact to switch operation or
performance.
External V+ Series Resistor
For improved ESD and latch-up immunity Intersil
recommends adding a 100 resistor in series with the V+
power supply pin of the ISL8484 IC (see Figure 8).
FN6128 Rev 5.00
May 12, 2008
Page 7 of 13
ISL8484
.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the purpose
V+
C
of using a low r
switch. Connecting Schottky diodes to the
ON
OPTIONAL
PROTECTION
RESISTOR
signal pins as shown in Figure 8 will shunt the fault current to
the supply or to ground thereby protecting the switch. These
Schottky diodes must be sized to handle the expected fault
current.
100
NO
NC
COM
Power-Supply Considerations
IN
The ISL8484 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins: V+
and GND. V+ and GND drive the internal CMOS switches and
set their analog voltage limits. Unlike switches with a 4V
maximum supply voltage, the ISL8484 5.5V maximum supply
voltage provides plenty of room for the 10% tolerance of 4.3V
supplies, as well as room for overshoot and noise spikes.
GND
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer to
the “Electrical Specifications” tables, beginning on page 3, and
“Typical Performance Curves”, beginning on page 9, for
details.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
IN
V
X
V+ and GND also power the internal logic and level shiftiers.
The level shiftiers convert the input logic levels to switched V+
and GND signals to drive the analog switch gate terminals.
V
NX
COM
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes negative
in this configuration.
GND
OPTIONAL
SCHOTTKY
DIODE
Logic-Level Thresholds
FIGURE 9. OVERVOLTAGE PROTECTION
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.7V to 4.5V (see Figure18). At 2.7V the
V
level is about 0.53V. This is still above the 1.8V CMOS
IL
Supply Sequencing and Overvoltage Protection
guaranteed low output maximum level of 0.5V, but noise
margin is reduced.
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 9). To prevent forward biasing these diodes, V+ must be
applied before any input signals, and the input signal voltages
must remain between V+ and GND.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving the
digital input signals from GND to V+ with a fast transition time
minimizes power dissipation.
The ISL8484 has been designed to minimize the supply
current whenever the digital input voltage is not driven to the
supply rails (0V to V+). For example driving the device with
2.85V logic (0V to 2.85V) while operating with a 4.2V supply
the device draws only 12µA of current
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at the
logic pin and signal pins from exceeding the maximum ratings
of the switch. The following two methods can be used to
provided additional protection to limit the current in the event
that the voltage at a signal pin or logic pin goes below ground
or above the V+ rail.
(see Figure17 for VIN = 2.85V).
High-Frequency Performance
In 50 systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 120MHz (see Figure 22).
The frequency response is very consistent over a wide V+
range, and for varying analog signal levels.
Logic inputs can be protected by adding a 1k resistor in
series with the logic input (see Figure 9). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
FN6128 Rev 5.00
May 12, 2008
Page 8 of 13
ISL8484
the resistance to this feedthrough, while crosstalk indicates the
amount of feedthrough from one switch to another. Figure 23
details the high off isolation and crosstalk rejection provided by
this part. At 100kHz, off isolation is about 62dB in 50
systems, decreasing approximately 20dB per decade as
frequency increases. Higher load impedances decrease off
isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load impedance.
signal pin are identical and therefore fairly well balanced, they
are reverse biased differently. Each is biased by either V+ or
GND and the analog signal. This means their leakages will
vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the
analog-signal-path leakage current. All analog leakage current
flows between each pin and one of the supply terminals, not to
the other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Leakage Considerations
Reverse ESD protection diodes are internally connected between
each analog-signal pin and both V+ and GND. One of these
diodes conducts if any analog signal exceeds V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
Typical Performance Curves T = +25°C, Unless Otherwise Specified.
A
0.30
0.29
0.28
0.27
0.26
0.25
0.35
0.34
0.33
0.32
0.31
0.3
I = 100mA
COM
I
= 100mA
COM
V+ = 2.7V
V+ = 3.9V
V+ = 3V
0.29
0.28
V+ = 4.3V
V+ = 3.3V
V+ = 4.5V
3
0
1
2
4
5
0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
V
(V)
COM
COM
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.70
0.35
V+ = 4.3V
I
= 100mA
COM
I
= 100mA
COM
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
+85°C
+25°C
-40°C
V+ = 1.65V
0.30
0.25
0.20
V+ = 1.8V
V+ = 2V
0
0.5
1.0
1.5
2.0
0
1.0
2.0
3.0
4.0
5.0
V
(V)
V
(V)
COM
COM
FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FN6128 Rev 5.00
May 12, 2008
Page 9 of 13
ISL8484
Typical Performance Curves T = +25°C, Unless Otherwise Specified. (Continued)
A
0.40
0.35
0.30
0.25
0.20
0.40
0.35
0.30
0.25
V+ = 3.3V
= 100mA
V+ = 2.7V
= 100mA
I
I
COM
COM
+85°C
+25°C
+85°C
+25°C
-40°C
-40°C
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
V
V
COM
COM
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 14. ON RESISTANCE vs SWITCH VOLTAGE
0.60
200
V+ = 1.8V
= 100mA
+85°C
+25°C
V+ = 4.2V
SWEEPING BOTH LOGIC INPUTS
I
COM
0.55
0.50
0.45
0.40
0.35
0.30
0.25
150
100
50
-40°C
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
V
(V)
V
(V)
COM
IN 1 AND 2
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 17. SUPPLY CURRENT vs VLOGIC VOLTAGE
200
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
150
100
50
V
INH
V+ = 4.3V
V
INL
V+ = 1.8V
0
V+ = 3V
-50
-100
0
1
2
3
4
5
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
4.5
V
(V)
COM
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE
FN6128 Rev 5.00
May 12, 2008
Page 10 of 13
ISL8484
Typical Performance Curves T = +25°C, Unless Otherwise Specified. (Continued)
A
200
150
100
50
250
200
150
100
25
+85°C
+25°C
+85°C
+25°C
-40°C
-40°C
0
1.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V+ (V)
V+ (V)
FIGURE 20. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 21. TURN-OFF TIME vs SUPPLY VOLTAGE
-10
-20
-30
-40
-50
-60
-70
-80
-90
10
V+ = 3V
GAIN
V+ = 4.3V
20
30
40
50
60
70
80
90
0
-20
0
PHASE
ISOLATION
20
40
60
CROSSTALK
80
-100
-110
100
110
R
= 50
= 0.2V
100
L
V
to 2V
IN
P-P
P-P
10
1
100
FREQUENCY (MHz)
600
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 22. FREQUENCY RESPONSE
FIGURE 23. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (DFN Paddle Connection: Tie to GND or Float)
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
FN6128 Rev 5.00
May 12, 2008
Page 11 of 13
ISL8484
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
MILLIMETERS
2X
0.10
C B
SYMBOL
MIN
0.70
-
NOMINAL
MAX
0.80
0.05
NOTES
A
A1
A3
b
0.75
-
-
0.20 REF
0.25
3.0
-
E
-
6
INDEX
AREA
0.20
2.95
2.25
2.95
1.45
0.30
3.05
2.35
3.05
1.55
5, 8
D
-
TOP VIEW
B
A
D2
E
2.30
3.0
7, 8
-
// 0.10
0.08
C
E2
e
1.50
0.50 BSC
-
7, 8
-
C
k
0.25
0.25
-
-
A3
C
SIDE VIEW
L
0.30
10
0.35
8
SEATING
PLANE
N
2
D2
D2/2
2
Nd
5
3
7
8
(DATUM B)
Rev. 3 3/06
NOTES:
1
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
NX k
E2
3. Nd refers to the number of terminals on D.
(DATUM A)
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N
N-1
NX b
8
e
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
(Nd-1)Xe
REF.
M
0.10
C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
C
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
L
(A1)
NX (b)
L1
L
9
5
e
SECTION "C-C"
TERMINAL TIP
FOR ODD TERMINAL/SIDE
C C
FN6128 Rev 5.00
May 12, 2008
Page 12 of 13
ISL8484
Mini Small Outline Plastic Packages
(MSOP)
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
N
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.18
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.27
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.007
0.004
0.116
0.116
0.043
0.006
0.037
0.011
0.008
0.120
0.120
-
E1
E
-
-
-B-
0.20 (0.008)
INDEX
AREA
9
1 2
A
B
C
c
-
TOP VIEW
D
3
4X
0.25
(0.010)
R1
E1
e
4
R
GAUGE
PLANE
0.020 BSC
0.50 BSC
-
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
SEATING
PLANE
L
6
L
-C-
4X
L1
L1
N
0.037 REF
10
0.95 REF
10
-
A
A2
7
SEATING
PLANE
R
0.003
0.003
-
-
0.07
0.07
-
-
-
0.10 (0.004)
-A-
C
C
b
R1
-
-H-
A1
o
o
o
o
5
15
5
15
-
e
D
o
o
o
o
0
6
0
6
-
0.20 (0.008)
C
Rev. 0 12/02
a
SIDE VIEW
C
L
E
1
-B-
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
© Copyright Intersil Americas LLC 2006-2008. All Rights Reserved.
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
All trademarks and registered trademarks are the property of their respective owners.
- B -
-A -
10. Datums
and
to be determined at Datum plane
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
For additional products, see www.intersil.com/en/products.html
sions are for reference only
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6128 Rev 5.00
May 12, 2008
Page 13 of 13
ISL8484IR-T 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ISL8484IRZ | INTERSIL | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch | 获取价格 |
|
| ISL8484IRZ-T | INTERSIL | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch | 获取价格 |
|
| ISL8484IRZ-T | RENESAS | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch; DFN10, MSOP10; Temp Range: -40&deg; to 85&deg;C | 获取价格 |
|
| ISL8484IU | INTERSIL | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch | 获取价格 |
|
| ISL8484IU | RENESAS | DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO10, PLASTIC, MO-187BA, MSOP-10 | 获取价格 |
|
| ISL8484IU-T | INTERSIL | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch | 获取价格 |
|
| ISL8484IU-T | RENESAS | DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO10, PLASTIC, MO-187BA, MSOP-10 | 获取价格 |
|
| ISL8484IUZ | INTERSIL | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch | 获取价格 |
|
| ISL8484IUZ | RENESAS | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch; MSOP10; Temp Range: -40&deg; to 85&deg;C | 获取价格 |
|
| ISL8484IUZ-T | INTERSIL | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch | 获取价格 |
|
ISL8484IR-T 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
