ISL85003AEVAL2Z [RENESAS]
Highly Efficient 3A Synchronous Buck Regulator;
| 型号： | ISL85003AEVAL2Z |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Highly Efficient 3A Synchronous Buck Regulator |
| 文件： | 总23页 (文件大小：1462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL85003, ISL85003A
Highly Efficient 3A Synchronous Buck Regulator
FN7968
Rev.2.00
Jan 15, 2016
The ISL85003 and ISL85003A are synchronous buck regulators
with integrated high-side and low-side FETs. The regulator can
operate from an input voltage range of 4.5V to 18V while
delivering a very efficient continuous 3A current. This is all
delivered in a very compact 3mmx4mm DFN package.
Features
• Input voltage range 4.5V to 18V
• Output voltage adjustable from 0.8V, ±1%
• Efficiency up to 95%
The ISL85003 is designed on Intersil’s proprietary fab process
• Integrated boot diode with undervoltage detection
that is designed to deliver very low r
FETs with an
optimized current mode controller wrapped around it. The
DS(ON)
• Current mode control
high-side NFET is designed to have an r
the low-side NFET is designed to have an r
With these two FETs, the device delivers very high efficiency
power to the load.
of 65mΩ while
of 45mΩ.
- DCM/CCM
DS(ON)
- Internal or external compensation options
- 500kHz switching frequency option
- External synchronization up to 2MHz on ISL85003
DS(ON)
The ISL85003 can automatically switch between DCM and
CCM for light-load efficiency in DCM. The switching frequency
in CCM is internally set to 500kHz.
• Adjustable soft-start time on the ISL85003A
• Open-drain PG window comparator
- Built-in protection
The device provides a maximum static regulation tolerance of
±1% over wide line, load and temperature ranges. The output
is user adjustable, with external resistors, down to 0.8V. Pulling
EN above 0.6V enables the controller. The regulator supports
prebiased output.
- Positive and negative overcurrent protection
- Overvoltage and thermal protection
- Input overvoltage protection
• Small 12 Ld 3mmx4mm Dual Flat No-Lead (DFN) package
Fault protection is provided by internal current limiting during
positive or negative overcurrent conditions, output and input
under and overvoltage detection and an over-temperature
monitoring circuit.
Applications
• Network and communication equipment
• Industrial process control
• Multifunction printers
Related Literature
• AN1935, “ISL85003DEMO1Z, ISL85003ADEMO1Z
Evaluation Board User Guide”
• Point-of-load regulators
• Standard 12V rail supplies
• Embedded computing
• AN1930, “ISL85003EVAL2Z, ISL85003AEVAL2Z Evaluation
Board User Guide”
• AN1965, “Effectively Using the Intersil Small Form Factor
Power Management Evaluation Boards”
OPTIONAL CAP
NO CAP: t = 2ms
SS
U1
SS
ISL85003A
t
= 2ms, FIXED
U1
ISL85003
SS
For t >2ms, ADD CAP:
SS
C[nF] = 4.1 * t [ms]-1.6nF
SS
C
2
C
C
3
0.1µF
1µF
22nF
3
0.1µF
1µF
1
2
L = 0.5V H = 1.20V POS EDGE
L = DE H = FPWM
12
11
1
2
12
11
SYNC
BOOT
VDD
VIN
SYNC
PG
SYNC
PG
BOOT
VDD
VIN
C
C
4
4
PG
PG
OPEN DRAIN, ADD PULL-UP
+5V
10
OPEN DRAIN, ADD PULL-UP
+5V
10
4.5 TO 18V
3
4.5 TO 18V
3
EN
EN
VIN
EN
VIN
EN
THRESHOLD 1V, HYST 100mV
C
5
10µF
THRESHOLD 1V, HYST 100mV
C
10µF
C
5
10µF
C
10µF
6
6
+0.8V ±8mV
+0.8V ±8mV
GND
4
9
8
GND
4
9
8
AGND
AGND
FB
VIN
PHASE
PHASE
FB
VIN
PHASE
PHASE
R
R
2
R
R
1
1
2
5
6
301k 57.1k
5
6
301k 57.1k
C
C
4.7pF
1
COMP
AGND
1
1%
1%
COMP
AGND
1%
1%
4.7pF
+5V
MAX 3A
+5V
MAX 3A
L
1
L
1
7
f
7
f
VOUT
GND
VOUT
GND
= 500kHz
4.7µH
C ,22µF
= 500kHz
SW
4.7µH
C
8
C ,22µF
9
SW
C
9
8
47µF
47µF
DEVICE MUST BE
CONNECTED TO GND
PLANE WITH 8 VIAs.
DEVICE MUST BE
CONNECTED TO GND
PLANE WITH 8 VIAs.
+5V
FIGURE 1A. ISL85003 V RANGE FROM 4.5V TO 18V, V
IN
= 5V AND
FIGURE 1B. ISL85003A V RANGE FROM 4.5V TO 18V, V
IN
= 5V
OUT
OUT
AND INTERNAL COMPENSATION WITH EXTERNAL
SOFT-START
INTERNAL COMPENSATION WITH EXTERNAL
FREQUENCY SYNC
FIGURE 1. TYPICAL APPLICATION SCHEMATICS
FN7968 Rev.2.00
Jan 15, 2016
Page 1 of 23
ISL85003, ISL85003A
Table of Contents
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CCM Control Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Light-Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Enable, Soft-Start and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Switching Regulator Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Negative Current Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
BOOT Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Switching Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Compensator Design Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
High DC Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FN7968 Rev.2.00
Jan 15, 2016
Page 2 of 23
ISL85003, ISL85003A
Functional Block Diagram
SS (ISL85003A)
SYNC (ISL85003)
SOFT-START
CONTROL
1
1
2
BOOT
BOOT
12
11
REFRESH
VDD
VIN
VIN
PG
LDO
10
9
1.5ms
DELAY
FAULT
MONITOR
CIRCUITS
CSA
UNDERVOLTAGE
LOCKOUT
SLOPE COMP
0.8V
+
EN
REFERENCE
3
4
+
-
POR
+
-
FB
PHASE
PHASE
8
7
EA
GATE DRIVE
600k
PGND
30pF
13
COMP
5
OSCILLATOR
DCM
GND DETECT
DETECTOR
ZERO CROSS
DETECTOR
AGND
NEGATIVE
CURRENT
LIMIT
6
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
FN7968 Rev.2.00
Jan 15, 2016
Page 3 of 23
ISL85003, ISL85003A
Pin Configurations
ISL85003
(12 ld 3X4 DFN)
TOP VIEW
ISL85003A
(12 LD 3X4 DFN)
TOP VIEW
SYNC
PG
SS
PG
1
2
3
4
5
6
12 BOOT
1
2
3
4
5
6
12 BOOT
11
10
9
11
10
9
VDD
VDD
EN
EN
VIN
VIN
PGND
13
PGND
13
FB
FB
VIN
VIN
COMP
AGND
8
PHASE
PHASE
COMP
AGND
8
PHASE
PHASE
7
7
Pin Descriptions
PIN
PIN
NUMBER
NAME
DESCRIPTION
1
SYNC Synchronization and mode selection input. Connect to VDD for CCM mode. Connect to AGND for DCM mode. Connect to an
external function generator for synchronization with the positive edge trigger. There is an internal 1MΩ pull-up resistor to VDD,
which prevents an undefined logic state in cases where SYNC is floating.
(ISL85003)
1
SS
Soft-Start input. This pin provides a programmable soft-start. When the chip is enabled, the regulated 4µA pull-up current
source charges a capacitor connected from SS to ground. The output voltage of the converter follows the ramping voltage on
this pin. Without the external capacitor, the default soft-start is 2ms.
(ISL85003A)
2
PG
Power-good open-drain output. Connect 10kΩ to 100kΩ pull-up resistor between PG and VDD or between PG and a voltage not
exceeding 5.5V. PG transitions high about 1ms after the switching regulator’s output voltage reaches the regulation threshold,
which is 85% of the regulated output voltage typically.
3
4
EN
FB
Enable input. The regulator is held off when the pin is pulled to ground. The device is enabled when the voltage on this pin rises
above 0.6V.
Feedback input. The synchronous buck regulator employs a current mode control loop. FB is the negative input to the voltage
loop error amplifier. The output voltage is set by an external resistor divider connected to FB. The output voltage can be set to
any voltage between the power rail (reduced by converter losses) and the 0.8V reference.
5
6
COMP Compensation node. This pin is connected to the output of the error amplifier, and is used to compensate the loop. Internal
compensation is used to meet most applications. Connect COMP to AGND to select internal compensation. Connect a
compensation network between COMP and FB to use external compensation.
AGND The AGND terminal provides the return path for the core analog control circuitry within the device. Connect AGND to the board
ground plane. AGND and PGND are connected internally within the device. Do not operate the device with AGND and PGND
connected to dissimilar voltages.
7, 8
PHASE Phase switch output node. This is the main output of the device. Connect to the external output inductor.
9, 10
VIN
Voltage supply input. The main power input for the IC. Connect to a suitable voltage supply. Place a ceramic capacitor from VIN
to PGND, close to the IC for decoupling (typical 10µF).
11
12
VDD
Low dropout linear regulator decoupling pin. VDD is the internally generated 5V supply voltage and is derived from VIN. The
VDD is used to power all the internal core analog control blocks and drivers. Connect a 1µF capacitor from VDD to the board
ground plane. If VIN is between 4.5V to 5.5V, then connect VDD directly to VIN to improve efficiency.
BOOT Bootstrap input. Floating bootstrap supply pin for the upper power MOSFET gate driver. Connect a 0.1µF capacitor between
BOOT and PHASE.
13
(EPAD)
PGND Power ground terminal. Provides thermal relief for the package and is connected to the source of the low-side output MOSFET.
Connect PGND to the board ground plane using as many vias as possible. AGND and PGND are connected internally within the
device. Do not operate the device with AGND and PGND connected to dissimilar voltages.
FN7968 Rev.2.00
Jan 15, 2016
Page 4 of 23
ISL85003, ISL85003A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
FREQUENCY
(kHz)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
OPTION
SYNC
ISL85003FRZ
003F
-40 to +125
-40 to +125
500
500
12 Ld DFN
12 Ld DFN
L12.3x4
L12.3x4
ISL85003AFRZ
ISL85003EVAL2Z
ISL85003AEVAL2Z
ISL85003DEMO1Z
ISL85003ADEMO1Z
NOTES:
003A
Soft-Start
Evaluation Board
Evaluation Board
Demo Evaluation Board
Demo Evaluation Board
1. Add “-T” suffix for 6k unit, “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel
specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL85003, ISL85003A. For more information on MSL, please see tech
brief TB363.
4. The ISL85003 is provided with a frequency synchronization input. The ISL85003A is a version of the part with programmable soft-start.
TABLE 1. COMPONENTS SELECTION (Refer to Figures 1A and 1B)
V
0.8V
10µF
22µF
22µF
Open
1.8µH
301kΩ
Open
1V
1.2V
10µF
1.5V
10µF
1.8V
10µF
2.5V
10µF
3.3V
10µF
5V
OUT
C , C
10µF
22µF
22µF
Open
2.2µH
301kΩ
1.2MΩ
10µF
5
6
C
C
C
22µF
47µF
47µF
47µF
47µF
47µF
8
9
1
1
22µF
22µF
22µF
22µF
22µF
22µF
4.7pF
4.7µH
301kΩ
57.1kΩ
Open
4.7pF
3.3µH
301kΩ
344kΩ
4.7pF
3.3µH
301kΩ
241kΩ
4.7pF
3.3µH
301kΩ
142kΩ
4.7pF
4.7µH
301kΩ
96.3kΩ
L
2.2µH
301kΩ
604kΩ
R
1
2
R
NOTE: V = 12V, I
IN
= 3A; The components selection table is a suggestion for typical application using internal compensation mode. For application
OUT
that required high output capacitance greater than 200µF, R should be adjusted to maintain loop response bandwidth about 40kHz. See “Loop
1
Compensation Design” on page 19 for more detail.
TABLE 2. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
INTERNAL/EXTERNAL
COMPENSATION
EXTERNAL FREQUENCY
SYNC
PROGRAMMABLE
SOFT-START
PART NUMBER
ISL85003
SWITCHING FREQUENCY
300kHz to 2MHz
500kHz
Yes
Yes
Yes
No
No
ISL85003A
Yes
FN7968 Rev.2.00
Jan 15, 2016
Page 5 of 23
ISL85003, ISL85003A
Absolute Maximum Ratings
Thermal Information
VIN, EN to AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
PHASE to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . -0.7V to +24V (DC)
PHASE to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . -2V to +24V (40ns)
FB to AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
BOOT to PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
VDD, COMP, SYNC, PG to AGND and PGND. . . . . . . . . . . . . . . -0.3V to +7V
Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . .-55°C to +150°C
ESD Rating
Thermal Resistance
DFN Package (Notes 5, 6) . . . . . . . . . . . . . .
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
(°C/W)
49
(°C/W)
5
JA
JC
Recommended Operating Conditions
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 150V
Charged Device Model (Tested per JESD22-A115-A). . . . . . . . . . . . . 1kV
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 18V
IN
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
6. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications All parameter limits are established over the Recommended Operating Conditions with T = -40°C to +125°C,
J
and with V = 12V unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply across the operating junction temperature range,
IN
A
-40°C to +125°C.
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7) TYP (Note 7) UNIT
SUPPLY VOLTAGE
V
V
Voltage Range
V
I
4.5
18
V
IN
IN
IN
Quiescent Supply Current
SYNC = Low, EN > 1V, FB = 0.85V, not
switching
3.2
6
4.5
mA
Q
V
Shutdown Supply Current
I
EN = AGND
11
µA
IN
SD
UNDERVOLTAGE LOCKOUT
Rising Edge
Falling Edge
4.20
3.8
4.35
V
V
V
UVLO Threshold
IN
3.6
4.3
INTERNAL VDD LDO
V
V
Output Voltage
V
= 6V to 18V, I = 0mA to 30mA
VDD
5.00
50
5.50
V
DD
DD
IN
Output Current Limit
mA
OSCILLATOR
Nominal Switching Frequency
Minimum On-Time
Minimum Off-Time
Synchronization Range
SYNC High-Time
f
400
500
120
140
600
140
kHz
ns
ns
kHz
ns
ns
V
SW
t
I
= 0mA (Note 8)
ON
OUT
t
(Note 8)
180
OFF
SYNC
ISL85003
ISL85003
ISL85003
ISL85003
ISL85003
300
100
100
2000
t
HI
SYNC Low-Time
t
LO
SYNC Logic Input Low
SYNC Logic Input High
ERROR AMPLIFIER
FB Regulation Voltage
FB Leakage Current
Open Loop Bandwidth
Gain
0.50
1.20
V
V
V
V
= 4.5V to 18V
0.792
0.8
0.3
5.5
70
0.808
10
V
FB
IN
= 0.8V (Note 8)
nA
FB
BW
MHz
dB
FN7968 Rev.2.00
Jan 15, 2016
Page 6 of 23
ISL85003, ISL85003A
Electrical Specifications All parameter limits are established over the Recommended Operating Conditions with T = -40°C to +125°C,
J
and with V = 12V unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply across the operating junction temperature range,
IN
A
-40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
Output Drive
SYMBOL
TEST CONDITIONS
= 1.5V
(Note 7) TYP (Note 7) UNIT
V
±110
0.2
µA
Ω
COMP
Current Sense Gain
Slope Compensation
ENABLE INPUT
RT
Se
f
500kHz
550
mV/µs
SW =
Rising Edge
Hysteresis
0.5
60
0.6
0.7
V
EN Input Threshold
100
140
mV
SOFT-START FUNCTION
Default Soft-Start Time
ISL85003, ISL85003A with soft-start open
ISL85003A
1
2.3
3.5
3.6
4.5
ms
µA
SS Internal Soft-Start Charging Current
POWER GOOD OPEN DRAIN OUTPUT
Output Low Voltage
2.5
I
= 5mA sinking
0.25
0.01
85
V
µA
%
PG
PG Pin Leakage Current
PG Lower Threshold
V
= V
PG DD
Percentage of output regulation
Percentage of output regulation
80
90
PG Upper Threshold
110
115
3
120
%
PG Thresholds Hysteresis
%
Rising Edge
Falling Edge
1.5
18
ms
µs
Delay Time
FAULT PROTECTION
Positive Overcurrent Protection Threshold
Negative Overcurrent Protection Threshold
I
4.0
5.0
6.0
A
A
POCP
I
Current forced into PHASE node, high-side
MOSFET is off, SYNC = High
-3.2
-2.2
-1.1
NOCP
Positive Overcurrent Protection Low-Side MOSFET
Current in low-side MOSFET at end of low-side
cycle.
6
A
19
20
1
V
V
V
Overvoltage Threshold
IN
Hysteresis
T
Rising Threshold
Hysteresis
165
10
°C
°C
SD
Thermal Shutdown Temperature
POWER MOSFET
T
HYS
High-Side MOSFET r
R
I
I
= 100mA
= 100mA
65
45
10
110
75
mΩ
mΩ
KΩ
DS(ON)
HDS
PHASE
Low-Side MOSFET r
R
LDS
DS(ON)
PHASE
PHASE Pull-Down Resistor
DIODE EMULATION
Zero Crossing Threshold
NOTES:
EN = AGND
ISL85003
150
mA
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. Compliance to limits is assured by characterization and design.
FN7968 Rev.2.00
Jan 15, 2016
Page 7 of 23
ISL85003, ISL85003A
Typical Performance Curves Circuit of V = 12V, V = 5V, I = 3A, T = -40°C to +125°C unless otherwise noted.
IN
OUT
OUT
J
Typical values are at T = +25°C.
A
100
100
90
90
80
70
60
50
40
80
2.5V
1.8V
OUT
OUT
2.5V
1.2V
OUT
3.3V
OUT
1.5V
OUT
OUT
70
1V
OUT
3.3V
1.8V
OUT
OUT
1V
OUT
60
1.5V
OUT
50
1.2V
OUT
40
0
0.1
1.0
10
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 3. EFFICIENCY vs LOAD, 5V DCM
IN
FIGURE 4. EFFICIENCY vs LOAD, 5V CCM
IN
100
90
80
70
60
50
40
100
90
80
70
60
50
40
3.3V
OUT
5V
OUT
3.3V
OUT
1.5V
1.8V
OUT
OUT
2.5V
1.2V
OUT
1.2V
OUT
OUT
1V
1.5V
OUT
OUT
1V
OUT
1.8V
OUT
5V
OUT
2.5V
0.1
OUT
0
1.0
10
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 5. EFFICIENCY vs LOAD, 12V DCM
IN
FIGURE 6. EFFICIENCY vs LOAD, 12V CCM
IN
100
90
80
70
60
50
40
100
90
80
70
60
50
40
1.8V
OUT
2.5V
OUT
3.3V
OUT
1.5V
OUT
3.3V
OUT
OUT
1.5V
OUT
5V
OUT
1.2V
OUT
1.8V
OUT
2.5V
OUT
OUT
1.2V
1V
1V
5V
OUT
OUT
0
0.1
OUTPUT LOAD (A)
1.0
10
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
OUTPUT LOAD (A)
0
3.0
FIGURE 7. EFFICIENCY vs LOAD, 18V DCM
IN
FIGURE 8. EFFICIENCY vs LOAD, 18V CCM
IN
FN7968 Rev.2.00
Jan 15, 2016
Page 8 of 23
ISL85003, ISL85003A
Typical Performance Curves Circuit of V = 12V, V = 5V, I = 3A, T = -40°C to +125°C unless otherwise noted.
IN
OUT
OUT
J
Typical values are at T = +25°C. (Continued)
A
1.006
1.004
1.002
1.000
0.998
0.996
0.994
1.204
1.202
1.200
1.198
1.196
1.194
1.192
5 V DCM
IN
IN
5 V DCM
IN
5 V CCM
5 V CCM
IN
12 V DCM
IN
12 V DCM
IN
12 V CCM
IN
12 V CCM
IN
18V DCM
IN
18 V CCM
IN
3.0
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
OUTPUT LOAD (A)
0
0.3
0.9 1.2 1.5 1.8 2.1
OUTPUT LOAD (A)
2.7 3.0
0.6
2.4
FIGURE 10. V
OUT
REGULATION vs LOAD, 1.2V
FIGURE 9. V
OUT
REGULATION vs LOAD, 1V
1.500
1.498
1.496
1.494
1.492
1.490
1.488
1.800
1.798
1.796
1.794
1.792
1.790
1.788
5V DCM
IN
5V CCM
IN
5V DCM
IN
5V CCM
IN
12V DCM
12V DCM
IN
IN
12V CCM
IN
12V CCM
IN
18V DCM
IN
18V DCM
IN
18V CCM
IN
18V CCM
IN
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
OUTPUT LOAD (A)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
OUTPUT LOAD (A)
FIGURE 11. V
OUT
REGULATION vs LOAD, 1.5V
FIGURE 12. V
REGULATION vs LOAD, 1.8V
OUT
3.330
3.328
3.326
3.324
3.322
3.320
3.318
2.486
2.484
2.482
2.480
2.478
2.476
2.474
5V DCM
IN
5V DCM
IN
5V CCM
IN
5V CCM
IN
12V DCM
IN
12V DCM
IN
12V CCM
IN
12V CCM
IN
18V DCM
IN
18 V CCM
18V DCM
IN
IN
18V CCM
IN
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
OUTPUT LOAD (A)
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
OUTPUT LOAD (A)
FIGURE 13. V
OUT
REGULATION vs LOAD, 2.5V
FIGURE 14. V REGULATION vs LOAD, 3.3V
OUT
FN7968 Rev.2.00
Jan 15, 2016
Page 9 of 23
ISL85003, ISL85003A
Typical Performance Curves Circuit of V = 12V, V = 5V, I = 3A, T = -40°C to +125°C unless otherwise noted.
IN
OUT
OUT
J
Typical values are at T = +25°C. (Continued)
A
4.989
4.986
4.983
4.980
4.977
4.974
4.971
7V DCM
IN
7V CCM
IN
PHASE 10V/DIV
12V DCM
IN
12V CCM
IN
18V DCM
IN
18V CCM
V
5V/DIV
IN
OUT
V
10V/DIV
EN
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
OUTPUT LOAD (A)
PG 5V/DIV
1ms/DIV
FIGURE 15. V
OUT
REGULATION vs LOAD 5V
FIGURE 16. START-UP V AT NO LOAD (DCM)
EN
PHASE 10V/DIV
PHASE 10V/DIV
V
5V/DIV
OUT
V
5V/DIV
OUT
V
10V/DIV
EN
V
10V/DIV
EN
PG 5V/DIV
PG 5V/DIV
50ms/DIV
1ms/DIV
FIGURE 17. START-UP V AT NO LOAD (CCM)
EN
FIGURE 18. SHUTDOWN V AT NO LOAD (DCM)
EN
PHASE 10V/DIV
PHASE 10V/DIV
V
5V/DIV
OUT
V
5V/DIV
OUT
V
10V/DIV
V
10V/DIV
EN
EN
PG 5V/DIV
PG 5V/DIV
50ms/DIV
1ms/DIV
FIGURE 19. SHUTDOWN V AT NO LOAD (CCM)
EN
FIGURE 20. START-UP V AT 3A LOAD
EN
FN7968 Rev.2.00
Jan 15, 2016
Page 10 of 23
ISL85003, ISL85003A
Typical Performance Curves Circuit of V = 12V, V = 5V, I = 3A, T = -40°C to +125°C unless otherwise noted.
IN
OUT
OUT
J
Typical values are at T = +25°C. (Continued)
A
PHASE 10V/DIV
V
10V/DIV
IN
V
5V/DIV
V
I
5V/DIV
OUT
OUT
2A/DIV
L
V
10V/DIV
EN
PG 5V/DIV
PG 5V/DIV
1ms/DIV
50ms/DIV
FIGURE 21. SHUTDOWN V AT 3A LOAD
EN
FIGURE 22. START-UP V AT NO LOAD (CCM)
IN
V
10V/DIV
IN
V
10V/DIV
IN
V
5V/DIV
OUT
V
5V/DIV
OUT
I
2A/DIV
I
2A/DIV
L
L
PG 5V/DIV
PG 5V/DIV
100ms/DIV
1ms/DIV
FIGURE 23. SHUTDOWN V AT NO LOAD (CCM)
IN
FIGURE 24. START-UP V AT NO LOAD (DCM)
IN
V
10V/DIV
V
10V/DIV
IN
IN
V
5V/DIV
OUT
V
5V/DIV
OUT
I
2A/DIV
L
I
2A/DIV
L
PG 5V/DIV
PG 5V/DIV
100ms/DIV
1ms/DIV
FIGURE 25. SHUTDOWN V AT NO LOAD (DCM)
IN
FIGURE 26. STAR-TUP V AT 3A LOAD
IN
FN7968 Rev.2.00
Jan 15, 2016
Page 11 of 23
ISL85003, ISL85003A
Typical Performance Curves Circuit of V = 12V, V = 5V, I = 3A, T = -40°C to +125°C unless otherwise noted.
IN
OUT
OUT
J
Typical values are at T = +25°C. (Continued)
A
V
10V/DIV
IN
PHASE 5V/DIV
V
I
5V/DIV
OUT
2A/DIV
L
PG 5V/DIV
20ns/DIV
1ms/DIV
FIGURE 28. JITTER AT NO LOAD (CCM )
FIGURE 27. SHUTDOWN V AT 3A LOAD
IN
PHASE 5V/DIV
PHASE 5V/DIV
V
10mV/DIV
OUT
I
2A/DIV
L
500ns/DIV
20ns/DIV
FIGURE 29. JITTER AT FULL LOAD 3A (CCM)
FIGURE 30. STEADY STATE AT NO LOAD CCM
PHASE 5V/DIV
PHASE 5V/DIV
V
10mV/DIV
OUT
V
20mV/DIV
OUT
I
0.2A/DIV
L
I
2A/DIV
L
500ns/DIV
50µs/DIV
FIGURE 31. STEADY STATE AT NO LOAD DCM
FIGURE 32. STEADY STATE AT 3A LOAD DCM
FN7968 Rev.2.00
Jan 15, 2016
Page 12 of 23
ISL85003, ISL85003A
Typical Performance Curves Circuit of V = 12V, V = 5V, I = 3A, T = -40°C to +125°C unless otherwise noted.
IN
OUT
OUT
J
Typical values are at T = +25°C. (Continued)
A
I
2A/DIV
L
I
2A/DIV
L
V
RIPPLE 100mV/DIV
100µs/DIV
V
RIPPLE 50mV/DIV
OUT
OUT
100µs/DIV
FIGURE 33. LOAD TRANSIENT (CCM)
FIGURE 34. LOAD TRANSIENT (DCM)
PHASE 10V/DIV
V
5V/DIV
OUT
V
2V/DIV
OUT
I
2A/DIV
L
I
2A/DIV
OUT
PG 5V/DIV
PG 5V/DIV
100µs/DIV
1ms/DIV
FIGURE 35. OUTPUT SHORT-CIRCUIT
FIGURE 36. OVERCURRENT PROTECTION
PHASE 10V/DIV
PHASE 10V/DIV
V
RIPPLE 20mV/DIV
OUT
V
RIPPLE 50mV/DIV
OUT
I
1A/DIV
L
I
1A/DIV
L
10µs/DIV
5µs/DIV
FIGURE 37. DCM TO CCM TRANSITION
FIGURE 38. CCM TO DCM TRANSITION
FN7968 Rev.2.00
Jan 15, 2016
Page 13 of 23
ISL85003, ISL85003A
Typical Performance Curves Circuit of V = 12V, V = 5V, I = 3A, T = -40°C to +125°C unless otherwise noted.
IN
OUT
OUT
J
Typical values are at T = +25°C. (Continued)
A
V
2V/DIV
+165°C
OUT
PHASE 10V/DIV
2V/DIV
V
OUT
I
2A/DIV
L
PG 2V/DIV
PG 5V/DIV
1µs/DIV
20ms/DIV
FIGURE 40. OVER-TEMPERATURE PROTECTION
FIGURE 39. 0VERVOLTAGE PROTECTION
FN7968 Rev.2.00
Jan 15, 2016
Page 14 of 23
ISL85003, ISL85003A
PWM operation is initialized by the clock from the oscillator. The
upper MOSFET is turned on at the beginning of a cycle and the
current in the MOSFET starts to ramp up. When the sum of the
current amplifier CSA signal and the slope compensation reaches
the control reference of the current loop, the PWM comparator
sends a signal to the logic to turn off the upper MOSFET and turn
on the lower MOSFET. The lower MOSFET stays on until the end of
the cycle. Figure 41 shows the typical operating waveforms during
Continuous Conduction Mode (CCM) operation. The dotted lines
illustrate the sum of the compensation ramp and the
Detailed Description
The ISL85003 and ISL85003A combine a synchronous buck
controller with a pair of integrated switching MOSFETs. The buck
controller drives the internal high-side and low-side N-channel
MOSFETs to deliver load currents up to 3A. The buck regulator
can operate from an unregulated DC source, such as a battery,
with a voltage ranging from +4.5V to +18V. An internal 5V LDO
voltage regulator is used to bias the controller. The converter
output voltage is programmed using an external resistor divider
and will generate regulated voltages down to 0.8V. These
features make the regulator suited for a wide range of
applications.
current-sense amplifier’s output.
V
EAMP
The controller uses a current mode loop, which simplifies the
loop compensation and permits fixed frequency operation over a
wide range of input and output voltages. The internal feedback
loop compensation option allows for simple circuit design. The
regulator switches at a default of 500kHz or it can be
V
CSA
DUTY
CYCLE
synchronized from 300kHz to 2MHz on an ISL85003.
I
L
The buck regulator is equipped with a lossless current limit
scheme. The current in the output stage is derived from
temperature compensated measurements of the drain-to-source
voltage of the internal power MOSFETs. The current limit
threshold is internally set at 5A.
V
OUT
FIGURE 41. CCM OPERATION WAVEFORMS
Operation Initialization
Light-Load Operation
Pull EN high to start operation. The power-on reset circuitry will
prevent operation if the input voltage is below 4.2V. Once the
power-on reset requirement is met, the controller will soft-start
with a 2ms ramp on an ISL85003 or at a rate determined by the
value of a capacitor connected between SS and AGND on an
ISL85003A.
The ISL85003 monitors both the current in the low-side MOSFET
and the voltage of the FB node for regulation. Pulling the SYNC
pin low allows the ISL85003 to enter discontinuous operation
when lightly loaded by operating the low-side MOSFET in Diode
Emulation Mode (DEM). In this mode, reverse current is not
allowed in the inductor, and the output falls naturally to the
regulation voltage before the high-side MOSFET is switched for
the next cycle. Figure 42 shows the transition from CCM to DCM
operation. In CCM mode, the boundary is set by Equation 1:
CCM Control Scheme
The regulator employs a current-mode pulse-width modulation
control scheme for fast transient response and pulse-by-pulse
current limiting. The current loop consists of the oscillator, the
PWM comparator, current sensing circuit, and a slope
compensation circuit. The gain of the current sensing circuit is
typically 200mV/A and the slope compensation is 1.1V/T. The
reference for the current loop is in turn provided by the output of
an Error Amplifier (EA), which compares the feedback signal at
the FB pin to the integrated 0.8V reference. Thus, the output
voltage is regulated by using the error amplifier to control the
reference for the current loop.
V
1 – D
OUT
(EQ. 1)
----------------------------------
=
I
OUT
2Lf
SW
Where D = duty cycle, f
SW
= switching frequency, L = inductor
value, I
= output loading current, V
= output voltage.
OUT
OUT
The error amplifier is an operational amplifier that converts the
voltage error signal to a voltage output. The voltage loop is
internally compensated with the 30pF and 600kΩ RC network
that can support most applications.
FN7968 Rev.2.00
Jan 15, 2016
Page 15 of 23
ISL85003, ISL85003A
CCM
DCM
CLOCK
I
L
LOAD CURRENT
0
V
OUT
NOMINAL
FIGURE 42. DCM MODE OPERATION WAVEFORMS
Synchronization Control
R
0.8V
1
----------------------------------
R
=
(EQ. 3)
2
V
– 0.8V
The ISL85003 can be synchronized from 300kHz to 2MHz by an
external signal applied to the SYNC pin. The rising edge on the SYNC
triggers the rising edge of the PHASE pulse. Make sure that the
on-time of the SYNC pulse is greater than 100ns. Although the
maximum synchronized frequency can be as high as 2MHz, the
ISL85003 is a current mode regulator that requires a minimum
of 140ns on-time to regulate properly. As an example, the
maximum recommended synchronized frequency will be about
OUT
If the output voltage desired is 0.8V, then R is left unpopulated.
R is still required to set the low frequency pole of the modulator
compensation.
2
1
V
OUT
R1
R2
-
600kHz with 12V and 1V
.
+
IN OUT
EA
Enable, Soft-Start and Disable
Chip operation begins after V exceeds its rising POR trip point
0.8V
REFERENCE
IN
(nominal 4.2V). If EN is held low externally, nothing happens until
this pin is released. Once the voltage on the EN pin is above 0.6V,
the LDO powers up and soft-start control begins. The default
soft-start time is 2ms.
FIGURE 43. EXTERNAL RESISTOR DIVIDER
Protection Features
On the ISL85003A, let SS float to select the internal soft-start
time with a default of 2ms. The soft-start time is extended by
connecting an external capacitor between SS and AGND. A 3.5µA
current source charges up the capacitor. The soft-start capacitor
is charged until the voltage on the SS pin reaches a 2.0V clamp
level. However, the output voltage reaches its regulation value
when the voltage on the SS pin reaches approximately 0.9V. The
capacitor, along with an internal 3.5µA current source, sets the
The regulator limits current in all on-chip power devices.
Overcurrent limits are applied to the two output switching
MOSFETs as well as to the LDO linear regulator that feeds VDD.
Input and output overvoltage protection circuitry on the switching
regulator provides a second layer of protection.
Switching Regulator Overcurrent Protection
soft-start interval of the converter, t , according to Equation 2:
SS
Current flowing through the internal high-side switching MOSFET
is monitored during the on-time. The current is compared to a
nominal 5A overcurrent limit. If the measured current exceeds
the overcurrent limit reference level, the high-side MOSFET is
immediately turned off and will not turn on again until the next
switching cycle. Current through the low-side switching MOSFET
is sampled during off time. If the low-side MOSFET current
exceeds 6A at the end of the low-side cycle, then the high-side
MOSFET will skip the next cycle, allowing the inductor current to
decay to a safe level before resuming switching.
(EQ. 2)
C
nF = 4.1 t mS – 1.6nF
SS
SS
Output Voltage Selection
The regulator output voltage is programmed using an external
resistor divider that scales the feedback relative to the internal
reference voltage. The scaled voltage is fed back to the inverting
input of the error amplifier; refer to Figure 43.
The output voltage programming resistor, R , will depend on the
2
value chosen for the feedback resistor, R , and the desired
1
Once an output overload condition is removed, the output voltage
will rise into regulation at the internal SS rate.
regulator output voltage, V ; (see Equation 3). The R value will
OUT
1
determine the gain of the feedback loop. (See “Loop
Compensation Design” on page 19) for more details. The value
for the feedback resistor is typically between 10kΩ and 400kΩ.
FN7968 Rev.2.00
Jan 15, 2016
Page 16 of 23
ISL85003, ISL85003A
T
3.0
2.5
Negative Current Protection
1V
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the low-side MOSFET, as
shown in “Functional Block Diagram” on page 3. When the
inductor current reaches -2.2A, the synchronous rectifier is turned
off. This limits the ability of the regulator to actively pull down on
the output and prevents large reverse currents that may fall
outside the range of the high-side current sense amp.
3.3V
1.8V
2.0
2.5V
5V
1.5
1.0
0.5
0
Output Overvoltage Protection
V
= 12V, ZERO LFM
IN
The output overvoltage protection is triggered when the output
voltage exceeds 115% of the set voltage. In this condition,
high-side and low-side MOSFETs are tri-stated until the output
drops to within the regulation band. Once the output is in
regulation, the controller will restart under internal SS control.
50
60
70
80
90
100
110
120
130
TEMPERATURE (°C)
FIGURE 44. DERATING CURVE vs TEMPERATURE
Application Guidelines
Input Overvoltage Protection
BOOT Undervoltage Detection
The input overvoltage protection system prevents operation of the
switching regulator whenever the input voltage is higher than 20V.
The high-side and low-side MOSFETs are tri-stated and the
converter will restart under internal SS control when the input
voltage returns to normal.
The internal driver of the high-side FET is equipped with a BOOT
Undervoltage (UV) detection circuit. In the event the voltage
difference between BOOT and PHASE falls below 2.5V, the UV
detection circuit allows the low-side MOSFET on for 300ns, to
recharge the bootstrap capacitor.
Thermal Overload Protection
Thermal overload protection limits the maximum die
temperature, thus the total power dissipation in the regulator. A
sensor on the chip monitors the junction temperature. A signal is
sent to the fault monitor circuits whenever the junction
While the ISL85003 includes an internal bootstrap diode,
efficiency can be improved by using an external supply voltage
and bootstrap Schottky diode. The external diode is then sourced
from a fixed external 5V supply or from the output of the
switching regulator if this is at 5V. The bootstrap diode can be a
low cost type, such as the BAT54.
temperature (T ) exceeds +165°C and this causes the switching
J
regulator and LDO to shut down.
PHASE
The switching regulator turns on again and soft-starts after the
IC’s junction temperature cool by 10°C. The switching regulator
exhibits hiccup mode operation during continuous thermal
overload conditions. For continuous operation, do not exceed the
+125°C junction temperature rating.
C
4
µ
0.1 F
BOOT
ISL85003
ISL85003A
BAT54
5V
Power Derating Characteristics
To prevent the regulator from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 4:
or 5V SOURCE
OUT
FIGURE 45. EXTERNAL BOOTSTRAP DIODE
(EQ. 4)
T
= PD
JA
RISE
Switching Regulator Output Capacitor
Selection
Where PD is the power dissipated by the regulator and θ is the
thermal resistance from the junction of the die to the ambient
JA
temperature. The junction temperature, T , is given by
An output capacitor is required to filter the inductor current and
supply the load transient current. The filtering requirements are a
function of the switching frequency, the ripple current and the
required output ripple. The load transient requirements are a
function of the slew rate (di/dt) and the magnitude of the transient
load current. These requirements are generally met with a mix of
capacitor types and careful layout.
J
Equation 5:
(EQ. 5)
T
= T + T
RISE
J
A
Where T is the ambient temperature. For the DFN package, the
A
θ
is 49 (°C/W).
JA
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C when considering
the thermal design.
High frequency ceramic capacitors initially supply the transient and
slow the current load rate seen by the bulk capacitors. The bulk filter
capacitor values are generally determined by the (Equivalent Series
Resistance) ESR and voltage rating requirements rather than actual
capacitance requirements.
FN7968 Rev.2.00
Jan 15, 2016
Page 17 of 23
ISL85003, ISL85003A
V
V
= ESR I
tran
(EQ. 6)
(EQ. 7)
ESR
ESL
SAG
DV
dI
tran
HUMP
---------------
dt
= ESL
V
OUT
2
L
I
DV
ESR
out tran
(EQ. 8)
(EQ. 9)
-------------------------------------------------
V
V
=
C
V – V
out
out
in
DV
DV
SAG
2
L
I
out tran
ESL
--------------------------------
=
HUMP
C
V
out
out
Where: I
= Output Load Current Transient and C = Total
out
I
tran
Output Capacitance.
OUT
I
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. The ESR and the ESL are
typically the major contributing factors in determining the output
capacitance. The number of output capacitors can be
determined by using Equation 10, which relates the ESR and ESL
of the capacitors to the transient load step and the voltage limit
(Vo):
tran
FIGURE 46. TYPICAL TRANSIENT RESPONSE
ESL I
tran
-----------------------------
+ ESR I
tran
The high frequency decoupling capacitors should be placed as close
to the power pins of the load as physically possible. Be careful not to
add inductance in the circuit board wiring that could cancel the
usefulness of these low inductance components. Consult with the
manufacturer of the load on specific decoupling requirements.
dt
(EQ. 10)
-------------------------------------------------------------------
Number of Caps =
V
o
If V
SAG
or V are found to be too large for the output
HUMP
voltage limits, then the amount of capacitance may need to be
increased. In this situation, a trade-off between output
inductance and output capacitance may be necessary.
The shape of the output voltage waveform during a load transient
that represents the worst case loading conditions will ultimately
determine the number of output capacitors and their type. When
this load transient is applied to the converter, most of the energy
required by the load is initially delivered from the output capacitors.
This is due to the finite amount of time required for the inductor
current to slew up to the level of the output current required by the
load. This phenomenon results in a temporary dip in the output
voltage. At the very edge of the transient, the Equivalent Series
Inductance (ESL) of each capacitor induces a spike that adds on top
of the existing voltage drop due to the ESR.
The ESL of the capacitors, which is an important parameter in
the above equations, is not usually listed in specification.
Practically, it can be approximated using Equation 11 if an
Impedance vs Frequency curve is given for a specific capacitor:
1
(EQ. 11)
----------------------------------------
ESL =
2
C2 f
res
Where: f is the resonant frequency where the lowest
res
impedance is achieved.
After the initial spike, attributable to the ESR and ESL of the
capacitors, the output voltage experiences sag. This sag is a direct
consequence of the amount of capacitance on the output.
The ESL of the capacitors becomes a concern when designing
circuits that supply power to loads with high rates of change in
the current.
During the removal of the same output load, the energy stored in the
inductor is dumped into the output capacitors. This energy dumping
creates a temporary hump in the output voltage. This hump, as with
the sag, can be attributed to the total amount of capacitance on the
output. Figure 46 shows a typical response to a load transient.
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple
requirements and minimize the converter’s response time to the
load transient. The inductor value determines the converter’s
ripple current and the output ripple voltage is a function of the
ripple current. The ripple voltage and current are approximated
by Equations 12 and 13:
The amplitudes of the different types of voltage excursions can
be approximated using Equations 6, 7, 8 and 9.
V – V
V
OUT
V
IN
IN
OUT
(EQ. 12)
------------------------------------ ---------------
I =
Fs L
(EQ. 13)
V
= I x ESR
OUT
FN7968 Rev.2.00
Jan 15, 2016
Page 18 of 23
ISL85003, ISL85003A
Increasing the value of inductance reduces the ripple current and
voltage. However, the large inductance values reduce the
converter’s response time to a load transient. Furthermore, the
ripple current is an important signed in current mode control.
Therefore, set the ripple inductor current to approximately 30%
of the maximum output current or about 1A for optimized
performance.
For a through-hole design, several electrolytic capacitors may be
needed, especially at temperature less than -25°C. The
electrolytic's ESR can increase ten times higher than at room
temperature and cause input line oscillation. In this case, a more
thermally stable capacitor such as X7R ceramic should be used.
For surface mount designs, solid tantalum capacitors can be
used, but caution must be exercised with regard to the capacitor
surge current rating. Some capacitor series available from
reputable manufacturers are surge current tested.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
regulator will provide either 0% or 100% duty cycle in response
to a load transient. The response time is the time required to
slew the inductor current from an initial current value to the
transient current level. During this interval, the difference
between the inductor current and the transient current level
must be supplied by the output capacitor. Minimizing the
response time can minimize the output capacitance required.
Loop Compensation Design
When COMP is not connected to GND, the COMP pin is active for
external loop compensation. In an application where extreme
temperature such as less than -10°C or greater than +85°C,
external compensation mode should be used. The regulator uses
constant frequency peak current mode control architecture to
achieve a fast loop transient response. An accurate current
sensing pilot device in parallel with the upper MOSFET is used for
peak current control signal and overcurrent protection. The
inductor is not considered as a state variable since its peak
current is constant, and the system becomes a single order
system. It is much easier to design a type II compensator to
stabilize the loop than to implement voltage mode control. Peak
current mode control has an inherent input voltage feed-forward
function to achieve good line regulation. Figure 47 shows the
small signal model of the synchronous buck regulator.
The response time to a transient is different for the application of
load and the removal of load. Equations 14 and 15 give the
approximate response time interval for application and removal
of a transient load:
L x I
TRAN
- V
OUT
(EQ. 14)
t
=
RISE
V
IN
L x I
V
TRAN
(EQ. 15)
t
=
FALL
^
^
^
L
R
LP
i
i
P
L
v
in
OUT
o
Where: I
TRAN
response time to the application of load, and t
response time to the removal of load. The worst case response
time can be either at the application or removal of load. Be sure
to check both of these equations at the minimum and maximum
output levels for the worst case response time.
is the transient load current step, t
is the
^
d
RISE
is the
V
IN
^
^
1:D
I d
V
L
IN
FALL
Rc
Co
+
R
T
Ro
T (S)
i
^
d
K
Input Capacitor Selection
Fm
Use a mix of input bypass capacitors to control the input voltage
ripple. Use ceramic capacitors for high frequency decoupling and
bulk capacitors to supply the current needed each time the
switching MOSFET turns on. Place the ceramic capacitors
physically close to the MOSFET VIN pins (switching MOSFET
drain) and PGND.
T (S)
+
v
He(S)
^
Vcomp
-Av(S)
FIGURE 47. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
The important parameters for the bulk input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and largest RMS current required by the
circuit. Their voltage rating should be at least 1.25x greater than
the maximum input voltage, while a voltage rating of 1.5x is a
conservative guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
C
7
Vo
R
6
C
6
R
R
C
3
1
2
-
V
COMP
V
FB
+
V
REF
The maximum RMS current required by the regulator may be
more closely approximated through Equation 16:
FIGURE 48. TYPE II COMPENSATOR
2
VOUT
-------------
VIN
VIN – VOUT VOUT
2
1
12
------ ---------------------------- -------------
IRMS
=
IOUT
+
L fs
VIN
MAX
MAX
(EQ. 16)
FN7968 Rev.2.00
Jan 15, 2016
Page 19 of 23
ISL85003, ISL85003A
Figure 48 shows the type II compensator and its transfer function
is expressed, as shown in Equation 17:
5V 60F
10 3A 153k
(EQ. 23)
-----------------------------------------
= 65pF
C
=
6
S
S
------------
------------
1 +
1 +
ˆ
v
1
1.5m 60F
10 153k
1
comp
cz1
cz2
---------------------------------------------------
(EQ. 17)
C = max[-------------------------------------,
]= (0.06pF, 4.2pF)
---------------- ------------------------------------- --------------------------------------------------------------
A S=
=
7
500kHz 153k
v
ˆ
C + C R
S
S
v
6
7
1
o
-------------
-------------
S 1 +
1 +
(EQ. 24)
cp1
cp2
Use the closest standard values for R , C and C . There is
6
6
7
approximately 3pF parasitic capacitance from V
to GND;
COMP
Where,
therefore, C is optional. Use R = 150kΩ, C = 62pF, and
7
6
6
C
+ C
7
1
1
6
C = OPEN.
7
--------------
--------------
----------------------
=
,
=
=
350kHz
cp2
cz1
cz2
cp1
R C
R C
R C C
6 6 7
6
6
1
3
1
(EQ. 25)
---------------------------------------------
C =
= 62pF
3
250kHz 51k
Compensator Design Goal
Use C = 68pF. Note that C may increase the loop bandwidth
3
3
from the previous estimated value. Figure 49 shows the
simulated voltage loop gain. It has a 42kHz loop bandwidth with
54°of phase margin and 17dB of gain margin. It may be more
desirable to achieve an increased phase margin. This can be
accomplished by lowering R or increasing C by 20% to 30%.
High DC Gain
Choose Loop bandwidth f of approximately 50kHz or 1/10 of
the switching frequency.
c
Gain margin: >10dB
6
3
Phase margin: >40°
60
40
20
0
BANDWIDTH OF CLOSE LOOP
The compensator design procedure is as follows:
The loop gain at crossover frequency of f has a unity gain.
c
Therefore, the compensator resistance R is determined by
Equation 18.
6
(EQ. 18)
R
= 2f C R R f C R
c o t 1 c o 1
6
-20
-40
Note that C is the actual capacitance seen by the regulator,
o
which may include ceramic high frequency decoupling and bulk
output capacitors. Ceramic may have to be derated by
-60
1.E+00
approximately 40% depending on dielectric, voltage stress and
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
temperature. Compensator capacitor C is then given by
6
FREQUENCY (kHz)
Equations 19 and 20.
R C
V C
o o
10I R
o 6
o
o
(EQ. 19)
(EQ. 20)
-------------- -------------------
C
=
=
6
120
80
40
0
10R
6
PHASE MARGIN CLOSED LOOP
R C
1
c
o
C = max[--------------,---------------]
7
10R f R
s 6
6
An optional zero can boost the phase margin. CZ2 is a zero due
to R and C
1
3
-40
-80
Put compensator zero, CZ2 from 1/2f to f .
c
c
1
(EQ. 21)
-------------------
C =
3
2f R
c
2
-120
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
For internal compensation mode, R is equal 600kΩ and C is
6
6
FREQUENCY (kHz)
30pF. Equation 18 can be rearranged to solve for R .
1
FIGURE 49. SIMULATED LOOP GAIN
Example: V = 12V, V = 5V, I = 3A, fSW = 500kHz, R = 51kΩ,
IN
O
O
1
R = 9.7kΩ, C = 2x47µF/3mΩ 6.3V ceramic (~60µF with
2
o
derating), L = 4.7µH, f = 50kHz, then compensator resistance
c
R :
6
(EQ. 22)
R
6
= 50k 60F 51k = 153k
FN7968 Rev.2.00
Jan 15, 2016
Page 20 of 23
ISL85003, ISL85003A
Layout Considerations
V
IN
The layout is very important in high frequency switching
converter design. With power devices switching efficiently at
500kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage spikes
can degrade efficiency, radiate noise into the circuit, and lead to
device overvoltage stress. Careful component layout and printed
circuit board design minimizes these voltage spikes.
V
IN
C
IN
ISL85003
ISL85003A
L
V
OUT1
PHASE
C
OUT1
PGND
COMP
As an example, consider the turn-off transition of the upper
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET and
is picked up by the internal body diode. Any parasitic inductance
in the switched current path generates a large voltage spike
during the switching interval. Careful component selection, tight
layout of the critical components and short, wide traces minimize
the magnitude of voltage spikes.
C
6
C
7
R
6
R
1
FB
R
PGND PAD
2
C
3
There are two sets of critical components in the regulator
switching converter. The switching components are the most
critical because they switch large amounts of energy and
therefore tend to generate large amounts of noise. Next are the
small signal components, which connect to sensitive nodes or
supply critical bypass current and signal coupling.
KEY
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 50. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
A multi-layer printed circuit board is recommended. Figure 50
shows the connections of the critical components in the
The critical small signal components include any bypass
capacitors, feedback components and compensation
components. Place the compensation components close to the
FB and COMP pins. The feedback resistors should be located as
close as possible to the FB pin with vias tied straight to the
ground plane.
converter. Note that capacitors C and C
could each
IN OUT
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground plane
and make all critical component ground connections with vias to
this layer. Dedicate another solid layer as a power plane and
break this plane into smaller islands of common voltage levels.
Keep the metal runs from the PHASE terminals to the output
inductor short. The power plane should support the input power
and output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the phase nodes. Use the remaining
printed circuit layers for small signal wiring.
In order to dissipate heat generated by the internal LDO and
MOSFETs, the ground pad should be connected to the internal
ground plane through at least five vias. This allows the heat to
move away from the IC and also ties the pad to the ground plane
through a low impedance path.
The switching components should be placed close to the
regulator first. Minimize the length of the connections between
the input capacitors, C , and the power switches by placing
IN
them nearby. Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible.
FN7968 Rev.2.00
Jan 15, 2016
Page 21 of 23
ISL85003, ISL85003A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN7968.2
CHANGE
Jan 15, 2016
Added the Related Literature section on page 1.
On page 4, updated VDD pin description by changing VIN range from “3V to 5.5V” to “4.5V to 5.5V”.
Updated Note 1 in the ordering information table to include all tape and reel options.
Added Table 2 on page 5.
Updated POD L12.3x4 to the latest revision the changes are as follows:
Tiebar Note 5 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
Jul 17, 2014
FN7968.1
Detailed Description on page 15 changed from 4.5A to 5A.
“Switching Regulator Overcurrent Protection” on page 16: Changed 4.5A to 5A.
Equation 12 on page 18, updated from “dI=/(Fs*L)*Vout/Vin” to “dI=(Vin-Vout)/(Fs*L)*Vout/Vin”
“Input Capacitor Selection” on page 19 : Change RESR to ESR
“Negative Current Protection” on page 17: Changed -2.5A to -2.2A.
Updated Package information from 4x3 to 3x4 on page 1, Pin Configuration on page 4, Ordering Information
on page 5, and replaced the “Package Outline Drawing” on page 23.
Updated the Ordering Information on page 5 to include the new Evaluation Boards that are now available.
Mar 21, 2014
FN7968.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2014-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7968 Rev.2.00
Jan 15, 2016
Page 22 of 23
ISL85003, ISL85003A
For the most recent package outline drawing, see L12.3x4.
Package Outline Drawing
L12.3x4
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/15
6
3.00
A
PIN #1
SEE DETAIL "X"
INDEX AREA
B
6
PIN 1
INDEX AREA
1
12
3.30 ±0.10
2X 2.50
6
(4X)
0.10
7
10X 0.50
12X 0.25 ±0.05
0.10M C A B
TOP VIEW
0.90 MAX
1.70
±0.10
4
C
12X 0.40 ± 0.05
SIDE VIEW
BOTTOM VIEW
(12X 0.60)
( 12 X 0.25)
( 3.30 )
( 2.50)
0.10 C
(10x 0.50)
C
0 . 203 REF
SEATING PLANE
0.08 C
(1.70)
0 . 00 MIN.
0 . 05 MAX.
( 2.80 )
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Reference document JEDEC MO-229.
FN7968 Rev.2.00
Jan 15, 2016
Page 23 of 23
相关型号：
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