ISL85033DUALEVAL1Z [RENESAS]
Wide VIN Dual Standard Buck Regulator With 3A/3A Continuous Output Current;
| 型号： | ISL85033DUALEVAL1Z |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Wide VIN Dual Standard Buck Regulator With 3A/3A Continuous Output Current |
| 文件： | 总26页 (文件大小：1888K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL85033
FN6676
Rev 8.00
February 17, 2015
Wide V Dual Standard Buck Regulator With 3A/3A Continuous Output Current
IN
The ISL85033 is a dual standard buck regulator capable of 3A
Features
per channel continuous output current. With an input range of
4.5V to 28V, it provides a high frequency power solution for a
variety of point of load applications.
• Wide input voltage range from 4.5V to 28V
• Adjustable output voltage with continuous output current up
to 3A
The PWM controller in the ISL85033 drives an internal
switching N-Channel power MOSFET and requires an external
Schottky diode to generate the output voltage. The integrated
power switch is optimized for excellent thermal performance
up to 3A of output current. The PWM regulator switches at a
default frequency of 500kHz and it can be user programmed
or synchronized from 300kHz to 2MHz. The ISL85033 utilizes
peak current mode control to provide flexibility in component
selection and minimize solution size. The protection features
include overcurrent, UVLO and thermal overload protection.
• Current mode control
• Adjustable switching frequency from 300kHz to 2MHz
• Independent power-good detection
• Selectable in-phase or out-of-phase PWM operation
• Independent, sequential, ratiometric or absolute tracking
between outputs
• Internal 2ms soft-start time
• Overcurrent/short circuit protection, thermal overload
protection, UVLO
The ISL85033 is available in a small 4mmx4mm Thin Quad
Flat No-Lead (TQFN) Pb-free package.
• Boot undervoltage detection
• Pb-free (RoHS compliant)
Related Literature
• AN1574 “ISL85033DUALEVAL1Z Wide VIN Dual Standard
Buck Regulator With 3A/3A Output Current”
Applications
• General purpose point-of-load DC/DC power conversion
• AN1585 “ISL85033EVAL2Z (Small Form) Wide VIN Dual
Standard Buck Regulator With 3A/3A Output Current - Short
Form”
• Set-top boxes
• FPGA power and STB power
• DVD and HDD drives
• AN1584 “ISL85033EVAL2Z (Small Form) Wide VIN Dual
Standard Buck Regulator With 3A/3A Output Current - Long
Form”
• LCD panels, TV power
• Cable modems
• AN1605 “ISL85033CRSHEVAL1Z Wide VIN Current sharing
Standard Buck Regulator With 6A Output Current”
100
90
80
70
60
50
40
12V
OUT
1MHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT LOAD (A)
FIGURE 1. EFFICIENCY vs LOAD, V = 28V, T = +25°C
IN
A
FN6676 Rev 8.00
February 17, 2015
Page 1 of 26
ISL85033
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-on Reset and Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Tracking and Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Buck Regulator Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
BOOT Undervoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Buck Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current Sharing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Theory of Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PWM Comparator Gain Fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Stage Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Rectifier Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FN6676 Rev 8.00
February 17, 2015
Page 2 of 26
ISL85033
Pin Configuration
ISL85033
(28 LD TQFN)
TOP VIEW
28
27 26 25 24
23 22
1
21
20
19
COMP1
FB1
COMP2
FB2
2
3
4
5
6
7
SS1
SS2
PGND1
BOOT1
PHASE1
PHASE1
18 PGND2
17
PD
BOOT2
16 PHASE2
15
PHASE2
8
9
10 11 12 13 14
Pin Descriptions
PIN NUMBER
SYMBOL
COMP1, COMP2
FB1, FB2
PIN DESCRIPTION
1, 21
COMP1, COMP2 are the output of the error amplifier.
2, 20
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. COMP is the
output of the error amplifier. The output voltage is set by an external resistor divider connected to FB.
In addition, the PWM regulator’s power-good and undervoltage protection circuits use FB1, FB2 to monitor
the regulator output voltage.
3, 19
SS1, SS2
Soft-start pins for each controller. The SS1, SS2 pins control the soft-start and sequence of their respective
outputs. A single capacitor from the SS pin to ground determines the output ramp rate. See the “Output
Tracking and Sequencing” on page 16 for soft-start and output tracking/sequencing details. If SS pins are
tied to VCC, an internal soft-start of 2ms will be used. Maximum C value is 100nF.
SS
4, 18
5, 17
PGND1, PGND2
BOOT1, BOOT2
Power ground connections. Connect directly to the system GND plane.
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the
necessary charge to turn on the internal N-Channel MOSFET. Connect an external capacitor from this pin to
PHASE.
6, 7, 15, 16
8, 9, 13, 14
PHASE1, PHASE2
VIN1, VIN2
Switch node output. It connects the source of the internal power MOSFET with the external output inductor
and with the cathode of the external diode.
The input supply for the power stage of the PWM regulator and the source for the internal linear regulator
that provides bias for the IC. Place a minimum of 10µF ceramic capacitance from each VIN to GND and
close to the IC for decoupling.
10, 12
EN1, EN2
PWM controller’s enable inputs. The PWM controllers are held off when the pin is pulled to ground. When
the voltage on this pin rises above 2V, the PWM controller is enabled. If EN1, EN2 pins are driven by an
external signal, the minimum off-time for EN1, EN2 should be:
EN_T_off s = 10s C
2.2nF
SS
where C is the soft-start pin capacitor (nF). The ISL85033 does not have debouncing to EN1, EN2 external
SS
signals.
11
VCC
Output of the internal 5V linear regulator. Decouple to PGND with a minimum of 4.7µF ceramic capacitor.
This pin is provided only for internal bias of ISL85033 (not to be loaded with current over 10mA).
FN6676 Rev 8.00
Page 3 of 26
February 17, 2015
ISL85033
Pin Descriptions(Continued)
PIN NUMBER
SYMBOL
SYNCOUT
SYNCIN
PIN DESCRIPTION
23
24
Synchronization output. Provides a signal that is the inverse of the SYNCIN signal.
Connect to an external signal for synchronization from 300kHz to 2MHz (negative edge trigger). SYNCIN is
not allowed to be floating.
When SYNCIN = logic 0, PHASE1 and PHASE2 are running at 180° out-of-phase.
When SYNCIN = logic 1, PHASE1 and PHASE2 are running at 0° in-phase.
When SYNCIN = an external clock, PHASE1 and PHASE2 are running at 180° out-of-phase.
External SYNC frequency applied to the SYNCIN pin should be at least 2.4 x the internal switching frequency
setting.
25
SGND
Signal ground connections. The exposed pad must be connected to SGND and soldered to the PCB. All
voltage levels are measured with respect to this pin.
26
27
NC
FS
This is a no connection pin.
Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for
adjustable frequency from 300kHz to 2MHz.
22, 28
PGOOD2, PGOOD1
PD
Open-drain power-good output that is pulled to ground when the output voltage is below regulation limits or
during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.
The exposed pad must be connected to the system GND plane with as many vias as possible for proper
electrical and thermal performance.
FN6676 Rev 8.00
February 17, 2015
Page 4 of 26
ISL85033
Typical Application Schematics
V
V
OUT2
OUT1
R
42.2k
R
5
25.5k
1
R
8.06k
R
2
8.06k
6
C
C
2
470pF
5
C
68pF
1
C
68pF
4
470pF
R
R
4
8
69.8k
69.8k
20
21
1
2
VIN1
VIN2
FS
27
19
8/9
VCC
SS2
VCC
VCC
C
71
µ
13/14
SS1
20 F
3
µ
10 F
C
72
PGOOD2
PGOOD1
22
28
ISL85033
L1
7µ
L
7µ
2
H
V
V
OUT1
3A
H
OUT2
3A
PHASE1
PHASE2
6/7
5
15/16
C
8
C
9
47 F
C
12
10nF
C
47 F
10nF
13
µ
D
1
BOOT1
D
µ
2
B340B
B340B
17
BOOT2
24 23 4/18
12 26 10 25
11
4.7µF
FIGURE 2. DUAL 3A OUTPUT (V RANGE FROM 4.5V TO 28V)
IN
FB2
V
OUT1
R
5
42.2k
R
6
8.06k
COMP2
C
5
C
68pF
R
0
4
7
1nF
FB2
8/9
R
8
34k
20
21
1
2
FS
VIN1
VIN2
27
VCC
C
20 F
SS2
SS1
71
µ
19
3
C
ss2
13/14
47nF
C
ss1
PGOOD2
PGOOD1
22
28
µ
C72
C8
10 F
47nF
ISL85033
V
OUT1
6A
PHASE1
V
OUT1
PHASE2
6/7
5
15/16
17
L
7µ
1
H
L
7µ
2
H
C
C
µ
47 F
12
9
C
13
µ
47 F
10n
F
10nF
BOOT1
D
D
1
2
B340B
B340B
BOOT2
24 23 4/18 12 26 10 25
11
4.7µF
FIGURE 3. SINGLE 6A OUTPUT (V RANGE FROM 4.5V TO 28V) CURRENT SHARING
IN
FN6676 Rev 8.00
February 17, 2015
Page 5 of 26
ISL85033
Functional Block Diagram
VCC
5MΩ
-
+
BOOT UV
DETECTION
-10%
VIN2
SOFT-START
CONTROL
SS2
-
CSA2
VOLTAGE
MONITOR
-
+
+
EA
COMP2
0.8V
REFERENCE
FAULT
MONITOR
GATE
DRIVE
PHASE2
PGND2
EN2
CSA2
BOOT
REFRESH
CONTROL
+
SLOPE COMP
POWER-ON
RESET
MONITOR
VIN1
LDO
V
= 5V
CC
CSA2
CSA1
VIN1
THERMAL
MONITOR
+150°C
SYNCOUT
FS
OSCILLATOR
SYNCIN
+
SLOPE COMP
VIN1
CSA1
CSA1
EN1
FAULT
MONITOR
0.8V
REFERENCE
DRIVE
GATE
COMP1
+
-
PHASE1
PGND1
+ EA
-
MONITOR
VOLTAGE
CONTROL
SOFT-START
BOOT
REFRESH
CONTROL
SS1
-10%
+
-
VCC
5MΩ
BOOT UV
VCC
DETECTION
FN6676 Rev 8.00
February 17, 2015
Page 6 of 26
ISL85033
Ordering Information
PART NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
(Notes 1, 2, 3)
ISL85033IRTZ
850 33IRTZ
-40 to +85
28 Ld TQFN
L28.4x4
ISL85033-12VEVAL3Z
ISL85033DUALEVAL1Z
ISL85033EVAL2Z
ISL85033CRSHEVAL1Z
NOTES:
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
1. Add “-T*” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85033. For more information on MSL please see techbrief TB363.
FN6676 Rev 8.00
February 17, 2015
Page 7 of 26
ISL85033
Absolute Maximum Ratings
Thermal Information
VIN1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +30V
PHASE1/2 to GND . . . . . . . . . . . . . . . . . . . -7V (<10ns) /-0.3V (DC) to +33V
BOOT1/2 to PHASE1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
FS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
SYNCIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
FB1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V
EN1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
PGOOD1/2 to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
COMP1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
VCC to GND Short Maximum Duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1s
SYNCOUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
SS1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
ESD Rating
Thermal Resistance
QFN Package (Notes 4, 5) . . . . . . . . . . . . . .
(°C/W)
38
(°C/W)
3
JA
JC
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 28V
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . .2.2kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Latch-up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379 for details.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
T
= -40°C to +85°C, V = 4.5V to 28V, unless otherwise noted. Typical values are at T = +25°C.
IN
A
A
Boldface limits apply across the operating temperature range, -40°C to +85°C
MIN
MAX
PARAMETER
SUPPLY VOLTAGE
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
V
V
V
V
Voltage Range
VIN
4.5
4.5
28
2.2
45
V
mA
µA
V
IN
IN
IN
CC
Quiescent Supply Current
Shutdown Supply Current
Voltage
I
1.2
20
Q
I
EN1/2 = 0V
= 12V; I = 0mA
OUT
SD
V
V
5.1
5.6
CC
IN
POWER-ON RESET
VIN POR Threshold
Rising Edge
Falling Edge
3.9
3.7
4.4
V
V
3.2
OSCILLATOR
Nominal Switching Frequency
f
FS pin = VCC
420
500
300
2000
800
580
kHz
kHz
kHz
mV
kHz
kHz
ns
SW
Resistor from FS pin to GND = 383kΩ
Resistor from FS pin to GND = 40.2kΩ
FS = 100kΩ
FS Voltage
V
780
600
820
FS
Switching Frequency
SYNCIN = 600kHz
300
1.2MHz ≤ SYNCIN ≤ 4MHz
2000
Minimum Off-time
t
130
OFF
ERROR AMPLIFIER
Error Amplifier Transconductance Gain
FB1, FB2 Leakage Current
Current Sense Amplifier Gain
Reference Voltage
gm
125
205
10
285
100
0.24
0.808
3.5
µA/V
nA
V
= 0.8V
FB
R
0.18
0.792
1.5
0.21
0.8
2.5
2
V/A
V
T
Soft-start Ramp Time
SS1, SS2 = V
DD
ms
µA
Soft-start Charging Current
ISS
1.4
2.6
FN6676 Rev 8.00
February 17, 2015
Page 8 of 26
ISL85033
Electrical Specifications
T
= -40°C to +85°C, V = 4.5V to 28V, unless otherwise noted. Typical values are at T = +25°C.
IN
A
A
Boldface limits apply across the operating temperature range, -40°C to +85°C (Continued)
MIN
MAX
PARAMETER
POWER-GOOD
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
PG1, PG2 Trip Level PG to PGOOD1,
PGOOD2
Rise
Fall
91
85.5
10
94
%
%
82.5
PG1, PG2 Propagation Delay
PG1, PG2 Low Voltage
Percentage of the soft-start time
ISINK = 3mA
%
100
300
mV
ENABLE INPUT
EN1, EN2 Leakage Current
EN1, EN2 Input Threshold Voltage
EN1/2 = 0V/5V
Low Level
-1
1
µA
V
0.8
1.4
Float Level
High Level
1.0
2
V
V
SYNC INPUT/OUTPUT
SYNCIN Input Threshold
Falling Edge
Rising Edge
Hysteresis
1.1
1.4
1.6
200
10
V
V
1.9
mV
nA
SYNCIN Leakage Current
SYNCIN Pulse Width
SYNCIN = 0V/5V
1000
100
600
ns
SYNCOUT Phase-shift to SYNCIN
Measured from rising edge to rising
edge, if duty cycle is 50%
180
Degree
SYNCOUT Frequency Range
SYNCOUT Output Voltage High
SYNCOUT Output Voltage Low
FAULT PROTECTION
4000
0.3
kHz
V
ISYNCOUT = 3mA
V
- 0.3
V
-0.08
CC
CC
0.08
V
Thermal Shutdown Temperature
T
Rising Threshold
Hysteresis
150
20
°C
°C
A
SD
T
HYS
Overcurrent Protection Threshold
OCP Blanking Time
POWER MOSFET
(Note 7)
4.1
5.1
60
6.1
ns
High-side
R
I
I
= 100mA
= 100mA
75
1
150
300
mΩ
Ω
HDS
PHASE
Internal BOOT1, BOOT2 Refresh Low-side
PHASE Leakage Current
PHASE Rise Time
R
LDS
PHASE
EN1/2 = PHASE1/2 = 0V
= 25V
nA
ns
t
V
10
RISE
IN
NOTES:
6. Test Condition: V = 28V, FB forced above regulation point (0.8V), no switching, and power MOSFET gate charging current not included.
IN
7. Established by both current sense amplifier gain test and current sense amplifier output test at I = 0A.
L
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN6676 Rev 8.00
February 17, 2015
Page 9 of 26
ISL85033
Typical Performance Curves Circuit of Figure 2. V = 12V, V
= 5V, V
OUT2
= 3.3V, I
OUT1
= 3A, I
= 3A,
OUT2
IN
OUT1
T
= -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.
A
A
100
90
80
70
60
50
40
100
90
12V
1MHz
80
70
60
50
40
OUT
9V
OUT
1MHz
5V
OUT
3.3V
OUT
5V
OUT
500kHz
3.3V
500kHz
OUT
1.8V
300kHz
OUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD, T = +25°C, V = 28V
IN
FIGURE 5. EFFICIENCY vs LOAD, T = +25°C, f = 500kHz,
SW
A
A
V
= 12V
IN
4.2
3.5
2.8
2.1
1.4
0.7
0.0
100
90
80
70
60
50
40
9V
IN
12V
IN
28V
IN
12V
IN
28V
IN
9V
IN
0
1
2
3
4
5
6
0
1
2
3
4
5
6
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 6. EFFICIENCY vs LOAD, T = +25°C, CURRENT SHARING
FIGURE 7. POWER DISSIPATION vs LOAD, T = +25°C,
A
A
5V
, f
= 500kHz
CURRENT SHARING 5V
, f
= 500kHz
OUT SW
OUT SW
4.8
4.0
3.2
2.4
1.6
0.8
0.0
5.04
5.03
5.02
5.01
5.00
4.99
4.98
12V
IN
9V
IN
12V
IN
28V
IN
28V
IN
9V
IN
0
1
2
3
4
5
6
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 8. POWER DISSIPATION vs LOAD, T = +85°C,
FIGURE 9. V
OUT
REGULATION vs LOAD, CHANNEL 1,
, f = 500kHz
A
CURRENT SHARING 5V
, f
= 500kHz
T
= +25°C, 5V
OUT SW
A
OUT SW
FN6676 Rev 8.00
February 17, 2015
Page 10 of 26
ISL85033
Typical Performance Curves Circuit of Figure 2. V = 12V, V
= 5V, V
= 3.3V, I
OUT1
= 3A, I = 3A,
OUT2
IN
OUT1
OUT2
T
= -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
A
3.329
3.328
3.326
3.325
3.323
3.322
3.320
5.04
5.03
5.02
5.01
5.00
4.99
4.98
28V
IN
18V
IN
9V
IN
12V
IN
28V
IN
12V
1.0
IN
0
0.5
1.5
2.0
2.5
3.0
0
1
2
3
4
5
6
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 11. V
OUT
REGULATION vs LOAD, CHANNEL 2, T = +25°C,
A
FIGURE 10. V
T
REGULATION vs LOAD, CURRENT SHARING,
OUT
= +25°C, 5V
3.3V
, f
= 500kHz
, f
= 500kHz
OUT SW
A
OUT SW
5.04
5.03
5.02
5.01
5.00
4.99
4.98
5.02
5.01
5.00
4.99
4.98
4.97
4.96
0A
3A
2A
0A
4A
6A
0
5
10
15
20
25
30
0
5
10
15
20
25
30
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 12. OUTPUT VOLTAGE REGULATION vs V , CHANNEL 1,
IN
FIGURE 13. OUTPUT VOLTAGE REGULATION vs V , CURRENT
IN
T
= +25°C, 5V
, f
= 500kHz
SHARING, T = +25°C, 5V = 500kHz
, f
A
OUT SW
A
OUT SW
3.340
3.335
3.330
3.325
3.320
3.315
3.310
LX1 5V/DIV
V
RIPPLE 20mV/DIV
OUT1
0A
3A
2A
IL1 0.1A/DIV
0
5
10
15
20
25
30
INPUT VOLTAGE (V)
FIGURE 14. OUTPUT VOLTAGE REGULATION vs V , CHANNEL 2,
IN
FIGURE 15. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
T
= +25°C, 3.3V = 500kHz
, f
A
OUT SW
FN6676 Rev 8.00
February 17, 2015
Page 11 of 26
ISL85033
Typical Performance Curves Circuit of Figure 2. V = 12V, V
= 5V, V
OUT2
= 3.3V, I
OUT1
= 3A, I
= 3A,
OUT2
IN
OUT1
T
= -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
A
LX1 5V/DIV
LX2 5V/DIV
V
RIPPLE 20mV/DIV
IL1 0.2A/DIV
OUT1
V
RIPPLE 20mV/DIV
OUT2
IL2 0.1A/DIV
FIGURE 16. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
(V = 9V)
FIGURE 17. STEADY STATE OPERATION AT NO LOAD CHANNEL 2
IN
LX1 5V/DIV
LX2 5V/DIV
V
RIPPLE 20mV/DIV
OUT2
V
RIPPLE 20mV/DIV
OUT1
IL1 1A/DIV
IL2 1A/DIV
FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 1
FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 2
LX2 10V/DIV
V
RIPPLE 20mV/DIV
OUT1
V
RIPPLE 20mV/DIV
OUT
LX1 10V/DIV
IL1 2A/DIV
FIGURE 20. STEADY STATE OPERATION WITH FULL LOAD CURRENT
SHARING
FIGURE 21. LOAD TRANSIENT CHANNEL 1
FN6676 Rev 8.00
February 17, 2015
Page 12 of 26
ISL85033
Typical Performance Curves Circuit of Figure 2. V = 12V, V
= 5V, V
OUT2
= 3.3V, I
OUT1
= 3A, I
= 3A,
OUT2
IN
OUT1
T
= -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
A
EN1 5V/DIV
V
2V/DIV
OUT1
V
RIPPLE 20mV/DIV
OUT2
IL1 0.5A/DIV
PG1 5V/DIV
IL2 2A/DIV
FIGURE 22. LOAD TRANSIENT CHANNEL 2
FIGURE 23. SOFT-START WITH NO LOAD CHANNEL 1
EN2 5V/DIV
EN1 5V/DIV
V
2V/DIV
OUT2
V
2V/DIV
OUT1
IL2 0.5A/DIV
PG2 5V/DIV
IL1 2A/DIV
PG1 5V/DIV
FIGURE 24. SOFT-START WITH NO LOAD CHANNEL 2
FIGURE 25. SOFT-START AT FULL LOAD CHANNEL 1
EN2 5V/DIV
EN1 5V/DIV
V
2V/DIV
OUT2
V
1V/DIV
OUT1
IL2 2A/DIV
IL1 0.5A/DIV
PG 5V/DIV
PG2 5V/DIV
FIGURE 26. SOFT-START AT FULL LOAD CHANNEL 2
FIGURE 27. SOFT-DISCHARGE SHUTDOWN CHANNEL 1
FN6676 Rev 8.00
February 17, 2015
Page 13 of 26
ISL85033
Typical Performance Curves Circuit of Figure 2. V = 12V, V
= 5V, V
OUT2
= 3.3V, I
OUT1
= 3A, I
= 3A,
OUT2
IN
OUT1
T
= -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
A
V
V
2V/DIV
2V/DIV
OUT1
OUT2
EN2 5V/DIV
V
0.5V/DIV
OUT2
EN1, 2 2V/DIV
IL2 0.5A/DIV
PG 5V/DIV
FIGURE 28. SOFT-DISCHARGE SHUTDOWN CHANNEL 2
FIGURE 29. INDEPENDENT START-UP SEQUENCING AT NO LOAD
V
V
2V/DIV
2V/DIV
V
2V/DIV
2V/DIV
OUT1
OUT2
OUT1
V
OUT2
EN1, 2 2V/DIV
EN1, 2 2V/DIV
FIGURE 30. RATIOMETRIC START-UP SEQUENCING AT NO LOAD
FIGURE 31. ABSOLUTE START-UP SEQUENCING AT NO LOAD
LX1 10V/DIV
LX1 10V/DIV
V
RIPPLE 20mV/DIV
OUT1
V
RIPPLE 20mV/DIV
OUT2
LX2 10V/DIV
SYNC 5V/DIV
LX2 10V/DIV
SYNC 5V/DIV
FIGURE 32. STEADY STATE OPERATION CHANNEL 1 AT FULL LOAD WITH
SYNC FREQUENCY = 4MHz
FIGURE 33. STEADY STATE OPERATION CHANNEL 2 AT FULL LOAD WITH
SYNC FREQUENCY = 4MHz
FN6676 Rev 8.00
February 17, 2015
Page 14 of 26
ISL85033
Typical Performance Curves Circuit of Figure 2. V = 12V, V
= 5V, V
OUT2
= 3.3V, I
OUT1
= 3A, I
= 3A,
OUT2
IN
OUT1
T
= -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C. (Continued)
A
A
PHASE1 10V/DIV
PHASE1 10V/DIV
V
2V/DIV
OUT1
IL1 2A/DIV
V
2V/DIV
IL1 2A/DIV
PG1 5V/DIV
OUT1
PG1 5V/DIV
FIGURE 34. OUTPUT SHORT CIRCUIT CHANNEL 1
FIGURE 35. OUTPUT SHORT CIRCUIT HICCUP AND RECOVERY FOR
CHANNEL 1
PHASE2 10V/DIV
IL2 2A/DIV
PHASE2 10V/DIV
V
2V/DIV
OUT2
V
2V/DIV
OUT2
IL2 2A/DIV
PG2 5V/DIV
PG2 5V/DIV
FIGURE 36. OUTPUT SHORT CIRCUIT CHANNEL 2
FIGURE 37. OUTPUT SHORT CIRCUIT HICCUP AND RECOVERY FOR
CHANNEL 2
FN6676 Rev 8.00
February 17, 2015
Page 15 of 26
ISL85033
pin. PG is actively held low when EN is low and during the buck
regulator soft-start period. After the soft-start period terminates,
PG becomes high impedance as long as the output voltage
(monitored on the FB pin) is above 90% of the nominal regulation
Detailed Description
The ISL85033 combines a standard buck PWM controller with
integrated switching MOSFETs. The buck controller drives an
internal N-Channel MOSFET and requires an external diode to
deliver load current up to 3A. A Schottky diode is recommended
for improved efficiency and performance over a standard diode.
The standard buck regulator can operate from an unregulated DC
source, such as a battery, with a voltage ranging from +4.5V to
+28V. The converter output can be regulated to as low as 0.8V.
These features make the ISL85033 ideally suited for FPGA,
set-top boxes, LCD panels, DVD drives, and wireless chipset
power applications.
voltage set by FB. When V
drops 10% below the nominal
OUT
regulation voltage, the ISL85033 pulls PG low. Any fault condition
forces PG low until the fault condition is cleared by attempts to
soft-start. There is an internal 5MΩ internal pull-up resistor.
Output Voltage Selection
The regulator output voltage is easily programmed using an
external resistor divider to scale V
relative to the internal
OUT
reference voltage. The scaled voltage is applied to the inverting
input of the error amplifier; refer to Figure 38.
The ISL85033 employs peak current-mode control loop, which
simplifies feedback loop compensation and rejects input voltage
variation. External feedback loop compensation allows flexibility
in output filter component selection. The regulator switches at a
default 500kHz and it can be adjusted from 300kHz to 2MHz
with a resistor from FS to GND. The ISL85033 is synchronizable
from 300kHz to 2MHz.
The output voltage programming resistor, R , depends on the
2
value chosen for the feedback resistor, R , and the desired
3
output voltage, V , of the regulator. Equation 2 describes the
OUT
relationship between V
OUT
and resistor values. R is often
3
chosen to be in the 1kΩ to 10kΩ range.
(EQ. 2)
R
= V
– 0.8 R 0.8
OUT 3
2
Operation Initialization
The power-on reset circuitry and enable inputs prevent false
start-up of the PWM regulator output. Once all input criteria are
met, the controller soft starts the output voltage to the
programmed level.
If the desired output voltage is 0.8V, then R is left unpopulated
3
and R is 0Ω.
2
V
OUT
R
R
2
FB
-
+
Power-on Reset and Undervoltage Lockout
The ISL85033 automatically initializes upon receipt of input
power supply. The power-on reset (POR) function continually
EA
3
0.8V
REFERENCE
monitors V
voltage. While below the POR threshold, the
IN1
controller inhibits switching of the internal power MOSFET. Once
exceeded, the controller initializes the internal soft-start circuitry.
If V
supply drops below their falling POR threshold during
FIGURE 38. EXTERNAL RESISTOR DIVIDER
IN1
soft-start or operation, the buck regulator is disabled until the
input voltage returns.
Output Tracking and Sequencing
Enable and Disable
The output tracking and sequencing between channels can be
implemented by using the SS1 and SS2 pins. Figures 39, 40 and
41 show several configurations for output tracking/sequencing
for a 2.5V and 1.8V application. Independent soft-start for each
channel is shown in Figure 39 and measured in Figure 29. The
When EN1 and EN2 are pulled low, the device enters shutdown
mode and the supply current drops to a typical value of 20µA. All
internal power devices are held in a high impedance state while
in shutdown mode.
output ramp-time for each channel (t ) is set by the soft-start
capacitor (C ) as shown by Equation 3.
SS
SS
The EN pin enables the controller of the ISL85033. When the
voltage on the EN pin exceeds its logic rising threshold, the
controller initiates the 2ms soft-start function for the PWM
regulator. If the voltage on the EN pin drops below the falling
threshold, the buck regulator shuts down.
(EQ. 3)
C
F = 2.5*t s
SS
SS
The maximum C value is recommended not to exceed 100nF.
SS
Ratiometric tracking is achieved in Figure 40 by using the same
value for the soft-start capacitor on each channel; it is measured
in Figure 30.
If EN1 and EN2 pins are driven by an external signal, the
minimum off-time for EN1 and EN2 should be:
EN_T_off s = 10s C
2.2nF
(EQ. 1)
SS
By connecting a feedback network from V
with the same ratio that sets V
OUT2
shown in Figure 41 is implemented. The measurement is shown
in Figure 31. If the output of Channel 1 is shorted to GND, it will
enter overcurrent hiccup mode, SS2 will be pulled low through
to the SS2 pin
voltage, absolute tracking
OUT1
Where C is the soft-start pin capacitor (nF). The ISL85033 does
SS
not have debouncing to the EN1 and EN2 external signals.
Power-good
the added resistor between V
Channel 2 into hiccup as well. If the output of Channel 2 is
and SS2 and this will force
PG is the open-drain output of a window comparator that
continuously monitors the buck regulator output voltage via the FB
OUT1
FN6676 Rev 8.00
February 17, 2015
Page 16 of 26
ISL85033
shorted to GND with V
in regulation, it will enter overcurrent
OUT1
V
V
OUT1
hiccup mode with a very short hiccup waiting time. The reason is
that V is still in regulation and can pull up SS2 very quickly
5.0V
3.3V
SS1
SS2
C
C
OUT1
via the resistor added between V
3
C
47nF
1
and SS2.
OUT1
Figure 42 illustrates output sequencing. When EN1 is high and
EN2 is floating, OUT1 comes up first and OUT2 will not start until
OUT1 > 90% of its regulation point. If EN1 is floating and EN2 is
high, OUT2 comes up first and OUT1 will not start until
ISL85033
OUT2
4
OUT2 > 90% of its regulation point. If EN1 = EN2 = high, OUT1
and OUT2 come up at the same time. Please refer to Table 1 for
conditions related to Figure 42 (Output Sequencing).
TABLE 1. OUTPUT SEQUENCING
R
8.06k
R
1
25.5k
2
EN1
High
EN2
Floating
High
V
V
NOTE
OUT1
OUT2
First
After V
> 90%
OUT1
Floating
High
After V
> 90%
First
OUT2
FIGURE 41. ABSOLUTE START-UP
High
Same time
as V
Same time
as V
OUT2
OUT1
Floating Floating
Not
Allowed
5.0V
3.3V
V
OUT1
OUT2
SS1
C
3
C
22nF
1
V
5.0V
OUT1
OUT2
SS2
EN1
SS1
SS2
ISL85033
C
C
3
4
C
22nF
2
C1
22nF
V
C
EN2
4
ISL85033
C2
47nF
V
3.3V
FIGURE 42. OUTPUT SEQUENCING
Protection Features
FIGURE 39. INDEPENDENT START-UP
The ISL85033 limits the current in all on-chip power devices.
Overcurrent protection limits the current on the two buck
regulators and internal LDO for V
.
CC
V
5.0V
3.3V
OUT1
SS1
Buck Regulator Overcurrent Protection
C
3
4
C
1
During PWM on-time, current through the internal switching
MOSFET is sampled and scaled through an internal pilot device.
The sampled current is compared to a nominal 5A overcurrent
limit. If the sampled current exceeds the overcurrent limit
reference level, an internal overcurrent fault counter is set to 1
and an internal flag is set. The internal power MOSFET is
immediately turned off and will not be turned on again until the
next switching cycle.
22nF
SS2
ISL85033
V
OUT2
C
C
2
22nF
The protection circuitry continues to monitor the current and
turns off the internal MOSFET as described. If the overcurrent
condition persists for 17 sequential clock cycles, the overcurrent
fault counter overflows indicating an overcurrent fault condition
exists. The regulator is shutdown and power-good goes low.
FIGURE 40. RATIOMETRIC START-UP
The buck controller attempts to recover from the overcurrent
condition after waiting 8 soft-start cycles. The internal
overcurrent flag and counter are reset. A normal soft-start cycle
FN6676 Rev 8.00
February 17, 2015
Page 17 of 26
ISL85033
is attempted and normal operation continues if the fault
condition has cleared. If the overcurrent fault counter overflows
during soft-start, the converter shuts down and this hiccup mode
operation repeats.
Synchronization Control
The frequency of operation can be synchronized up to 2MHz by
an external signal applied to the SYNCIN pin. The falling edge on
the SYNCIN triggers the rising edge of PHASE1/2. The switching
frequency for each output is half of the SYNCIN frequency.
Thermal Overload Protection
Thermal overload protection limits maximum junction
temperature in the ISL85033. When the junction temperature
Output Inductor Selection
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% of
total load current. The inductor value can then be calculated
using Equation 5:
(T ) exceeds +150°C, a thermal sensor sends a signal to the fault
monitor.
J
The fault monitor commands the buck regulator to shutdown.
When the junction temperature has decreased by 20°C, the
regulator will attempt a normal soft-start sequence and return to
normal operation. For continuous operation, the +125°C
junction temperature rating should not be exceeded.
V
– V
V
OUT
IN
OUT
(EQ. 5)
------------------------------- ---------------
L =
f
I
V
IN
SW
Increasing the value of inductance reduces the ripple current and
thus ripple voltage. However, the larger inductance value may
reduce the converter’s response time to a load transient. The
inductor current rating should be such that it will not saturate in
overcurrent conditions.
BOOT Undervoltage Protection
If the BOOT capacitor voltage falls below 2.5V, the BOOT
undervoltage protection circuit will pull the phase pin low through
a 1Ω switch for 400ns to recharge the capacitor. This operation
may arise during long periods of no switching as in no load
situations.
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current. The
Output ripple voltage and transient response are 2 critical factors
when considering output capacitance choice. The current mode
control loop allows the usage of low ESR ceramic capacitors and
thus smaller board layout. Electrolytic and polymer capacitors
may also be used.
Application Guidelines
Operating Frequency
The ISL85033 operates at a default switching frequency of
500kHz if FS is tied to V . Tie a resistor from FS to GND to
CC
program the switching frequency from 300kHz to 2MHz, as
shown in Equation 4. [Minimum on-time of 150ns (typical) in
conjunction with the input and output voltage should be
considered when selecting the maximum operating frequency].
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings and with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturers data sheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
(EQ. 4)
k = 122k t – 0.17s
R
FS
Where t is the switching period in µs.
300
200
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
100
0
For the ceramic capacitors (low ESR):
I
------------------------------------
V
=
(EQ. 6)
is the
OUTripple
C
OUT
500
750
1000
1250
(kHz)
1500
1750
2000
8 f
SW
f
SW
Where I is the inductor’s peak-to-peak ripple current, f
SW
FIGURE 43. R SELECTION vs f
FS
SW
switching frequency and C
is the output capacitor.
OUT
If using electrolytic capacitors then:
V
= I*ESR
(EQ. 7)
OUTripple
FN6676 Rev 8.00
February 17, 2015
Page 18 of 26
ISL85033
Regarding transient response needs, a good starting point is to
IRMS
2
(EQ. 10)
-----------
=
D – D
determine the allowable overshoot in V
if the load is suddenly
OUT
I
o
removed. In this case, energy stored in the inductor will be
transferred to C causing its voltage to rise. After calculating
Where D = V /V
IN
O
OUT
capacitance required for both ripple and transient needs, choose
the larger of the calculated values. Equation 8 determines the
required output capacitor value in order to achieve a desired
overshoot relative to the regulated voltage.
The input ripple current is graphically represented in Figure 45.
0.6
0.5
0.4
2
I
L
*
OUT
--------------------------------------------------------------------------------------------
=
C
(EQ. 8)
OUT
2
2
V
V
V
– 1
*
OUT
OUTMAX
OUT
Where V is the relative maximum overshoot
allowed during the removal of the load. For an overshoot of 5%,
the equation becomes Equation 9:
/V
OUTMAX OUT
0.3
0.2
0.1
0
2
I
L
*
OUT
-----------------------------------------------------
=
C
(EQ. 9)
OUT
2
2
V
1.05 – 1
*
OUT
Figure 44 shows the relationship of C
OUT
and % overshoot at three
0
0.2
0.4
0.6
0.8
different output voltages. L is assumed to be 7µH and I
is 3A.
OUT
DUTY CYCLE (D)
FIGURE 45. I
/I vs DUTY CYCLE
O
RMS
A minimum of 10µF ceramic capacitance is required on each VIN
pin. The capacitors must be as close to the IC as physically
possible. Additional capacitance may be used.
80
60
3.3V
OUT
Loop Compensation Design
The ISL85033 uses a constant frequency current mode control
architecture to achieve simplified loop compensation and fast
loop transient response.
40
5V
OUT
20
0
12V
OUT
The compensator schematic is shown in Figure 47. As mentioned
in the C
selection, ISL85033 allows the usage of low ESR
OUT
1.02
1.04
1.06
/V
1.08
1.10
output capacitor. Choice of the loop bandwidth f is somewhat
c
arbitrary but should not exceed 1/4 of the switching frequency.
As a starting point, the lower of 100kHz or 1/6 of the switching
frequency is reasonable. The following equations determine
initial component values for the compensation, allowing the
designer to make the selection with minimal effort. Further detail
is provided in “Theory of Compensation” on page 20 to allow fine
tuning of the compensator.
V
OUTMAX OUT
FIGURE 44. C
vs OVERSHOOT V
/V
OUT
OUTMAX OUT
Current Sharing Configuration
In current sharing configuration, FB1 is connected to FB2, EN1 to
EN2, COMP1 to COMP2 and V
to V as shown in Figure 3
OUT1
OUT2
on page 5. As a result, the equivalent g doubles its single
m
Compensation resistor R is given by Equation 11:
1
channel value. Since the two channels are out-of-phase, the
frequency will be 2x the channel switching frequency. Ripple
current cancellation will reduce the ripple current seen by the
output capacitors and thus lower the ripple voltage. This results
in the ability to use less capacitance than would be required by a
single phase design of similar rating. Ripple current cancellation
also reduces the ripple current seen at the input capacitors.
2f V C R
o o T
c
(EQ. 11)
-----------------------------------
=
R
1
g
V
FB
m
Which, when applied to the ISL85033 becomes:
V C
o o
(EQ. 12)
R k= 0.008247 f
1
c
Where C is the output capacitor value [µF], f = loop bandwidth
o
c
Input Capacitor Selection
[kHz] and V is the output voltage [V].
o
To reduce the resulting input voltage ripple and to minimize EMI
by forcing the very high frequency switching current into a tight
local loop, an input capacitor is required. The input capacitor
must have adequate ripple current rating, which can be
approximated by Equation 10. If capacitors other than MLCC are
used, attention must be paid to ripple and surge current ratings.
Compensation capacitors C [nF], C [pF] are given by
Equation 13:
1
2
3
6
C
V 10
C
R 10
(EQ. 13)
o
o
o
c
-----------------------------------------
-----------------------------------------
C
=
,C =
1
2
I
R
R
1
o
1
Where I [A] is the output load current, R (Ω) and R (Ω) is the
o
1
C
ESR of the output capacitor C .
o
FN6676 Rev 8.00
February 17, 2015
Page 19 of 26
ISL85033
Example: V = 5V, I = 3A, f
= 500kHz, f = 50kHz,
c
Power Stage Transfer Functions
o
o
SW
C = 47µF/R = 5mΩ, then the compensation resistance
o
c
Transfer function F (S) from control to output voltage is
1
R = 96kΩ.
1
calculated in Equation 17:
The compensation capacitors are:
S
-----------
1 +
ˆ
v
esr
(EQ. 17)
o
C = 815pF, C = 2.5pF (There is approximately 3pF parasitic
------
ˆ
--------------------------------------
F S =
= V
IN
1
2
1
2
d
S
S
capacitance from V
to GND; therefore, C is optional).
COMP
2
------ --------------
+
+ 1
2
o
Q
o
p
Theory of Compensation
C
1
1
o
--------------
------
--------------
Where
=
,Q R
=
The sensed current signal is injected into the voltage loop to
achieve current mode control to simplify the loop compensation
design. The inductor is not considered as a state variable for
current mode control and the system becomes a single order
system. It is much easier to design a compensator to stabilize the
voltage loop than voltage mode control. Figure 46 shows the
small signal model of the synchronous buck regulator.
esr
p
o
o
R C
L
LC
o
c
o
Transfer function F (S) from control to inductor current is given
2
by Equation 18:
S
------
1 +
ˆ
V
I
o
IN
z
----
ˆ
-------------------- --------------------------------------
F S =
=
(EQ. 18)
2
2
R
+ R
L
d
o
S
S
------ --------------
+
+ 1
2
o
Q
^
^
^
L
o
p
i
i
L
IN
V
O
1
^
d
--------------
=
V
Where
z
IN
^
^
R C
1:D
I d
V
o
o
L
IN
Rc
Ro
+
R
Current loop gain T (S) is expressed as Equation 19:
i
T
(EQ. 19)
T S = R F F SH S
Co
i
T
m
2
e
T (S)
The voltage loop gain with open current loop is calculated in
Equation 20:
i
^
d
K
Fm
(EQ. 20)
T S = KF F SA S
v
m
1
v
The voltage loop gain with current loop closed is given by
Equation 21:
T (S)
v
+
He(S)
^
V
COMP
T S
(EQ. 21)
-Av(S)
v
-----------------------
L S =
v
1 + T S
i
FIGURE 46. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
V
FB
----------
K =
, V
FB
Where
V
is the feedback voltage of the voltage
o
error amplifier. If T (S)>>1, then Equation 21 can be simplified as
shown in Equation 22:
PWM Comparator Gain F
i
m
The PWM comparator gain F for peak current mode control is
m
S
given by Equation 14:
-----------
1 +
V
R
+ R
A S
esr v
1
FB
o
L
ˆ
(EQ. 22)
-------------------------------------------------------------------
--------------
d
1
L S=
,
p
v
-------------------
-------------------------------
(EQ. 14)
F
=
=
V
R
S
H S
R C
o o
m
ˆ
o
T
e
------
S + S T
s
1 +
v
e
n
COMP
p
Where S is the slew rate of the slope compensation and S is
given by Equation 15.
e
n
Equation 22 shows that the system is a single order system,
which has a single pole located at P before the half switching
frequency. Therefore, a simple type II compensator can be easily
used to stabilize the system.
V
– V
o
L
IN
(EQ. 15)
----------------------
= R
T
S
n
Where R is transresistance and is the product of the current
T
sensing resistance and gain of the current amplifier in current
loop.
CURRENT SAMPLING TRANSFER FUNCTION H (S)
e
In current loop, the current signal is sampled every switching
cycle. Equation 16 shows the transfer function:
2
S
S
(EQ. 16)
------ --------------
+
H S=
+ 1
e
2
n
Q
n
n
2
--
Where Q and are given by Q = – = = f .
n
n
n
n
S
FN6676 Rev 8.00
February 17, 2015
Page 20 of 26
ISL85033
Put the compensator zero at 6.6kHz (~1.5x C R ), and put the
o o
Vo
compensator pole at ESR zero, which is 1.45MHz. The
compensator capacitors are:
R
2
C
3
C = 470pF, C = 3pF (There is approximately 3pF parasitic
1
2
V
FB
-
capacitance from V
to GND; therefore, C is optional).
V
COMP
2
COMP
GM
V
Figure 48A shows the simulated voltage loop gain. It is shown
that it has 80kHz loop bandwidth with 69° phase margin and
15dB gain margin. Optional addition phase boost can be added
REF
R
3
+
R
1
1
C
2
to the overall loop response by using C .
3
C
60
45
30
FIGURE 47. TYPE II COMPENSATOR
GAIN (dB)
Figure 47 shows the type II compensator and its transfer function
is expressed as Equation 23:
15
0
S
S
------------
------------
1 +
1 +
ˆ
g
v
COMP
m
cz1
cz2
(EQ. 23)
------------------- -------------------- ---------------------------------------------------------
A S=
=
-15
-30
v
ˆ
C
+ C
S
v
1
2
FB
---------
S 1 +
cp
3
4
5
6
100
1•10
1•10
1•10
1•10
Where:
FIGURE 48A.
C
+ C
2
1
1
1
(EQ. 24)
--------------
--------------
----------------------
=
=
,
=
cp
cz1
cz2
R C
R C
R C C
1 1 2
1
1
2
3
100
80
60
40
20
0
The compensator design goal is:
High DC gain
1
1
-- ------
to
f
Loop bandwidth f :
c
SW
4
10
PHASE (°)
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is shown in Equation 25:
1
(EQ. 25)
--------------
= 1to3
Put compensator zero
cz1
R C
o
0
-20
100
3
4
5
6
1•10
1•10
1•10
1•10
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower.
FIGURE 48B.
Rectifier Selection
The loop gain T (S) at crossover frequency of f has unity gain.
v
c
Current circulates from ground to the junction of the external
Schottky diode and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is negative
with respect to ground. This voltage is approximately -0.5V (a
Schottky diode drop) during the off-time. The rectifier's rated
reverse breakdown voltage must be at least equal to the
maximum input voltage, preferably with a 20% derating factor.
The power dissipation when the Schottky diode conducts is
expressed in Equation 28:
Therefore, the compensator resistance R is determined by
Equation 26:
1
2f V C R
o o T
c
(EQ. 26)
-----------------------------------
=
R
1
g
V
FB
m
Where g is the transconductance of the voltage error amplifier,
m
typically 200µA/V. Compensator capacitor C is then given by
1
Equation 27:
1
1
V
(EQ. 27)
-----------------
------------------------
C
=
,C =
OUT
(EQ. 28)
1
2
---------------
R
2R f
P
W = I
V 1 –
1
cz
1 esr
D
OUT
D
V
IN
Example: V = 12V, V = 5V, I = 3A, f
= 500kHz,
C = 22µF (derated value over voltage, temperature)/5mΩ,
IN SW
o
o
Where:
o
5
The V is the voltage drop of the Schottky diode. Selection of the
D
Schottky diode is critical in terms of the high temperature
reverse bias leakage current, which is very dependent on V and
exponentially increasing with temperature. Due to the nature of
L = 5.6µH, g = 200µs, R = 0.21, V = 0.8V, S = 1.110 V/s,
m
T
FB
e
5
S = 3.410 V/s, f = 80kHz, then compensator resistance
n
c
R = 72kΩ.
IN
1
FN6676 Rev 8.00
February 17, 2015
Page 21 of 26
ISL85033
reverse bias leakage vs temperature, the diode should be
carefully selected to operate in the worst case circuit conditions.
Catastrophic failure is possible if the diode chosen experiences
thermal runaway at elevated temperatures. Refer to Application
Notes for AN1574, AN1605, AN1584 diode selection listed on
page 1.
Layout Considerations
Layout is very important in high frequency switching converter
designs. With power devices switching efficiently between
100kHz and 600kHz, the resulting current transitions from one
device to another cause voltage spikes across the
interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, radiate noise into
the circuit, and lead to device overvoltage stress. Careful
component layout and printed circuit board design minimizes
these voltage spikes.
Power Derating Characteristics
To prevent the ISL85033 from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 29:
As an example, consider the turn-off transition of the upper
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET and
is picked up by the Schottky diode. Any parasitic inductance in
the switched current path generates a large voltage spike during
the switching interval. Careful component selection, tight layout
of the critical components and short, wide traces minimizes the
magnitude of voltage spikes.
(EQ. 29)
T
= PD
JA
RISE
Where PD is the power dissipated by the regulator and θ is the
JA
thermal resistance from the junction of the die to the ambient
temperature. The junction temperature, T , is given by
Equation 30:
J
(EQ. 30)
T = T + T
RISE
J
A
There are two sets of critical components in the ISL85033
switching converter. The switching components are the most
critical because they switch large amounts of energy and
therefore tend to generate large amounts of noise. Next are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
Where T is the ambient temperature. For the QFN package, the
A
θ
is +38°C/W.
JA
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C When considering
the thermal design, (consider the thermal needs of the rectifier
diode).
A multilayer printed circuit board is recommended. Figure 50
shows the connections of the critical components in the
The ISL85033 delivers full current at ambient temperatures up
to +85°C if the thermal impedance from the thermal pad
maintains the junction temperature below the thermal shutdown
level, depending on the Input Voltage/Output Voltage
combination and the switching frequency. The device power
dissipation must be reduced to maintain the junction
temperature at or below the thermal shutdown level. Figure 49
illustrates the power derating versus ambient temperature for
the ISL85033 evaluation kit. Note that the evaluation kit derating
curve is based on total circuit dissipation, not IC dissipation
alone.
converter. Note that capacitors C and C
could each
IN OUT
represent numerous physical capacitors. Dedicate one solid
layer, (usually a middle layer of the PC board) for a ground plane
and make all critical component ground connections with vias to
this layer. Dedicate another solid layer as a power plane and
break this plane into smaller islands of common voltage levels.
Keep the metal runs from the PHASE terminals to the output
inductor short. The power plane should support the input power
and output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the phase nodes. Use the remaining
printed circuit layers for small signal wiring.
120
110
100
90
In order to dissipate heat generated by the internal LDO and
MOSFET, the ground pad should be connected to the internal
ground plane through at least four vias. This allows the heat to
move away from the IC and also ties the pad to the ground plane
through a low impedance path.
80
70
60
50
40
30
20
10
0
= +38°C/W
JA
The switching components should be placed close to the
ISL85033 first. Minimize the length of the connections between
the input capacitors, C , and the power switches by placing
IN
them nearby. Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible. Position the
output inductor and output capacitors between the upper and
Schottky diode and the load.
0
1
2
3
4
5
6
7
8
9
10 11 12
ISL85033EVAL1ZB EVALUATION BOARD
TOTAL POWER DISSIPATION (W)
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB pin with
vias tied straight to the ground plane as required.
FIGURE 49. POWER DERATING CURVE
FN6676 Rev 8.00
February 17, 2015
Page 22 of 26
ISL85033
Fb1
Fb2
ISL85033
L1
L2
LX1 trace
LX2 trace
. . .
vias
D1
D2
Cin1 Cin2
VOUT2
Cout1
Cout2
VOUT1
FIGURE 50. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
FN6676 Rev 8.00
February 17, 2015
Page 23 of 26
ISL85033
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
February 17, 2015
FN6676.8 Page 21, paragraph below Equation 27, changed “Co = 220µF/5mΩ...” to "Co = 22µF (derated value over voltage,
temperature)/5mΩ...
April 17, 2014
FN6676.7 On page 16 in the "Output Tracking and Sequencing" changed the sentence "Maximum CSS value is 50nF" to "The
maximum CSS value is recommended not to exceed 100nF".
Figure 39 on page 17, changed C1 from 0.1µF to 22nF and C2 from 0.2µF to 47nF.
Figure 40 on page 17, changed the value of both C1 and C2 to 22nF each.
Figure 41 on page 17, changed C1 value to 47nF.
Figure 42 on page 17, changed C1 and C2 value to 22nF each.
On page 18 in the Operating Frequency chapter, after the sentence "Tie a resistor from FS to GND to program the
switching frequency from 300kHz to 2MHz, as shown in Equation 4." Added : "Minimum on-time of 150ns (typical)
in conjunction with input and output voltage should be considered when selecting the maximum operating
frequency".
November 2, 2011
FN6676.6 In the “Pin Descriptions” on page 3, added the following to end of EN1, EN2 description:
"If EN1, EN2 pins are driven by an external signal, the minimum off-time for EN1, EN2 should be:
EN_T_off s = 10s C
2.2nF
SS
where CSS is the soft-start pin capacitor (nF). ISL85033 does not have debouncing to EN1, EN2 external signals."
In “Enable and Disable” on page 16, adding the following:
"If EN1, EN2 pins are driven by an external signal, the minimum off-time for EN1, EN2 should be:
EN_T_off s = 10s C
2.2nF
SS
where CSS is the soft-start pin capacitor (nF). ISL85033 does not have debouncing to EN1, EN2 external signals."
Adding the following after Equation 3 on page 16:
"Maximum Css value is 50nF".
In the “Pin Descriptions” on page 3, added the following to the end of SS1, SS2 description:
"Maximum Css value is 50nF".
October 7, 2011
FN6676.5 In “Absolute Maximum Ratings” on page 8, changed:
PHASE1/2 to GND . . . . .-0.3V to +33V
to:
PHASE1/2 to GND . . . . .-7V (<10ns) /-0.3V (DC) to +33V
September 14, 2011 FN6676.4 In the “Pin Descriptions” on page 4, for “SYNCIN”, replaced “Set the internal switching frequency 20% lower than
the external SYNC frequency applied to the SYNCIN pin" with "External SYNC frequency applied to the SYNCIN pin
should be at least 2.4 times the internal switching frequency setting"
August 9, 2011
April 5, 2011
On page 8, changed parameter name from “Syncronization Frequency” to “Switching Frequency”.
FN6676.3 Converted to new template
Updated Intersil Trademark statement at bottom of page 1 per directive from Legal.
Page 2 in the pin table definition, please add the following sentence to the Pin 11 (VCC) description after “Output
of the internal 5V linear regulator. Decouple to PGND with a minimum of 4.7μF ceramic capacitor.”
“This pin is provided only for internal bias of ISL85033 (not to be loaded with current over 10mA).”
Page 8 all Absolute Max Ratings that are “5.5” should be changed to “5.9”
October 15, 2010
FN6676.2 Added the following sentence to the “SYNCIN” description in the “Pin Descriptions” table on page 4:
“Set the internal switching frequency 20% lower than the external SYNC frequency applied to the SYNCIN pin.”
Added the following sentence to “Synchronization Control” on page 18: “The switching frequency for each output
is half of the SYNCIN frequency.”
Revised tape and reel note in “Ordering Information” on page 7 from:
“Add “-T” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications”
to:
“Add “-T*” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications”
This is in order to delineate all tape and reel options.
FN6676 Rev 8.00
February 17, 2015
Page 24 of 26
ISL85033
Revision History(Continued)
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev. (Continued)
DATE
REVISION
CHANGE
September 14, 2010
Corrected Eq. 2 on page 16 from:
R x0.8V
2
----------------------------------
=
R
3
V
– 0.8V
OUT
to:
R
= V
– 0.8 R 0.8
2
OUT
3
Revised preceding paragraph from:
“The output voltage programming resistor, R , depends on the value chosen for the feedback resistor, R , and the
3
2
desired output voltage, V , of the regulator. Equation 2 describes the relationship between V
and resistor
OUT OUT
values. R is often chosen to be in the 1kΩ to 10kΩ range.”
2
to:
“The output voltage programming resistor, R , depends on the value chosen for the feedback resistor, R , and the
2
3
desired output voltage, V , of the regulator. Equation 2 describes the relationship between V
and resistor
OUT OUT
values. R is often chosen to be in the 1kΩ to 10kΩ range.”
3
July 21, 2010
July 18, 2010
FN6676.1 Changed MIN/MAX for “Soft-start Charging Current” on page 8 from 1.5/2.5µA to 1.4/2.6µA
FN6676.0 Initial Release.
About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
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Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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FN6676 Rev 8.00
February 17, 2015
Page 25 of 26
ISL85033
Package Outline Drawing
L28.4x4
28 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/06
A
4 . 00
2 . 50
B
PIN 1
PIN #1 INDEX AREA
CHAMFER 0 . 400 X 45°
0 . 40
INDEX AREA
22
28
21
1
0 . 40
15
7
0 . 10
2X
14
8
0 . 20 ±0 . 05
0 . 10 M
C
A B
0 . 4 x 6 = 2 . 40 REF
3 . 20
TOP VIEW
BOTTOM VIEW
SEE DETAIL X''
0 . 10 C
C
(3 . 20)
PACKAGE BOUNDARY
MAX. 0 . 80
SEATING PLANE
0 . 08 C
(28X 0 . 20)
0 . 00 - 0 . 05
0 . 20 REF
SIDE VIEW
(0 . 40)
0 . 20 REF
C
5
(0 . 40)
0 ~ 0 . 05
(28X 0 . 60)
(2 . 50)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) for reference only.
2. Unless otherwise specified, tolerance : Decimal ±0.05
Angular ±2°
3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994
4. Bottom side Pin#1 ID is diepad chamfer as shown.
5. Tiebar shown (if present) is a non-functional feature.
.
FN6676 Rev 8.00
February 17, 2015
Page 26 of 26
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