ISL85403 [RENESAS]
2.5A Regulator with Integrated High-side MOSFET for Synchronous Buck or Boost Buck Converter;
| 型号： | ISL85403 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 2.5A Regulator with Integrated High-side MOSFET for Synchronous Buck or Boost Buck Converter |
| 文件： | 总24页 (文件大小：1405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL85403
FN8631
Rev 1.00
March 13, 2015
2.5A Regulator with Integrated High-side MOSFET for Synchronous Buck or
Boost Buck Converter
The ISL85403 is a 40V, 2.5A synchronous buck or boost buck
Features
controller with a high-side MOSFET and low-side driver
• Buck mode: input voltage range 3V to 40V (refer to “Input
Voltage” on page 15 for more details)
integrated. In buck mode, the ISL85403 supports a wide input
range of 3V to 40V. In boost-buck mode, the input range can
be extended down to 2.5V and output regulation can be
maintained when V drops below V , enabling sensitive
• Boost mode expands operating input voltage lower than
2.5V (refer to “Input Voltage” on page 15 for more details)
IN
OUT
electronics to remain on in low input voltage conditions.
• Selectable forced PWM mode or PFM mode
The ISL85403 has a flexible selection of operation modes of
forced PWM mode and PFM mode. In PFM mode, the
quiescent input current is as low as 180µA (AUXVCC connected
• 300µA IC quiescent current (PFM, no load); 180µA input
quiescent current (PFM, no load, V
tied to AUXVCC)
OUT
• Less than 5µA (MAX) shutdown input current (IC disabled)
to V
). The load boundary between PFM and PWM can be
OUT
programmed to cover wide applications.
• Operational topologies
- Synchronous buck
The low-side driver can be either used to drive an external low-side
MOSFET for a synchronous buck or left unused for a standard
non-synchronous buck. The low-side driver can also be used to
drive a boost converter as a preregulator followed by a buck
controlled by the same IC, which greatly expands the operating
input voltage range down to 2.5V or lower (Refer to “Typical
Application Schematic III - Boost Buck Converter” on page 6).
- Non-synchronous buck
- Two-stage boost buck
- Non-inverting single inductor buck boost
• Programmable frequency from 200kHz to 2.2MHz and
frequency synchronization capability
• ±1% tight voltage regulation accuracy
The ISL85403 offers the most robust current protections. It uses
peak current mode control with cycle-by-cycle current limiting.
It is implemented with frequency foldback under current limit
condition; also, the hiccup overcurrent mode is also
implemented to guarantee reliable operations under harsh
short conditions.
• Reliable overcurrent protection
- Temperature compensated current sense
- Cycle-by-cycle current limiting with frequency foldback
- Hiccup mode for worst case short condition
• 20 Ld 4x4 QFN package
• Pb-free (RoHS compliant)
The ISL85403 has comprehensive protections against various
faults including overvoltage and over-temperature protections,
etc.
Applications
• General purpose
• 24V bus power
Related Literature
• AN1960, “ISL85403DEMO1Z Demonstration Board User
Guide”
• Battery power
• UG010, “ISL85403EVAL2Z Evaluation Board User Guide”
•
Point-of-load
• Embedded processor and I/O supplies
100
95
90
85
80
75
70
65
60
55
50
6V V
IN
PGOOD
EN
V
IN
VIN
MODE
SYNC
AUXVCC
12V V
IN
BOOT
36V V
ISL85403
IN
VCC
ILIMIT
SS
V
OUT
24V V
PHASE
LGATE
IN
PGND
FB
EXT_BOOST
FS
SGND
COMP
0.1m
1m
10m
100m
1.0
2.5
LOAD CURRENT (A)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
5V, T = +25°C
V
OUT
A
FN8631 Rev 1.00
March 13, 2015
Page 1 of 24
ISL85403
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Application Schematic I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application Schematic II - VCC Switchover to V
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application Schematic III - Boost Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PFM Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Synchronous and Non-Synchronous Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AUXVCC Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2-Stage Boost Buck Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Oscillator and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Component Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Capacitors - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Capacitors - Buck. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Inductor - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low-side Power MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Voltage Feedback Resistor Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Boost Inductor (2-Stage Boost Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Boost Output Capacitor (2-Stage Boost Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Loop Compensation Design - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PWM Comparator Gain Fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Current Sampling Transfer Function He(S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Stage Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Loop Compensation Design for 2-Stage Boost Buck and Single-stage Buck Boost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Layout Suggestions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FN8631 Rev 1.00
March 13, 2015
Page 2 of 24
ISL85403
Pin Configuration
ISL85403
(20 LD QFN)
TOP VIEW
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
EN
FS
SS
BOOT
PGND
PAD
LGATE
SYNC
FB
EXT_BOOST
COMP
6
7
8
9
10
Functional Pin Descriptions
PIN NAME PIN #
DESCRIPTION
EN
FS
SS
FB
1
2
3
4
The controller is enabled when this pin is left floating or pulled HIGH. The IC is disabled when this pin is pulled LOW.
Range: 0V to 5.5V.
Connecting this pin to VCC, or GND, or leaving it open will force the IC to have 500kHz switching frequency. The oscillator switching
frequency can also be programmed by adjusting the resistor from this pin to GND.
Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start interval of
the converter. Also, this pin can be used to track a ramp on this pin.
This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from V
OUT
to FB, the output voltage can be set to any voltage between the power rail (reduced by maximum duty cycle and voltage drop) and
the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin is also monitored
for overvoltage events.
COMP
ILIMIT
5
6
Output of the voltage feedback error amplifier.
Programmable current limit pin. With this pin connected to the VCC pin, or to GND, or left open, the current limiting threshold is set
to default of 3.6A; the current limiting threshold can be programmed with a resistor from this pin to GND.
MODE
7
8
Mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to VCC will enable PFM mode when
the peak inductor current is below the default threshold of 700mA. The current boundary threshold between PFM and PWM can
also be programmed with a resistor at this pin to ground. Check for more details in the “PFM Mode Operation” on page 14.
PGOOD
PHASE
PGOOD is an open-drain output and pull-up pin with a resistor to VCC for proper function. PGOOD will be pulled low under the events
when the output is out of regulation (OV or UV) or EN pin is pulled low. PGOOD rising has a fixed 128 cycles delay.
9, 10 These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected to the source of the
high-side N-channel MOSFET.
EXT_BOOST 11 This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After VCC POR, the
controller will detect the voltage on this pin; if voltage on this pin is below 200mV, the controller is set in
synchronous/non-synchronous buck mode and will latch in this state unless VCC is below POR falling threshold; if the voltage on
this pin after VCC POR is above 200mV, the controller is set in boost mode and latch in this state. In boost mode, the low-side driver
output PWM with same duty cycle with upper-side driver to drive the boost switch.
In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high threshold
and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost converter is
disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled.
In boost mode operation, PFM is disabled when boost PWM is enabled. Check the “2-Stage Boost Buck Converter Operation” on
page 16 for more details.
FN8631 Rev 1.00
March 13, 2015
Page 3 of 24
ISL85403
Functional Pin Descriptions (Continued)
PIN NAME PIN #
DESCRIPTION
SYNC
12 This pin can be used to synchronize two or more ISL85403 controllers. Multiple ISL85403s can be synchronized with their SYNC
pins connected together. 180° phase shift is automatically generated between the master and slave ICs.
The internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with frequency
10% higher than the IC’s local frequency, and pulse width higher than 150ns). Range: 0V to 5.5V.
This pin should be left floating if not used.
LGATE
13 In synchronous buck mode, this pin is used to drive the lower side MOSFET to improve efficiency. A 5.1k or smaller value resistor
has to be added to connect LGATE to ground to avoid falsely turn-on of LGATE caused by coupling noise.
In non-synchronous buck when a diode is used as the bottom side power device, this pin should be connected to VCC through a
resistor (less than 5k) before IC start-up to have the low-side driver (LGATE) disabled.
In boost mode, it can be used to drive the boost power MOSFET. The boost control PWM is same with the buck control PWM.
PGND
BOOT
14 This pin is used as the ground connection of the power flow including driver. Connect it to large ground plane.
15 This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the
internal N-channel MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed. A 1µF
ceramic capacitor is recommended to be used between BOOT and PHASE pin.
VIN
16, 17 Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET as well as the source for the
internal linear regulator that provides the bias of the IC. Range: 3V to 40V.
With the part switching, the operating input voltage applied to the VIN pins must be under 40V. This recommendation allows for
short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding “Absolute Maximum Ratings”
on page 7.
SGND
VCC
18 This pin provides the return path for the control and monitor portions of the IC. Connect it to a quiet ground plane.
19 This pin is the output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum 4.7µF
decoupling ceramic capacitor is recommended between VCC to ground.
AUXVCC
20 This pin is the input of the auxiliary internal linear regulator, which can be supplied by the regulator output after power-up. With
such configuration, the power dissipation inside of the IC is reduced. The input range for this LDO is 3V to 20V.
In boost mode operation, this pin works as boost output overvoltage detection pin. It detects the boost output through a resistor
divider. When voltage on this pin is above 0.8V, the boost PWM is disabled; and when voltage on this pin is below 0.8V minus the
hysteresis, the boost PWM is enabled.
Range: 0V to 20V.
PAD
-
Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to PCB ground copper
plane with area as large as possible to effectively reduce the thermal impedance.
Ordering Information
PART NUMBER
PART
TEMP.
PACKAGE
(Notes 1, 2, 3)
MARKING
RANGE (°C)
(RoHS Compliant)
PKG. DWG. #
L20.4x4C
ISL85403FRZ
85 403FRZ
-40 to +105
20 Ld 4x4 QFN
ISL85403DEMO1Z
ISL85403EVAL2Z
NOTES:
Compact size demo board for SYNC buck
Evaluation Board for non-inverting buck-boost configuration
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL85403. For more information on MSL please see techbrief TB363.
FN8631 Rev 1.00
March 13, 2015
Page 4 of 24
Block Diagram
VCC
AUXVCC
PGOOD
VIN (x2)
VIN
CURRENT
MONITOR
AUXILARY LDO
BIAS LDO
ILIMIT
BOOT
POWER-ON
RESET
SGND
VCC
OCP, OVP, OTP
PFM LOGIC
BOOST MODE CONTROL
EN
EXT_BOOST
MODE
PFM/FPWM
PHASE (x2)
LGATE
GATE DRIVE
VOLTAGE
MONITOR
SYNC
FS
SLOPE
COMPENSATION
OSCILLATOR
+
+
BOOT REFRESH
0.8V
REFERENCE
SOFT-START
LOGIC
VCC
5 µA
COMPARATOR
EA
SS
FB
COMP
PGND
ISL85403
Typical Application Schematic I
PGOOD
PGOOD
EN
MODE
SYNC
AUXVCC
EN
V
IN
V
IN
VIN
VIN
BOOT
MODE
SYNC
AUXVCC
BOOT
VCC
ILIMIT
SS
V
VCC
ILIMIT
SS
V
OUT
OUT
ISL85403
ISL85403
PHASE
LGATE
PHASE
LGATE
PGND
PGND
FB
EXT_BOOST
FS
SGND
EXT_BOOST
FS
SGND
FB
COMP
COMP
(b) NON-SYNCHRONOUS BUCK
(a) SYNCHRONOUS BUCK
Typical Application Schematic II - VCC Switchover to V
OUT
PGOOD
EN
MODE
SYNC
AUXVCC
PGOOD
EN
MODE
SYNC
AUXVCC
V
IN
V
IN
VIN
BOOT
VIN
BOOT
VCC
ILIMIT
SS
V
OUT
VCC
ILIMIT
SS
V
OUT
ISL85403
ISL85403
PHASE
PHASE
LGATE
LGATE
PGND
PGND
FB
EXT_BOOST
FS
SGND
EXT_BOOST
FS
SGND
FB
COMP
COMP
(a) SYNCHRONOUS BUCK
(b) NON-SYNCHRONOUS BUCK
Typical Application Schematic III - Boost Buck Converter
Battery
+
+
R1
R2
1M
130k
VCC
PGOOD
EN
EXT_BOOST
AUXVCC
VIN
PGOOD
EN
MODE
EXT_BOOST
LGATE
R3
R4
V
IN
SYNC
VCC
AUXVCC
VIN
SYNC
BOOT
V
OUT
ISL85403
VCC
PHASE
ILIMIT
SS
ISL85403
BOOT
ILIMIT
SS
V
OUT
PHASE
PGND
LGATE
FB
FS
FS
PGND
FB
SGND
COMP
SGND
COMP
(a) 2-STAGE BOOST BUCK
(b) NON-INVERTING SINGLE INDUCTOR BUCK BOOST
FN8631 Rev 1.00
March 13, 2015
Page 6 of 24
ISL85403
Absolute Maximum Ratings
Thermal Information
VIN, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +44V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.0V
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +22V
Thermal Resistance
QFN 4x4 Package (Notes 4, 5). . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
JA (°C/W) JC (°C/W)
40 3.5
Absolute Boot Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0V
BOOT
Upper Driver Supply Voltage, V
- V
. . . . . . . . . . . . . . . . . . . +6.0V
BOOT PHASE
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 1kV
Latch-up Rating (Tested per JESD78B; Class II, Level A) . . . . . . . . . 100mA
Recommended Operating Conditions
Supply Voltage on V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V
IN
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Refer to “Block Diagram” on page 5 and “Typical Application Schematics” on page 6. Operating Conditions
Unless Otherwise Noted: V = 12V, or V = 4.5V ±10%, T = -40°C to +105°C. Typicals are at T = +25°C. Boldface limits apply across the operating
IN
CC
A
A
temperature range, -40°C to +105°C.
MIN
MAX
PARAMETER
VIN PIN SUPPLY
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6) UNITS
VIN Pin Voltage Range
VIN Pin
3.05
3.05
40
V
V
VIN Pin connected to VCC
5.5
Operating Supply Current
I
MODE = VCC/FLOATING (PFM), no load at the
output
300
1.3
2.8
µA
Q
MODE = GND (forced PWM), V = 12V,
IN
IC operating, not including driving current
mA
µA
Shutdown Supply Current
I
EN connected to GND, V = 12V
IN
4.5
IN_SD
INTERNAL MAIN LINEAR REGULATOR
MAIN LDO V Voltage
CC
V
V
> 5V
IN
4.2
4.5
0.3
4.8
V
V
CC
MAIN LDO Dropout Voltage
V
V
= 4.2V, I
= 35mA
0.52
0.42
DROPOUT_MAIN IN
VCC
V
= 3V, I
VCC
= 25mA
0.25
60
V
IN
V
Current Limit of MAIN LDO
mA
CC
INTERNAL AUXILIARY LINEAR REGULATOR
AUXVCC Input Voltage Range
V
3
20
V
V
AUXVCC
AUX LDO V Voltage
CC
V
V
> 5V
4.2
4.5
0.3
4.8
CC
DROPOUT_AUX
AUXVCC
LDO Dropout Voltage
V
V
= 4.2V, I
= 35mA
0.52
0.42
V
AUXVCC
VCC
= 25mA
VCC
V
= 3V, I
0.25
60
V
AUXVCC
Current Limit of AUX LDO
mA
V
AUX LDO Switchover Rising Threshold
AUX LDO Switchover Falling Threshold Voltage
V
AUXVCC voltage rise; Switch to auxiliary LDO
2.97
2.73
3.1
3.2
AUXVCC_RISE
V
AUXVCC voltage fall; Switch back to main BIAS
LDO
2.87
2.97
V
AUXVCC_FALL
AUX LDO Switchover Hysteresis
V
AUXVCC switchover hysteresis
0.2
V
AUXVCC_HYS
FN8631 Rev 1.00
March 13, 2015
Page 7 of 24
ISL85403
Electrical Specifications Refer to “Block Diagram” on page 5 and “Typical Application Schematics” on page 6. Operating Conditions
Unless Otherwise Noted: V = 12V, or V = 4.5V ±10%, T = -40°C to +105°C. Typicals are at T = +25°C. Boldface limits apply across the operating
IN
CC
A
A
temperature range, -40°C to +105°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
PORH_RISE
TEST CONDITIONS
(Note 6)
TYP
(Note 6) UNITS
POWER-ON RESET
Rising V POR Threshold
CC
V
2.82
1.7
2.9
2.6
0.3
3.05
2.8
V
V
V
Falling V POR Threshold
CC
V
PORL_FALL
V
POR Hysteresis
V
PORL_HYS
CC
ENABLE
Enable On Voltage
Enable Off voltage
EN Pull-up Current
V
V
ENH
V
1
V
ENL
EN_PULLUP
I
V
V
V
= 1.2V, V = 24V
IN
1.5
1.2
0.9
µA
µA
µA
EN
EN
EN
= 1.2V, V = 12V
IN
= 1.2V, V = 5V
IN
OSCILLATOR
PWM Frequency
F
R = 665kΩ
160
1870
450
200
2200
500
130
210
240
2530
550
kHz
kHz
kHz
ns
OSC
T
R = 51.1kΩ
T
FS pin connected to VCC or floating or GND
MIN ON Time
t
225
MIN_ON
MIN OFF Time
t
330
ns
MIN_OFF
SYNCHRONIZATION
Input High Threshold
Input Low Threshold
Input Minimum Pulse Width
Input Impedance
VIH
VIL
2
V
V
0.5
25
ns
kΩ
100
1.1
Input Minimum Frequency Divided by Free
Running Frequency
Input Maximum Frequency Divided by Free
Running Frequency
1.6
Output Pulse Width
Output Pulse High
Output Pulse Low
REFERENCE VOLTAGE
Reference Voltage
System Accuracy
FB Pin Source Current
Soft-start
C
= 100pF
100
VCC-0.25
GND
ns
V
SYNC
VOH
VOL
R
= 1kΩ
LOAD
V
V
0.8
5
V
%
REF
-1.0
3
+1.0
7
nA
Soft-start Current
ERROR AMPLIFIER
Unity Gain-bandwidth
DC Gain
I
5
µA
SS
C
C
= 50pF
= 50pF
10
88
3.6
0.5
5
MHz
dB
V
LOAD
LOAD
Maximum Output Voltage
Minimum Output Voltage
Slew Rate
V
SR
C
= 50pF
V/µs
LOAD
FN8631 Rev 1.00
March 13, 2015
Page 8 of 24
ISL85403
Electrical Specifications Refer to “Block Diagram” on page 5 and “Typical Application Schematics” on page 6. Operating Conditions
Unless Otherwise Noted: V = 12V, or V = 4.5V ±10%, T = -40°C to +105°C. Typicals are at T = +25°C. Boldface limits apply across the operating
IN
CC
A
A
temperature range, -40°C to +105°C. (Continued)
MIN
MAX
PARAMETER
PFM MODE CONTROL
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
700
127
(Note 6) UNITS
Default PFM Current Threshold
INTERNAL HIGH-SIDE MOSFET
MODE = VCC or floating
mA
Upper MOSFET r
r
Limits apply for +25°C only
140
mΩ
DS(ON)
DS(ON)_UP
LOW-SIDE MOSFET GATE DRIVER
LGate Source Resistance
100mA source current
100mA sink current
3.5
2.8
Ω
Ω
LGATE Sink Resistance
BOOST CONVERTER CONTROL
EXT_BOOST Boost_Off Threshold Voltage
EXT_BOOST Hysteresis Sink Current
AUXVCC Boost Turn-Off Threshold Voltage
AUXVCC Hysteresis Sink Current
POWER-GOOD MONITOR
0.74
2.1
0.8
3.2
0.8
3.2
0.86
4.2
V
µA
V
I
EXT_BOOST_HYS
0.74
2.1
0.86
4.2
I
µA
AUXVCC_HYS
Overvoltage Rising Trip Point
Overvoltage Rising Hysteresis
Undervoltage Falling Trip Point
Undervoltage Falling Hysteresis
PGOOD Rising Delay
V
V
Percentage of reference point
Percentage below OV trip point
Percentage of reference point
Percentage above UV trip point
104
84
110
3
116
96
%
%
FB/ REF
V
V
V
FB/ OVTRIP
V
V
90
%
FB/ REF
V
3
%
FB/ UVTRIP
t
128
10
cycle
nA
V
PGOOD_R_DELAY
PGOOD Leakage Current
PGOOD HIGH, V
= 4.5V
PGOOD LOW, IPGOOD = 0.2mA
PGOOD
PGOOD Low Voltage
V
0.10
PGOOD
OVERCURRENT PROTECTION
Default Cycle-by-cycle Current Limit Threshold
Hiccup Current Limit Threshold
OVERVOLTAGE PROTECTION
OV 120% Trip Point
I
I
= GND or VCC or floating
3
3.6
4.2
A
OC_1
LIMIT
I
Hiccup, I
/I
OC_2 OC_1
115
%
OC_2
Active in and after soft-start.
Percentage of reference point
LG = UG = LOW
120
%
OV 120% Release Point
OV 110% Trip Point
Active in and after soft-start.
Percentage of reference point
102.5
110
%
%
Active after soft-start done.
Percentage of reference point
LG = UG = LOW
OV 110% Release Point
Active after soft-start done.
Percentage of reference point
102.5
%
OVER-TEMPERATURE PROTECTION
Over-temperature Trip Point
Over-temperature Recovery Threshold
NOTE:
160
140
°C
°C
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN8631 Rev 1.00
March 13, 2015
Page 9 of 24
ISL85403
Typical Performance Curves
100
95
90
85
80
75
70
65
60
55
50
100
95
6V V
IN
90
85
80
75
70
65
60
55
50
45
40
24V V
IN
36V V
12V V
IN
IN
12V V
IN
6V V
IN
36V V
IN
24V V
IN
35
30
0.1m
1m
10m
100m
1.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
LOAD CURRENT (A)
LOAD CURRENT (A)
FIGURE 3. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, V 5V, T = +25°C
FIGURE 4. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
5V, T = +25°C
V
OUT
A
OUT
A
5.200
5.150
5.100
5.050
5.000
4.950
4.900
4.850
4.800
5.200
5.150
5.100
5.050
5.000
4.950
4.900
4.850
4.800
I
= 0A
O
24V V
IN
12V V
IN
36V V
IN
I
= 1A
I
= 2A
O
O
6V V
2.0
IN
5
10
15
20
25
30
35
40
0
0.5
1.0
1.5
2.5
LOAD CURRENT (A)
INPUT VOLTAGE (V)
FIGURE 5. LINE REGULATION, V
OUT
5V, T = +25°C
FIGURE 6. LOAD REGULATION, V
5V, T = +25°C
OUT A
A
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
100
95
90
85
80
75
70
65
60
55
50
45
40
6V V
IN
12V V
IN
24V V
IN
12V V
IN
36V V
IN
6V V
36V V
IN
IN
24V V
IN
0.0
0.5
1.0
1.5
2.0
2.5
0.1m
1m
10m
100m
1.0
2.5
LOAD CURRENT (A)
LOAD CURRENT (A)
FIGURE 7. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, V 3.3V, T = +25°C
FIGURE 8. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
3.3V, T = +25°C
V
OUT
A
OUT
A
FN8631 Rev 1.00
March 13, 2015
Page 10 of 24
ISL85403
Typical Performance Curves(Continued)
200
180
V
= 12V
IN
V
2V/DIV
160
140
120
100
80
OUT
V
= 24V
IN
PHASE 20V/DIV
60
40
20
0
-50
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
2ms/DIV
FIGURE 10. SYNCHRONOUS BUCK MODE, V 36V, I 2A,
FIGURE 9. INPUT QUIESCENT CURRENT UNDER NO LOAD,
PFM MODE, V = 5V
IN
O
ENABLE ON
OUT
V
2V/DIV
OUT
V
2V/DIV
OUT
PHASE 20V/DIV
PHASE 20V/DIV
2ms/DIV
2ms/DIV
FIGURE 12. V 36V, PREBIASED START-UP
IN
FIGURE 11. SYNCHRONOUS BUCK MODE, V 36V, I 2A,
IN
O
ENABLE OFF
V
20mV/DIV (5V OFFSET)
OUT
V
100mV/DIV (5V OFFSET)
OUT
I
1A/DIV
OUT
PHASE 20V/DIV
PHASE 20V/DIV
1ms/DIV
5µs/DIV
FIGURE 14. V 24V, 0 TO 2A STEP LOAD, FORCE PWM MODE
IN
FIGURE 13. SYNCHRONOUS BUCK WITH FORCE PWM MODE,
36V, I 2A
V
IN
O
FN8631 Rev 1.00
March 13, 2015
Page 11 of 24
ISL85403
Typical Performance Curves(Continued)
V
200mV/DIV (5V OFFSET)
OUT
V
70mV/DIV (5V OFFSET)
OUT
LGATE 5V/DIV
LGATE 5V/DIV
I
1A/DIV
OUT
PHASE 20V/DIV
PHASE 20V/DIV
1ms/DIV
100µs/DIV
FIGURE 15. V 24V, 80mA LOAD, PFM MODE
IN
FIGURE 16. V 24V, 0 TO 2A STEP LOAD, PFM MODE
IN
V
10mV/DIV (5V OFFSET)
OUT
V
10mV/DIV (5V OFFSET)
OUT
PHASE 5V/DIV
PHASE 10V/DIV
20µs/DIV
5µs/DIV
FIGURE 17. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
12V, NO LOAD
FIGURE 18. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
12V, 2A
V
V
IN
IN
V
BUCK 100mV/DIV (5V OFFSET)
V
BUCK 100mV/DIV (5V OFFSET)
OUT
OUT
V
_BOOST_INPUT 5V/DIV
V
_BOOST_INPUT 5V/DIV
IN
IN
PHASE_BOOST 10V/DIV
PHASE_BUCK 10V/DIV
PHASE_BOOST 10V/DIV
PHASE_BUCK 10V/DIV
20ms/DIV
10ms/DIV
FIGURE 20. BOOST BUCK MODE, BOOST INPUT STEP FROM
3V TO 36V, V BUCK = 5V, I
FIGURE 19. BOOST BUCK MODE, BOOST INPUT STEP FROM 36V TO
3V, V BUCK = 5V, I = 1A
= 1A
OUT_BUCK
OUT
OUT
OUT_BUCK
FN8631 Rev 1.00
March 13, 2015
Page 12 of 24
ISL85403
Typical Performance Curves(Continued)
95
90
85
80
75
70
65
60
55
50
V
5V/DIV
OUT
15V V
IN
30V V
IN
IL_BOOST 2A/DIV
5V V
6V V
IN
IN
PHASE_BOOST 20V/DIV
PHASE_BUCK 20V/DIV
9V V
IN
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
10ms/DIV
LOAD CURRENT (A)
FIGURE 22. EFFICIENCY, BOOST BUCK, 500kHz, V
OUT
12V,
FIGURE 21. BOOST BUCK MODE, V = 9V, I = 1.8A, BOOST INPUT
O
O
T
= +25°C
DROPS FROM 16V TO 9V DC
A
190
180
170
160
150
140
130
120
110
100
DIE TEMPERATURE (°C)
FIGURE 23. UPPER MOSFET r
(mΩ) OVER-TEMPERATURE
DS(ON)
FN8631 Rev 1.00
March 13, 2015
Page 13 of 24
ISL85403
PFM Mode Operation
Functional Description
To pull the MODE pin HIGH (>2.5V) or leave the MODE pin floating
will set the IC to have PFM (Pulse Frequency Modulation)
operation in light load. In PFM mode, the switching frequency is
dramatically reduced to minimize the switching loss. The
ISL85403 enters PFM mode when the MOSFET peak current is
lower than the PWM/PFM boundary current threshold. The
default threshold is 700mA when there is no programming
resistor at the MODE pin.
Initialization
Initially the ISL85403 continually monitors the voltage at the EN
pin. When the voltage on the EN pin exceeds its rising ON
threshold, the internal LDO will start-up to build up VCC. After
Power-on Reset (POR) circuits detect that VCC voltage has
exceeded the POR threshold, the soft-start will be initiated.
Soft-start
The current threshold for PWM/PFM boundary can be
programmed by choosing the MODE pin resistor value calculated
from Equation 2.
The soft-start (SS) ramp is built up in the external capacitor on
the SS pin that is charged by an internal 5µA current source.
(EQ. 1)
118500
C
F = 6.5 t S
SS
(EQ. 2)
SS
R
= --------------------------------------
MODE
I
+ 0.2
PFM
The SS ramp starts from 0 to a voltage above 0.8V. Once SS
reaches 0.8V, the bandgap reference takes over and IC gets into
steady state operation. The soft-start time is referring to the
duration for SS pin ramps from 0 to 0.8V while output voltage
ramps up with the same rate from 0 to target regulated voltage.
The required capacitance at SS pin can be calculated from
Equation 1.
where I
is the desired PWM/PFM boundary current threshold
is the programming resistor. The usable resistor
PFM
and R
MODE
value range to program PFM current threshold is 150kΩ to
200kΩ. R
value out of this range is not recommended.
MODE
200
The SS plays a vital role in the hiccup mode of operation. The IC
works as cycle-by-cycle peak current limiting at over load
condition. When a harsh condition occurs and the current in the
upper side MOSFET reaches the second overcurrent threshold,
the SS pin is pulled to ground and a dummy soft-start cycle is
initiated. At dummy SS cycle, the current to charge soft-start
capacitor is cut down to 1/5 of its normal value. Thus, a dummy
SS cycle takes 5x of the regular SS cycle. During the dummy SS
period, the control loop is disabled and no PWM output. At the
end of this cycle, it will start the normal SS. The hiccup mode
persists until the second overcurrent threshold is no longer
reached.
190
180
170
160
150
0.3
0.4
0.5
(A)
0.6
0.7
I
PFM
The ISL85403 is capable of starting up with prebiased output.
FIGURE 24. R
vs I
PFM
MODE
PWM Control
Synchronous and Non-Synchronous Buck
Pulling the MODE pin to GND will set the IC in forced PWM mode.
The ISL85403 employs the peak current mode PWM control for
fast transient response and cycle-by-cycle current limiting. See
“Block Diagram” on page 5.
The ISL85403 supports both Synchronous and non-synchronous
buck operations.
In synchronous buck configuration, a 5.1k or smaller value
resistor must be added from LGATE to ground to avoid falsely
turn-on of LGATE caused by coupling noise.
The PWM operation is initialized by the clock from the oscillator.
The upper MOSFET is turned on by the clock at the beginning of a
PWM cycle and the current in the MOSFET starts to ramp up.
When the sum of the current sense signal and the slope
compensation signal reaches the error amplifier output voltage
level, the PWM comparator is triggered to shut down the PWM
logic to turn off the high-side MOSFET. The high-side MOSFET
stays off until the next clock signal comes for next cycle.
For a non-synchronous buck operation when a power diode is
used as the low-side power device, the LGATE driver can be
disabled with LGATE connected to VCC (before IC start-up). For
non-synchronous buck, the phase node will show oscillations
after high-side turns off (as shown in Figure 17 on page 12 - blue
trace). This is normal due to the oscillations among the parasitic
capacitors at phase node and output inductor. A RC snubber
(suggesting 200Ω and 2.2nF as typical) at phase node can
reduce this ringing.
The output voltage is sensed by a resistor divider from V
OUT
to
the FB pin. The difference between the FB voltage and 0.8V
reference is amplified and compensated to generate the error
voltage signal at the COMP pin. Then the COMP pin signal is
compared with the current ramp signal to shut down the PWM.
FN8631 Rev 1.00
March 13, 2015
Page 14 of 24
ISL85403
AUXVCC Switchover
Output Voltage
The ISL85403 has an auxiliary LDO integrated as shown in the
“Block Diagram” on page 5. It is used to replace the internal
MAIN LDO function after the IC start-up. “Typical Application
The output voltage can be programmed down to 0.8V by a
resistor divider from V
to FB. For Buck, the maximum
- V ), where V is the
OUT
achievable voltage is (V *D
IN MAX DROP
DROP
Schematic II - VCC Switchover to V
” on page 6 shows its basic
voltage drop in the power path including mainly the MOSFET
r and inductor DCR. The maximum duty cycle D is
OUT
application setup with output voltage connected to AUXVCC. After
IC soft-start is done and the output voltage is built up to steady
state, and once the AUXVCC pin voltage is over the AUX LDO
Switchover Rising Threshold, the MAIN LDO is shut off and the
AUXILIARY LDO is activated to bias VCC. Since the AUXVCC pin
DS(ON)
decided by (1 - f
MAX
* t
).
SW
MIN(OFF)
Output Current
With the high-side MOSFET integrated, the maximum output
current, which the ISL85403 can support is decided by the
package and many operating conditions including input voltage,
output voltage, duty cycle, switching frequency and temperature,
etc. From the thermal perspective, the die temperature shouldn’t
exceed +125°C with the power loss dissipated inside of the IC.
voltage is lower than the input voltage V , the internal LDO
IN
dropout voltage and the consequent power loss is reduced. This
feature brings substantial efficiency improvements in light load
range, especially at high input voltage applications.
When the voltage at AUXVCC falls below the AUX LDO Switchover
Falling Threshold, the AUXILIARY LDO is shut off and the MAIN LDO
is reactivated to bias VCC. At the OV/UV fault events, the IC also
switches back over from AUXILIARY LDO to MAIN LDO.
Note that more temperature rise is expected at higher ambient
temperature due to more conduction loss caused by r
increase.
DS(ON)
The AUXVCC switchover function is offered in buck configuration.
It is not offered in boost configuration when the AUXVCC pin is
used to monitor the boost output voltage for OVP.
Basically, the die temperature is equal to the sum of ambient
temperature and the temperature rise resulting from the power
dissipated by the IC package with a certain junction to ambient
thermal impedance . The power dissipated in the IC is related
JA
Input Voltage
to the MOSFET switching loss, conduction loss and the internal
LDO loss. Besides the load, these losses are also related to input
voltage, output voltage, duty cycle, switching frequency and
temperature. With the exposed pad at the bottom, the heat of
With the part switching, the operating ISL85403 input voltage
must be under 40V. This recommendation allows for short
voltage ringing spikes (within a couple of ns time range) due to
part switching while not exceeding the 44V, as stated in the
Absolute Maximum Ratings.
the IC mainly goes through the bottom pad and is greatly
JA
reduced. The is highly related to layout and air flow
JA
conditions. In layout, multiple vias (≥9) are strongly
recommended in the IC bottom pad. The bottom pad with its vias
should be placed in the ground copper plane with an area as
The lowest IC operating input voltage (VIN pin) depends on VCC
voltage and the Rising and Falling V POR Threshold in
CC
Electrical Specifications table on page 8. At IC start-up when VCC
is just over rising POR threshold, there is no switching before the
soft-start starts. Therefore, the IC minimum start-up voltage on
large as possible across multiple layers. The can be reduced
JA
further with air flow. Refer to Figures 8 and 9 for the thermal
performance with 100 CFM air flow.
the VIN pin is 3.05V (MAX of Rising V POR). When the soft-start
CC
is initiated, the regulator is switching and the dropout voltage
across the internal LDO increases due to driving current. Thus,
the IC VIN pin shutdown voltage is related to driving current and
VCC POR falling threshold. The internal upper side MOSFET has
typical 10nC gate drive. For a typical example of synchronous
buck with 4nC lower MOSFET gate drive and 500kHz switching
frequency, the driving current is 7mA total causing 70mV drop
For applications with high output current and bad operating
conditions (compact board size, high ambient temperature, etc.),
synchronous buck is highly recommended since the external
low-side MOSFET generates smaller heat than external low-side
power diode. This helps to reduce PCB temperature rise around
the ISL85403 and less junction temperature rise.
across internal LDO under 3V V . Then the IC shutdown voltage
IN
on the VIN pin is 2.87V (2.8V + 0.07V). In practical design, extra
room should be taken into account with concern to voltage
spikes at VIN.
With boost buck configuration, the input voltage range can be
expanded further down to 2.5V or lower depending on the boost
stage voltage drop upon maximum duty cycle. Since the boost
output voltage is connected to the VIN pin as the buck inputs,
after the IC starts up, the IC will keep operating and switching as
long as the boost output voltage can keep the VCC voltage higher
than the falling threshold. Refer to “2-Stage Boost Buck
Converter Operation” on page 16 for more details.
FN8631 Rev 1.00
March 13, 2015
Page 15 of 24
ISL85403
Use Equation 4 to calculate the lower resistor RLOW (R2 in
Figure 25) according to a desired boost enable threshold.
2-Stage Boost Buck Converter Operation
The “Typical Application Schematic III - Boost Buck Converter” on
page 6, shows the circuits of boost function. Schematic (a) shows
a boost working as a pre-stage to provide input to the following
Buck stage. This is for applications when the input voltage could
drop to a very low voltage in some constants (i.e., in some battery
powered systems), causing the output voltage to drop out of
regulation. The boost converter can be enabled to boost the input
voltage up to keep the output voltage in regulation. When system
input voltage recovers back to normal, the boost stage is
disabled while only the buck stage is switching.
R
0.8
UP
(EQ. 4)
R
= ---------------------------------------
LOW
VFTH – 0.8
Where VFTH is the desired falling threshold on boost input
voltage to turn on the boost, 3µA is the hysteresis current and
0.8V is the reference voltage to be compared with.
Note that the boost start-up threshold has to be selected in a way
that the buck is operating working well and kept in close loop
regulation before boost start-up. Otherwise, large inrush current
at boost start-up could occur at boost input due to the buck open
loop saturation. The boost start-up input voltage threshold should
be set high enough to cover the DC voltage drop of boost inductor
and diode, also the buck’s maximum duty cycle and voltage
conduction drop. This ensures buck is not reaching maximum
duty cycle before boost start-up.
The EXT_BOOST pin is used to set boost mode and monitor the
boost input voltage. At IC start-up before soft-start, the controller
will be latched in boost mode when the voltage is at or above
200mV; it will latch in synchronous buck mode if voltage on this
pin is below 200mV. In boost mode, the low-side driver output
PWM has the same PWM signal with the buck regulator.
Similarly, a resistor divider from the boost output voltage to the
AUXVCC pin is used to detect the boost output voltage. When the
voltage on the AUXVCC pin is below 0.8V, the boost PWM is
enabled with a fixed 500µs soft-start and a 3µA sinking current
is enabled at AUXVCC pin for hysteresis purposes. When the
voltage on the AUXVCC pin recovers to be above 0.8V, the boost
PWM is disabled immediately. Use Equation 3 to calculate the
In boost mode, the EXT_BOOST pin is used to monitor boost input
voltage to turn on and turn off the boost PWM. The AUXVCC pin is
used to monitor the boost output voltage to turn on and turn off
the boost PWM.
Referring to Figure 25, a resistor divider from boost input voltage
to the EXT_BOOST pin is used to detect the boost input voltage.
When the voltage on EXT_BOOST pin is below 0.8V, the boost
PWM is enabled with a fixed 500µs soft-start and the boost duty
upper resistor R (R in Figure 25) according to a desired
UP
3
hysteresis V at boost output voltage. Use Equation 4 to
HY
calculate the lower resistor R
LOW
(R in Figure 25) according to a
4
cycle increases linearly from t
*Fs to ~50%. A 3µA sinking
MIN(ON)
desired boost enable threshold at boost output.
current is enabled at the EXT_BOOST pin for hysteresis purposes.
When the voltage on the EXT_BOOST pin recovers to be above
0.8V, the boost PWM is disabled immediately. Use Equation 3 to
Assuming V is the boost input voltage, V
is the boost
BAT
output voltage and V
OUT_BST
is the buck output voltage, the steady
OUT
calculate the upper resistor RUP (R in Figure 25) for a desired
1
state DC transfer function are:
hysteresis V
at boost input voltage.
HYS
HYS
3A
1
1 – D
(EQ. 5)
(EQ. 6)
-----------------
V
V
=
V
V
OUTBST
BAT
R
M = ---------------------
(EQ. 3)
UP
D
-----------------
V
BAT
= D V
=
OUT
OUTBST
1 – D
BATTERY
VOUT_BST
+
+
R1
EXT_BOOST
0.8V
R2
I_HYS = 3µA
LOGIC
R3
R4
LGATE
AUXVCC
LGATE
DRIVE
PWM
0.8V
I_HYS = 3µA
FIGURE 25. BOOST CONVERTER CONTROL
FN8631 Rev 1.00
March 13, 2015
Page 16 of 24
ISL85403
From Equations 5 and 6, Equation 7 can be derived to estimate
Where V is the input voltage, V
is the buck boost output
OUT
IN
the steady state boost output voltage as function of V
and
voltage, D is duty cycle.
BAT
V
:
OUT
Equation 10 is another useful equation used to calculate the
inductor DC current as below:
(EQ. 7)
V
= V
+ V
OUT
OUTBST
BAT
1
After the IC starts up, the boost buck converters can keep
-----------------
IL
=
I
(EQ. 10)
DC
OUT
1 – D
working when the battery voltage drops extremely low because
the IC’s bias (VCC) LDO is powered by the boost output. For
example, a 3.3V output application battery drops to 2V, and the
VIN pin voltage is powered by the boost output voltage that is
5.2V (Equation 7), meaning that the VIN pin (buck input) still sees
5.2V to keep the IC working.
Where IL is the inductor DC current and I
DC
is the output DC
OUT
current.
Equation 10 shows the inductor current is charging output only
during (1-D)T, which means inductor current has larger DC
current than output load current. Thus, for this part with high-side
FET integrated, the non-inverting buck boost configuration has
less load current capability compared with buck and 2-stage
boost buck configurations. Its load current capability depends
mainly on the duty cycle and inductor current.
Note that in the previously mentioned case, the boost input
current could be high because the input voltage is very low
(V *I = V /Efficiency). If the design is to achieve the
*I
IN IN OUT OUT
low input operation with full load, the inductor and MOSFET have
to be selected with enough current ratings to handle the high
current appearing at boost input. The boost inductor current are
the same with the boost input current, which can be estimated as
Inductor ripple current can be calculated using Equation 11:
V
1 – DT
OUT
(EQ. 11)
(EQ. 12)
IL
= -----------------------------------------------------
RIPPLE
Equation 8, where P
is the output power, V is the boost input
OUT
BAT
L
voltage, and EFF is the estimated efficiency of the whole boost and
buck stages.
The inductor peak current is,
1
2
P
(EQ. 8)
OUT
IL = ----------------------------------------
IN
---
IL
= IL
+
IL
RIPPLE
PEAK
DC
V
EFF
BAT
In power stage DC calculations, use Equation 9 to calculate D,
Based on the same concerns of boost input current, the start-up
sequence must follow the rule that the IC is enabled after the
boost input voltage rise above a certain level. The shutdown
sequence must follow the rule that the IC is disabled first before
the boost input power source is turned off. At boost mode
applications where there is no external control signal to
enable/disable the IC, an external input UVLO circuit must be
implemented for the start-up and shutdown sequence.
then use Equation 10 to calculate IL . D and IL are useful
DC DC
information to estimate the high-side FET’s power losses and
check if the part can meet the load current requirements.
Oscillator and Synchronization
The oscillator has a default frequency of 500kHz with the FS pin
connected to VCC, or ground, or floating. The frequency can be
programmed to any frequency between 200kHz and 2.2MHz with
a resistor from FS pin to GND.
Non-inverting Single inductor Buck Boost
Converter Operation
145000 – 16 f
kHz
SW
R
k = -----------------------------------------------------------------------------------------
(EQ. 13)
FS
f
[kHz]
SW
In “Typical Application Schematic III - Boost Buck Converter” on
page 6, schematic (b) shows non-inverting single inductor buck
boost configuration. The recommended setting is to use resistor
divider 1MΩ and 130kΩ (as shown in TYP Schematic III b)
connecting from VCC to both EXT_BOOST and AUXVCC pins
(EXT_BOOST and AUXVCC pin are directly connected). In this way,
the EXT_BOOST pin voltage is a fixed voltage 0.52V that is higher
than the boost mode detection threshold 0.2V to set IC in boost
mode and lower than the boost switching threshold 800mV to
have boost being constantly switching (during and after
soft-start).
1200
1000
800
600
400
200
0
As the same in 2-stage boost buck mode, LGATE is switching ON
with the same phase of upper FETs switching ON, meaning both
upper and lower side FETs are ON and OFF at the same time with
the same duty cycle. When both FETs are ON, input voltage
charges inductor current ramping up for duration of DT; when
both FETs are OFF, inductor current is free wheeling through the 2
power diodes to output and output voltage discharge the inductor
current ramping down for (1-D)T (in CCM mode). The steady state
DC transfer function is:
0
500
1000
1500
(kHz)
2000
2500
f
SW
FIGURE 26. R vs FREQUENCY
FS
The SYNC pin is bidirectional and it outputs the IC’s default or
programmed local clock signal when it’s free running. The IC
locks to an external clock injected to the SYNC pin (external clock
frequency recommended to be 10% higher than the free running
frequency). The delay from the rising edge of the external clock
signal to the PHASE rising edge is half of the free running switching
D
1 – D
-----------------
(EQ. 9)
V
=
V
OUT
IN
FN8631 Rev 1.00
March 13, 2015
Page 17 of 24
ISL85403
period pulse 220ns, (0.5t +220ns). The maximum external clock
SW
frequency is recommended to be 1.6 of the free running frequency.
for dummy soft-start duration equaling to 5 regular soft-start
periods. After this dummy soft-start cycle, the true soft-start cycle
is attempted again. The I
protection against the worst case conditions.
offers a robust and reliable
OC2
When the part enters PFM pulse skipping mode, the
synchronization function is shut off and also no clock signal
output in SYNC pin.
The frequency foldback is implemented for the ISL85403. When
overcurrent limiting, the switching frequency is reduced to be
proportional to output voltage in order to keep the inductor
current under limit threshold during overload condition. The low
limit of frequency under frequency foldback operation is 40kHz.
With the SYNC pins simply connected together, multiple
ISL85403s can be synchronized. The slave ICs automatically
have 180° phase shift with respective to the master IC.
PGOOD
320
300
280
260
240
220
200
180
160
140
120
100
80
The PGOOD pin is output of an open-drain transistor (refer to
“Block Diagram” on page 5). An external resistor is required to be
pulled up to VCC for proper PGOOD function. At start-up, PGOOD
will be turned HIGH (internal PGOOD open-drain transistor is
turned off) with 128 cycles delay after soft-start is finished
(soft-start ramp reaches 1.02V) and FB voltage is within OV/UV
window (90%REF < FB < 110%REF).
At normal operation, PGOOD will be pulled low with 1 cycle
(minimum) and 6 cycles (maximum) delay if any of the OV
(110%) or UV (90%) comparator is tripped. The PGOOD will be
released HIGH with 128 cycles delay after FB recovers to be
within OV/UV window (90%REF < FB < 110%REF). When EN is
pulled low or VCC is below POR, PGOOD is pulled low with no
delay.
60
40
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
(A)
I
OC1
FIGURE 27. R
LIM
vs I
OC1
In the case when the PGOOD pin is pulled up by external bias
supply instead of VCC of itself, when the part is disabled, the
internal PGOOD open-drain transistor is off, the external bias
supply can charge PGOOD pin HIGH. This should be known as
false PGOOD reporting. At start-up when VCC rise from 0, PGOOD
will be pulled low when VCC reaches 1V. After EN is pulled low
and VCC is falling, the PGOOD internal open-drain transistor will
open with high impedance when VCC falls below 1V. The time
between EN pulled low and PGOOD OPEN depends on the VCC
falling time to 1V.
Overvoltage Protection
If the voltage detected on the FB pin is over 110% or 120% of
reference, the high-side and low-side driver shuts down
immediately and stays off until FB voltage drops to 0.8V. When
the FB voltage drops to 0.8V, the drivers are released ON. 110%
OVP is off during soft-start and active after soft-start is done.
120% OVP is active during and after soft-start.
Thermal Protection
The ISL85403 PWM will be disabled if the junction temperature
reaches +160°C. There is +20°C hysteresis for OTP. The part will
restart after the junction temperature drops below +140°C.
Fault Protection
Overcurrent Protection
The overcurrent function protects against any overload condition
and output short at worst case, by monitoring the current flowing
through the upper MOSFET.
Component Selections
The ISL85403 iSim model can be used to simulate for both the
time domain behaviors and small signal loop stability analysis.
There are 2 current limiting thresholds. The first one I
OC1
is to
Output Capacitors - Buck
limit the high-side MOSFET peak current cycle-by-cycle. The
current limit threshold is set to default at 3.6A with ILIMIT pin
connected to GND or VCC, or left open. The current limit threshold
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are two critical
factors when considering output capacitance choice. The current
mode control loop allows for the usage of low ESR ceramic
capacitors and thus smaller board layout. Electrolytic and
polymer capacitors may also be used.
can also be programmed by a resistor R
at ILIMIT pin to
LIM
ground. Use Equation 14 to calculate the resistor.
300000
A + 0.018
(EQ. 14)
R
= ------------------------------------------------------
LIM
I
OC
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
Note that I
OC1
is higher with lower R . The usable resistor
LIM
value range to program OC1 peak current threshold is 40kΩ
to 330kΩ. R value out of this range is not recommended.
LIM
The second current protection threshold I
is 15% higher than
OC2
mentioned previously. Instantly after the high-side MOSFET
I
OC1
current reaches I
, the PWM is shut off after 2-cycle delay and
OC2
the IC enters hiccup mode. In hiccup mode, the PWM is disabled
FN8631 Rev 1.00
March 13, 2015
Page 18 of 24
ISL85403
manufacturers datasheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
reduce the converter’s response time to a load transient. The
inductor current rating should be as such that it will not saturate
in overcurrent conditions.
Low-side Power MOSFET
In synchronous buck application, a power N MOSFET is needed
as the synchronous low-side MOSFET and a good one should
have low Qgd, low r
and small Rg (Rg_typ < 1.5Ω
DS(ON)
recommended). The Vgth_min is recommended to be or higher
than 1.2V. A good example is SQS462EN.
In buck topology, the following equations allow calculation of the
required capacitance to meet a desired ripple voltage level.
Additional capacitance may be used.
A 5.1k or smaller value resistor has to be added to connect
LGATE to ground to avoid falsely turn-on of LGATE caused by
coupling noise.
For the ceramic capacitors (low ESR):
I
------------------------------------
V
=
(EQ. 15)
is the
Output Voltage Feedback Resistor Divider
The output voltage can be programmed down to 0.8V by a
OUTripple
8 f
C
OUT
SW
where I is the inductor’s peak to peak ripple current, f
SW
switching frequency and C
resistor divider from V
to FB according to Equation 19.
OUT
is the output capacitor.
OUT
R
UP
----------------
(EQ. 19)
V
= 0.8 1 +
If using electrolytic capacitors then:
OUT
R
LOW
V
= I*ESR
(EQ. 16)
OUTripple
In an application requiring least input quiescent current, large
resistors should be used for the divider. Generally, a resistor
value of 10k to 300k can be used for the upper resistor.
Regarding transient response needs, a good starting point is to
determine the allowable overshoot in V if the load is suddenly
OUT
removed. In this case, energy stored in the inductor will be
transferred to C causing its voltage to rise. After calculating
OUT
Boost Inductor (2-Stage Boost Buck)
capacitance required for both ripple and transient needs, choose
the larger of the calculated values. The Equation 17 determines
the required output capacitor value in order to achieve a desired
overshoot relative to the regulated voltage.
Besides the need to sustain the current ripple to be within a
certain range (30% to 50%), the boost inductor current at its
soft-start is a more important perspective to be considered in
selection of the boost inductor. Each time the boost starts up,
there is a fixed 500µs soft-start time when the duty cycle
2
I
L
*
OUT
--------------------------------------------------------------------------------------------
=
C
(EQ. 17)
OUT
2
2
V
V
V
– 1
increases linearly from t
*f to ~50%. Before and after
*
MIN(ON) SW
OUT
OUTMAX
OUT
boost start-up, the boost output voltage will jump from
to voltage (V + V ). The design target
in boost soft-start is to ensure the boost input current is
where V is the relative maximum overshoot
allowed during the removal of the load.
/V
V
OUTMAX OUT
IN_BOOST
IN_BOOST
OUT_BUCK
sustained to minimum but capable to charge the boost output
Input Capacitors - Buck
voltage to have a voltage step equaling to V
. A big
OUT_BUCK
inductor will block the inductor current to increase and not high
enough to be able to charge the output capacitor to the final
Depending on the system input power rail conditions, the
aluminum electrolytic type capacitor is normally needed to
provide the stable input voltage. Thus, restrict the switching
frequency pulse current in a small area over the input traces for
better EMC performance. The input capacitor should be able to
handle the RMS current from the switching power devices.
steady state value (V
+ V ) within 500µs. A
IN_BOOST
OUT_BUCK
6.8µH inductor is a good starting point for its selection in design.
The boost inductor current at start-up must be checked by
oscilloscope to ensure it is under an acceptable range. It is
suggested to run the iSim model (use the ISL85403 iSim model
available on the internet) to assist in the proper inductor value.
Ceramic capacitors must be used at VIN pin of the IC and
multiple capacitors including 1µF and 0.1µF are recommended.
Place these capacitors as closely as possible to the IC.
Boost Output Capacitor (2-Stage Boost Buck)
Based on the same theory in boost start-up previously described
in the boost inductor selection, a large capacitor at boost output
will cause high inrush current at boost PWM start-up. 22µF is a
good choice for applications with a buck output voltage less than
10V. Also some minimum amount of capacitance has to be used
in boost output to keep the system stable. It is suggested to run
the iSim model, which is available on the internet to assist in
designing the proper capacitor value.
Output Inductor - Buck
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% to
40% of total load current. The inductor value is calculated using
Equation 18:
V
– V
V
OUT
V
IN
IN
f
OUT
(EQ. 18)
------------------------------- ---------------
L =
I
SW
Increasing the value of inductance reduces the ripple current and
thus ripple voltage. However, the larger inductance value may
FN8631 Rev 1.00
March 13, 2015
Page 19 of 24
ISL85403
Power Stage Transfer Functions
Transfer function F (S) from control to output voltage is:
1
Loop Compensation Design -
Buck
S
-----------
1 +
The ISL85403 uses constant frequency peak current mode
control architecture to achieve fast loop transient response. An
accurate current sensing pilot device in parallel with the upper
MOSFET is used for peak current control signal and overcurrent
protection. The inductor is not considered as a state variable
since its peak current is constant and the system becomes single
order system. It is much easier to design the compensator to
stabilize the loop compared with voltage mode control. Peak
current mode control has inherent input voltage feed-forward
function to achieve good line regulation. Figure 28 shows the
small signal model of a buck regulator.
ˆ
v
esr
o
(EQ. 23)
------
ˆ
--------------------------------------
F S =
= V
1
in
2
d
S
S
------ --------------
+
+ 1
2
o
Q
o
p
C
1
1
o
--------------
------------------
=
,Q R ------ , =
Where,
esr
p
o
o
R C
L
L C
c
o
P
P
o
Transfer function F (S) from control to inductor current is given
2
by Equation 24:
S
------
1 +
ˆ
V
I
(EQ. 24)
o
in
z
----
ˆ
------------------------ --------------------------------------
F S =
=
2
2
R
+ R
LP
d
o
S
S
^
^
------ --------------
+
+ 1
^
o
L
R
LP
i
P
i
2
o
L
v
Q
in
o
p
^
d
1
V
in
^
^
--------------
=
1:D
I d
where
.
V
z
L
in
R C
o
o
Rc
Co
+
R
T
Current loop gain T (S) is expressed as Equation 25:
i
Ro
(EQ. 25)
T S = R F F SH S
i
t
m
2
e
The voltage loop gain with open current loop is expressed in
Equation 26:
T (S)
i
^
d
(S)
Fm
T S = KF F SA S
(EQ. 26)
v
m
1
v
The Voltage loop gain with current loop closed is given by
Equation 27:
T (S)
+
v
He(S)
^
v
comp
T S
-Av(S)
v
(EQ. 27)
-----------------------
L S =
v
1 + T S
i
FIGURE 28. SMALL SIGNAL MODEL OF BUCK REGULATOR
If T (S)>>1, then Equation 27 can be simplified as Equation 28:
i
PWM Comparator Gain F
m
S
-----------
1 +
The PWM comparator gain F for peak current mode control is
m
R
+ R
A S
esr v
1
o
LP
(EQ. 28)
given by Equation 20:
-------------------------------------------------------------
--------------
L S=
,
p
v
R
S
H S
R C
o o
t
e
------
1 +
ˆ
d
1
(EQ. 20)
p
----------------
-------------------------------
F
=
=
m
ˆ
S + S T
s
v
e
n
comp
Equation 28 shows that the system is a single order system.
Therefore, a simple type II compensator can be easily used to
stabilize the system. A type III compensator is needed to expand
the bandwidth for current mode control in some cases.
Where, S is the slew rate of the slope compensation and S is
given by Equation 21:
e
n
V
– V
o
L
P
(EQ. 21)
in
---------------------
S
= R
n
t
C1
R2
R3
C3
where, R is the gain of the current amplifier.
t
VO
VCOMP
Current Sampling Transfer Function H (S)
e
In current loop, the current signal is sampled every switching
cycle. It has the following transfer function in Equation 22:
R1
VREF
RBIAS
2
(EQ. 22)
S
S
------ --------------
+
H S=
+ 1
e
2
n
Q
n
n
FIGURE 29. TYPE III COMPENSATOR
2
--
Q
= – = f
n
n
SW
where, Q and are given by
n
n
FN8631 Rev 1.00
March 13, 2015
Page 20 of 24
ISL85403
A compensator with 2 zeros and 1 pole is recommended for this
part, as shown in Figure 29. Its transfer function is expressed as
Equation 29:
Example: V = 12V, V = 5V, I = 2A, f
= 500kHz,
C = 60µF/3mΩ, L = 10µH, R = 0.20V/A, f = 50kHz,
IN SW
o
o
o
t
c
R = 105k, R
= 20kΩ.
1
BIAS
S
S
------------
------------
Select the crossover frequency to be 35kHz. Since the output
capacitors are all ceramic, use Equations 33 and 34 to
derive R to be 20k and C to be 470pF.
1 +
1 +
ˆ
v
(EQ. 29)
1
comp
cz1
cz2
---------------- ------------------- ---------------------------------------------------------
A S=
=
v
ˆ
SR C
S
v
1
O
---------
1
1 +
3
3
cp
Then use Equations 35 and 36 to calculate C1 to be 180pF
and R to be 12.7k. Select 150pF for C and 15k for R .
where,
2
1
2
1
1
1
--------------
---------------------------------
--------------
=
,
=
=
cp
There is approximately 30pF parasitic capacitance between
COMP to FB pins that contributes to a high frequency pole.
Any extra external capacitor is not recommended between
COMP and FB.
cz1
cz2
R C
R + R C
R C
3 3
2
1
1
3
3
Compensator design goal:
1
4
1
10
-- ------
to
f
Loop bandwidth f :
SW
c
Figure 30 shows the simulated bode plot of the loop. It is
shown that it has 26kHz loop bandwidth with 70° phase
margin and -28 dB gain margin.
Gain margin: >10dB
Phase margin: 45°
Note in applications where the PFM mode is desired especially
when type III compensation network is used, the value of the
capacitor between the COMP pin and the FB pin (not the
capacitor in series with the resistor between COMP and FB)
should be minimal to reduce the noise coupling for proper PFM
operation. No external capacitor between COMP and FB is
recommended at PFM applications.
The compensator design procedure is as follows:
1. Position CZ2 and CP to derive R and C .
3
3
Put the compensator zero CZ2 at (1 to 3)/(R C )
o o
(EQ. 30)
3
--------------
=
cz2
R C
o
o
In PFM mode operations, a RC filter from FB to ground (R in
series with C, connecting from FB to ground) may help to reduce
the noise effects injected to FB pin. The recommended values for
the filter is 499Ω to 1k for the R and 470pF for the C.
Put the compensator pole CP at ESR zero or 0.35 to 0.5
times of switching frequency, whichever is lower. In
all-ceramic-cap design, the ESR zero is normally higher than
half of the switching frequency. R and C can be derived as
3
3
follows:
1
----------------------
Case A: ESR zero
less than (0.35 to 0.5)f
SW
2R C
c
o
R C – 3R C
c o
(EQ. 31)
(EQ. 32)
o
o
---------------------------------------
C
R
=
=
3
3R
1
3R R
c
1
-----------------------
3
R
– 3R
c
o
1
----------------------
Case B: ESR zero
larger than (0.35 to 0.5)f
SW
2R C
c
o
0.33R C f
– 0.46
(EQ. 33)
(EQ. 34)
o
o SW
-------------------------------------------------------
C
R
=
=
3
3
f
R
SW
1
R
1
-----------------------------------------
0.73R C f – 1
o
o s
2. Derive R and C .
2
1
The loop gain L (S) at cross over frequency of f has unity
v
c
gain. Therefore, C is determined by Equation 35.
1
R + R C
3
(EQ. 35)
1
3
---------------------------------
=
C
1
2f R R C
c
t 1
o
The compensator zero CZ1 can boost the phase margin and
bandwidth. To put CZ1 at 2 times of cross cover frequency
f is a good start point. It can be adjusted according to
c
specific design. R can be derived from Equation 36.
1
(EQ. 36)
1
-------------------
R
=
2
4f C
c
1
FN8631 Rev 1.00
March 13, 2015
Page 21 of 24
ISL85403
Loop Compensation Design for
2-Stage Boost Buck and
Layout Suggestions
1. Place the input ceramic capacitors as closely as possible to
the IC VIN pin and power ground connecting to the power
MOSFET or Diode. Keep this loop (input ceramic capacitor, IC
VIN pin and MOSFET/Diode) as tiny as possible to achieve the
least voltage spikes induced by the trace parasitic
inductance.
Single-stage Buck Boost
For 2-stage boost buck and single-stage non-inverting buck boost
configurations, it’s highly recommended to use the iSim model
(use the ISL85403 iSim model available in internet) to evaluate
the loop bandwidth and phase margin.
2. Place the input aluminum capacitors closely as possible to
the IC VIN pin.
80
60
40
20
0
3. Keep the phase node copper area small but large enough to
handle the load current.
4. Place the output ceramic and aluminum capacitors close to
the power stage components as well.
5. Place vias (≥9) in the bottom pad of the IC. The bottom pad
should be placed in ground copper plane with an area as large
as possible in multiple layers to effectively reduce the thermal
impedance.
6. Place the 4.7µF ceramic decoupling capacitor at the VCC pin
(the closest place to the IC). Put multiple vias (≥3) close to the
ground pad of this capacitor.
-20
-40
-60
7. Keep the bootstrap capacitor close to the IC.
3
4
5
6
100
1•10
1•10
1•10
1•10
8. Keep the LGATE drive trace as short as possible and try to
avoid using via in the LGATE drive path to achieve the lowest
impedance.
FREQUENCY (Hz)
9. Place the positive voltage sense trace close to the place to be
strictly regulated.
180
160
140
120
100
80
10. Place all the peripheral control components close to the IC.
60
40
20
FIGURE 31. PCB VIA PATTERN
0
100
3
4
5
6
1•10
1•10
1•10
1•10
FREQUENCY (Hz)
FIGURE 30. SIMULATED LOOP BODE PLOT
FN8631 Rev 1.00
March 13, 2015
Page 22 of 24
ISL85403
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN8631.1
CHANGE
March 13, 2015
Changed the max input Voltage (Vin) from 36V to 40V on the following pages:
On page 1: In the description and features sections
On page 4: V pin description
IN
On page 7: Recommended operating conditions for V
IN
On page 15: Application description for the “Input Voltage” section
On page 1, added “Related Literature” section.
On page 4, added ISL85403EVAL2Z to the Ordering Information table.
Replaced Figures 5 and 6.
Removed Figures 10 and 11 and the references on page 15.
March 12, 2014
FN8631.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2014-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8631 Rev 1.00
March 13, 2015
Page 23 of 24
ISL85403
Package Outline Drawing
L20.4x4C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/06
4X
2.0
4.00
0.50
16X
A
6
B
16
20
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
1
15
2 .70 ± 0 . 15
11
5
(4X)
0.15
6
10
0.10 M
C
A B
4
20X 0.25 +0.05 / -0.07
20X 0.4 ± 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3. 8 TYP )
(
SEATING PLANE
0.08 C
2. 70 )
( 20X 0 . 5 )
SIDE VIEW
( 20X 0 . 25 )
( 20X 0 . 6)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN8631 Rev 1.00
March 13, 2015
Page 24 of 24
相关型号：
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2.5A Regulator with Integrated High-side MOSFET for Synchronous Buck or Boost Buck Converter
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ISL85403FRZ
2.5A Regulator with Integrated High-side MOSFET for Synchronous Buck or Boost Buck Converter
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