ISL88016IHTZ-TK [RENESAS]
6-Pin Voltage Supervisors with Pin-Selectable Voltage Trip Points; TSOT6; Temp Range: -40° to 85°C;
| 型号： | ISL88016IHTZ-TK |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 6-Pin Voltage Supervisors with Pin-Selectable Voltage Trip Points; TSOT6; Temp Range: -40° to 85°C 光电二极管 |
| 文件： | 总8页 (文件大小：514K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL88016, ISL88017
6-Pin Voltage Supervisors with Pin-Selectable Voltage Trip Points
FN6141
Rev 1.00
August 5, 2015
The ISL88016, ISL88017 supervisors offer pin-selectable
voltage trip points along with popular functions such as
Features
• Pin-Selectable Single Voltage Monitoring Supervisors
Power-on Reset control, Supply Voltage Supervision, and
Manual Reset assertion in a small 6 Ld TSOT-23 package.
• User Pin-Selectable Voltage Trip Points
- ISL88016: 1.60V to 2.85V in 50mV Steps
- ISL88017: 2.15V to 4.65V in 100mV Steps
By connecting the three VSET pins to V , GND or floating,
DD
users can program the voltage trip point from 1.60V to 2.85V
in 50mV increments on the ISL88016 and from 2.15V to
4.65V in 100mV increments on the ISL88017. These user-
selectable reset threshold voltages are accurate to ±2% over
temperature and the reset signal is valid down to 1V.
• Reduce Inventory on Fixed Voltage Trip Point Options
• Manual Reset Capability
• Proprietary TwinPin™ Combines Active-Low Reset Output
and Manual Reset Input Functions into One Pin
Intersil’s proprietary TwinPin™ combines the active low reset
out with the manual reset input into one pin. This provides
device adjustability without sacrificing functionality. These
parts are specifically designed for low power consumption
and high threshold accuracy.
• Reset Signal Valid Down to V
= 0.8V
DD
• Voltage Threshold ±2% Accuracy Over Temp
• No External Components Necessary
• Immune to Power-Supply Transients
• Ultra Low 3µA Supply Current
Pinout
ISL88016, ISL88017
(6 LD TSOT-23)
TOP VIEW
• Small 6 Ld TSOT-23 Pb-Free Plus Anneal Available
(RoHS Compliant)
V
1
2
3
6
5
4
RST/MR
VSET3
VSET2
Ordering Information
DD
PART NUMBER
(Note)
PART
MARKING REEL
TAPE & PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL88016
ISL88017
GND
ISL88016IHTZ-T
(Nolongeravailable
or supported)
016Z
3k pcs 6 Ld TSOT-23 MDP0049
Tape & Reel
VSET1
ISL88017IHTZ-T
017Z
016Z
3k pcs 6 Ld TSOT-23 MDP0049
Tape & Reel
ISL88016IHTZ-TK
(Nolongeravailable
or supported)
1k pcs 6 Ld TSOT-23 MDP0049
Tape & Reel
Applications
• Process Control Systems
• Intelligent Instruments
• Embedded Control Systems
• Computer Systems
ISL88017IHTZ-T7A 017Z
250 pcs 6 Ld TSOT-23 MDP0049
Tape & Reel
ISL88017IHTZ-TK
017Z
1k pcs 6 Ld TSOT-23 MDP0049
Tape & Reel
• Portable/Battery-Powered Equipment
• PDA and Hand-Held PC Devices
ISL88016/17EVAL1Z Evaluation Platform
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN6141 Rev 1.00
August 5, 2015
Page 1 of 8
ISL88016, ISL88017
Functional Block Diagrams
V
DD
RST/MR
PB
VSET1
VSET2
POR
VOLTAGE
SETTING
±
V
DD
V
REF
VSET3
GND
ISL88016
ISL88017
Product Features Table
FUNCTION
ISL88016
ISL88017
Active-Low Reset (RST)
Manual Reset Input (MR)
x
x
x
x
x
1.60V to 2.85V (50mV Increments) Pin-Selectable Voltage Trip Range
2.15V to 4.65V (100mV Increments) Pin-Selectable Voltage Trip Range
Pb-Free Package Option Available
x
x
x
Pin Descriptions
PIN
NAME
FUNCTION
1
V
Supply Voltage and Monitored Input. The V
pin is the IC power supply terminal and also the
monitored input. The voltage at this pin is compared against the programmed voltage trip point, V
DD
DD
.
TP
A reset is first asserted when the device is initially powered up to ensure that the power supply has
stabilized. Thereafter, reset is again asserted whenever V falls below V . The device is designed
DD TH
with hysteresis to help prevent chattering due to noise and is immune to brief power-supply transients.
2
3
4
5
6
GND
VSET1
VSET2
VSET3
RST/MR
Ground.
Voltage Trip Point Select Pins 1, 2 and 3. These inputs are either tied either to GND or V
floating in various combinations to program the falling voltage trip point. See Voltage Trip Point Setting
Table on following page for programming configurations.
or left
DD
Proprietary TwinPin™ technology combines Active-Low Reset Output and Manual Reset Input
Functions into one pin. This dual function pin functions as both the reset output and a manual reset
input. The RST output pin has an integrated 100k pull-up resistor to V
that is pulled to GND (LOW)
DD
< programmed voltage trip point. The MR input is an active-low
when reset is asserted, V
DD
debounced input to which a user can connect a push-button to add manual reset capability.
FN6141 Rev 1.00
August 5, 2015
Page 2 of 8
ISL88016, ISL88017
Power-On Reset Voltage Setting
V
TH
ISL88016
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
Reserved
ISL88017
2.15
2.25
2.35
2.45
2.55
2.65
2.75
2.85
2.95
3.05
3.15
3.25
3.35
3.45
3.55
3.65
3.75
3.85
3.95
4.05
4.15
4.25
4.35
4.45
4.55
4.65
Reserved
VSET1
GND
VSET2
GND
VSET3
GND
FLOAT
GND
GND
V
GND
GND
DD
GND
FLOAT
FLOAT
FLOAT
GND
FLOAT
GND
V
GND
DD
GND
V
V
V
GND
DD
DD
DD
FLOAT
GND
V
GND
DD
GND
GND
GND
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
V
GND
DD
GND
FLOAT
FLOAT
FLOAT
FLOAT
V
DD
GND
V
V
V
DD
DD
DD
FLOAT
V
DD
GND
GND
GND
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
FLOAT
V
GND
DD
GND
FLOAT
FLOAT
FLOAT
FLOAT
V
DD
GND
V
V
V
DD
DD
DD
FLOAT
V
DD
FN6141 Rev 1.00
August 5, 2015
Page 3 of 8
ISL88016, ISL88017
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on Any Pin with Respect to GND . . . . . . . . . . .-1.0V to +7V
D.C. Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C
Temperature Range (Industrial). . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Absolute Maximum Ratings indicate limits beyond which permanent damage to the device and impaired reliability may occur. These are stress ratings
provided for information only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification are not implied.
For guaranteed specifications and test conditions, see Electrical Specifications. The guaranteed specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
Electrical Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
BIAS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage Range
ISL88016 Supply Current
DD > V
1.6
5.5
6
V
DD
I
V
V
V
V
V
V
V
V
= 5.0V
= 3.3V
= 2.5V
= 1.8V
= 5.0V
= 3.3V
= 2.5V
= 2.25V
4.3
3.1
3.1
2.5
4.0
3.2
3.2
3.0
µA
µA
µA
µA
µA
µA
µA
µA
DD
DD
DD
DD
DD
DD
DD
DD
DD
V
TH
4.9
4.5
4.4
8.5
8.5
6.5
5.4
ISL88017 Supply Current
DD > V
V
TH
VOLTAGE THRESHOLD
Voltage Trip Point
V
V
See Power-On Reset Voltage
Setting Table on page 3
-2
+2
%
%
TH
DD
V
Hysteresis at VTH Input
Temperature = +25°C
1
THHYST
RESET
V
ISL88016 Reset Output Voltage Low
ISL88017 Reset Output Voltage Low
Reset Output Voltage High
V
V
V
< V
< V
Sinking 0.225mA
Sinking 0.225mA
0.20
0.20
0.5
0.5
V
V
OL
DD
DD
DD
TH,
TH,
TH
V
V
V
V
OH
DD
t
POR Time-Out Delay
140
200
0.01
5
280
100
1
ms
µs
pF
POR
t
V
Low to Reset Asserted Delay
V
Open
DD
RST
TH
C
Load Capacitance on Reset Pin
LOAD
MANUAL RESET
V
MR Input Voltage
mV
µs
MR
t
MR Minimum Pulse Width
Integrated RST/MR Pull-Up Resistor
10
MR
R
100
k
PU
VSET
I
VSET Current
µA
V
VSET
V
VSET Open Pin Voltage
VSET Input Voltage Low
VSET Input Voltage High
VSET = Open
0.5V
DD
VSET
V
0.1V
V
IL
DD
V
0.9 x V
V
IH
DD
FN6141 Rev 1.00
August 5, 2015
Page 4 of 8
ISL88016, ISL88017
V
V
TH / POR
V
DD
1V
t
t
t
t
POR
POR
RST
POR
RST
MR
>t
MR
FIGURE 1. VOLTAGE MONITORING TIMING DIAGRAM
Principles of Operation
The ISL88016 and ISL88017 devices provides a low cost
solution for those voltage monitoring applications needing
supply voltage supervision with power reset control, and
manual reset assertion. By integrating these common
features along with three pins of Vth programming into a
small 6 Ld TSOT-23 package and using only 1µA of supply
current, the ISL88016 and ISL88017 devices can lower
system cost, reduce board space requirements, and
increase the reliability of a system while reducing inventory
overhead costs.
V
DD
RST/MR
GND
ISL88016
ISL88017
VSET3
VSET2
VSET1
FIGURE 2. SETTING V
USING VSET INPUTS
POR
Power-On Reset (POR)
Applying power to the ISL88016 and ISL88017 activates a
POR circuit which asserts reset once V = 1 V. (i.e., RST
Low Voltage Monitoring
DD
goes LOW). This provides several benefits:
During normal operation, the ISL88016 and ISL88017
monitor the voltage level of V . The device asserts a reset
DD
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
(RST = LOW) if this voltage is less than the programmed
voltage trip point. The reset signal prevents system
operation during a power failure or brownout condition. This
• It prevents the processor from operating prior to
stabilization of the oscillator.
reset signal remains asserted until V
exceeds the voltage
DD
threshold setting for the reset time delay period t
Figure 1).
. (See
POR
• It ensures that the monitored device is held out of
operation until internal registers are properly loaded.
The ISL88016 and ISL88017 allow users to customize the
Power-On Reset voltage threshold level, which is the voltage
at which the reset is deasserted. The three VSET inputs are
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
The reset signal remains asserted until V
rises above the
. This
POR
DD
minimum voltage sense level for time period t
either tied to V , GND or left open to program V . See
DD TH
the Power-On Reset Voltage Setting table on page 3 for
specific voltage configuration. Also see Figure 2 for a
schematic representation of the VSET pins being
programmed, noting the minimum necessary components
ensures that the V
voltage has stabilized.
DD
Optional V
de-coupling capacitance can be added to filter
DD
transients if needed.
for IC operation. Do not attempt to reprogram a V while
TH
the IC is biased.
FN6141 Rev 1.00
August 5, 2015
Page 5 of 8
ISL88016, ISL88017
Manual Reset
The manual reset input (MR) allows the user to trigger a
reset by using a push-button switch. The MR input is an
active low debounced input. By connecting a push-button
directly from MR to ground, the designer adds manual
system reset capability (see Figure 3). Reset is asserted if
the MR pin is pulled low to less than 100mV for 10µs or
longer while the push-button is closed. After MR is released,
the reset outputs remain asserted for t
released.
(200ms) and then
POR
FIGURE 5. ISL88016/17EVAL1Z PHOTOGRAPH
ISL88016
ISL88017
RST/MR
PB
0.1
-0.1
-0.3
-0.5
-0.7
-0.9
-1.1
-1.3
TARGET 0%
88017_3.55V
88017_4.55V
88016_2.80V
88016_2.25V
88017_2.25V
FIGURE 3. CONNECTING A MANUAL RESET PUSH-BUTTON
Using the ISL88016/17EVAL1Z Platform
88016_1.75V
The ISL88016/17EVAL1Z platform is provided with both an
ISL88016 in the top and an ISL88017 in the bottom
-40 -30 -20 -10
0
10 25 35 45 55 65 75 85
positions. Each IC is default programmed to VSET1, VSET2
and VSET3 = FLOAT but provided with jumpers to change
the Vth level by individually connecting the three VSET pins
TEMPERATURE (°C)
FIGURE 6. SAMPLED V % TO TARGET OVER TEMP
TH
to either V
(1) or GND (0). To the left of the circuits is a
DD
VSET programming table for easy reference. Provide
adequate bias to V to deassert RESET signal. See
6.00
5.00
4.00
3.00
2.00
1.00
0.00
V
= 5V
DD
DD
Figure 4 for the ISL88016/17EVAL1Z schematic and
Figure 5 for its photograph.
V
= 2.5V
DD
V
= 1.8V
DD
V
= 3.3V
DD
-40 -30 -20 -10
0
10 25 35 45 55 65 75 85
TEMPERATURE (oC)
FIGURE 7. I
OVER TEMP
DD
204
203
202
201
200
199
198
197
196
195
194
193
V
= 5V
DD
V
= 3.3V
DD
FIGURE 4. ISL88016/17EVAL1Z SCHEMATIC
-40 -30 -20 -10
0
10
25
35
45
55
65
75
85
TEMPERATURE (o C)
FIGURE 8. t
OVER TEMP
POR
FN6141 Rev 1.00
August 5, 2015
Page 6 of 8
ISL88016, ISL88017
Revision History. The revision history provided is for informational purposes only and is believed to be accurate, but not
warranted. Please go to the web to make sure that you have the latest revision.
DATE
REVISION
CHANGE
August 5, 2015
FN6141.1
Updated Ordering Information Table on page 1.
Added Revision History and About Intersil sections.
Updated package outline drawing to latest revision. Changes from Revision A to Revision B are as follows:
Added dimensions (MILLIMETERS) to table.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
FN6141 Rev 1.00
August 5, 2015
Page 7 of 8
ISL88016, ISL88017
TSOT Package Family
MDP0049
TSOT PACKAGE FAMILY
e1
D
A
MILLIMETERS
6
4
N
SYMBOL
TSOT5
1.00
0.05
0.87
0.38
0.127
2.90
2.80
1.60
0.95
1.90
0.40
0.60
0.20
5
TSOT6
1.00
0.05
0.87
0.38
0.127
2.90
2.80
1.60
0.95
1.90
0.40
0.60
0.20
6
TSOT8
1.00
0.05
0.87
0.29
0.127
2.90
2.80
1.60
0.65
1.95
0.40
0.60
0.13
8
TOLERANCE
Max
A
A1
A2
b
±0.05
E1
E
±0.03
2
3
±0.07
0.15
2X
C
D
c
+0.07/-0.007
Basic
1
2
(N/2)
0.25
C
D
5
2X N/2 TIPS
e
E
Basic
E1
e
Basic
ddd
C A-B D
M
B
b
NX
Basic
e1
L
Basic
±0.10
L1
ddd
N
Reference
-
0.15
2X
C A-B
1
3
D
Reference
Rev. B 2/07
C
NOTES:
A2
1. Plastic or metal protrusions of 0.15mm maximum per side are
not included.
SEATING
PLANE
2. Plastic interlead protrusions of 0.15mm maximum per side are
not included.
A1
0.10
NX
C
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(TSOT6 AND TSOT8 only).
(L1)
H
6. TSOT5 version has no center lead (shown as a dashed line).
A
GAUGE
PLANE
0.25
c
L
4° ±4°
© Copyright Intersil Americas LLC 2006-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6141 Rev 1.00
August 5, 2015
Page 8 of 8
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