ISL89166FBECZ-T [RENESAS]
AND GATE BASED MOSFET DRIVER;型号: | ISL89166FBECZ-T |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | AND GATE BASED MOSFET DRIVER 驱动 |
文件: | 总14页 (文件大小:454K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
High Speed, Dual Channel, 6A, Power MOSFET Driver
With Programmable Delays
ISL89166, ISL89167, ISL89168
Features
• Typical ON-resistance <1Ω
• Specified Miller plateau drive currents
The ISL89166, ISL89167, and ISL89168 are high-speed, 6A,
dual channel MOSFET drivers. These parts are similar to the
ISL89160, ISL89161, ISL89162 drivers but use the NC pins for
programming the rising edge time delays of the outputs used for
dead time control.
• Very low thermal impedance (θ = 3°C/W)
JC
• Hysteretic Input logic levels for 3.3V CMOS, 5V CMOS, and TTL
• Precision threshold inputs for optional time delays with
external RC components
As an alternative to using external RC circuits for time delays, the
programmable delays on the RDTA and RDTB pins allows the
user to delay the rising edge of the respective outputs just by
connecting an appropriate resistor value between these pins and
ground. The accuracy and temperature characteristics of the
time delays are specified freeing the user of the need to select
appropriate external resistors and capacitors that traditionally
are applied to the logic inputs to delay the output edges.
• Instead of RC components for time delays, a resistor can be
used to program delays
• 20ns rise and fall time driving a 10nF load.
• NC pins may be connected to ground or VDD for flexible PCB
layout options
At high switching frequencies, these MOSFET drivers use very
little internal bias currents. Separate, non-overlapping drive
circuits are used to drive each CMOS output FET to prevent
shoot-thru currents in the output stage.
Applications
• Synchronous Rectifier (SR) Driver
• Switch mode power supplies
• Motor Drives, Class D amplifiers, UPS, Inverters
• Pulse Transformer Driver
The start-up sequence is design to prevent unexpected glitches
when V is being turned on or turned off. When V < ~1V, an
DD DD
internal 10kΩ resistor between the output and ground helps to
• Clock/Line Driver
keep the output voltage low. When ~1V <V < UV, both outputs
DD
are driven low with very low resistance and the logic inputs are
ignored. This insures that the driven FETs are off. When
V
> UVLO, and after a short delay, the outputs now respond to
DD
the logic inputs.
350
300
VDD
+125°C (WORST CASE)
250
RDTA
RDTB
OUTA
1
2
3
4
8
7
6
5
INA
GND
INB
200
EPAD
150
+25°C (TYPICAL)
OUTB
4.7µF
100
50
-40°C (WORST CASE)
0
0
5
10
15
20
RDT (2k to 20k)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. PROGRAMMABLE TIME DELAYS
February 23, 2012
FN7720.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL89166, ISL89167, ISL89168
Block Diagram
VDD
Separate FET drives, with
The UV comparator holds off
the outputs until VDD ~>
3.3VDC.
non-overlapping outputs,
prevent shoot-thru
currents in the output
CMOS FETs resulting with
very low operating
currents.
For clarity, only one
channel is shown
RDTx
RDTx
ISL89166
rising
INx
edge
delay
OUTx
10k
ISL89167,
ISL89168
EPAD
For proper thermal and electrical
performance, the EPAD must be
connected to the PCB ground plane.
GND
Pin Configurations
Pin Descriptions
PIN
NUMBER
ISL89166FR, ISL89166FB
(8 LD TDFN, EPSOIC)
TOP VIEW
ISL89167FR, ISL89167FB
(8 LD TDFN, EPSOIC)
TOP VIEW
SYMBOL
RDTA
DESCRIPTION
1
Connect a resistor between this pin and
ground to program the rising edge delay of
OUTA, 0k to 20k
RDTA
INA
RDTB
OUTA
VDD
RDTA
/INA
GND
RDTB
OUTA
VDD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
2
3
4
5
6
7
8
INA or /INA Channel A input, 0V to VDD
GND Power Ground, 0V
INB or /INB Channel B enable, 0V to VDD
GND
INB
/INB
OUTB
OUTB
OUTB
VDD
Channel B output
Power input, 4.5V to 16V
Channel A output, 0V to VDD
ISL89168FR, ISL89168FB
(8 LD TDFN, EPSOIC)
TOP VIEW
OUTA
RDTB
Connect a resistor between this pin and
ground to program the rising edge delay of
OUTB, 0k to 20k
RDTA
/INA
GND
INB
RDTB
OUTA
VDD
1
2
3
4
8
7
6
5
EPAD
Power Ground, 0V
OUTB
FN7720.1
February 23, 2012
2
ISL89166, ISL89167, ISL89168
Ordering Information
PART NUMBER
PACKAGE
(Pb-Free)
PKG.
DWG. #
(Notes 1, 2, 3)
PART MARKING
166A
TEMP RANGE (°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
INPUT CONFIGURATION
non-inverting
ISL89166FRTAZ
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld 3x3 TDFN
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
8 Ld EPSOIC
L8.3x3I
ISL89167FRTAZ
ISL89168FRTAZ
ISL89166FRTBZ
ISL89167FRTBZ
ISL89168FRTBZ
ISL89166FRTCZ
ISL89167FRTCZ
ISL89168FRTCZ
ISL89166FBEAZ
ISL89167FBEAZ
ISL89168FBEAZ
ISL89166FBEBZ
ISL89167FBEBZ
ISL89168FBEBZ
ISL89166FBECZ
ISL89167FBECZ
ISL89168FBECZ
NOTES:
167A
inverting
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
L8.3x3I
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
M8.15D
168A
inverting + non-inverting
non-inverting
166B
167B
inverting
168B
inverting + non-inverting
non-inverting
166C
167C
inverting
168C
inverting + non-inverting
non-inverting
89166 FBEAZ
89167 FBEAZ
89168 FBEAZ
89166 FBEBZ
89167 FBEBZ
89168 FBEBZ
89166 FBECZ
89167 FBECZ
89168 FBECZ
inverting
inverting + non-inverting
non-inverting
inverting
inverting + non-inverting
non-inverting
inverting
inverting + non-inverting
1. Add “-T*”, suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL89166, ISL89167, ISL89168. For more information on MSL, please
see Technical Brief TB363.
FN7720.1
February 23, 2012
3
ISL89166, ISL89167, ISL89168
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V Relative to GND. . . . . . . . . . . . . . . . . . . . -0.3V to 18V
Logic Inputs (INA, INB) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to V + 0.3V
DD
Thermal Resistance (Typical)
8 Ld TDFN Package (Notes 4, 5). . . . . . . . .
8 Ld EPSOIC Package (Notes 4, 5). . . . . . .
θ
(°C/W)
44
42
θ
(°C/W)
JC
DD
JA
3
3
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to V + 0.3V
DD
Average Output Current (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA
Max Power Dissipation at +25°C in Free Air . . . . . . . . . . . . . . . . . . . . . 2.27W
Max Power Dissipation at +25°C with Copper Plane . . . . . . . . . . . . .33.3W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temp Range . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . . . 2000V
Machine Model Class B (Tested per JESD22-A115-A) . . . . . . . . . . . . 200V
Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V
Latch-Up
Maximum Recommended Operating
Conditions
(Tested per JESD-78B; Class 2, Level A)
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage, V Relative to GND. . . . . . . . . . . . . . . . . . . . . .4.5V to 16V
DD
Logic Inputs (INA, INB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V
DD
DD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379 for details.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output
currents of this driver are self limiting by transconductance or r
and do not required any external components to minimize the peaks. If the
DS(ON)
output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to less than the specified
absolute maximum.
DC Electrical Specifications
V
= 12V, GND = 0V, No load on OUTA or OUTB, RDTA = RDTB = 0kΩ unless otherwise specified.
DD
Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
T = +25°C
T = -40°C to +125°C
J
J
MIN
MAX
PARAMETERS
POWER SUPPLY
Voltage Range
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
(Note 7)
(Note 7)
UNITS
V
-
-
-
-
-
-
-
4.5
16
V
DD
INx = GND
5
-
-
-
-
mA
mA
V
Quiescent Current
I
DD
DD
INA = INB = 1MHz, square wave
25
UNDERVOLTAGE
-
-
3.3
-
-
-
-
-
-
VDD Undervoltage Lock-out
(Note 9) (Figure 9)
V
INA = INB = True (Note 10)
V
UV
~25
Hysteresis
mV
INPUTs
Input Range for INA, INB
V
-
-
-
-
-
GND
1.12
V
V
V
IN
DD
Logic 0 Threshold
for INA, INB
V
Nominally 37% x 3.3V
Nominally 63% x 3.3V
1.22
1.32
2.18
-
IL
IH
IN
Logic 1 Threshold
for INA, INB
V
C
-
-
2.08
2
-
-
1.98
-
V
Input Capacitance of
INA, INB (Note 8)
pF
FN7720.1
February 23, 2012
4
ISL89166, ISL89167, ISL89168
DC Electrical Specifications
V
= 12V, GND = 0V, No load on OUTA or OUTB, RDTA = RDTB = 0kΩ unless otherwise specified.
DD
Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)
T = +25°C
J
T = -40°C to +125°C
J
MIN
MAX
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
-
TYP
-
MAX
-
(Note 7)
(Note 7)
UNITS
µA
Input Bias Current
for INA, INB
I
GND < V < V
IN
-10
+10
IN
DD
OUTPUTS
High Level Output Voltage
V
V
-
-
-
-
-
-
V
- 0.1
V
DD
V
V
OHA OHB
DD
V
V
OLA
OLB
Low Level Output Voltage
GND
GND + 0.1
Peak Output Source Current
Peak Output Sink Current
NOTES:
I
V
V
(initial) = 0V, C
LOAD
= 10nF
= 10nF
-
-
-6
-
-
-
-
-
-
A
A
O
O
O
I
(initial) = 12V, C
+6
O
LOAD
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
9. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9
10. The true state of a specific part number is defined by the input logic symbol.
AC Electrical Specifications
V
= 12V, GND = 0V, No Load on OUTA or OUTB, RDTA = RDTB = 0kΩ unless Otherwise
DD
Specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
T = +25°C
J
T = -40°C to +125°C
J
TEST CONDITIONS
/NOTES
MIN
(Note 7)
MAX
(Note 7)
PARAMETERS
SYMBOL
MIN
-
TYP
20
MAX
-
UNITS
ns
Output Rise Time (see Figure 4)
t
C
= 10nF,
-
40
R
LOAD
10% to 90%
Output Fall Time (see Figure 4)
t
C
= 10nF,
-
20
-
-
40
ns
F
LOAD
90% to 10%
RDTx = 0kΩ
RDTx = 0kΩ
Output Rising Edge Propagation Delay (see Figure 3)
t
-
-
25
25
-
-
-
-
50
50
ns
ns
RDLY
Output Falling Edge Propagation Delay (see Figure 3)
(Note 12)
t
FDLY
Rising Propagation Matching (see Figure 3)
Falling Propagation Matching (see Figure 3)
Rising edge timer delay (Note 11)
t
RDTx = 0kΩ
RDTx = 0kΩ
-
-
-
<1ns
<1ns
266
-
-
-
-
-
-
-
ns
ns
ns
RM
t
FM
t
RTx = 20kΩ,
237
297
RTDLY20
No load
RTx = 2.0kΩ, No
load
-
-
-
-
42
6
-
-
-
-
29
58
ns
A
t
RTDLY2
Miller Plateau Sink Current
(See Test Circuit Figure 5)
-I
-I
-I
V
V
= 10V,
-
-
-
-
-
-
MP
MP
MP
DD
MILLER
= 5V
= 3V
= 2V
V
V
= 10V,
4.7
3.7
A
DD
MILLER
V
V
= 10V,
A
DD
MILLER
FN7720.1
February 23, 2012
5
ISL89166, ISL89167, ISL89168
AC Electrical Specifications
V
= 12V, GND = 0V, No Load on OUTA or OUTB, RDTA = RDTB = 0kΩ unless Otherwise
DD
Specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)
T = +25°C
J
T = -40°C to +125°C
J
TEST CONDITIONS
/NOTES
MIN
(Note 7)
MAX
(Note 7)
PARAMETERS
Miller Plateau Source Current
SYMBOL
MIN
-
TYP
5.2
MAX
-
UNITS
A
I
I
I
V
V
= 10V,
-
-
-
-
-
-
MP
MP
MP
DD
MILLER
(See Test Circuit Figure 6)
= 5V
= 3V
= 2V
V
V
= 10V,
-
-
5.8
6.9
-
-
A
A
DD
MILLER
V
V
= 10V,
DD
MILLER
NOTE:
11. The rising edge delay timer increases the propagation delay for values of RDTx > 2.0kΩ. Time delays for RDTx < 2.0kΩ and RDTx > 20kΩ are not
specified and are not recommended. The resistors tolerances (including the boundary values of 2.0kΩ and 20.0kΩ) are recommended to be 1% or
better.
12. The falling edge propagation delays are independent of the RDT value.
Test Waveforms and Circuits
3.3V
63%
37%
INA, INB
0V
tRDLY
tFDLY
90%
10%
/OUTA
OUTA
OUTA
OR
tRDLY
tFDLY
OUTB
tR
tF
/OUTB
OUTB
tRM
tFM
FIGURE 3. PROP DELAYS AND MATCHING
FIGURE 4. RISE/FALL TIMES
10V
10V
ISL8916x
ISL8916x
0.1µF
10k
10k
0.1µF
VMILLER
VMILLER
10µF
10µF
200ns
200ns
+ISENSE
+ISENSE
10nF
10nF
50m
50m
-ISENSE
-ISENSE
FIGURE 5. MILLER PLATEAU SINK CURRENT TEST CIRCUIT
FIGURE 6. MILLER PLATEAU SOURCE CURRENT TEST CIRCUIT
FN7720.1
February 23, 2012
6
ISL89166, ISL89167, ISL89168
Test Waveforms and Circuits (Continued)
10V
CURRENT THROUGH
IMP
Ω
0.1 RESISTOR
0A
VMILLER
VOUT
VOUT
VMILLER
-IMP
CURRENT THROUGH
Ω
0.1 RESISTOR
0
0V
200ns
200ns
FIGURE 7. MILLER PLATEAU SINK CURRENT
FIGURE 8. MILLER PLATEAU SOURCE CURRENT
RISING VDD
THIS DURATION IS DEPENDENT ON
RISE TIME OF VDD
3.3V UV THRESHOLD
THIS DURATION IS
INDEPENDENT ON
RISE TIME OF VDD
~1V
10kΩ TO
GROUND
OUTPUTS CONTROLLED
BY LOGICAL INPUTS
OUTA, OUTB
OUTPUT STATE
OUTPUTS
ACTIVE LOW
UP TO 400µs
<1Ω TO GROUND
FIGURE 9. START-UP SEQUENCE
Typical Performance Curves
3.5
35
30
25
20
15
10
5
+125°C
+125°C
+25°C
-40°C
3.0
+25°C
-40°C
2.5
2.0
4
8
12
16
4
8
12
16
V
V
DD
DD
FIGURE 11. I vs V (1MHz)
DD DD
FIGURE 10. I vs V (STATIC)
DD
DD
FN7720.1
February 23, 2012
7
ISL89166, ISL89167, ISL89168
Typical Performance Curves(Continued)
50
40
30
20
10
0
1.1
1.0
16V
V
LOW
HIGH
OUT
NO LOAD
0.9
0.8
0.7
10V
V
OUT
12V
5V
0.6
0.5
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
FREQUENCY (MHz)
-45
-20
5
30
55
80
105
130
TEMPERATURE (°C)
FIGURE 13. r
vs TEMPERATURE
FIGURE 12. I
vs FREQUENCY (+25°C)
DS(ON)
DD
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
25
20
15
FALL TIME, C
= 10nF
LOAD
POSITIVE THRESHOLD
RISE TIME, C
LOAD
= 10nF
NEGATIVE THRESHOLD
-45
-20
5
30
55
80
105
130
-45
-20
5
30
55
80
105
130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 14. INPUT THRESHOLDS
FIGURE 15. OUTPUT RISE/FALL TIME
350
300
250
200
150
100
50
30
25
+125°C (WORST CASE)
OUTPUT FALLING PROP DELAY
OUTPUT RISING PROP DELAY
+25°C (TYPICAL)
20
15
-40°C (WORST CASE)
0
0
5
10
15
20
5
7
9
11
DD
13
15
RDT (2k to 20k)
V
FIGURE 16. PROPAGATION DELAY vs V
FIGURE 17. PROPAGATION DELAY vs RDT
DD
FN7720.1
February 23, 2012
8
ISL89166, ISL89167, ISL89168
Functional Description
D
Overview
INx
OUTx
The ISL89166, ISL89167, ISL89168 drivers incorporate several
features including precision input logic thresholds, undervoltage
lock-out, fast rising high output drive currents and programmable
rising edge output delays.
Rdel
cdel
ISL89160
The programmable delays require only a resistor connecter
between the RDTA or RDTB pins and ground. This is a useful
feature to create dead times for bridge applications to prevent
shoot-through or for synchronous rectifier applications to adjust
the timing.
FIGURE 19. SETTING DELAYS WITH A RCD NETWORK
Paralleling Outputs to Double the Peak Drive
Currents
The typical propagation matching of the ISL89166 and ISL89167
is less than 1ns. Note that the propagation matching is only valid
when RTDA and RTDB = 0kΩ. The matching is so precise that
carefully matched and calibrated scopes probes and scope
channels must be used to make this measurement. Because of
this excellent performance, these driver outputs can be safely
paralleled to double the current drive capacity. It is important
that the INA and INB inputs be connected together on the PCB
with the shortest possible trace. This is also required of OUTA and
OUTB. Note that the ISL89168 cannot be paralleled because of
the complementary logic.
Fast rising (or falling) output drive current of the ISL89166,
ISL89167, ISL89168 minimizes the turn-on (off) delay due to the
input capacitance of the driven FET. The switching transition
period at the Miller plateau is also minimized by the high drive
currents. (See the specified Miller plateau currents in the AC
Electrical Specifications on page 5).
The start-up sequence for is designed to prevent unexpected
glitches when V is being turned on or turned off. When
DD
V
< ~1V, an internal 10kΩ resistor connected between the
DD
output and ground, help to keep the gate voltage close to ground.
When ~1V<V < UV, both outputs are driven low while ignoring
DD
Power Dissipation of the Driver
the logic inputs. This low state has the same current sinking
capacity as during normal operation. This insures that the driven
FETs are held off even if there is a switching voltage on the drains
that can inject charge into the gates via the Miller capacitance.
The power dissipation of the ISL89166, ISL89167, ISL89168 is
dominated by the losses associated with the gate charge of the
driven bridge FETs and the switching frequency. The internal bias
current also contributes to the total dissipation but is usually not
significant as compared to the gate charge losses.
When V > UVLO, and after a 400µs delay, the outputs now
DD
respond to the logic inputs. See Figure 9 for complete details.
For the negative transition of V through the UV lockout voltage,
DD
Figure 20 illustrates how the gate charge varies with the gate
voltage in a typical power MOSFET. In this example, the total gate
the outputs are active low when V < ~3.2V regardless of the
DD DC
input logic states.
charge for V = 10V is 21.5nC when V = 40V. This is the
gs DS
charge that a driver must source to turn-on the MOSFET and
must sink to turn-off the MOSFET.
Application Information
Programming Rising Edge Delays
12
10
As compared to setting the output delays of a driver using an
resistor, capacitor and diode on the logic inputs, programming
the rising edge output delays of the ISL89166, ISL89167,
ISL89168 is almost trivial.
V
= 64V
DS
8
6
4
2
0
V
= 40V
DS
All that is necessary is to select the required resistor value from
the Propagation Delay vs RDT graph, Figure 17. Unlike using an
RCD network, the operating tolerances over temperature are
specified. If a traditional RCD network (Figure 19) is used on the
input logic, then it is necessary to account for the tolerance of the
logic input threshold, the tolerances of R and C, and their
temperature sensitivity.
RDTx
0
2
4
6
8
10 12 14 16 18 20 22 24
GATE CHARGE (nC)
Q
g,
INx
OUTx
FIGURE 20. MOSFET GATE CHARGE vs GATE VOLTAGE
ISL89166
Equation 1 shows calculating the power dissipation of the driver:
R
gate
------------------------------------------
P
= 2 • Q • freq • V
•
+ I (freq) • V
DD
D
c
GS
DD
R
+ r
DS(ON)
FIGURE 18. SETTING DELAYS WITH A RESISTOR
gate
(EQ. 1)
FN7720.1
February 23, 2012
9
ISL89166, ISL89167, ISL89168
Where:
r
= ON-resistance of the driver
DS(ON)
freq = Switching frequency,
R
= External gate resistance (if any).
gate
V
= V bias of the ISL89166, ISL89167, ISL89168
DD
Note that the gate power dissipation is proportionally shared with
the external gate resistor. When sizing an external gate resistor,
do not overlook the power dissipated by this resistor.
GS
Q = Gate charge for V
GS
c
I
(freq) = Bias current at the switching frequency (see Figure 10
DD
on page 7)
Typical Application Circuit
VBRIDGE
ZVS FULL BRIDGE
QUL
QUR
SQR
PWM
LL
VGUL
VGUR
U1A
SQR
L
R
L
ISL89162
T2
T1A
VGLL
VGUL
LR
T1B
½ ISL89166
U1B
½ ISL89166
QLL
QLR
Red dashed lines
emphasize the
resonant switching
delay of the low-side
bridge FETs
VGLL
VGLR
U2A
U2B
LL
LR
VGLR
VGUR
LL: Lower Left
LR: Lower Right
UL: Upper Left
UR: Upper Right
GLL: Gate Lower Left
FN7720.1
February 23, 2012
10
ISL89166, ISL89167, ISL89168
The Typical Application Circuit is an example of how the
that source the input signals to the ISL89166, ISL89167,
ISL89166, ISL89167, ISL89168, MOSFET drivers can be applied
in a zero voltage switching full bridge. Two main signals are
required: a 50% duty cycle square wave (SQR) and a PWM signal
synchronized to the edges of the SQR input. An ISL89162 is used
ISL89168.
• Avoid having a signal ground plane under a high amplitude
dv/dt circuit. This will inject di/dt currents into the signal
ground paths.
to drive T1 with alternating half cycles driving Q and Q . An
UL UR
• Do power dissipation and voltage drop calculations of the
power traces. Many PCB/CAD programs have built in tools for
calculation of trace resistance.
ISL89166 is used to drive Q and Q also with alternating half
LL LR
cycles. Unlike the two high side bridge FETs, the two low-side
bridge FETs are turned on with a rising edge delay. The delay is
setup by resistors connected to RDTA and RDTB pins of the
ISL89166. The duration of the delay is chosen to turn on the
low-side FETs when the voltage on their respective drains is at the
resonant valley.
• Large power components (Power FETs, Electrolytic caps, power
resistors, etc.) will have internal parasitic inductance which
cannot be eliminated.
This must be accounted for in the PCB layout and circuit
design.
General PCB Layout Guidelines
• If you simulate your circuits, consider including parasitic
components especially parasitic inductance.
The AC performance of the ISL89166, ISL89167, ISL89168
depends significantly on the design of the PC board. The
following layout design guidelines are recommended to achieve
optimum performance:
General EPAD Heatsinking
Considerations
• Place the driver as close as possible to the driven power FET.
The thermal pad is electrically connected to the GND supply
through the IC substrate. The epad of the ISL89166, ISL89167,
ISL89168 has two main functions: to provide a quiet GND for the
input threshold comparators and to provide heat sinking for the
IC. The EPAD must be connected to a ground plane and no
switching currents from the driven FET should pass through the
ground plane under the IC.
• Understand where the switching power currents flow. The high
amplitude di/dt currents of the driven power FET will induce
significant voltage transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Use planes where practical; they are usually more effective
than parallel traces.
Figure 21 is a PCB layout example of how to use vias to remove
heat from the IC through the epad.
• Avoid paralleling high amplitude di/dt traces with low level
signal lines. High di/dt will induce currents and consequently,
noise voltages in the low level signal lines.
EPAD GND
PLANE
EPAD GND
PLANE
• When practical, minimize impedances in low level signal
circuits. The noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
• Be aware of magnetic fields emanating from transformers and
inductors. Gaps in these structures are especially bad for
emitting flux.
BOTTOM
LAYER
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines to minimize
coupling.
COMPONENT
LAYER
FIGURE 21. TYPICAL PCB PATTERN FOR THERMAL VIAS
• The use of low inductance components such as chip resistors
and chip capacitors is highly recommended.
For maximum heatsinking, it is recommended that a ground
plane, connected to the EPAD, be added to both sides of the PCB.
A via array, within the area of the EPAD, will conduct heat from
the EPAD to the GND plane on the bottom layer. The number of
vias and the size of the GND planes required for adequate
heatsinking is determined by the power dissipated by the
ISL89166, ISL89167, ISL89168, the air flow and the maximum
temperature of the air around the IC.
• Use decoupling capacitors to reduce the influence of parasitic
inductance in the VDD and GND leads. To be effective, these
caps must also have the shortest possible conduction paths. If
vias are used, connect several paralleled vias to reduce the
inductance of the vias.
• It may be necessary to add resistance to dampen resonating
parasitic circuits especially on OUTA and OUTB. If an external
gate resistor is unacceptable, then the layout must be
improved to minimize lead inductance.
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for control circuits
FN7720.1
February 23, 2012
11
ISL89166, ISL89167, ISL89168
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN7720.1
FN7720.0
CHANGE
(page 1) Figure 1 illustration improved.
(page 1) Last paragraph of the product description is changed to better describe the improved turn on
characteristics.
(page 1) Features list is revised to improve readability and to add new product specific features.
(page 3) Updated Ordering information with new parts.
(page 4) Abs Max Ratings ESD Ratings Charged Device Model changed from "1000" to "1500"
(page 4) Note and figure references are added to the VDD Under-voltage lock-out parameter.
(page 5) Note 9 is revised to more clearly describe the turn-on characteristics. Changed "200us" to "400us"
(page 6) Wording of Note 11 is revised to correctly label the RDT resistors.
(page 7) Figure 9 added to clearly define the startup characteristics.
(page 9) The paragraphs of the Functional Description Overview describing the turn-on sequence is replaced by
3 paragraphs to more clearly describe the under voltage and turn-on and turn-off characteristics.
(page 9) A new section is added to the application information describing how the drivers outputs can be
paralleled.
January 31, 2012
(pages 1..12) Various minor corrections to text for grammar and spelling.
M8.15D POD on page 14 - Converted to new POD format. Removed table of dimensions and moved dimensions
onto drawing. Added land pattern.
January 14, 2011
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL89166, ISL89167, ISL89168.
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7720.1
February 23, 2012
12
ISL89166, ISL89167, ISL89168
Package Outline Drawing
L8.3x3I
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1 6/09
2X 1.950
3.00
A
6X 0.65
B
5
8
(4X)
0.15
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
4
1
4
8X 0.30
0.10 M C A B
8X 0.400 ± 0.10
TOP VIEW
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
C
0.10
C
Max 0.80
0.08
C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
5
C
0 . 2 REF
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7720.1
February 23, 2012
13
ISL89166, ISL89167, ISL89168
Package Outline Drawing
M8.15D
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD PLASTIC PACKAGE
Rev 1, 3/11
8
INDEX
AREA
6.20 (0.244)
5.84 (0.230)
DETAIL "A"
1.27 (0.050)
0.41 (0.016)
3.99 (0.157)
3.81 (0.150)
0.50 (0.02)
x 45°
1
2
3
0.25 (0.01)
TOP VIEW
8°
0°
0.25 (0.010)
0.19 (0.008)
SEATING PLANE
SIDE VIEW “B”
1.72 (0.067)
4.98 (0.196)
4.80 (0.189)
1.52 (0.059)
-C-
2.25
(0.089)
1.95
(0.077)
0.25 (0.010)
0.10 (0.004)
1.27 (0.050)
1
2
3
4
8
0.46 (0.019)
0.36 (0.014)
0.60 (0.023)
1.27 (0.050)
7
6
5
SIDE VIEW “A
1
2
3
5.45 (0.214)
2.50 (0.099)
2.00 (0.078)
TYPICAL RECOMMENDED LAND PATTERN
8
NOTES:
1. Dimensions are in millimeters. Dimensions in ( ) for reference only.
2. Dimensioning and tolerancing per ASME-Y14.5M-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05.
3.50 (0.137)
3.00 (0.118)
4. Dimension does not include interlead flash or protrusions. Interlead flash
or protrusions shall not exceed 0.25mm per side.
5. The Pin 1 identifier may be either a mold or a mark feature.
6. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
BOTTOM VIEW
FN7720.1
February 23, 2012
14
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