ISL89401 [RENESAS]
100V, 1.25A Peak, High Frequency Half-Bridge Drivers;
| 型号： | ISL89401 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 100V, 1.25A Peak, High Frequency Half-Bridge Drivers |
| 文件： | 总12页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL89400, ISL89401
100V, 1.25A Peak, High Frequency Half-Bridge Drivers
FN6614
Rev 3.00
December 4, 2015
The ISL89400, ISL89401 are 100V, high frequency, half-bridge
N-Channel power MOSFET driver ICs. They are based on the
popular HIP2100, HIP2101 half-bridge drivers, but offer
several performance improvements. The ISL89400 has
additional input hysteresis for superior operation in noisy
environments and the inputs of the ISL89401 (like those of the
Features
• Drives N-channel MOSFET half-bridge
• Space saving DFN package
• DFN package compliant with 100V conductor spacing
guidelines per IPC-2221
ISL89400) can now safely swing to the V supply rail. Finally,
DD
• Pb-free (RoHS compliant)
both parts are available in a very compact 9 Ld DFN package
and an 8 Ld SOIC to minimize the required PCB footprint.
• Bootstrap supply maximum voltage to 114VDC
• On-chip 1Ω bootstrap diode
Applications
• Fast propagation times for multi-MHz circuits
• Drives 1nF load with typical rise/fall times of 16ns
• CMOS compatible input thresholds (ISL89400)
• 3.3V/TTL compatible input thresholds (ISL89401)
• Independent inputs provide flexibility
• No start-up problems
• Telecom half-bridge converters
• Telecom full-bridge converters
• Two-switch forward converters
• Active-clamp forward converters
• Class-D audio amplifiers
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
• Outputs unaffected by supply glitches, HS ringing below
ground or HS slewing at high dV/dt
PART NUMBER
ISL89400
INPUT THRESHOLDS
CMOS Compatible
• Low power consumption
• Wide supply voltage range (9V to 14V)
• Supply undervoltage protection
ISL89401
3.3V/TTL Compatible
• 4.0Ω typical output pull-up/pull-down resistance
Application Block Diagram
+12V
+100V
SECONDARY
CIRCUIT
V
DD
HB
DRIVE
HI
HO
HS
LO
HI
LI
PWM
CONTROLLER
DRIVE
LO
ISL89400
ISL89401
REFERENCE
AND
ISOLATION
V
SS
FIGURE 1. APPLICATION BLOCK DIAGRAM
FN6614 Rev 3.00
December 4, 2015
Page 1 of 12
ISL89400, ISL89401
Ordering Information
PART NUMBER
(Notes 3, 4)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL89400AR3Z (Note 1)
ISL89401AR3Z (Note 1)
ISL89400ABZ (Note 2)
ISL89401ABZ (Note 2)
NOTES:
9400
9401
-40 to +125
-40 to +125
-40 to +125
-40 to +125
9 Ld 3x3 DFN
L9.3x3
9 Ld 3x3 DFN
8 Ld SOIC
L9.3x3
M8.15
M8.15
89400 ABZ
89401 ABZ
8 Ld SOIC
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Add “-T” suffix for 2.5k unit or add “-TK” suffix for 1k unit tape and reel. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for ISL89400, ISL89401. For more information on MSL, please see tech
brief TB363.
Pin Configurations
ISL89400, ISL89401
(8 LD SOIC)
ISL89400, ISL89401
(9 LD DFN)
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
LO
V
V
DD
V
LO
1
9
8
7
6
5
DD
HB
HO
HS
SS
V
SS
LI
2
3
4
EPAD
HB
HO
HS
LI
HI
HI
NC
NOTE: EPAD = Exposed PAD.
Pin Descriptions
SYMBOL
DESCRIPTION
V
Positive supply to lower gate driver. Bypass this pin to V .
SS
DD
HB
High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap
diode is on-chip.
HO
HS
HI
High-side output. Connect to gate of high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
High-side input.
LI
Low-side input.
V
Chip negative supply, which will generally be ground.
Low-side output. Connect to gate of low-side power MOSFET.
No connect.
SS
LO
NC
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
FN6614 Rev 3.00
December 4, 2015
Page 2 of 12
ISL89400, ISL89401
Functional Block Diagram
HB
HO
V
DD
HI
UNDERVOLTAGE
LEVEL SHIFT
DRIVER
HS
ISL89401
UNDERVOLTAGE
ISL89401
LO
DRIVER
LI
V
SS
EPAD (DFN PACKAGE ONLY)
*EPAD = EXPOSED PAD. THE EPAD IS ELECTRICALLY ISOLATED FROM ALL OTHER
PINS. FOR BEST THERMAL PERFORMANCE, CONNECT THE EPAD TO THE PCB
POWER GROUND PLANE.
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
FN6614 Rev 3.00
December 4, 2015
Page 3 of 12
ISL89400, ISL89401
+48V
+12V
SECONDARY
CIRCUIT
ISL89400
ISL89401
PWM
ISOLATION
FIGURE 3. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
ISL89400
ISL89401
PWM
ISOLATION
FIGURE 4. FORWARD CONVERTER WITH AN ACTIVE-CLAMP
FN6614 Rev 3.00
December 4, 2015
Page 4 of 12
ISL89400, ISL89401
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
(Note 6). . . . . . . . . . . . . . . . . . -0.3V to 18V
Thermal Resistance (Typical)
9 Ld DFN (Notes 7, 9). . . . . . . . . . . . . . . . . .
8 Ld SOIC (Note 8, 10) . . . . . . . . . . . . . . . . .
(°C/W)
55
107
(°C/W)
3.5
50
DD, VHB - VHS
JA
JC
LI and HI Voltages (Note 6) . . . . . . . . . . . . . . . . . . . . . . -0.3V to V + 0.3V
Voltage on LO (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V + 0.3V
DD
DD
Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . V - 0.3V to V + 0.3V
Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in V to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
DD
Max Power Dissipation at +25°C in Free Air (Note 7). . . . . . . . . . . . . . 2.27W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link TB493
HS
HB
Maximum Recommended Operating
Conditions
Supply Voltage, V (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 14V
DD
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . . . . . . . V + 8V to V + 14V and V - 1V to V + 100V
HS HS DD DD
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. The ISL89400 and ISL89401 are capable of derated operation at supply voltages exceeding 14V. Figure 24 shows the high-side voltage derating curve
for this mode of operation.
6. All voltages referenced to V , unless otherwise specified.
SS
7. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.See Tech
JA
Brief TB379.
8. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
9. For the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
JC,
10. For , the “case temp” location is taken at the package top center.
JC
Electrical Specifications
V
= V = 12V, V = V = 0V, No Load on LO or HO, unless otherwise specified. Parameters with MIN
HB SS HS
DD
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits at –40°C and +125°C are established by characterization
and are not production tested.
T = +25°C
J
T = -40°C to +125°C
J
PARAMETERS
SUPPLY CURRENTS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNIT
V
V
V
V
Quiescent Current
I
I
ISL89400; LI = HI = 0V
ISL89401; LI = HI = 0V
ISL89400; f = 500kHz
ISL89401; f = 500kHz
LI = HI = 0V
-
-
-
-
-
-
-
-
0.1
0.3
1.6
1.9
0.1
2.0
0.05
0.9
0.25
0.45
2.2
2.5
0.15
2.5
1
-
-
-
-
-
-
-
-
0.3
0.55
2.7
3
mA
mA
mA
mA
mA
mA
µA
DD
DD
DD
DD
DD
Quiescent Current
Operating Current
Operating Current
DD
I
I
DDO
DDO
Total HB Quiescent Current
Total HB Operating Current
I
0.2
3
HB
I
f = 500kHz
HBO
HB to V Current, Quiescent
SS
I
LI = HI = 0V; V = V = 114V
HB HS
10
-
HBS
HB to V Current, Operating
SS
I
f = 500kHz; V = V = 114V
HB HS
-
mA
HBSO
INPUT PINS
Low Level Input Voltage Threshold
Low Level Input Voltage Threshold
High Level Input Voltage Threshold
High Level Input Voltage Threshold
Input Voltage Hysteresis
V
V
ISL89400
ISL89401
ISL89400
ISL89401
ISL89400
3.7
4.4
1.8
6.6
1.8
2.2
210
-
2.7
-
-
V
V
IL
1.4
-
7.4
2.2
-
1.2
IL
V
V
-
-
-
-
-
8.4
2.4
-
V
IH
-
-
V
IH
V
V
IHYS
Input Pull-Down Resistance
R
-
100
500
kΩ
I
FN6614 Rev 3.00
December 4, 2015
Page 5 of 12
ISL89400, ISL89401
Electrical Specifications
V
= V = 12V, V = V = 0V, No Load on LO or HO, unless otherwise specified. Parameters with MIN
HB SS HS
DD
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits at –40°C and +125°C are established by characterization
and are not production tested. (Continued)
T = +25°C
J
T = -40°C to +125°C
J
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNIT
UNDERVOLTAGE PROTECTION
V
V
Rising Threshold
6.8
7.3
0.6
6.9
0.6
7.8
6.5
8.1
V
V
V
V
DD
DD
VDDR
VDDH
VHBR
VHBH
Threshold Hysteresis
-
6.2
-
-
7.5
-
-
5.9
-
-
7.8
-
HB Rising Threshold
HB Threshold Hysteresis
BOOTSTRAP DIODE
Low Current Forward Voltage
High Current Forward Voltage
Dynamic Resistance
V
I
I
I
= 100µA
= 100mA
= 100mA
-
-
-
0.5
0.7
0.8
0.6
0.9
1
-
-
-
0.7
1
V
V
DL
VDD-HB
VDD-HB
VDD-HB
V
DH
R
1.5
Ω
D
LO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
V
I
I
= 100mA
-
-
-
-
0.4
0.4
0.5
-
-
-
-
0.7
V
V
A
A
OLL
OHL
OHL
LO
LO
V
= -100mA, V
OHL
= V - V
DD LO
0.5
0.7
I
V
V
= 0V
1.25
1.25
-
-
-
-
LO
LO
Peak Pull-Down Current
HO GATE DRIVER
I
= 12V
OLL
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
V
I
= 100mA
-
-
-
-
0.4
0.4
0.5
-
-
-
-
0.7
V
V
A
A
OLH
OHH
OHH
HO
V
I
= -100mA, V
= V - V
0.5
0.7
HO
OHH HB HO
I
V
= 0V
1.25
1.25
-
-
-
-
HO
HO
Peak Pull-Down Current
I
V
= 12V
OLH
Switching Specifications
V
= V = 12V, V = V = 0V, No Load on LO or HO, unless otherwise specified. Parameters with MIN
HB SS HS
DD
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits at –40°C and +125°C are established by characterization
and are not production tested.
T = +25°C
T = -40°C to +125°C
J
J
TEST
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP MAX
MIN
MAX
60
60
60
60
16
16
-
UNIT
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
Delay Matching: Upper Turn-Off to Lower Turn-On
Delay Matching: Lower Turn-Off to Upper Turn-On
Either Output Rise/Fall Time (10% to 90%/90% to 10%)
Either Output Rise/Fall Time (3V to 9V/9V to 3V)
Minimum Input Pulse Width that Changes the Output
Bootstrap Diode Turn-On or Turn-Off Time
t
-
-
34
31
39
39
8
50
-
-
-
-
-
-
-
-
-
-
LPHL
t
50
HPHL
t
-
50
LPLH
t
-
50
HPLH
t
1
1
-
-
MON
t
6
-
MOFF
t
t
C = 1nF
16
0.8
-
-
RC, FC
L
t
t
C = 0.1µF
-
1.0
1.2
50
-
R, F
L
t
-
-
-
PW
t
-
10
BS
FN6614 Rev 3.00
December 4, 2015
Page 6 of 12
ISL89400, ISL89401
Timing Diagrams
LI
HI
HI,
LI
t
t
,
t
t
,
HPLH
HPHL
LPHL
LO
HO
LPLH
t
t
MOFF
MON
HO,
LO
FIGURE 5. PROPAGATION DELAYS
FIGURE 6. DELAY MATCHING
Typical Performance Curves
10.0
10.0
T = -40°C
T = -40°C
T = +25°C
T = +25°C
T = +125°C
1.0
1.0
T = +125°C
T = +150°C
T = +150°C
0.1
0.1
10k
100k
1M
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. ISL89400 I OPERATING CURRENT vs FREQUENCY
DD
FIGURE 8. ISL89401 I OPERATING CURRENT vs FREQUENCY
DD
10.00
10.00
T = +125°C
T = -40°C
1.00
1.00
T = +25°C
T = +150°C
0.10
0.10
T = -40°C
T = +150°C
T = +125°C
T = +25°C
0.01
0.01
10k
100k
1M
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. I OPERATING CURRENT vs FREQUENCY
HB
FIGURE 10. I
OPERATING CURRENT vs FREQUENCY
HBS
FN6614 Rev 3.00
December 4, 2015
Page 7 of 12
ISL89400, ISL89401
Typical Performance Curves (Continued)
450
400
350
300
250
200
150
500
V
= V
= 9V
HB
DD
V
= V = 9V
HB
DD
450
400
350
300
250
200
150
V
= V
= 12V
V
= V = 12V
HB
DD
HB
DD
V
= V = 14V
HB
V
= V
= 14V
HB
DD
DD
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 11. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 12. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
0.60
7.6
V
DDR
V
HBH
0.55
0.50
0.45
0.40
7.4
7.2
7.0
6.8
V
HBR
V
DDH
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 13. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
FIGURE 14. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
55
55
t
LPLH
t
LPLH
50
45
40
35
30
25
20
50
45
40
35
30
25
20
t
HPLH
t
HPLH
t
LPHL
t
LPHL
t
HPHL
t
HPHL
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 15. ISL89400 PROPAGATION DELAYS vs TEMPERATURE
FIGURE 16. ISL89401 PROPAGATION DELAYS vs TEMPERATURE
FN6614 Rev 3.00
December 4, 2015
Page 8 of 12
ISL89400, ISL89401
Typical Performance Curves (Continued)
10
10
9
9
t
MOFF
8
8
7
6
5
4
3
t
MON
7
6
5
4
3
t
t
MON
100
MOFF
2
-50
0
50
TEMPERATURE (°C)
150
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 17. ISL89400 DELAY MATCHING vs TEMPERATURE
FIGURE 18. ISL89401 DELAY MATCHING vs TEMPERATURE
1.25
1.00
0.75
0.50
0.25
0
1.25
1.00
0.75
0.50
0.25
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
V
, V (V)
LO HO
V
, V (V)
LO HO
FIGURE 19. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
FIGURE 20. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE
260
240
220
200
180
160
140
120
100
80
340
320
300
280
260
240
220
200
180
160
140
120
100
80
I
DD
I
DD
I
I
HB
HB
60
40
20
0
60
40
20
0
0
5
10
, V
15
20
0
5
10
, V
15
20
V
(V)
V
(V)
DD HB
DD HB
FIGURE 21. ISL89400 QUIESCENT CURRENT vs VOLTAGE
FIGURE 22. ISL89401 QUIESCENT CURRENT vs VOLTAGE
FN6614 Rev 3.00
December 4, 2015
Page 9 of 12
ISL89400, ISL89401
Typical Performance Curves (Continued)
120
100
80
60
40
20
0
1.00
0.10
0.01
.
-3
-4
-5
-6
1 10
.
1 10
.
1 10
.
1 10
12
13
14
15
16
0.3
0.4
0.5
0.6
0.7
0.8
V
to V
SS
VOLTAGE (V
)
DD
FORWARD VOLTAGE (V)
FIGURE 23. BOOTSTRAP DIODE I-V CHARACTERISTICS
FIGURE 24. V VOLTAGE vs V VOLTAGE
HS DD
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN6614.3
CHANGE
December 4, 2015
Updated datasheet to the latest Intersil standards.
Moved Note 5 from “Absolute Maximum Ratings” section to “Maximum Recommended Operating
Conditions”section.
Updated Theta JC on page 5 for DFN from “7.5” to “3.5”.
Added Theta JC on page 5 for SOIC.
Updated Theta JA on page 5 for SOIC from “115” to “107”.
Added Note 10 on page 5.
Updated last sentence in the “Electrical Specifications” table title area.
Added more verbiage to “Switching Specifications” table title area.
Added Revision History and About Intersil sections
Updated package outline drawings to the latest revisions. Changes are as follows:
M8.15
-Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern
-Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
-Changed Note 1 “1982” to “1994”
L9.3x3
-Tiebar Note 9 added: Tiebar shown (if present) is a non-functional feature and may be located on any of the
4 sides (or ends).
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
FN6614 Rev 3.00
December 4, 2015
Page 10 of 12
ISL89400, ISL89401
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6614 Rev 3.00
December 4, 2015
Page 11 of 12
ISL89400, ISL89401
Dual Flat No-Lead Plastic Package (DFN)
2X
L9.3x3
0.15 C
A
9 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
A
D
2X
MILLIMETERS
0.15
C B
SYMBOL
MIN
0.80
NOMINAL
0.90
MAX
1.00
NOTES
A
A1
A3
b
-
-
0.20
1.85
0.80
-
0.05
-
E
0.20 REF
0.25
-
5
INDEX
AREA
0.30
2.10
1.05
4, 7
D
3.00 BSC
2.00
-
TOP VIEW
B
A
D2
E
6, 7
3.00 BSC
0.95
-
// 0.10
0.08
C
E2
e
6, 7
0.50 BSC
-
-
C
k
0.60
0.25
-
-
A3
C
SIDE VIEW
L
0.35
0.45
7
SEATING
PLANE
N
9
2
D2
D2/2
2
6
7
Rev. 1 3/15
(DATUM B)
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
1
5
INDEX
AREA
3. All dimensions are in millimeters. Angles are in degrees.
NX k
E2
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
(DATUM A)
E2/2
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
6. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
N
N-1
NX b
4
7
e
7. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
(Nd-1)Xe
REF.
M
0.10
C A B
8. Compliant toJEDECMO-229-WEED-3exceptfordimensionsE2
& D2.
BOTTOM VIEW
9. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
C
L
(A1)
NX (b)
L
8
4
e
SECTION "C-C"
TERMINAL TIP
FOR ODD TERMINAL/SIDE
C C
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6614 Rev 3.00
December 4, 2015
Page 12 of 12
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