ISL9000AMRNCEP-TK [RENESAS]

ISL9000AMRNCEP-TK;


型号：	ISL9000AMRNCEP-TK
厂家：	RENESAS TECHNOLOGY CORP
描述：	ISL9000AMRNCEP-TK
文件：	总2页 (文件大小：66K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL9000AM

Data Sheet

November 11, 2011

FN6620.1

Dual LDO with Low Noise, Very High

Features

PSRR and Low I

• Integrates Two 100mA High Performance LDO’s

• I per Channel is 50mA at T = +150°C

ISL9000AMRNCP is a high performance dual LDO capable

of sourcing 100mA current from each output. It has a low

standby current and very high PSRR and is stable with

output capacitance of 1µF to 10µF with ESR of up to 200mΩ.

OUT

• Excellent Transient Response to Large Current Steps

• ±1.8% Accuracy Over all Operating Conditions

The device integrates an individual Power-On-Reset (POR)

function for each output. The POR delay for VO2 can be

externally programmed by connecting a timing capacitor to

the CPOR pin. The POR delay for VO1 is internally fixed at

approximately 2ms. A reference bypass pin is also provided

for connecting a noise filtering capacitor for low noise and

high-PSRR applications.

• Excellent Load Regulation:

< 0.1% Voltage Change Across Full Range of Load

Current

• Low Output Noise: Typically 30µV

• Very High PSRR: 90dB @ 1kHz

@ 100µA (1.5V)

rms

• Extremely Low Quiescent Current: 42µA (both LDOs

active)

The quiescent current is typically only 42µA with both LDO’s

enabled and active. Separate enable pins control each

individual LDO output. When both enable pins are low, the

device is in shutdown, typically drawing less than 0.1µA.

• Wide Input Voltage Capability: 2.3V to 5.5V

• Low Dropout Voltage: Typically 200mV @ 100mA

• Stable with 1µF to 10µF Ceramic Capacitors

• Separate Enable and POR Pins for Each LDO

Output voltage for the LDO are VOUT1 = 3.3V and

VOUT2 = 1.8V.

• Soft-Start and Staged Turn-On to Limit Input Current

Surge During Enable

Device Information

The specifications for an Enhanced Product (EP) device are

defined in a Vendor Item Drawing (VID), which is controlled

by the Defense Logistics Agency (DLA). “Hot-links” to the

applicable VID and other supporting application information

are provided on our website.

• Current Limit and Overheat Protection

• Tiny 10 Ld 3x3mm DFN Package

• -55°C to +125°C Operating Temperature Range

Applications

Pinout

• PDAs, Cell Phones and Smart Phones

• Portable Instruments, MP3 Players

• Handheld Devices including Medical Handheld

ISL9000AMNCEP

(10 LD 3X3 DFN)

TOP VIEW

VO1

VO2

VIN

EN1

EN2

POR2

POR1

GND

CBYP

CPOR

Ordering Information

VENDOR PART

VO1

VO2

NUMBER

VENDOR ITEM

PART

VOLTAGE VOLTAGE TEMP RANGE

PKG

(Notes 1, 2)

DRAWING

MARKING

(V)

(°C)

PACKAGE

DWG. #

ISL9000AMRNCEP

NOTES:

V62/08609-01XB

DKTA

3.3

1.8

-55 to +125

10 Ld 3x3 DFN L10.3x3C

1. Add -T to part number for tape and reel.

2. Devices must be procured to the VENDOR PART NUMBER.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL9000AM

Dual Flat No-Lead Plastic Package (DFN)

L10.3x3C

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

0.10 C

MILLIMETERS

SYMBOL

MIN

0.85

NOMINAL

0.90

MAX

0.95

0.05

NOTES

0.10

C B

0.20 REF

0.25

0.20

2.33

1.59

0.30

2.43

1.69

5, 8

INDEX

AREA

3.00 BSC

2.38

7, 8

TOP VIEW

3.00 BSC

1.64

7, 8

// 0.10

0.08

0.50 BSC

0.20

0.35

0.40

0.45

SIDE VIEW

SEATING

PLANE

D2/2

Rev. 1 4/06

(DATUM B)

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

INDEX

AREA

NX k

3. Nd refers to the number of terminals on D.

(DATUM A)

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

E2/2

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

NX L

N-1

NX b

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

(Nd-1)Xe

REF.

0.10

C A B

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

BOTTOM VIEW

9. COMPLIANT TO JEDEC MO-229-WEED-3 except for

dimensions E2 & D2.

(A1)

NX (b)

SECTION "C-C"

TERMINAL TIP

C C

FOR ODD TERMINAL/SIDE

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6620.1

ISL9000AMRNCEP-TK [RENESAS]

相关型号：

ISL9000IRBBZ

ISL9000IRBBZ

ISL9000IRBBZ-T

ISL9000IRBCZ

ISL9000IRBCZ

ISL9000IRBCZ-T

ISL9000IRBJZ

ISL9000IRBJZ-T

ISL9000IRBLZ

ISL9000IRBLZ-T

ISL9000IRCCZ

ISL9000IRCJZ