ISL9012IRNNZ-T [RENESAS]
Dual LDO with Low Noise, Low IQ, and High PSRR; DFN10; Temp Range: -40° to 85°C;
| 型号： | ISL9012IRNNZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual LDO with Low Noise, Low IQ, and High PSRR; DFN10; Temp Range: -40° to 85°C 光电二极管 输出元件 调节器 |
| 文件： | 总12页 (文件大小：643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL9012
FN9220
Rev 4.00
December 10, 2015
Dual LDO with Low Noise, Low I , and High PSRR
Q
ISL9012 is a high performance dual LDO capable of
sourcing 150mA current from Channel 1, and 300mA from
Channel 2. The device has a low standby current and
high-PSRR and is stable with output capacitance of 1µF to
10µF with ESR of up to 200m.
Features
• Integrates two high performance LDOs
- VO1 - 150mA output
- VO2 - 300mA output
• Excellent transient response to large current steps
The device integrates a Power-On-Reset (POR) function for
the VO2 output. The POR delay for VO2 can be externally
programmed by connecting a timing capacitor to the CPOR
pin. A reference bypass pin is also provided for connecting a
noise-filtering capacitor for low noise and high PSRR
applications.
• Excellent load regulation:
1% voltage change across full range of load current
• High PSRR: 70dB @ 1kHz
• Wide input voltage capability: 2.3V to 6.5V
• Extremely low quiescent current: 45µA (both LDOs on)
• Low dropout voltage: typically 120mV @ 150mA
The quiescent current is typically only 45µA with both LDO’s
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.1µA.
• Low output noise: typically 30µV
@ 100µA (1.5V)
RMS
• Stable with 1 to10µF ceramic capacitors
• Separate enable pins for each LDO
Several combinations of voltage outputs are standard.
Output voltage options for each LDO range from 1.5V to
3.3V. Other output voltage options are available on request.
• POR output, with adjustable delay time indicates when the
VO2 output is good
Pinout
• Soft-start to limit input current surge during enable
• Current limit and overheat protection
• ±1.8% accuracy over all operating conditions
• Tiny 10 Ld 3x3mm DFN package
ISL9012
(10 LD 3X3 DFN)
TOP VIEW
VIN
EN1
VO1
VO2
POR
NC
1
2
3
4
5
10
9
• -40°C to +85°C operating temperature range
• Pin compatible with Micrel MIC2212
• Pb-free (RoHS compliant)
EN2
8
CBYP
CPOR
7
GND
6
Applications
• PDAs, Cell Phones and Smart Phones
• Portable Instruments, MP3 Players
• Handheld Devices including Medical Handhelds
FN9220 Rev 4.00
Page 1 of 12
December 10, 2015
ISL9012
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
VO1 VOLTAGE VO2 VOLTAGE
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PART MARKING
(V)
3.3
3.3
(V)
3.3
2.8
PKG. DWG. #
L10.3x3C
ISL9012IRNNZ
DCTA
DAPA
-40 to +85
-40 to +85
10 Ld 3x3 DFN
10 Ld 3x3 DFN
ISL9012IRNJZ (No
longer available,
recommended
replacement:
L10.3x3C
ISL9000AIRNJZ)
ISL9012IRNFZ (No
longer available,
recommended
replacement:
DARA
DCYA
3.3
2.5
-40 to +85
10 Ld 3x3 DFN
L10.3x3C
ISL9000AIRNFZ)
ISL9012IRMNZ
3.0
3.0
3.3
3.0
-40 to +85
-40 to +85
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3C
L10.3x3C
ISL9012IRMMZ (No DAAK
longer available,
recommended
replacement:
ISL9000AIRMGZ-T)
ISL9012IRMGZ
ISL9012IRJNZ
DCBC
DCBD
DAAH
3.0
2.8
2.8
2.7
3.3
3.0
-40 to +85
-40 to +85
-40 to +85
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3C
L10.3x3C
L10.3x3C
ISL9012IRJMZ (No
longer available,
recommended
replacement:
ISL9000AIRJBZ-T)
ISL9012IRJRZ (No
longer available,
recommended
replacement:
ISL9000AIRJNZ-T)
DAAG
DAAF
2.8
2.8
2.6
1.8
-40 to +85
-40 to +85
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3C
L10.3x3C
ISL9012IRJCZ (No
longer available,
recommended
replacement:
ISL9000AIRJBZ-T)
ISL9012IRFDZ
ISL9012IRFCZ
ISL9012IRCJZ
ISL9012IRCCZ
NOTES:
DCBK
DCBL
DCBN
DCBP
2.5
2.5
1.8
1.8
2.0
2.0
2.8
1.8
-40 to +85
-40 to +85
-40 to +85
-40 to +85
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3C
L10.3x3C
L10.3x3C
L10.3x3C
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
FN9220 Rev 4.00
December 10, 2015
Page 2 of 12
ISL9012
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V
Thermal Resistance (Notes 4, 5)
(°C/W)
50
(°C/W)
10
JA
JC
V
V
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
O1, O2
3x3 DFN Package . . . . . . . . . . . . . . . .
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V + 0.3)V
IN
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (T ) . . . . . . . . . . . . . . .-40°C to +85°C
A
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
5. , “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
JC
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
T
= -40°C to +85°C; V = (V + 0.5V) to 6.5V with a minimum V of 2.3V; C = 1µF; C = 1µF;
A
IN
O
IN
IN
O
C
= 0.01µF; C
POR
= 0.01µF
BYP
MIN
MAX
PARAMETER
DC CHARACTERISTICS
Supply Voltage
SYMBOL
TEST CONDITIONS
(Note 8) TYP (Note 8) UNITS
V
2.3
6.5
V
IN
Ground Current
Quiescent condition: I = 0µA; I = 0µA
O1 O2
I
One LDO active
Both LDO active
@+25°C
25
45
40
60
µA
µA
µA
V
DD1
DD2
DDS
I
Shutdown Current
UVLO Threshold
I
0.1
2.1
1.8
1.0
2.3
2.0
+1.8
V
1.9
1.6
UV+
V
V
UV-
Regulation Voltage Accuracy
Variation from nominal voltage output, V = V + 0.5 to 5.5V,
IN
-1.8
%
O
T = -40°C to +125°C
J
Line Regulation
Load Regulation
V
= (V
+ 1.0V relative to highest output voltage) to 5.5V
OUT
-0.2
0
0.2
0.7
1.0
%/V
%
IN
I
I
= 100µA to 150mA (VO1 and VO2)
= 100µA to 300mA (VO2)
0.1
OUT
OUT
%
Maximum Output Current
I
VO1: Continuous
VO2: Continuous
150
300
350
mA
mA
mA
mV
mV
mV
mV
°C
MAX
Internal Current Limit
I
V
V
V
V
T
475
125
300
250
200
145
110
600
200
500
400
325
LIM
Dropout Voltage (Note 7)
I
I
I
I
= 150mA; V 2.1V (VO1)
O
DO1
DO2
DO3
DO4
SD+
O
O
O
O
= 300mA; V < 2.5V (VO2)
O
= 300mA; 2.5V V 2.8V (VO2)
O
= 300mA; V > 2.8V (VO2)
O
Thermal Shutdown Temperature
T
°C
SD-
AC CHARACTERISTICS
Ripple Rejection
I
= 10mA, V = 2.8V(min), V = 1.8V, C = 0.1µF
IN BYP
O
O
@ 1kHz
70
55
40
dB
dB
dB
@ 10kHz
@ 100kHz
FN9220 Rev 4.00
December 10, 2015
Page 3 of 12
ISL9012
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
T
= -40°C to +85°C; V = (V + 0.5V) to 6.5V with a minimum V of 2.3V; C = 1µF; C = 1µF;
A
IN
O
IN
IN
O
C
= 0.01µF; C
POR
= 0.01µF (Continued)
BYP
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
= 100µA, V = 1.5V, T = +25°C, C = 0.1µF
BYP
(Note 8) TYP (Note 8) UNITS
Output Noise Voltage
I
30
µVrms
O
O
A
BW = 10Hz to 100kHz (Note 6)
DEVICE START-UP CHARACTERISTICS
Device Enable TIme
t
Time from assertion of the ENx pin to when the output voltage
reaches 95% of the VO(nom)
250
30
500
60
µs
EN
LDO Soft-start Ramp Rate
t
Slope of linear portion of LDO output voltage ramp during start-
up
µs/V
SSR
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage
V
-0.3
1.4
0.5
V
V
IL
Input High Voltage
V
V +0.3
IN
IH
Input Leakage Current
Pin Capacitance
I , I
IL IH
0.1
µA
pF
C
Informative
5
PIN
POR PIN CHARACTERISTICS
POR Thresholds
V
As a percentage of nominal output voltage
CPOR = 0.01µF
91
87
94
90
97
93
%
%
POR+
V
POR-
POR Delay
t
t
100
200
25
300
ms
µs
V
PLH
PHL
POR Pin Output Low Voltage
V
@I = 1.0mA
OL
0.2
OL
POR Pin Internal Pull-Up
Resistance
R
78
100
180
k
POR
NOTES:
6. Limits established by characterization and are not production tested.
7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
EN2
t
EN
V
POR+
V
POR+
V
V
POR-
POR-
<t
PHL
VO2
POR
t
t
PLH
PHL
FIGURE 1. TIMING PARAMETER DEFINITION
FN9220 Rev 4.00
December 10, 2015
Page 4 of 12
ISL9012
Typical Performance Curves
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
0.8
0.6
0.4
VIN = 3.8V
VO = 3.3V
VO = 3.3V
= 0mA
I
LOAD
0.2
-40C
-40C
+25C
0.0
+25C
-0.2
+85C
-0.4
-0.6
-0.8
+85C
0
50
100
150
200
250
300
350
400
3.4
3.8
4.2
4.6
5.0
5.4
5.8
6.2
6.6
LOAD CURRENT - I (mA)
O
INPUT VOLTAGE (V)
FIGURE 2. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V
OUTPUT)
FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
3.4
0.10
VIN = 3.8V
VO = 3.3V
VO1 = 3.3V
0.08
I
= 0mA
O
3.3
3.2
3.1
3.0
2.9
2.8
I
= 0mA
LOAD
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
I
= 150mA
O
-0.08
-0.10
3.1
3.6
4.1
4.6
5.1
5.6
6.1
6.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
INPUT VOLTAGE (V)
TEMPERATURE (C)
FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE
(VO1 = 3.3V)
2.9
350
300
VO2 = 2.8V
I
= 0mA
O
2.8
2.7
2.6
2.5
2.4
2.3
250
VO2 = 2.8V
I
= 150mA
O
200
150
100
I
= 300mA
O
VO1 = 3.3V
50
0
2.6
3.1
3.6
4.1
4.6
5.1
5.6
6.1 6.5
0
50
100
150
200
250
300
350
400
INPUT VOLTAGE (V)
OUTPUT LOAD (mA)
FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE
(VO2 = 2.8V)
FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT
FN9220 Rev 4.00
December 10, 2015
Page 5 of 12
ISL9012
Typical Performance Curves (Continued)
55
50
45
40
35
30
25
175
VO1 = 3.3V
150
125
+125C
+25C
+85C
+25C
-40C
100
75
50
25
0
-40C
VO1 = 3.3V
VO2 = 2.8V
I
(BOTH CHANNELS) = 0µA
O
3.0
3.5
4.0
4.58
5.0
5.5
6.0
6.5
0
25
50
75
100
125
150
175
200
OUTPUT LOAD (mA)
INPUT VOLTAGE (V)
FIGURE 8. VO1 DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
200
180
160
55
50
45
40
140
+25C
+85C
120
-40C
100
80
35
60
VIN = 3.8V
40
VIN = 3.8V
VO1 = 3.3V
VO2 = 2.8V
VO = 3.3V
= 0µA
30
I
20
LOAD
BOTH OUTPUTS ON
0
25
-40 -25 -10
0
50
100
150
200
250
300
350
400
5
20 35 50 65 80 95 110 125
LOAD CURRENT (mA)
TEMPERATURE (C)
FIGURE 10. GROUND CURRENT vs LOAD
FIGURE 11. GROUND CURRENT vs TEMPERATURE
3.5
VO1 = 3.3V
VO2 = 2.8V
VO1 = 3.3V
VO2 = 2.8V
I 1 = 150mA
L
5
4
3
2
1
0
3.0
2.5
2.0
1.5
1.0
0.5
0
I 1 = 150mA
L
I 2 = 300mA
L
VIN
VO1
I 2 = 300mA
L
POR
CPOR = 0.1µF
VO-1
VO-2
VO2
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1.0
1.5
2.0
2.5
TIME (s)
3.0
3.5
4.0
4.5
5.0
TIME (s)
FIGURE 13. POWER-UP/POWER-DOWN WITH POR SIGNALS
FIGURE 12. POWER-UP/POWER-DOWN
FN9220 Rev 4.00
December 10, 2015
Page 6 of 12
ISL9012
Typical Performance Curves (Continued)
VO2 (10mV/DIV)
VO = 3.3V
= 150mA
I
LOAD
C
C
= 1µF
LOAD
= 0.01µF
BYP
VIN = 5.0V
VO1 = 3.3V
VO2 = 2.8V
3
2
1
0
5
0
4.3V
3.6V
I 1 = 150mA
L
I 2 = 300mA
L
C 1, C 2 = 1µF
L
L
C
= 0.01µF
BYP
10mV/DIV
0
100 200 300 400 500 600 700 800 900 1000
TIME (µs)
400µs/DIV
FIGURE 14. TURN ON/TURN OFF RESPONSE
FIGURE 15. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
VO = 2.8V
I
= 300mA
LOAD
C
C
= 1µF
LOAD
= 0.01µF
VO (25mV/DIV)
BYP
4.2V
3.5V
VO = 1.8V
VIN = 2.8V
300mA
10mV/DIV
I
LOAD
10µA
100µs/DIV
400µs/DIV
FIGURE 17. LOAD TRANSIENT RESPONSE
FIGURE 16. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
100
1000
100
10
VIN = 3.6V
90
80
70
60
50
40
30
20
10
0
VO = 1.8V
= 10mA
I
O
C
C
= 0.01µF
BYP
= 1µF
LOAD
VIN = 3.6V
VO = 1.8V
I
= 10mA
LOAD
C
C
C
= 0.01µF
BYP
1
= 1µF
IN
= 1µF
LOAD
0.1
10
0.1k
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 18. PSRR vs FREQUENCY
FIGURE 19. SPECTRAL NOISE DENSITY vs FREQUENCY
FN9220 Rev 4.00
December 10, 2015
Page 7 of 12
ISL9012
Pin Description
PIN
PIN
NUMBER
NAME
TYPE
DESCRIPTION
1
2
3
4
VIN
Analog I/O
Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
EN1
Low Voltage Compatible
CMOS Input
LDO-1 Enable.
EN2
Low Voltage Compatible
CMOS Input
LDO-2 Enable.
CBYP
Analog I/O
Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.
5
CPOR
Analog I/O
POR Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR output release after LDO-2
output reaches 94% of its specified voltage level (200ms delay per 0.01µF).
6
7
8
9
GND
NC
Ground
GND is the connection to system ground. Connect to PCB Ground plane.
No Connection.
NC
POR
VO2
Open Drain Output (1mA)
Analog I/O
Open-drain POR Output for LDO-2 (active-low).
LDO-2 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
10
VO1
Analog I/O
LDO-1 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
Typical Application
R1
ISL9012
10
9
1
2
VIN (2.3V TO 6.5V)
ON
V
V
1
VIN
VO1
VO2
OUT
OUT
EN1
2
ENABLE 1
V
2 OK
ON
OUT
OFF
8
7
3
4
EN2
POR
NC
RESET
ENABLE 2
OFF
V
2 TOO LOW
(200ms DELAY, C3 = 0.01µF)
OUT
CBYP
6
5
CPOR
GND
C1
C2
C3
C4
C5
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.01µF X5R CERAMIC CAPACITOR
C3: 0.01µF X5R CERAMIC CAPACITOR
R1: 100k RESISTOR, 5%
FN9220 Rev 4.00
December 10, 2015
Page 8 of 12
ISL9012
Block Diagram
VIN
IS2
LDO
VREF
TRIM
ERROR
1V
VO1
VO2
VO2
AMPLIFIER
QEN2
~1.0V
POR
COMPARATOR
VOK2
POR
LDO-2
LDO-1
EN1
EN2
POR
CONTROL
LOGIC
POR
DELAY
VOK2
1.00V
BANDGAP AND
TEMPERATURE
SENSOR
VOLTAGE
REFERENCE
GENERATOR
0.94V
0.90V
UVLO
GND
CBYP
CPOR
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDO’s power up.
Functional Description
The ISL9012 contains all circuitry required to implement two
high performance LDO’s. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9012 adjusts its biasing to achieve the lowest standby
current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart Thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device
turn-on time.
If EN1 is brought high, and EN2 goes high before the VO1
output stabilizes, the ISL9012 delays the VO2 turn-on until
the VO1 output reaches its target level.
Power Control
The ISL9012 has two separate enable pins, EN1 and EN2,
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown
If EN2 is brought high, and EN1 goes high before VO2 starts
its output ramp, then VO1 turns on first and the ISL9012
FN9220 Rev 4.00
December 10, 2015
Page 9 of 12
ISL9012
delays the VO2 turn-on until the VO1 output reaches its target
level.
following output voltages: 1.5V, 1.8V, 1.85V, 2.5V, 2.6V, 2.7V,
2.8V, 2.85V, 2.9V, 3.0V, and 3.3V.
If EN2 is brought high, and EN1 goes high after VO2 starts its
output ramp, then the ISL9012 immediately starts to ramp up
the VO1 output.
Power-On Reset Generation
LDO-2 has a Power-on Reset signal generation circuit which
outputs to the POR pin. The POR signal is generated as
follows:
If both EN1 and EN2 are high, the VO1 output has priority, and
is always powered up first.
A POR comparator continuously monitors the voltage of the
LDO-2 output. The LDO enters a power-good state when the
output voltage is above 94% of the expected output voltage for
a period exceeding the LDO PGOOD entry delay time. In the
power-good state, the open-drain POR output is in a high-
impedance state. An external resistor can be added between
the POR output and either LDO output or the input voltage,
VIN.
During operation, whenever the VIN voltage drops below about
1.8V, the ISL9012 immediately disables both LDO outputs.
When VIN rises back above 2.1V, the device re-initiates its
start-up sequence and LDO operation will resume
automatically.
Reference Generation
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin. A
0.01µF capacitor connected CBYP implements a 100Hz
lowpass filter, and is recommended for most high performance
applications. For the lowest noise application, a 0.1µF or
greater CBYP capacitor should be used. This filters the
reference noise to below the 10Hz to1kHz frequency band,
which is crucial in many noise-sensitive applications.
The power-good state is exited when the LDO-2 output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9012 pulls the respective POR pin low.
The PGOOD entry and exit delays are determined by the value
of the external capacitor connected to the CPOR pin. For a
0.01µF capacitor, the entry and exit delays are 200ms and
25µs respectively. Larger or smaller capacitor values will yield
proportionately longer or shorter delay times. The POR exit
delay should never be allowed to be less than 10µs to ensure
sufficient immunity against transient induced false POR
triggering.
The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference, POR detection thresholds,
and other voltage references required for current generation
and over-temperature detection.
Overheat Detection
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This current
is compared with references to determine if the device is in
danger of damage due to overheating. When the die
The current generator outputs references required for adaptive
biasing as well as references for LDO output current limit and
thermal shutdown determination.
temperature reaches about +145°C, one or both of the LDO’s
momentarily shut down until the die cools sufficiently. In the
overheat condition, only the LDO sourcing more than 50mA
will be shut off. This does not affect the operation of the other
LDO. If both LDOs source more than 50mA and an overheat
condition occurs, both LDO outputs are disabled. Once the die
temperature falls back below about +110°C, the disabled
LDO(s) are re-enabled and soft-start automatically takes place.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9012 provides a regulator that has low
quiescent current, fast transient response, and overall stability
across all operating and load current conditions. LDO stability
is guaranteed for a 1µF to 10µF output capacitor that has a
tolerance better than 20% and ESR less than 200m. The
design is performance-optimized for a 1µF capacitor. Unless
limited by the application, use of an output capacitor value
above 4.7µF is not recommended as LDO performance
improvement is minimal.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9012 provides short-circuit protection by limiting the output
current to about 475mA.
Each LDO uses an independently trimmed 1V reference. An
internal resistor divider drops the LDO output voltage down to
1V. This is compared to the 1V reference for regulation. The
resistor division ratio is programmed in the factory to one of the
FN9220 Rev 4.00
December 10, 2015
Page 10 of 12
ISL9012
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
December 10, 2015
FN9220.4
Added Rev History beginning with Rev 4.
Added About Intersil. Verbiage.
Updated Ordering Information table on page 2
Updated POD L10.3x3C to most current version. Revision changes are as follows:
Updated Format to new standard
Removed package outline and included center to center distance between lands on recommended land
pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and
0.30mm from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly.
Tiebar Note 4 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2005-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9220 Rev 4.00
December 10, 2015
Page 11 of 12
ISL9012
Package Outline Drawing
L10.3x3C
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 4, 3/15
5
3.00
A
B
PIN #1 INDEX AREA
10
1
2
5
PIN 1
INDEX AREA
10 x 0.25
6
C B
0.10
(4X)
1.64
10x 0.40
TOP VIEW
BOTTOM VIEW
M C B
(4X)
0.10
SEE DETAIL "X"
(10 x 0.60)
(10x 0.25)
0.10
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
1.64
2.80 TYP
4
0.20 REF
0.05
C
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5.
6. Compliant to JEDEC MO-229-WEED-3 except for E-PAD
dimensions.
FN9220 Rev 4.00
December 10, 2015
Page 12 of 12
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