ISL91128IIN-EVZ [RENESAS]
High Efficiency Buck-Boost Regulator with 4.5A Switches and I2C Interface;
| 型号： | ISL91128IIN-EVZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | High Efficiency Buck-Boost Regulator with 4.5A Switches and I2C Interface |
| 文件： | 总17页 (文件大小：999K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL91128
FN8732
Rev.3.00
May 3, 2018
2
High Efficiency Buck-Boost Regulator with 4.5A Switches and I C Interface
The ISL91128 is a high-current, buck-boost switching regulator
Features
for systems using new battery chemistries. It uses the Renesas
• Accepts input voltages above or below regulated output
voltage
proprietary buck-boost algorithm to maintain voltage
regulation while providing excellent efficiency and very low
output voltage ripple when the input voltage is close to the
output voltage. The device also includes a selectable Bypass
mode for low power consumption in applications that have a
Sleep or Low Power mode.
• Automatic and seamless transitions between Buck and
Boost modes
2
• I C interface
• Input voltage range: 1.8V to 5.5V
The ISL91128 is capable of delivering at least 2.2A continuous
• Continuous output current: up to 2.4A (PVIN = 2.5V,
output current (V
= 3.3V) across a battery voltage range of
OUT
V
= 3.3V)
OUT
2.5V to 4.35V. This maximizes the energy utilization of
advanced, single-cell Li-ion battery chemistries that have
significant capacity left at voltages below the system voltage.
Its fully synchronous low ON-resistance 4-switch architecture
and a low quiescent current of only 30µA optimize efficiency
under all load conditions.
• High efficiency: up to 96%
• 30µA quiescent current maximizes light-load efficiency
• Selectable bypass power saving mode operation
• 2.5MHz switching frequency minimizes external component
size
The ISL91128 supports a broader set of programmable
2
• Fully protected for short-circuit, over-temperature, and
undervoltage
features that can be accessed using an I C bus interface. With
a programmable output voltage range of 1.9V to 5.0V, the
ISL91128 is ideal for applications requiring dynamically
changing supply voltages. A programmable slew rate can be
selected to provide smooth transitions between output voltage
settings.
• Small 2.15mmx1.74mm WLCSP
Applications
• Brownout-free system voltage for smart phones and tablet
PCs
The ISL91128 is available in a 20 bump, 0.4mm pitch WLCSP
(2.15mmx1.74mm) with a 2.5MHz switching frequency, which
further reduces the size of external components.
• Wireless communication devices
• 2G/3G/4G RF power amplifiers
Related Literature
For a full list of related documents, visit our website
• ISL91128 product page
100
ISL91128IINZ
VIN = 4.2V
VIN = 3.3V
VIN = 3.6V
V
1.8V TO 5.5V
IN =
LX1
PVIN
95
90
85
80
75
L
1µH
C
1
10µF
1
LX2
V
= 3.3V
VIN
EN
OUT
VOUT
C
2
VIN = 2.8V
2x22µF
FB
SDA
SCL
VIN = 3V
1
10
100
1000
LOAD CURRENT (mA)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. EFFICIENCY: V
OUT
= 3.3V, T = +25°C
A
FN8732 Rev.3.00
May 3, 2018
Page 1 of 17
ISL91128
Block Diagram
LX1
LX2
B1 B2 B3
D1 D2 D3
A1
E1
E2
E3
PVIN
VOUT
PGND
B2
A3
SOFT
DISCHARGE
EN
GATE DRIVERS
AND ANTI-
SHOOT THRU
EN
EN
B4
A4
C1
C2
C3
EN
VIN
VREF
PVIN
MONITOR
VOUT
CLAMP
THERMAL
SHUTDOWN
PWM CONTROL
CURRENT
DETECT
C3
C4
SCL
SDA
EN
EN
VOUT
MONITOR
FB
E4
OSC
EN
REF
ERROR
AMP
VOLTAGE
PROG.
D4
SGND
FIGURE 3. BLOCK DIAGRAM
FN8732 Rev.3.00
May 3, 2018
Page 2 of 17
ISL91128
Pin Descriptions
Pin Configuration
ISL91128
PIN #
PIN NAMES
DESCRIPTION
(20 BALL WLCSP, 0.4mm PITCH)
TOP VIEW, BUMPS DOWN
A1, A2, A3
PVIN
Power input. Range: 1.8V to 5.5V. Connect
2x10μF capacitors to PGND.
1
2
3
4
B1, B2, B3
C1, C2
LX1
PGND
LX2
Inductor connection, input side
Power ground for high switching current
Inductor connection, output side
PVIN
LX1
PVIN
LX1
PVIN
LX1
VIN
A
B
C
D
E
D1, D2,
D3
E1, E2,
E3
VOUT
Buck-boost regulator output. Connect
2x22μF capacitors to PGND.
EN
2
C4
C3
A4
B4
D4
E4
SDA
SCL
VIN
I C data input
PGND
LX2
PGND
LX2
SCL
LX2
SDA
SGND
FB
2
I C clock input
Supply input. Range: 1.8V to 5.5V.
Logic input, drive HIGH to enable device.
Analog ground pin
EN
SGND
FB
VOUT
VOUT
VOUT
Voltage feedback pin. Connect to VOUT
Ordering Information
PART NUMBER
PART
DEFAULT OUTPUT
VOLTAGE (V)
TEMP RANGE
(°C)
TAPE AND REEL
(UNITS) (Note 1)
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
(Notes 2, 3)
MARKING
ISL91128IINZ-T
GAYC
GAYC
3.3
3.3
-40 to +85
-40 to +85
3k
20 Ball WLCSP
20 Ball WLCSP
W4x5.20M
W4x5.20M
ISL91128IINZ-T7A
ISL91128IIN-EVKIT1Z
ISL91128IIN-EVZ
NOTES:
250
Evaluation Board Kit for ISL91128IINZ
Evaluation Board for ISL91128IINZ
1. Refer to TB347 for details about reel specifications.
2. These Pb-free WLCSP packaged products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball
terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free WLCSP packaged products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL91128 product information page. For more information about MSL, see TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
BUCK-BOOST
REGULATION
DYNAMIC VOLTAGE
SCALING
2
PART NUMBER
ISL91127
BYPASS
No
I C
PACKAGE
WLCSP
QFN
Yes
Yes
Yes
No
No
No
No
ISL91127IR
ISL91128
No
Yes
Yes
Yes
WLCSP
NOTE: For the full family of ISL911xx buck-boost regulators, please visit our website.
FN8732 Rev.3.00
May 3, 2018
Page 3 of 17
ISL91128
Absolute Maximum Ratings
Thermal Information
PVIN, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
LX1, LX2. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5VDC, -2V to 7V for 10ns
FB (Adjustable Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Thermal Resistance (Typical)
20 Ball WLCSP Package (Notes 4, 5) . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
JA (°C/W)
72
JB (°C/W)
16
FB (Fixed V
Versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
OUT
GND, PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ESD Rating
Human Body Model (Tested per JS-001-2010). . . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD-78D; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Maximum Load Current
V
= 2.5V V = 3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2ADC
IN
OUT
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
JA
5. For , the board temp is taken on the board near the edge of the package, on a trace at the middle of one side. See TB379.
JB
Analog Specifications
V
= V
= V = 3.6V, V = 3.3V, L = 1µH, C = 10µF, C = 2x22µF, T = +25°C. Boldface limits apply across
EN OUT 1 1 2 A
IN
PVIN
the operating temperature range, -40°C to +85°C and input voltage range (1.8V to 5.5V) unless specified otherwise.
MIN
TYP
MAX
PARAMETER
POWER SUPPLY
Input Voltage Range
SYMBOL
TEST CONDITIONS
(Note 6) (Note 7) (Note 6)
UNIT
2
V
V
needs to be higher than the I C pull-up voltage
1.8
5.5
V
V
IN
IN
V
Undervoltage Lockout Threshold
V
Rising
1.725
1.650
30
1.795
IN
UVLO
Falling
1.550
V
V
Supply Current
I
PFM mode, no external load on V
(Note 8),
45
µA
IN
VIN
OUT
V
= 4.5V
IN
V
V
Supply Current, Bypass
I
Bypass mode, V = 4.5V
6.0
µA
µA
IN
IN
BYP
IN
Supply Current, Shutdown
I
EN = GND, V = 3.6V
0.05
1.00
SD
IN
OUTPUT VOLTAGE REGULATION
Output Voltage Range
V
I
= 100mA, V = 3.6V
OUT IN
1.95
-2
5.00
+2
V
%
OUT
Output Voltage Accuracy
V
V
= 3.7V, V
= 3.3V, I
= 3.3V, I
= 0mA, PWM mode
= 1mA, PFM mode
IN
IN
OUT
OUT
OUT
OUT
= 3.7V, V
-3
+4
%
Line Regulation, PWM Mode
Load Regulation, PWM Mode
Line Regulation, PFM Mode
Load Regulation, PFM Mode
V
V
/
/
I
= 500mA, V
OUT
= 3.3V, V step from 2.3V to
IN
±5
mV/V
OUT
OUT
V
5.5V
IN
V
= 3.7V, V
= 3.3V, I step from 0mA to
OUT
±0.05
±12.5
±0.4
mV/mA
mV/V
OUT
IN
OUT
I
1000mA
OUT
V
/
I
= 100mA, V
OUT
= 3.3V, V step from 2.3V to
IN
OUT
OUT
5.5V
V
IN
V
/
V
= 3.7V, V
OUT
= 3.3V, I step from 0mA to
OUT
mV/mA
OUT
IN
I
100mA
OUT
Output Voltage Clamp
V
Rising
5.25
5.95
V
CLAMP
Output Voltage Clamp Hysteresis
DC/DC SWITCHING SPECIFICATIONS
Oscillator Frequency
400
mV
f
2.10
-1
2.50
80
2.90
1
MHz
ns
SW
Minimum On-Time
t
ON(MIN)
LX1 Pin Leakage Current
IPFETLEAK
V
= 3.6V
µA
IN
FN8732 Rev.3.00
May 3, 2018
Page 4 of 17
ISL91128
Analog Specifications
V
= V
= V = 3.6V, V = 3.3V, L = 1µH, C = 10µF, C = 2x22µF, T = +25°C. Boldface limits apply across
EN OUT 1 1 2 A
IN
PVIN
the operating temperature range, -40°C to +85°C and input voltage range (1.8V to 5.5V) unless specified otherwise. (Continued)
MIN
TYP
MAX
PARAMETER
LX2 Pin Leakage Current
SOFT-START AND SOFT DISCHARGE
Soft-Start Time
SYMBOL
INFETLEAK
TEST CONDITIONS
(Note 6) (Note 7) (Note 6)
UNIT
µA
V
= 3.6V
-1
1
IN
t
Time from when EN signal asserts to when output
voltage ramp starts
1
2
ms
ms
SS
Time from when output voltage ramp starts to when
output voltage reaches 95% of its nominal value
with device operating in Buck mode.
V
= 4V, V = 3.3V, I = 200mA
IN
OUT O
Time from when output voltage ramp starts to when
output voltage reaches 95% of its nominal value
with device operating in Boost mode.
2
ms
V
= 2V, V = 3.3V, I = 200mA
IN
EN < V
IL
OUT O
V
Soft Discharge ON-Resistance
R
120
Ω
OUT
DISCHG
POWER MOSFET
Input P-Channel MOSFET ON-Resistance
Output P-Channel MOSFET ON-Resistance
Input N-Channel MOSFET ON-Resistance
Output N-Channel MOSFET ON-Resistance
P-Channel MOSFET Peak Current Limit
PFM/PWM TRANSITION
R
V
V
V
V
V
= 3.6V, I = 200mA
30
27
25
25
4.2
mΩ
mΩ
mΩ
mΩ
A
DS(ON)_PI
IN
IN
IN
IN
IN
O
R
= 3.6V, I = 200mA
O
DS(ON)_PO
R
= 3.6V, I = 200mA
O
DS(ON)_NI
R
= 3.6V, I = 200mA
O
DS(ON)_NO
I
= 3.6V
4.0
5.2
PK_LMT
Load Current Threshold, PFM to PWM
Load Current Threshold, PWM to PFM
Thermal Shutdown
V
V
= 3.6V, V
= 3.6V, V
= 3.3V
= 3.3V
200
75
mA
mA
°C
IN
IN
OUT
OUT
155
30
Thermal Shutdown Hysteresis
LOGIC INPUTS
°C
Input Leakage
I
V
V
V
= 3.6V
= 3.6V
= 3.6V
0.05
1
µA
V
LEAK
IN
IN
IN
Input HIGH Voltage
V
1.4
IH
Input LOW Voltage
V
0.4
V
IL
2
I C Interface Timing Specification For SCL and SDA pins, unless otherwise noted.
MIN
(Note 9)
TYP
MAX
PARAMETER
Pin Capacitance
SYMBOL
TEST CONDITIONS
(Note 7) (Note 9)
UNIT
pF
C
15
400
50
pin
SCL Frequency
f
kHz
ns
SCL
Pulse Width Suppression Time at SDA
and SCL Inputs
t
Any pulse narrower than the maximum
specification is suppressed
sp
SCL Falling Edge to SDA Output Data Valid
t
SCL falling edge crossing V , until SDA exits the
IL
900
ns
ns
AA
V
to V window
IL
IH
Time the Bus Must be Free Before the
Start of a New Transmission
t
SDA crossing V during a STOP condition, to SDA
IH
1300
BUF
crossing V during the following START condition
IH
Clock LOW Time
Clock HIGH Time
t
Measured at the V crossings
IL
1300
600
ns
ns
LOW
t
Measured at the V crossings
IH
HIGH
FN8732 Rev.3.00
May 3, 2018
Page 5 of 17
ISL91128
2
I C Interface Timing Specification For SCL and SDA pins, unless otherwise noted. (Continued)
MIN
TYP
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 9)
(Note 7) (Note 9)
UNIT
ns
START Condition Set-Up Time
t
SCL rising edge to SDA falling edge; both crossing
600
SU:STA
V
IH
START Condition Hold Time
Input Data Set-Up Time
Input Data Hold Time
t
From SDA falling edge crossing V to SCL falling
600
100
0
ns
ns
ns
ns
ns
ns
HD:STA
IL
edge crossing V
IH
t
From SDA exiting the V to V window, to SCL
IL IH
SU:DAT
rising edge crossing V
IL
t
From SCL rising edge crossing V to SDA
IH
HD:DAT
entering the V to V window
IL IH
STOP Condition Set-Up Time
t
From SCL rising edge crossing V , to SDA rising
IH
600
1300
0
SU:STO
edge crossing V
IL
From SDA rising edge to SCL falling edge; both
crossing V
STOP Condition Hold Time for Read or
Volatile Only Write
t
HD:STO
IH
From SCL falling edge crossing V , until SDA
Output Data Hold Time
t
DH
IL
enters the V to V window
IL IH
SDA and SCL Rise Time
t
From V to V
IL
20 + 0.1 x Cb
250
250
400
ns
ns
pF
kΩ
R
IH
SDA and SCL Fall Time
t
From V to V
IH
20 + 0.1 x Cb
F
IL
Capacitive Loading of SDA or SCL
SDA and SCL Bus Pull-Up Resistor Off-Chip
Cb
Total on-chip and off-chip
10
1
Rpu
Maximum is determined by t and t
R
F
For Cb = 400pF, max is about 2kΩ~2.5kΩ
For Cb = 40pF, max is about 15kΩ~20kΩ
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Typical values are for T = +25°C and V = 3.6V.
IN
A
8. Quiescent current measurements are taken when the output is not switching.
9. Limits established by characterization and are not production tested.
FN8732 Rev.3.00
May 3, 2018
Page 6 of 17
ISL91128
Typical Performance Curves Unless otherwise noted, operating conditions are: T = +25°C, V = EN = 3.6V, L = 1µH,
A
IN
1
C
= 2x10µF, C = 2x22µF, V
2
= 3.3V, I
= 0A to 3A.
OUT
1
OUT
100.00
3.3
3.29
3.28
3.27
3.26
3.25
3.24
3.23
3.22
3.21
3.2
LOAD = 500mA
LOAD = 1000mA
LOAD = 100mA
95.00
90.00
85.00
80.00
3V
2.8V
LOAD = 10mA
4.2V
2.5V
3.6V
3.3V
1
10
100
LOAD CURRENT(mA)
1000
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VIN (V)
FIGURE 4. EFFICIENCY vs INPUT VOLTAGE
FIGURE 5. OUTPUT VOLTAGE vs LOAD CURRENT
2.55
2.50
2.45
2.40
2.35
2.30
2.25
80
T
T
= +85°C
= +25°C
A
70
60
50
40
30
20
10
0
A
T
= -40°C
A
1.5
2.5
3.5
(V)
4.5
5.5
1.5
2.5
3.5
(V)
4.5
5.5
V
V
IN
IN
FIGURE 6. QUIESCENT CURRENT vs INPUT VOLTAGE (V
MODE = HIGH)
= 3.3V,
FIGURE 7. SWITCHING FREQUENCY vs INPUT VOLTAGE
OUT
EN (2V/DIV)
LX1 (2V/DIV)
LX2 (2V/DIV)
V
(AC, 1V/DIV)
OUT
V
(AC, 50mV/DIV)
OUT
I
(1A/DIV)
L
I
(500mA/DIV)
L
1ms/DIV
400ns/DIV
FIGURE 8. STEADY-STATE OPERATION IN PFM (V = 3.3V,
IN
FIGURE 9. SOFT-START (V = 3.6V, V = 3.3V, NO LOAD)
IN OUT
V
= 3.3V, NO LOAD)
OUT
FN8732 Rev.3.00
May 3, 2018
Page 7 of 17
ISL91128
Typical Performance Curves Unless otherwise noted, operating conditions are: T = +25°C, V = EN = 3.6V, L = 1µH,
A
IN
1
C
= 2x10µF, C = 2x22µF, V
2
= 3.3V, I
= 0A to 3A. (Continued)
OUT
1
OUT
I
(1A/DIV)
L
EN (2V/DIV)
LX1 (2V/DIV)
V
(AC, 1V/DIV)
OUT
LX2 (2V/DIV)
V
(AC, 20mV/DIV)
OUT
I
(1A/DIV)
L
400ns/DIV
1ms/DIV
FIGURE 10. SOFT-START (V = 2.5V, V
IN OUT
= 3.3V, NO LOAD)
FIGURE 11. STEADY-STATE OPERATION (V = 2.5V, V
IN
= 3.3V,
OUT
2A LOAD)
V
(AC, 100mV/DIV)
OUT
V
(AC, 100mV/DIV)
OUT
I
(1A/DIV)
L
I
(1A/DIV)
L
100µs/DIV
100µs/DIV
FIGURE 12. 0A TO 2A LOAD TRANSIENT (V = 3.6V, V
IN OUT
= 3.3V)
FIGURE 13. 0.5A TO 1.5A LOAD TRANSIENT (V = 3.6V, V
= 3.3V)
OUT
IN
LX1 (2V/DIV)
LX2 (2V/DIV)
V
(AC, 100mV/DIV)
OUT
V
(2V/DIV)
OUT
I
(1A/DIV)
L
I
(2A/DIV)
L
100µs/DIV
20ms/DIV
FIGURE 14. 0A TO 1A LOAD TRANSIENT (V = 3.6V, V
IN OUT
= 3.3V)
FIGURE 15. OUTPUT SHORT-CIRCUIT BEHAVIOR (V = 3.6V,
IN
V
= 3.3V)
OUT
FN8732 Rev.3.00
May 3, 2018
Page 8 of 17
ISL91128
Typical Performance Curves Unless otherwise noted, operating conditions are: T = +25°C, V = EN = 3.6V, L = 1µH,
A
IN
1
C
= 2x10µF, C = 2x22µF, V
= 3.3V, I
= 0A to 3A. (Continued)
OUT
1
2
OUT
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
V
(1V/DIV)
IN
(AC, 100mV/DIV)
OUT
2.5
3.0
3.5
4.0
4.5
5.0
5.5
100µs/DIV
VIN (V)
FIGURE 17. OUTPUT CURRENT CAPABILITY: V
OUT
= 3.3V, T = +25°C
A
FIGURE 16. 4V TO 3.2V LINE TRANSIENT (V
= 3.3V, LOAD = 1A)
OUT
When the target output voltage is higher than the input voltage,
the device transitions from Buck mode to Boost mode during the
soft-start sequence. During this transition, the ramp rate of the
reference voltage is decreased, such that the output voltage slew
rate is decreased. This provides a slower output voltage slew
rate.
Functional Description
Functional Overview
The ISL91128 implements a complete buck-boost switching
regulator with PWM controller, internal switches, references,
protection circuitry, and control inputs. Refer to the “Block
Diagram” on page 2.
The V
OUT
ramp time is not constant for all operating conditions.
Soft-start into Boost mode takes longer than soft-start into Buck
mode. The total soft-start time into Buck operating mode is
typically 2ms, whereas the typical soft-start time into Boost
operating mode is typically 3ms. Increasing the load current
increases these typical soft-start times.
The PWM controller automatically switches between Buck and
Boost modes as necessary to maintain a steady output voltage
with changing input voltages and dynamic external loads.
Internal Supply and References
Short-Circuit Protection
Referring to the “Block Diagram” on page 2, the ISL91128
provides four power input pins. The PVIN pin supplies input power
to the DC/DC converter, while the VIN pin provides an operating
The ISL91128 provides short-circuit protection by monitoring the
feedback voltage. When feedback voltage is sensed to be lower
than a certain threshold, the PWM oscillator frequency is
reduced in order to protect the device from damage. The
P-channel MOSFET peak current limit remains active during this
state.
voltage source required for stable V
generation. Separate
REF
ground pins (SGND and PGND) are provided to avoid problems
caused by ground shift due to the high switching currents.
Enable Input
Thermal Shutdown
A built-in thermal protection feature protects the ISL91128 if the
die temperature reaches +155°C (typical). At this die
The device enable by asserting the EN pin HIGH. Driving EN LOW
invokes a power-down mode in which most internal device
functions are disabled.
temperature, the regulator is completely shut down. The die
temperature continues to be monitored in this thermal shutdown
mode. When the die temperature falls to +125°C (typical), the
device resumes normal operation. When exiting thermal
shutdown, the ISL91128 executes its soft-start sequence.
Soft Discharge
When the device is disabled by driving EN LOW, an internal resistor
between VOUT and GND is activated to slowly discharge the output
capacitor. This internal resistor has a typical 120Ω resistance. The
2
soft discharge function can be disabled through the I C interface
(see Table 5 on page 14).
POR Sequence and Soft-Start
Asserting the EN pin HIGH allows the device to power up. The
following events occur during the start-up sequence. The internal
voltage reference powers up and stabilizes. The device then
starts operating. A typical 1ms delay occurs between assertion of
the EN pin and the start of the switching regulator soft-start
ramp.
FN8732 Rev.3.00
May 3, 2018
Page 9 of 17
ISL91128
Buck-Boost Conversion Topology
Operation with V Close to V
IN OUT
The ISL91128 operates in either Buck or Boost mode. When
operating in conditions where PVIN is close to VOUT, the
ISL91128 alternates between Buck and Boost mode as
necessary to provide a regulated output voltage.
When the output voltage is close to the input voltage, the
ISL91128 rapidly and smoothly switches from Boost to Buck
mode as needed to maintain the regulated output voltage. This
behavior provides excellent efficiency and very low output
voltage ripple.
L
1
2
LX1
LX2
I C Serial Interface
The ISL91128 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL91128 operates as a slave device in all
applications. The SCL and SDA pins are open drain and need
external pull-up resistors connected with a proper voltage level,
SWITCH A
SWITCH D
VOUT
PVIN
SWITCH B
SWITCH C
FIGURE 18. BUCK-BOOST TOPOLOGY
2
for example, 3.3V. Pull the SCL and SDA pins to GND if the I C
interface is not used.
Figure 18 shows a simplified diagram of the internal switches
and external inductor.
2
All communication over the I C interface is conducted by sending
the MSB of each byte of data first.
PWM Operation
In Buck PWM mode, Switch D is continuously closed and
Switch C is continuously open. Switches A and B operate as a
synchronous buck converter when in this mode.
Bypass Mode Operation
Bypass mode is always enabled and can be disabled by writing a
‘1’ to Bit 5 in the Mode Control register. When this function is
disabled, setting the EN pin to ‘0’ will disable the device. To
prevent the device from going into Bypass mode at power-up, EN
should be set to ‘1’ or connected to VIN before power is applied.
In Boost PWM mode, Switch A remains closed and Switch B
remains open. Switches C and D operate as a synchronous boost
converter when in this mode.
When the device enters Bypass mode, both high-side FETs are
turned ON, passing the input voltage to the output through the
two high-side FETs and the inductor. In Bypass mode, all other
blocks are turned off to minimize quiescent current
consumption. There should be at least 1ms of time delay
between entry into or exit out of Bypass mode, when
PFM Operation
During PFM operation in Buck mode, Switch D is continuously
closed, and Switch C is continuously open. Switches A and B
operate in Discontinuous mode during PFM operation. During
PFM operation in Boost mode, the ISL91128 closes Switch A and
Switch C to ramp up the current in the inductor. When the
inductor current reaches a certain threshold, the device turns off
Switches A and C, then turns on Switches B and D. With Switches
B and D closed, output voltage increases as the inductor current
ramps down.
transitioning between Bypass mode and a Voltage Regulation
mode. Note there is no overcurrent protection in Bypass mode.
In most operating conditions, there will be multiple PFM pulses
to charge up the output capacitor. These pulses continue until
V
has achieved the upper threshold of the PFM hysteretic
OUT
controller. Switching then stops and remains stopped until V
OUT
decays to the lower threshold of the hysteretic PFM controller.
Switch B stays on after the multiple PFM pulses to hold LX1 to
GND, which reduces EMI noise (see Figure 8 on page 7).
FN8732 Rev.3.00
May 3, 2018
Page 10 of 17
ISL91128
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data (see
Figure 20).
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. The SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 19). Upon
power-up of the ISL91128, the SDA pin is in the Input mode.
The ISL91128 responds with an ACK after recognition of a START
condition followed by a valid identification byte and once again
after successful receipt of a register address byte. The ISL91128
also responds with an ACK after receiving a data byte of a write
operation. The master must respond with an ACK after receiving
a data byte of a read operation.
2
All I C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
ISL91128 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 19). A START condition is ignored
during the power-up sequence and when EN input is low.
A valid Identification byte contains 0b0011100 as the seven
2
MSBs, corresponding to the ISL91128 I C slave address. The LSB
2
All I C interface operations must be terminated by a STOP
of the identification byte is the Read/Write bit. Its value is “1” for
a Read operation and “0” for a Write operation (see Table 2).
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 19). A STOP condition at the end of a write
operation initiates the reconfiguration of the ISL91128’s voltage
feedback loop as necessary to provide the programmed output
voltage.
TABLE 2. IDENTIFICATION BYTE FORMAT
0
0
1
1
1
0
0
R/W
(MSB)
(LSB)
An Acknowledge (ACK), is a software convention used to indicate
a successful data transfer. The transmitting device, either master
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 19. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT
FROM RECEIVER
START
FIGURE 20. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
FN8732 Rev.3.00
May 3, 2018
Page 11 of 17
ISL91128
Write Operation
Read Operation
A write operation requires a START condition, followed by a valid
identification byte (containing the slave address with the R/W bit
set to 0), a valid register address byte, a data byte, and a STOP
condition. After each of the three bytes, the ISL91128 responds
with an ACK. The master sends a STOP to complete the
command.
Figure 22 shows a Read operation. It consists of four bytes.
• The host generates a START condition, then transmits an
Identification byte (containing the slave address with the R/W
bit set to 0).
• The ISL91128 responds with an ACK.
• The host transmits the register address byte and the ISL91128
responds with another ACK.
STOP conditions that terminate write operations must be sent by
the master after sending at least one full data byte and its
associated ACK signal. If a STOP condition is issued in the middle
of a data byte or before one full data byte + ACK is sent, then the
ISL91128 ignores the command and not change output voltage
or other settings.
• The host generates a repeat START condition or a STOP
condition followed by a START condition.
• The host transmits an identification byte (containing the slave
address with the R/W bit set to 1).
• The ISL91128 responds with an ACK, indicating it is ready to
begin providing the requested data.
• The ISL91128 transmits the data byte by asserting control of
the SDA pin while the host generates clock pulses on the SCL
pin.
• When transmission of the data byte is complete, the host
generates a Not Acknowledge (NACK) condition followed by a
2
STOP condition. This completes the I C Read operation.
The ISL91128 register map supports two registers (see Tables 3
through 5). Attempts to read other register addresses are not
supported and should not be attempted. Similarly, the ISL91128
2
does not support I C block reads and writes.
ISL91128 I2C WRITE PROTOCOL
SYSTEM HOST
S
0
0
1
1
1
0
0
0
A
0
0
0
0
0
0
0
0
A
DATA BYTE
A
P
ISL91128
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
I2C SLAVE
7-BIT ADDRESS
REGISTER
ADDRESS = 0x00
DCDV1
(5 BITS)
R/W
P – STOP
2
FIGURE 21. I C REGISTER WRITE PROTOCOL
ISL91128 I2C READ PROTOCOL #1
SYSTEM
HOST
ISL91128
S
0
0
1
1
1
0
0
0
A
0
0
0
0
0
0
0
0
0
A
A
S
P
0
0
1
1
1
0
0
1
A
DATA BYTE
N
P
I2C SLAVE
7-BIT ADDRESS
REGISTER
ADDRESS = 0x00
I2C SLAVE
7-BIT ADDRESS
DCDV1
(5 BITS)
R/W
R/W
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
P – STOP
ISL91128 I2C READ PROTOCOL #2
S
0
0
1
1
1
0
0
0
A
0
0
0
0
0
0
0
S
0
0
1
1
1
0
0
1
A
DATA BYTE
N
P
I2C SLAVE
7-BIT ADDRESS
REGISTER
ADDRESS = 0x00
I2C SLAVE
7-BIT ADDRESS
DCDV1
(5 BITS)
R/W
R/W
2
FIGURE 22. I C REGISTER READ PROTOCOL
FN8732 Rev.3.00
May 3, 2018
Page 12 of 17
ISL91128
TABLE 4. DCDOUT[5:0] VALUE vs OUTPUT VOLTAGE (Continued)
Digital Slew Rate Control
2
DCDOUT[5:0]
0b010000
0b010001
0b010010
0b010011
0b010100
0b010101
0b010110
0b010111
0b011000
0b011001
0b011010
0b011011
0b011100
0b011101
0b011110
0b011111
0b100000
0b100001
0b100010
0b100011
0b100100
0b100101
0b100110
0b100111
0b101000
0b101001
0b101010
0b101011
0b101100
0b101101
0b101110
0b101111
0b110000
0b110001
0b110010
0b110011
0b110100
0b110101
0b110110
0b110111
0b111000
0b111001
0b111010
0b111011
OUTPUT VOLTAGE (V)
2.65
2.70
2.75
2.80
2.85
2.90
3.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
3.70
3.75
3.80
3.85
3.90
3.95
4.00
4.05
4.10
4.15
4.20
4.25
4.30
4.35
4.40
4.45
4.50
4.55
4.60
4.65
4.70
4.75
4.80
When changing voltages using the I C interface, the ISL91128
can be programmed to control the rate of voltage increase or
decrease as it transitions from one voltage setting to the next.
Details about the digital slew rate settings can be found in
Table 5 on page 14.
Register Description
2
The ISL91128 has two I C accessible control registers that set
output voltage, operating mode, and digital slew rate.
TABLE 3. REGISTER ADDRESS 0x00: VOLTAGE CONTROL
BIT NAME TYPE RESET
5:0 DCDOUT R/W 00000 V
DESCRIPTION
programming. See Table 4.
OUT
6
ULTRA R/W
0
Ultrasonic mode select. Not applicable in
forced PWM mode:
0: Ultrasonic feature disabled
1: Ultrasonic feature enabled
2
7
I2CEN R/W
0
I C programming enable bit:
2
0: Device ignores I C command, and uses
factory programmed default DCDOUT and
ULTRA settings.
1: Device uses the I C programmed
DCDOUT and ULTRA settings.
2
Bits DCDOUT[5:0] set the output voltage, as shown in Equation 1
and Table 4. The ISL91128 output voltage range is 1.90V to 5.0V.
(EQ. 1)
V
= 1.9V + n – 1 0.05 where n = 1 to 63
OUT
The power-up output voltage will be at 3.3V. To change to other
voltages after power-up, write the VOLTAGE CONTROL register for
3.3V (0b011101) before enabling the ‘I2CEN’ bit in the VOLTAGE
CONTROL register. Then enable the ‘I2CEN’ bit and write the
desired output voltage code to the VOLTAGE CONTROL register.
TABLE 4. DCDOUT[5:0] VALUE vs OUTPUT VOLTAGE
DCDOUT[5:0]
OUTPUT VOLTAGE (V)
0b000001
0b000010
0b000011
0b000100
0b000101
0b000110
0b000111
0b001000
0b001001
0b001010
0b001011
0b001100
0b001101
0b001110
0b001111
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
FN8732 Rev.3.00
May 3, 2018
Page 13 of 17
ISL91128
TABLE 4. DCDOUT[5:0] VALUE vs OUTPUT VOLTAGE (Continued)
Inductor Selection
DCDOUT[5:0]
0b111100
0b111101
0b111110
0b111111
OUTPUT VOLTAGE (V)
Use an inductor with high frequency core material (for example,
ferrite core) to minimize core losses and provide good efficiency.
The inductor must be able to handle the peak switching currents
without saturating.
4.85
4.90
4.95
5.00
A 1µH inductor with ≥4A saturation current rating is
recommended. Select an inductor with low DCR to provide good
efficiency. In applications in which radiated noise must be
minimized, a toroidal or shielded inductor can be used (refer to
Table 7).
TABLE 5. REGISTER ADDRESS 0x01: MODE CONTROL
BIT
NAME
TYPE
R/W
RESET
000
DESCRIPTION
2:0 SLEWRATE
Slew rate control (typical),
expressed as µs per LSB
change in DCDOUT value:
0b000 = 0.8µs/LSB
0b001 = 1.6µs/LSB
0b010 = 3.2µs/LSB
0b011 = 6.4µs/LSB
0b100 = 12.8µs/LSB
0b101 = 25.6µs/LSB
0b110 = 51.2µs/LSB
0b111 = 102.4µs/LSB
PVIN and V
Capacitor Selection
OUT
The input and output capacitors should be ceramic X5R type with
low ESL and ESR. The recommended input capacitor value is
2x10µF. The recommended V
OUT
capacitor value is 2x22µF.
TABLE 6. CAPACITOR VENDOR INFORMATION
MANUFACTURER
AVX
SERIES
X5R
WEBSITE
www.avx.com
Murata
Taiyo Yuden
TDK
X5R
www.murata.com
www.t-yuden.com
www.tdk.com
3
4
5
MODE
R/W
0
0
0
Mode control, 1 = Forced PWM
0 = Auto PFM/PWM
X5R
X5R
DISCHARGE R/W
Soft discharge, 1 = Active,
0 = OFF
Recommended PCB Layout
Correct PCB layout is critical for proper operation of the
ISL91128. The input and output capacitors should be positioned
as close to the IC as possible. The ground connections of the
input and output capacitors should be kept as short as possible,
and should be on the component layer to avoid problems that are
caused by high switching currents flowing through PCB vias.
Bypass
R/W
Bypass entry: 1 = Disable
Bypass mode, 0 = Enable
Bypass mode
7:6
Reserved
R/W
00
Applications Information
Component Selection
The ISL91128 requires only three external power components to
implement the buck-boost converter: an inductor, an input
capacitor, and an output capacitor.
TABLE 7. INDUCTOR VENDOR INFORMATION
MANUFACTURER
PART NUMBER
MANUFACTURER
Toko
DESCRIPTION
DIMENSION (mm)
3.2x2.5x1.2
WEBSITE
1277AS-H-1R0M
FDSD0312-H-1R0M
XFL4020-102ME
1µH, 20%, DCR = 34mΩtypicalI
= 4.6A (typical)
= 4.5A (typical)
= 5.1A (typical)
www.toko.com
SAT
SAT
SAT
1µH, 20%, DCR = 43mΩtypicalI
1µH, 20%, DCR = 11mΩtypicalI
3.2x3.0x1.2
Coilcraft
4.0x4.0x2.1
www.coilcraft.com
FN8732 Rev.3.00
May 3, 2018
Page 14 of 17
ISL91128
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
FN8732.3
CHANGE
May 3, 2018
Added a test condition for Input Voltage Range on page 4.
Removed About Intersil section and updated disclaimer.
Jul 7, 2017
FN8732.2
FN8732.1
Table 4 on page 14, 0b111110 output voltage changed from 5.95 to 4.95.
Jun 15, 2017
Updated Related Literature section on page 1.
Updated Table 1 on page 3.
- changed “VSEL” column to “Dynamic Voltage Scaling” and made ISL91128 parameter “Yes”.
- removed “and DVS” from I2C column.
Added ISL91128EVKIT1Z to ordering information table on page 3
Removed ISLUSBMINIEVAL1Z (dongle and cables) from ordering information table on page 3 - the kit includes
the dongle and cables and they will not be offered as a stand-alone item.
Aug 3, 2016
FN8732.0
Initial release
FN8732 Rev.3.00
May 3, 2018
Page 15 of 17
ISL91128
For the most recent package outline drawing, see W4x5.20M.
Package Outline Drawing
W4x5.20M
20 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP 0.4mm PITCH)
Rev 0, 01/15
X
0.400
1.74 ±0.030
Y
20x 0.265 ±0.035
E
D
C
B
A
2.15 ±0.030
0.275
0.10
(4X)
1
2
3
4
PIN 1
0.200
(A1 CORNER)
0.270
TOP VIEW
BOTTOM VIEW
Z
SEATING PLANE
3
PACKAGE
OUTLINE
0.05 Z
0.240
0.400
0.290
2
0.265 ±0.035 x20
0.10
0.05
Z X Y
Z
4
0.200 ±0.030
NSMD
6
0.500 ±0.050
RECOMMENDED LAND PATTERN
SIDE VIEW
NOTES:
10. Dimensions and tolerance per ASMEY 14.5 - 1994.
11. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
12. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
13. Bump position designation per JESD 95-1, SPP-010.
14. All dimensions are in millimeters.
15. NSMD refers to non-solder mask defined pad design per TB451.
FN8732 Rev.3.00
May 3, 2018
Page 16 of 17
Notice
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http://www.renesas.com
Renesas Electronics America Inc.
1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.
Tel: +1-408-432-8888, Fax: +1-408-434-5351
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 1709 Quantum Plaza, No.27 ZhichunLu, Haidian District, Beijing, 100191 P. R. China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, 200333 P. R. China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
© 2018 Renesas Electronics Corporation. All rights reserved.
Colophon 7.0
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