ISL9237 [RENESAS]
Buck-Boost Narrow VDC Battery Charger with SMBus Interface and USB OTG;
| 型号： | ISL9237 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Buck-Boost Narrow VDC Battery Charger with SMBus Interface and USB OTG 电池 |
| 文件： | 总40页 (文件大小：1606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL9237
FN8723
Rev.5.00
Nov 29, 2017
Buck-Boost Narrow VDC Battery Charger with SMBus Interface and USB OTG
The ISL9237 is a buck-boost Narrow Output Voltage DC (NVDC)
Features
charger utilizing Intersil’s advanced R3™ Technology to provide
• Buck-boost NVDC charger for 1-, 2- or 3-cell Li-ion batteries
• Input voltage range 3.2V to 23.4V (no dead zone)
• System output voltage 2.4V to 13.824V
• System power monitor PSYS output, IMVP-8 compliant
• Up to 1MHz switching frequency
high light-load efficiency, fast transient response and
seamless DCM/CCM transitions for a variety of mobile and
industrial applications.
In Charge mode, the ISL9237 takes input power from a wide
range of DC power sources (conventional AC/DC charger
adapters, USB PD ports, travel adapters, etc.) and safely
charges battery packs with up to 3 cells in a series
configuration.
• LDO output for charger VDD
• Adapter current monitor (AMON)
ISL9237 supports On-the-Go (OTG) function for 2- and 3-cell
battery applications. When OTG function is enabled, the
ISL9237 operates in the reverse Buck mode to provide 5V at
the USB port.
• Battery discharging current monitor (BMON)
• PROCHOT# open-drain output, IMVP-8 compliant
• Allows trickle charging of depleted battery
• Optional ASGATE FET control
As a NVDC topology charger, it also regulates the system
output to a narrow DC range for stable system bus voltage. The
system power can be provided from the adapter, battery or a
combination of both. The ISL9237 can operate with only a
battery, only an adapter or both connected. For Intel IMVP8
compliant systems, the ISL9237 includes PSYS functionality,
which provides an analog signal representing total platform
power. The PSYS output will connect to a wide range of Intersil
IMVP8 core regulators to provide an IMVP8 compliant power
domain function.
• Ideal diode control in Turbo mode
• Supports OTG function for 2- and 3-cell batteries
2
• SMBus and auto-increment I C compatible
• Two-level adapter current limit available
• Pb-free (RoHS compliant)
• Package 4x4 32 Ld QFN
Applications
2
The ISL9237 has serial communication via SMBus/I C that
• Mobile devices with rechargeable batteries
allows programming of many critical parameters to deliver a
customized solution. These programming parameters include,
but are not limited to: Adapter current limit, charger current
limit, system voltage setting and trickle charging current limit.
• Industrial devices with rechargeable batteries
Related Literature
• For a full list of related documents please visit our web page
- ISL9237 product page
OPTIONAL
VADP
R
s1
VSYS
Q1
Q2
Q4
L1
Q3
VSYS
CSOP
CSIN
CSIP
R
s2
ASGATE
CSON
ADP
ACIN
ISL9237
GND
ACOK
PROCHOT#
AMON/BMON
BATGONE
BGATE
V
BAT
VBAT
OTGPG/CMOUT
OTGEN/CMIN
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FN8723 Rev.5.00
Nov 29, 2017
Page 1 of 40
ISL9237
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SMBUS Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SMBus Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
SMBus and I C Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ISL9237 SMBus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting Charging Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Setting Adapter Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Setting Two-Level Adapter Current Limit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Setting Maximum Charging Voltage or System Regulating Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Setting Minimum System Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Setting PROCHOT# Threshold for Adapter Overcurrent Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Setting PROCHOT# Threshold for Battery Over Discharging Current Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Setting PROCHOT# Debounce Time and Duration Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
OTGVoltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
OTGCurrent Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ISL9237 Buck-Boost Charger with USB OTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Programming Charger Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Battery Learn Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Turbo Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Two-Level Adapter Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PSYS Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Trickle Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
System Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Charger Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
USB OTG (On-the-Go) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Stand-Alone Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
System Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Way Overcurrent Protection (WOCP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Over-Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Switching Power MOSFET Gate Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Adapter Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Select the LC Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Select the Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FN8723 Rev.5.00
Nov 29, 2017
Page 2 of 40
ISL9237
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
PART MARKING
ISL9237HRZ
923 7HRZ
-10 to +100
32 Ld 4x4 QFN
L32.4x4A
ISL9237EVAL2Z
NOTES:
Evaluation Board
1. Add “-T” suffix for 6k unit, “-TK” suffix for 1k unit, or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel
specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL9237. For more information on MSL, please see tech brief TB363.
Pin Configuration
ISL9237
(32 LD 4x4 QFN)
TOP VIEW
32 31 30 29 28 27 26 25
CSON
CSOP
ACOK
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PROCHOT#
SCL
VSYS
BOOT2
UGATE2
PHASE2
LGATE2
VDDP
SDA
GND
(BOTTOM PAD)
OTGEN/CMIN
ACIN
VDD
DCIN
9
10 11
12 13 14 15 16
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
BOTTOM PAD
GND
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. It should also be used as the
thermal pad for heat dissipation.
1
2
3
CSON
CSOP
VSYS
Battery current sense “–” input. Connect to battery current resistor negative input. Place a 0.1µF ceramic capacitor
between CSOP to CSON to provide differential mode filtering.
Battery current sense “+” input. Connect to battery current resistor positive input. Place a 0.1µF ceramic capacitor
between CSOP to CSON to provide differential mode filtering.
Provides feedback voltage for MaxSystemVoltage regulation.
FN8723 Rev.5.00
Nov 29, 2017
Page 3 of 40
ISL9237
Pin Descriptions(Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
4
BOOT2
High-side MOSFET Q4 gate driver supply. Connect an MLCC capacitor across the BOOT2 pin and the PHASE2 pin. The
boot capacitor is charged through an internal boot diode connected from the VDDP pin to the BOOT2 pin when the
PHASE2 pin drops below VDDP minus the voltage drop across the internal boot diode.
5
6
UGATE2
PHASE2
High-side MOSFET Q4 gate drive.
Current return path for the high-side MOSFET Q4 gate drive. Connect this pin to the node consisting of the high-side
MOSFET Q4 source, the low-side MOSFET Q3 drain and the one terminal of the inductor.
7
8
LGATE2
VDDP
Low-side MOSFET Q3 gate drive.
Power supply for the gate drivers. Connect to VDD pin through a 4.7Ω resistor and connect a 1µF ceramic capacitor to
GND.
9
LGATE1
PHASE1
Low-side MOSFET Q2 gate drive.
10
Current return path for the high side MOSFET Q1 gate drive. Connect this pin to the node consisting of the high-side
MOSFET Q1 source, the low-side MOSFET Q2 drain and the input terminal of the inductor.
11
12
UGATE1
BOOT1
High-side MOSFET Q1 gate drive.
High-side MOSFET Q1 gate driver supply. Connect an MLCC capacitor across the BOOT1 pin and the PHASE1 pin. The
boot capacitor is charged through an internal boot diode connected from the VDDP pin to the BOOT1 pin when the
PHASE1 pin drops below VDDP minus the voltage drop across the internal boot diode.
13
ASGATE
Gate drive output to the P-channel adapter FET. The use of ASGATE FETs is optional, if not used, leave ASGATE pin
floating.
When ASGATE turns on, it is clamped 10V below ADP pin voltage.
14
15
CSIN
CSIP
Adapter current sense “-” input.
Adapter current sense “+” input. The modulator also uses this for sensing input voltage in forward mode and output
voltage in reverse mode.
16
17
18
ADP
DCIN
VDD
Adapter input. Used to sense adapter voltage. When adapter voltage is higher than 3.2V, AGATE is turned on.
ADP pin is also one of the two internal low power LDO inputs.
Input of an internal LDO; provides power to the IC. Connect a diode OR from adapter and system outputs. Bypass this
pin with an MLCC capacitor.
Output of the internal LDO; provides the bias power for the internal analog and digital circuit. Connect a 1µF ceramic
capacitor to GND.
If VDD is pulled below 2V for more than 1ms, ISL9237 will reset all the SMBus register values to the default.
19
20
ACIN
Adapter voltage sense. Use a resistor divider externally to detect adapter voltage. The adapter voltage is valid if the ACIN
pin voltage is greater than 0.8V.
OTGEN/
CMIN
OTG function enable pin or stand-alone comparator input pin.
Pull high to enable OTG function. The OTG function is enabled when the control register is written to select OTG mode
and when the battery voltage is above 5.8V.
When OTG function is not selected, this pin is the general purpose stand-alone comparator input.
21
22
SDA
SCL
SMBus data I/O. Connect to the data line from the host controller or smart battery. Connect a 10k pull-up resistor
according to SMBus specification.
SMBus clock I/O. Connect to the clock line from the host controller or smart battery. Connect a 10k pull-up resistor
according to SMBus specification.
23
24
25
PROCHOT# Open-drain output. Pulled low when ACProchot#, DCProchot# or Low_VSYS event is detected. IMVP-8 compliant.
ACOK
Adapter presence indicator output to indicate the adapter is ready.
BATGONE
Input pin to the IC. Logic high on this pin indicates the battery has been removed. Logic low on this pin indicates the
battery is present.
BATGONE pin logic high will force BGATE FET to turn off in any circumstance.
26
OTGPG/
CMOUT
Open-drain output. OTG function output power-good indicator or the stand-alone comparator output.
When OTG function is enabled, low if OTG output voltage is not within regulation window.
When OTG function is not used, it is the general purpose comparator output.
FN8723 Rev.5.00
Nov 29, 2017
Page 4 of 40
ISL9237
Pin Descriptions(Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
27
PROG
A resistor from PROG pin to GND sets the following configurations:
1. Default number of the battery cells in series, 1-, 2- or 3-cell.
2. Default switching frequency 733kHz or 1MHz.
3. Default adapter current limit value 0.476A or 1.5A.
Refer to Table 18 for programming options.
28
29
COMP
Error amplifier output. Connect a compensation network externally from COMP to GND.
Adapter current monitor output or battery discharging current monitor output.
AMON/
BMON
V
= 18 x (V
- V
); V
= 18 x (V )
- V
AMON
CSIP CSIN BMON
CSON CSOP
30
31
PSYS
VBAT
Current source output that indicates the whole platform power consumption.
Battery voltage sensing. Used for trickle charging detection and ideal diode mode control. The VBAT pin is also one of
the two internal low power LDO inputs.
32
BGATE
Gate drive output to the P-channel FET connecting the system and the battery. This pin can go high to disconnect the
battery, low to connect the battery or operate in a linear mode to regulate trickle charge current during trickle charge.
ISL9237 pulls down BGATE to GND to turn on BGATE PFET. Therefore, BGATE PFET gate-to-source voltage rating should
be higher than the battery voltage.
Simplified Application Circuit
OPTIONAL
Rs1
VSYS
VADP
20m
Q1
Q2
Q4
Q3
L1
VSYS
CSOP
CSIN
CSIP
Rs2
10m
ASGATE
CSON
ADP
ACIN
ISL9237
GND
ACOK
BGATE
PROCHOT#
AMON/BMON
BATGONE
VBAT
VBAT
OTGPG/CMOUT
PSYS
OTGEN/CMIN
VADP
VSYS
FIGURE 2. SIMPLIFIED APPLICATION DIAGRAM
FN8723 Rev.5.00
Nov 29, 2017
Page 5 of 40
ISL9237
Absolute Maximum Ratings
Thermal Information
CSIP, CSIN, DCIN, ADP, ASGATE . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
PHASE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +28V
PHASE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND-2V(<20ns) to +28V
BOOT1, UGATE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +33V
PHASE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +15V
PHASE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 2V(<20ns) to +15V
BOOT2, UGATE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to +20V
LGATE1, LGATE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to +6.5V
LGATE1, LGATE2 . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 2V(<20ns) to +6.5V
VBAT, VSYS, CSOP, CSON, BGATE . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
VDD, VDDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
AMON/BMON, PSYS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
OTGEN, BATGONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
ACIN, ACOK, PROCHOT#, OTGPG . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
CLK, DAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
BOOT1-PHASE1, BOOT2-PHASE2 . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
CSIP-CSIN, CSOP-CSON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +0.5V
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA
ACIN, SDA, SCL, DCIN, ACOK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA
ESD Rating
Thermal Resistance (Typical)
32 Ld QFN Package (Notes 4, 5) . . . . . . . .
Ambient Temperature Range (T ) . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Junction Temperature Range (T ) . . . . . . . . . . . . . . . . . . . .-10°C to +150°C
Storage Temperature Range (T ) . . . . . . . . . . . . . . . . . . . .-65°C to +175°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
(°C/W)
38
(°C/W)
3.5
JA
JC
A
J
S
Recommended Operating Conditions
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101A) . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For , the "case temp" location is the center of the ceramic on the package underside.
JC
Electrical Specifications Operating conditions: ADP = CSIP = CSIN = 5V and 20V, VSYS = V
= CSOP = CSON = 8V, unless otherwise
noted. Boldface limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified.
BAT
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6) UNIT
UVLO/ACOK
VADP UVLO Rising (Note 7)
VADP_UVLO_r
VADP_UVLO_h
VBAT_UVLO_r
VBAT_UVLO_h
VBAT_5P8_r
VBAT_5P8_h
VDD_2P7_r
3.1
3.2
600
2.45
350
5.95
600
2.70
3.4
V
mV
V
VADP UVLO Hysteresis (Note 7)
V
V
V
V
UVLO Rising
2.30
5.50
2.55
2.60
6.45
2.85
BAT
BAT
BAT
BAT
UVLO Hysteresis
5P8V Rising
mV
V
5P8V Hysteresis
mV
V
VDD 2P7 POR Rising, SMBus and
BGATE/BMON Active Threshold
VDD 2P7 POR Hysteresis (Note 7)
VDD_2P7_h
VDD_3P8_r
150
3.8
mV
V
VDD 3P8 POR Rising, Modulator and
Gate Driver Active (Note 7)
VDD 3P8 POR Hysteresis (Note 7)
ACIN Rising
VDD_3P8_h
ACIN_r
150
0.8
50
mV
V
0.775
0.825
ACIN Hysteresis
ACIN_h
mV
FN8723 Rev.5.00
Nov 29, 2017
Page 6 of 40
ISL9237
Electrical Specifications Operating conditions: ADP = CSIP = CSIN = 5V and 20V, VSYS = V
= CSOP = CSON = 8V, unless otherwise
noted. Boldface limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified. (Continued)
BAT
MIN
MAX
PARAMETER
LINEAR REGULATOR
SYMBOL
TEST CONDITIONS
(Note 6)
4.5
TYP
(Note 6) UNIT
VDD Output Voltage
VDD Dropout Voltage
VDD Overcurrent Threshold
Battery Current
VDD
6V < V
< 23V, no load
5.0
110
70
5.5
V
DCIN
30mA, V
VDD_dp
VDD_OC
= 4V
mV
mA
µA
DCIN
40
110
I
I
I
Battery only, BGATE on, PSYS OFF, BMON OFF,
= 12V, DCIN current comes from battery,
12
30
BAT1
BAT2
BAT3
V
I
BAT
= I
+ I
+ I
+ I + I
BAT VBAT CSOP
Battery only, BGATE on, PSYS OFF, BMON ON,
= 12V, DCIN current comes from battery,
CSON DCIN VSYS
74
µA
µA
V
I
BAT
= I
+ I
+ I
+ I + I
BAT VBAT CSOP
Battery only, BGATE on, PSYS ON, BMON OFF,
= 12V, DCIN current comes from battery,
CSON DCIN VSYS
940
1025
V
I
BAT
= I
+ I
+ I
+ I + I
BAT VBAT CSOP
CSON DCIN VSYS
INPUT CURRENT REGULATION, R = 20mΩ
s1
Input Current Accuracy
CSIP - CSIN = 80mV
CSIP - CSIN = 40mV
CSIP - CSIN = 10mV
4
2
A
%
-2
2
A
-2.5
-10
2.5
10
%
0.5
A
%
Adapter Current PROCHOT# Threshold
= 20mΩ
I
ACProchot = 0x0A80H (2688mA)
ACProchot = 0x0400H (1024mA)
2688
1027
mA
%
ADP_HOT_TH10
R
s1
-3.0
-6.0
3.0
6.0
mA
%
VOLTAGE REGULATION
Maximum System Voltage Regulation
Accuracy
MaxSystemVoltage for 1-cell, (4.2V)
-0.75
-0.50
-3
0.75
0.50
3
%
%
%
MaxSystemVoltage for 2-cell and 3-cell
Minimum System Voltage Regulation
Accuracy
Input Voltage Regulation Accuracy
-3
3
%
CHARGE CURRENT REGULATION, R = 10mΩ
s2
Charge Current Accuracy
CSOP - CSON = 60mV
CSOP - CSON = 20mV
CSOP - CSON = 10mV
CSOP - CSON = 5mV
6
2
A
%
A
-2.5
-5
2.5
5
%
A
1
-10
-20
10
20
%
A
0.5
%
FN8723 Rev.5.00
Nov 29, 2017
Page 7 of 40
ISL9237
Electrical Specifications Operating conditions: ADP = CSIP = CSIN = 5V and 20V, VSYS = V
= CSOP = CSON = 8V, unless otherwise
noted. Boldface limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified. (Continued)
BAT
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6) UNIT
TRICKLE CHARGING CURRENT REGULATION, R = 10mΩ
s2
Trickle Charge Current Accuracy
Trickle, options 256mA and 512mA
Trickle, option 128mA
-20
-30
1.5
20
30
%
%
V
Fast Charge to Trickle Charge
Threshold
V
rising
1.7
92
1.9
BGATE
Trickle Charge to Fast Charge
Threshold Hysteresis
65
125
mV
IDEAL DIODE MODE
Entering Ideal Diode Mode VSYS
Voltage Threshold
BGATE off, VSYS falling
- V
150
150
mV
mA
V
VBAT VSYS
R = 10mΩ
s2
Exiting Ideal Diode Mode Battery
Current Threshold
BGATE Source
BGATE Sink
VSYS - BGATE = 2V
BGATE - GND = 2V
12
4
17
6
20
10
mA
mA
AMON/BMON
INPUT CURRENT SENSE AMPLIFIER, R = 20mΩ
s1
AMON Gain
17.91
0.4
V/V
%
AMON Accuracy
V
- V
CSIP CSIN
= 100mV (5A), CSIP = 5V, 20V
= 20mV (1A), CSIP = 5V, 20V
-2
2
V
= 17.91 (CSIP - CSIN)
AMON
V - V
CSIP CSIN
-5.0
5.0
%
V
V
V
- V
= 10mV (0.5A), CSIP = 5V, 20V
= 2mV (0.1A), CSIP = 5V, 20V
= 0V
-10
-40
1
4
10
40
30
%
%
CSIP CSIN
- V
CSIP CSIN
AMON Minimum Output Voltage
- V
CSIP CSIN
mV
DISCHARGE CURRENT SENSE AMPLIFIER, R = 10mΩ
s2
BMON Gain
17.95
-0.15
-0.68
V/V
%
BMON Accuracy
V
- V
CSON CSOP
= 100mV (10A), V
= 8V
= 8V
-2.00
-5.00
2.00
5.00
CSON
V
= 17.95 (V )
- V
BMON
CSON CSOP
V - V
CSON CSOP
= 20mV (2A), V
= 10mV (1A), V
%
CSON
V
V
V
- V
= 8V
= 8V
-10.0
-20.0
-1.3
-2.2
10.0
20.0
30
%
%
CSON CSOP
CSON
- V
CSON CSOP
= 6mV (0.6A), V
= 0V
CSON
BMON Minimum Output Voltage
Discharging Current PROCHOT#
- V
CSON CSOP
mV
mA
%
I
DCProchot = 0x1000H (4096mA)
DCProchot = 0x0C00H (3072mA)
4096
3072
DIS_HOT_TH5
Threshold, R = 10mΩ
s2
-3
-5
3
mA
%
5
5
5
AMON/BMON Source Resistance
AMON/BMON Sink Resistance
Ω
Ω
ACOK, PROCHOT#, OTGPG/CMOUT (OPEN-DRAIN)
Open-Drain Current
1
µA
BATGONE AND OTGEN
High-Level Input Voltage
Low-Level Input Voltage
0.9
V
V
0.4
1
Input Leakage Current
V
= 3.3V, 5V; V
OTGEN
= 3.3V, 5V
µA
BATGONE
PROCHOT#
PROCHOT# Debounce Time (Note 7)
Prochot# Debounce register Bit<1:0> = 11
Prochot# Debounce register Bit<1:0> = 10
1
ms
µs
500
FN8723 Rev.5.00
Nov 29, 2017
Page 8 of 40
ISL9237
Electrical Specifications Operating conditions: ADP = CSIP = CSIN = 5V and 20V, VSYS = V
= CSOP = CSON = 8V, unless otherwise
noted. Boldface limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified. (Continued)
BAT
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
Prochot# Duration register Bit<2:0> = 011
Prochot# Duration register Bit<2:0> = 001
Control1 register Bit<9:8> = 00
(Note 6)
TYP
10
(Note 6) UNIT
PROCHOT# Duration Time (Note 7)
ms
ms
20
Low VSYS PROCHOT# Trip Threshold
V
5.8
6.1
6.4
6.7
6.0
6.3
6.6
6.9
6.2
6.5
6.8
7.1
V
V
V
V
LOW_VSYS_HOT
Control1 register Bit<9:8> = 01
Control1 register Bit<9:8> = 10
Control1 register Bit<9:8> = 11
PSYS
PSYS Output Current
I
V
V
= 19V, V
= 80mV,
= 0mV
109
36
24
12
2
µA
%
PSYS
CSIP
BAT
CSIP-CSIN
R
R
= 20mΩ
= 10mΩ
= 12V, V
s1
s2
CSOP-CSON
-5
-6
5
6
V
V
= 19V, V
= 0mV,
= 20mV
µA
%
CSIP
BAT
CSIP-CSIN
= 12V, V
CSOP-CSON
V
V
= 19V, V
= 8.4V, V
= 0mV,
= -20mV
µA
%
CSIP
BAT
CSIP-CSIN
CSOP-CSON
-7
7
V
V
= 0V, V
CSIP-CSIN
= 0mV,
= -10mV
µA
%
CSIP
BAT
= 8.4V, V
CSOP-CSON
-8.5
8.5
Maximum PSYS Output Voltage
V
I
= 200µA
V
PSYS_MAX
PSYS
OTG
OTG Voltage
OTG Current
OTGVoltage register = 5.12V
OTGCurrent register = 512mA
OTGCurrent register = 1024mA
OTGCurrent register = 4096mA
5.04
435
5.11
512
5.18
589
V
mA
mA
mA
922
1024
4096
1126
4220
3975
GENERAL PURPOSE COMPARATOR
General Purpose Comparator Rising
Threshold
Reference = 1.2V
Reference = 2V
Reference = 1.2V
Reference = 2V
1.15
1.95
25
1.20
2.00
40
1.25
2.05
65
V
V
General Purpose Comparator
Hysteresis
mV
mV
25
40
65
PROTECTION
VSYS Overvoltage Rising Threshold
VSYS Overvoltage Hysteresis
MaxSystemVoltage register value = 8.4V
8.79
185
8
8.96
280
12
9.18
380
18
V
mV
A
Adapter Way Overcurrent Rising
Threshold
Adapter Way Overcurrent Hysteresis
2.8
10
3.5
15
4.2
24
A
A
Battery Discharge Way Overcurrent
Rising Threshold (Note 7)
R
R
= 20mΩ
= 10mΩ
s1
s2
Battery Discharge Way Overcurrent
Hysteresis (Note 7)
2.56
3.20
3.84
A
Over-Temperature Threshold (Note 7)
Adapter Overvoltage Rising Threshold
Adapter Overvoltage Hysteresis
MISCELLANEOUS
140
22.5
200
150
23.4
400
160
24
°C
V
600
mV
Switching Frequency Accuracy
1MHz Oscillator
All programmed fSW settings
-15
0.85
-15
15
1.15
15
%
MHz
%
1.00
0
Digital Debounce Time Accuracy
(Note 7)
BGATE_Low Voltage
VSYS = 8V
-10
10
mV
FN8723 Rev.5.00
Nov 29, 2017
Page 9 of 40
ISL9237
Electrical Specifications Operating conditions: ADP = CSIP = CSIN = 5V and 20V, VSYS = V
= CSOP = CSON = 8V, unless otherwise
noted. Boldface limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified. (Continued)
BAT
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
VADP = 23V, VADP - ASGATE
(Note 6)
8
TYP
11
(Note 6) UNIT
ASGATE_Low Voltage Clamp
12
V
V
Battery Learn Mode Auto-Exit
Threshold
MinSystemVoltage = 5.376V
Control1 register Bit<13> = 1
5.05
5.70
Battery Learn Mode Auto-Exit
Hysteresis (Note 7)
80
160
320
mV
SMBus
SDA/SCL Input Low Voltage
SDA/SCL Input High Voltage
SDA/SCL Input Bias Current
SDA, Output Sink Current
GATE DRIVER (Note 7)
0.8
1
V
V
2
4
µA
mA
SDA = 0.4V, on
UGATE1 Pull-Up Resistance
UGATE1 Source Current
UGATE1 Pull-Down Resistance
UGATE1 Sink Current
UG1
UG1
UG1
UG1
LG1
LG1
100mA source current
UGATE1 - PHASE1 = 2.5V
100mA sink current
800
2
1200
475
mΩ
A
RPU
SRC
RPD
SNK
RPU
SRC
RPD
SNK
RPU
SRC
RPD
SNK
RPU
1.3
1.9
1.3
2.3
1.3
2.3
1.3
350
2.8
800
2
mΩ
A
UGATE1 - PHASE1 = 2.5V
100mA source current
LGATE1 - GND = 2.5V
100mA sink current
LGATE1 Pull-Up Resistance
LGATE1 Source Current
LGATE1 Pull-Down Resistance
LGATE1 Sink Current
1200
450
mΩ
A
LG1
LG1
LG2
LG2
LG2
LG2
UG2
300
3.5
800
2
mΩ
A
LGATE1 - GND = 2.5V
100mA source current
LGATE2 - GND = 2.5V
100mA sink current
LGATE2 Pull-Up Resistance
LGATE2 Source Current
LGATE2 Pull-Down Resistance
LGATE2 Sink Current
1200
450
mΩ
A
300
3.5
800
2
mΩ
A
LGATE2 - GND = 2.5V
100mA source current
UGATE2 - PHASE2 = 2.5V
100mA sink current
UGATE2 Pull-Up Resistance
UGATE2 Source Current
UGATE2 Pull-Down Resistance
UGATE2 Sink Current
1200
475
mΩ
A
UG2
UG2
UG2
SRC
RPD
SNK
350
2.8
20
mΩ
A
UGATE2 - PHASE2 = 2.5V
1.9
10
15
15
10
UGATE1 to LGATE1 Dead Time
LGATE1 to UGATE1 Dead Time
LGATE2 to UGATE2 Dead Time
UGATE2 to LGATE2 Dead Time
t
t
t
t
40
45
40
40
ns
UG1LG1DEAD
LG1UG1DEAD
LG2UG2DEAD
UG2LG2DEAD
25
ns
22
ns
20
ns
SMBUS Timing Specification (Note 7)
MIN
MAX
PARAMETERS
SMBus Frequency
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6) UNIT
f
10
4.7
4
400
kHz
µs
µs
µs
µs
ns
ns
µs
µs
SMB
Bus Free Time
t
BUF
Start Condition Hold Time from SCL
Start Condition Set-Up Time from SCL
Stop Condition Set-Up Time from SCL
SDA Hold Time from SCL
SDA Set-up Time from SCL
SCL Low Period
t
HD:STA
t
4.7
4
SU:STA
SU:STO
HD:DAT
t
t
300
250
4.7
4
t
SU:DAT
t
LOW
SCL High Period
t
HIGH
FN8723 Rev.5.00
Nov 29, 2017
Page 10 of 40
ISL9237
SMBUS Timing Specification (Note 7)
MIN
MAX
PARAMETERS
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
175
(Note 6) UNIT
SMBus Inactivity Timeout
Maximum charging period without a SMBus
Write to MaxSystemVoltage or ChargeCurrent
register
s
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits established by characterization and are not production tested.
Buck Mode Gate Driver Timing Diagram
PWM
tLGFUGR
t
FU
t
RU
1V
UGATE
LGATE
1V
t
RL
t
FL
tUGFLGR
t
t
= t
= t
LGFUGR
UGFLGR
LG1UG1DEAD
UG1LG1DEAD
FIGURE 3. BUCK MODE GATE DRIVER TIMING DIAGRAM
FN8723 Rev.5.00
Nov 29, 2017
Page 11 of 40
ISL9237
Typical Performance
FIGURE 4. ADAPTER INSERTION, V
ADP
= 2OV, V
= 7.5V,
FIGURE 5. ADAPTER INSERTION, V
ADP
= 2OV, V
= 7.5V,
BAT
BAT
CHARGECURRENT = 0A, ADAPTER INSERTION
CHARGECURRENT = 0A
DEBOUNCE = 1.3s
FIGURE 6. ADAPTER INSERTION, V
ADP
= 2OV, V
= 7.5V,
BAT
FIGURE 7. ADAPTER REMOVAL, V
= 2OV, V = 7.5V,
BAT
ADP
CHARGECURRENT = 0A, ADAPTER INSERTION
CHARGECURRENT = 0A
DEBOUNCE = 1.3s
FIGURE 8. ADAPTER VOLTAGE RAMPS UP, BOOST ->
BUCK-BOOST -> BUCK OPERATION MODE TRANSITION
FIGURE 9. ADAPTER VOLTAGE RAMPS DOWN, BUCK ->
BUCK-BOOST -> BOOST OPERATION MODE TRANSITION
FN8723 Rev.5.00
Nov 29, 2017
Page 12 of 40
ISL9237
Typical Performance(Continued)
FIGURE 11. BOOST MODE, CHARGING CURRENT LOOP TO ADAPTER
CURRENT LOOP TRANSITION. V = 5V,
FIGURE 10. BOOST MODE, OUTPUT VOLTAGE LOOP TO ADAPTER
CURRENT LOOP TRANSITION. V
MAXSYSTEMVOLTAGE = 8.496V, V
= 5V,
= 7V, SYSTEM
ADP
MAXSYSTEMVOLTAGE = 8.496V, V
ADP
= 7V, SYSTEM
BAT
BAT
LOAD 0.5A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 1A
LOAD 0.5A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 0A
FIGURE 12. BUCK-BOOST MODE, OUTPUT VOLTAGE LOOP TO
FIGURE 13. BUCK-BOOST MODE, CHARGING CURRENT LOOP TO
ADAPTER CURRENT LOOP TRANSITION. V
= 12V,
= 11V, SYSTEM
ADAPTER CURRENT LOOP TRANSITION. V
MAXSYSTEMVOLTAGE = 12.6V, V
BAT
LOAD 1A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 1A
= 12V,
= 11V, SYSTEM
ADP
ADP
MAXSYSTEMVOLTAGE = 12.6V, V
BAT
LOAD 1A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 0A
FN8723 Rev.5.00
Nov 29, 2017
Page 13 of 40
ISL9237
Typical Performance(Continued)
FIGURE 14. BUCK MODE, OUTPUT VOLTAGE LOOP TO ADAPTER
FIGURE 15. BUCK MODE, CHARGING CURRENT LOOP TO ADAPTER
CURRENT LOOP TRANSITION. V = 20V,
CURRENT LOOP TRANSITION. V
MAXSYSTEMVOLTAGE = 8.496V, V
= 20V,
= 7V, SYSTEM
ADP
ADP
MAXSYSTEMVOLTAGE = 8.496V, V
= 7V, SYSTEM
BAT
BAT
LOAD 2A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 0A
LOAD 2A TO 10A STEP, ADAPTERCURRENTLIMIT = 3A,
CHARGECURRENT = 2A
FIGURE 16. BOOST MODE, OUTPUT VOLTAGE LOOP TO INPUT
FIGURE 17. BOOST MODE, CHARGING CURRENT LOOP TO INPUT
VOLTAGE LOOP TRANSITION. V
MAXSYSTEMVOLTAGE = 8.496V, V
= 5V,
= 7V,
VOLTAGE LOOP TRANSITION. V
= 5V,
MAXSYSTEMVOLTAGE = 8.496V, V = 7V,
BAT
ADP
ADP
BAT
VINDAC = 4.5V, SYSTEM LOAD 0.5A TO 10A STEP,
VINDAC = 4.5V, SYSTEM LOAD 0.5A TO 10A STEP,
CHARGECURRENT = 0A
CHARGECURRENT = 1A
FN8723 Rev.5.00
Nov 29, 2017
Page 14 of 40
ISL9237
Typical Performance(Continued)
FIGURE 18. OTG MODE ENABLE, OTG ENABLE 150ms DEBOUNCE TIME
FIGURE 19. OTG MODE 0.5A TO 2A TRANSIENT LOAD,
OTG VOLTAGE = 5.12V
FN8723 Rev.5.00
Nov 29, 2017
Page 15 of 40
ISL9237
Acknowledge
General SMBus Architecture
Each address and data transmission uses 9 clock pulses. The
ninth pulse is the acknowledge bit (ACK). After the start
condition, the master sends 7 slave address bits and a R/W bit
during the next 8 clock pulses. During the 9 clock pulse, the
device that recognizes its own address holds the data line low to
acknowledge (Refer to Figure 23). The acknowledge bit is also
used by both the master and the slave to acknowledge receipt of
register addresses and data.
VDD SMB
SMBUS SLAVE
INPUT
SCL
CONTROL
OUTPUT
INPUT
STATE
MACHINE
REGISTERS
MEMORY
etc...
SMBUS MASTER
INPUT
SCL
CONTROL
SDA
CONTROL
OUTPUT
INPUT
OUTPUT
INPUT
CPU
SDA
CONTROL
SMBUS SLAVE
OUTPUT
SCL
CONTROL
MSB
OUTPUT
INPUT
STATE
MACHINE
REGISTERS
MEMORY
etc...
SDA
SDA
CONTROL
SCL SDA
OUTPUT
SCL
1
2
8
9
TO OTHER
SLAVE DEVICES
START
ACKNOWLEDGE
FROM SLAVE
FIGURE 20. GENERAL SMBus ARCHITECTURE
FIGURE 23. ACKNOWLEDGE ON THE SMBus
Data Validity
The data on the SDA line must be stable during the HIGH period
of the SCL, unless generating a START or STOP condition. The
HIGH or LOW state of the data line can only change when the
clock signal on the SCL line is LOW. Refer to Figure 21.
SMBus Transactions
All transactions start with a control byte sent from the SMBus
master device. The control byte begins with a Start condition,
followed by 7 bits of slave address (0001001 for the ISL9237)
and the R/W bit. The R/W bit is 0 for a WRITE or 1 for a READ. If
any slave device on the SMBus bus recognizes its address, it will
acknowledge by pulling the serial data (SDA) line low for the last
clock cycle in the control byte. If no slave exists at that address or
it is not ready to communicate, the data line will be one,
indicating a Not Acknowledge condition.
SDA
SCL
DATA LINE
STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
Once the control byte is sent and the ISL9237 acknowledges it,
the second byte sent by the master must be a register address
byte such as 0x14 for the ChargeCurrent register. The register
address byte tells the ISL9237 which register the master will
write or read. See Table 1 on page 17 for details of the registers.
Once the ISL9237 receives a register address byte, it will respond
with an acknowledge.
FIGURE 21. DATA VALIDITY
START and STOP Conditions
Figure 22 START condition is a HIGH to LOW transition of the SDA
line while SCL is HIGH.
Byte Format
The STOP condition is a LOW to HIGH transition on the SDA line
while SCL is HIGH. A STOP condition must be sent before each
START condition.
Every byte put on the SDA line must be 8 bits long and must be
followed by an acknowledge bit. Data is transferred with the
Most Significant Bit first (MSB) and the Least Significant Bit (LSB)
last. The LO BYTE data is transferred before the HI BYTE data. For
example, when writing 0x41A0, 0xA0 is written first and 0x41 is
written second.
SDA
SCL
WRITE TO A REGISTER
SLAVE
ADDR + W
REGISTER
ADDR
LO BYTE
DATA
HI BYTE
DATA
S
A
A
A
A P
S
P
READ FROM A REGISTER
SLAVE
ADDR + W
REGISTER
ADDR
SLAVE
ADDR + R
LO BYTE
DATA
HI BYTE
DATA
S
A
A
P
S
A
A
N P
START
STOP
CONDITION
CONDITION
DRIVEN BY THE
MASTER
S
P
A
N
START
STOP
ACKNOWLEDGE
FIGURE 22. START AND STOP WAVEFORMS
NO
P
DRIVEN BY THE IC
ACKNOWLEDGE
FIGURE 24. SMBus READ AND WRITE PROTOCOL
FN8723 Rev.5.00
Nov 29, 2017
Page 16 of 40
ISL9237
2
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs
that can accommodate slow edges. Choose pull-up resistors for
SDA and SCL to achieve rise times according to the SMBus
specifications.
SMBus and I C Compatibility
The ISL9237 SMBus minimum input logic high voltage is 2V, so it
is compatible with an I C with higher than 2V pull-up power supply.
2
The ISL9237 SMBus registers are 16 bits, so it is compatible with
a 16-bit I C or an 8-bit I C with auto-increment capability.
The illustration in this datasheet is based on current sensing
2
2
resistors R = 20mΩand R = 10mΩ unless otherwise
s1 s2
specified.
ISL9237 SMBus Commands
The ISL9237 receives control inputs from the SMBus interface after
Power-On Reset (POR). The serial interface complies with the
System Management Bus Specification, which can be downloaded
from www.smbus.org. The ISL9237 uses the SMBus Read-word and
Write-word protocols (see Figure 24 on page 16) to communicate
with the host system and a smart battery. The ISL9237 is an SMBus
slave device and does not initiate communication on the bus. It
responds to the 7-bit address 0b0001001_:
Read address = 0b00010011 (0x13H) and
Write address = 0b00010010 (0x12H).
TABLE 1. REGISTER SUMMARY
NUMBER OF
REGISTER
NAMES
REGISTER
ADDRESS
READ/
WRITE
BITS
DESCRIPTION
DEFAULT
ChargeCurrentLimit
AdapterCurrentLimit1
AdapterCurrentLimit2
MaxSystemVoltage
0x14
0x3F
0x3B
0x15
R/W
R/W
R/W
R/W
11
[12:2] 11-bit, LSB size 4mA, maximum range 6080mA for 0A
10mΩ R
.
s2
[12:2] 11-bit, LSB size 4mA, maximum range 6080mA for Set by PROG pin
20mΩ R
11
11
11
.
s1
[12:2] 11-bit, LSB size 4mA, maximum range 6080mA for 1500mA
20mΩ R
.
s1
[13:3] 11-bit, LSB size 8mV, maximum range 13.824V.
4.192V for 1-cell
8.384V for 2-cell
12.576V for 3-cell
2.688V for 1-cell
5.376V for 2-cell
8.064V for 3-cell
3.072A
MinSystemVoltage
0x3E
R/W
11
[13:3] 11-bit, LSB size 8mV, maximum range 13.824V.
ACProchot#
DCProchot#
0x47
0x48
R/W
R/W
6
6
[12:7] adapter current Prochot# threshold.
LSB size 128mA, maximum 6.4A for 20mΩ Rs1.
[13:8] Battery discharging current Prochot# threshold.
4.096A
LSB size 256mA, maximum 12.8A for 10mΩ R
.
s2
T1 and T2
Control0
0x38
0x39
0x3C
0x3D
0x3A
0x49
R/W
R/W
R/W
R/W
R
6
8
Configure two-level adapter current limit duration
Configure various charger options
Configure various charger options
Configure various charger options
Indicate various charger status
0x000h
0x0000h
0x0000h
0x0000h
0x0000h
5.12V
Control1
16
16
16
6
Control2
Information
OTGVoltage
R/W
[12:7] 6-bit, OTG mode output voltage reference.
LSB size 128mV, maximum 5.376V and minimum
4.864V.
OTGCurrent
0x4A
R/W
6
[12:7] 6-bit, OTG mode output current limit.
512mA
LSB size 128mA, maximum 4.096A for 20mΩ R
Manufacturers ID register – 0x49 - Read only
Device ID register - 0x0A- Read only
.
s1
ManufacturerID
DeviceID
0xFE
0xFF
R
R
8
8
0x0049h
0x000Ah
FN8723 Rev.5.00
Nov 29, 2017
Page 17 of 40
ISL9237
TABLE 3. ChargeCurrentLimit REGISTER 0x14H (11-BIT, 8mA STEP,
Setting Charging Current Limit
5mΩ SENSE RESISTOR, x36)
To set the charging current limit, write a 16-bit ChargeCurrentLimit
command (0x14H or 0b00010100) using the Write-word protocol
shown in Figure 24 on page 16 and the data format shown in
BIT
<1:0>
<2>
DESCRIPTION
Not used
Table 2 for a 10mΩ R or Table 3 for a 5mΩ R
.
s2 s2
0 = Add 0mA of charge current limit.
1 = Add 8mA of charge current limit.
The ISL9237 limits the charging current by limiting the
CSOP-CSON voltage. By using the recommended current sense
<3>
<4>
0 = Add 0mA of charge current limit.
1 = Add 16mA of charge current limit.
resistor values R = 20mΩand R = 10mΩ, the register’s LSB
s1
s2
always translates to 1mA of charging current. The
0 = Add 0mA of charge current limit.
1 = Add 32mA of charge current limit.
ChargeCurrentLimit register accepts any charging current
command but only the valid register bits will be written to the
register and the maximum value is clamped at 6080mA for
<5>
0 = Add 0mA of charge current limit.
1 = Add 64mA of charge current limit.
R
= 10mΩ.
s2
<6>
0 = Add 0mA of charge current limit.
1 = Add 128mA of charge current limit.
After POR, the ChargeCurrentLimit register is reset to 0x0000H. To
set the battery charging current value, write a non-zero number to
the ChargeCurrentLimit register. The ChargeCurrentLimit register
can be read back to verify its content.
<7>
0 = Add 0mA of charge current limit.
1 = Add 256mA of charge current limit.
<8>
0 = Add 0mA of charge current limit.
1 = Add 512mA of charge current limit.
Table 2 shows the conditions to enable fast charging according to
the ChargeCurrentLimit register setting.
<9>
0 = Add 0mA of charge current limit.
1 = Add 1024mA of charge current limit.
TABLE 2. ChargeCurrentLimit REGISTER 0x14H (11-BIT, 4mA STEP,
10mΩ SENSE RESISTOR, x36)
<10>
<11>
<12>
0 = Add 0mA of charge current limit.
1 = Add 2048mA of charge current limit.
BIT
<1:0>
<2>
DESCRIPTION
Not used
0 = Add 0mA of charge current limit.
1 = Add 4096mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 4mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 8192mA of charge current limit.
<3>
<4>
0 = Add 0mA of charge current limit.
1 = Add 8mA of charge current limit.
<13:15>
Not used
0 = Add 0mA of charge current limit.
1 = Add 16mA of charge current limit.
Maximum
<12:2> = 10111110000, 12160mA
<5>
0 = Add 0mA of charge current limit.
1 = Add 32mA of charge current limit.
Setting Adapter Current Limit
To set the adapter current limit, write a 16-bit
<6>
0 = Add 0mA of charge current limit.
1 = Add 64mA of charge current limit.
AdapterCurrentLimit1 command (0x3FH or 0b00111111) and/or
AdapterCurrentLimit2 command (0x3BH or 0b00111011) using
the Write-word protocol shown in Figure 24 and the data format
<7>
0 = Add 0mA of charge current limit.
1 = Add 128mA of charge current limit.
<8>
0 = Add 0mA of charge current limit.
1 = Add 256mA of charge current limit.
shown in Table 4 for a 20mΩ R or Table 5 for a 10mΩ R
.
s1 s1
The ISL9237 limits the adapter current by limiting the CSIP-CSIN
voltage. By using the recommended current sense resistor values,
the register’s LSB always translates to 1mA of adapter current. Any
adapter current limit command will be accepted but only the valid
register bits will be written to the AdapterCurrentLimit1 and
AdapterCurrentLimit2 registers, and the maximum value is
<9>
0 = Add 0mA of charge current limit.
1 = Add 512mA of charge current limit.
<10>
<11>
<12>
0 = Add 0mA of charge current limit.
1 = Add 1024mA of charge current limit.
0 = Add 0mA of charge current limit.
1 = Add 2048mA of charge current limit.
clamped at 6080mA for R = 20mΩ.
s1
0 = Add 0mA of charge current limit.
1 = Add 4096mA of charge current limit.
After adapter POR, the AdapterCurrentLimit1 register is reset to
the value programmed through the PROG pin resistor. The
AdapterCurrentLimit2 register is set to its default value of 1.5A or
keep the value that is written to it previously if battery is present
first. The AdapterCurrentLimit1 and AdapterCurrentLimit2
registers can be read back to verify their content.
<13:15> Not used
Maximum <12:2> = 10111110000, 6080mA
To set a second level adapter current limit, write a 16-bit
AdapterCurrentLimit2 (0x3BH or 0b00111011) command using
the Write-word protocol shown in Figure 24 and the data format as
shown in Table 4 for a 20mΩ R or Table 5 for a 10mΩ R
.
s1 s1
FN8723 Rev.5.00
Nov 29, 2017
Page 18 of 40
ISL9237
TABLE 5. AdapterCurrentLimit1 REGISTER 0x3FH AND
AdapterCurrentLimit2 REGISTER 0x3BH (11-BIT, 8mA
STEP, 10mΩ SENSE RESISTOR, x16) (Continued)
The AdapterCurrentLimit2 register has the same specification as
the AdapterCurrentLimit1 register. Refer to “Two-Level Adapter
Current Limit” on page 30 for detailed operation.
BIT
DESCRIPTION
TABLE 4. AdapterCurrentLimit1 REGISTER 0x3FH AND
AdapterCurrentLimit2 REGISTER 0x3BH (11-BIT,
4mA STEP, 20mΩ SENSE RESISTOR, x16)
<8>
0 = Add 0mA of adapter current limit.
1 = Add 512mA of adapter current limit.
BIT
<1:0>
<2>
DESCRIPTION
<9>
0 = Add 0mA of adapter current limit.
1 = Add 1024mA of adapter current limit.
Not used
<10>
<11>
<12>
0 = Add 0mA of adapter current limit.
1 = Add 2048mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 4mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 4096mA of adapter current limit.
<3>
<4>
0 = Add 0mA of adapter current limit.
1 = Add 8mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 16mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 8192mA of adapter current limit.
<5>
0 = Add 0mA of adapter current limit.
1 = Add 32mA of adapter current limit.
<13:15>
Not used
Maximum
<12:4> = 10111110000, 12160mA
<6>
0 = Add 0mA of adapter current limit.
1 = Add 64mA of adapter current limit.
Setting Two-Level Adapter Current Limit
Duration
<7>
0 = Add 0mA of adapter current limit.
1 = Add 128mA of adapter current limit.
For a two-level adapter current limit, write a 16-bit T1 and T2
command (0x38H or 0b00111000) using the Write-word protocol
shown in Figure 24 and the data format as shown in Table 6 to set
the AdapterCurrentLimit1 duration T1. Write a 16-bit T2
command (0x38H or 0b00111000) to set AdapterCurrentLimit2
duration T2. T1 and T2 register accepts any command, however,
only the valid register bits will be written. Refer to “Two-Level
Adapter Current Limit” on page 30 for detailed operation.
<8>
0 = Add 0mA of adapter current limit.
1 = Add 256mA of adapter current limit.
<9>
0 = Add 0mA of adapter current limit.
1 = Add 512mA of adapter current limit.
<10>
<11>
<12>
0 = Add 0mA of adapter current limit.
1 = Add 1024mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 2048mA of adapter current limit.
TABLE 6. T1 AND T2 REGISTER 0x38H
0 = Add 0mA of adapter current limit.
1 = Add 4096mA of adapter current limit.
BIT
DESCRIPTION
T1
<2:0>
000 = 10ms
001 = 20ms
010 = 15ms
011 = 5ms
100 = 1ms
101 = 0.5ms
110 = 0.1ms
111 = 0ms
<13:15>
Not used
Maximum
<12:4> = 10111110000, 6080mA
TABLE 5. AdapterCurrentLimit1 REGISTER 0x3FH AND
AdapterCurrentLimit2 REGISTER 0x3BH (11-BIT, 8mA
STEP, 10mΩ SENSE RESISTOR, x16)
T2
<10:8>
000 = 10µs (default)
001 = 100µs
010 = 500µs
011 = 1ms
100 = 300µs
101 = 750µs
110 = 2ms
BIT
<1:0>
<2>
DESCRIPTION
Not used.
0 = Add 0mA of adapter current limit.
1 = Add 8mA of adapter current limit.
<3>
<4>
<5>
<6>
<7>
0 = Add 0mA of adapter current limit.
1 = Add 16mA of adapter current limit.
111 = 10ms
0 = Add 0mA of adapter current limit.
1 = Add 32mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 64mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 128mA of adapter current limit.
0 = Add 0mA of adapter current limit.
1 = Add 256mA of adapter current limit.
FN8723 Rev.5.00
Nov 29, 2017
Page 19 of 40
ISL9237
and the maximum value is clamped at 13.824V. The
MinSystemVoltage register value should be set lower than the
MaxSystemVoltage register value.
Setting Maximum Charging Voltage or
System Regulating Voltage
To set the maximum charging voltage or the system regulating
voltage, write a 16-bit MaxSystemVoltage command (0x15H or
0b00010101) using the Write-word protocol shown in Figure 24
and the data format as shown in Table 7.
The MinSystemVoltage register sets the battery voltage threshold
for entry and exit of the trickle charging mode and for entry and
exit of the Learn mode. The VBAT pin is used to sense the battery
voltage to compare with the MinSystemVoltage register setting.
Refer to “Trickle Charging” on page 31 and “Battery Learn Mode”
on page 29 for details.
The MaxSystemVoltage register accepts any voltage command
however, only the valid register bits will be written to the register
and the maximum value is clamped at 13.824V.
The MinSystemVoltage register setting also is the system voltage
regulation point when it is in trickle charging mode. The CSON
pin is the system voltage regulation sense point in trickle
charging mode. Refer to “System Voltage Regulation” on page 31”
for details.
The MaxSystemVoltage register sets the battery full charging
voltage limit. The MaxSystemVoltage register setting also is the
system bus voltage regulation point when battery is absent or
battery is present, however, is not in charging mode. See “System
Voltage Regulation” on page 31 for details.
TABLE 8. MinSystemVoltage REGISTER 0x3EH
The VSYS pin is used to sense the battery voltage for maximum
charging voltage regulation. VSYS pin is also the system bus
voltage regulation sense point.
BIT
<2:0>
<3>
DESCRIPTION
Not used
0 = Add 0mV of charge voltage.
1 = Add 8mV of charge voltage.
TABLE 7. MaxSystemVoltage REGISTER 0x15H (8mV STEP)
BIT
<2:0>
<3>
DESCRIPTION
<4>
<5>
0 = Add 0mV of charge voltage.
1 = Add 16mV of charge voltage.
Not used
0 = Add 0mV of charge voltage.
1 = Add 8mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 32mV of charge voltage.
<4>
<5>
0 = Add 0mV of charge voltage.
1 = Add 16mV of charge voltage.
<6>
0 = Add 0mV of charge voltage.
1 = Add 64mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 32mV of charge voltage.
<7>
0 = Add 0mV of charge voltage.
1 = Add 128mV of charge voltage.
<6>
0 = Add 0mV of charge voltage.
1 = Add 64mV of charge voltage.
<8>
0 = Add 0mV of charge voltage.
1 = Add 256mV of charge voltage.
<7>
0 = Add 0mV of charge voltage.
1 = Add 128mV of charge voltage.
<9>
0 = Add 0mV of charge voltage.
1 = Add 512mV of charge voltage.
<8>
0 = Add 0mV of charge voltage.
1 = Add 256mV of charge voltage.
<10>
<11>
<12>
<13>
<15:14>
0 = Add 0mV of charge voltage.
1 = Add 1024mV of charge voltage.
<9>
0 = Add 0mV of charge voltage.
1 = Add 512mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 2046mV of charge voltage.
<10>
<11>
<12>
<13>
0 = Add 0mV of charge voltage.
1 = Add 1024mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 4096mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 2046mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 8192mV of charge voltage.
0 = Add 0mV of charge voltage.
1 = Add 4096mV of charge voltage.
Not used
Maximum <13:3> = 11011000000, 13824mV
0 = Add 0mV of charge voltage.
1 = Add 8192mV of charge voltage.
Setting PROCHOT# Threshold for Adapter
Overcurrent Condition
<15:14> Not used
Maximum <13:3> = 11011000000, 13824mV
To set the PROCHOT# assertion threshold for adapter overcurrent
condition, write a 16-bit ACProchot# command (0x47H or
0b01000111) using the Write-word protocol shown in Figure 24
and the data format shown in Table 9 on page 21. By using the
recommended current sense resistor values, the register’s LSB
always translates to 1mA of adapter current. The ACProchot#
register accepts any current command, however, only the valid
register bits will be written to the register, and the maximum value
Setting Minimum System Voltage
To set the minimum system voltage, write a 16-bit
MinSystemVoltage command (0x3EH or 0b00111110) using the
Write-word protocol shown in Figure 24 and the data format as
shown in Table 8.
The MinSystemVoltage register accepts any voltage command,
however, only the valid register bits will be written to the register,
is clamped at 6400mA for R = 20mΩ.
s1
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ISL9237
After POR, the ACProchot# register is reset to 0x0C00H. The
ACProchot# register can be read back to verify its content.
TABLE 10. DCPROCHOT# REGISTER 0x48H (10mΩ SENSING
RESISTOR, 256mA STEP, x18 GAIN)
BIT
<7:0>
<8>
DESCRIPTION
If the adapter current exceeds the ACProchot# register setting,
PROCHOT# signal will assert after the debounce time programmed
by the Control2 register Bit<10:9> and latch on for a minimum time
programmed by Control2 register Bit<8:6>.
Not used
0 = Add 0mA of DCProchot# threshold.
1 = Add 256mA of DCProchot# threshold.
TABLE 9. ACProchot# REGISTER 0x47H (20mΩ SENSING RESISTOR,
<9>
0 = Add 0mA of DCProchot# threshold.
1 = Add 512mA of DCProchot# threshold.
128mA STEP, x18 GAIN)
BIT
<6:0>
<7>
DESCRIPTION
<10>
<11>
<12>
<13>
0 = Add 0mA of DCProchot# threshold.
1 = Add 1024mA of DCProchot# threshold.
Not used
0 = Add 0mA of DCProchot# threshold.
1 = Add 2048mA of DCProchot# threshold.
0 = Add 0mA of ACProchot# threshold.
1 = Add 128mA of ACProchot# threshold.
0 = Add 0mA of DCProchot# threshold.
1 = Add 4096mA of DCProchot# threshold.
<8>
<9>
0 = Add 0mA of ACProchot# threshold.
1 = Add 256mA of ACProchot# threshold.
0 = Add 0mA of DCProchot# threshold.
1 = Add 8192mA of DCProchot# threshold.
0 = Add 0mA of ACProchot# threshold.
1 = Add 512mA of ACProchot# threshold.
<15:14>
Not used
<10>
<11>
<12>
0 = Add 0mA of ACProchot# threshold.
1 = Add 1024mA of ACProchot# threshold.
Maximum
<13:8> = 110010, 12800mA
0 = Add 0mA of ACProchot# threshold.
1 = Add 2048mA of ACProchot# threshold.
Setting PROCHOT# Debounce Time and
Duration Time
Control2 register Bit<10:9> configures the PROCHOT# signal
debounce time before its assertion for ACProchot# and
DCProchot#. The low system voltage Prochot# has a fixed
debounce time of 10µs.
0 = Add 0mA of ACProchot# threshold.
1 = Add 4096mA of ACProchot# threshold.
<15:13>
Not used
Maximum
<12:7> = 110010, 6400mA
Setting PROCHOT# Threshold for Battery
Over Discharging Current Condition
Control2 register Bit<8:6> configures the minimum duration of
Prochot# signal once asserted.
To set the PROCHOT# signal assertion threshold for battery over
discharging current condition, write a 16-bit DCProchot#
command (0x48H or 0b01001000) using the Write-word protocol
shown in Figure 24 and the data format shown in Table 10. By
using the recommended current sense resistor values, the
register’s LSB always translates to 1mA of adapter current. The
DCProchot# register accepts any current command, however, only
the valid register bits will be written to the register and the
Control Registers
Control0, Control1 and Control2 registers configure the operation of
the ISL9237. To change certain functions or options after POR, write
an 8-bit control command to Control0 register (0x39H or
0b00111001) or a 16-bit control command to Control1 register
(0x3CH or 0b00111100) or Control2 register (0x3DH or
0b00111101) using the Write-word protocol shown in Figure 24
and the data format shown in Tables 11, 12 and 13, respectively.
maximum value is clamped at 12.8A for R = 10mΩ.
s2
After POR, the DCProchot# register is reset to 0x1000H. The
DCProchot# register can be read back to verify its content.
If the battery discharging current exceeds the DCProchot# register
setting, the PROCHOT# signal will assert after the debounce time
programmed by the Control2 register Bit<10:9> and latch on for a
minimum time programmed by Control2 register Bit<8:6>.
In battery only and Low Power mode, the DCProchot# threshold
is set by Control0 register Bit<4:3>.
In battery only mode, DCProchot# function works only when
PSYS is enabled, since enabling PSYS will activate the internal
comparator reference. The Information register Bit<15>
indicates if the internal comparator reference is active or not.
When adapter is present, the internal comparator reference is
always active.
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ISL9237
TABLE 11. CONTROL0 REGISTER 0x39H
DESCRIPTION
BIT
<15:8>
<7>
BIT NAME
Not used
SMBus Timeout
The ISL9237 includes a timer to insure the SMBus master is active and to prevent overcharging the battery.
If the adapter is present and if the ISL9237 does not receive a write to the MaxChargeVoltage or
ChargeCurrentLimit register within 175s, ISL9237 will terminate charging. If a timeout occurs, writing the
MaxChargeVoltage or ChargeCurrentLimit register will re-enable charging.
0 = Enable the SMBus timeout function (default).
1 = Disable the SMBus timeout function.
<6:5>
<4:3>
High-Side FET Short
Detection Threshold
Bit<6:5> configures the high-side FET short detection PHASE node voltage threshold during low-side FET
turning on.
00 = 400mV (default)
01 = 500mV
10 = 600mV
11 = 800mV
DCProchot# Threshold in
Battery Only Low Power
Mode
Bit<4:3> only configures the battery discharging current DCProchot# threshold in battery only Low Power
mode indicated by the Information register 0x3A Bit<15>. If PSYS is enabled, battery discharge current
DCProchot# threshold is set by the DCProchot# register 0x48 setting.
R
= 10mΩ
R
= 20mΩ
R = 5mΩ
s2
s2
s2
BIT<4:3>
00
(A)
(A)
(A)
12 (Default)
6
5
4
3
24
20
16
12
01
10
8
10
11
6
<2>
Input Voltage Regulation
Loop
Bit<2> disables or enables the input voltage regulation loop.
0 = Enable (default)
1 = Disable
<1:0>
Input Voltage Regulation
Reference
Bit<1:0> configures the input voltage loop regulation reference.
00 = 3.9V (default)
01 = 4.2V
10 = 4.5V
11 = 4.8V
TABLE 12. CONTROL1 REGISTER 0x3CH
DESCRIPTION
BIT
BIT NAME
<15:14> General Purpose
Comparator Assertion
Debounce Time
Bit<15:14> configures the general purpose comparator assertion debounce time.
00 = 2µs (default)
01 = 12µs
10 = 2ms
11 = 5s
13
12
Exit Learn Mode Option
Learn Mode
Bit<12> provides the option to exit Learn mode when battery voltage is lower than MinSystemVoltage
register setting.
0 = Stay in Learn mode even if V
< MinSystemVoltage register setting (default)
BAT
< MinSystemVoltage register setting
1 = Exit Learn mode if V
BAT
Bit<13> enables or disables the Battery Learn mode.
0 = Disable (default)
1 = Enable
To enter Learn mode, BATGONE pin needs to be low, i.e., battery must be present.
11
10
OTG Function
Audio Filter
Bit<11> enables or disables OTG function.
0 = Disable (default)
1 = Enable
Bit<10> enables or disables the audio filter function.
0 = Disable (default)
1 = Enable
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ISL9237
TABLE 12. CONTROL1 REGISTER 0x3CH
DESCRIPTION
BIT
BIT NAME
<9:7>
Switching Frequency
Bit<9:7> configures the switching frequency and overrides the switching frequency set by PROG pin.
000 = Switching frequency set by PROG pin (default)
001 = 913kHz
010 = 839kHz
011 = 777kHz
100 = 723kHz
101 = 676kHz
110 = 635kHz
111 = 599kHz
To keep the switching frequency set by PROG pin resistor, leave Bit<9:7> as it is or write code 000, which
sets the same frequency as the PROG pin resistor.
6
5
Turbo
Bit<6> enables or disables Turbo mode. When the turbo function is enabled, BGATE FET turns on in Turbo
mode. Refer to Table 19 on page 30 for BGATE ON/OFF truth table.
0 = Enable (default)
1 = Disable
AMON/BMON Function
Bit<5> enables or disables the current monitor function AMON and BMON.
0 = Enable AMON/BMON (default)
1 = Disable AMON/BMON
Bit<5> is only valid in battery only mode. When adapter is present, AMON/BMON is automatically enabled
and Bit<5> becomes invalid.
4
3
2
AMON or BMON
PSYS
Bit<4> selects AMON or BMON as the output of AMON/BMON pin.
0 = AMON (default)
1 = BMON
Bit<3> enables or disable system power monitor PSYS function.
0 = Disable (default)
1 = Enable
VSYS
Bit<2> enables or disables the buck-boost charger switching VSYS output. When disabled, ISL9237 stops
switching and forces BGATE FET on.
0 = Enable (default)
1 = Disable
<1:0>
Low_VSYS_Prochot#
Reference
Bit<1:0> configures the Low_VSYS_Prochot# assertion threshold.
00 = 6.0V (default)
01 = 6.3V
10 = 6.6V
11 = 6.9V
For 1-cell configuration, the Low_VSYS_Prochot# assertion threshold is fixed 2.4V.
TABLE 13. CONTROL2 REGISTER 0x3DH
DESCRIPTION
BIT
BIT NAME
<15:14> Trickle Charging Current
Bit<15:14> configures the charging current in trickle charging mode.
00 = 256mA (default)
01 = 128mA
10 = 64mA
11 = 512mA
13
12
OTG Function Enable
Debounce Time
Bit<13> configures the OTG function debounce time from when ISL9237 receives the OTG enable command.
0 = 1.3s (default)
1 = 150ms
Two-Level Adapter Current Bit<12> enables or disables the two-level adapter current limit function.
Limit Function
0 = Disable (default)
1 = Enable
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ISL9237
TABLE 13. CONTROL2 REGISTER 0x3DH (Continued)
DESCRIPTION
BIT
11
BIT NAME
Adapter Insertion to
ASGATE Turning On
Debounce
Bit<11> configures the debounce time from adapter insertion to ASGATE turning on.
0 = 1.3s (default)
1 = 150ms
After VDD POR, for the first time adapter is plugged in, the ASGATE turn-on delay is always 150ms, regardless
of the Bit<11> setting. This bit only sets the ASGATE turn-on delay after ASGATE turns off at least one time
when VDD is above the POR value and Bit<11> default is 0 for 1.3s.
<10:9>
<8:6>
Prochot# Debounce
Prochot# Duration
Bit<10:9> configures the Prochot# debounce time before its assertion for ACProchot# and DCProchot#.
00: 10µs (default)
01: 100µs
10: 500µs
11: 1ms
The Low_VSYS_Prochot# has fixed 10µs debounce time.
Bit<8:6> configures the minimum duration of Prochot# signal once asserted.
000 = 10ms (default)
001 = 20ms
010 = 15ms
011 = 5ms
100 = 1ms
101 = 500µs
110 = 100µs
111 = 0s
5
4
3
2
ASGATE in OTG Mode
CMIN Reference
Bit<5> turns on or off the ASGATE FET in OTG mode.
0 = Turn ON ASGATE in OTG mode (default)
1 = Turn OFF ASGATE in OTG mode
Bit<4> configures the general purpose comparator reference voltage.
0 = 1.2V (default)
1 = 2V
General Purpose
Comparator
Bit<3> enables or disabled the general purpose comparator.
0 = Enable (default)
1 = Disable
CMOUT Polarity
Bit<2> configures the general purpose comparator output polarity once asserted. The comparator reference
voltage is connected at the inverting input node.
0 = CMOUT is high when CMIN is higher than reference (default)
1 = CMOUT is low when CMIN is higher than reference
1
0
WOCP Function
PSYS Gain
Bit<1> enables or disables the WOC (Way Overcurrent) fault protection function.
0 = Enable WOCP (default)
1 = Disable WOCP
Bit<0> configures the system power monitor PSYS output gain.
0 = 1.44µA/W (default)
1 = 0.36µA/W
OTGVoltage Register
TABLE 14. OTGVOLTAGE REGISTER 0x49H
To set the OTG mode output regulation voltage, write a 16-bit
OTGVoltage command (0x49H or 0b01001001) using the
Write-word protocol shown in Figure 24 on page 16 and the data
format as shown in Table 14.
BIT
<6:0>
<7>
DESCRIPTION
Not used
0 = Add 0mV of OTG voltage
1 = Add 128mV of OTG voltage
The OTGVoltage register accepts any voltage command, however,
only the valid register bits will be written to the register, and the
maximum value is clamped at 5.376V and the minimum value is
clamped at 4.864V.
<8>
<9>
0 = Add 0mV of OTG voltage
1 = Add 256mV of OTG voltage
0 = Add 0mV of OTG voltage
1 = Add 512mV of OTG voltage
<10>
0 = Add 0mV of OTG voltage
1 = Add 1024mV of OTG voltage
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ISL9237
TABLE 14. OTGVOLTAGE REGISTER 0x49H (Continued)
BIT DESCRIPTION
0 = Add 0mV of OTG voltage
Information Register
The Information Register contains SMBus readable information
about manufacturing and operating modes. Table 16 identifies
the bit locations of the information available.
<11>
<12>
1 = Add 2048mV of OTG voltage
TABLE 16. INFORMATION REGISTER 0x3AH
0 = Add 0mV of OTG voltage
1 = Add 4096mV of OTG voltage
BIT
DESCRIPTION
<15:13>
Range
Not used
<3:0>
Bit<3:0> indicates the configuration set by PROG pin
resistor.
<12:7> = 101010, maximum 5.376V
<12:7> = 100110, minimum 4.864V
In battery only mode, Bit<3:0> shows the PROG pin
programmed configuration only after PROG pin
resistor is read by enabling PSYS.
OTGCurrent Register
To set the OTG mode output current limit threshold, write a 16-bit
OTGVoltage command (0x4AH or 0b01001010) using the
Write-word protocol shown in Figure 24 on page 16 and the data
format as shown in Table 15.
<3:0> = Cell number, Default f , default
SW
AdapterCurrentLimit1 register setting.
0000 = 3-cell, 1MHz, 1.5A,
0001 = 3-cell, 1MHz, 0.476A,
0010 = 3-cell, 723kHz, 1.5A
0011 = 3-cell, 723kHz, 0.476A
0100 = 3-cell, 723kHz, 0.1A
The OTGCurrent register accepts any current command, however,
only the valid register bits will be written to the register, and the
maximum value is clamped at 4096mA for R = 20mΩ.
s1
0101 = 2-cell, 1MHz, 1.5A
0110 = 2-cell, 1MHz, 0.476A
0111 = 2-cell, 723kHz, 1.5A
1000 = 2-cell, 723kHz, 0.476A
1001 = 2-cell, 723kHz, 0.1A
TABLE 15. OTGCURRENT 0x4AH
BIT
<6:0>
<7>
DESCRIPTION
Not used
0 = Add 0mA of OTG current
1 = Add 128mA of OTG current
1010 = 1-cell, 1MHz, 0.1A
1011 = 1-cell, 1MHz, 1.5A
1100 = 1-cell, 1MHz, 0.476A
1101 = 1-cell, 723kHz, 1.5A
1110 = 1-cell, 723kHz, 0.476A
1111 = 1-cell, 723kHz, 0.1A
<8>
<9>
0 = Add 0mA of OTG current
1 = Add 256mA of OTG current
0 = Add 0mV of OTG current
1 = Add 512mA of OTG current
<4>
Bit<4> indicates if the trickle charging mode is active
or not.
0 = Trickle charging mode is not active
1 = Trickle charging mode is active
<10>
<11>
<12>
0 = Add 0mV of OTG current
1 = Add 1024mA of OTG current
0 = Add 0mV of OTG current
1 = Add 2048mA of OTG current
<6:5>
Bit<6:5> indicates the ISL9237 operation mode.
00 = Buck mode
01 = Boost mode
0 = Add 0mV of OTG current
1 = Add 4096mA of OTG current
10 = Buck-boost mode
11 = OTG mode
<15:13>
Not used
Maximum
<12:7> = 100000, 4096mA
<9:7>
Bit<9:7> indicates the ISL9237 state machine status
000 = OFF
001 = BATTERY
010 = ADAPTER
011 = ACOK
100 = VSYS
101 = CHARGE
110 = ENOTG
111 = OTG
<10>
<11>
Bit<10> indicates if the Low_VSYS_Prochot# is
tripped or not.
0 = Low_VSYS Prochot# is not tripped
1 = Low_VSYS Prochot# is tripped
Bit<11> indicates if the battery discharging Prochot#
signal DCProchot# is tripped or not.
0 = DCProchot# is not tripped
1 = DCProchot# is tripped
FN8723 Rev.5.00
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ISL9237
TABLE 16. INFORMATION REGISTER 0x3AH (Continued)
BIT
DESCRIPTION
PWM
<12>
Bit<12> indicates if the adapter current Prochot#
signal ACProchot# is tripped or not.
0 = ACProchot# is not tripped
VW
1 = ACProchot# is tripped
<14:13>
<15>
Bit<14:13> indicates the active control loop.
00 = MaxSystemVoltage control loop is active
01 = Charging current loop is active
10 = Adapter current limit loop is active
11 = Input voltage loop is active
COMP
VCR
Bit<15> indicates if the internal reference circuit is
active or not. Bit<15> = 0 indicates that ISL9237 is in
Low Power mode.
FIGURE 27. R3™ MODULATOR OPERATION PRINCIPLES IN DYNAMIC
RESPONSE
0 = Reference is not active
1 = Reference is active
Application Information
PHASE
R3™ Modulator
UGATE
LGATE
COMP
+
-
S
R
V
CR
PWM
Q
L
V
O
IL
+
-
PHASE
V
W
I
L
C
O
FIGURE 28. DIODE EMULATION
+
GM
-
C
R
CCM/DCM BOUNDARY
VW
VCR
FIGURE 25. R3™ MODULATOR
CCM
IL
PWM
LIGHT DCM
VW
VW
VCR
HYSTERETIC
WINDOW
V
CR
IL
COMP
DEEP DCM
VW
FIGURE 26. R3™ MODULATOR OPERATION PRINCIPLES IN STEADY
STATE
VCR
IL
FIGURE 29. PERIOD STRETCHING
The ISL9237 uses the Intersil patented R3™ (Robust Ripple
Regulator) modulation scheme. The R3™ modulator combines
the best features of fixed frequency PWM and hysteretic PWM
while eliminating many of their shortcomings. Figure 25
FN8723 Rev.5.00
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Page 26 of 40
ISL9237
conceptually shows the R3™ modulator circuit and Figure 26
shows the operation principles in steady state.
connected to the same inductor’s “output” as is the case with a
boost converter. This arrangement supports bucking from a
voltage input higher than the battery and also boosting from a
voltage input lower than the battery.
There is a fixed voltage window between VW and COMP. This
voltage window is called the VW window in the following
discussion. The modulator charges the ripple capacitor C with a
In Buck mode, Q1 and Q2 turn on and off alternatively, while Q3
remains off and Q4 remains on.
R
current source equal to g (V - V ) during PWM on-time and
m
IN
O
discharges the ripple capacitor C with a current source equal to
R
In Boost mode, Q3 and Q4 turn on and off alternatively, while Q1
remains on and Q2 remains off.
g V , during PWM off-time, where g is a gain factor. The C
m O
m
r
voltage V therefore emulates the inductor current waveform.
CR
The modulator turns off the PWM pulse when V reaches VW
CR
and turns on the PWM pulse when it reaches COMP.
In Buck-boost mode, Q1 and Q3 is turned on and off at the same
time and alternatively with Q2 and Q4, which turned off and on at
the same time.
Since the modulator works with V , which is a large amplitude
cr
and noise free synthesized signal, it achieves lower phase jitter
than conventional hysteretic mode modulator.
In OTG mode, Q3 and Q4 turn on and off alternatively as a buck
regulator with V
as the input, while Q1 remains on and Q2
BAT
remains off with the CSIP pin as the output sensing point.
Figure 27 shows the operation principles during dynamic
response. The COMP voltage rises during dynamic response,
turning on PWM pulses earlier and more frequently temporarily,
which allows for higher control loop bandwidth than conventional
fixed frequency PWM modulator at the same steady state
switching frequency.
TABLE 17. OPERATION MODE
MODE
Buck
Q1
Control FET
ON
Q2
Sync. FET
OFF
Q3
Q4
OFF
ON
Boost
Control FET
Control FET
Sync. FET
Sync. FET
Sync. FET
Control FET
The R3™ modulator can operate in Diode Emulation (DE) mode
to increase light-load efficiency. In DE mode the low-side MOSFET
conducts when the current is flowing from source-to-drain and
does not allow reverse current, emulating a diode. As shown in
Figure 28, when LGATE is on, the low-side MOSFET carries
current, creating negative voltage on the phase node due to the
voltage drop across the ON-resistance. The IC monitors the
current by monitoring the phase node voltage. It turns off LGATE
when the phase node voltage reaches zero to prevent the
inductor current from reversing the direction and creating
unnecessary power loss.
Buck-Boost
OTG
Control FET
ON
Sync. FET
OFF
RS1
VSYS
VADP
CSOP
SYSTEM
LOAD
Q4
Q3
CSIP
CSIN
Q1
Q2
RS2
L1
CSON
BGATE
FET
V
BAT
BATTERY
If the load current is light enough, as Figure 28 shows, the
inductor current will reach and stay at zero before the next phase
node pulse and the regulator is in Discontinuous Conduction
Mode (DCM). If the load current is heavy enough, the inductor
current will never reach 0A and the regulator is in CCM although
the controller is in DE mode.
FIGURE 30. BUCK-BOOST CHARGER TOPOLOGY
The ISL9237 optimizes the operation mode transition algorithm
by considering the input and output voltage ratio and the load
condition. When adapter voltage V
is rising and is higher than
ADP
Figure 29 shows the operation principle in diode emulation
mode at light load. The load gets incrementally lighter in the
three cases from top to bottom. The PWM on-time is determined
by the VW window size, therefore is the same, making the
inductor current triangle the same in the three cases. The R3™
94% of the system bus voltage VSYS, ISL9237 will transit from
Boost mode to Buck-boost mode; if V is higher than 120% of
VSYS, ISL9237 will forcedly transit from Buck-boost mode to
Buck mode at any circumstance. At heavier load, the mode
transition point changes accordingly to accommodate the duty
cycle change due to the power loss on the charger circuit.
ADP
modulator clamps the ripple capacitor voltage V in DE mode to
CR
make it mimic the inductor current. It takes the COMP voltage
When the adapter voltage V
ADP
is falling and is lower than 106%
longer to hit V , naturally stretching the switching period. The
CR
of the system bus voltage VSYS, ISL9237 will transit from Buck
mode to Buck-boost mode; if V is lower than 80% of VSYS,
inductor current triangles move further apart from each other,
such that the inductor current average value is equal to the load
current. The reduced switching frequency helps increase
light-load efficiency.
ADP
ISL9237 will transit from Buck-boost mode to Boost mode.
ISL9237 Buck-Boost Charger with USB OTG
The ISL9237 buck-boost charger drives an external N-channel
MOSFET bridge comprised of two transistor pairs as shown in
Figure 30. The first pair, Q1 and Q2, is a buck arrangement with
the transistor center tap connected to an inductor “input” as is
the case with a buck converter. The second transistor pair, Q3
and Q4, is a boost arrangement with the transistor center tap
FN8723 Rev.5.00
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ISL9237
ACOK is an open-drain output pin indicating the presence of the
adapter and readiness of the adapter to supply power to the
system bus. The ISL9237 actively pulls ACOK low in the absence of
the adapter.
V A D P
B U C K
B U C K
120%
B U C K -B O O S T
Before ASGATE turns ON, the ISL9237 will source 10µA of current
out of the PROG pin and read the pin voltage to determine the
PROG resistor value. The PROG resistor programs the
configurations of the ISL9237.
106%
V S Y S
94%
B U C K -B O O S T
In battery only mode, ISL9237 enters Low Power mode if only
battery is present. VDD is 4V from the low power LDO to minimize
the power consumption. VDD becomes 5V once it exits the Low
Power mode such as when PSYS is enabled.
B O O S T
80%
B O O S T
Programming Charger Option
V A D P
The resistor from the PROG pin to GND programs the configuration
of the ISL9237 for the default number of battery cells in series, the
default switching frequency and the default AdapterCurrentLimit1
register value. AdapterCurrentLimit2 register default value is 1.5A.
Table 18 shows the programing options.
FIGURE 31. OPERATION MODE
When the OTG function is enabled with SMBus command and
OTGEN pin, and if battery voltage V is higher than 5.8V,
BAT
ISL9237 operates in the reverse Buck mode, Q4, Q3 and L1
consists of the reverse buck regulator, Q1 is turned on and Q2 is
turned off. For reverse buck, there is one digital bit to control
ASGATE. OTG mode is not available for 1-cell battery systems.
TABLE 18. PROG PIN PROGRAMMING OPTIONS
PROG-PIN
DEFAULT
The ISL9237 connects the system voltage rail to either the
output of the buck-boost switcher or the battery. In Turbo event,
the ISL9237 will turn on the BGATE FET to discharge the battery
so the battery works with the adapter together to supply the
system power.
RESISTOR (kΩ)
BATTERY
CELL
DEFAULT AdapterCurrent
SWITCHING Limit1 Register
VALUE
1%
MIN
MAX NUMBER FREQUENCY
(A)
0
1-cell
733kHz
0.1
16.6
31.1
16.9
31.6
44.2
59
17.2
32.1
0.476
1.5
Soft-Start
The ISL9237 includes a low power LDO with nominal 4V output,
which input is OR-ed from pins VBAT and ADP. The ISL9237 also
includes a high power LDO with nominal 5V output, which input is
from the DCIN pin connected to the adapter and the system bus
through an external OR-ing diode circuit. Both LDO outputs are tied
to the VDD pin to provide the bias power and gate drive power for
ISL9237. VDDP pin is the ISL9237 gate drive power supply input.
Use an R-C filter to generate the VDDP pin voltage from the VDD
pin voltage.
43.5
44.9
1MHz
0.476
1.5
58.1
59.9
72.1
73.2
86.6
102
115
130
143
158
174
187
74.3
0.1
85.3
87.9
2-cell
3-cell
733kHz
0.1
101
103
0.476
1.5
113.9
128.7
141.6
156.4
172.3
185.1
201
116.2
131.3
144.4
159.6
175.7
188.9
205
When VDD > 2.7V, the ISL9237 digital block is activated and the
SMBus register is ready to communicate with the master
controller.
1MHz
0.476
1.5
733kHz
0.1
When VADP > 3.2V, after 1.3s or 150ms debounce time set by
Control2 register Bit<11> (after VDD POR, for the first time
adapter plugged in, the ASGATE turn on delay is always 150ms),
ASGATE starts turning on with 10µA sink current. During the 1.3s
or 150ms debounce time, ISL9237 uses ‘Intersil’s patent pending
technique to check if the input bus is short or not; if CSIP < 2V or
ACIN < 0.8V, ASGATE will not turn on. The soft-start scheme will
carefully bias up the input capacitors and protect the back-to-back
ASGATE FETs against potential damage caused by the inrush
current.
0.476
1.5
203
(Note 8)
1MHz
0.476
218.8
221
223.2
1.5
NOTE:
8. 203kΩ is not standard resistor; use two resistors in series or in parallel
to get the closest value.
Use a voltage divider from the adapter voltage to set the ACIN pin
voltage. The ISL9237 monitors the ACIN pin voltage to determine
the presence of the adapter. Once VDD > 3.8V, the ACIN pin
voltage exceeds 0.8V and ASGATE is fully turned on, the ISL9237
will allow the external circuit to pull up the ACOK pin. Once ACOK is
asserted, ISL9237 will start switching.
ISL9237 will use the default number of cells in series as Table 18
shows and sets the default MaxSystemVoltage register value and
default MinSystemVoltage register value accordingly.
FN8723 Rev.5.00
Nov 29, 2017
Page 28 of 40
ISL9237
The switching frequency can be changed through SMBus
Control1 register Bit<9:7> after POR. Refer to the SMBus
Control1 register programming table for detailed description.
Power Source Selection
The ISL9237 automatically selects the adapter and/or the
battery as the source for system power.
Before ASGATE turns on, ISL9237 will source 10µA current out of
the PROG pin and read the PROG pin voltage to determine the
resistor value. However, application environmental noise may
pollute the PROG pin voltage and cause incorrect reading. If noise
is a concern, it is recommended to connect a capacitor from the
PROG pin to GND to provide filtering. The resistor and the capacitor
RC time constant should be less than 40µs so the PROG pin
voltage can rise to steady state before the ISL9237 reads it.
The BGATE pin drives a P-channel MOSFET gate that
connects/disconnects the battery from the system and the
switcher.
The ASGATE pin drives a pair of back-to-back common source
PFETs to connect/disconnect the adapter from the system and
the battery. Use of the ASGATE pin is optional.
When battery voltage V
is higher than 2.4V and adapter
BAT
is less than 3.2V, ISL9237 operates in battery only
If ISL9237 is powered up from battery, it will not read the PROG
resistor unless PSYS is enabled through SMBus Control1 register
Bit<3>. In battery only mode, whenever PSYS is enabled,
ISL9237 will read the PROG pin resistor and reset the
configuration to the default.
voltage V
ADP
mode. During the battery only mode, ISL9237 turns on the
BGATE FET to connect the battery to the system. In battery only
mode, the ISL9237 consumes very low power, less than 20µA
during this mode. The battery discharging current monitor BMON
can be turned on during this mode to monitor the battery
Whenever the adapter is plugged in, ISL9237 will reset the
AdapterCurrentLimit1 register to the default by reading PROG pin
resistor if it is not read before or by loading the previous reading
result.
discharging current. If the battery voltage V
is higher than
BAT
5.8V, the system power monitor PSYS function also can be
turned on during this mode to monitor system power.
In battery only mode, the USB OTG function can be enabled, see
“USB OTG (On-the-Go)” on page 31 for details.
If PSYS is not enabled, ISL9237 will reset MaxSystemVoltage
register and MinSystemVoltage register to their default values
according to the PROG pin cell number setting. If PSYS is
enabled, ISL9237 will keep the values in these two registers.
When adapter voltage, V
, is more than 3.2V, ISL9237 turns
ADP
on ASGATE. If V is higher than 3.8V, ISL9237 enters in the
DD
forward buck, forward boost or forward Buck-boost mode
depending upon the adapter and system voltage, VSYS, duty
cycle ratio. The system bus voltage is regulated at the voltage set
on the MaxSystemVoltage register. If the charge current register
is programmed (non-zero), ISL9237 charges the battery either in
trickle charging mode or fast charging mode, as long as
BATGONE is low.
By default, the adapter current sensing resistor, R , is 20mΩ
s1
and the battery current sensing resistor, R , is 10mΩ. Using this
s2
R
= 20mΩand R = 10mΩ option would result in 1mA/LSB
s2
s1
correlation in the SMBus current commands.
If R and R values are different from this R = 20mΩand
s1 s2 s1
R
= 10mΩ option, the SMBus command needs to be scaled
s2
accordingly to obtain the correct current. Smaller current sense
resistor values reduce the power loss while larger current sense
resistor values give better accuracy.
Battery Learn Mode
The ISL9237 supports battery Learn mode. The ISL9237 enters
Battery Learn mode when it receives SMBus Control command.
If different current sensing resistors are used, the R :R ratio
s1 s2
should be kept as 2:1, then PSYS output can be scaled
accordingly to reflect the total system power correctly.
This mode of operation is used when it is desired to supply the
system power from the battery even when the adapter is plugged
in, such as calibration of the battery fuel gauge, hence the name
“Battery Learn mode”.
The illustration in this datasheet is based on current sensing
resistors R = 20mΩ and R = 10mΩ unless specified
s1 s2
otherwise.
Upon entering Battery Learn mode the ISL9237 will turn on the
BGATE FET when the system bus voltage decays to the battery
voltage in order to avoid inrush current from the system bus to
the battery.
DE Operation
In DE mode of operation, the ISL9237 employs a phase
comparator to monitor the PHASE node voltage during the
low-side switching FET on-time in order to detect the inductor
current zero crossing. The phase comparator needs a minimum
on-time of the low-side switching FET for it to recognize inductor
current zero crossing. If the low-side switching FET on-time is too
short for the phase comparator to successfully recognize the
inductor zero crossing, the ISL9237 may lose diode emulation
ability. To prevent such a scenario, the ISL9237 employs a
minimum low-side switching FET on-time. When the intended
low-side switching FET on-time is shorter than the minimum
value, the ISL9237 stretches the switching period in order to
keep the low-side switching FET on-time at the minimum value,
which causes the CCM switching frequency to drop below the set
point.
In Battery Learn mode, the ISL9237 turns on BGATE, keeps
ASGATE on, however, turns off the buck-boost switcher
regardless of whether the adapter is present or not.
There are three ways of exiting Battery Learn mode:
1. Receive Battery Learn mode exit command through SMBus.
2. Battery voltage is less than MinSystemVoltage register setting
(according to Control1 register Bit<12> setting).
3. BATGONE pin voltage goes from logic LOW to HIGH.
In all these cases, the ISL9237 resumes switching immediately
to supply power to the system bus from the adapter in order to
prevent system voltage collapse.
FN8723 Rev.5.00
Nov 29, 2017
Page 29 of 40
ISL9237
output surge current without requiring the charger to enter Turbo
mode. Such operation maximizes battery life.
Turbo Mode Support
Turbo mode refers to the scenario when the system draws more
power than the adapter’s power rating.
AdapterCurrentLimit1 register value can be higher or lower than
AdapterCurrentLimit2 value.
If the adapter current reaches the AdapterCurrentLimit1 register
set value (or AdapterCurrentLimit2 register set value, if two-level
adapter current limit function is enabled), or the adapter input
voltage drops to the input voltage regulation reference set by
Control0 register 0x39H Bit<1:0>, the ISL9237 will limit the
input power by regulating the adapter current at
The two-level adapter current limit function can be enabled and
disabled through SMBus Control2 register Bit<12>. When the
two-level adapter current limit function is disabled, only
AdapterCurrentLimit1 value is used as the adapter current limit
and AdapterCurrentLimit2 value is ignored.
AdapterCurrentLimit1/2 register set value, or by regulating the
adapter voltage at the input voltage regulation reference point.
I
t2
t2
t1
t1
In Turbo mode, the system bus voltage VSYS will drop
automatically or the charging current will drop automatically to
limit the adapter input power. If the VSYS pin voltage is 150mV
lower than the VBAT pin voltage, BGATE FET will turn on, such
that the battery supplies the rest of the power required by the
system.
AdapterCurrentLimit2
AdapterCurrentLimit1
I_Adapter
I
T
T
If the ISL9237 detects 150mA charging current or if the battery
discharging current is less than 300mA for longer than 20ms, it
will turn off BGATE to exit Turbo mode. Refer to Table 19 for
BGATE control logic.
I_System
I_Battery
FIGURE 32. TWO LEVEL ADAPTER CURRENT LIMIT
TABLE 19. BGATE ON/OFF TRUTH TABLE
Current Monitor
TURBO
(CONTROL CHARGECURRENT
The ISL9237 provides an adapter current monitor or a battery
BIT)
REGISTER
BGATE ON/OFF
discharging current monitor through the AMON/BMON pin. The
AMON output voltage is 18x the (CSIP-CSIN) voltage and the BMON
output voltage is 18x the (CSON-CSOP) voltage.
SYSTEM
LOAD IN
TURBO
MODE
SYSTEM LOAD NOT
IN TURBO MODE
RANGE
AMON and BMON function can be enabled or disabled through
SMBus Control1 register Bit<5> and Bit<4> as Table 12 on
page 22 shows.
0 = ENABLE
1 = DISABLE
0 = ZERO
1 = NONZERO
RANGE
0
0
0
1
OFF
ON
ON
PSYS Monitor
The ISL9237 PSYS pin provides a measure of the instantaneous
power consumption of the entire platform. The PSYS pin outputs a
current source described by Equation 1.
ON for fast charge;
Trickle charge is
enabled
1
1
0
1
OFF
OFF
ON
ON for fast charge;
Trickle charge is
enabled
(EQ. 1)
I
= K
V
I
+ V
I
BAT
PSYS
PSYS
ADP
ADP
BAT
K
R
is based on current sensing resistor R = 20mΩ and
s1
PSYS
s2
= 10mΩ. V
is the adapter voltage in volts, I
is the
is the battery voltage and I
ADP
ADP
Two-Level Adapter Current Limit
adapter current in amperes, V
BAT
BAT
In a real system, Turbo event usually does not last very long. It is
often no longer than milliseconds, a time length during which the
adapter can supply current higher than its DC rating. The
ISL9237 employs two-level adapter current limit in order to fully
take advantage of adapter’s surge capability and minimize the
power drawn from the battery.
is the battery discharging current. When the battery is
discharging, I is a positive value; when the battery is being
BAT
is a negative value. The battery voltage V
charged, I
is
BAT
BAT
detected through the CSON pin to maximize the power monitor
accuracy in NVDC configuration trickle charge mode.
The R to R ratio must be 2:1 for a valid power calculation to
s1 s2
Figure 32 shows the two SMBus programmable adapter current
limit levels, AdapterCurrentLimit1 and AdapterCurrentLimit2, as
well as the durations t1 and t2. The two-level adapter current
limit function is initiated when the adapter current is less than
100mA lower than the AdapterCurrentLimit1 register setting and
it starts at AdapterCurrentLimit2 for t2 duration and then
changes to AdapterCurrentLimit1 for t1 duration before
occur. If the resistance values are higher (or lower) than the
suggested values above, K will be proportionally higher (or
PSYS
lower). As an example, if R = 10mΩ and R = 5mΩ, then the
s1 s2
output current will be half the value for the same power. If the
PSYS information is not needed then any R :R ratio is
s1 s2
acceptable.
The PSYS information includes the power loss of the charger
circuit and the actual power delivered to the system. Resistor
repeating the pattern. These parameters can set adapter current
limit with an envelope that allows the adapter to temporarily
FN8723 Rev.5.00
Nov 29, 2017
Page 30 of 40
ISL9237
connected between the PSYS pin and GND converts the
R
its value instead of resetting to zero. If a timeout occurs,
MaxSystemVoltage or ChargeCurrent register must be written to
re-enable charging.
PSYS
PSYS information from current to voltage.
PSYS accuracy limits and a typical accuracy scan are shown in
Figure 33 on page 31.
The ISL9237 allows users to disable the charger timeout function
through SMBus Control0 register Bit<7> as Table 11 on page 22
shows.
USB OTG (On-the-Go)
When the OTG function is enabled with SMBus command and
OTGEN pin, and if battery voltage V
is higher than 5.8V,
BAT
ISL9237 operates in the reverse Buck mode, Q4, Q3 and L1
consists of the reverse buck regulator and Q1 remains on and Q2
remains off.
Once ISL9237 receives the command to enable the OTG
function, it will start switching after the 1.3s or 150ms debounce
time set by Control2 register Bit<13>. Once the OTG output
voltage is between 4.2V and 6V, OTG power-good OTGPG will
assert to High. Moreover, Control2 register Bit<5> can be used to
turn ASGATE FET off to cut off the OTG output.
FIGURE 33. PSYS ACCURACY AND LIMITS
The PSYS function can be enabled or disabled through SMBus
Control1 register Bit<3> as shown in Table 12 on page 22.
In battery only mode, the PSYS function cannot work if the
battery voltage is less than 5.8V.
Before OTG mode starts switching, the CSIP pin voltage needs to
drop below the OTG output overvoltage protection threshold of
6V first.
Trickle Charging
The default OTG output voltage is 5.12V. The OTGVoltage register
0x49H can be used to configure the OTG output voltage.
The ISL9237 supports trickle charging to an overly discharged
battery. It can activate the trickle charging function when the
battery voltage is lower than MinSystemVoltage setting. VBAT pin
is the battery voltage sense point for trickle charge mode.
The default OTG output current is limited at 512mA through R
.
s1
The OTGCurrent register 0x4AH can be used to adjust the OTG
output current limit.
To enable trickle charging, set ChargeCurrent register to a
non-zero value. To disable trickle charging, set ChargeCurrent
register to 0. Refer to Table 19 for trickle charging control logic.
ISL9237 includes the OTG output undervoltage and overvoltage
protection functions. The UVP threshold is 4.2V and the OVP
threshold is 6V.
The trickle charging current can be programmed to be 256mA,
128mA or 64mA through SMBus Control2 register Bit<15:14> in
Table 13 on page 23.
Once UV is detected, ISL9237 will stop switching and turn off
ASGATE and deassert OTGPG. Once OTG output increases above
4.5V, after 1.3s or 150ms debounce time set by Control2 register
Bit<13>, it will resume switching.
In trickle charging mode, the ISL9237 regulates the trickle
charging current through the buck-boost switcher. Another
independent control loop controls the BGATE FET such that the
system voltage is maintained at the voltage set in the
MinSystemVoltage register. The VSYS pin is the system voltage
sensing point in trickle charging mode.
Once OV is detected, ISL9237 will stop switching and deassert
OTGPG. It will resume switching after 100µs once OTG voltage
drops below 5.7V.
BATGONE needs to be low to enable OTG mode. OTG mode is not
available for 1-cell battery systems.
Once the battery voltage is charged the MinSystemVoltage register
value, the ISL9237 enters fast charging mode by limiting the
charging current at the ChargeCurrentLimit register setting.
Stand-Alone Comparator
The ISL9237 includes a general purpose stand-alone
System Voltage Regulation
comparator. OTGEN/CMIN pin is the comparator input. The
internal comparator reference is connected to the inverting input
of the comparator and can be configured as 1.2V or 2V through
SMBus Control2 register Bit<4>. The comparator output is the
OTGPG/CMOUT pin and the output polarity when the comparator
is tripped can be configured through SMBus register bit.
If the battery is absent, or if a battery is present, however, BGATE
is turned off, the ISL9237 will regulate the system bus voltage at
the MaxSystemVoltage register setting. The VSYS pin is used to
sense the system bus voltage.
Charger Timeout
When Control2 register Bit<2> = 0 for normal comparator output
polarity, if CMIN > Reference then CMOUT = High; if
CMIN < Reference then CMOUT = Low.
The ISL9237 includes a timer to insure the SMBus master is active
and to prevent overcharging the battery. The ISL9237 will
terminate charging by turning off BGATE FET if the charger has not
received a write command to the MaxSystemVoltage or
ChargeCurrent register within 175s. When the charging is
terminated by the timeout, the ChargeCurrent register will retain
When Control2 register Bit<2> = 1 for inversed comparator
output polarity, if CMIN > Reference then CMOUT = Low; if
CMIN < Reference then CMOUT = High.
FN8723 Rev.5.00
Nov 29, 2017
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ISL9237
In battery only mode, the stand-alone comparator is disabled
unless PSYS is enabled through SMBus Control1 register Bit<3>
to enable the internal reference, which is indicated through
Information register Bit<15>.
Table 20 shows the OTG mode and the stand-alone comparator
truth table.
TABLE 20. OTG AND COMPARATOR TRUTH TABLE
CONTROL1
CONTROL2
REGISTER 0x3C
REGISTER 0x3D
PIN-2O
PIN-26
BIT<11>
BIT<3>
OTG FUNCTION
COMPARATOR
ENABLE/DISABLE ENABLE/DISABLE OTGEN/CMIN
OTGPG/CMOUT
DESCRIPTION
0
0
Comparator
Comparator output OTG function is disabled.
input pin CMIN pin CMOUT
Comparator is enabled.
Both OTG function and comparator are disabled.
Comparator output Both OTG function and comparator are enabled.
0
1
1
0
X
X
Comparator
input pin CMIN pin CMOUT
OTG function is enabled when V > 5.8V and Control1 register
BAT
Bit<11> = 1 without OTG power-good pin indication. While the
Information register 0x3A Bit<6:5> = 11 indicates it is in OTG mode.
1
1
OTG enable
OTG power-good
Comparator is disabled.
input pin OTGEN indication pin
OTGPG
OTG function is enabled when V
Control1 register Bit<11> = 1
> 5.8V and ENOTG pin = High and
BAT
FN8723 Rev.5.00
Nov 29, 2017
Page 32 of 40
ISL9237
Adapter Overvoltage Protection
Switching Power MOSFET Gate Capacitance
If the ADP pin voltage exceeds 23.4V for more than 10µs, the
ISL9237 will consider an adapter overvoltage condition has
occurred. It will turn off the ASGATE MOSFETs to isolate the
adapter from the system, deassert the ACOK signal by pulling it
low and stop switching. BGATE will turn on for the battery to
support the system load. Once ADP voltage drops below 23.04V
from more than 100µs, it will start to turn on ASGATE and start
switching.
The ISL9237 includes an internal 5V LDO output at VDD pin,
which can be used to provide the switching MOSFET gate driver
power through VDDP pin with an R-C filter. The 5V LDO output
overcurrent protection threshold is 70mA nominal. When
selecting the switching power MOSFET, the MOSFET gate
capacitance should be considered carefully to avoid overloading
the 5V LDO, specially in Buck-boost mode when four MOSFETs
switching at the same time. For one MOSFET, the gate drive
current can be estimated by Equation 2:
System Overvoltage Protection
(EQ. 2)
I
= Q f
g
SW
driver
The ISL9237 provides system rail overvoltage protection. If the
system voltage VSYS is 600mV higher than MaxSystemVoltage
register set value, it will declare the system overvoltage and stop
switching. It will resume switching without the 1.3s or 150ms
debounce once VSYS drops 300mV below the system
overvoltage threshold.
Where:
• Q is the total gate charge, which can be found in the MOSFET
g
datasheet
• f
SW
is switching frequency
Way Overcurrent Protection (WOCP)
Adapter Input Filter
In the case that the system bus is shorted, either a MOSFET short
or an inductor short, the input current could be high. ISL9237
includes input overcurrent protection to turn off the ASGATE and
stop switching.
The adapter cable parasitic inductance and capacitance could
cause some voltage ringing or an overshoot spike at the adapter
connector node when the adapter is hot plugged in. This voltage
spike could damage the ASGATE MOSFET or the ISL9237 pins
connecting to the adapter connector node. One low cost solution
is to add an RC snubber circuit at the adapter connector node to
clamp the voltage spike as shown in Figure 34. A practical value
of the RC snubber is 2.2Ω to 2.2µF while the appropriate values
and power rating should be carefully characterized based on the
actual design. Meanwhile, it is not recommended to add a pure
capacitor at the adapter connector node, which can cause an
even bigger voltage spike due to the adapter cable or the adapter
current path parasitic inductance.
The ISL9237 provides adapter current and battery discharging
current WOCP (Way Overcurrent Protection) function against the
MOSFET short, system bus short and inductor short scenarios.
ISL9237 monitors the CSIP-CSIN voltage and CSON-CSOP
voltage, compares them with the WOCP threshold 12A for
adapter current and 16A for battery discharge current.
When the WOC comparator is tripped, ISL9237 counts one time
within each 20µs. Whenever ISL9237 counts WOC to 7 times in
656ms, it turns off ASGATE, deasserts ACOK and stops switching
immediately. After the 1.3s or 150ms debounce time set by
Control2 register Bit<11>, it goes through the start-up sequence
to retry.
ADAPTER
CONNECTOR
The WOCP function can be disabled through Control2 register
Bit<1>.
Ri
2.2
ASGATE
Over-Temperature Protection
The ISL9237 turns off the internal LDO for self protection when
the junction temperature exceeds +140°C. The internal LDO
stays off until the junction temperature falls below +120°C.
Ci
2.2µF
ACIN
RC SNUBBER
ISL9237
The ISL9237 stops switching after declaring over-temperature
protection.
Once the temperature falls below +120°C, and after a 100µs
delay, the ISL9237 will enable the internal LDO and the ISL9237
will resume operation.
FIGURE 34. ADAPTER INPUT RC SNUBBER CIRCUIT
FN8723 Rev.5.00
Nov 29, 2017
Page 33 of 40
ISL9237
capacitor can fade as much as 50% as the DC voltage across it
increases.
General Application Information
This design guide is intended to provide a high-level explanation of
the steps necessary to design a single-phase power converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced in the following section. In addition to
this guide, Intersil provides complete reference designs that
include schematics, bill of materials and example board layouts.
Select the Input Capacitor
The important parameters for the input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select capacitors with voltage and current ratings above the
maximum input voltage and capable of supplying the RMS
current required by the switching circuit. Their voltage rating
should be at least 1.25x greater than the maximum input
voltage, while a voltage rating of 1.5x is a preferred rating.
Figure 35 is a graph of the input capacitor RMS ripple current,
normalized relative to output load current, as a function of duty
cycle and is adjusted for converter efficiency. The normalized RMS
ripple current calculation is written as Equation 8:
Select the LC Output Filter
The duty cycle of an ideal buck converter in CCM is a function of
the input and the output voltage. This relationship is written by
Equation 3:
V
OUT
(EQ. 3)
---------------
D =
V
IN
2
D k
12
--------------
D 1 – D +
-----------------------------------------------------------------------
I
The output inductor peak-to-peak ripple current is written by
Equation 4:
MAX
I
=
RMS,NORMALIZED
C
(EQ. 8)
I
IN
MAX
V
OUT 1 – D
(EQ. 4)
-------------------------------------
=
I
P-P
Where:
• I
SW L
f
is the maximum continuous I
of the converter
LOAD
MAX
A typical step-down DC/DC converter will have an I
P-P
of 20% to
40% of the maximum DC output load current for a practical
design. The value of I is selected based upon several criteria
such as MOSFET switching loss, inductor core loss and the
resistive loss of the inductor winding.
• k is a multiplier (0 to 1) corresponding to the inductor
peak-to peak ripple amplitude expressed as a ratio of I
(0 to 1)
P-P
MAX
• D is the duty cycle that is adjusted to take into account the
efficiency of the converter, which is written as Equation 9:
The DC copper loss of the inductor can be estimated by
Equation 5:
V
OUT
EFF
--------------------------
D =
2
V
(EQ. 9)
(EQ. 5)
P
= I
DCR
IN
COPPER
LOAD
In addition to the capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET.
Where I
LOAD
is the converter output DC current.
The copper loss can be significant so attention has to be given to the
DCR selection. Another factor to consider when choosing the
inductor is its saturation characteristics at elevated temperatures. A
saturated inductor could cause destruction of circuit components.
0.60
A DC/DC buck regulator must have output capacitance C into
O
0.48
k = 0.25
which ripple current I
can flow. Current I
develops a
P-P
P-P
across C which is the sum of
corresponding ripple voltage V
P-P
O,
k = 0.5
the voltage drop across the capacitor ESR and of the voltage
change stemming from charge moved in and out of the
capacitor. These two voltages are written by Equations 6 and 7:
k = 0
0.36
k = 1
k = 0.75
(EQ. 6)
0.24
V
= I
P-P ESR
ESR
V
= ±2.5V
S
I
P-P
0.12
0
-----------------------------
(EQ. 7)
V
=
C
8 C
O f
SW
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled to
0
0.1
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.2
reduce the total ESR until the required V is achieved. The
DUTY CYCLE
P-P
inductance of the capacitor can cause a brief voltage dip if the
load transient has an extremely high slew rate. Low inductance
capacitors should be considered in this scenario. A capacitor
dissipates heat as a function of RMS current and frequency. Be
FIGURE 35. NORMALIZED RMS INPUT CURRENT AT EFF = 1
sure that I
is shared by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated RMS
P-P
current at f . Take into account that the rated value of a
SW
FN8723 Rev.5.00
Nov 29, 2017
Page 34 of 40
ISL9237
Select the Switching Power MOSFET
Select the Bootstrap Capacitor
Typically, a MOSFET cannot tolerate even brief excursions beyond
their maximum drain-to-source voltage rating. The MOSFETs used
in the power stage of the converter should have a maximum VDS
rating that exceeds the sum of the upper voltage tolerance of the
input power source and the voltage spike that occurs when the
MOSFET switches off.
The selection of the bootstrap capacitor is written by
Equation 13:
Q
g
-----------------------
(EQ. 13)
C
=
BOOT
V
BOOT
Where:
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the device
spends the least amount of time dissipating power in the linear
region. Unlike the low-side MOSFET which has the drain-to-source
voltage clamped by its body diode during turn off, the high-side
• Q is the total gate charge required to turn on the high-side
g
MOSFET.
• V
, is the maximum allowed voltage decay across the
BOOT
boot capacitor each time the high-side MOSFET is switched on.
As an example, suppose the high-side MOSFET has a total gate
MOSFET turns off with a VDS of approximately V - V
, plus
IN OUT
charge Q , of 25nC at V = 5V and a V
GS BOOT
of 200mV. The
g
the spike across it. The preferred low-side MOSFET emphasizes
low r when fully saturated to minimize conduction loss. It
calculated bootstrap capacitance is 0.125µF; for a comfortable
margin, select a capacitor that is double the calculated
capacitance. In this example, 0.22µF will suffice. Use an X7R or
X5R ceramic capacitor.
DS(ON)
should be noted that this is an optimal configuration of MOSFET
selection for low duty cycle applications (D < 50%). For higher
output, low input voltage solutions, a more balanced MOSFET
selection for high- and low-side devices may be warranted.
For the low-side (LS) MOSFET, the power loss can be assumed to
be conductive only and is written as Equation 10:
2
P
I
r
DSON_LS 1 – D
(EQ. 10)
CON_LS
LOAD
For the high-side (HS) MOSFET, or conduction loss is written by
Equation 11:
2
P
= I
r
DSON_HS D
(EQ. 11)
CON_HS
LOAD
For the high-side MOSFET, the switching loss is written as
Equation 12:
V
V
IN IPEAK tSWOFF f
IN IVALLEY tSWON f
SW
SW
-------------------------------------------------------------------------- ----------------------------------------------------------------------
P
=
+
SW_HS
2
2
(EQ. 12)
Where:
• I
is the difference of the DC component of the inductor
VALLEY
current minus 1/2 of the inductor ripple current.
• I
is the sum of the DC component of the inductor current
PEAK
plus 1/2 of the inductor ripple current.
• t
• t
is the time required to drive the device into saturation.
is the time required to drive the device into cut-off.
SW(ON)
SW(OFF)
FN8723 Rev.5.00
Nov 29, 2017
Page 35 of 40
Q6 is for:
Q7 is for:
OTG mode output ON/OFF control;
Input voltage polarity reverse protection.
Adapter plug in inrush current control;
Input OVP control.
Components in dot line frame are optional
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FIGURE 38. ISL9237 REFERENCE DESIGN
ISL9237
Layout Guidelines
PIN NUMBER
PIN NAME
LAYOUT GUIDELINES
BOTTOM PAD
33
GND
Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to
connect to ground planes in PCB to ensure there is sufficient thermal dissipation directly under the IC.
1
2
CSON
CSOP
Run two dedicated traces with decent width in parallel (close to each other to minimize the loop area) from the two
terminals of the battery current sensing resistor to the IC. Place the differential mode and common-mode RC filter
components in general proximity of the controller.
Route the current sensing traces through vias to connect the center of the pads; or route the traces into the pads from
the inside of the current sensing resistor. The following drawings show the two preferred ways of routing current
sensing traces.
VIAS
CURRENT-SENSING TRACES CURRENT-SENSING TRACES
3
4
VSYS
Signal pin. Provides feedback for the system bus voltage. Place the optional RC filter in general proximity of the
controller. Run a dedicated trace from system bus to the pin and do not route near the switching traces. Do not share
the same trace with the signal routing to the DCIN pin OR diodes.
BOOT2
Switching pin. Place the bootstrap capacitor in general proximity of the controller. Use decent wide trace. Avoid any
sensitive analog signal trace from crossing over or getting close.
5
6
UGATE2
PHASE2
Run these two traces in parallel fashion with decent width. Avoid any sensitive analog signal trace from crossing over
or getting close. Recommend routing PHASE2 trace to high-side MOSFET source pin instead of general copper.
The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal traces short
for a clean MOSFET drive. The IC can be placed on the opposite side of the switching MOSFETs.
Place the output capacitors as close as possible to the switching high-side MOSFET drain and the low-side MOSFET
source; and use shortest PCB trace connection. Place these capacitors on the same PCB layer with the MOSFETs
instead of on different layers and using vias to make the connection.
Place the inductor terminal to the switching high-side MOSFET drain and low-side MOSFET source terminal as close
as possible. Minimize this phase node area to lower the electrical and magnetic field radiation, however, make this
phase node area big enough to carry the current. Place the inductor and the switching MOSFETs on the same layer of
the PCB.
7
8
9
LGATE2
VDDP
Switching pin. Run LGATE2 trace in parallel with UGATE2 and PHASE2 traces on the same PCB layer. Use decent
width. Avoid any sensitive analog signal trace from crossing over or getting close.
Place the decoupling capacitor in general proximity of the controller. Run the trace connecting to VDD pin with decent
width.
LGATE1
Switching pin. Run LGATE1 trace in parallel with UGATE1 and PHASE1 traces on the same PCB layer. Use decent
width. Avoid any sensitive analog signal trace from crossing over or getting close.
10
11
PHASE1
UGATE1
Run these two traces in parallel fashion with decent width. Avoid any sensitive analog signal trace from crossing over
or getting close. Recommend routing PHASE1 trace to high-side MOSFET source pin instead of general copper.
The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal traces short
for a clean MOSFET drive. The IC can be placed on the opposite side of the switching MOSFETs.
Place the input capacitors as close as possible to the switching high-side MOSFET drain and the low-side MOSFET
source; and use shortest PCB trace connection. Place these capacitors on the same PCB layer with the MOSFETs
instead of on different layers and using vias to make the connection.
Place the inductor terminal to the switching high-side MOSFET drain and low-side MOSFET source terminal as close
as possible. Minimize this phase node area to lower the electrical and magnetic field radiation, however, make this
phase node area big enough to carry the current. Place the inductor and the switching MOSFETs on the same layer of
the PCB.
FN8723 Rev.5.00
Nov 29, 2017
Page 37 of 40
ISL9237
Layout Guidelines(Continued)
PIN NUMBER
PIN NAME
LAYOUT GUIDELINES
12
BOOT1
Switching pin. Place the bootstrap capacitor in general proximity of the controller. Use decent wide trace. Avoid any
sensitive analog signal trace from crossing over or getting close.
13
14
15
ASGATE
CSIN
Run this trace with decent width in parallel fashion with the ADP pin trace.
Run two dedicated traces with decent width in parallel (close to each other to minimize the loop area) from the two
terminals of the adapter current sensing resistor to the IC. Place the differential mode and common-mode RC filter
components in general proximity of the controller.
CSIP
Route the current sensing traces through vias to connect the center of the pads; or route the traces into the pads from
the inside of the current sensing resistor. The following drawings show the two preferred ways of routing current
sensing traces.
VIAS
CURRENT-SENSING TRACES CURRENT-SENSING TRACES
16
17
ADP
Run this trace with decent width in parallel fashion with the ASGATE pin trace.
DCIN
Place the OR diodes and the RC filter in general proximity of the controller. Run the VADP trace and VSYS trace to the
OR diodes with decent width.
18
VDD
Place the RC filter connecting with VDDP pin in general proximity of the controller. Run the trace connecting to VDDP
pin with decent width.
19
20
21
22
23
24
25
ACIN
Place the voltage divider resistors and the optional decoupling capacitor in general proximity of the controller.
OTGEN/CMIN No special consideration.
SDA
SCL
Digital pins. No special consideration. Run SDA and SCL traces in parallel.
PROCHOT#
ACOK
Digital pin, open-drain output. No special consideration.
BATGONE
Digital pin. Place the 100kΩ resistor series in the BATGONE signal trace and the optional decoupling capacitor in
general proximity of the controller.
26
27
28
OTGPG/CMOUT Digital pin, open-drain output. No special consideration.
PROG
COMP
Signal pin. Place the PROG programming resistor in general proximity of the controller.
Place the compensation components in general proximity of the controller. Avoid any switching signal from crossing
over or getting close.
29
30
31
AMON/BMON No special consideration. Place the optional RC filter in general proximity of the controller.
PSYS
VBAT
Signal pin, current source output. No special consideration.
Place the optional RC filter in general proximity of the controller. Run a dedicated trace from the battery positive
connection point to the IC.
32
BGATE
Use decent width trace from the IC to the BGATE MOSFET gate. Place the capacitor from BGATE to ground close to the
MOSFET.
FN8723 Rev.5.00
Nov 29, 2017
Page 38 of 40
ISL9237
Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not
warranted. Please go to the web to make sure that you have the latest revision.
DATE
REVISION
FN7823.5
FN7823.4
CHANGE
Nov 29, 2017
October 4, 2017
Added Way Overcurrent Protection (WOCP) function to datasheet.
Applied new header/footer and formatting.
Updated Related Literature Removed Way Overcurrent Protection (WOCP) feature from datasheet. Made
Bit 1 on page 24 “Not used”.
July 7, 2016
June 7, 2016
FN8723.3
FN8723.2
Removed confidential information to make the datasheet publicly available on the web.
Added Related Literature section.
Updated the Ordering Information table by adding the Evaluation board part number.
Fixed typo on Figure 2 on page 5.
Updated “Power Source Selection” on page 29.
Updated “Stand-Alone Comparator” on page 31.
May 12, 2016
FN8723.1
Updated Note 1 by adding “-T7A” option.
Removed Evaluation Board from ordering information table.
-Table 13 on page 23 updated Bit 11 from "Bit<11> configures the debounce time from ACOK assertion
to switching" to "Bit<11> configures the debounce time from adapter insertion to ASGATE turning on" and
changed the Bit name from “Adapter Insertion to Switching Debounce” to “Adapter Insertion to ASGATE
Turning ON Debounce”.
-Table 18 on page 28 added Min and Max column to the table and updated Typ 1% values. Changed the
note from "207kΩ is not standard resistor" to "203kΩ is not standard resistor”.
February 10, 2016
FN8723.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
For a listing of definitions and abbreviations of common terms used in our documents, visit: www.intersil.com/glossary.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2016-2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8723 Rev.5.00
Nov 29, 2017
Page 39 of 40
ISL9237
For the most recent package outline drawing, see L32.4x4A.
Package Outline Drawing
L32.4x4A
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 2/16
8X 0.36
8X 0.179
6
4.00 ±0.05
2.80
6
A
B
PIN 1
PIN #1
28X 0.40
INDEX AREA
INDEX AREA
8X 0.179
(4X)
0.15
24X 0.40
32X 0.20
4
0.10
M
C
A B
TOP VIEW
BOTTOM VIEW
(3.80)
(2.80)
SEE DETAIL “X”
0.90 ±0.10
// 0.10C
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
(28X 0.40)
5
C
0.2 REF
(32X 0.20)
(32X 0.60)
0.00 MIN
0.05 MAX
TYPICAL RECOMMENDED LAND PATTERN
DETAIL “X”
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ±0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8723 Rev.5.00
Nov 29, 2017
Page 40 of 40
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