ISL94202IRTZ_技术文档

DATASHEET

ISL94202

FN8889

Rev.2.00

Mar 8, 2017

Series Charge/Discharge Path 3-to-8 Cell Li-Ion Battery Pack Monitor

1. Overview

The ISL94202 is a Li-ion battery monitor IC that supports from three to eight series connected cells. It provides complete

battery monitoring and pack control. The ISL94202 provides automatic shutdown and recovery from out-of-bounds conditions

and automatically controls pack cell balancing.

The ISL94202 is highly configurable as a stand-alone unit, but can be used with an external microcontroller, which

2

communicates to the IC through an I C interface.

1.1

Features

• Eight cell voltage monitors support Li-ion CoO , Li-ion Mn O , and Li-ion FePO chemistries

2

4

• Stand-alone pack control - no microcontroller needed

• Multiple voltage protection options (each programmable to 4.8V; 12-bit digital value) and selectable overcurrent

protection levels

• Programmable detection/recovery times for overvoltage, undervoltage, overcurrent, and short-circuit conditions

• Configuration/calibration registers maintained in EEPROM

• Open battery connect detection

• Integrated charge/discharge FET drive circuitry with built-in charge pump supports high-side N-channel FETs

• Cell balancing uses external FETs with internal state machine or external microcontroller

• Enters low power states after periods of inactivity

• Charge or discharge current detection resumes normal scan rates

1.2

Applications

• Power tools

• Battery back-up systems

• Light electric vehicles

• Portable equipment

• Energy storage systems

• Solar farms

• Medical equipment

• Hospital beds

• Monitoring equipment

• Ventilators

1.3

Related Literature

• For a full list of related documents, visit our website

• ISL94202 product page

FN8889 Rev.2.00

Mar 8, 2017

Page 1 of 89

ISL94202

1. Overview

1.4

Typical Application Diagram

P+

43V

VBATT

VC8

PSD

CB8

VC7

FETSOFF

CB7

VC6

INT

RGO

CHRG

CB6

VC5

ISL94202

CB5

VC4

SD

EOC

CB4

VC3

SCL

CB3

VC2

SDA

TEMPO

CB2

VC1

xT1

xT2

CB1

VC0

VREF

VSS

ADDR

GND

P-

Figure 1.1

Typical Application Diagram

FN8889 Rev.2.00

Mar 8, 2017

Page 2 of 89

ISL94202

1. Overview

1.5

Block Diagram

N-CHANNEL FETs

P+

PACK+

VDD

+16V

CS2

CS1

CURRENT-SENSE GAIN AMPLIFIER

x5/x50/x500 GAIN

OVERCURRENT STATE MACHINE

O.C.

RECOVERY

WAKEUP

CIRCUIT

FET CONTROLS/CHARGE PUMP

100Ω

POWER-ON

RESET STATE

MACHINE

470nF

VBATT

VC8

1kΩ

EOC

330kΩ

47nF

EOC/SD

ERROR CONDITIONS

(OV, UV, SLP STATE MACHINES)

10kΩ

1kΩ

VSS

CB8

CB7

CB6

SD

CB STATE

MACHINE

CB8:1

VC7

VC6

VC5

VC4

330kΩ

47nF

10kΩ

VSS

FETSOFF

1kΩ

PSD

INT

330kΩ

47nF

RAM

10kΩ

1kΩ

EEPROM

REGISTERS

TEMP/VOLTAGE

MONITOR ALU

47nF

10kΩ

CB5

CB4

CB3

330kΩ

MEMORY

MANAGER

1kΩ

47nF

LDO

RGO

REG

RGO (OUT)

OSC

10kΩ

TIMING

AND

CONTROL

SCAN STATE

CB STATE

OVERCURRENT STATE

330kΩ

VC3

VC2

VC1

1kΩ

47nF

SCAN STATE

MACHINE

EOC/SD/ERROR STATE

SDAO

SDAI

SCL

10kΩ

330kΩ

2

I C

ADDR

1kΩ

47nF

10kΩ

TEMPO

CB2

CB1

330kΩ

WATCHDOG TIMER

1kΩ

47nF

xT2

xT1

xT2

xT1

10kΩ

14-BIT

ADC

TEMP

330kΩ

VB/16

iT

RGO/2

T

GAIN

VC0

x1/x2

BAT-

VREF

P-

VREF

V

SS

PACK-

Figure 1.2

Block Diagram

FN8889 Rev.2.00

Mar 8, 2017

Page 3 of 89

ISL94202

1. Overview

1.6

Ordering Information

Part Number

(Notes 1 2, 3)

Part

Marking

Temp. Range

(°C)

Package

(RoHS Compliant)

Pkg.

Dwg. #

ISL94202IRTZ

94202 IRTZ

-40 to +85

48 Ld TQFN

L48.6x6

ISL94202EVKIT1Z

Notes:

Evaluation Kit

1. Add “-T” suffix for 4k unit, “-T7” for 1k unit, or “-T7A” suffix for 250 unit tape and reel options. Refer to TB347 for details on

reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures

that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), see product information page for ISL94202. For more information on MSL, see tech

brief TB363.

Table 1.1

Key Differences Between Family of Parts

Pack

Voltage

(Op)

Cells

Supported

Supply Current

(Typ)

Charge/Discharge FET

Stand-

Alone

Capable

Cell

Current

Internal Daisy

Part #

Balance Sense

ADC

Chain

Min Max

(V) (V)

Min Max

Control Arrangement Location Normal Sleep

ISL94202

ISL94203

ISL94208

ISL94212

High

Side

High

Side

3

8

4

36 External

Yes

One Path

Two Path

348µA 13µA

Yes

No

High

Side

High

Side

Low

Side

4

6

8

6

26.4 Internal

60 External

Yes

No

Both

N/A

Low Side 850µA 2µA

N/A 3.31mA 12µA

No

12

No

Yes

FN8889 Rev.2.00

Mar 8, 2017

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ISL94202

1. Overview

1.7

Pin Configuration

ISL94202

(48 LD TQFN)

TOP VIEW

48 47 46 45 44 43 42 41 40 39 38 37

1

2

36

35

34

33

VC8

CB8

VC7

CB7

VC6

CB6

RGO

EOC

3

SD

4

FETSOFF

5

32 PSD

31

6

INT

30 DNC

PAD

(GND)

7

VC5

CB5

VC4

8

29

28

VSS

9

CB4

10

27 SDAO

SDAI

SCL

VC3 11

CB3

26

25

12

13 14 15 16 17 18 19 20 21 22 23 24

FN8889 Rev.2.00

Mar 8, 2017

Page 5 of 89

ISL94202

1. Overview

1.8

Pin Descriptions

Number

Symbol

Description

Battery cell n voltage input. This pin is used to monitor the voltage of this battery cell. The voltage is level

shifted to a ground reference and is monitored internally by an ADC converter. VCn connects to the positive

terminal of a battery cell (CELLN) and VC(n-1) the negative terminal of CELLN (VSS connects with the

negative terminal of CELL1).

1, 3, 5, 7,

9, 11, 13,

15, 17

VC[8:0]

Cell balancing FET control output n. This internal drive circuit controls an external FET used to divert a

2, 4, 6, 8,

portion of the current around a cell while the cell is being charged or adds to the current pulled from a cell

10, 12, 14, CB[8:1] during discharge in order to perform a cell voltage balancing operation. This function is generally used to

16

reduce the voltage on an individual cell relative to other cells in the pack. The cell balancing FETs are turned

on or off by an internal cell balance state machine or an external controller.

18, 28, 29

VSS

VREF

XT1

Ground. This pin connects to the most negative terminal in the battery string.

Voltage Reference Output. This output provides a 1.8V reference voltage for the internal circuitry and for the

external microcontroller.

19

20

21

Temperature monitor inputs. These pins input the voltage across two external thermistors used to determine

the temperature of the cells and or the power FET. When this input drops below the threshold, an external

over-temperature condition exists.

XT2

Temperature Monitor Output Control. This pin outputs a voltage to be used in a divider that consists of a

fixed resistor and a thermistor. The thermistor is located in close proximity to the cells or the power FET. The

TEMPO output is connected internally to the VREF voltage through a PMOS switch only during a

measurement of the temperature, otherwise the TEMPO output is off.

22

TEMPO

23, 30

24

DNC

ADDR

SCL

Do not connect

Serial Address. This is an address input for an I²C communication link to allow for two devices on one bus.

Serial Clock. This is the clock input for an I²C communication link.

25

Serial Data. These are the data lines for an I²C interface. When connected together, they form the standard

bidirectional interface for the I²C bus (recommended). When separated, they can use separate level shifters for

two-device operation (not supported).

26

SDAI

27

31

SDAO

INT

Interrupt. This pin goes active low when there is an external µC connected to the ISL94202 and µC

communication fails to send a slave byte within a watchdog timer period. This is a CMOS type output.

Pack Shutdown. This pin goes active high when any cell voltage reaches the OVLO threshold (OVLO flag).

Optionally, PSD is also set if there is a voltage differential between any two cells that is greater than a specified

limit (CELLF flag) or if there is an open-wire condition. This pin can be used for blowing a fuse in the pack or as

an interrupt to an external µC.

32

PSD

FETSOFF. This input allows an external microcontroller to turn off both Power FET and CB outputs. This pin

should be pulled low when inactive.

33

34

FETSOFF

SD

Shutdown. This output indicates that the ISL94202 detected any failure condition that would result in the

DFET turning off. This could be undervoltage, overcurrent, over-temperature, under-temperature, etc. The SD

pin also goes active if there is any charge overcurrent condition. This is an open-drain output.

End-of-Charge. This output indicates that the ISL94202 detected a fully charged condition. This is defined by

any cell voltage exceeding an EOC voltage (as defined by an EOC value in EEPROM).

35

36

EOC

RGO

Regulator Output. This is the 2.5V regulator output.

Charge Monitor. This input monitors the charger connection. When the IC is in the Sleep mode, connecting

this pin to the charger wakes up the device. When the IC recovers from a charge overcurrent condition, this pin

is used to monitor that the charger is removed prior to turning on the power FETs. In a single-path

configuration, this pin and the LDMON pin connect together.

37

CHMON

Load Monitor. This pin monitors the load connection. When the IC is in the Sleep mode, connecting this pin to

a load wakes up the device. When the IC recovers from a discharge overcurrent or short-circuit condition, this

pin is used to monitor that the load is removed prior to turning on the power FETs. In a single path

configuration, this pin and the CHMON pin connect together.

38

LDMON

C[3:1]

Charge Pump Capacitor Pins. These external capacitors are used for the charge pump driving the power

FETs.

39, 40, 41

Discharge FET Control. The ISL94202 controls the gate of a discharge FET through this pin. The power FET

is an N-channel device. The FET is turned on by the ISL94202 if all conditions are acceptable. The ISL94202

will turn off the FET in the event of an out-of-bounds condition. The FET can be turned off by an external

microcontroller by writing to the CFET control bit. The CFET output is also turned off by the FETSOFF pin. The

FET output cannot be turned on by an external microcontroller if there are any out-of-bounds conditions.

42

43

DFET

VDD

IC Supply Pin. This pin provides the operating voltage for the IC circuitry.

FN8889 Rev.2.00

Mar 8, 2017

Page 6 of 89

ISL94202

1. Overview

Number

Symbol

Description

Precharge FET Control. The ISL94202 controls the gate of a precharge FET through this pin. The power FET

is an N-channel device. The FET is turned on by the ISL94202 if all conditions are acceptable. The ISL94202

will turn off the FET in the event of an out-of-bounds condition. The FET can be turned off by an external

microcontroller by writing to the PCFET control bit. The PCFET output is also turned off by the FETSOFF pin.

The FET output cannot be turned on by an external microcontroller if there are any out-of-bounds conditions.

Either the PCFET or the CFET turn on, but not both.

44

45

PCFET

Charge FET Control. The ISL94202 controls the gate of a charge FET through this pin. The power FET is an

N-channel device. The FET is turned on by the ISL94202 if all conditions are acceptable. The ISL94202 will

turn off the FET in the event of an out-of-bounds condition. The FET can be turned off by an external

microcontroller by writing to the CFET control bit. The CFET output is also turned off by the FETSOFF pin. The

FET output cannot be turned on by an external microcontroller if there are any out-of-bounds conditions. Either

the PCFET or the CFET turn on, but not both.

CFET

46

47

CSI2

CSI1

Current-Sense Inputs. These pins connect to the ISL94202 current-sense circuit. There is an external

resistance across which the circuit operates. The sense resistor is typically in the range of 0.2mΩ to 5mΩ.

Input Level Shifter Supply and Battery Pack Voltage Input. This pin powers the input level shifters and is

also used to monitor the voltage of the battery stack. The voltage is internally divided by 32 and connected to

an ADC converter through a MUX.

48

VBATT

GND

PAD

Thermal Pad. This pad should connect to ground.

FN8889 Rev.2.00

Mar 8, 2017

Page 7 of 89

ISL94202

Contents

1.

Overview ............................................................................................................... 1

1.1

Features .................................................................................................................................... 1

Applications .............................................................................................................................. 1

Related Literature ..................................................................................................................... 1

Typical Application Diagram ..................................................................................................... 2

Block Diagram .......................................................................................................................... 3

Ordering Information ................................................................................................................. 4

Pin Configuration ...................................................................................................................... 5

Pin Descriptions ........................................................................................................................ 6

1.2

1.3

1.4

1.5

1.6

1.7

1.8

3.

Specifications ...................................................................................................... 11

Absolute Maximum Ratings .................................................................................................... 11

Thermal Information ................................................................................................................ 12

Recommended Operating Conditions ..................................................................................... 12

Electrical Specification ............................................................................................................ 13

Symbol Table .......................................................................................................................... 20

Timing Diagrams ..................................................................................................................... 20

3.1

3.2

3.3

3.4

3.5

3.6

3.6.1

3.6.2

External Temperature Configuration ................................................................................... 20

Wake-Up Timing ................................................................................................................ 21

Power-Up Timing ................................................................................................................ 21

Change in FET Control ....................................................................................................... 22

Automatic Temperature Scan ............................................................................................. 23

Serial Interface Timing Diagrams ....................................................................................... 23

Discharge Overcurrent/Short-Circuit Monitor ...................................................................... 24

Charge Overcurrent Monitor ............................................................................................... 24

3.6.3

3.6.4

3.6.5

3.6.6

3.6.7

3.6.8

4.

5.

Functional Description ........................................................................................ 25

Battery Connections ........................................................................................... 26

Power Path ............................................................................................................................. 26

Pack Configuration ................................................................................................................. 27

Battery Cell Connections ........................................................................................................ 27

5.1

5.2

5.3

6.

Operating Modes ................................................................................................ 28

Power-Up Operation ............................................................................................................... 28

Wake-Up Circuit ...................................................................................................................... 29

Low Power States ................................................................................................................... 30

6.1

6.2

6.3

6.3.1

6.3.2

Normal mode ...................................................................................................................... 30

Idle mode ............................................................................................................................ 30

Doze Mode ......................................................................................................................... 30

Sleep Mode ......................................................................................................................... 30

Power-Down Mode ............................................................................................................. 31

Exceptions .......................................................................................................................... 31

6.3.3

6.3.4

6.3.5

6.3.6

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ISL94202

7.

8.

9.

Typical Operating Conditions .............................................................................. 32

Cell Fail Detection ............................................................................................... 33

Open-Wire Detection .......................................................................................... 34

10. Current and Voltage Monitoring .......................................................................... 37

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

Current Monitor ....................................................................................................................... 37

Current Sense ......................................................................................................................... 37

Overcurrent and Short-Circuit Detection ................................................................................. 40

Overcurrent and Short-Circuit Response (Discharge) ............................................................ 40

Overcurrent Response (Charge) ............................................................................................ 41

Microcontroller Overcurrent FET Control Protection ............................................................... 42

Voltage, Temperature, and Current Scan ............................................................................... 43

Cell Voltage Monitoring ........................................................................................................... 44

10.8.1 UVLO and OVLO ................................................................................................................ 44

10.8.2 UV, OV, and Sleep .............................................................................................................. 44

10.9

Overvoltage Detection/Response ........................................................................................... 46

10.10 Undervoltage Detection/Response ......................................................................................... 48

10.11 Temperature Monitoring/Response ......................................................................................... 49

10.11.1 Over-Temperature ............................................................................................................... 50

10.11.2 Under-Temperature ............................................................................................................. 50

10.12 Microcontroller Read of Voltages ............................................................................................ 52

10.13 Voltage Conversions ............................................................................................................... 53

10.13.1 Cell Voltages ....................................................................................................................... 53

10.13.2 Pack Current ....................................................................................................................... 53

10.13.3 Temperature ........................................................................................................................ 53

10.13.4 14-bit Register .................................................................................................................... 53

11. Microcontroller FET Control ................................................................................ 54

12. Cell Balance ........................................................................................................ 55

12.1

µC Control of Cell Balance FETs ............................................................................................ 57

12.2

Cell Balance FET Drive .......................................................................................................... 57

13. Watchdog Timer .................................................................................................. 59

14. Power FET Drive ................................................................................................ 60

15. General I/Os ....................................................................................................... 61

16. Higher Voltage Microcontrollers .......................................................................... 62

17. Packs with Fewer than Eight Cells ..................................................................... 63

FN8889 Rev.2.00

Mar 8, 2017

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ISL94202

18. PC Board Layout ................................................................................................ 64

18.1

QFN Package ......................................................................................................................... 65

18.2

Circuit Diagrams ..................................................................................................................... 65

19. EEPROM ............................................................................................................ 66

20. Serial Interface .................................................................................................... 67

20.1

20.2

20.3

20.4

20.5

20.6

Serial Interface Conventions ................................................................................................... 67

Clock and Data ....................................................................................................................... 67

Start Condition ........................................................................................................................ 67

Stop Condition ........................................................................................................................ 67

Acknowledge .......................................................................................................................... 68

Write Operations ..................................................................................................................... 69

20.6.1 Byte Write ........................................................................................................................... 69

20.6.2 Page Write .......................................................................................................................... 69

20.7

Read Operations ..................................................................................................................... 70

20.7.1 Current Address Read ........................................................................................................ 70

20.7.2 Random Read ..................................................................................................................... 70

20.7.3 Sequential Read ................................................................................................................. 71

20.7.4 EEPROM Access ................................................................................................................ 72

20.7.5 EEPROM Read ................................................................................................................... 72

20.7.6 EEPROM Write ................................................................................................................... 72

20.8

Synchronizing Microcontroller Operations with Internal Scan ................................................ 72

21. Register Protection ............................................................................................. 73

22. Registers: Summary (EEPROM) ........................................................................ 74

23. Registers: Summary (RAM) ................................................................................ 75

24. Registers: Detailed (EEPROM) ........................................................................... 76

25. Registers: Detailed (RAM) .................................................................................. 82

26. Revision History .................................................................................................. 87

27. Package Outline Drawing ................................................................................... 88

FN8889 Rev.2.00

Mar 8, 2017

Page 10 of 89

ISL94202

3. Specifications

3.1

Absolute Maximum Ratings

(Note 1)

Maximum

(Note 1)

Parameter

Minimum

Unit

Power Supply Voltage, VDD

VSS - 0.5

VSS+ 45.0

V

Cell Voltage (VC, VBATT)

VCn

-0.5

-3.0

-0.5

VBATT + 0.5

45.0

36.0

27.0

17.0

7.0

V

VCn - VSS (n = 8)

VCn - VSS (n = 6, 7)

VCn - VSS (n = 4, 5)

VCn - VSS (n = 2, 3)

VCn - VSS (n = 1)

VCn - VSS (n = 0)

VCn - VC(n-1) (n = 2 to 12)

VC1 - VC0

3.0

7.0

Cell Balance Pin Voltages (VCB)

VCBn - VC(n-1), n = 1 to 5

VCn - VCBn, n = 6 to 8

-0.5

7.0

V

Terminal Voltage

ADDR, xT1, xT2, FETSOFF, PSD, INT

VRGO +0.5

5.5

-0.5

V

SCL, SDAI, SDAO, EOC, SD

CFET, PCFET, C1, C2, C3

DFET, CHMON, LDMON

Terminal Current

VDD - 0.5

-0.5

VDD + 15.5 (60V max)

VDD + 15.0 (60V max)

V

RGO

25

mA

Current-Sense Voltage

VBATT, CS1, CS2

VDD +1.0

-0.5

V

VBATT - CS1, VBATT - CS2

CS1 - CS2

+0.5

V

ESD Rating

Value

Unit

kV

mA

Human Body Model (Tested per JS-001-2014)

Charged Device Model (Tested per JS-002-2014)

Latch-Up (Tested per JESD78E; Class 2, Level A)

Note:

1.5

1

100

1. Devices are characterized, but not production tested, at Absolute Maximum Voltages.

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely

impact product reliability and result in failures not covered by warranty.

FN8889 Rev.2.00

Mar 8, 2017

Page 11 of 89

ISL94202

3. Specifications

3.2

Thermal Information



_JA(°C/W)



_JC(°C/W)

Thermal Resistance (Typical)

48 Ld QFN Package (Notes 2, 3)

Notes:

28

0.75

2. _JAis measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct

attach” features. See Tech Brief TB379.

3. For _JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Parameter

Continuous Package Power Dissipation

Maximum Junction Temperature

Storage Temperature Range

Pb-Free Reflow Profile

Minimum

Maximum

400

Unit

mW

°C

+125

-55

+125

°C

see TB493

3.3

Recommended Operating Conditions

Parameter

Minimum

Maximum

Unit

Temperature Range

Operating Voltage

VDD

-40

+85

°C

4V

2.0

1.0

0.5

36

4.3

4.4

4.8

V

VCn-VC(n-1) Specified Range

VCn-VC(n-1) Extended Range

VCn-VC(n-1) Maximum Range (any cell)

FN8889 Rev.2.00

Mar 8, 2017

Page 12 of 89

ISL94202

3. Specifications

3.4

Electrical Specification

V

= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating

A

DD

temperature range, -40°C to +85°C.

Min

(Note 4)

Max

(Note 4)

Parameter

Symbol

Test Conditions

Typ

Unit

Power-Up Condition – Threshold

Rising

V_DDminimum voltage at which device

operation begins

V_PORR1

6.0

V

(Device becomes operational)

(CFET turns on; CHMON = V_DD

CHMON minimum voltage at which device

V_PORR2operation begins

(CFET turns on; V_DD> 6.0V)

)

V_DD

3.0

V

Power-Down Condition –

Threshold Falling

V_DDminimum voltage device remains

operational (RGO turns off)

I_RGO= 3mA

V_PORF

2.5V Regulated Voltage

1.8V Reference Voltage

VBATT Input Current - V_BATT

V_RGO

V_REF

2.4

2.5

1.8

2.6

V

1.79

1.81

Input current; Normal/Idle/Doze modes

V_DD= 33.6V

38

45

1

µA

I_VBATT

Input current; Sleep/Power-Down modes

V_DD= 33.6V

V

_DDSupply Current

Device active (Normal mode)

(No error conditions)

I_VDD1

310

215

370

275

µA

CFET, PCFET, DFET = OFF; V_DD= 33.6V

Device active (Idle mode)

(No error conditions)

Idle = 1

I_VDD2

CFET, PCFET, DFET = OFF; V_DD= 33.6V

Device active (Doze mode)

(No error conditions)

Doze = 1

I_VDD3

210

215

265

µA

CFET, PCFET, DFET = OFF; V_DD= 33.6V

FET drive current

(I_VDDincrease when FETs are on -

I_VDD4

Normal/Idle/Doze modes); V_DD= 33.6V

Device active (Sleep mode);

Sleep = 1; V_DD= 33.6V

I_VDD5

0°C to +60°C

13

10

30

µA

-40°C to +85°C

50

Power-down

PDWN = 1; V_DD= 33.6V

I_VDD6

1

µA

Input Bias Current

V_DD= V_BATT= VCS1 = VCS2 = 33.6V

15

(Normal, idle, doze)

V_DD= V_BATT= VCS1 = VCS2 = 33.6V

(Sleep, Power-Down)

0°C to +60°C

ICS1

ICS2

1

µA

-40°C to +85°C

3

V_DD= V_BATT= VCS1 = VCS2 = 33.6V

(Normal, Idle, Doze)

10

15

µA

V_DD= V_BATT= VCS1 = VCS2 = 33.6V

(Sleep, Power-Down)

0°C to +60°C

1

µA

-40°C to +85°C

3

VCn Input Current

CBn Input Current

Cell input leakage current

AO2:AO0 = 0000H

(Normal/Idle/Doze; not sampling cells)

I_VCN

-1

1

µA

Cell Balance pin leakage current

(no balance active)

I_CBN

FN8889 Rev.2.00

Mar 8, 2017

Page 13 of 89

ISL94202

3. Specifications

= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating

V

DD

A

temperature range, -40°C to +85°C. (Continued)

Min

(Note 4)

Max

(Note 4)

Parameter

Symbol

Test Conditions

Typ

Unit

Temperature Monitor Specifications

External Temperature Accuracy

External temperature monitoring error.

ADC voltage error when monitoring xT1

input. TGain = 0; (xTn = 0.2V to 0.737V)

V_XT1

-25

15

mV

V

Internal Temperature Monitor

Output

(See “Temperature

[iTB:iT0]₁₀*1.8/4095/GAIN

T_INT25

0.276

1.0

GAIN = 2 (TGain bit = 0)

Temperature = +25°C

Monitoring/Response” on page 49)

Change in

[iTB:iT0]₁₀*1.8/4095/GAIN

V_INTMON

mV/°C

GAIN = 2 (TGain bit = 0)

Temperature = -40°C to +85°C

Cell Voltage Monitor Specifications

Cell Monitor Voltage Accuracy

(Relative)

Relative cell measurement error

(Maximum absolute cell measurement

error -

Minimum absolute cell measurement error)

VCn - VC(n-1) = 2.4V to 4.2V; 0°C to

3

10

15

30

mV

V_ADCR

+60°C

VCn - VC(n-1) = 0.1V to 4.7V; 0°C to

+60°C

VCn - VC(n-1) = 0.1V to 4.7V; -40°C to

+85°C

Cell Monitor Voltage Accuracy

(Absolute)

Absolute cell measurement error

(Cell measurement error compared with

voltage at the cell)

VCn - VC(n-1) = 2.4V to 4.2V; 0°C to

+60°C

-15

-20

-30

15

20

30

mV

V_ADC

VCn - VC(n-1) = 0.1V to 4.7V; 0°C to

+60°C

VCn - VC(n-1) = 0.1V to 4.7V; -40°C to

+85°C

V_BATTVoltage Accuracy

V_BATT- [VBB:VB0]₁₀*32*1.8/4095;

V_BATT

0°C to +60°C

-200

200

mV

-40°C to +85°C

-270

270

Current-Sense Amplifier Specifications

Charge Current Threshold

VCS1-VCS2, CHING indicates charge

VCCTH current

-100

100

μV

VCS1 = 26.4V

Discharge Current Threshold

VCS1-VCS2, DCHING indicates discharge

current; VCS1 = 26.4V

VDCTH

FN8889 Rev.2.00

Mar 8, 2017

Page 14 of 89

ISL94202

3. Specifications

= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating

V

DD

A

temperature range, -40°C to +85°C. (Continued)

Min

(Note 4)

Max

(Note 4)

Parameter

Symbol

Test Conditions

Typ

Unit

Current-Sense Accuracy

V_IA1= ([ISNSB:ISNS0]₁₀*1.8/4095)/5;

VIA1

97

-107

8.0

102

107

-97

mV

CHING bit set; Gain = 5

VCS1 = 26.4V, VCS2 - VCS1 = + 100mV

V

_IA2= ([ISNSB:ISNS0]₁₀*1.8/4095)/5;

VIA2

VIA3

VIA4

-102

10.0

-10.0

mV

DCHING bit set; Gain = 5

VCS1 = 26.4V, VCS2 - VCS1 = - 100mV

V_IA3= ([ISNSB:ISNS0]₁₀*1.8/4095)/50;

12.0

-8.0

CHING bit set; Gain = 50

VCS1 = 26.4V, VCS2 - VCS1 = + 10mV

V

_IA4= ([ISNSB:ISNS0]₁₀*1.8/4095)/50;

-12.0

DCHING bit set; Gain = 50

VCS1 = 26.4V, VCS2 - VCS1 = - 10mV

V

_IA3= ([ISNSB:ISNS0]₁₀*1.8/4095)/500;

CHING bit set; Gain = 500

VCS1 = 26.4V, VCS2 - VCS1 = + 1mV

VIA5

VIA6

0°C to +60°C

0.5

1.0

1.5

mV

-40°C to +85°C

0.4

1.6

V

_IA4= ([ISNSB:ISNS0]₁₀*1.8/4095)/500;

DCHING bit set; Gain = 500

VCS1 = 26.4V, VCS2 - VCS1 = - 1mV

0°C to +60°C

-1.5

-1.0

-0.5

mV

-40°C to +85°C

-1.6

-0.4

Overcurrent/Short-Circuit Protection Specifications

Discharge Overcurrent Detection

Threshold

V_OCD= 4mV [OCD2:0] = 0,0,0

2.6

6.4

4.0

8.0

5.4

9.6

mV

V

_OCD= 8mV [OCD2:0] = 0,0,1

_OCD= 16mV [OCD2:0] = 0,1,0

_OCD= 24mV [OCD2:0] = 0,1,1

_OCD= 32mV [OCD2:0] = 1,0,0 (default)

12.8

20

16.0

25

19.2

30

V_OCD

t_OCDT

V_SCD

t_SCT

26.4

42.5

60.3

90

33.0

50.0

67.0

100

39.6

57.5

73.7

110

V_OCD= 48mV [OCD2:0] = 1,0,1

V

_OCD= 64mV [OCD2:0] = 1,1,0

_OCD= 96mV [OCD2:0] = 1,1,1

Discharge Overcurrent Detection

Time

[OCDTA:OCDT0] = 0A0H (160ms) (default)

Range:

0ms to 1023ms 1ms/step

0s to 1023s; 1s/step

160

ms

Short-Circuit Detection Threshold

V_SCD= 16mV [SCD2:0] = 0,0,0

V_SCD= 24mV [SCD2:0] = 0,0,1

10.4

18

16.0

24

21.6

30

mV

V

_SCD= 32mV [SCD2:0] = 0,1,0

_SCD= 48mV [SCD2:0] = 0,1,1

_SCD= 64mV [SCD2:0] = 1,0,0

_SCD= 96mV [SCD2:0] = 1,0,1 (default)

_SCD= 128mV [SCD2:0] = 1,1,0

_SCD= 256mV [SCD2:0] = 1,1,1

26

33

40

42

49

56

60

67

74

90

100

134

262

110

141

275

127

249

Short-Circuit Current Detection

Time

[SCTA:SCT0] = 0C8H (200µs) (default)

Range:

0µs to 1023µs; 1µs/step

0ms to 1023ms 1ms/step

200

µs

FN8889 Rev.2.00

Mar 8, 2017

Page 15 of 89

ISL94202

3. Specifications

= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating

V

DD

A

temperature range, -40°C to +85°C. (Continued)

Min

(Note 4)

Max

(Note 4)

Parameter

Symbol

Test Conditions

Typ

Unit

Charge Overcurrent Detection

Threshold

V_OCC= 1mV [OCC2:0] = 0,0,0

0.2

0.7

1.0

2.0

2.1

3.3

mV

V

_OCC= 2mV [OCC2:0] = 0,0,1

_OCC= 4mV [OCC2:0] = 0,1,0

_OCC= 6mV [OCC2:0] = 0,1,1

_OCC= 8mV [OCC2:0] = 1,0,0 (default)

2.8

4.0

5.2

4.5

6.0

7.5

V_OCC

6.6

8.0

9.8

V_OCC= 12mV [OCC2:0] = 1,0,1

9.6

12.0

17.0

25.0

14.4

19.6

27.5

V

_OCC= 16mV [OCC2:0] = 1,1,0

_OCC= 24mV [OCC2:0] = 1,1,1

14.5

22.5

Overcurrent Charge Detection

Time

[OCCTA:OCCT0] = 0A0H (160ms) (default)

Range:

0ms to 1023ms 1ms/step

0s to 1023s; 1s per step

t_OCCT

160

8.9

ms

V

Charge Monitor Input Threshold

(Falling Edge)

µCCMON bit = 1; CMON_EN bit = 1

V_CHMON

V_LDMON

8.2

9.8

Load Monitor Input Threshold

(Rising Edge)

µCLMON bit = 1; LMON_EN bit = 1

0.45

0.60

62

0.75

V

Load Monitor Output Current

I_LDMONµCLMON bit = 1; LMON_EN bit = 1

µA

Voltage Protection Specifications

Overvoltage Lockout Threshold

(Rising Edge - Any Cell)

[VCn-VC(n-1)]

[OVLOB:OVLO0] = 0E80H (4.35V)

(default)

Range: 12-bit value (0V to 4.8V)

V_OVLO

V_OVLOR

V_UVLO

V_UVLOR

t_OVLO

4.35

V

Overvoltage Lockout Recovery

Threshold - All Cells

Falling edge

V_OVR

Undervoltage Lockout Threshold

(Falling Edge - Any Cell)

[VCn-VC(n-1)]

[UVLOB:UVLO0] = 0600H (1.8V) (default)

Range: 12-bit value (0V to 4.8V)

1.8

V

Undervoltage Lockout Recovery

Threshold - All Cells

Rising edge

V_UVR

V

Overvoltage Lockout Detection

Time

Normal operating mode

5 consecutive samples over the limit

(minimum = 160ms, maximum = 192ms)

176

4.25

4.15

1

ms

Undervoltage Lockout Detection

Time

Normal operating mode

5 consecutive samples under the limit

(minimum = 160ms, maximum = 192ms)

t_UVLO

ms

V

Overvoltage Threshold

(Rising Edge - Any Cell)

[VCn-VC(n-1)]

[OVLB:OVL0] = 0E2AH (4.25V) (default)

Range: 12-bit value (0V to 4.8V)

V_OV

Overvoltage Recovery Voltage

(Falling Edge - All Cells)

[VCn-VC(n-1)]

[OVRB:OVR0] = 0DD5H (4.15V) (default)

Range: 12-bit value (0V to 4.8V)

V_OVR

V

Overvoltage Detection/Release

Time

[OVTA:OVT0] = 201H (1s) (default) Range:

0ms to 1023ms; 1ms/step

t_OVT

s

0s to 1023s; 1s/step

Undervoltage Threshold

(Falling Edge - Any Cell)

[VCn-VC(n-1)]

[UVLB:UVL0] = 0900H (2.7V) (default)

Range: 12-bit value (0V to 4.8V)

V_UV

2.7

V

Undervoltage Recovery Voltage

(Rising Edge - All Cells)

[VCn-VC(n-1)]

[UVRB:UVR0] = 0A00H (3.0V) (default)

Range: 12-bit value (0V to 4.8V)

V_UVR

3.0

V

Undervoltage Detection Time

[UVTA:UVT0] = 201H (1s) (default)

Range:

0ms to 1023ms; 1ms/step

0s to 1023s; 1s/step

t_UVT

1

s

FN8889 Rev.2.00

Mar 8, 2017

Page 16 of 89

ISL94202

3. Specifications

= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating

V

DD

A

temperature range, -40°C to +85°C. (Continued)

Min

(Note 4)

Max

(Note 4)

Parameter

Symbol

Test Conditions

Typ

Unit

Undervoltage Release Time

[UVTA:UVT0] = 201H (1s) + 3s (default)

Range:

(0ms to 1023ms) + 3s; 1ms/step

(0s to 1023s) + 3s; 1s/step

t_UVTR

3

s

Sleep Voltage Threshold

(Falling Edge - Any Cell)

[VCn-VC(n-1)]

[SLLB:SLL0] = 06AAH (2.0V) (default)

Range: 12-bit value (0V to 4.8V)

V_SLL

2.0

1

V

s

Sleep Detection Time

[SLTA:SLT0] = 201H (1s) (default) Range:

0ms to 1023ms; 1ms/step

t_SLT

0s to 1023s; 1s/step

Low Voltage Charge Threshold

(Falling Edge - Any Cell)

[VCn-VC(n-1)]

[LVCHB:LVCH0] = 07AAH (2.3V) (default)

Range: 12-bit value (0V to 4.8V)

Precharge if any cell is below this voltage

V_LVCH

V_LVCHH

V_EOC

2.3

117

4.2

117

V

mV

V

Low Voltage Charge Threshold

Hysteresis

End-of-Charge Threshold

(Rising Edge - Any Cell)

[VCn-VC(n-1)]

[EOCSB:EOCS0] = 0E00H (4.2V) (default)

Range: 12-bit value (0V to 4.8V)

End-of-Charge Threshold

Hysteresis

V_EOCH

mV

Sleep Mode Timer

[MOD7:MOD0] = 0DH (off)

(default)

Range:

t_SMT

90

31

min

s

0s to 255 minutes

Watchdog Timer

[WDT4:WDT0] = 1FH (31s) (default)

Range: 0s to 31s

t_WDT

Temperature Protection Specifications

Internal Temperature Shutdown

Threshold

[IOTSB:IOTS0] = 02D8H

T_ITSD

115

95

°C

V

Internal Temperature Recovery

T_ITRCV[IOTRB:IOTR0] = 027DH

External Temperature Output

Voltage

Voltage output at TEMPO pin (during

temperature scan); I_TEMPO= 1mA

V_TEMPO

2.30

2.45

2.60

External Temperature Limit

Threshold (Hot) - xT1 or xT2

Charge, Discharge, Cell Balance

(see Figure 3.1)

xTn Hot threshold. Voltage at V_TEMPI,

xT1 or xT2 = 04B6H

TGain = 0

~+55°C; thermistor = 3.535k

Detected by COT, DOT, CBOT bits = 1

T_XTH

0.265

0.295

0.672

0.595

V

External Temperature Recovery

Threshold (Hot) - xT1 or xT2

Charge, Discharge, Cell Balance

(see Figure 3.1)

xTn Hot recovery voltage at V_TEMPI

xT1 or xT2 = 053EH

TGain = 0

(~+50°C; thermistor = 4.161k)

Detected by COT, DOT, CBOT bits = 0

T_XTHR

External Temperature Limit

Threshold (Cold) - xT1 or xT2

Charge, Discharge, Cell Balance

(see Figure 3.1)

xTn Cold threshold. Voltage at V_TEMPI

xT1 or xT2 = 0BF2H

TGain = 0

(~ -10°C; thermistor = 42.5k)

Detected by CUT, DUT, CBUT bits

T_XTC

External Temperature Recovery

Threshold (Cold) - xT1 or xT2

Charge, Discharge, Cell Balance

(see Figure 3.1)

xTn Cold recovery voltage at V_TEMPI. xT1

or xT2 = 0A93H

TGain = 0

(~5°C; thermistor = 22.02k)

Detected by CUT, DUT, CBUT bits

T_XTCH

Cell Balance Specifications

Cell Balance FET Gate Drive

Current

VC1 to VC5 (current out of pin)

VC6 to VC8 (current into pin)

15

25

35

µA

FN8889 Rev.2.00

Mar 8, 2017

Page 17 of 89

ISL94202

3. Specifications

= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating

V

DD

A

temperature range, -40°C to +85°C. (Continued)

Min

(Note 4)

Max

(Note 4)

Parameter

Symbol

Test Conditions

Typ

4.2

Unit

V

Cell Balance Maximum Voltage

Threshold (Rising Edge - Any cell)

[VCMAX]

[CBVUB:CBVU0] = 0E00H (4.2V) (default)

Range: 12-bit value (0V to 4.8V)

V_CBMX

Cell Balance Maximum Threshold

Hysteresis

V_CBMXH

117

3.0

mV

V

Cell Balance Minimum Voltage

Threshold (Falling Edge - Any cell)

[VCMIN]

[CBVLB:CBVL0] = 0A00H (3.0V) (default)

Range: 12-bit value (0V to 4.8V)

V_CBMN

Cell Balance Minimum Threshold

Hysteresis

V_CBMNH

117

mV

Cell Balance Maximum Voltage

Delta Threshold (Rising Edge -

Any Cell)

[CBDUB:CBD0] = 06AAH (2.0V) (default)

Range: 12-bit value (0V to 4.8V)

V_CBDU

2.0

V

[VCn-VC(n-1)]

Cell Balance Maximum Voltage

Delta Threshold Hysteresis

V_CBDUH

117

mV

Wake-Up Specifications

Device CHMON Pin Voltage

Threshold (Wake on Charge)

(Rising Edge)

CHMON pin rising edge

Device wakes up and sets Sleep flag LOW

V_WKUP1

7.0

8.0

9.0

V

Device LDMON Pin Voltage

Threshold (Wake on Load)

(Falling Edge)

LDMON pin falling edge

Device wakes up and sets Sleep flag LOW

V_WKUP2

0.15

0.40

0.70

Open-Wire Specifications

Open-Wire Current

I_OW

1.0

mA

V

Open-Wire Detection Threshold

VCn-VC(n-1); VCn is open. (n = 2, 3, 4, 5,

6, 7, 8). Open-wire detection active on the

VCn input.

V_OW1

-0.3

VC1-VC0; VC1 is open. Open-wire

detection active on the VC1 input.

V_OW2

V_OW3

0.4

V

VC0-VSS; VC0 is open. Open-wire

detection active on the VC0 input.

1.25

FET Control Specifications

DFET Gate Voltage

V_DFET1(ON) 100µA load; V_DD= 36V

V_DFET2(ON) 100µA load; V_DD= 6V

V_DFET3(OFF)

47

8

52

9

57

10

V

0

V

CFET Gate Voltage (ON)

PCFET Gate Voltage (ON)

V_CFET1(ON) 100µA load; V_DD= 36V

V_CFET2(ON) 100µA load; V_DD= 6V

V_CFET3(OFF)

47

8

52

9

57

10

V

V_DD

V

V_PFET1(ON) 100µA load; V_DD= 36V

V_PFET2(ON) 100µA load; V_DD= 6V

V_PFET3(OFF)

47

8

52

9

57

10

V

V_DD

V

FET Turn-Off Current (DFET)

FET Turn-Off Current (CFET)

FET Turn-Off Current (PCFET)

FETSOFF Rising Edge Threshold

I_DF(OFF)

14

9

15

13

16

17

mA

I_CF(OFF)

I_PF(OFF)

9

FETSOFF rising edge threshold. Turn off

FETs

V_FO(IH)

V_FO(IL)

1.8

1.2

V

FETSOFF Falling Edge Threshold

FETSOFF falling edge threshold. Turn on

FETs

Serial Interface Characteristics (Note 5)

Input Buffer Low Voltage (SCL,

V

Voltage relative to V_SSof the device

V_RGOx 0.3

-0.3

V

IL

SDA)

Input Buffer High Voltage (SCL,

SDAI, SDAO)

V

V_RGOx 0.7

V

_RGO+ 0.1

IH

FN8889 Rev.2.00

Mar 8, 2017

Page 18 of 89

ISL94202

3. Specifications

= 26.4V, T = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating

V

DD

A

temperature range, -40°C to +85°C. (Continued)

Min

(Note 4)

Max

(Note 4)

Parameter

Symbol

Test Conditions

Typ

Unit

V

Output Buffer Low Voltage (SDA)

V_OL

I_OL= 1mA

0.4

SDA and SCL Input Buffer

Hysteresis

Sleep bit = 0

I²CHYST

f_SCL

0.05 x V_RGO

V

SCL Clock Frequency

400

50

kHz

ns

Pulse Width Suppression Time at

SDA and SCL Inputs

Any pulse narrower than the maximum

spec is suppressed.

t_IN

SCL Falling Edge to SDA Output

Data Valid

From SCL falling crossing V_IH(minimum),

until SDA exits the V_IL(maximum) to V_IH

(minimum) window

t_AA

0.9

µs

Time the Bus Must Be Free Before

Start of New Transmission

SDA crossing V_IH(minimum) during a

STOP condition to SDA crossing V_IH

t_BUF

1.3

(minimum) during the following START

condition

Clock Low Time

t_LOW

t_HIGH

Measured at the V_IL(maximum) crossing

Measured at the V_IH(minimum) crossing

1.3

0.6

µs

Clock High Time

Start Condition Set-Up Time

SCL rising edge to SDA falling edge, both

crossing the V_IH(minimum) level

t_SU:STA

0.6

µs

Start Condition Hold Time

Input Data Set-Up Time

Input Data Hold Time

From SDA falling edge crossing

V_IL(maximum) to SCL falling edge

t_HD:STA

0.6

µs

crossing V_IH(minimum)

From SDA exiting the V_IL(maximum) to V_IH

t_SU:DAT

(minimum) window to SCL rising edge

crossing V_IL(minimum)

100

0

ns

µs

From SCL falling edge crossing

V_IH(minimum) to SDA entering the

t_HD:DAT

0.9

V

_IL(maximum) to V_IH(minimum) window

Stop Condition Set-Up Time

From SCL rising edge crossing V_IH

(minimum) to SDA rising edge crossing V_IL

(maximum)

t_SU:STO

t_HD:STO

t_DH

0.6

0

µs

ns

Stop Condition Hold Time

Data Output Hold Time

From SDA rising edge to SCL falling edge.

Both crossing V_IH(minimum)

From SCL falling edge crossing V_IL

(maximum) until SDA enters the V_IL

(maximum) to V_IH(minimum) window

SDA and SCL Rise Time

SDA and SCL Fall Time

t_R

t_F

From V_IL(maximum) to V_IH(minimum)

From V_IH(minimum) to V_IL(maximum)

300

ns

SDA and SCL Bus Pull-Up

Resistor Off-Chip

Maximum is determined by t_Rand t_F

R_OUT

For C_B= 400pF, maximum is 2kΩ ~ 2.5kΩ

For C_B= 40pF, maximum is 15kΩ~ 20kΩ

1

kΩ

Input Leakage (SCL, SDA)

EEPROM Write Cycle Time

Notes:

I_LI

-10

10

µA

ms

t_WR

+25°C

30

4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Device MIN and/or MAX

values are based on temperature limits established by characterization and are not production tested.

5. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.

FN8889 Rev.2.00

Mar 8, 2017

Page 19 of 89

ISL94202

3. Specifications

3.5

Symbol Table

WAVEFORM

INPUTS

OUTPUTS

WAVEFORM

INPUTS

OUTPUTS

DON’T CARE:

CHANGES

ALLOWED

CHANGING:

STATE NOT

KNOWN

MUST BE

STEADY

WILL BE

STEADY

N/A

CENTER LINE

IS HIGH

IMPEDANCE

MAY CHANGE

FROM LOW

TO HIGH

WILL CHANGE

FROM LOW

TO HIGH

MAY CHANGE

FROM HIGH

TO LOW

WILL CHANGE

FROM HIGH

TO LOW

3.6

Timing Diagrams

3.6.1

External Temperature Configuration

TEMPO PIN

22kΩ

xT1 PIN

xT2 PIN

DIGITAL TEMPERATURE VOLTAGE READING =

xTn * 2 (TGAIN BIT = 0)

xTn * 1 (TGAIN BIT = 1)

10kΩ

THERMISTORS: 10k, Murata XH103F

Figure 3.1

External Temperature Configuration

FN8889 Rev.2.00

Mar 8, 2017

Page 20 of 89

ISL94202

3. Specifications

3.6.2

Wake-Up Timing

ENTERS SLEEP MODE

LDMON PIN

V

WKUP2

<1µs

CAN STAY IN

SLEEP MODE

CAN STAY IN

SLEEP MODE

IN_SLEEP BIT

V

WKUP1

<1µs

CHMON PIN

~50ms

CAN STAY IN

SLEEP MODE

CAN STAY IN

SLEEP MODE

IN_SLEEP BIT

~140ms

DFET/CFET

If LDMON or CHMON is “active” when entering

Sleep mode, the IC wakes up after a short delay.

Figure 3.2

Wake-Up Timing (from Sleep)

3.6.3

Power-Up Timing

VWKUP1

CHMON PIN

~3s

256ms

LDMON CHECK

DFET/CFET

TURN ON FETs IF NO PACK FAULTS

RGO

~4ms

I C COMMUNICATION

2

Figure 3.3

Power-Up Timing (from Power-Up/Shutdown)

FN8889 Rev.2.00

Mar 8, 2017

Page 21 of 89

ISL94202

3. Specifications

3.6.4

Change in FET Control

SCL

SDA

BIT

3

BIT

2

BIT

1

BIT

0

BIT

1

BIT

0

ACK

~1µs

DATA

~1µs (~500µs IF BOTH FETs OFF)

t

FTOFF

FTON

90%

DFET/CFET TURN ON

10%

2

Figure 3.4

I C FET Control Timing

V

FO(OFF)

V

FETSOFF PIN

FO(ON)

~500µs

~1µs

DFET/CFET

TURN ON

FET

CHARGE PUMP

Figure 3.5

FETSOFF FET Control Timing

FN8889 Rev.2.00

Mar 8, 2017

Page 22 of 89

ISL94202

3. Specifications

3.6.5

Automatic Temperature Scan

128ms

1024ms

2048ms

MONITOR

TIME = 120µs

2.5V

TEMPO PIN

EXTERNAL

TEMPERATURE

OVER-TEMPERATURE

THRESHOLD

UNDER-TEMP

OVER-TEMP

xTn

DELAY TIME = 20µs

MONITOR TEMPERATURE DURING THIS

TIME PERIOD

CBOT, DOT, COT BITs

FET SHUTDOWN OR

CELL BALANCE TURN

OFF (IF ENABLED)

SEE Figure 3.1 FOR TEST CIRCUIT

Figure 3.6

Automatic Temperature Scan

3.6.6

Serial Interface Timing Diagrams

t

R

HIGH

LOW

t

F

SCL

t

SU:STA

t

SU:DAT

HD:DAT

SU:STO

t

HD:STA

SDA

(INPUT

TIMING)

t

BUF

t

AA

DH

SDA

(OUTPUT

TIMING)

Figure 3.7

Serial Interface Bus Timing

FN8889 Rev.2.00

Mar 8, 2017

Page 23 of 89

ISL94202

3. Specifications

3.6.7

Discharge Overcurrent/Short-Circuit Monitor

LOAD RELEASES DURING THIS TIME

256ms

V

LDMON

3s

LDMON PIN

DETECTS 2 LDMON PULSES ABOVE THRESHOLD

V

SC

V

OCD

V

DSENSE

t

SCD

OCD

‘1’

‘0’

DOC BIT

DSC BIT

‘1’

2.5V

µC REGISTER 1 READ

SD

OUTPUT

µC REGISTER 1 READ

µC IS OPTIONAL

LDMON DETECTS

LOAD RELEASE

RESETS DOC, SCD BIT,

TURNS ON FET

LDMON DETECTS LOAD RELEASE

RESETS DOC, SCD BIT, TURNS ON FET

V

+15V

DD

DFET

OUTPUT

ISL94202 TURNS ON DFET

(µCFET BIT = 0)

Figure 3.8

Discharge/Short-Circuit Monitor

3.6.8

Charge Overcurrent Monitor

(Assumes NO_OCCR bit is ‘0’)

CHARGER RELEASES

V

CHMON

DETECTS 2 CHMON PULSES BELOW THRESHOLD

CHMON PIN

V

CSENSE

V

OCC

t

OCC

‘1’

‘0’

COC BIT

SD

2.5V

OUTPUT

CHMON DETECTS CHARGER RELEASE

RESETS DOC, SCD BIT, TURNS ON FET

REGISTER 1 READ

V

+15V

DD

CFET

OUTPUT

ISL94202 TURNS ON CFET

(µCFET BIT = 0)

Figure 3.9

Charge Overcurrent Monitor

FN8889 Rev.2.00

Mar 8, 2017

Page 24 of 89

ISL94202

4. Functional Description

This IC is intended to be a stand-alone battery pack monitor, so it provides monitor and protection functions without requiring

an external microcontroller.

The part operates power control FETs on the high side with a built-in charge pump for driving N-channel FETs. The

current-sense function is also on the high side.

To extend battery life, power is minimized in all areas with parts of the circuit powered down a majority of the time. The RGO

output stays on so that any connected microcontroller can remain on most of the time.

The ISL94202 includes:

• Input level shifter to enable monitoring of battery stack voltages

• 14-bit ADC converter, with voltage readings trimmed and saved as 12-bit results

• 1.8V voltage reference (0.8% accurate)

• 2.5V regulator, with the voltage maintained during sleep

• Automatic scan of the cell voltages; overvoltage, undervoltage, and sleep voltage monitoring

• Selectable overcurrent detection settings

• Eight discharge overcurrent thresholds

• Eight charge overcurrent thresholds

• Eight short-circuit thresholds

• 12-bit programmable discharge overcurrent delay time

• 12-bit programmable charge overcurrent delay time

• 12-bit programmable short-circuit delay time

• Current-sense monitor with gain that provides the ability to read the current-sense voltage

• Second external temperature sensor for use in monitoring the pack or power FET temperatures

• EEPROM for storing operating parameters and a user area for general purpose pack information

FN8889 Rev.2.00

Mar 8, 2017

Page 25 of 89

ISL94202

5. Battery Connections

5.1

Power Path

Figure 5.1 shows the main power path connections for a single charge/discharge path.

These figures show Schottky diodes on the VDD pin. These are to maintain the voltage on the VDD pin during high current

conditions or when the Charge FET is OFF. These are not needed if V can be maintained within 0.5V of V

.

BATT

DD

The CHMON pin connects to the pack pin that receives the charge and the LDMON pin connects to the pack pin that drives

the load. For the single path application, these pins can tie together.

N-CHANNEL FETs

CHG+

DISCHG+

PACK+

CS1

CS2

100Ω

1kΩ

VBATT

470nF

47nF

VC8

VC7

47nF

Figure 5.1

Single Path FET Drive/Power Supply Detail

FN8889 Rev.2.00

Mar 8, 2017

Page 26 of 89

ISL94202

5. Battery Connections

5.2

Pack Configuration

A register in EEPROM (CELLS) identifies the number of cells that are supposed to be present, so the ISL94202 only scans

these cells. This register is also used for the cell balance operation. The register contents are a 1:1 representation of the cells

connected to the pack. For example, in a 6-cell pack, the value in CELLS is ‘11100111’ (CFH), which indicates that Cells 1,

2, 3, 6, 7, and 8 are connected. Also see Figure 5.2.

5.3

Battery Cell Connections

Suggested connections for pack configurations varying from three cells to eight cells are shown in Figure 5.2.

8 CELLS

VC8

7 CELLS

VC8

6 CELLS

VC8

CB8

VC7

CB7

VC6

CB6

VC5

CB5

VC4

CB8

VC7

CB7

VC6

CB6

VC5

CB5

VC4

CB8

VC7

CB7

VC6

CB6

VC5

CB5

VC4

CB4

VC3

CB4

VC3

CB4

VC3

CB3

VC2

CB2

VC1

CB1

CB3

VC2

CB2

VC1

CB1

CB3

VC2

CB2

VC1

CB1

VC0

VSS

VC0

VSS

VC0

VSS

5 CELLS

VC8

4 CELLS

VC8

3 CELLS

VC8

CB8

VC7

CB7

VC6

CB8

VC7

CB7

VC6

CB8

VC7

CB7

VC6

CB6

VC5

CB5

VC4

CB6

VC5

CB5

VC4

CB6

VC5

CB5

VC4

CB4

VC3

CB4

VC3

CB4

VC3

CB3

VC2

CB2

VC1

CB1

CB3

VC2

CB2

VC1

CB1

CB3

VC2

CB2

VC1

CB1

VC0

VSS

VC0

VSS

VC0

VSS

NOTE: MULTIPLE CELLS CAN BE CONNECTED IN PARALLEL

Figure 5.2

Battery Connection Options

FN8889 Rev.2.00

Mar 8, 2017

Page 27 of 89

ISL94202

6. Operating Modes

6.1

Power-Up Operation

When the ISL94202 first connects to the battery pack, it is unknown which pins connect first or in what order. When the

VDD and VSS pins connect, the device enters the power-down state. It remains in this state until a charger is connected.

The device will also power up if the CHMON pin is connected to the VDD pin through an outside resistor to simplify the

PCB manufacture. It is possible that the pack powers up automatically when the battery stack is connected due to

momentary conduction through the power FET G-S and G-D capacitors.

Once the charger connects (or CHMON connects), the internal power supply turns on. This powers up all internal supplies

and starts the state machine. If some cells are not connected, the state machine recognizes this, either through the open-wire

test (see “Typical Operating Conditions” on page 32) or because the monitored cell voltage reads zero when the “CELLS”

register indicates that there should be a voltage at that pin. If the cell voltages do not read correctly, then the ISL94202

remains in the POR loop until conditions are valid for power-up. (It is for this reason that the factory default for the device

is three cells. When manufacturing the application board, Cells 1, 2, and 8 must be connected to power up. If other cells are

connected it is OK, but for the other cells to be monitored, the CELLS register needs to be changed.)

If the inputs all read “good” during this sequence, then the state machine enters the normal monitor state. In the normal

state, if all cell voltages read “good” and there are no overcurrent or temperature issues and there is no load, the FETs turn

on. To determine if there is a load, the device does a load check. This operation waits for about three seconds and then must

see no load for two successive load monitor cycles (256ms apart).

During the POR operation, the RAM registers are all reset to default conditions from values saved in the EEPROM.

When the cell voltages drop, the ISL94202 remains on if the V voltage remains above 1V and the VRGO voltage is

DD

above 2.25V. This is to maintain operation of the device in the event of a short drop in cell voltage due to a pack short-

circuit condition. In the event of a longer battery stack voltage drop, the device will return to a power-down condition if

V

drops below a POR threshold of about 3.5V when V

is below 2.25V (see Figures 6.14 and 6.15).

DD

RGO

•

DO A VOLTAGE SCAN.

POWER-DOWN

STATE

ONLY LOOK AT CELLS THAT ARE

SPECIFIED IN THE “CELL” REG.

•

IF ALL CELL VOLTAGES AND TEMPS

ARE OK, DO A LOAD TEST.

CHARGER CONNECT

BATTERY STACK CONNECT

AND V > V

IF THERE ARE ANY ERRORS, KEEP

SCANNING VOLTAGES,

DD

POR

TEMPERATURES, AND LOAD AT

NORMAL SCAN RATES.

POWER ON RESET

V

< 1.2V

RGO

FETs OFF, NO CURRENT SCAN.

SCAN ONLY VOLTAGES, TEMP, LOAD

OR

(ANY CELL < V

FOR 160ms AND

UVLO

UVLOPD = 1)

OR

ALL VOLTAGES OK

TEMP OK

PDWN BIT SET

NO LOAD

NORMAL OPERATING

MODE

Figure 6.14

Power-On Reset State Machine

FN8889 Rev.2.00

Mar 8, 2017

Page 28 of 89

ISL94202

6. Operating Modes

WHILE RGO IS ABOVE 2.25V, V DROPPING BELOW

DD

POR DOES NOT CAUSE A POWER-DOWN

6V

POR ~3.5V

POR SCAN

UVR

UV

VDD

LAST CELL CONNECTED

POR

(RESET

REGISTERS)

POWERED STATE

2.25V

RGO

3s

DFET

CHMON

LDMON

Figure 6.15

Power-Up/Power-Down Low Voltage Waveforms

6.2

Wake-Up Circuit

When in Sleep mode, the wake-up circuit detects that the output pin is pulled low (as might be the case when a load is

attached to the pack and the FETs are off) or pulled high (as might be the case when the charger is connected and the FETs

are off).

The wake-up circuit does not draw significant continuous current from the battery.

FN8889 Rev.2.00

Mar 8, 2017

Page 29 of 89

ISL94202

6. Operating Modes

6.3

Low Power States

In order to minimize power consumption, most circuits are kept off when not being used and items are sampled when

possible.

There are five power states in the device (see Figure 6.16).

6.3.1

Normal mode

This is the normal monitoring/scan mode. In this mode, the device monitors the current continuously and scans the

voltages every 32ms. If balancing is called for, then the device activates external balancing components. All necessary

circuits are on and unnecessary circuits are off.

During the scan, the ISL94202 draws more current as it activates the input level shifter, the ADC, and data processing.

Between scans, circuits turn off to minimize power consumption.

6.3.2

Idle mode

If there is no current flowing for 0 to 15 minutes (set in the MOD register), then the device enters the Idle mode. In this

mode, voltage scanning slows to every 256ms per scan. The FETs and the LDO remain on. In this mode, the device

consumes less current, because there is more time between scans.

When the ISL94202 detects any charge or discharge current, the device exits the Idle mode and returns to the Normal

mode of operation.

The device does not automatically enter the Idle mode if the µCSCAN bit is set to “1”, because the microcontroller is in

charge of performing the scan and controlling the operation.

Setting the Idle bit to “1” forces the device to enter Idle mode, regardless of current flow. When a µC sets the Idle bit, the

device remains in Idle, regardless of the timer or the current. Setting the mode control bits to “0” allows the device to

control the mode.

6.3.3

Doze Mode

While in Idle mode, if there is no current flowing for another 0 to 16 minutes (same value as the idle timer), the device

enters the Doze mode, where cell voltage sampling occurs every 512ms. The FETs and the LDO remain on. In this

mode, the device consumes less current than in Idle mode, because there is more time between scans.

When the ISL94202 detects any charge or discharge current, the device exits Doze mode and returns to the Normal

mode.

The device does not automatically enter the Idle mode if the µCSCAN bit is set to “1”, because the microcontroller is in

charge of performing the scan and controlling the operation.

Setting the Doze bit forces the device to enter the Doze mode, regardless of the current flow. When a microcontroller

sets the Doze bit, the device remains in Doze mode regardless of the timer or the current. Setting the mode control bits to

“0” allows the device to control the mode.

Note: Setting the Idle/Doze timer to 0 immediately forces the device into the Doze mode when there is no current.

6.3.4

Sleep Mode

The ISL94202 enters the Sleep mode when the voltage on the cells drops below the sleep voltage threshold for a period

of time, specified by the sleep delay timer. To prevent the device from entering the Sleep mode by a low voltage on the

cells, the Sleep Voltage Level (SLL) register can be set to “0”.

The device can also enter the Sleep mode from the Doze mode if there has been no detected current for more than the

duration of the Sleep mode timer (set in the MOD register). In this case, the device remains in Doze mode until there has

been no current for 0 to 240 minutes (with 16 minute steps).

The external microcontroller forces the ISL94202 to enter Sleep mode by writing to the Sleep bit (Register 88H). Setting

the Sleep bit forces the Sleep mode, regardless of the current flow.

FN8889 Rev.2.00

Mar 8, 2017

Page 30 of 89

ISL94202

6. Operating Modes

Note: If both Idle/Doze and Sleep timers are set to “0”, the device immediately goes to sleep. To recover from this

condition, apply current to the device or hold the LDMON pin low (or CHMON pin high) and write non-zero values to

the registers.

While in the Sleep mode, everything is off except for the 2.5V regulator and the wake up circuits. The device can be

waken by LDMON connection to a load or CHMON connection to a charger.

6.3.5

Power-Down Mode

This mode occurs when the voltage on the pack is too low for proper operation. This occurs when:

• V is less than the POR threshold and RGO < 2.25V. This condition occurs if cells discharge over a long period of

DD

time.

• V is less than 1V and RGO > 2.25V. This condition can occur during a short-circuit with minimum capacity cells.

DD

The V drops out, but the RGO cap maintains the logic supply.

DD

• Any cell voltage is less than the UVLO threshold for more than about 160ms (and UVLOPD = 1).

• Commanded by an external µC.

Recovering out of any low power state brings the ISL94202 into the Normal operating mode.

6.3.6

Exceptions

There is one exception to the normal sequence of mode management. When the microcontroller sets the µCSCAN bit,

the internal scan stops. This means that the device no longer looks for the conditions required for sleep. The external

microcontroller needs to manage the modes of operation.

{ANY CELL VOLTAGE LESS THAN UVLO

FOR 160ms AND UVLOPD = 1} OR

RGO < 1.2V OR

POWER-DOWN STATE

POWER CONSUMPTION <1µA

PDWN BIT SET TO “1”

FIRST POWER UP: VOLTAGE ON VDD RISES ABOVE

THE POR THRESHOLD.

ALREADY POWERED: A CHARGER WAKE UP SIGNAL.

NORMAL OPERATING

STATE

POWER CONSUMPTION AVERAGE

450µA (2mA PEAKS)

WAKE UP SIGNAL (EITHER

CHARGER OR LOAD)

NO CHARGE OR DISCHARGE CURRENT DETECTED FOR

0 TO 15 MIN FROM NORMAL STATE OR IDLE BIT IS SET

ANY CELL VOLTAGE

DROPS BELOW SLEEP

THRESHOLD FOR

IDLE STATE

DOZE STATE

SLEEP STATE

POWER CONSUMPTION AVERAGE

350µA MAX (2mA PEAKS)

SLEEP DELAY TIME

NO CHARGE OR DISCHARGE CURRENT DETECTED FOR

0 TO 15 MIN FROM IDLE STATE OR DOZE BIT IS SET

OR SLEEP BIT

IS SET

WHEN THE DEVICE

DETECTS ANY CHARGE

POWER CONSUMPTION AVERAGE

300µA (2mA PEAKS)

OR DISCHARGE CURRENT,

OPERATION MOVES FROM

DOZE OR IDLE STATES BACK TO

THE NORMAL OPERATING STATE

NO CHARGE OR DISCHARGE CURRENT DETECTED FOR

0 TO 240 MIN FROM DOZE STATE OR SLEEP BIT IS SET

POWER CONSUMPTION AVERAGE

15µA

Figure 6.16

ISL94202 Power States

FN8889 Rev.2.00

Mar 8, 2017

Page 31 of 89

ISL94202

7. Typical Operating Conditions

Table 7.2 shows some typical device operating parameters.

Table 7.2

Typical Operating Conditions

Function

Typical

Unit

Bits

µs

ADC Resolution

14

12

ADC Results Saved (and calibrated)

ADC Conversion Time

10

Overcurrent/Short-Circuit Scan Time

Voltage Scan Time (Time per Cell) Includes Settling Time

Continuous

125

µs

Voltage Protection Scan Rate

(Time between scans) Normal Mode;

Idle Mode

32

256

512

ms

Doze Mode

Internal Over-temperature Turn-on/Turn-off Delay Time

External Temperature Autoscan On Time; TEMPO = 2.5V

128

0.2

ms

External Temperature Autoscan Off Time; TEMPO = 0V Normal Mode

Idle Mode

Doze Mode

128

1024

2048

ms

Wake-Up Delay from Sleep. Time to Turn On Power FETs Following Load or Charger Connection. All Pack

Conditions OK.

140

3

ms

Wake-Up Delay from Shutdown or Initial Power-Up. Time to Turn On Power FETs Following Charger

Connection. All Pack Conditions OK.

sec

Default Idle/Doze Mode Delay Times

Default Sleep Mode Delay Time

10

90

min

FN8889 Rev.2.00

Mar 8, 2017

Page 32 of 89

ISL94202

8. Cell Fail Detection

The Cell Fail (CELLF) condition indicates that the difference between the highest voltage cell and the lowest voltage cell

exceeds a programmed threshold (as specified in the CBDU register). Once detected, the CELLF condition turns off the cell

balance FETs and the power FETs, but only if the µCFET bit = “0.” Setting the µCFET bit = 1 prevents the power FETs from

turning off during a CELLF condition. The microcontroller is then responsible for the power FET control.

An EEPROM bit, CFPSD, when set to “1”, enables the PSD activation when the ISL94202 detects a Cell Fail condition. When

CELLF = 1 and CFPSD = 1, the power FETs and cell balance FETs turn off, PLUS the PSD output goes active. The pack

designer can use the PSD pin output to deactivate the pack by blowing a fuse.

The CELLF function can be disabled by setting the CBDU value to FFFH. In this case, the voltage differential can never

exceed the limit. However, disabling the cell fail condition also disables the open-wire detection (see “Open-Wire Detection”

on page 34).

FN8889 Rev.2.00

Mar 8, 2017

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ISL94202

9. Open-Wire Detection

The ISL94202 device has a special, open-battery wire detection function that prevents the cells from being excessively charged

or discharged by turning off the power FETs if there is an open wire. Additionally, the open-wire detection function prevents

the operation of cell balancing when there is an open wire. Cell balancing with an open wire should be avoided for two reasons.

First, an open wire compromises cell balancing. Second, excessive voltage may appear on the ISL94202 VCn input pins if the

cell balance turns on the external balancing FET when there is an open wire. Internal clamps and input series resistors prevent

damage as a result of short term exposure to higher input voltages.

The open-wire feature uses built in circuits to force short pulses of current into or out of the input capacitors (see Figure 9.17).

When there is no open wire, the battery cell itself changes little in response to the open-wire test.

The open-wire operation is disabled by setting a control bit (DOWD) to “1”. When enabled (DOWD = 0), the ISL94202

performs an open-wire test when the CELLF condition exists and then once every 32 voltage scans as long as the CELLF

condition remains. A CELLF condition is the first indication that there might be an open wire.

In operation, the open-wire circuit pulls (or pushes) 1mA of current sequentially on each VCn input for a period of time. The

open-wire on-time is programmable by a value in the OWT register. The pulse duration is programmable between 1µs and

512ms. The default values for current and time are 1mA current and 1ms duration. Note that, in the absence of a battery cell,

1mA input current, along with an external capacitor of 4.7nF, changes the voltage of the input to the open-wire threshold of

-1.4V (relative to the adjacent cell) within 30µs. With the cell present, the voltage will have a negligible change.

Each input has a comparator that detects if the voltage on an input drops more than 1.4V below the voltage of the cell below.

Exceptions are VC1 and VC0. For VC1, the circuit looks to see if the voltage drops below 1V. For VC0, the circuit looks to see

if the voltage exceeds 1.4V. If any comparator trips, then the device sets an OPEN error flag indicating an open-wire failure and

disables cell balancing. See Figure 9.18 on page 35 for sample timing.

VCn

CELL n

INTERNAL

2.5V SUPPLY

NOTE: THE OPEN-WIRE TEST IS

RUN ONLY IF THE DEVICE DETECTS

THE CELLF CONDITION AND THEN

ONCE EVERY 32 VOLTAGE SCANS

WHILE A CELLF CONDITION

EXISTS. EACH CURRENT SOURCE

IS TURNED ON SEQUENTIALLY.

VC4

VC3

VC2

CELL 4

CELL 3

CELL 2

CELL 1

VC1

VC0

Figure 9.17

Open-Wire Detection

FN8889 Rev.2.00

Mar 8, 2017

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ISL94202

9. Open-Wire Detection

PACK VC5 OPEN WIRE

PACK OPEN WIRE CLEARED

PACK CELL IMBALANCE

CELLF THRESHOLD

VC

-

MAX

CBAL FETs TURN OFF

MIN

CELLF BIT

1s (Note 4)

NO OPEN-WIRE SCANS

~160ms (DEFAULT)

OPEN-WIRE SCAN

t

OW

~1ms

VC8 OW TEST

VC7 OW TEST

VC6 OW TEST

VC5 OW TEST

VC4 OW TEST

VC3 OW TEST

VC2 OW TEST

VC1 OW TEST

DEFAULT = 20ms

VC6

VC5

VC4

1V

32ms

(Note 1)

~1.7V

(Note 5)

(Note 2)

VOLTAGE SCAN

OPEN BIT

VOLTAGE SCAN REPORTS THAT

VC5 = 0V AND VC6 = 4.8V

Notes:

1. Voltage drop = 1mA * 1kΩ = 1V.

2. Voltage = V_Fof CB5 Balance FET body diode + (1mA * 1kΩ).

3. OWPSD bit = 0.

4. This time is 8s in Idle and 16s in Doze.

5. This 32ms scan rate increases to 256ms in Idle and 512ms in Doze.

Figure 9.18

Open-Wire Test Timing

With the open-wire setting of 1mA, input resistors of 1kΩ create a voltage drop of 1V. This voltage drop, combined with the

body diode clamp of the cell balance FET, provides the -1.4V needed to detect an open wire. For this reason and for the

increased protection, it is not recommended that smaller input series resistors be used. For example, with a 100Ω input resistor,

the voltage across the input resistor drops only 0.1V. This will not allow the input open-wire detection hardware to trigger

(although the digital detection of an open wire still works, the hardware detection automatically turns off the open-wire

current).

Input resistors larger than 1kΩ may be desired to increase the input filtering. This is allowed in the open-wire test, by providing

an increase in the detection time (by changing the OWT value.) However, increasing the input resistors can significantly affect

measurement accuracy. The ISL94202 has up to 2µA variation in the input measurement current. This amounts to about 2mV

measurement error with 1k resistors (this error has been factory calibrated out). However, 10kΩ resistors can result in up to

20mV measurement errors. To increase the input filtering, the preferred method is to increase the size of the capacitors.

Depending on the selection of the input filter components, the internal open-wire comparators may not detect an open-wire

condition. This might happen if the input resistor is small. In this case, the body diode of the cell balance FET may clamp the

input before it reaches the open-wire detection threshold. To overcome this limitation and provide a redundant open-wire

detection, at the end of the open-wire scan, all input voltages are converted to digital values. If any digital value equals 0V

(minimum) or 4.8V (maximum), the device sets an OPEN error flag indicating an open-wire failure.

When an open-wire condition occurs and the “Open-Wire Power Shutdown” (OWPSD) bit is equal to “0”, the ISL94202 turns

off all power FETs and the cell balance FETs, but does not set the PSD output. While in this condition, the device continues to

operate normally in all other ways (i.e., the cells are scanned and the current monitored. As time passes, the device drops into

lower power modes).

FN8889 Rev.2.00

Mar 8, 2017

Page 35 of 89

ISL94202

9. Open-Wire Detection

When an open-wire condition occurs and OWPSD = 1, the OPEN flag is set, the ISL94202 turns off all power FETs, and the

cell balance FETs and the ISL94202 sets the PSD output port active.

The device can automatically recover from an open-wire condition, because the open-wire test is still functional, unless the

OWPSD bit equals 1 and the PSD pin blows a fuse in the pack. If the open-wire test finds that the open wire has been cleared,

then OPEN bit is reset and other tests determine whether conditions allow the power FETs to turn back on.

The open-wire test hardware has two limitations. First, it depends on the CELLF indicator. If the Cell Balance Maximum

Voltage Delta (CBDU) value is set to high (FFFh for example), then the device may never detect a CELLF condition. The

second limitation is that the open-wire test does not happen immediately. First, a scan must detect a CELLF condition. CELLF

detection happens in a maximum of 32ms (Normal mode) or in a maximum of 256ms (Doze mode). Once CELLF is detected,

the open-wire test occurs on the next scan, 32ms to 256ms later.

FN8889 Rev.2.00

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ISL94202

10. Current and Voltage Monitoring

There are two main automatic processes in the ISL94202. The first are the current monitor and overcurrent shutdown circuits.

The second are the voltage, temperature, and current analog-to-digital scan circuits.

10.1 Current Monitor

The current monitor is an analog detection circuit that tracks the charge and discharge current and current direction. The

current monitor circuit is on all the time, except in Sleep and Power-Down modes.

The current monitor compares the voltage across the sense resistor to several different thresholds. These are short-circuit

(discharge), overcurrent (discharge), and overcurrent (charge). If the measured voltage exceeds the specified limit, for a

specified duration of time, the ISL94202 acts to protect the system, as described in the following section.

The current monitor also tracks the direction of the current. This is a low-level detection and indicates the presence of a

charge or discharge current. If either condition is detected, the ISL94202 sets an appropriate flag.

10.2 Current Sense

The current-sense element is on the high-side of the battery pack.

The current-sense circuit has a gain x5, x50, or x500. The sense amplifier allows a very wide range of currents to be

monitored. The gain settings allow a sense resistor in the range of 0.3mΩ to 5mΩ. A diagram of the current-sense circuit is

shown in Figure 10.19.

There are two parts of the current-sense circuit. The first part is a digital current monitor circuit. This circuit allows the

current to be tracked by an external microcontroller or computer. The current-sense amplifier gain in this current

measurement is set by the [CG1:CG0] bits. The 14-bit offset adjusted ADC result of the conversion of the voltage across the

current-sense resistor is saved to RAM, as well as a 12-bit value that is used for threshold comparisons. The offset

adjustment is based on a “factory calibration” value saved in EEPROM.

The digital readouts cover the input voltage ranges shown in Table 10.3.

Table 10.3

Maximum Current Measurement Range

Voltage Range

Current Range

(RSENSE = 1mΩ)

Gain Setting

5x

(mV)

-250 to 250

-25 to 25

-2.5 to 2.5

-250A to 250A

-25A to 25A

50x

500x

-2.5A to 2.5A

FN8889 Rev.2.00

Mar 8, 2017

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ISL94202

10. Current and Voltage Monitoring

R

SENSE

CS2

CS1

500Ω

5kΩ

50kΩ

+

-

AO2:0 = 9H

CHARGE

OVERCURRENT

DETECT

PROGRAMMABLE

DETECTION TIME

COC

VOLTAGE SCAN

NOTE:

AGC SETS GAIN DURING

250kΩ

[OCCTB:OCC0]

OVERCURRENT MONITORING.

CG BITS SELECT GAIN WHEN ADC

MEASURES CURRENT.

GAIN SELECT

PROGRAMMABLE

THRESHOLDS

[OCC2:OCC0]

CG1:0

DISCHARGE

OVERCURRENT

DETECT

PROGRAMMABLE

DETECTION TIME

DOC

14-BIT ADC OUTPUT

14-BIT

AGC

RAM REGISTER

VALUE

[OCDTB:OCDT0]

[OCD2:OCD0]

ADDRESS: [ABh:AAh]

PROGRAMMABLE

THRESHOLDS

PACK CURRENT

12-BIT

14-BIT

ADC

+

-

POLARITY

CONTROL

+

RAM REGISTER

VALUE

ADDRESS: [8Fh:8Eh]

DISCHARGE

SHORT-CIRCUIT

DETECT

12

4

PROGRAMMABLE

DETECTION TIME

DSC

DIGITAL CAL EEPROM

[SCTB:SCT0]

[DSC2:DSC0]

CURRENT

DIRECTION

DETECT +

2ms FILTER

CHING

PROGRAMMABLE

THRESHOLDS

DCHING

AO3:AO0

VOLTAGE SELECT BITS

Figure 10.19 Block Diagram for Overcurrent Detect and Current Monitoring

The second part is the analog current direction, overcurrent, and short-circuit detect mechanisms. This circuit is on all the

time. During the operation of the overcurrent detection circuit, the sense amplifier gain is automatically controlled.

For current direction detection, there is a 2ms digital delay for getting into or out of either direction condition. This means

that charge current detection circuit needs to detect an uninterrupted flow of current out of the pack for more than 2ms to

indicate a discharge condition. Then, the current detector needs to identify that there is a charge current or no current for a

continuous 2ms to remove the discharge condition.

The overvoltage and short-circuit detection thresholds are programmable using values in the EEPROM. The discharge

overcurrent thresholds are shown in Table 10.4. The charge overcurrent thresholds are shown in Table 10.5. The discharge

short-circuit thresholds are shown in Table 10.6.

FN8889 Rev.2.00

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ISL94202

Table 10.4

10. Current and Voltage Monitoring

Discharge Overcurrent Threshold Voltages

Equivalent Current (A)

OCD

Threshold

SETTING

(mV)

0.3mΩ

13.3

0.5mΩ

8

1mΩ

2mΩ

2

5mΩ

0.8

000

001

4

8

26.6

16

4

1.6

010

16

24

32

48

64

96

53.3

32

16

8

3.2

011

80

48

24

12

16

24

32

48

4.8

100

106.7

(Note 1)

64

32

6.4

101

96

48

9.6

110

(Note 1)

64

12.8

19.2

111

(Note 1)

Note:

1. These selections may not be reasonable due to sense resistor power dissipation.

Table 10.5

Charge Overcurrent Threshold Voltages

Equivalent Current (A)

OCC

Threshold

Setting

(mV)

0.3mΩ

3.3

0.5mΩ

1mΩ

1

2mΩ

0.5

1

5mΩ

0.2

0.4

0.8

1.2

1.6

2.4

3.2

4.8

000

001

010

011

100

101

110

111

1

2

6.7

4

2

4

13.3

20

8

4

2

6

12

16

24

32

48

6

3

8

26.6

40

8

4

12

16

24

12

16

24

6

53.3

80

8

12

Table 10.6

Discharge Short-Circuit Current Threshold Voltages

Equivalent Current (A)

DSC

Setting

Threshold

(mV)

0.3mΩ

53.3

0.5mΩ

1mΩ

16

2mΩ

8

5mΩ

3.2

000

001

16

24

32

48

80

24

12

4.8

010

32

106.7

160

64

32

16

6.4

011

48

96

48

24

9.6

100

64

213.3

(Note 1)

128

64

32

12.8

19.2

25.6

51.2

101

96

192

96

48

110

128

256

(Note 1)

128

Note

64

111

128

Note:

1. These selections may not be reasonable due to sense resistor power dissipation. Assumes short-circuit FET turn off in 10ms

or less.

The charge and discharge overcurrent conditions and the discharge short-circuit condition need to be continuous for a

period of time before an overcurrent condition is detected. These times are set by individual 12-bit timers. The timers

consist of a 10-bit timer value and a 2-bit scale value (see Table 10.7).

Table 10.7

Charge/Discharge Overcurrent/Short-Circuit Delay Times

[OCCTB:A]

[OCDTB:A]

[OCCT9:0]

[OCDT9:0]

[SCTB:A]

[SCT9:0]

Scale Value

Delay (10-bit Value)

00

01

10

11

0 to 1024µs

0 to 1024ms

0 to 1024s

0 to 1024 minutes

FN8889 Rev.2.00

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ISL94202

10. Current and Voltage Monitoring

10.3 Overcurrent and Short-Circuit Detection

The ISL94202 continually monitors current by mirroring the current across a current-sense resistor (between the CS1 and

CS2 pins) to a resistor to ground.

• A discharge overcurrent condition exists when the voltage across the external sense resistor exceeds the discharge

overcurrent threshold, set by the discharge overcurrent threshold bits [OCD2:OCD0], for an overcurrent time delay, set by

the discharge overcurrent timeout bits [OCDTB:OCDT0]. This condition sets the DOC bit high. The LD_PRSNT bit is

also set high at this time. If the µCFET bit is 0, then the power FETs turn off automatically. If the µCFET bit is 1, then the

external µC must control the power FETs.

• A charge overcurrent condition exists when the voltage across the external sense resistor exceeds the charge overcurrent

threshold, set by the charge overcurrent threshold bits [OCC2:OCC0], for an overcurrent time delay, set by the discharge

overcurrent timeout bits [OCCTB:OCCT0]. This condition sets the COC bit high. The CH_PRSNT bit is also set high at

this time. If the µCFET bit is 0, then the power FETs turn off automatically. If the µCFET bit is 1, then the external µC

must control the power FETs.

• A discharge short-circuit condition exists when the voltage across the external sense resistor exceeds the discharge

short-circuit threshold, set by the discharge short-circuit threshold bits [SCD2:SCD0], for an overcurrent time delay, set by

the discharge short-circuit timeout bits [SCDTB:SCDT0]. This condition sets the DSC bit high. The LD_PRSNT bit is

also set high at this time. The power FETs turn off automatically in a short-circuit condition, regardless of the condition of

the µCFET bit.

10.4 Overcurrent and Short-Circuit Response (Discharge)

Once the ISL94202 enters the discharge overcurrent protection or short-circuit protection mode, the ISL94202 begins a load

monitor state. In the load monitor state, the ISL94202 waits three seconds and then periodically checks the load by turning

on the LDMON output for 0 to 15ms every 256ms. Program the pulse duration with the [LPW3:LPW0] bits in EEPROM.

When turned on, the recovery circuit outputs a small current (~60µA) to flow from the device and into the load. With a load

present, the voltage on the LDMON pin is low and the LD_PRSNT bit remains set to “1”. When the load rises to a

sufficiently high resistance, the voltage on the LDMON pin rises above the LDMON threshold and the LD_PRSNT bit is

reset. When the load has been released for a sufficiently long period of time (two successive load sample periods) the

ISL94202 recognizes that the conditions are OK and resets the DOC or DSC bits.

If the µCFET bit is 0, then the device automatically re-enables the power FETs by setting the DFET and CFET (or PCFET)

bits to “1” (assuming all other conditions are within normal ranges). If the µCFET bit is 1, then the µC must turn on the

power FETs.

An external microcontroller can override the automatic load monitoring of the device. It does this by taking control of the

load monitor circuit (set the µCLMON bit = 1) and periodically pulsing the LMON_EN bit. When the microcontroller

detects that LD_PRSNT = 0, the µC sets the CLR_LERR bit to “1” (to clear the error condition and reset the DOC or DSC bit)

and sets the DFET and CFET (or PCFET) bits to “1” to turn on the power FETs.

FN8889 Rev.2.00

Mar 8, 2017

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ISL94202

10. Current and Voltage Monitoring

10.5 Overcurrent Response (Charge)

Once the ISL94202 enters the charge Overcurrent Protection mode, the ISL94202 begins a charger monitor state. In the

charger monitor state, the ISL94202 periodically checks the charger connection by turning on the CHMON output for 0ms

to 15ms every 256ms. Program the use duration with the [CPW3:CP0] bits in EEPROM.

When turned on, the recovery circuit checks the voltage on the CHMON pin. With a charger present, the voltage on the

CHMON pin is high (>9V) and the CH_PRSNT bit remains set to “1”. When the charger connection is removed, the

voltage on the CHMON pin falls below the CHMON threshold and the CH_PRSNT bit is reset. When the charger has been

released for a sufficiently long period of time (two successive sample periods), the ISL94202 recognizes that the conditions

are OK and clears the COC bit.

If the µCFET bit is 0, the device automatically re-enables the power FETs by setting the DFET and CFET (or PCFET) bits to

“1” (assuming all other conditions are within normal ranges). If the µCFET bit is 1, then the µC must turn on the power FETs.

An external microcontroller can override the automatic charger monitoring of the device. It does this by taking control of

the load monitor circuit (set the µCCMON bit = 1) and periodically pulsing the CMON_EN bit. When the microcontroller

detects that CH_PRSNT = 0, the µC sets the CLR_CERR bit to “1” (to clear the error condition and reset the COC bit) and sets

the DFET and CFET (or PCFET) bits to “1” to turn on the power FETs.

OVERCURRENT

PROTECTION

MODE

NORMAL OPERATION MODE

SENSE

CURRENT

I

OCC

t

OCCT

CHARGER REMOVED

CHARGER STILL

CONNECTED

V

CHMON

WHEN µCFET = 0

SAMPLE RATE SET BY ISL94202

CHMON PIN

WHEN µCFET = 1 AND µCCMON = 1

SAMPLE RATE SET BY MICROCONTROLLER

CMON_EN

(FROM µC)

(Note 2)

COC BIT

(µCFET = 0)

(Note 1)

COC BIT

(µCFET = 1)

CFET

Notes:

1. When µCFET = 1, COC bit is reset when the CLR_CERR is set to “1”.

2. When µCFET = 0, COC is reset by the ISL94202 when the condition is released

Figure 10.20 Charge Overcurrent Protection Mode - Event Diagram

FN8889 Rev.2.00

Mar 8, 2017

Page 41 of 89

ISL94202

10. Current and Voltage Monitoring

10.6 Microcontroller Overcurrent FET Control Protection

If any of the microcontroller override bits (µCSCAN, µCFET, µCLMON, µCCMON, or µCBAL) are set to “1” and the

microcontroller does not send a valid slave byte to the ISL94202 within the watchdog timeout period, then the

microcontroller control bits are all reset, the device turns off the power FETs and the balance FETs, and the INT output

provides a 1µs pulse one time per second.

NORMAL OPERATION MODE

O.C. PROTECTION

NORMAL

SHORT

NORMAL

BATTERY

VOLTAGE

LOAD RELEASED

LOAD NOT RELEASED

3s

WHEN µCFET = 0

V

LDMON

SAMPLE RATE SET BY µC

LDMON PIN

WHEN µCFET = 1 AND µCLMON = 1

SAMPLE RATE IS SET BY µC.

LMON_EN

(FROM µC)

NO CURRENT

FOR 2x IDLE/MODE MODE TIME +

SLEEP MODE TIME

V

DSC

V

DSC

V

OCD

V

OCD

SS

SLEEP

V

CS

t

SC

OCDT

DFET

Note 3

Note 6

Note 5

Note 6

Note 5

CFET

Note 3

PCFET

Note 3

Note 4

DOC

(STAND ALONE)

DSC

Note 4

DOC

(EXTERNAL

CONTROL)

LD_PRSNT

Figure 10.21 Discharge Overcurrent Protection Mode - Event Diagram

Notes:

3. When µCFET = 1, CFET, DFET and PCFET are controlled by external µC.

When µCFET = 0, CFET, DFET and PCFET are controlled automatically by the ISL94202.

4. When µCFET = 1, DOC and DSC bits are reset by setting the CLR_LERR bit.

When µCFET = 0, DOC and DSC are reset by the ISL94202 when the condition is released.

5. PCFET turns on if any cell voltage is less than LVCHG threshold. Otherwise CFET turns on.

6. DFET does not turn on if any cell is less than the UV threshold, unless the DFODUV bit is set.

FN8889 Rev.2.00

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ISL94202

10. Current and Voltage Monitoring

10.7 Voltage, Temperature, and Current Scan

The voltage scan consists of the monitoring of the digital representation of the current, cell voltages, temperatures, pack

voltage, and regulator voltage. This scan occurs once every 32ms, 256ms, or 512ms (depending on the mode of operation,

see Figure 10.22). The temperature, pack voltage, and regulator voltage are scanned only every fourth scan. The open wire

is scanned every 32nd scan as long as the CELLF condition exists.

After each measurement scan, the ISL94202 performs an offset adjustment and stores the values in RAM. After the values

are stored, the state machine executes compare operations that determine if the pack is operating within limits. See

Figure 10.22 for details on the scan sequence.

During manufacture, Intersil provides calibration values in the EEPROM for each cell voltage reading. When there is a new

conversion for a particular voltage, the calibration is applied to the conversion.

CURRENT/VOLTAGE MONITOR (EVERY CYCLE)

ISL94202 CURRENT MONITORING

CURRENT SELECT/SETTLING TIMEADC CONVERT

~500µs

ISL94202 CELL VOLTAGE MONITORING

TURN ON ADC MUX SEL SETTLING TIME ADC CONVERT

OV/UV/UVLO DETECT/FET UPDATE/ADD

OFFSETS/CB CALCULATIONS/OPEN WIRE DETECT

~100µs

OPEN WIRE

CELL1

CELL2

CELL3

CELL7

~1.3 ms

CELL8

CURRENT

LOW POWER STATE

INT_SCAN BIT

32ms

256ms

512ms

CURRENT/VOLTAGE/TEMPERATURE MONITOR (EVERY 4TH CYCLE)

ISL94202 TEMPERATURE MONITORING

MUX SEL SETTLING TIME ADC CONVERT

ISL94202 PACK VOLTAGE MONITORING

MUX SEL SETTLING TIME ADC CONVERT

OV/UV/UVLO DETECT/FET UPDATE/ADD

OFFSETS/CB CALCULATIONS/OPEN WIRE DETECT

TEMPERATURE CALCULATIONS

~50µs

V

/16

OPEN WIRE

CELL1

CELL2

CURRENT

BATT

RGO/2

~1.7 ms

32ms

xT1

xT2

iT

CELL1

LOW POWER

INT_SCAN BIT

256ms

512ms

Figure 10.22 Cell Voltage, Current, Temperature Scanning

Notes:

7. The open-wire test performed every 32 voltage scans, if CELLF = 1, just prior to the scan.

8. FETs turn off immediately if there is an error, but they do not turn on until the end of the voltage scan (at “FET update” if

everything else is OK). An exception to this is when a device wakes up when connected to a load. In this case, the FETs turn

on immediately on wake-up, then a scan begins.

9. The voltage scan can be turned off by an external microcontroller by setting the µCSCAN bit. This bit is monitored by the

watchdog timer, so if an external microcontroller stops communicating with the ISL94202 for more than the WDT period, this

bit is automatically reset and the scan resumes.

FN8889 Rev.2.00

Mar 8, 2017

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ISL94202

10. Current and Voltage Monitoring

10.8 Cell Voltage Monitoring

The circuit that monitors the input cell voltage multiplies the cell voltage by 3/8. The ADC converts this voltage to a digital

value, using a 1.8V internal reference. The ADC produces a calibrated 14-bit value, but only 12 bits are stored in the cell

registers (see Figure 10.23.)

In manufacturing, each cell voltage is calibrated at 3.6V per cell and at +25°C. This calibrated value is used for all

subsequent voltage threshold comparisons.

The ISL94202 has two different overvoltage and undervoltage level comparisons, OVLO/UVLO and OV/UV. While both

use the ADC converter output values and a digital comparator, the responses are different. The OVLO and UVLO levels are

meant to be secondary thresholds above and below the OV and UV thresholds.

10.8.1 UVLO and OVLO

Because they provide a secondary safety condition, OVLO and UVLO can cause the pack to shut down, either

permanently, as in the case of an OVLO when the PSD pin connects to an external fuse; or severely, as in the case of an

UVLO when the device powers down and requires connection to a charger to recover.

The OVLO condition can be overridden by setting the OVLO threshold to FFFH or by an external µC setting the

µCSCAN bit to override the internal automatic scan, then turning on the CFET. However, if the µC takes permanent

control of the scan, the µC needs to take over the scan for all cells and all control functions, including comparisons of

the cell voltage to OV and UV thresholds, managing time delays, and controlling all cell balance functions.

The UVLO response can be overridden by setting the UVLO threshold to 0V. The device can respond to the UVLO

condition by entering the Power-Down mode (set UVLOPD in EEPROM to “1”) or by turning off the FETs and setting

the UVLO bit (UVLOPD = “0”).

When the UVLOPD bit is set to “1” (indicating that the ISL94202 should power down during a UVLO condition) and

the µCFET bit is set to “1” (indicating that the µC is in control of the FETs), the automatic UVLO control forces a

power-down condition, overriding the µC FET control.

The UVLO and OVLO detection both have delays of 5 sample cycles (typically 160ms) to prevent noise generated entry

into the mode.

The OVLO and UVLO values are each set by 12-bit values in EEPROM.

The OVLO has a recovery threshold of OVR and UVLO has a recovery threshold of UVR (if the response overrides

have been set). If the response overrides are not set, then the recovery thresholds are usually irrelevant; for example,

when the UVLO forces the device into a power-down condition or the OVLO condition caused a PSD controlled fuse to

blow.

10.8.2 UV, OV, and Sleep

UV, OV, and SLP thresholds are set by individual 12-bit values.

UV and OV recovery thresholds are set by individual 12-bit values.

The voltage protection scan occurs once every 32ms in normal operation. If there has been no activity (no charge or

discharge current) detected in a programmable period of 1 to 16 minutes, then the scan occurs every 256ms (Idle mode).

If no charge or discharge condition has been detected in Idle mode for the programmable period, then the scan occurs

every 512ms.

If an overvoltage, undervoltage, or sleep condition is detected and is pending, the scan rate remains unchanged. It can

take longer to detect the fault condition in Idle or Doze modes. The scan rate is determined by the mode of operation and

the mode of operation is determined solely by the time since pack charge/discharge current was detected.

FN8889 Rev.2.00

Mar 8, 2017

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ISL94202

10. Current and Voltage Monitoring

VC8

VC7

VOLTAGE

BUFFER

14-BIT ADC OUTPUT

14-BIT VALUE

1.8V

RAM REGISTER

ADDRESS: [ABh:AAh]

CELL VOLTAGE

RAM REGISTER

INPUT

MUX/

LEVEL

SHIFTER

(x 3/8)

12-BIT VALUE

14-BIT

ADC



ADDRESS: [91h:90h] + 2(n-1);

(n = CELL NUMBER)

VC1

VC0

12

VSS

VOLTAGE

BUFFER

DIGITAL CAL EEPROM

TRIM ADDRESS

[AO3:AO0]

VOLTAGE SELECT BITS

Figure 10.23 Block Diagram of Cell Voltage Capture

During a scan, each cell is monitored for overvoltage, undervoltage, and sleep voltage. The voltage will also be

converted to an ADC value and be stored in memory.

If, during the scan, a voltage is outside the set limit, then a timer starts. There is one timer for all of the cells. If the

condition remains on any cell or combination of cells for the duration of the time period, an error condition exists. This

sets the appropriate flag and notifies the protection circuitry to take action (if automatic action is enabled).

The timeout delays for OV, UV, and Sleep are each 12-bit values stored in EEPROM (see Table 10.8).

Table 10.8

OV, UV, Sleep Delay Times

Scale Value

Delay (10-Bit Value)

0 to 1024µs

00

01

10

11

0 to 1024ms

0 to 1024s

0 to 1024min

The control logic for overvoltage, undervoltage, and sleep conditions is shown in Table 10.8, Figure 10.24 and

Figure 10.25 on page 48.

FN8889 Rev.2.00

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ISL94202

10. Current and Voltage Monitoring

10.9 Overvoltage Detection/Response

The device needs to monitor the voltage on each battery cell (V ). If for any cell, [V

> V for a time

OV

Cn

Cn - VC(n-1)]

exceeding t , the device sets an OV flag. Then (if µCFET = 0), the ISL94202 turns the charge FET OFF, by setting the

OV

CFET bit to “0”. Once the OV flag is set the pack has entered Overcharge Protection mode. The status of the discharge FET

remains unaffected.

The charge FET remains off until the voltage on the overcharged cell drops back below a recovery level, V

, for a

OVR

recovery time period, t

. The t

time equals the t time.

OVR

OVR OV

The detection timer and recovery timer are asynchronous to the voltage threshold. As a result, a setting of 1s can result in a

delay time of 1s to 2s, depending on when the OV/OVR is detected. For a setting of 1000ms, the detection time will be

within 1ms.

The device further continues to monitor the battery cell voltages and is released from overcharge protection mode when

[V

< V

for more than the overcharge release time, for all cells.

Cn - VC(n-1)]

OVR

When the device is released from overcharge protection mode, the charge FET is automatically switched ON (if µCFET =

0). When the device returns from Overcharge Protection mode, the status of the discharge FET remains unaffected.

During charge, if the voltage on any cell exceeds an End-Of-Charge threshold (EOCS), then an EOCHG bit is set and the

EOC output is pulled low. The EOCHG bit and the EOC output resume normal conditions when the voltage on all cells

drops back below the [EOCS - 117mV] threshold.

There is also an overvoltage lockout. When this level is reached, an OVLO bit is set, the PSD output is set, and the charge

FET or precharge FET is immediately turned off (by setting the CFET or PCFET bit to “0”). The PSD output can be used to

blow a fuse to protect the cells in the pack.

If, during an OV condition, the µCFET bit is set to “1”, the microcontroller must control both turn off and turn on of the

charge and precharge power FETs. This does not apply to the OVLO condition.

The device includes an option to turn the charge FET back on in an overvoltage condition, if there is discharge current

flowing out of the pack. This option is set by the CFODOV (CFET ON During Overvoltage) Flag stored in EEPROM.

Then, if the discharge current stops and there is still an overcharge condition on the cell, the device again disables the charge

FET.

FN8889 Rev.2.00

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ISL94202

10. Current and Voltage Monitoring

OVERVOLTAGE LOCK-OUT

PROTECTION MODE

NORMAL

OPERATION

MODE

NORMAL OPERATION MODE

OVERCHARGE

PROTECTION MODE

V

OVLO

V

OV

VEOC

t

OV

V

OVR

VCn

t

OVR

CFLG RESET

DISCHARGE

CHARGE

PACK

CURRENT

DFLG RESET

DFLG SET

DFET

CFET

CFODOV FLAG = 1 ALLOWS

CFET TO TURN ON DURING OV, IF DISCHARGING

EOC PIN

EOCHG BIT

OV BIT

SD PIN

PSD PIN

OVLO BIT

Figure 10.24 Overvoltage Protection Mode-Event Diagram

FN8889 Rev.2.00

Mar 8, 2017

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ISL94202

10. Current and Voltage Monitoring

VC

V

UVR

V

UV

LVCH

V

SL

UVLO

t

+3s

t

+3s

UV

V

t

UV

t

SL

IF CHARGE VOLTAGE

CONNECTED

CHARGE

I

PACK

DISCHARGE

MICROCONTROLLER ONLY.

(µCLMON BIT = 1)

SAMPLING FOR LOAD RELEASE

(µCLMON PULSES)

LMON_EN BIT

(FROM µC)

(LOOKING FOR TOOL TRIGGER RELEASE)

LOAD RELEASED

LDMON PIN

V

LDMON

(STARTS LOOKING FOR CHARGER/LOAD CONNECT)

CMON_EN BIT

CHMON PIN

V

WAKE UP

WKUPC

WKUPL

DFET REMAINS

SET IF

UVLOPD = 0

CHARGE

CONNECT

V

AND µCFET = 1

LD_PRSNT BIT

DFET BIT

DFET ON IF CHARGING

AND DFODUV BIT IS SET

DFET ON IF CHARGING

AND DFODUV BIT IS SET

CFET BIT

IF PCFETE SET, PCFET

PCFET BIT

TURNS ON HERE, NOT CFT

IN_SLP BIT

UVLO BIT

OVERDISCHARGE

SLEEP

PROTECTION MODE

OVERDISCHARGE

PROTECTION MODE

UVLO SET IF UVLOPD = 0

If UVLOPD = 1 AND

µCFET = 0 OR 1, DEVICE

POWERS DOWN

UV BIT

(µCFET = 0)

UV BIT

(µCFET = 1)

RESET WHEN MICROCONTROLLER WRITES CLR_LERR BIT = 1

Figure 10.25 Undervoltage Protection Mode-Event Diagram

10.10 Undervoltage Detection/Response

If V < V , for a time exceeding t , the cells are said to be in an overdischarge (undervoltage) state. In this condition,

Cn

UV

UVT

the ISL94202 sets a UV bit. If the µCFET bit is set to “0”, the ISL94202 also switches the discharge FET OFF (by setting

the DFET bit = 0).

While any cell voltage is less than a low voltage charge threshold, and if the PCFETE bit is set, the PCFET output is turned

on instead of the CFET output. This enables a precharge condition to limit the charge current to undervoltage cells.

From the undervoltage mode, if the cells recover to above a V

level for a time exceeding t

plus three seconds, the

UVT

UVR

ISL94202 pulses the LDMON output once every 256ms and looks for the absence of a load. The pulses are of

programmable duration (0ms to 15ms) using the [LPW3:LPW0] bits. During the pulse period, a small current (~60µA) is

output into the load. If there is no load, then the LDMON voltage will be higher than the recovery threshold of 0.6V. When

the load has been removed and the cells are above the undervoltage recovery level, the ISL94202 clears the UV bit and, if

µCFET = 0, turns on the discharge FET and resumes normal operation.

Note, the t detection timer and t

recovery timer are asynchronous to the voltage threshold. As a result, a setting of 1s

UVR

UV

can result in a delay time of 1s to 2s (and a recovery time of 3s to 4s), depending on when the UV/UVR is detected. For a

setting of 1000ms, the detection time will be within 1ms.

FN8889 Rev.2.00

Mar 8, 2017

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ISL94202

10. Current and Voltage Monitoring

If any of the cells drop below a sleep threshold (VCn < V ) for a period of time (t ), the device sets the Sleep bit and

SLP

SLT

(if µCFET = 0), the ISL94202 turns off both FETs (DFET and CFET = 0) and puts the pack into a Sleep mode by setting the

Sleep bit to “1”. If the µCFET bit is set, the device does not go to sleep.

There is also an undervoltage lockout condition. This is detected by comparing the cell voltages to a programmable UVLO

threshold. When any cell voltage drops below the UVLO threshold and remains below the threshold for five voltage scan

periods (~160ms), a UVLO bit is set and the SD output pin goes active. If UVLOPD = 0 and µCFET = 0, the DFET is also

turned off. If UVLOPD = 1, then the ISL94202 goes into a power-down state.

If the µCFET bit is set to “1”, the microcontroller must both turn off and turn on the discharge power FETs and control the

sleep and power-down conditions.

The device includes an option to turn the discharge FET back on in an undervoltage condition, if there is a charge current

flowing into the pack. This option is set by the DFODUV (DFET ON During Undervoltage) Flag stored in EEPROM. Then,

if the charge current stops and there is still an undervoltage condition on the cell, the device again disables the discharge

FET.

10.11 Temperature Monitoring/Response

As part of the normal voltage scan, the ISL94202 monitors both the temperature of the device and the temperature of two

external temperature sensors. External Temperature 2 can be used to monitor the temperature of the FETs, instead of the

cells, by setting the xT2M bit to “1”.

The temperature voltages have two gain settings (the same gain for all temperature inputs). For external temperatures, a

TGain bit = 0, sets the gain to 2x (full scale input voltage = 0.9V). A TGain bit = 1 and sets the gain to 1x (full scale input

voltage = 1.8V). See Figure 10.26.

The default temperature gain setting is x2, so the temperature monitoring circuit of T

= 0 (GAIN = 2) is preferred. This

GAIN

configuration has other advantages. The temperature response is more linear and covers a wider temperature range before

nearing the limits of the ADC reading.

The internal temperature reading converts from voltage to temperature using (EQ. 1) and (EQ. 2):

intTempmV  1000

------------------------------------------------------

0.92635

TGain = 1

TGain = 0

– 273.15 = ICTempC

(EQ. 1)

(EQ. 2)

intTempmV  1000

------------------------------------------------------

1.8527

If the temperature of the IC (Internal Temp) goes above a programmed over-temperature threshold, then the ISL94202 sets

an over-temperature flag (IOT), prevents cell balancing and turns off the FETs.

TEMPO PIN

22kΩ

82.5kΩ

xT1 PIN

xT2 PIN

xT1 PIN

xT2 PIN

+80°C = 0.050V

+80°C = 0.153V

+50°C = 0.120V

+25°C = 0.270V

0°C = 0.620V

+50°C = 0.295V

+25°C = 0.463V

0°C = 0.710V

10kΩ

-40°C = 1.758V

THERMISTORS: 10k,

Murata XH103F

-40°C = 0.755V

T_GAIN= 0 (GAIN = 2)

T_GAIN= 1 (GAIN = 1)

Figure 10.26 External Temperature Circuits

FN8889 Rev.2.00

Mar 8, 2017

Page 49 of 89

ISL94202

10. Current and Voltage Monitoring

Figure 10.27 Temperature Management State Machine

FN8889 Rev.2.00

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ISL94202

10. Current and Voltage Monitoring

10.11.1 Over-Temperature

If the temperature of either of the external temperature sensors (xT1 or xT2), as determined by an external resistor and

thermistor, goes below any of the thresholds (charge, discharge, and cell balance as set by internal EEPROM values),

indicating an over-temperature condition, the ISL94202 sets the corresponding over-temp flag.

If the automatic responses are enabled (µCFET = 0), the Charge Over-Temperature (COT) or Discharge Over-

Temperature (DOT) flag is set and the corresponding charge or discharge FET is turned off. For series FET applications,

COT will not shut off CFET during discharge regardless of µCFET setting. If the Cell Balance Over-Temperature

(CBOT) flag is set, the device turns off the balancing outputs and prevents cell balancing while the condition exists.

If the automatic responses are disabled (µCFET = 1), then the ISL94202 only sets the flags and an external

microcontroller responds to the condition.

An exception to the above occurs if the xT2 sensor is configured as a FET temperature indicator (XT2M = 1). In this

case, the xT2 is not compared to the cell balance temperature thresholds, it is used only for power FET control.

10.11.2 Under-Temperature

If the temperature of either of the external temperature sensors (xT1 or xT2), as determined by an external resistor and

thermistor, goes above any of the thresholds (charge, discharge, and cell balance as set by internal EEPROM values),

indicating an under-temperature condition, the ISL94202 sets the corresponding under-temperature flag.

If the xT1 automatic responses are enabled (µCFET = 0), then the Charge Under-Temperature (CUT) or Discharge

Under-Temperature (DUT) flag is set the corresponding charge or discharge FET is turned off. For series FET

applications, CUT will not shut off CFET during discharge regardless of µCFET setting. If the Cell Balance

Under-Temperature (CBUT) flag is set, the device turns off cell balancing outputs and prevents cell balancing.

If the xT2 automatic responses are disabled (µCFET = 1) then the ISL94202 only sets the flags and an external

microcontroller responds to the condition.

An exception to the above occurs if the xT2 sensor is configured as a FET temperature indicator (XT2M = 1). In this

case, the xT2 is not compared to the cell balance temperature thresholds. It is used only for power FET control).

For both xT1 and xT2, when the temperature drops back within a normal operating range, the over or under-temperature

condition is reset.

FN8889 Rev.2.00

Mar 8, 2017

Page 51 of 89

ISL94202

10. Current and Voltage Monitoring

10.12 Microcontroller Read of Voltages

An external microcontroller can read the value of any of the internally monitored voltages independently of the normal

voltage scan. To do this requires that the µC first set the µCSCAN bit. This stops the internal scan and starts the watchdog

timer. If the µC maintains this state, then communication must continue and the µC must manage all voltage and current

pack control operations as well as implement the cell balance algorithms. However, if the µCSCAN bit remains set for a

short period of time, the device continues to monitor voltages and control the pack operation.

Once the µCSCAN bit is set, the external µC writes to register 85H to select the desired voltage and to start the ADC

conversion (set the ADCSTRT bit to “1” to start an ADC conversion). Once the conversion is complete, the results are read

from the ADC registers [ADCD:ADC0]. The result is a 14-bit value. The ADC conversion takes about 100µs or the µC can

2

poll the I C link waiting for an ACK to indicate that the ADC conversion is complete.

If the µCSCAN bit is set when the ISL94202 internal scan is scheduled, then the internal scan pauses until the µCSCAN bit

is cleared and the internal scan occurs immediately.

Reading an ADC value from the µC requires the following sequence (and time) to complete:

Table 10.9

µC Controlled Measurement of Individual Voltages

Time at 400kHz

I²C CLK (ea.)

Time (Cumulative)

(µs)

Number I²CCycles

Step

Operation

(µs)

1

2

3

4

5

6

Set µCSCAN bit

29

72.5

110

72.5

145

Set voltage and start ADC

Wait for ADC complete

Read register AB

N/A

29

255

72.5

100

327.5

410

Read register AA

29

Clear µCSCAN bit

29

472.5

To sample more than one time (for averaging), repeat Steps 2 through 5 as many times as desired. However, if this is a

continuous operation, care must be taken to monitor other pack functions or to pause long enough for the ISL94202 internal

operations to collect data to control the pack. A burst of five measurements takes about 1.8ms.

FN8889 Rev.2.00

Mar 8, 2017

Page 52 of 89

ISL94202

10. Current and Voltage Monitoring

10.13 Voltage Conversions

To convert from the digital value stored in the register to a “real world” voltage, the following conversion equations should

be used.

The term “HEXvalue ” means the Binary to Decimal conversion of the register value.

10

10.13.1 Cell Voltages

HEXvalue₁₀ 1.8  8

(EQ. 3)

-------------------------------------------------------

Cell Voltage =

4095  3

The cell voltage conversion equation is also used to set the voltage thresholds.

10.13.2 Pack Current

HEXvalue₁₀ 1.8

(EQ. 4)

--------------------------------------------------------

Pack Current =

4095  Gain  SenseR

Gain is the gain setting in register 85H, set by the [CG1:CG0] bits.

SenseR is the sense resistor value in Ohms.

This pack current reading is valid only when the current direction indicators show that there is a charge or discharge

current. If the current is too low for the indicators to show current flowing, then use the 14-bit value to estimate the

current. See “14-bit Register” on page 53.

10.13.3 Temperature

HEXvalue₁₀ 1.8

---------------------------------------------

4095

(EQ. 5)

Temperature =

Equation 5 converts the register value to a voltage, but the temperature then is converted to a temperature depending on

the external arrangement of thermistor and resistors. See “Temperature Monitoring/Response” on page 49.

10.13.4 14-bit Register

If HEXvalue is greater than or equal to 8191, then:

10

HEXvalue₁₀– 16384  1.8

14-bit value =

(EQ. 6)

(EQ. 7)

-----------------------------------------------------------------------

8191

If HEXvalue is less than 8191, then:

10

HEXvalue₁₀ 1.8

14-bit value =

---------------------------------------------

8191

Once the voltage value is obtained, if the measurement is a cell voltage, then the value should be multiplied by 8/3. A

temperature value is used “as-is”, but the voltage value is converted to temperature by including the external

temperature circuits into the conversion.

To determine pack current from this 14-bit value requires the following computations.

First, if both current direction flags show zero current, then the external controller must apply an offset. Measure the 14-

bit voltage when there is a pack current of 0. Then subtract this offset from the 14-bit current-sense measurement value

and take the absolute value of the result. If either of the current direction flags indicate a current, then do not subtract the

offset value, but use the 14-bit value directly. In either case, divide the 14-bit voltage value by the current-sense gain and

the current-sense resistor to arrive at the pack current.

FN8889 Rev.2.00

Mar 8, 2017

Page 53 of 89

ISL94202

11. Microcontroller FET Control

The external microcontroller can override the device control of the FETs. With the µCFET bit set to “1”, the external

microcontroller can turn the FETs on or off under all conditions except the following:

• If there is a discharge short-circuit condition, the device turns the FETs off. The external microcontroller is responsible for

turning the FETs back on once the short-circuit condition clears.

• If there is an internal over-temperature condition, the device turns the FETs off. The external microcontroller is responsible for

turning the FETs back on once the temperature returns to within normal operating limits.

• If there is an overvoltage lockout condition, the device turns the charge or precharge FETs off. The external microcontroller is

responsible for turning the FETs back on, once the OVLO condition clears. This assumes that the PSD output has not blown a fuse to

disable the pack.

• If there is an open-wire detection, the device turns the FETs off. The external microcontroller is responsible for turning the FET back

on. This assumes that the open wire did not cause the PSD output to blow a fuse to disable the pack.

• If the FETSOFF input is HIGH, the FETs turn off and remain off. The external µC is responsible for turning the FETs on once

the FETSOFF condition clears.

• If there is a sleep condition, the device turns the FETs off. On wake up, the microcontroller is responsible for turning on

the FETs.

The microcontroller can also control the FETs by setting the µCSCAN bit. However, this also stops the scan, requiring the

microcontroller to manage the scan, voltage comparisons, FET control, and cell balance. While the µCSCAN bit is set to “1”,

the only operations controlled by the device are:

• Discharge short-circuit FET control. The external µC cannot override the turn off of the FETs during the short-circuit.

• FETSOFF external control. The FETSOFF pin has priority on control of the FETs, even when the microcontroller is managing

the scan.

• In all other cases, the microcontroller must manage the FET control, because it is also managing the voltage scan and all

comparisons.

FN8889 Rev.2.00

Mar 8, 2017

Page 54 of 89

ISL94202

12. Cell Balance

At the same rate as the scan of the cell voltages, if cell balancing is on, the system checks for proper cell balance conditions.

The ISL94202 prevents cell balancing if proper temperature, current, and voltage conditions are not met. The cells only balance

during a CBON time period. When the CBOFF timer is running, the cell balance is off. Three additional bits determine whether

the balancing happens only during charge, only during discharge, during both charge and discharge, during the end of charge

condition, or not at any time.

• The cell balance circuit depends on the 14-bit ADC converter built into the device and the results of the cell voltage scan

(after calibration).

• The ADC converter loads a set of registers with each cell voltage during every cell voltage measurement.

• At the end of the cell voltage measurement scan, the ISL94202 updates the minimum (CELMIN) and maximum (CELMAX)

cell voltages.

• After calculating the CELMIN and CELMAX values, all of the cell voltages are compared with the CELMIN value. When

any of the cells exceed CELMIN by CBDL (the minimum CB delta voltage), a flag is set in RAM indicating that the cell

needs balancing (this is the CBnON bit).

• If any of the cells exceed the lowest cell by CBDU (maximum CB delta voltage) then a flag is set indicating that a Cell

voltage failure occurred (CELLF).

• When the CELLF flag indicates that there is too great a cell to cell differential, the balancing is turned off.

• If CELMAX is below CBMIN (all the cell voltages are too low for balancing) then the CBUV bit is set and there will be no

cell balancing. Cell balance does not start again until the CBMIN value rises above (CBMIN + 117mV). When this happens,

the ISL94202 clears the CBUV bit.

• If the CELMIN voltage is greater than the CBMAX voltage (all the cell voltages are too high for balancing) then the CBOV

bit is set and there will be no cell balancing. Cell balancing does not start again until the CBMAX value drops below

(CBMAX - 117mV). When this happens, the ISL94202 clears the CBOV bit.

• A register in EEPROM (CELLS) identifies the number of cells that are supposed to be present so only the cells present are

used for the cell balance operation. Note: This is also used in the cell voltage scan and open-wire detect operation.

• There are no limits to the number of cells that can be balanced at any one time, because the balancing is done external to the

device.

• The cell balance block updates at the start of the cell balance ON period to determine if balancing is needed and that the right

cells are being balanced. The cells selected at this time will be balanced for the duration of the cell balance period.

• The cell balance is disabled if any external temperature is out of a programmed range set by CBUTS (cell balance under

temperature) and CBOTS (cell balance over-temperature).

• The cell balance operation can be disabled by setting the Cell Balance During Charge (CBDC), the Cell Balance During

Discharge (CBDD), and the Cell Balance During End-of-Charge (CB_EOC) bits to zero. See Table 12.10 on page 56.

• Cell balancing turns off when set to balance in the charge mode and there is no charging current detected (see CB_EOC

exception below).

• Cell balancing turns off when set to balance in the discharge mode and there is no discharge current detected (see CB_EOC

exception below).

• If cell balancing is set to operate during both charge and discharge, then ISL94202 balances while there is charge current or

discharge current, but does not balance when no current flow is detected (all other limiting factors continue to apply). See

CB_EOC exception in the following.

• The CB_EOC bit provides an exception to the cell balance current direction limit. When the CB_EOC bit is set, balancing

occurs while an end of charge condition exists (EOC bit = 1), regardless of current flow. This allows the ISL94202 to “drain”

high voltage cells when the charge is complete. This speeds the balancing of the pack, especially when there is a large

capacity differential between cells. Once the end of charge condition clears, the cell balance operation returns to normal

programming.

• Balance is disabled by asserting the FETSOFF external pin.

FN8889 Rev.2.00

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ISL94202

12. Cell Balance

• The cell balance outputs are on only while the cell balance on timer is counting down. This is a 12-bit timer. The cell balance

outputs are all off while the cell balance off timer is counting down. This is also a 12-bit timer. The timer values are set as in

Table 12.11.

Table 12.10 Cell Balance Truth Table (see Figure 12.28)

CB_EOC Bit

EOC Pin

CBDC

CHING

CBDD

DCHING

Enable

0

1

x

1

0

1

x

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

0

1

x

1

x

1

x

1

x

1

x

0

1

0

Table 12.11 CBON and CBOFF Times

Scale Value

Time (10-Bit Value)

0 to 1024µs

00

01

10

11

0 to 1024ms

0 to 1024s

0 to 1024min

FN8889 Rev.2.00

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Page 56 of 89

ISL94202

12. Cell Balance

CELL8 VOLTAGE - CELLMIN >

CBMINDV OR [CB8ON]

CB8 DRIVER

CB7 DRIVER

CB6 DRIVER

CB5 DRIVER

CELL7 VOLTAGE - CELLMIN >

CBMINDV OR [CB7ON]

CB OFF TIMER IS COUNTING

CBOV BIT

CELL6 VOLTAGE - CELLMIN >

CBMINDV OR [CB6ON]

CBUV BIT

CBERR

CBOT BIT

CBUT BIT

OPEN BIT

CELLF BIT

CELL5 VOLTAGE - CELLMIN >

CBMINDV OR [CB5ON]

ENABLE

CASC

CELL4 VOLTAGE - CELLMIN >

CBMINDV OR [CB4ON]

CB4 DRIVER

CB3 DRIVER

CB2 DRIVER

CB1 DRIVER

SD PIN

FETSOFF PIN

CELL3 VOLTAGE - CELLMIN >

CBMINDV OR [CB3ON]

1

3

EOC PIN

CB_EOC

2

7

CELL2 VOLTAGE - CELLMIN >

CBMINDV OR [CB2ON]

CHING BIT

CBDD

4

CELL1 VOLTAGE - CELLMIN >

CBMINDV OR [CB1ON]

CBDC BIT

6

5

DCHING BIT

Figure 12.28 Cell Balance Operation

12.1 µC Control of Cell Balance FETs

To control the cell balance FETs, the external microcontroller first needs to set the µCCBAL bit to turn off the automatic

cell balance operation.

To turn on a cell balance FET, the µC needs to turn on the cell balance output FET using the Cell Balance Control Register

84H. In this register, each bit corresponds to a specific cell balance output.

With the cell balance outputs specified, the microcontroller sets the CBAL_ON bit. This turns on the cell balance output

control circuit.

12.2 Cell Balance FET Drive

The cell balance FETs are driven by a current source or sink of 25µA. The gate voltage on the externals FET is set by the

gate to source resistor. This resistor should be set such that the gate voltage does not exceed 9V. An external 9V zener diode

across the gate to source resistor can help to prevent overvoltage conditions on the cell balance pin.

The cell balance circuit connection is shown in Figure 12.29 on page 58.

FN8889 Rev.2.00

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ISL94202

12. Cell Balance

ISL94202

CBAL_ON

100Ω

VC8

470nF

10kΩ

4M

10V

CB8

VC7

ENABLE

316kΩ

39Ω

1kΩ

CB5ON

CB4ON

CB3ON

47nF

10kΩ

10V

4M

CB7

VC6

CB6

VC5

316kΩ

39Ω

1kΩ

47nF

10kΩ

316kΩ

CB2ON

CB1ON

1kΩ

39Ω

47nF

10kΩ

39Ω

CB5

VC4

CB4

10V

316kΩ

1kΩ

4M

47nF

10kΩ

39Ω

316kΩ

1kΩ

VC3

CB3

VC2

CB2

VC1

CB1

47nF

10kΩ

316kΩ

1kΩ

47nF

10kΩ

39Ω

316kΩ

1kΩ

4M

47nF

10kΩ

316kΩ

1kΩ

10V

VC0

VSS

CB8ON

CB7ON

CB6ON

47nF

VSS

Figure 12.29 Cell Balance Drive Circuits and Cell Connection Options

FN8889 Rev.2.00

Mar 8, 2017

Page 58 of 89

ISL94202

13. Watchdog Timer

2

The I C watchdog timer prevents an external microcontroller from initiating an action that it cannot undo through the I C port,

which can result in poor or unexpected operation of the pack.

The watchdog timer is normally inactive when operating the device in a stand-alone operation. When the pack is expected to

have a µC along with the ISL94202, the WDT is activated by setting any of the following bits: µCSCAN, µCCMON,

µCLMON, µCCBAL, µCFET, EEEN.

2

When active (an external µC is assumed to be connected), the absence of I C communications for the watchdog timeout period

causes a timeout event. The ISL94202 needs to see a start bit and a valid slave byte to restart the timer.

The watchdog timeout signal turns off the cell balance and power FET outputs, resets the serial interface, and pulses the INT

output once per second in an attempt to get the microcontroller to respond. If the INT is unsuccessful in restarting the

communication interface, the part operates normally, except the power FETs and cell balance FETs are forced off. The

2

ISL94202 remains in this condition until I C communications resumes.

2

When I C communication resumes, the µCSCAN, µCCMON, µCLMON, µCFET, and EEEN bits are automatically cleared

and the µCCBAL bit remains set. The power FETs and cell balance FETs turn on, if conditions allow.

FN8889 Rev.2.00

Mar 8, 2017

Page 59 of 89

ISL94202

14. Power FET Drive

The ISL94202 drives the power FETs gates with a voltage higher than the supply voltage by using external capacitors as part of

a charge pump. The capacitors connect (as shown in Figure 1.2 on page 3) and are nominally 4.7nF. The charge pump applies

approximately (V * 2) voltage to the gate, although the voltage is clamped at V + 16V.

DD

The power FET turn-on times are limited by the capacitance of the power FET and the current supplied by the charge pump.

The power FET turn-off times are limited by the capacitance of the power FET and the pull-down current of the ISL94202. The

ISL94202 provides a pull-down current for up to 300µs. This should be long enough to discharge any FET capacitance.

Table 14.12 shows typical turn-on and turn-off times for the ISL94202 under specific conditions.

Table 14.12 Power Fet Gate Control (Typical)

Parameter

Conditions

DFET, CFET, PCFET

Typical

Power FET Gate Turn-On Current

32kHz 5mA, pulses, 50% duty cycle

Charge pump caps = 4.7nF

Power FET Gate Turn-On Time

10% to 90% of final voltage

V_DD= 28V;

160µs

DFET, CFET = IRF1404

PCFET = FDD8451

Power FET Gate Turn-Off Current

CFET, CFET, PCFET

13mA (CFET, PCFET)

15mA (DFET)

Power FET Gate Turn-Off Pulse Width

Power FET Gate Fall Time

Pulse duration

300µs

90% to 10% of final voltage V_DD= 28V;

DFET: IRF1404

CFET: IRF1404

PCFET: FDD8451

6µs

2µs

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ISL94202

15. General I/Os

There is an open-drain output (SD) that is pulled up to RGO (using an external resistor) and indicates if there are any error

conditions, such as overvoltage, undervoltage, over-temperature, open input, and overcurrent. The output goes active (LOW)

when there is any cell or pack failure condition. The output returns HIGH when all error conditions clear.

There is an open-drain output (EOC) that is pulled up to RGO (using an external resistor) and indicates that the cells have

reached an end of charge state. The output goes active (LOW) when all cell voltages are above a threshold specified by a 12-bit

value in EEPROM. The output returns HIGH, when all cells are below the EOC threshold.

Factory programmable options offer inverse polarity of SD or EOC. Please contact Automotive Marketing if there is interest in

either of these options.

The PSD pin goes active high, when any cell voltage reaches the OVLO threshold (OVLO flag). Optionally, PSD also goes

high if there is a voltage differential between any two cells that is greater than a specified limit (CELLF flag) or if there is an

open-wire condition. This pin can be used for blowing a fuse in the pack or as an interrupt to an external µC.

An input pin (FETSOFF), when pulled high, turns off the power FETs and the cell balance FETs, regardless of any other

condition.

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ISL94202

16. Higher Voltage Microcontrollers

When using a microcontroller powered by 3.3V or 5V, the design can include pull-up resistors to the microcontroller supply on

the communication link and the open-drain SD and EOC pins (instead of pull-up resistors to RGO.)

The INT pin is a CMOS output with a maximum voltage of RGO+0.5V. It is OK to connect this directly to a microcontroller as

long as the microcontroller pin does not have a pull up to the 3.3/5V supply. If it does, then a series resistor is recommended.

The FETSOFF input on the ISL94202 is also limited to RGO+0.5V. This is limited by an input ESD structure that clamps the

voltage. The connection from the µC to this pin should include a series resistor to limit any current resulting from the clamp.

An example of this connection is shown in Figure 16.30.

ISL94202

µCONTROLLER

3.3/5V

SD

In_SD

In_EOC

In_INT

EOC

INT

*

SCL

SDA

SDAI

SDAO

10k

Out_FETSOFF

FETSOFF

* Resistor needed only if µC has a pull-up on the In_INT pin

Figure 16.30 Connection of Higher Voltage Microcontroller

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ISL94202

17. Packs with Fewer than Eight Cells

See “Pack Configuration” on page 27 for help when using fewer than eight cells. This section presents options for minimum

number of components. However, when using the ISL94202EVAL1Z evaluation board with fewer than eight cells, it is not

necessary to remove components from the PCB. Simply tie the unused connections together, as shown in Figure 17.31. This

normally requires only a different cable.

8 CELLS

VC8

7 CELLS

VC8

6 CELLS

VC8

CB8

VC7

CB7

VC6

CB6

VC5

CB5

VC4

CB8

VC7

CB7

VC6

CB6

VC5

CB5

VC4

CB8

VC7

CB7

VC6

CB6

VC5

CB5

VC4

CB4

VC3

CB4

VC3

CB4

VC3

CB3

VC2

CB2

VC1

CB1

CB3

VC2

CB2

VC1

CB1

CB3

VC2

CB2

VC1

CB1

VC0

VSS

VC0

VSS

VC0

VSS

5 CELLS

VC8

4 CELLS

VC8

3 CELLS

VC8

CB8

VC7

CB7

VC6

CB8

VC7

CB7

VC6

CB8

VC7

CB7

VC6

CB6

VC5

CB5

VC4

CB6

VC5

CB5

VC4

CB6

VC5

CB5

VC4

CB4

VC3

CB4

VC3

CB4

VC3

CB3

VC2

CB2

VC1

CB1

CB3

VC2

CB2

VC1

CB1

CB3

VC2

CB2

VC1

CB1

VC0

VSS

VC0

VSS

VC0

VSS

Figure 17.31 Battery Connection Options Using the ISL94202EVAL1Z Board

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ISL94202

18. PC Board Layout

The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are

recommendations to achieve optimum high performance from your PC board.

• The use of low inductance components, such as chip resistors and chip capacitors, is strongly recommended.

• Minimize signal trace lengths. This is especially true for the CS1, CS2, and VC0-VC8 inputs. Trace inductance and

capacitance can easily affect circuit performance. Vias in the signal lines add inductance at high frequency and should be

avoided.

• Match channel-to-channel analog I/O trace lengths and layout symmetry. This is especially true for the CS1 and CS2 lines,

since their inputs are normally very low voltage.

• Maximize use of AC decoupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e., no split

planes or ground plane gaps under these lines). Avoid vias in the signal I/O lines.

• VDD bypass and charge pump capacitors should use wide temperature and high frequency dielectric (X7R or better) with

capacitors rated at 2X the maximum operating voltage.

• The charge pump and VDD bypass capacitors should be located close to the ISL94202 pins and VDD should have a good

ground connection.

• When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum.

• An example PCB layout is shown in Figure 18.32. This figure shows placement of the VDD bypass capacitor close to the

VDD pin and with a good ground connection. The charge pump capacitors are also close to the IC. The current-sense lines are

shielded by ground plane as much as possible. The ground plane under the IC is shown as an “island”. The intent of this layout

was to minimize voltages induced by EMI on the ground plane in the vicinity of the IC. This example assumes a 4-layer board

with most signals on the inner layers.

CURRENT-SENSE

CHARGE PUMP

INPUTS

VDD CAP

CAPS

GND PLANE

PINK = TOP

BLUE = BOTTOM

“ISLAND GROUND”

Figure 18.32 Example 4-Layer PCB Layout for VDD Bypass, Charge Pump, and Current Sense

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ISL94202

18. PC Board Layout

18.1 QFN Package

The QFN package requires additional PCB layout rules for the thermal pad. The thermal pad is electrically connected to

VSS supply through the high-resistance IC substrate. The thermal pad provides heat sinking for the IC. In normal operation,

the device should generate little heat, so thermal pad design and layout are not too important. However, if the design uses

the RGO pin to supply power to external components, then the IC can experience some internal power dissipation. In this

case, careful layout of the thermal pad and the use of thermal vias to direct the heat away from the IC is an important

consideration. Besides heat dissipation, the thermal pad also provides noise reduction by providing a ground plane under the

IC.

18.2 Circuit Diagrams

The “Block Diagram” on page 3 shows a simple application diagram with eight cells in series and two cells in parallel

(8S2P).

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ISL94202

19. EEPROM

The ISL94202 contains an EEPROM array for storing the device configuration parameters, the device calibration values, and

2

some user available registers. Access to the EEPROM is through the I C port of the device. Memory is organized in a memory

map as described in:

• “Registers: Summary (EEPROM)” on page 74

• “Registers: Summary (RAM)” on page 75

• “Registers: Detailed (EEPROM)” on page 76

• “Registers: Detailed (RAM)” on page 82.

When the device powers up, the ISL94202 transfers the contents of the configuration EEPROM memory areas to RAM. (Note

that the user EEPROM has no associated RAM). An external microcontroller can read the contents of the Configuration RAM

or the contents of the EEPROM. Prior to reading the EEPROM, set the EEEN bit to “1”. This enables access to the EEPROM

area. If EEEN is “0”, then a read or write occurs in the shadow RAM area.

The content of the Shadow Ram determines the operation of the device.

Reading from the RAM or EEPROM can be done using a byte or page read. See:

• “Current Address Read” on page 70

• “Random Read” on page 70

• “Sequential Read” on page 71

• “EEPROM Access” on page 72

• “Register Protection” on page 73

Writing to the Configuration or User EEPROM must use a Page Write operation. Each Page is four bytes in length and pages

begin at Address 0.

See:

• “Page Write” on page 69

• “Register Protection” on page 73

The EEPROM contains an error detection and correction mechanism. When reading a value from the EEPROM, the device

checks the data value for an error.

If there are no errors, then the EEPROM value is valid and the ECC_USED and ECC_FAIL bits are set to “0”. If there is a 1-bit

error, the ISL94202 corrects the error and sets the ECC_USED bit. This is a valid operation and value read from the EEPROM

is correct. During an EEPROM read, if there is an error consisting of two or more bits, the ISL94202 sets the ECC_FAIL bit

(ECC_USED = 0). This read contains invalid data.

The error correction is also active during the initial power-on recall of the EEPROM values to the shadow RAM. The circuit

corrects for any one-bit errors. Two-bit errors are not corrected and the contents of the shadow RAM maintain the previous

value.

Internally, the power-on recall circuit uses the ECC_USED and ECC_FAIL bits to determine there is a proper recall before

allowing the device operation to start. However, an external µC cannot use these bits to detect the validity of the shadow RAM

on power-up or determine the use of the error correction mechanism, because the bits automatically reset on the next valid read.

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ISL94202

20. Serial Interface

• The ISL94202 uses a standard I C interface, except the design separates the SDA input and output (SDAI and SDAO)

2

• Separate SDAI and SDAO lines can be tied together and operate as a typical I C bus

• Interface speed is 400kHz, maximum

20.1 Serial Interface Conventions

The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a

transmitter and the receiving device as the receiver. The device controlling the transfer is called the master and the device

being controlled is called the slave. The master always initiates data transfers and provides the clock for both transmit and

receive operations. Therefore, the ISL94202 devices operate as slaves in all applications.

When sending or receiving data, the convention with the most significant bit (MSB) is sent first. Therefore, the first address

bit sent is Bit 7.

20.2 Clock and Data

Data states on the SDA line can change only while SCL is LOW. SDA state changes during SCL HIGH are reserved for

indicating start and stop conditions (see Figure 20.33).

20.3 Start Condition

All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The

device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this

condition has been met (see Figure 20.34).

20.4 Stop Condition

All communications must be terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is

HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop

condition is only issued after the transmitting device has released the bus (see Figure 20.34).

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ISL94202

20. Serial Interface

20.5 Acknowledge

Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or

slave, releases the bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to

acknowledge that it received the eight bits of data (see Figure 20.35).

The device responds with an acknowledge after recognition of a start condition and the correct slave byte. If a write

operation is selected, the device responds with an acknowledge after the receipt of each subsequent eight bits. The device

acknowledges all incoming data and address bytes, except for the slave byte when the contents do not match the device’s

internal slave address.

In the read mode, the device transmits eight bits of data, releases the SDA line, then monitors the line for an acknowledge.

If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data.

The device terminates further data transmissions if an acknowledge is not detected. The master must then issue a stop

condition to return the device to Standby mode and place the device into a known state.

SCL

SDA

DATA

STABLE

CHANGE

STABLE

2

Figure 20.33 Valid Data Changes On I C Bus

SCL

SDA

START

2

STOP

Figure 20.34 I C Start and Stop Bits

SCL FROM

MASTER

1

8

9

DATA OUTPUT

FROM

TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 20.35 Acknowledge Response From Receiver

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ISL94202

20. Serial Interface

20.6 Write Operations

20.6.1 Byte Write

For a byte write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master

access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an

acknowledge and awaits the next eight bits of data. After receiving the eight bits of the Data Byte, the device again responds

with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device

begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so

the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 20.36.

WATCHDOG

TIMER

RESET

S

T

A

R

T

S

T

O

P

SLAVE

BYTE

ADDRESS

DATA

SDA BUS

0 1 0 1 0 0 0 0

A

C

K

A

C

K

A

C

K

ISL94202: SLAVE BYTE = 50H (ADDR = 0)

ISL94202: SLAVE BYTE = 52H (ADDR = 1)

Figure 20.36 Byte Write Sequence

A write to a protected block of memory suppresses the acknowledge bit.

When writing to the EEPROM, write to all addresses of a page without an intermediate read operation or use a page

write command. Each page is four bytes long, starting at Address 0.

20.6.2 Page Write

A page write operation is initiated in the same manner as the byte write operation; but instead of terminating the write

cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt

of each byte, the device will respond with an acknowledge and the address is internally incremented by one. The page

address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to ‘0’ on the same

page. This means that the master can write four bytes to the page starting at any location on that page. If the master

begins writing at Location 2 and loads four bytes, then the first two bytes are written to Locations 2 and 3 and the last

two bytes are written to Locations 0 and 1. Afterwards, the address counter would point to Location 2 of the page that

was just written. If the master supplies more than four bytes of data, then new data overwrites the previous data, one

byte at a time. See Figure 20.37.

Do not write to addresses 58H through 7FH or locations higher than address ABH, since these addresses access registers

that are reserved. Writing to these locations can result in unexpected device operation.

ADDRESS = 0

DATA BYTE 3

ADDRESS = 1

DATA BYTE 4

ADDRESS = 2

DATA BYTE 1

ADDRESS = 3

DATA BYTE 2

ADDRESS POINTER STARTS AND ENDS HERE

Figure 20.37 Writing 4 Bytes to A 4-Byte Page Starting at Location 2

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ISL94202

20. Serial Interface

WATCHDOG TIMER

S

T

A

R

T

S

T

O

P

SLAVE

BYTE

REGISTER

ADDRESS

DATA(1)

DATA(n)

SDA BUS

0 1 0 1 0 0 0 0

A

C

K

A

C

K

A

C

K

A

C

K

ISL94202: SLAVE BYTE = 50H (ADDR = 0)

ISL94202: SLAVE BYTE = 52H (ADDR = 1)

Figure 20.38 Page Write Sequence

20.7 Read Operations

Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave

Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential

Reads.

20.7.1 Current Address Read

Internally the device contains an address counter that maintains the address of the last word read incremented by one.

Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power-up,

the address of the address counter is undefined, requiring a read or write operation for initialization. See Figure 20.39 on

page 71.

Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits

the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge

during the ninth clock and then issues a stop condition.

It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the

master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and

then issue a stop condition.

20.7.2 Random Read

Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address

Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start

condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After

acknowledging receipts of the Word Address Bytes, the master immediately issues another start condition and the Slave

Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit

word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop

condition (see Figure 20.40)

20.7.3 Sequential Read

Sequential reads can be initiated as either a current address read or random address read. The first Data Byte is

transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires

additional data. The device continues to output data for each acknowledge received. The master terminates the read

operation by not responding with an acknowledge and then issuing a stop condition

The data output is sequential, with the data from address n followed by the data from address n+1. The address counter

for read operations increments through all page and column addresses, allowing the entire memory contents to be

serially read during one operation. At the end of the address space the counter “rolls over” to address 0000H and the

device continues to output data for each acknowledge received. See Figure 20.41 for the acknowledge and data transfer

sequence.

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ISL94202

20. Serial Interface

WATCHDOG TIMER RESET

S

T

A

R

T

N

A

C

K

S

T

O

P

SLAVE

BYTE

0 1 0 1 0 0 0 1

SDA BUS

A

C

K

A

C

K

DATA

ISL94202: SLAVE BYTE = 50H (ADDR = 0)

ISL94202: SLAVE BYTE = 52H (ADDR = 1)

Figure 20.39 Current Address Read Sequence

WATCHDOG TIMER RESET

S

T

A

R

T

S

T

A

R

T

N

A

C

K

S

T

O

P

SLAVE

BYTE

SLAVE

BYTE

REGISTER

ADDRESS

SDA BUS

0 1 0 1 0 0 0 0

0 1 0 1 0 0 0 1

A

C

K

A

C

K

A

C

K

A

C

K

DATA

ISL94202: SLAVE BYTE = 50H (ADDR = 0)

ISL94202: SLAVE BYTE = 52H (ADDR = 1)

Figure 20.40 Random Read Sequence

WATCHDOG TIMER RESET

S

T

A

R

T

S

T

A

R

T

N

A

C

K

S

T

O

P

SLAVE

BYTE

SLAVE

BYTE

REGISTER

ADDRESS

SDA BUS

0 1 0 1 0 0 0 0

0 1 0 1 0 0 0 1

A

C

K

A

C

K

A

C

K

A

C

K

DATA

ISL94202: SLAVE BYTE = 50H (ADDR = 0)

ISL94202: SLAVE BYTE = 52H (ADDR = 1)

Figure 20.41 Sequential Read Sequence

20.7.4 EEPROM Access

2

The user is advised not to use page transfers when reading or writing to EEPROM. Only single byte I C transactions

should be used. In addition, “Write” transactions should be separated with a 30ms delay to enable each byte write

operation to complete.

20.7.5 EEPROM Read

The ISL94202 has a special requirement when reading the EEPROM. An EEPROM read operation from the first byte of

a four byte page (locations 0H, 4H, 8H, etc.) initiates a recall of the EEPROM page. This recall takes more than 200µs,

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ISL94202

20. Serial Interface

2

so the first byte may not be ready in time for a standard I C response. It is necessary to read this first byte of every page

two times.

20.7.6 EEPROM Write

The ISL94202 also has a special requirement when writing the EEPROM. An EEPROM write operation to the first byte

of a four byte page (locations 0H, 4H, 8H, etc.) initiates a recall of the EEPROM page. This recall takes more than

2

200µs, so the first byte may not be ready in time for a standard I C response. It is necessary to write this first byte of

every page two times. These “duplicate” writes should be separated with a 30ms delay and followed with a 30ms delay.

Again, only single byte transactions should be used with a 30ms delay between each write operation.

20.8 Synchronizing Microcontroller Operations with Internal Scan

Internal scans occur every 32ms in Normal mode, 256ms in Idle mode and 512ms in Doze mode. The internal scan

normally takes about 1.3ms, with every fourth scan taking about 1.7ms. While the percentage of time taken by the scan is

small, it is long enough that random communications from the microcontroller can coincide with the internal scan. When

the two scans happen at the same time, errors can occur in the recorded values.

2

To avoid errors in the recorded values, the goal is to synchronize external I C transactions so that they only occur during the

device’s Low Power State (see Figure 10.22 on page 43.) To assist in the synchronization, the microcontroller can use the

INT_SCAN bit. This bit is “0” during the internal scan and “1” during the “Low Power State”.

The microcontroller software should look for the INT_SCAN bit to go from a “0” to a “1” to allow the maximum time to

complete read or write operations. This insures that the results reported to the µC are from a single scan and changes made

do not interfere with state machine detection and timing.

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ISL94202

21. Register Protection

The entire EEPROM memory is write protected on initial power-up and during normal operation. An enable byte allows

writing to various areas of the memory array.

The enable byte is encoded, so that a value of ‘0’ in the EEPROM Enable register (89H) enables access to the shadow memory

(RAM), a value of ‘1’ allows access to the EEPROM.

After a read or write of the EEPROM, the microcontroller should reset the EEPROM Enable register value back to

zero to prevent inadvertent writes to the EEPROM and to turn off the EEPROM block to reduce current consumption.

If the microcontroller fails to reset the EEPROM bit and communications to the chip stops, then the Watchdog timer will reset

the EEPROM select bit.

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ISL94202

22. Registers: Summary (EEPROM)

Table 22.13 EEPROM Register Summary

EEPROM (Configured as 32 4-Byte Pages)

Page ADDR

0x

1x

2x

3x

4x

5x

0

Overvoltage Level Overvoltage Delay Minimum CB Charge

Internal

User EEPROM

Timer

Delta

Over-Temperature

Level

Over-Temperature

Level

1

0

2

Overvoltage

recovery

UndervoltageDelay Maximum CB Charge Over-Temp Internal

Timer

Delta

Recovery

Over-Temperature

Recovery

3

4

5

Undervoltage Level Open Wire Timing Cell Balance Charge

On time Under-Temperature

Level

Cell Balance Charge

Sleep Voltage

1

6

7

8

9

A

Undervoltage

Recovery

Discharge

Sleep Delay Timer/

Overcurrent

Timeout Settings,

Discharge Setting

Off Time

Under-Temperature Watchdog Timer

Recovery

OVLO Threshold

UVLO Threshold

Charge overcurrent Minimum CB Discharge

Timeout Settings, Temperature Over-Temperature

Sleep Mode Timer Reserved

CELLS Config

Charge overcurrent Level

Setting

Level

2

3

Short-Circuit

Timeout Settings/

Recovery Settings, Recovery

Short-Circuit

Minimum CB Discharge

Temperature Over-Temperature

Features 1

Features 2

Recovery

B

Setting

C

D

E

F

EOC Voltage Level Minimum CB Volts Maximum CB Discharge

Temperature Under-Temperature

Level Level

Maximum CB Volts Maximum CB Discharge

Temperature Under-Temperature

Recovery Recovery

Reserved

Low Voltage

Charge Level

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ISL94202

23. Registers: Summary (RAM)

Table 23.14 RAM Register Summary

RAM

Page

ADDR

8x

9x

Ax

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Status1

CELL1 Voltage

CELL2 Voltage

CELL3 Voltage

CELL4 Voltage

CELL5 Voltage

CELL6 Voltage

CELL7 Voltage

CELL8 Voltage

iT Voltage

Status2

0

Status3

xT1 Voltage

Status4

Cell Balance

Analog Out

xT2 Voltage

1

2

3

FET Cntl/Override Control Bits

Override Control Bits

Force Ops

VBATT/16 Voltage

VRGO/2 Voltage

14-bit ADC Voltage

Reserved

EE Write Enable

CELLMIN Voltage

CELLMAX Voltage

ISense Voltage

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ISL94202

24. Registers: Detailed (EEPROM)

Table 24.15 EEPROM Register Detail

Bit/

ADDR

F

7

E

6

D

5

C

4

B

3

A

2

9

1

8

0

7

6

5

4

3

2

1

0

Overvoltage Threshold

If any cell voltage is above this threshold voltage for an overvoltage delay time, the

charge FET is turned off.

Default (Hex): 1E2A

(V): 4.25

Charge Detect Pulse Width

These bits set the duration of the

charger monitor pulse width.

OVLB OVLA OVL9 OVL8 OVL7 OVL6 OVL5 OVL4 OVL3 OVL2 OVL1 OVL0

00

01

CPW3

CPW2

CPW1

CPW0

HEXvalue  1.8  8

10

--------------------------------------------------------

Threshold =

0000 = 0ms to

1111 = 15ms; Default = 1ms

4095  3

Overvoltage Recovery

If all cells fall below this overvoltage recovery level, the charge FET is turned on.

Default (Hex): 0DD4

(V): 4.15

02

03

Reserved

OVRB OVRA OVR9 OVR8 OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0

Undervoltage Threshold

If any cell voltage is below this threshold voltage for an undervoltage delay time, the

discharge FET is turned off.

Default (Hex): 18FF

(V):

2.7

Load Detect Pulse Width

These bits set the duration of the

charger monitor pulse width.

UVLB UVLA UVL9

UVL8

UVL7

UVL6

UVL5

UVL4

UVL3

UVL2

UVL1

UVL0

04

05

LPW3

LPW2

LPW1

LPW0

HEXvalue  1.8  8

10

--------------------------------------------------------

0000 = 0 ms to

Threshold =

4095  3

1111 = 15ms; Default = 1ms

Undervoltage Recovery

If all cells rise above this overvoltage recovery level (and there is no load), the

discharge FET is turned on.

Default (Hex): 09FF

(V):

3.0

06

07

Reserved

UVRB UVRA UVR9 UVR8 UVR7 UVR6 UVR5 UVR4 UVR3 UVR2 UVR1 UVR0

Overvoltage Lockout Threshold

If any cell voltage is above this threshold for five successive scans, then the device is in

an overvoltage lockout condition. In this condition, the Charge FET is turned off, the cell

balance FETs are turned off, the OVLO bit is set, and the PSD output is set to active.

Default (Hex): 0E7F

(V): 4.35

08

09

OVLO OVLO OVLO OVLO OVLO OVLO OVLO OVLO OVLO OVLO OVLO OVLO

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Undervoltage Lockout Threshold

If any cell voltage is below this threshold for five successive scans, then the device is in

an undervoltage lockout condition. In this condition, the Discharge FET is turned off and

the UVLO bit is set. The device also powers down (unless overridden).

Default (Hex): 0600

(V):

1.8

0A

0B

UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

End-of-Charge (EOC) Threshold

If any cell exceeds this level, then the EOC output and the EOC bit are set.

Default (Hex): 0DFF

(V):

4.2

0C

0D

Reserved

EOCB EOCA EOC9 EOC8 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0

Low Voltage Charge Level

If the voltage on any cell is less than this level, then the PCFET output turns on instead

of the PC output. To disable this function, set the value to zero or set the PCFETE bit to

0.

Default (Hex): 07AA

(V):

2.3

0E

0F

LVCH LVCH

Reserved

LVCH9 LVCH8 LVCH7 LVCH6 LVCH5 LVCH4 LVCH3 LVCH2 LVCH1 LVCH0

B

A

Overvoltage Delay Time Out

This value sets the time that is required for any cell to be above the overvoltage

threshold before an overvoltage condition is detected.

Default (Hex): 0801

(s):

1

OVDT OVDT OVDT OVDT OVDT OVDT OVDT OVDT OVDT OVDT OVDT OVDT

10

11

B

A

9

8

7

6

5

4

3

2

1

0

00 = µs

Reserved

01 = ms

10 = s

0 to 1024

11 = min

FN8889 Rev.2.00

Mar 8, 2017

Page 76 of 89

ISL94202

Table 24.15 EEPROM Register Detail (Continued)

24. Registers: Detailed (EEPROM)

Bit/

ADDR

F

7

E

6

D

5

C

4

B

3

A

2

9

1

8

0

7

6

5

4

3

2

1

0

Undervoltage Delay Time Out

This value sets the time that is required for any cell to be below the undervoltage

threshold before an undervoltage condition is detected.

0801

Default (Hex):

(s):

1

UVDT UVDT UVDT UVDT UVDT UVDT UVDT UVDT UVDT UVDT UVDT UVDT

12

13

B

A

9

8

7

6

5

4

3

2

1

0

00 = µs

Reserved

01 = ms

10 = s

0 to 1024

11 = min

Open-Wire Timing (OWT)

This value sets the width of the open-wire test pulse for each cell input.

Default (Hex): 0214

(ms):

20

14

15

OWT

9

OWT

8

OWT

7

OWT

6

OWT

5

OWT

4

OWT

3

OWT

2

OWT

1

OWT

0

Reserved

0 = µs

1 = ms

0 to 512

Discharge Overcurrent Time Out/Threshold

Time Out

(ms):

(mV):

160

32

A discharge overcurrent needs to remain for this time period prior to entering a

discharge overcurrent condition. This is a 12-bit value: Lower 10 bits set the time.

Upper bits set the time base.

Default (Hex): 44A0

Threshold

This value sets the voltage across

current-sense resistor that creates a

discharge overcurrent condition.

16

17

OCD2

OCD1

OCD0

OCDT OCDT OCDT OCDT OCDT OCDT OCDT OCDT OCDT OCDT OCDT OCDT

B

A

9

8

7

6

5

4

3

2

1

0

000 = 4mV

001 = 8mV

010 = 16mV

011 = 24mV

100 = 32mV

101 = 48mV

110 = 64mV

111 = 96mV

00 = µs

01 = ms

10 = s

0 to 1024

11 = min

Charge Overcurrent Time Out/Threshold

Time Out

(ms):

(mV):

160

8

A charge overcurrent needs to remain for this time period prior to entering a charge

overcurrent condition. This is a 12-bit value: Lower 10 bits set the time. Upper bits set

the time base.

Default (Hex): 44A0

Threshold

This value sets the voltage across

current-sense resistor that creates a

charge overcurrent condition

18

19

OCC2

OCC1

OCC0

OCCT OCCT OCCT OCCT OCCT OCCT OCCT OCCT OCCT OCCT OCCT OCCT

B

A

9

8

7

6

5

4

3

2

1

0

000 = 1mV

001 = 2mV

010 = 4mV

011 = 6mV

100 = 8mV

101 = 12mV

110 = 16mV

111 = 24mV

00 = µs

01 = ms

10 = s

0 to 1024

11 = min

Discharge Short-Circuit Time Out/Threshold

Time Out

Default (Hex):

(µs):

(mV):

200

128

A short-circuit current needs to remain for this time period prior to entering a short-

circuit condition. This is a 12 bit value:

60C8

Lower 10 bits set the time. Upper bits set the time base

Threshold

This value sets the voltage across

current-sense resistor that creates a

short-circuit condition

1A

1B

SCD2

SCD1

SCD0

SCTB SCTA SCT9 SCT8 SCT7 SCT6 SCT5 SCT4 SCT3 SCT2 SCT1 SCT0

000 = 16mV

001 = 24mV

010 = 32mV

011 = 48mV

100 = 64mV

101 = 96mV

110 = 128mV

111 = 256mV

00 = µs

0 to 1024

01 = ms

10 = s

11 = min

FN8889 Rev.2.00

Mar 8, 2017

Page 77 of 89

ISL94202

Table 24.15 EEPROM Register Detail (Continued)

24. Registers: Detailed (EEPROM)

Bit/

ADDR

F

7

E

6

D

5

C

4

B

3

A

2

9

1

8

0

7

6

5

4

3

2

1

0

Cell Balance Minimum Voltage (CBMIN)

If all cell voltages are less than this voltage, then cell balance stops.

Default (Hex): 0A55

(V):

3.1

1C

1D

CBVL CBVL

Reserved

CBVL9 CBVL8 CBVL7 CBVL6 CBVL5 CBVL4 CBVL3 CBVL2 CBVL1 CBVL0

(V):

B

A

Cell Balance Maximum Voltage (CBMAX)

If all cell voltages are greater than this voltage, then cell balance stops.

Default (Hex): 0D70

4.0

1E

1F

CBVU CBVU CBVU CBVU CBVU CBVU CBVU CBVU CBVU CBVU CBVU CBVU

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Cell Balance Minimum Differential Voltage (CBMINDV)

If the difference between the voltage on CELLN and the lowest voltage cell is less than

this voltage, then cell balance for CELLN stops.

Default (Hex): 0010

(mV):

20

21

CBDL CBDL CBDL CBDL CBDL CBDL CBDL CBDL CBDL CBDL CBDL CBDL

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Cell Balance Maximum Differential Voltage (CBMAXDV)

If the difference between the voltage on CELLN and the lowest voltage cell is greater

than this voltage, then cell balance for CELLN stops and the CELLF flag is set.

Default (Hex): 01AB

(mV):

500

22

23

CBDU CBDU CBDU CBDU CBDU CBDU CBDU CBDU CBDU CBDU CBDU CBDU

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Cell Balance On Time (CBON)

Cell balance is on for this set amount of time, unless another condition indicates that

there should be no cell balance. This is a 12-bit value: Lower 10 bits set the time. Upper

2 bits set the time base.

Default (Hex): 0802

CBON

(s):

2

24

25

CBON CBON CBON CBON CBON CBON CBON

TB TA T9 T8 T7 T6 T5

CBON CBON CBON CBON

T3 T2 T1 T0

T

4

Reserved

00 = µs

01 = ms

10 = s

0 to 1024

11 = min

Cell Balance Off Time (CBOFF)

Cell balance is off for the set amount of time. This is a 12-bit value: Lower 10 bits set

the time. Upper 2 bits set the time base.

Default (Hex): 0802

(s):

2

CBOF CBOF CBOF CBOF CBOF CBOF CBOF CBOF CBOF CBOF CBOF CBOF

TB TA T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

26

27

00 = µs

Reserved

01 = ms

10 = s

0 to 1024

11 = min

Cell Balance Minimum Temperature Limit (CBUTS)

If the External Temperature 1 or the External Temperature 2 (XT2M = 0) is greater than

this voltage, then cell balance stops. The voltage is based on recommended external

components (see Figure 10.26 on page 50).

(V): 1.344

(°C): -10

Default (Hex): 0BF2

28

29

CBUT CBUT CBUT CBUT CBUT CBUT CBUT CBUT CBUT CBUT CBUT CBUT

SB SA S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Reserved

Cell Balance Minimum Temperature Recovery Level (CBUTR)

If the External Temperature 1 and the External Temperature 2 (XT2M = 0) all recover

and fall below this voltage, then cell balance can resume (all other conditions OK). The

voltage is based on recommended external components (see Figure 10.26 on

page 50).

(V): 1.19

(°C): +5

Default (Hex): 0A93

2A

2B

CBUT CBUT CBUT CBUT CBUT CBUT CBUT CBUT CBUT CBUT CBUT CBUT

RB RA R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

Reserved

Cell Balance Maximum Temperature Limit (CBOTS)

If the External Temperature 1 or the External Temperature 2 (XT2M = 0) is less than

this voltage, then cell balance stops. The voltage is based on recommended external

components (see Figure 10.26 on page 50).

(V): 0.530

(°C): +55

Default (Hex): 04B6

2C

2D

CBOT CBOT CBOT CBOT CBOT CBOT CBOT CBOT CBOT CBOT CBOT CBOT

SB SA S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Reserved

Cell Balance Maximum Temperature Recovery Level (CBOTR)

If the External Temperature 1 and the External Temperature 2 temperature (XT2M = 0)

all recover and rise above this voltage, then cell balance can resume (all other

conditions OK). The voltage is based on recommended external components (see

Figure 10.26 on page 50).

(V): 0.590

(°C): +50

Default (Hex): 053E

2E

2F

CBOT CBOT CBOT CBOT CBOT CBOT CBOT CBOT CBOT CBOT CBOT CBOT

RB RA R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

Reserved

For All Temperature Limits, TGain bit = 0, Temperature Gain = 2

FN8889 Rev.2.00

Mar 8, 2017

Page 78 of 89

ISL94202

Table 24.15 EEPROM Register Detail (Continued)

24. Registers: Detailed (EEPROM)

Bit/

ADDR

F

7

E

6

D

5

C

4

B

3

A

2

9

1

8

0

7

6

5

4

3

2

1

0

Charge Over-Temperature Voltage

If External Temperature 1 or the External Temperature 2 is less than this voltage, then

the charge FET is turned off and the COT bit is set. The voltage is based on

recommended external components (see Figure 10.26 on page 50).

(V): 0.530

(°C): +55

Default (Hex): 04B6

30

31

COTS COTS COTS COTS COTS COTS COTS COTS COTS COTS COTS COTS

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Charge Over-Temperature Recovery Voltage

If External Temperature 1 or the External Temperature 2 rise above this setting, then

the charge FET is turned on and the COT bit is reset (unless overrides are in place).

The voltage is based on recommended external components (see Figure 10.26 on

page 50).

(V): 0.590

(°C): +50

Default (Hex): 053E

32

33

COTR COTR COTR COTR COTR COTR COTR COTR COTR COTR COTR COTR

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Charge Under-Temperature Voltage

If External Temperature 1 or the External Temperature 2 is greater than this voltage,

then the charge FET is turned off and the CUT bit is set. The voltage is based on

recommended external components (see Figure 10.26 on page 50).

(V): 1.344

(°C): -10

Default (Hex): 0BF2

34

35

CUTS CUTS CUTS CUTS CUTS CUTS CUTS CUTS CUTS CUTS CUTS CUTS

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Charge Under-Temperature Recovery Voltage

If External Temperature 1 or the External Temperature 2 fall below this setting, then the

charge FET is turned on and the CUT bit is reset (unless overrides are in place). The

voltage is based on recommended external components (see Figure 10.26 on

page 50).

(V): 1.190

(°C): +5

Default (Hex): 0A93

36

37

CUTR CUTR CUTR CUTR CUTR CUTR CUTR CUTR CUTR CUTR CUTR CUTR

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Discharge Over-Temperature Voltage

If External Temperature 1 or the External Temperature 2 is less than this voltage, then

the discharge FET is turned off and the DOT bit is set. The voltage is based on

recommended external components (see Figure 10.26 on page 50).

(V): 0.530

(°C): +55

Default (Hex):

4B6

38

39

DOTS DOTS DOTS DOTS DOTS DOTS DOTS DOTS DOTS DOTS DOTS DOTS

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Discharge Over-Temperature Recovery Voltage

If External Temperature 1 or the External Temperature 2 rise above this setting, then

the discharge FET is turned on and the DOT bit is reset (unless overrides are in place).

The voltage is based on recommended external components (see Figure 10.26 on

page 50).

(V): 0.590

(°C): +50

Default (Hex): 053E

3A

3B

DOTR DOTR DOTR DOTR DOTR DOTR DOTR DOTR DOTR DOTR DOTR DOTR

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Discharge Under-Temperature Voltage

If External Temperature 1 or the External Temperature 2 is greater than this voltage,

then the discharge FET is turned off and the DUT bit is set. The voltage is based on

recommended external components (see Figure 10.26 on page 50).

(V): 1.344

(°C): -10

Default (Hex): 0BF2

3C

3D

DUTS DUTS DUTS DUTS DUTS DUTS DUTS DUTS DUTS DUTS DUTS DUTS

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Discharge Under-Temperature Recovery Voltage

If External Temperature 1 or the External Temperature 2 fall below this setting, then the

discharge FET is turned on and the DUT bit is reset (unless overrides are in place). The

voltage is based on recommended external components (see Figure 10.26 on

page 50).

(V): 1.190

(°C): +5

Default (Hex): 0A93

3E

3F

DUTR DUTR DUTR DUTR DUTR DUTR DUTR DUTR DUTR DUTR DUTR DUTR

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Internal Over-Temperature Voltage

If the internal temperature is greater than this voltage, then all FETs are turned off and

the IOT bit is set.

Default (Hex): 67CH

(V): 0.73

(°C): +115

40

41

IOTS

B

IOTS

A

Reserved

IOTS 9 IOTS 8 IOTS 7 IOTS 6 IOTS 5 IOTS 4 IOTS 3 IOTS 2 IOTS 1 IOTS 0

Internal Over-Temperature Recovery Voltage

When the internal temperature voltage drops below this level, then the FETs can be

turned on again and the IOT bit is reset on the next µC read.

Default (Hex): 621H

(V): 0.69

(°C): +95

42

43

IOTR

B

IOTR

A

Reserved

IOTR 9 IOTR 8 IOTR 7 IOTR 6 IOTR 5 IOTR 4 IOTR 3 IOTR 2 IOTR 1 IOTR 0

Sleep Level Voltage

If any cell voltage is below this threshold voltage for a sleep delay time, the device goes

into the Sleep mode.

Default (Hex): 06AA

(V):

2.0

44

45

Reserved

SLLB

SLLA SLL 9 SLL 8 SLL 7 SLL 6 SLL 5 SLL 4 SLL 3 SLL 2 SLL 1 SLL 0

FN8889 Rev.2.00

Mar 8, 2017

Page 79 of 89

ISL94202

Table 24.15 EEPROM Register Detail (Continued)

24. Registers: Detailed (EEPROM)

Bit/

ADDR

F

7

E

6

D

5

C

4

B

3

A

2

9

1

8

0

7

6

5

4

3

2

1

0

Sleep Delay Timer/Watchdog Timer

Sleep Delay

Sleep

WDT

(s)

1

31

This value sets the time that is required for any cell to be below the sleep voltage

threshold before the device enters the Sleep mode. Lower 10 bits set the time. Upper 1

bit sets the time base.

Default (Hex): FC0F

Watchdog Timer (WDT)

Time allowed the microcontroller between I C

2

46

47

slave byte writes to the ISL94202 after setting

any override bit.

WDT4

WDT3

WDT2

WDT1

WDT0 SLTA

SLT9

SLT8

SLT7

SLT6

SLT5

SLT4

SLT3

SLT2

SLT1

SLT0

00 = µs

01 = ms

10 = s

0 to 31 seconds

0 to 511

11 = min

Sleep Mode Timer/Cell Configuration

Mode Timer

Time required to enter Sleep mode from the Doze mode when no current is detected.

Idle/

Doze:

Sleep

Mode

(min)

Cells

15

240

3

Default (Hex): 83FF

Cell Configuration

Only these combinations are acceptable. Any other combination will prevent

any FET from turning on.

CELL8 CELL7 CELL6 CELL5 CELL4 CELL3 CELL2 CELL1 MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0

48

49

8 7 6 5 4 3 2 1

1 0 0 0 0 0 1 1

1 1 0 0 0 0 1 1

1 1 0 0 0 1 1 1

1 1 1 0 0 1 1 1

1 1 1 0 1 1 1 1

1 1 1 1 1 1 1 1

NUMBER OF CELLS

3 Cells connected

4 Cells connected

5 Cells connected

6 Cells connected

7 Cells connected

8 Cells connected

Idle and Doze Mode:

[MOD3:0] = 0 to 15 Minutes

[MOD7:4] = 0 to 240 Minutes

Sleep Mode

Example:

Value = 0101 1010

Idle/Doze = 10 minutes

Sleep = 80 minutes

FN8889 Rev.2.00

Mar 8, 2017

Page 80 of 89

ISL94202

24. Registers: Detailed (EEPROM)

Table 24.16 EEPROM Register Detail (Feature Controls)

Bit/

ADDR

7

6

5

4

3

2

1

0

PCFETE

Precharge

FET Enable

XT2M

xTemp 2 Mode

Control

OWPSD

Open-Wire

PSD

CFPSD

CELLF PSD

DOWD

Disable

Open-Wire

Scan

1 =

TGain

External Temp

Gain

1 =

Precharge

FET output

turns on

1 =

Responds

automatically

to the input

Open Wire

1 =

xT2 monitors

FETtemp. Cell

balance

outputs are not

shut off when

xT2

temperature

exceeds Cell

Balance limits

0 =

xT2 monitors

cell temp.

(Normal

Activates PSD

output when a

“Cell Fail”

condition

instead of the 1 =

1 =

CFET output

when any of

the cell

voltages are

below the

under the

LVCHG

threshold.

0 =

Precharge

FET is not

used

Disable the

input open-

Gain of iT, xT1 Reserved, this

and xT2 inputs bit must be 0.

is 1x.

0 =

Gain of iT, xT1

and xT2 inputs

is 2x.

4A

Reserved

condition AND

occurs.

wire detection sets PSD.

0 =

scan

0 =

Enable the

input open-

0 =

Does NOT

activate PSD

output when a

cell fails

condition

occurs.

Responds

automatically

to the input

wire detection Open Wire

scan

condition and

DOES NOT

set PSD.

operation.)

DFODUV

DFET on

during UV

(Charging)

CFODOV

CFET on

CBDD

CB during

Discharge

CBDC

CB during

Charge

UVLOPD

during OV

CB_EOC

Enable CBAL

during EOC

Enable UVLO

(Discharging)

Power-Down

1 =

Do balance

during

discharge

0 =

No balance

during

discharge

When both

CBDD and

CBDC equal

“0”, cell

1 =

Do balance

during charge while the pack while the pack

1 =

Keep DFET on Keep CFET on

1 =

The device

powers down

when

detecting an

UVLO

condition.

0 =

When a UVLO

condition is

detected, the

device

Cell balance

occurs during

EOC condition

regardless of

current

is charging,

regardless of

the cell

is discharging,

regardless of

the cell

0 =

No balance

4B

Reserved

during charge voltage. This

minimizes

voltage. This

minimizes

direction.

0 =

When both

CBDD and

CBDC equal

“0”, cell

DFET power

dissipation

during UV,

CFET power

dissipation

during OV,

Cell balance

turns off during

EOC if there is

no current

flowing.

when the pack when the pack

balance is

turned off.

balance is

turned off.

is charging

0 =

is discharging

0 =

remains

powered.

Normal DFET Normal CFET

operation. operation.

4C

4F

Reserved

50

57

User EEPROM

Available to the user (Note: There is no shadow memory associated with these registers).

FN8889 Rev.2.00

Mar 8, 2017

Page 81 of 89

ISL94202

25. Registers: Detailed (RAM)

Table 25.17 RAM Register Detail (Status and Control)

Bit/

ADDR

7

6

5

4

3

2

1

0

COT

Charge

Over-Temp

CUT

Charge

Under-Temp

DUT

Discharge

Under-Temp

DOT

Discharge

Over-Temp

80

(Read

only)

UVLO

Undervoltage

Lockout

OVLO

Overvoltage

Lockout

UV

OV

Overvoltage

Undervoltage

An external

thermistor

shows the

temp is higher

than the

maximum

charge temp

limit.

An external

thermistor

An external

thermistor

showsthetemp showsthetemp

is lower than

the minimum

discharge temp discharge temp

An external

thermistor

These

bits are

set and

reset by

the

At least one

cell is below

the

undervoltage undervoltage

lockout

At least one cell

is above the

overvoltage

lockout

At least one

cell has an

At least one cell

has an

overvoltage

condition.

showsthetemp

is lower than

the minimum

charge temp

limit.

is higher than

the maximum

condition.

threshold.

device.

threshold.

limit.

CELLF

81

Cell Fail

(Read

only)

DOC

Discharge

Overcurrent

IOT

Internal

Over-Temp

EOCHG

End of charge

OPEN

Open wire

DSC

Discharge

Short-Circuit

COC

Charge

Overcurrent

Indicates that

there is more

than the

maximum

allowable

These

bits are

set and

reset by

the

Reserved

Excessive

Discharge

current

The internal

sensor indicates

an over-temp

condition.

End of charge

voltage

reached.

An open input

circuit is

detected.

Short-circuit

current

detected.

Excessive

Charge current

detected.

voltage

detected.

device

difference

between cells.

CH_PRSNT

LD_PRSNT

Chrgr Present Load Present

LVCHG

Low Voltage

Charge

ECC_FAIL

82

(Read

only)

DCHING

Discharging

CHING

Charging

EEPROMError ECC_USED

Correct Fail EEPROMError

Correct

EEPROM error

correction

failed. Two bits correction

failed, error not used. One bit

corrected.

Previous value corrected.

retained.

Set to “1”

during COC,

Set to “1” during

DOC or DSC,

INT_SCAN

Internal Scan

while charger is while load

At least one cell In-Progress

Indicates that a Indicates that a

attached.

These voltage <

bits are LVCHG

set and threshold. If

reset by set, PCFET

the turns on

discharge

current is

detected.

Charge current is flowing into

is flowing out of the pack.

the pack.

charge current

is detected.

Charge current

EEPROM error

(CHMON >

threshold.)

(LDMON <

threshold.)

When this bit

is “0” for the

duration of the

internal scan.

If µCLMON = 0, If µCCMON = 0,

bit resets bit resets

automatically. If automatically. If

µCLMON = 1, µCCMON = 1,

bit resets by µC bit resets by µC

read of register. read of register.

failed, bit error

device instead of

CFET.

83

IN_SLEEP

CBUV

CBOV

CBUT

CBOT

(Read

only)

In Sleep Mode

Cell Balance

Undervoltage

Cell Balance

Overvoltage

Cell Balance

Under-Temp

Cell Balance

Over-Temp

IN_DOZE

In Doze mode In Idle Mode

IN_IDLE

No scans.

RGO remains

on, VREF off.

Monitors for a

charger or

load

These

All cell voltages All cell voltages xT1 or xT2

< the minimum > the maximum indicates temp indicates temp >

allowable cell allowable cell < allowable cell allowable cell

balance

voltage

threshold.

xT1 or xT2

Reserved

bits are

Scans every

512ms

Scans every

256ms

set and

reset by

the

balance

voltage

threshold.

balance low

temperature

threshold

balance high

temperature

threshold

device

connection.

Cell balance FET control bits

These bits control the cell balance when the external controller

overrides the internal cell balance operation.

84

(R/W)

CB8ON

CB7ON

CB6ON

CB5ON

CB4ON

CB3ON

CB2ON

CB1ON

If µCCBAL = 1, CBAL_ON = 1 and CBnON bit = 1 the cell balance FET is on.

If µCCBAL = 0, CBAL_ON = 0 or CBnON bit = 0 the cell balance FET is off.

FN8889 Rev.2.00

Mar 8, 2017

Page 82 of 89

ISL94202

Table 25.17 RAM Register Detail (Status and Control) (Continued)

25. Registers: Detailed (RAM)

Bit/

ADDR

7

6

5

4

3

2

1

0

Analog MUX control bits

Voltage monitored by ADC when microcontroller overrides the

internal scan operation.

Current Gain Setting

Current gain set when current is monitored by ADC. Only used

when microcontroller overrides the internal scan.

ADC Conversion Start

ADCSTRT

CG1

CG1 0 Gain

CG0

AO3

AO2

AO1

AO0

85

(R/W)

Ext µC sets

this bit to 1 to

start a

AO3 2 1 0

0 0 0 0 OFF

AO3 2 1 0

1 0 0 0 VC8

1 0 0 1 Pack current

1 0 1 0 VBAT/16

1 0 1 1 RGO/2

1 1 0 0 xT1

1 1 0 1 xT2

1 1 1 0 iT

1 1 1 1 OFF

0 0 x50

0 1 x5

1 0 x500

1 1 x500

0 0 0 1 VC1

0 0 1 0 VC2

0 0 1 1 VC3

0 1 0 0 VC4

0 1 0 1 VC5

0 1 1 0 VC6

0 1 1 1 VC7

conversion

Reserved

LMON_EN

Load monitor Clear charge

CLR_ERR

CLR_LERR

Clear load error

PCFET

Pre-charge

FET

CFET

Charge FET

CMON_EN

Chargemonitor

enable

DFET

Discharge FET

enable

error

PSD

Pack shut

down

1 = Resets load

monitor error

condition.

This bit is

automatically

cleared.

Only active

when

µCCMON = 1

1 = DFET on

0 = DFET off

Bit = 0 if DOC or

DSC unless the

automatic

response is

disabled by

µCFET bit. (4)

1 = Load

monitor on

0 = Load

1 = Resets

charge monitor

error condition.

This bit is

automatically

cleared.

1 = PCFET on 1 = CFET on

0 = PCFET off 0 = CFET off

Bit = 0 if DOC Bit = 0 if COC,

or DSC, unless unless the

the automatic automatic

response is

disabled by

µCFET bit. (4) µCFET bit. (4)

1 = Charger

monitor on

0 = Charger

monitor off.

Only active

when

86

(R/W)

monitor off

1 = PSD on

0 = PSD off

response is

disabled by

Only active

when

µCLMON = 1 µCCMON = 1

Only active

when

µCCMON = 1

µCCBAL

µCFET

OW_STRT

µCSCAN

µC does scan

µC does cell

µC does FET

balance

µCLMON

µC does load

monitor

µCCMON

µC does

charger mon

Open wire start

CBAL_ON

Cell balance On

control

1 = Does one

1 = No auto

1 = Internal

1 = FETs

open-wire scan 1 = (CBnON =1)

(bit auto reset outputs ON

to 0)

0 = No scan

Only active if

DOWD = 1 or µCCBAL= 1.

µCSCAN = 1

87

(R/W)

balance

scan. System

controlled by

µC.

0 = Normal

scan

Reserved

controlled by

disabled. µC

external µC.

manages cell

0 = Norm

1 = Load

monitor on

0 = Load

monitor off

(7)

1 = Charge

monitor on

0 = Charge

monitor off

(7)

0 = Cell bal

outputs OFF

Only active if

balance

automaticFET

0 = internal

control (7),

balance

(7), (99)

(10)

enabled. (7)

PDWN

SLEEP

DOZE

IDLE

Power-Down

Set Sleep

Set Doze

Set Idle

88

(R/W)

1 =

1 = Put device 1 = Put device 1 = Put device

Reserved

Power-down

the device.

0 = Normal

operation

into Sleep

mode.

0 = Normal

operation

into Doze

mode.

0 = Normal

operation

into Idle

mode 0 =

Normal

operation.

EEPROM Enable

EEEN

89

(R/W)

Reserved. These bits should be zero.

0 = RAM access

1 = EEPROM

access

FN8889 Rev.2.00

Mar 8, 2017

Page 83 of 89

ISL94202

25. Registers: Detailed (RAM)

Table 25.18 RAM Register Detail (Monitored Voltages)

Bit/

ADDR

F

7

E

6

D

5

C

4

B

3

A

2

9

1

8

0

7

6

5

4

3

2

1

0

Cell Minimum Voltage

This is the voltage of the cell with the minimum voltage.

HEXvalue  1.8  8

10

--------------------------------------------------------

8A

8B

4095  3

CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM

INB INA IN9 IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0

Reserved

Cell Maximum Voltage

This is the voltage of the cell with the maximum voltage.

HEXvalue  1.8  8

10

--------------------------------------------------------

8C

8D

4095  3

CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM CELLM

Reserved

AXB

AXA

AX9

AX8

AX7

AX6

AX5

AX4

AX3

AX2

AX1

AX0

Pack Current

This is the current flowing into or out of the pack.

HEXvalue  1.8

10

4095  Gain  SenseR

--------------------------------------------------------

8E

8F

Polarity

identified by CHING and DCHING bits.

Reserved

Cell 1 Voltage

This is the voltage of CELL1.

ISNSB ISNSA ISNS9 ISNS8 ISNS7 ISNS6 ISNS5 ISNS4 ISNS3 ISNS2 ISNS1 ISNS0

HEXvalue  1.8  8

10

--------------------------------------------------------

90

91

4095  3

CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1 CELL1

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Cell 2 Voltage

This is the voltage of CELL2.

HEXvalue  1.8  8

10

--------------------------------------------------------

92

93

4095  3

CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2 CELL2

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Cell 3 Voltage

This is the voltage of CELL3.

HEXvalue  1.8  8

10

--------------------------------------------------------

94

95

4095  3

CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3 CELL3

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Cell 4 Voltage

This is the voltage of CELL4.

HEXvalue  1.8  8

10

--------------------------------------------------------

96

97

4095  3

CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4 CELL4

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Cell 5 Voltage

This is the voltage of CELL5.

HEXvalue  1.8  8

10

--------------------------------------------------------

98

99

4095  3

CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5 CELL5

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Cell 6 Voltage

This is the voltage of CELL6.

HEXvalue  1.8  8

10

--------------------------------------------------------

9A

9B

4095  3

CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6 CELL6

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Cell 7 Voltage

This is the voltage of CELL7.

HEXvalue  1.8  8

10

--------------------------------------------------------

9C

9D

4095  3

CELL7 CELL7 CELL7 CELL7 CELL7 CELL7 CELL7 CELL7 CELL7 CELL7 CELL7 CELL7

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

FN8889 Rev.2.00

Mar 8, 2017

Page 84 of 89

ISL94202

Table 25.18 RAM Register Detail (Monitored Voltages)(Continued)

25. Registers: Detailed (RAM)

Bit/

ADDR

F

7

E

6

D

5

C

4

B

3

A

2

9

1

8

0

7

6

5

4

3

2

1

0

Cell 8 Voltage

This is the voltage of CELL8.

HEXvalue  1.8  8

10

--------------------------------------------------------

9E

9F

4095  3

CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8 CELL8

Reserved

B

A

9

8

7

6

5

4

3

2

1

0

Internal Temperature

This is the voltage reported by the ISL94202 internal temperature sensor.

HEXvalue  1.8

10

A0

A1

-----------------------------------------------

4095

Reserved

iTB

iTA

iT9

iT8

iT7

iT6

iT5

iT4

iT3

iT2

iT1

iT0

External Temperature 1

This is the voltage reported by an external thermistor divider on the xT1

pin.

HEXvalue  1.8

10

A2

A3

-----------------------------------------------

4095

Reserved

xT1B xT1A xT19 xT18 xT17 xT16 xT15 xT14 xT13 xT12

xT11

xT10

External Temperature 2

This is the voltage reported by an external thermistor divider on the xT2

pin.

HEXvalue  1.8

10

A4

A5

-----------------------------------------------

4095

Reserved

VBATT Voltage

This is the voltage of Pack.

xT2B xT2A xT29 xT28 xT27 xT26 xT25 xT24 xT23 xT22 xT21 xT20

HEXvalue  1.8  32

10

A6

A7

-----------------------------------------------------------

4095

Reserved

VBB

VBA

VB9

VB8

VB7

VB6

VB5

VB4

VB3

VB2

VB1

VB0

VRGO Voltage

This is the voltage of ISL94202 2.5V regulator.

HEXvalue  1.8  2

10

A8

A9

--------------------------------------------------------

4095

Reserved

RGOB RGOA RGO 9 RGO 8 RGO 7 RGO 6 RGO 5 RGO 4 RGO 3 RGO 2 RGO 1 RGO 0

FN8889 Rev.2.00

Mar 8, 2017

Page 85 of 89

ISL94202

Table 25.18 RAM Register Detail (Monitored Voltages)(Continued)

25. Registers: Detailed (RAM)

Bit/

ADDR

F

7

E

6

D

5

C

4

B

3

A

2

9

1

8

0

7

6

5

4

3

2

1

0

14-Bit ADC Voltage

This is the calibrated voltage out of the ISL94202 ADC. In normal scan

mode, this value is not usable, because it cannot be associated with a

specific monitored voltage. However, when the µC takes over the scan

operations, this value can be useful. This is a 2’s complement number.

HEXvalue – 16384 1.8

10

--------------------------------------------------------------------------------------------

if..HEXvalue  8191 

10

8191

AA

AB

HEXvalue  1.8

10

--------------------------------------------

else 

8191

ADC ADC ADC

ADC

A

ADC

9

ADC

8

ADC

7

ADC

6

ADC

5

ADC

4

ADC

3

ADC

2

ADC

1

ADC

0

Reserved

Notes:

D

C

B

1. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition

exists.

2. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to RAM addresses, write a reserved bit

with the value “0”. Do not write to reserved registers at addresses 4CH through 4FH, 58H through 7FH, or ACH through FFH.

Ignore reserved bits that are returned in a read operation.

3. The IN_SLEEP bit is cleared on initial power up, by the CHMON pin going high or by the LDMON pin going low.

4. When the automatic responses are enabled, these bits are automatically set and reset by hardware when any conditions indicate.

When automatic responses are over-ridden, an external microcontroller I²C write operation controls the respective FET and a read

of the register returns the current state of the FET drive output circuit (though not the actual voltage at the output pin).

5. Setting EEEN to 0 prior to a read or write to the EEPROM area results in a read or write to the shadow memory. Setting EEEN to

“1” prior to a read or write from the EEPROM area results in a read or write from the non-volatile array locations.

6. Writes to EEPROM registers require that the EEEN bit be set to “1” and all other bits in EEPROM enable register set to “0” prior to

the write operation.

7. This bit is reset when the Watchdog timer is active and expires.

8. The memory is configured as eight pages of 16 bytes. The I²C can perform a “page write” to write all values on one page in a single

cycle.

9. Setting this bit to “1” disables all internal voltage and temperature scans. When set to “1”, the external µC needs to process all

overvoltage, undervoltage, over-temp, under temp and all cell balance operations.

10.Short-Circuit, Open-Wire, Internal Over Temperature, OVLO and UVLO faults, plus Sleep, and FETSOFF conditions override the

µCFET control bit and automatically force the appropriate power FETs off.

FN8889 Rev.2.00

Mar 8, 2017

Page 86 of 89

ISL94202

26. Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit

our website to make sure you have the latest revision.

Date

Revision

Change

Updated entire datasheet to new standards.

Mar 7, 2017

FN8889.2

Updated Applications section on page 1

Added Table #1.1 on page 4.

Ordering Information table on page 4, updated Note 1 to include tape and reel options and

quantities.

Dec 12, 2016

Oct 24, 2016

FN8889.1

FN8889.0

ESD Rating on page 8, Human Body Model (Tested per JESD22-A114F) changed from:

2kV to: 1.5kV

Initial Release.

FN8889 Rev.2.00

Mar 8, 2017

Page 87 of 89

ISL94202

27. Package Outline Drawing

For the most recent package outline drawing, see L48.6x6

L48.6x6

48 Lead Thin Quad Flat No-Lead Plastic Package

Rev 2, 7/14

4X

4.4

6.00± 0.05

0.40

44X

A

6

B

PIN #1 INDEX AREA

48

37

6

1

36

PIN 1

INDEX AREA

4 .40 ± 0.15

25

12

0.15

(4X)

13

24

0.10 M C A B

0.05 M C

TOP VIEW

48X 0.45 ± 0.10

4

48X 0.20

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

C

MAX 0.80

BASE PLANE

SEATING PLANE

0.08

(44 X 0.40)

( 5. 75 TYP)

(

C

SIDE VIEW

4. 40)

5

0 . 2 REF

C

(48X 0 . 20)

(48X 0 . 65)

0 . 00 MIN.

0 . 05 MAX.

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance: Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN8889 Rev.2.00

Mar 8, 2017

Page 88 of 89

ISL94202

28. About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's

products address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end

consumer markets.

For the most updated datasheet, application notes, related documentation, and related parts, see the respective product

information page found at www.intersil.com.

For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support.

All trademarks and registered trademarks are the property of their respective owners.

FN8889 Rev.2.00

Mar 8, 2017

Page 89 of 89


型号：	ISL94202IRTZ
厂家：	RENESAS TECHNOLOGY CORP
描述：	Series Charge/Discharge Path 3-to-8 Cell Li-Ion Battery Pack Monitor 电池
文件：	总89页 (文件大小：3378K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL94202IRTZ [RENESAS]

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