ISL95712HRZ_技术文档

DATASHEET

ISL95712

FN8566

Rev 1.00

November 2, 2015

Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

The ISL95712 is fully compliant with AMD Fusion™ SVI 2.0 and

Features

provides a complete solution for microprocessor and graphics

• Supports AMD SVI 2.0 serial data bus interface and PMBus

- Serial VID clock frequency range 100kHz to 25MHz

• Dual output controller with 12V integrated core gate drivers

• Precision voltage regulation

processor core power. The ISL95712 controller supports two

Voltage Regulators (VRs) for Core and Northbridge outputs. The

Core VR can be configured for 4-, 3-, 2-, or 1-phase operation while

the Northbridge VR supports 3-, 2- or 1-phase configurations for

maximum flexibility. The two VRs share a serial control bus to

communicate with the AMD CPU and achieve lower cost and

smaller board area compared with two-chip solutions.

- 0.5% system accuracy over-temperature

- 0.5V to 1.55V in 6.25mV steps

- Enhanced load line accuracy

The PWM modulator is based on Intersil’s Robust Ripple

Regulator R3™ Technology. Compared to traditional modulators,

the R3™ modulator can automatically change switching

frequency for faster transient settling time during load transients

and improved light load efficiency.

• Supports multiple current sensing methods

- Lossless inductor DCR current sensing

- Precision resistor current sensing

• Programmable 1-, 2-, 3- or 4-phase for the core output and

1- , 2- or 3-phase for the Northbridge output

The ISL95712 has several other key features. Both outputs

support DCR current sensing with a single NTC thermistor for

DCR temperature compensation or accurate resistor current

sensing. They also utilize remote voltage sense, adjustable

switching frequency, OC protection and power-good indicators.

• Adaptive body diode conduction time reduction

• Superior noise immunity and transient response

• Output current and voltage telemetry

• Differential remote voltage sensing

Applications

• AMD Fusion CPU/GPU core power

• High efficiency across entire load range

• Programmable slew rate

• Desktop computers

• Programmable VID offset and droop on both outputs

• Programmable switching frequency for both outputs

• Excellent dynamic current balance between phases

• Protection: OCP/WOC, OVP, PGOOD and thermal monitor

• Small footprint 52 Ld 6x6 QFN package

- Pb-free (RoHS compliant)

Performance

100

1.6

CORE

90

1.5

NORTHBRIDGE

80

70

60

50

40

30

20

10

0

CORE

1.4

CORE

(PSI1)

1.3

NORTHBRIDGE

1.2

1.1

DAC = 1.500V

80 90 100 110

1.0

0

10

20

30

40

50

60

70

80

90 100 110

0

10

20

30

40

50

60

70

LOAD CURRENT (A)

FIGURE 1. EFFICIENCY vs LOAD

FIGURE 2. V vs LOAD

OUT

FN8566 Rev 1.00

November 2, 2015

Page 1 of 35

ISL95712

Table of Contents

Simplified Application Circuit for High Power CPU Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Diode Throttling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Differential Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Resistor Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

VID-on-the-Fly Slew Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AMD Serial VID Interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Pre-PWROK Metal VID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SVI Interface Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SVI Data Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SVI Bus Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Dynamic Load Line Slope Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Dynamic Offset Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Telemetry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PMBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Overcurrent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Current-Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Overvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Thermal Monitor [NTC, NTC_NB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Fault Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Interface Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Thermal Monitor Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

FN8566 Rev 1.00

November 2, 2015

Page 2 of 35

ISL95712

Simplified Application Circuit for High Power CPU Core

+12V

BOOT_NB

NB_PH1

NB_PH2

ISEN1_NB

ISEN2_NB

UGATE_NB

Ri

VNB1

VNB2

ISUMN_NB

PHASE_NB

LGATE_NB

Cn

NTC

NB_PH1

VNB1

NB_PH1

NB_PH2

ISUMP_NB

COMP_NB

FB_NB

VNB

PROG

+12V

*

PWM2_NB

*OPTIONAL

VNB_SENSE

VSEN_NB

IMON_NB

NB_PH2

VNB2

NTC_NB

I2DATA

+12V

I2CLK

THERMAL INDICATOR

VR_HOT_L

PWM4

PWROK

SVT

VO4

PH4

µP

SVD

SVC

VDDIO

IMON

+12V

NTC

PWM3

COMP

ISL95712

VO3

PH3

FB

*

+12V

BOOT2

*OPTIONAL

VSEN

RTN

UGATE2

PHASE2

VCORE

VCORE_SENSE

PH1

PH2

ISEN1

ISEN2

ISEN3

LGATE2

PH2

VO2

PH3

PH4

ISEN4

ISUMN

ISUMP

+12V

BOOT1

Ri

UGATE1

PHASE1

VO1

VO2

Cn

NTC

VO3

VO4

LGATE1

PH1

VO1

FIGURE 3. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING

FN8566 Rev 1.00

November 2, 2015

Page 3 of 35

ISL95712

Pin Configuration

ISL95712

(52 LD QFN)

TOP VIEW

47

52 51 50 49 48

46 45 44 43 42 41 40

1

39 PWM4

38

ISEN3_NB

NTC_NB

IMON_NB

SVC

PWM3

37 BOOT1_NB

2

3

4

36

35

34

33

32

UGATE1_NB

5

VR_HOT_L

SVD

PHASE1_NB

LGATE1_NB

LGATE2

GND

(BOTTOM PAD)

6

VDDIO

SVT

7

8

VDDP

ENABLE

PWROK

IMON

9

31 UGATE2

PHASE2

30

10

11

12

13

29

28

27

BOOT2

LGATE1

UGATE1

NTC

ISEN4

15 16

24 25

26

17 18 19 20 21

14

22 23

Pin Descriptions

PIN NUMBER

SYMBOL

DESCRIPTION

1

ISEN3_NB

Individual current sensing for Channel 3 of the Northbridge VR. When ISEN3_NB is pulled to +5V, the

controller will disable Channel 3 and the Northbridge VR will run 2-phase.

2

3

NTC_NB

Thermistor input to VR_HOT_L circuit to monitor Northbridge VR temperature.

IMON_NB

Northbridge output current monitor. A current proportional to the Northbridge VR output current is

sourced from this pin.

4

5

6

7

SVC

VR_HOT_L

SVD

Serial VID clock input from the CPU processor master device.

Thermal indicator signal to AMD CPU. Thermal overload open-drain output indicator active LOW.

Serial VID data bidirectional signal from the CPU processor master device to the VR.

VDDIO

VDDIO is the processor memory interface power rail and this pin serves as the reference to the controller

IC for this processor I/O signal level.

8

SVT

Serial VID Telemetry (SVT) data line input to the CPU from the controller IC. Telemetry and VID-on-the-fly

complete signal provided from this pin.

9

ENABLE

PWROK

Enable input. A high level logic on this pin enables both VRs.

2

10

System power-good input. When this pin is high, the SVI 2 interface is active and the I C protocol is

running. While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This

pin must be low prior to the ISL95712 PGOOD output going high per the AMD SVI 2.0 Controller

Guidelines.

11

12

13

IMON

NTC

Core output current monitor. A current proportional to the Core VR output current is sourced from this pin.

Thermistor input to VR_HOT_L circuit to monitor Core VR temperature.

ISEN4

ISEN4 is the individual current sensing for Channel 4 of the Core VR. When ISEN4 is pulled to +5V, the

controller disables Channel 4, and the Core VR runs in three-phase mode.

FN8566 Rev 1.00

November 2, 2015

Page 4 of 35

ISL95712

Pin Descriptions(Continued)

PIN NUMBER

SYMBOL

DESCRIPTION

14

ISEN3

ISEN3 is the individual current sensing for Channel 3 of the Core VR. When ISEN3 is pulled to +5V, the

controller disables Channel 3, and the Core VR runs in two-phase mode.

15

16

ISEN2

ISEN1

Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to +5V, the controller

disables Channel 2, and the Core VR runs in single-phase mode.

Individual current sensing for Channel 1 of the Core VR. If ISEN2 is tied to +5V, this pin cannot be left

open and must be tied to GND with a 10kΩ resistor. If ISEN1 is tied to +5V, the Core portion of the IC is

shut down.

17

18

19

20

ISUMP

ISUMN

VSEN

RTN

Noninverting input of the transconductance amplifier for current monitor and load line of Core output.

Inverting input of the transconductance amplifier for current monitor and load line of Core output.

Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.

Output voltage sense return pin for both Core VR and Northbridge VR. Connect to the -sense pin of the

microprocessor die.

21

22

FB

Output voltage feedback to the inverting input of the Core controller error amplifier.

VDD

5V bias power. A resistor [2Ω] and a decoupling capacitor should be used from the +5V supply. A high

quality, X7R dielectric MLCC capacitor is recommended.

23

PGOOD

Open-drain output to indicate the Core output is ready to supply regulated voltage. Pull-up externally to

VDD or 3.3V through a resistor.

24

25

COMP

Core controller error amplifier output. A resistor from COMP to GND sets the Core VR offset voltage.

BOOT1

Connect an MLCC capacitor across the BOOT1 and PHASE1 pins. The boot capacitor is charged, through

an internal boot diode connected from the VDDP pin to the BOOT1 pin, each time the PHASE1 pin drops

below VDDP minus the voltage dropped across the internal boot diode.

26

PHASE1

Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PHASE1 pin to the

node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output inductor of

Phase 1.

27

28

29

UGATE1

LGATE1

BOOT2

Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UGATE1 pin to the gate

of the Phase 1 high-side MOSFET(s).

Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LGATE1 pin to the gate

of the Phase 1 low-side MOSFET(s).

Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot capacitor is charged, through

an internal boot diode connected from the VDDP pin to the BOOT2 pin, each time the PHASE2 pin drops

below VDDP minus the voltage dropped across the internal boot diode.

30

PHASE2

Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PHASE2

pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output

inductor of Phase 2.

31

32

33

34

35

UGATE2

VDDP

Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UGATE2 pin to the gate

of the Phase 2 high-side MOSFET(s).

Input voltage bias for the internal gate drivers. Connect +12V to the VDDP pin. Decouple with at least 1µF

of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.

LGATE2

Output of the Phase 2 low-side MOSFET gate driver of the Core VR. Connect the LGATE2 pin to the gate

of the Phase 2 low-side MOSFET(s).

LGATE1_NB

PHASE1_NB

Output of Northbridge Phase 1 low-side MOSFET gate driver. Connect the LGATE1_NB pin to the gate of

the Northbridge VR Phase 1 low-side MOSFET(s).

Current return path for Northbridge VR Phase 1 high-side MOSFET gate driver. Connect the PHASE1_NB

pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain and the output

inductor of Northbridge Phase 1.

36

UGATE1_NB

Output of the Phase 1 high-side MOSFET gate driver of the Northbridge VR. Connect the UGATE1_NB pin

to the gate of the Northbridge VR Phase 1 high-side MOSFET(s).

FN8566 Rev 1.00

November 2, 2015

Page 5 of 35

ISL95712

Pin Descriptions(Continued)

PIN NUMBER

SYMBOL

DESCRIPTION

37

BOOT1_NB

Connect an MLCC capacitor across the BOOT1_NB and PHASE1_NB pins. The boot capacitor is charged,

through an internal boot diode connected from the VDDP pin to the BOOT1_NB pin, each time the

PHASE1_NB pin drops below VDDP minus the voltage dropped across the internal boot diode.

38

39

PWM3

PWM4

PWM output of Channel 3 of the Core VR. Disabled if ISEN3 is tied to +5V.

PWM output of Channel 4 of the Core VR. Disabled if ISEN4 is tied to +5V.

40

PWM2_NB

PWM3_NB

I2CLK, I2DATA

PWM output for Channel 2 of the Northbridge VR. Disabled when ISEN2_NB is tied to +5V.

PWM output for Channel 3 of the Northbridge VR. Disabled when ISEN3_NB is tied to +5V.

41

2

42, 43

SMBus/PMBus/I C interface used for additional communication with the controller outside of the SVI2

pins. Tie to VCC with 4.7kΩ pull-up resistor when not used.

44

45

PROG

A resistor from the PROG pin to GND programs the switching frequency.

PGOOD_NB

Open-drain output to indicate the Northbridge output is ready to supply regulated voltage. Pull-up

externally to VDD or 3.3V through a resistor.

46

COMP_NB

Northbridge VR error amplifier output. A resistor from COMP_NB to GND sets the Northbridge VR offset

voltage and is used to set the switching frequency for the Core VR and Northbridge VR.

47

48

FB_NB

Output voltage feedback to the inverting input of the Northbridge controller error amplifier.

VSEN_NB

Output voltage sense pin for the Northbridge controller. Connect to the +sense pin of the microprocessor

die.

49

50

ISUMN_NB

ISUMP_NB

Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR.

Noninverting input of the transconductance amplifier for current monitor and load line of the Northbridge

VR.

51

52

ISEN1_NB

Individual current sensing for Channel 1 of the Northbridge VR. If ISEN1_NB is tied to +5V, this pin cannot

be left open and must be tied to GND with a 10kΩ resistor. If ISEN1_NB is tied to +5V, the Northbridge

portion of the IC is shutdown.

ISEN2_NB

Individual current sensing for Channel 2 of the Northbridge VR. When ISEN2_NB is pulled to +5V, the

controller will disable Channels 2 and 3 and the Northbridge VR will run 1-phase.

GND (Bottom Pad)

Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.

Ordering Information

PART NUMBER

PART

TEMP.

PACKAGE

PKG.

(Notes 1, 2, 3)

MARKING

RANGE (°C)

(RoHS Compliant)

DWG. #

ISL95712HRZ

95712 HRZ

95712 IRZ

-10 to +100

-40 to +100

52 Ld 6x6 QFN

L52.6x6A

ISL95712IRZ

NOTES:

1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95712. For more information on MSL please see tech brief TB363.

FN8566 Rev 1.00

November 2, 2015

Page 6 of 35

ISL95712

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

Input Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

Thermal Resistance (Typical)

52 Ld QFN Package (Notes 4, 5) . . . . . . . .



_JA(°C/W)

28



_JC(°C/W)

DD

2.5

Gate Driver Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . -0.3V to + 15V

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

DDP

Boot Voltage (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

+ 15V

+ 0.3V

BOOT

DDP

BOOT

DDP

UGATE Voltage (V

). . . . . . . . . . . . . . V

- 0.3V to V

UGATE

PHASE

- 3.5V (<100ns Pulse Width, 2µJ) to V

DC

V

PHASE

LGATE Voltage (V

) . . . . . . . . . . . . . . . . . GND - 0.3V to V

LGATE

GND - 5V (<100ns Pulse Width, 2µJ) to V

DC

Recommended Operating Conditions

PHASE Voltage (V

) . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 25V

Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

PHASE DC

DC

GND - 8V (>400ns Pulse Width, 20µ) to 30V (<200ns)

DD

Input Supply and Gate Drive Voltages, V

Ambient Temperature

. . . . . . . . . . . . . . . +12V ±5%

DDP

Open-Drain Outputs, PGOOD, PGOOD_NB, VR_HOT_L. . . . . . . -0.3V to +7V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V

HRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C

IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C

Junction Temperature

HRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C

IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Operating Conditions: V = 5V, T = -10°C to +100°C (HRZ), f = 300kHz, unless otherwise noted.

DD

A

SW

Boldface limits apply across the operating temperature range, -40°C to +100°C.

MIN

MAX

PARAMETER

INPUT POWER SUPPLY

+5V Supply Current

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6)

UNIT

I

ENABLE = 1V

ENABLE = 0V

12.5

14.0

125

mA

µA

VDD

POWER-ON-RESET THRESHOLDS

VDD POR Threshold

VDD_POR

V

rising

4.35

4.15

4.50

V

r

DD

falling

4.00

f

SYSTEM AND REFERENCES

System Accuracy

HRZ

%Error (V

No load; closed loop, active mode range,

VID = 0.75V to 1.55V

-0.5

-10

+0.5

+10

%

OUT)

VID = 0.25V to 0.74375V

mV

IRZ

%Error (V

No load; closed loop, active mode range,

VID = 0.75V to 1.55V

-0.8

+0.8

)

%

mV

V

OUT

VID = 0.25V to 0.74375V

VID = [00000000]

-12

+12

Maximum Output Voltage

Minimum Output Voltage

CHANNEL FREQUENCY

Nominal Channel Frequency

Adjustment Range

V

1.55

0

OUT(max)

V

VID = [11111111]

V

OUT(min)

f

280

300

320

450

kHz

SW(nom)

AMPLIFIERS

Current-Sense Amplifier Input Offset

HRZ

IRZ

I

= 0A

-0.15

+0.15

mV

dB

FB

-0.20

+0.20

Error Amp DC Gain

Error Amp Gain-Bandwidth Product

ISEN

A

119

17

v0

GBW

C = 20pF

MHz

L

Input Bias Current

20

nA

FN8566 Rev 1.00

November 2, 2015

Page 7 of 35

ISL95712

Electrical Specifications Operating Conditions: V = 5V, T = -10°C to +100°C (HRZ), f = 300kHz, unless otherwise noted.

DD

A

SW

Boldface limits apply across the operating temperature range, -40°C to +100°C. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6)

UNIT

POWER-GOOD (PGOOD AND PGOOD_NB) AND PROTECTION MONITORS

PGOOD Low Voltage

V

I

= 4mA

PGOOD

0.4

1

V

OL

PGOOD Leakage Current

PWROK High Threshold

VR_HOT_L Pull-Down

PWROK Leakage Current

VR_HOT_L Leakage Current

GATE DRIVER

I

PGOOD = 3.3V

-1

µA

mV

Ω

OH

750

11

1

µA

UGATE Pull-Up Resistance

UGATE Source Current

UGATE Sink Resistance

UGATE Sink Current

R

200mA source current

UGATE - PHASE = 2.5V

250mA sink current

1.0

2

1.5

0.9

Ω

A

UGPU

I

UGSRC

R

1.0

2

Ω

A

UGPD

I

UGATE - PHASE = 2.5V

250mA source current

LGATE - VSSP = 2.5V

UGSNK

LGATE Pull-Up Resistance

LGATE Source Current

LGATE Sink Resistance

LGATE Sink Current

R

1.0

2

Ω

A

LGPU

I

LGSRC

R

250mA sink current

0.5

4

Ω

A

LGPD

I

LGATE - VSSP = 2.5V

LGSNK

UGATE to LGATE Dead Time

LGATE to UGATE Dead Time

PROTECTION

t

UGATE falling to LGATE rising, no load

LGATE falling to UGATE rising, no load

59

37

ns

UGFLGR

LGFUGR

t

Overvoltage Threshold

Undervoltage Threshold

Current Imbalance Threshold

OV

UV

VSEN rising above setpoint for >1µs

VSEN falls below setpoint for >1µs

One ISEN above another ISEN for >1.2ms

275

325

9

375

mV

µA

TH

Way Overcurrent Trip Threshold

[IMONx Current Based Detection]

IMONx

All states, I

= 60µA, R

= 135kΩ

IMON

15

WOC

DROOP

Overcurrent Trip Threshold

[IMONx Voltage Based Detection]

V

All states, I

= 45µA,

= 135kΩ

IMON

1.485

1.510

1.535

1

V

IMONx_OCP

DROOP

I

= 11.25µA, R

IMONx

LOGIC THRESHOLDS

ENABLE Input Low

ENABLE Input High

V

IL

V

HRZ

IRZ

1.6

1.65

-1

IH

V

ENABLE Leakage Current

I

ENABLE = 0V

ENABLE = 1V

0

1

µA

Ω

ENABLE

1

SVT Impedance

50

SVC, SVD Input Low

SVC, SVD Input High

SVC, SVD Leakage

V

% of VDDIO

30

%

IL

V

70

-1

%

IH

ENABLE = 0V, SVC, SVD = 0V and 1V

ENABLE = 1V, SVC, SVD = 1V

ENABLE = 1V, SVC, SVD = 0V

1

µA

-5

-35

-20

-5

PWM

PWM Output Low

PWM Output High

PWM Tri-State Leakage

THERMAL MONITOR

NTC Source Current

NTC Thermal Warning Voltage

V

Sinking 5mA

Sourcing 5mA

PWM = 2.5V

1

V

0L

V

3.5

0H

0.5

µA

NTC = 0.6V

27

30

33

µA

600

640

680

mV

FN8566 Rev 1.00

November 2, 2015

Page 8 of 35

ISL95712

Electrical Specifications Operating Conditions: V = 5V, T = -10°C to +100°C (HRZ), f = 300kHz, unless otherwise noted.

DD

A

SW

Boldface limits apply across the operating temperature range, -40°C to +100°C. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

20

(Note 6)

UNIT

mV

NTC Thermal Warning Voltage

Hysteresis

NTC Thermal Shutdown Voltage

SLEW RATE

530

580

630

mV

VID-on-the-Fly Slew Rate

Maximum Programmed

Minimum Programmed

16

8

20

10

24

12

mV/µs

NOTE:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

Gate Driver Timing Diagram

PWM

t

LGFUGR

t

FU

t

RU

1V

UGATE

LGATE

1V

t

RL

t

FL

t

UGFLGR

FIGURE 4. GATE DRIVER TIMING DIAGRAM

FN8566 Rev 1.00

November 2, 2015

Page 9 of 35

ISL95712

1-phase mode, the master clock signal will be distributed to

Phase 1 only and will be the Clock1 signal.

Theory of Operation

Multiphase R3™ Modulator

VW

The ISL95712 is a multiphase regulator implementing two voltage

regulators, CORE VR and Northbridge (NB) VR, on one chip

controlled by AMD’s™ SVI2™ protocol. The CORE VR can be

programmed for 1-, 2-, 3- or 4-phase operation. The Northbridge VR

can be configured for 1-, 2-, or 3-phase operation. Both regulators

use the Intersil patented R3™ (Robust Ripple Regulator) modulator.

The R3™ modulator combines the best features of fixed frequency

PWM and hysteretic PWM while eliminating many of their

shortcomings. Figure 5 conceptually shows the multiphase R3™

modulator circuit, and Figure 6 shows the operation principles.

HYSTERETIC

VCRM

WINDOW

COMP

MASTER

CLOCK

CLOCK1

PWM1

MASTER CLOCK CIRCUIT

VW

CLOCK2

PWM2

MASTER

CLOCK

CLOCK1

CLOCK2

CLOCK3

COMP

VCRM

MASTER

CLOCK

PHASE

SEQUENCER

CLOCK3

GMVO

CRM

PWM3

SLAVE CIRCUIT 1

L1

I_L1

PHASE1

PHASE2

PHASE3

VW

CLOCK1

PWM1

VO

S

R

VW

Q

CO

VCRS1

GM

VCRS2

VCRS3 VCRS1

CRS1

CRS2

CRS3

FIGURE 6. R3™ MODULATOR OPERATION PRINCIPLES IN

STEADY STATE

SLAVE CIRCUIT 2

L2

I_L2

CLOCK2

GM

PWM2

S

R

VW

Q

Each slave circuit has its own ripple capacitor C , whose voltage

RS

mimics the inductor ripple current. A g amplifier converts the

inductor voltage into a current source to charge and discharge

. The slave circuit turns on its PWM pulse upon receiving the

clock signal, and the current source charges C . When C

hits VW, the slave circuit turns off the PWM pulse,

and the current source discharges C

m

VCRS2

C

RS

RS RS

voltage V

CRS

SLAVE CIRCUIT 3

.

L3

I_L3

RS

CLOCK3

GM

PWM3

S

R

VW

Q

Since the controller works with V

, which are large amplitude

CRS

and noise-free synthesized signals, it achieves lower phase jitter

than conventional hysteretic mode and fixed PWM mode

controllers. Unlike conventional hysteretic mode converters, the

error amplifier allows the ISL95712 to maintain a 0.5% output

voltage accuracy.

VCRS3

FIGURE 5. R3™ MODULATOR CIRCUIT

Figure 7 shows the operation principles during load insertion

response. The COMP voltage rises during load insertion,

generating the master clock signal more quickly, so the PWM

pulses turn on earlier, increasing the effective switching

frequency. This allows for higher control loop bandwidth than

conventional fixed frequency PWM controllers. The VW voltage

rises as the COMP voltage rises, making the PWM pulses wider.

During load release response, the COMP voltage falls. It takes

the master clock circuit longer to generate the next master clock

signal so the PWM pulse is held off until needed. The VW voltage

falls as the COMP voltage falls, reducing the current PWM pulse

width. This kind of behavior gives the ISL95712 excellent

response speed.

Inside the IC, the modulator uses the master clock circuit to

generate the clocks for the slave circuits. The modulator

discharges the ripple capacitor C with a current source equal

rm

to g V , where g is a gain factor. C voltage V

m o rm CRM

is a

m

sawtooth waveform traversing between the VW and COMP

voltages. It resets to VW when it hits COMP, and generates a

one-shot master clock signal. A phase sequencer distributes the

master clock signal to the slave circuits. If the Core VR is in

4-phase mode, the master clock signal is distributed to the four

phases, and the Clock 1~4 signals will be 90° out-of-phase. If the

Core VR is in 3-phase mode, the master clock signal is

distributed to the three phases, and the Clock 1~3 signals will be

120° out-of-phase. If the Core VR is in 2-phase mode, the master

clock signal is distributed to Phases 1 and 2, and the Clock1 and

Clock2 signals will be 180° out-of-phase. If the Core VR is in

The fact that all the phases share the same VW window voltage

also ensures excellent dynamic current balance among phases.

FN8566 Rev 1.00

November 2, 2015

Page 10 of 35

ISL95712

Figure 9 shows the operation principle in diode emulation mode at

light load. The load gets incrementally lighter in each of the three

cases from top to bottom. The PWM on-time is determined by the

VW window size and therefore is the same, making the inductor

current triangle the same in each of the three cases. The ISL95712

VW

COMP

V_CRM

clamps the ripple capacitor voltage V

in DE mode to make it

CRS

mimic the inductor current. It takes the COMP voltage longer to hit

, naturally stretching the switching period. The inductor

current triangles move farther apart, such that the inductor current

average value is equal to the load current. The reduced switching

frequency helps increase light-load efficiency.

V

CRS

MASTER

CLOCK

CLOCK1

PWM1

CCM/DCM BOUNDARY

VW

CLOCK2

PWM2

PWM

V_CRS

CLOCK3

PWM3

IL

VW

LIGHT DCM

VW

V_CRS

VCRS1

VCRS3

VCRS2

IL

DEEP DCM

VW

FIGURE 7. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD

INSERTION RESPONSE

V_CRS

Diode Emulation and Period Stretching

IL

The ISL95712 can operate in Diode Emulation (DE) mode to

improve light-load efficiency. In DE mode, the low-side MOSFET

conducts when the current is flowing from source-to-drain and

does not allow reverse current, thus emulating a diode. Figure 8

shows when LGATE is on, the low-side MOSFET carries current,

creating negative voltage on the phase node due to the voltage

drop across the ON-resistance. The ISL95712 monitors the current

by monitoring the phase node voltage. It turns off LGATE when the

phase node voltage reaches zero to prevent the inductor current

from reversing the direction and creating unnecessary power loss.

FIGURE 9. PERIOD STRETCHING

Channel Configuration

Individual PWM channels of either VR can be disabled by

connecting the ISENx pin of the channel not required to +5V. For

example, placing the controller in a 3+1 configuration, requires

ISEN4 of the Core VR and ISEN2_NB and ISEN3_NB of the

Northbridge VR to be tied to +5V. This disables Channel 4 of the

Core VR and Channels 2 and 3 of the Northbridge VR. ISEN1_NB

must be tied through a 10kΩ resistor to GND to prevent this pin

from pulling high and disabling the channel. Similarly, if the Core

VR is set to single phase mode, ISEN4, ISEN3 and ISEN2 will be

tied to +5V while ISEN1 is tied to GND through a 10kΩ resistor.

PHASE

Connecting ISEN1 or ISEN1_NB to +5V will disable the

corresponding VR output. This feature allows debugging of

individual VR outputs.

UG A TE

LG ATE

Power-On Reset

IL

Before the controller has sufficient bias to guarantee proper

operation, the ISL95712 requires a +5V input supply tied to VDD

to exceed the VDD rising Power-On Reset (POR) threshold. Once

this threshold is reached or exceeded, the ISL95712 has enough

bias to check the state of the SVI inputs once ENABLE is taken

high. Hysteresis between the rising and the falling thresholds

assure the ISL95712 does not inadvertently turn off unless the

bias voltage drops substantially (see “Electrical Specifications”

FIGURE 8. DIODE EMULATION

If the load current is light enough, as Figure 8 shows, the inductor

current reaches and stays at zero before the next phase node

pulse, and the regulator is in Discontinuous Conduction Mode

(DCM). If the load current is heavy enough, the inductor current

will never reach 0A, and the regulator is in CCM, although the

controller is in DE mode.

on page 7). Note that V must be present for the controller to

IN

drive the output voltage.

FN8566 Rev 1.00

November 2, 2015

Page 11 of 35

ISL95712

1

4

5

6

2

3

7

8

VDD

SVC

SVD

VOTF

SVT

TELEMETRY

ENABLE

PWROK

METAL_VID

V

/ V

CORE CORE_NB

V_SVI

PGOOD AND PGOOD_NB

Interval 1 to 2: ISL95712 waits to POR.

Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.

Interval 3 to 4: ENABLE locks pre-Metal VID code. Both outputs soft-start to this level.

Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation.

Interval 5 to 6: PGOOD and PGOOD_NB high is detected and PWROK is taken high. The ISL95712 is prepared for SVI commands.

Interval 6 to 7: SVC and SVD data lines communicate change in VID code.

Interval 7 to 8: ISL95712 responds to VID-ON-THE-FLY code change and issues a VOTF for positive VID changes.

Post 8: Telemetry is clocked out of the ISL95712.

FIGURE 10. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP

Start-Up Timing

VDD

With VDD above the POR threshold, the controller start-up

SLEW RATE

MetalVID

ENABLE

sequence begins when ENABLE exceeds the logic high threshold.

Figure 11 shows the typical soft-start timing of the Core and

Northbridge VRs. Once the controller registers ENABLE as a high,

the controller checks the state of a few programming pins during

the typical 8ms delay prior to beginning soft-starting the Core

and Northbridge outputs. The pre-PWROK Metal VID is read from

the state of the SVC and SVD pins and programs the DAC, the

programming resistors on the COMP, COMP_NB and PROG pins

are read to configure switching frequency, slew rate and output

offsets. These programming resistors are discussed in

subsequent sections. The ISL95712 use a digital soft-start to

ramp up the DAC to the Metal VID level programmed. The

soft-start slew rate is programmed by the PROG resistor, which is

used to set the VID-on-the-fly slew rate as well. See the

“VID-on-the-Fly Slew Rate Selection” on page 17 for more details

on selecting the PROG resistor. PGOOD is asserted high at the

end of the soft-start ramp.

VID COMMAND

VOLTAGE

8ms

DAC

PGOOD

PWROK

VIN

FIGURE 11. TYPICAL SOFT-START WAVEFORMS

Voltage Regulation and Load Line

Implementation

After the soft-start sequence, the ISL95712 regulates the output

voltages to the pre-PWROK metal VID programmed, see Table 6

on page 17. The ISL95712 controls the no-load output voltage to

an accuracy of ±0.5% over the range of 0.75V to 1.55V. A

differential amplifier allows voltage sensing for precise voltage

regulation at the microprocessor die.

Diode Throttling

During the soft-start ramp-up, the ISL95712 operates in Diode

Throttling mode until the output has exceeded 400mV. In Diode

Throttling mode, the lower MOSFET is kept OFF so that the

MOSFET body diode conducts, similar to a standard buck

regulator.

FN8566 Rev 1.00

November 2, 2015

Page 12 of 35

ISL95712

amplifier regulates the inverting and noninverting input voltages to

be equal as shown in Equation 4:

R_droop

VCC

+ V

= V

+ VSS

DAC SENSE

VCC_SENSE

(EQ. 4)

SENSE

+

-

droop

V_droop

FB

VR LOCAL VO

“CATCH” RESISTOR

Rewriting Equation 4 and substituting Equation 3 gives Equation 5

the exact equation required for load line implementation.

I_droop

+

-

SVC

VCC

– VSS

= V

– R

 I

droop droop

(EQ. 5)

E/A

SENSE

DAC

SVID[7:0]

VSS_SENSE

COMP

DAC

X 1

SVD

RTN

VSS



VDAC

+

The VCC

SENSE

and VSS signals come from the processor die.

SENSE

+

The feedback is open circuit in the absence of the processor. As

Figure 12 shows, it is recommended to add a “catch” resistor to

feed the VR local output voltage back to the compensator, and to

add another “catch” resistor to connect the VR local output ground

to the RTN pin. These resistors, typically 10Ω, provide voltage

feedback if the system is powered up without a processor installed.

INTERNAL TO IC

-

“CATCH” RESISTOR

FIGURE 12. DIFFERENTIAL SENSING AND LOAD LINE

IMPLEMENTATION

Phase Current Balancing

As the load current increases from zero, the output voltage

droops from the VID programmed value by an amount

proportional to the load current, to achieve the load line. The

ISL95712 can sense the inductor current through the intrinsic DC

Resistance (DCR) of the inductors, as shown in Figures 13 and

14, or through resistors in series with the inductors, as shown in

R_dcr4

L4

R_pcb4

PHASE4

R_isen

I_L4

ISEN4

ISEN3

R_dcr3

C_isen

L3

R_pcb3

Figure 25 on page 28. In both methods, capacitor C voltage

n

PHASE3

R_isen

represents the total inductor current. An internal amplifier

I_L3

converts C voltage into an internal current source, I

, with the

n

sum

gain set by resistor R , see Equation 1.

C_isen

i

R_dcr2

L2

L1

R_pcb2

V_O

V

Cn

PHASE2

R_isen

----------

I

=

(EQ. 1)

sum

R

i

I_L2

ISEN2

ISEN1

C_isen

The I

current is used for load line implementation, current

sum

R_dcr1

R_pcb1

monitoring on the IMON pins and overcurrent protection.

PHASE1

R_isen

Figure 12 shows the load line implementation. The ISL95712

I_L1

drives a current source (I

droop

) out of the FB pin, which is a ratio

C_isen

of the I

current, as described by Equation 2.

sum

V

5

4

5

4

Cn

--

=

-- ----------

(EQ. 2)

I

 I

=

sum



FIGURE 13. CURRENT BALANCING CIRCUIT

droop

R

i

The ISL95712 monitors individual phase average current by

monitoring the ISEN1, ISEN2, ISEN3 and ISEN4 voltages.

Figure 13 shows the recommended current balancing circuit for

DCR sensing. Each phase node voltage is averaged by a low-pass

When using inductor DCR current sensing, a single NTC element

is used to compensate the positive temperature coefficient of the

copper winding, thus sustaining the load line accuracy with

reduced cost.

filter consisting of R

corresponding ISEN pin. R

and C

, and is presented to the

isen

should be routed to the inductor

I

flows through resistor R

droop

and creates a voltage drop as

isen

droop

shown in Equation 3.

phase-node pad in order to eliminate the effect of phase node

parasitic PCB DCR. Equations 6 through 9 give the ISEN pin

voltages:

V

= R

 I

droop droop

(EQ. 3)

droop

(EQ. 6)

(EQ. 7)

(EQ. 8)

V

= R

+ R

  I

ISEN1

ISEN2

ISEN3

dcr1

dcr2

dcr3

pcb1

pcb2

pcb3

L1

L2

L3

V

is the droop voltage required to implement load line.

droop

Changing R

Since I

recommended to first scale I

then select an appropriate R

load line slope.

or scaling I

can change the load line slope.

droop

sets the overcurrent protection level, it is

droop

sum

based on OCP requirement,

value to obtain the desired

sum

droop

(EQ. 9)

,

V

= R

+ R

  I

ISEN4

dcr4

pcb4

L4

Differential Sensing

Figure 12 also shows the differential voltage sensing scheme.

Where R

, R

pcb2 pcb3

inductor output side pad and the output voltage rail; and I , I

, R

and R

are inductor DCR; R

dcr1 dcr2 dcr3

dcr4

pcb1

R

, R

and R are parasitic PCB DCR between the

VCC

and VSS are the remote voltage sensing signals

pcb4

SENSE

,

from the processor die. A unity gain differential amplifier senses

the VSS voltage and adds it to the DAC output. The error

L1 L2

I

and I are inductor average currents.

L3

L4

SENSE

FN8566 Rev 1.00

November 2, 2015

Page 13 of 35

ISL95712

The ISL95712 will adjust the phase pulse-width relative to the

The ISL95712 will make V

ISEN1

= V

ISEN2

= V

ISEN3

= V as

ISEN4

other phases to make V

= V

= R

= V

, thus to

= R

shown in Equations 14 and 16:

ISEN1

ISEN2

ISEN3

ISEN4

achieve I = I = I = I , when R

= R

dcr3

L1 L2 L3 L4 dcr1

dcr2

dcr4

V

+ V + V + V

= V + V + V + V

1n 2p 3n 4n

(EQ. 14)

(EQ. 15)

(EQ. 16)

1p

2n

3n

and R

= R

.

pcb4

4n

pcb1

pcb2 pcb3

Using the same components for L1, L2, L3 and L4 provides a

good match of R , R , R and R . Board layout

V

+ V + V + V

= V + V + V + V

1n 2n 3p

1n

2p

3n

4n

4p

4n

dcr1 dcr2 dcr3 dcr4

determines R

, R , R and R . It is recommended

pcb1 pcb2 pcb3 pcb4

+ V + V + V

= V + V + V + V

1n 2n 3n

to have a symmetrical layout for the power delivery path between

each inductor and the output voltage rail, such that

2n

3p

R

= R

= R .

Rewriting Equation 14 gives Equation 17:

pcb1

pcb2

pcb3

pcb4

R_dcr4

L4

R_pcb4

V

– V

= V – V

1n 2p 2n

PHASE4 V4p

R_isen

(EQ. 17)

(EQ. 18)

(EQ. 19)

(EQ. 20)

1p

C_isen

ISEN4

I_L4

V_4n

Rewriting Equation 15 gives Equation 18:

R_isen

V

– V

= V – V

2n 3p 3n

2p

Rewriting Equation 16 gives Equation 19:

R_dcr3

L3

R_pcb3

V3p

PHASE3

R_isen

V

– V

= V – V

3n 4p 4n

3p

C_isen

ISEN3

I_L3

V_3n

R_isen

Combining Equations 17 through 19 give:

V

– V

= V – V

3n 4p 4n

1p

1n

2p

2n

3p

INTERNAL

TO IC

R_dcr2

L2

V

R_pcb2

o

V2p

Therefore:

PHASE2

R_isen

C_isen

R

 I

= R

 I

= R

 I

= R

 I

dcr4 L4

(EQ. 21)

pcb4

dcr1

L1

dcr2

L2

dcr3

L3

ISEN2

I_L2

V_2n

Current balancing (I = I = I = I ) is achieved when

L1 L2 L3 L4

R

= R

= R = R . R , R

, R and R

dcr1

dcr2

dcr3

dcr4 pcb1 pcb2 pcb3

R_dcr1

L1

do not have any effect.

R_pcb1

V1p

PHASE1

R_isen

C_isen

Since the slave ripple capacitor voltages mimic the inductor

currents, the R3™ modulator can naturally achieve excellent

current balancing during steady state and dynamic operations.

Figure 15 shows the current balancing performance of a

three-phase evaluation board with load transient of 12A/51A at

different rep rates. The inductor currents follow the load current

dynamic change with the output capacitors supplying the

difference. The inductor currents can track the load current well

at a low repetition rate, but cannot keep up when the repetition

rate gets into the hundred-kHz range, where it is out of the

control loop bandwidth. The controller achieves excellent current

balancing in all cases installed.

ISEN1

I_L1

V_1n

R_isen

FIGURE 14. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT

Sometimes, it is difficult to implement symmetrical layout. For

the circuit shown in Figure 13, asymmetric layout causes

different R

, R

and R values, thus creating a

pcb1 pcb2 pcb3

pcb4

current imbalance. Figure 14 shows a differential sensing current

balancing circuit recommended for ISL95712. The current

sensing traces should be routed to the inductor pads so they only

pick up the inductor DCR voltage. Each ISEN pin sees the average

voltage of three sources: its own, phase inductor phase-node

pad, and the other two phase inductor output side pads.

Equations 10 through 13 give the ISEN pin voltages:

V

= V + V + V + V

1p 2n 3n

(EQ. 10)

ISEN1

ISEN2

4n

V

= V + V + V + V

(EQ. 11)

1n

2p

3n

V

= V + V + V + V

1n 2n 3p

(EQ. 12)

(EQ. 13)

ISEN3

ISEN4

4n

4p

= V + V + V + V

1n

2n

3n

FN8566 Rev 1.00

November 2, 2015

Page 14 of 35

ISL95712

Modes of Operation

REP RATE = 10kHz

TABLE 1. CORE VR MODES OF OPERATION

PSI0_L

AND

CONFIG.

4-phase

Core VR

Configuration

ISEN4

ISEN3

ISEN2

PSI1_L

MODE

To Power To Power To Power

Stage Stage Stage

11

01

00

11

01

00

11

01

00

11

01

00

4-phase CCM

2-phase CCM

1-phase DE

3-phase CCM

2-phase CCM

1-phase DE

2-phase CCM

1-phase CCM

1-phase DE

1-phase CCM

1-phase DE

3-phase

Core VR

Configuration

Tied to 5V To Power To Power

Stage Stage

REP RATE = 25kHz

2-phase

Core VR

Configuration

Tied to 5V Tied to 5V To Power

Stage

1-phase

Core VR

Configuration

Tied to 5V Tied to 5V Tied to 5V

REP RATE = 50kHz

The Core VR can be configured for 4-, 3-, 2- or 1-phase operation.

Table 1 shows Core VR configurations and operational modes,

programmed by the ISEN4, ISEN3 and ISEN2 pin status and the

PSI0_L and PSI1_L commands via the SVI 2 interface. The SVI 2

interface description of these bits is outlined in Table 9.

The ISENx pins disable the channel which they are related to. For

example, to setup a 3-phase configuration the ISEN4 pin is tied to

5V. This disables Channel 4 of the controller on the Core side.

In a 3-phase configuration, the Core VR operates in 3-phase CCM,

with PSI0_L and PSI_L both high. If PSI0_L is taken low via the

SVI 2 interface, the Core VR sheds Phase 3. The Core VR then

operates 2-phase and remains in CCM. When both PSI0_L and

PSI1_L are taken low, the Core VR sheds Phase 2 and the Core

VR enters 1-phase Diode Emulation (DE) mode.

REP RATE = 100kHz

For 2-phase configurations, the Core VR operates in 2-phase CCM

with PSI0_L and PSI_L both high. If PSI0_L is taken low via the

SVI 2 interface, the Core VR sheds Phase 2 and the Core VR

operates in 1-phase and remains in CCM. When both PSI0_L and

PSI1_L are taken low, the Core VR operates in 1-phase DE mode.

In a 1-phase configuration, the Core VR operates in 1-phase CCM

and remains in this mode when PSI0_L is taken low. When both

PSI0_L and PSI1_L are taken low, the controller enters DE mode.

REP RATE = 200kHz

When the Core VR is taken into PSI1 mode, where both PSI0_L

and PSI1_L are taken low, the ISL95712 will shed any additional

phases in excess of Phase 1. If there is a VID change as well, the

regulator will then slew the output to the new VID level in CCM

mode. Once the output has reached the new VID level, the Core

VR is then placed into DE mode. The Core VR can be disabled

completely by connecting ISEN1 to +5V.

FIGURE 15. CURRENT BALANCING DURING DYNAMIC OPERATION.

CH1: I , CH2: I , CH3: I , CH4: I

L1 L2

LOAD

L3

FN8566 Rev 1.00

November 2, 2015

Page 15 of 35

ISL95712

The ISL95712 Northbridge VR can be configured for 3-, 2-, or 1-

phase operation. Table 2 shows the Northbridge VR

configurations and operational modes, which are programmed

by the ISEN3_NB and ISEN2_NB pin status and the PSI0_L and

PSI1_L bits of the SVI 2 command.

not reached zero when the low-side MOSFET turns off, it will flow

through the low-side MOSFET body diode, causing the phase

node to have a larger voltage drop until it decays to zero. If the

inductor current has crossed zero and reversed the direction

when the low-side MOSFET turns off, it will flow through the

high-side MOSFET body diode, causing the phase node to have a

spike until it decays to zero. The controller continues monitoring

the phase voltage after turning off the low-side MOSFET. To

minimize the body diode-related loss, the controller also adjusts

the phase comparator threshold voltage accordingly in iterative

steps such that the low-side MOSFET body diode conducts for

approximately 40ns.

TABLE 2. NORTHBRIDGE VR MODES OF OPERATION

PSI0_L AND

CONFIG.

ISEN3_NB

ISEN2_NB

PSI1_L

MODE

3-phase

NB VR

Configuration

To Power

Stage

To Power

Stage

11

2-phase CCM

1-phase CCM

1-phase DE

2-phase CCM

1-phase CCM

1-phase DE

1-phase CCM

1-phase DE

01

00

Resistor Configuration Options

2-phase

NB VR

Configuration

Tied to 5V

To Power

Stage

11

The ISL95712 uses the COMP, COMP_NB and PROG pins to

configure some functionality within the IC. Resistors from these

pins to GND are read during the first portion of the soft-start

sequence. The following sections outline how to select the

resistor values for each of these pins to correctly program the

output voltage offset of each output, VID-on-the-fly slew rate and

switching frequency used for both VRs.

01

00

1-phase

NB VR

Configuration

Tied to 5V

11

01

00

VR Offset Programming

In a 1-phase configuration, the ISEN2_NB pin is tied to +5V. The

Northbridge VR operates in 1-phase CCM when both PSI0_L and

PSI1_L are high and continues in this mode when PSI0_L is

taken low. The controller enters 1-phase DE mode when both

PSI0_L and PSI1_L are low.

A positive or negative offset is programmed for the Core VR using

a resistor to ground from the COMP pin and the Northbridge in a

similar manner from the COMP_NB pin. Table 3 provides the

resistor value to select the desired output voltage offset. The 1%

tolerance resistor value shown in Table 3 must be used to program

the corresponding Core or NB output voltage offset. The MIN and

MAX tolerance values provide margin to insure the 1% tolerance

resistor will be read correctly.

When the Northbridge VR is taken into PSI1 mode, where both

PSI0_L and PSI1_L are taken low, the ISL95712 will shed any

additional phases in excess of Phase 1. If there is a VID change

as well, the regulator will then slew the output to the new VID

level in CCM mode. Once the output has reached the new VID

level, the Northbridge VR is then placed into DE mode.

TABLE 3. COMP AND COMP_NB OUTPUT VOLTAGE OFFSET SELECTION

RESISTOR VALUE [kΩ]

COMP

COMP_NB

OFFSET

[mV]

The Northbridge VR can be disabled completely by tying

ISEN1_NB to 5V.

MIN

TOLERANCE

1% TOLERANCE

VALUE

MAX

TOLERANCE

V

CORE OFFSET

[mV]

3.96

7.76

4.02

7.87

11.5

16.9

19.6

24.9

34.0

41.2

52.3

73.2

95.3

121

4.07

7.98

-43.75

-37.5

-31.25

-25

18.75

31.25

43.76

50

Dynamic Operation

Core and Northbridge VRs behave the same during dynamic

operation. The controller responds to VID-on-the-fly changes by

slewing to the new voltage at the slew rate programmed, see

Table 4. During negative VID transitions, the output voltage

decays to the lower VID value at the slew rate determined by the

load.

11.33

16.65

19.3

11.67

17.15

19.89

25.27

34.51

41.81

53.08

74.29

96.72

112.81

156.31

184.73

213.15

-18.75

-12.5

-6.25

6.25

18.75

31.25

43.76

50

37.5

25

24.53

33.49

40.58

51.52

72.10

93.87

119.19

151.69

179.27

206.85

The R3™ modulator intrinsically has voltage feed-forward. The

output voltage is insensitive to a fast slew rate input voltage

change.

12.5

0

18.75

31.25

43.76

50

Adaptive Body Diode Conduction Time

Reduction

In DCM, the controller turns off the low-side MOSFET when the

inductor current approaches zero. During on-time of the low-side

MOSFET, phase voltage is negative and the amount is the

154

37.5

25

37.5

25

MOSFET r

voltage drop, which is proportional to the

DS(ON)

inductor current. A phase comparator inside the controller

monitors the phase voltage during on-time of the low-side

MOSFET and compares it with a threshold to determine the zero

crossing point of the inductor current. If the inductor current has

182

210

12.5

0

12.5

0

OPEN

FN8566 Rev 1.00

November 2, 2015

Page 16 of 35

ISL95712

TABLE 4. PROG RESISTOR SELECTION

TABLE 5. SWITCHING FREQUENCY SELECTION

FREQUENCY

COMP_NB RANGE

PROG RANGE

RESISTOR VALUE

SLEW RATE FOR CORE AND

NORTHBRIDGE [mV/µs]

[kHz]

[kΩ]

4.02

7.87

11.5

16.9

19.6

24.9

34.0

41.2

52.3

73.2

95.3

121

300

57.6 to OPEN

4.02 to 41.2

57.6 to OPEN

4.02 to 41.2

19.1 to 41.2

or

154 to OPEN

20

15

350

400

450

19.1 to 41.2

or

154 to OPEN

12.5

10

5.62 to 16.9

or

57.6 to 121

20

15

5.62 to 16.9

or

57.6 to 121

12.5

10

20

The controller monitors SVI commands to determine when to

enter power-saving mode, implement dynamic VID changes and

shut down individual outputs.

15

12.5

10

AMD Serial VID Interface 2.0

154

20

The on-board Serial VID Interface 2.0 (SVI 2) circuitry allows the

AMD processor to directly control the Core and Northbridge

voltage reference levels within the ISL95712. Once the PWROK

signal goes high, the IC begins monitoring the SVC and SVD pins

for instructions. The ISL95712 uses a Digital-to-Analog Converter

(DAC) to generate a reference voltage based on the decoded SVI

value. See Figure 10 on page 12 for a simple SVI interface timing

diagram.

182

15

210

12.5

10

OPEN

VID-on-the-Fly Slew Rate Selection

The PROG resistor is used to select the slew rate for VID changes

commanded by the processor. Once selected, the slew rate is

locked in during soft-start and is not adjustable during operation.

The lowest slew rate that can be selected is 10mV/µs, which is

above the minimum of 7.5mV/µs required by the SVI2

specification. The slew rate selected sets the slew rate for both

Core and Northbridge VRs. The controller does not allow for

independent selection of slew rate.

Pre-PWROK Metal VID

Typical motherboard start-up begins with the controller decoding

the SVC and SVD inputs to determine the pre-PWROK Metal VID

setting (see Table 6). Once the ENABLE input exceeds the rising

threshold, the ISL95712 decodes and locks the decoded value

into an on-board hold register.

TABLE 6. PRE-PWROK METAL VID CODES

CCM Switching Frequency

SVC

0

SVD

0

OUTPUT VOLTAGE (V)

The Core and Northbridge VR switching frequency is set by the

programming resistors on COMP_NB and PROG. When the

ISL95712 is in Continuous Conduction Mode (CCM), the

switching frequency is not absolutely constant due to the nature

of the R3™ modulator. As explained in “Multiphase R3™

Modulator” on page 10, the effective switching frequency

increases during load insertion and decreases during load

release to achieve fast response. Thus, the switching frequency is

relatively constant at steady state. Variation is expected when

the power stage condition, such as input voltage, output voltage,

load, etc. changes. The variation is usually less than 10% and

does not have any significant effect on output voltage ripple

magnitude. Table 5 defines the switching frequency based on the

resistor values used to program the COMP_NB and PROG pins.

Use the previous tables related to COMP_NB and PROG to

determine the correct resistor value in these ranges to program

the desired output offset and slew rate.

1.1

1.0

0.9

0.8

0

1

0

1

Once the programming pins are read, the internal DAC circuitry

begins to ramp Core and Northbridge VRs to the decoded

pre-PWROK Metal VID output level. The digital soft-start circuitry

ramps the internal reference to the target gradually at a fixed

rate of approximately 5mV/µs until the output voltage reaches

~250mV and then at the programmed slew rate. The controlled

ramp of all output voltage planes reduces inrush current during

the soft-start interval. At the end of the soft-start interval, the

PGOOD and PGOOD_NB outputs transition high, indicating both

output planes are within regulation limits.

If the ENABLE input falls below the enable falling threshold, the

ISL95712 tri-states both outputs. PGOOD and PGOOD_NB are

pulled low with the loss of ENABLE. The Core and Northbridge VR

output voltages decay, based on output capacitance and load

FN8566 Rev 1.00

November 2, 2015

Page 17 of 35

ISL95712

leakage resistance. If bias to VDD falls below the POR level, the

The ISL95712 responds in the manner previously described.

Once VDD and ENABLE rise above their respective rising

thresholds, the internal DAC circuitry reacquires a pre-PWROK

metal VID code, and the controller soft-starts.

VID-on-the-Fly Transition

Once PWROK is high, the ISL95712 detects this flag and begins

monitoring the SVC and SVD pins for SVI instructions. The

microprocessor follows the protocol outlined in the following

sections to send instructions for VID-on-the-fly transitions. The

ISL95712 decodes the instruction and acknowledges the new

VID code. For VID codes higher than the current VID level, the

ISL95712 begins stepping the commanded VR outputs to the

new VID target at the fixed slew rate of 10mV/µs. Once the DAC

ramps to the new VID code, a VID-on-the-Fly Complete (VOTFC)

request is sent on the SVI lines.

SVI Interface Active

Once the Core and Northbridge VRs have successfully soft-started

and PGOOD and PGOOD_NB signals transition high, PWROK can

be asserted externally to the ISL95712. Once PWROK is asserted

to the IC, SVI instructions can begin as the controller actively

monitors the SVI interface. Details of the SVI Bus protocol are

provided in the “AMD Serial VID Interface 2.0 (SVI2)

When the VID codes are lower than the current VID level, the

ISL95712 checks the state of power state bits in the SVI

command. If power state bits are not active, the controller begins

stepping the regulator output to the new VID target. If the power

state bits are active, the controller allows the output voltage to

decay and slowly steps the DAC down with the natural decay of

the output. This allows the controller to quickly recover and move

to a high VID code if commanded. The controller issues a VOTFC

request on the SVI lines once the SVI command is decoded and

prior to reaching the final output voltage.

Specification”. See AMD publication #48022.

Once a VID change command is received, the ISL95712 decodes

the information to determine which VR is affected and the VID

target is determined by the byte combinations in Table 7. The

internal DAC circuitry steps the output voltage of the VR

commanded to the new VID level. During this time, one or more

of the VR outputs could be targeted. In the event either VR is

commanded to power-off by serial VID commands, the PGOOD

signal remains asserted.

VOTFC requests do not take priority over telemetry per the AMD

SVI 2 specification.

If the PWROK input is deasserted, then the controller steps both

the Core and the Northbridge VRs back to the stored pre-PWROK

metal VID level in the holding register from initial soft-start. No

attempt is made to read the SVC and SVD inputs during this time.

If PWROK is reasserted, then the ISL95712 SVI interface waits

for instructions.

SVI Data Communication Protocol

The SVI WIRE protocol is based on the I C bus concept. Two wires

2

[serial clock (SVC) and serial data (SVD)], carry information

between the AMD processor (master) and VR controller (slave) on

the bus. The master initiates and terminates SVI transactions

and drives the clock, SVC, during a transaction. The AMD

processor is always the master and the voltage regulators are the

slaves. The slave receives the SVI transactions and acts

accordingly. Mobile SVI WIRE protocol timing is based on

If ENABLE goes low during normal operation, all external

MOSFETs are tri-stated and both PGOOD and PGOOD_NB are

pulled low. This event clears the pre-PWROK metal VID code and

forces the controller to check SVC and SVD upon restart, storing

the pre-PWROK metal VID code found on restart.

2

high-speed mode I C. See AMD publication #48022 for

A POR event on VCC during normal operation shuts down both

regulators, and both PGOOD outputs are pulled low. The

pre-PWROK metal VID code is not retained. Loss of VIN during

operation will typically cause the controller to enter a fault

condition on one or both outputs as the output voltage collapses.

The controller will shut down both Core and Northbridge VRs and

latch off. The pre-PWROK metal VID code is not retained during

the process of cycling ENABLE to reset the fault latch and restart

the controller.

additional details.

FN8566 Rev 1.00

November 2, 2015

Page 18 of 35

ISL95712

TABLE 7. SERIAL VID CODES

SVID[7:0]

VOLTAGE (V)

1.55000

1.54375

1.53750

1.53125

1.52500

1.51875

1.51250

1.50625

1.50000

1.49375

1.48750

1.48125

1.47500

1.46875

1.46250

1.45625

1.45000

1.44375

1.43750

1.43125

1.42500

1.41875

1.41250

1.40625

1.40000

1.39375

1.38750

1.38125

1.37500

1.36875

1.36250

1.35625

0.75000

0.74375

0.73750

0.73125

0.72500

0.71875

0.71250

0.70625

SVID[6:0]

VOLTAGE (V)

1.35000

1.34375

1.33750

1.33125

1.32500

1.31875

1.31250

1.30625

1.30000

1.29375

1.28750

1.28125

1.27500

1.26875

1.26250

1.25625

1.25000

1.24375

1.23750

1.23125

1.22500

1.21875

1.21250

1.20625

1.20000

1.19375

1.18750

1.18125

1.17500

1.16875

1.16250

1.15625

0.55000*

0.54375*

0.53750*

0.53125*

0.52500*

0.51875*

0.51250*

0.50625*

SVID[6:0]

VOLTAGE (V)

1.15000

1.14375

1.13750

1.13125

1.12500

1.11875

1.11250

1.10625

1.10000

1.09375

1.08750

1.08125

1.07500

1.06875

1.06250

1.05625

1.05000

1.04375

1.03750

1.03125

1.02500

1.01875

1.01250

1.00625

1.00000

0.99375

0.98750

0.98125

0.97500

0.96875

0.96250

0.95625

0.35000*

0.34375*

0.33750*

0.33125*

0.32500*

0.31875*

0.31250*

0.30625*

SVID[6:0]

VOLTAGE (V)

0.95000

0.94375

0.93750

0.93125

0.92500

0.91875

0.91250

0.90625

0.90000

0.89375

0.88750

0.88125

0.87500

0.86875

0.86250

0.85625

0.85000

0.84375

0.83750

0.83125

0.82500

0.81875

0.81250

0.80625

0.80000

0.79375

0.78750

0.78125

0.77500

0.76875

0.76250

0.75625

0.15000*

0.14375*

0.13750*

0.13125*

0.12500*

0.11875*

0.11250*

0.10625*

0000_0000

0000_0001

0000_0010

0000_0011

0000_0100

0000_0101

0000_0110

0000_0111

0000_1000

0000_1001

0000_1010

0000_1011

0000_1100

0000_1101

0000_1110

0000_1111

0001_0000

0001_0001

0001_0010

0001_0011

0001_0100

0001_0101

0001_0110

0001_0111

0001_1000

0001_1001

0001_1010

0001_1011

0001_1100

0001_1101

0001_1110

0001_1111

1000_0000

1000_0001

1000_0010

1000_0011

1000_0100

1000_0101

1000_0110

1000_0111

0010_0000

0010_0001

0010_0010

0010_0011

0010_0100

0010_0101

0010_0110

0010_0111

0010_1000

0010_1001

0010_1010

0010_1011

0010_1100

0010_1101

0010_1110

0010_1111

0011_0000

0011_0001

0011_0010

0011_0011

0011_0100

0011_0101

0011_0110

0011_0111

0011_1000

0011_1001

0011_1010

0011_1011

0011_1100

0011_1101

0011_1110

0011_1111

1010_0000

1010_0001

1010_0010

1010_0011

1010_0100

1010_0101

1010_0110

1010_0111

0100_0000

0100_0001

0100_0010

0100_0011

0100_0100

0100_0101

0100_0110

0100_0111

0100_1000

0100_1001

0100_1010

0100_1011

0100_1100

0100_1101

0100_1110

0100_1111

0101_0000

0101_0001

0101_0010

0101_0011

0101_0100

0101_0101

0101_0110

0101_0111

0101_1000

0101_1001

0101_1010

0101_1011

0101_1100

0101_1101

0101_1110

0101_1111

1100_0000

1100_0001

1100_0010

1100_0011

1100_0100

1100_0101

1100_0110

1100_0111

0110_0000

0110_0001

0110_0010

0110_0011

0110_0100

0110_0101

0110_0110

0110_0111

0110_1000

0110_1001

0110_1010

0110_1011

0110_1100

0110_1101

0110_1110

0110_1111

0111_0000

0111_0001

0111_0010

0111_0011

0111_0100

0111_0101

0111_0110

0111_0111

0111_1000

0111_1001

0111_1010

0111_1011

0111_1100

0111_1101

0111_1110

0111_1111

1110_0000

1110_0001

1110_0010

1110_0011

1110_0100

1110_0101

1110_0110

1110_0111

FN8566 Rev 1.00

November 2, 2015

Page 19 of 35

ISL95712

TABLE 7. SERIAL VID CODES (Continued)

SVID[7:0]

VOLTAGE (V)

0.70000

0.69375

0.68750

0.68125

0.67500

0.66875

0.66250

0.65625

0.65000

0.64375

0.63750

0.63125

0.62500

0.61875

0.61250

0.60625

0.60000*

0.59375*

0.58750*

0.58125*

0.57500*

0.56875*

0.56250*

0.55625*

SVID[6:0]

VOLTAGE (V)

0.50000*

0.49375*

0.48750*

0.48125*

0.47500*

0.46875*

0.46250*

0.45625*

0.45000*

0.44375*

0.43750*

0.43125*

0.42500*

0.41875*

0.41250*

0.40625*

0.40000*

0.39375*

0.38750*

0.38125*

0.37500*

0.36875*

0.36250*

0.35625*

SVID[6:0]

1100_1000

1100_1001

1100_1010

1100_1011

1100_1100

1100_1101

1100_1110

1100_1111

1101_0000

1101_0001

1101_0010

1101_0011

1101_0100

1101_0101

1101_0110

1101_0111*

1101_1000

1101_1001

1101_1010

1101_1011

1101_1100

1101_1101

1101_1110

1101_1111

VOLTAGE (V)

0.30000*

0.29375*

0.28750*

0.28125*

0.27500*

0.26875*

0.26250*

0.25625*

0.25000*

0.24375*

0.23750*

0.23125*

0.22500*

0.21875*

0.21250*

0.20625*

0.20000*

0.19375*

0.18750*

0.18125*

0.17500*

0.16875*

0.16250*

0.15625*

SVID[6:0]

VOLTAGE (V)

0.10000*

0.09375*

0.08750*

0.08125*

0.07500*

0.06875*

0.06250*

0.05625*

0.05000*

0.04375*

0.03750*

0.03125*

0.02500*

0.01875*

0.01250*

0.00625*

OFF*

1000_1000

1000_1001

1000_1010

1000_1011

1000_1100

1000_1101

1000_1110

1000_1111

1001_0000

1001_0001

1001_0010

1001_0011

1001_0100

1001_0101

1001_0110

1001_0111

1001_1000

1001_1001

1001_1010

1001_1011

1001_1100

1001_1101

1001_1110

1001_1111

1010_1000

1010_1001

1010_1010

1010_1011

1010_1100

1010_1101

1010_1110

1010_1111

1011_0000

1011_0001

1011_0010

1011_0011

1011_0100

1011_0101

1011_0110

1011_0111

1011_1000

1011_1001

1011_1010

1011_1011

1011_1100

1011_1101

1011_1110

1011_1111

1110_1000

1110_1001

1110_1010

1110_1011

1110_1100

1110_1101

1110_1110

1110_1111

1111_0000

1111_0001

1111_0010

1111_0011

1111_0100

1111_0101

1111_0110

1111_0111

1111_1000

1111_1001

1111_1010

1111_1011

1111_1100

1111_1101

1111_1110

1111_1111

OFF*

NOTE: * Indicates a VID not required for AMD Family 10h processors. Loosened AMD requirements at these levels.

FN8566 Rev 1.00

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Page 20 of 35

ISL95712

VID

Bit [0]

VID Bits [7:1]

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

SVC

SVD

ACK

FIGURE 16. SVD PACKET STRUCTURE

SVI Bus Protocol

Power States

The AMD processor bus protocol is similar to SMBus send byte

protocol for VID transactions. The AMD SVD packet structure is

shown in Figure 16. The description of each bit of the three bytes

that make up the SVI command are shown in Table 8. During a

transaction, the processor sends the start sequence followed by

each of the three bytes, which end with an optional acknowledge

bit. The ISL95712 does not drive the SVD line during the ACK bit.

Finally, the processor sends the stop sequence. After the

ISL95712 has detected the stop, it can then proceed with the

commanded action from the transaction.

SVI2 defines two power state indicator levels, see Tables 1, 2,

and 9. As processor current consumption is reduced, the power

state indicator level changes to improve VR efficiency under low

power conditions.

For the Core VR operating in 4-phase mode (when PSI0_L is

asserted) Channels 3 and 4 are tri-stated. The controller

continues to operate in 2-phase CCM. The shedding of phases

improves the efficiency of the VR at the light to moderate load

levels of the CPU in this power state. When PSI1_L is asserted

the Core VR sheds Channel 2. If there is a corresponding VID

change, then the output is moved to the new VID level while in

single phase DE mode. Once the output is at the proper VID level,

Channel 1 enters diode emulation mode to further boost

light-load efficiency in this power state.

TABLE 8. SVD DATA PACKET

BITS

1:5

6

DESCRIPTION

Always 11000b

Core domain selector bit, if set then the following data byte

contains VID, power state, telemetry control, load line trim

and offset trim apply to the Core VR.

For the Northbridge VR operating in 3-phase mode, when PSI0_L

is asserted, Channels 2 and 3 are tri-stated while Channel 1

continues in continuous conduction mode. When PSI1_L is

asserted, the output is moved to the new VID level if one is

commanded and Channel 1 then enters diode emulation mode

to conserve power.

7

Northbridge domain selector bit, if set then the following data

byte contains VID, power state, telemetry control, load line

trim and offset trim apply to the Northbridge VR.

8

9

Always 0b

It is possible for the processor to assert or deassert PSI0_L and

PSI1_L out of order. PSI0_L takes priority over PSI1_L. If PSI0_L

is deasserted while PSI1_L is still asserted, the ISL95712 will

return the selected VR back full channel CCM operation. For

example, if the Core VR is configured for 4-Phase operation and

both PSI0_L and PSI1_L are asserted low during a command, the

VR will shed three phases and operate in 1-Phase DE mode. If an

SVI command follows which takes PSI0_L high, but leaves

PSI1_L low, the VR will exit power savings mode and being

operation in 4-Phase CCM mode.

Acknowledge bit

PSI0_L

10

11:17 VID code bits [7:1]

18

19

20

21

Acknowledge bit

VID code bit [0]

PSI1_L

TFN (Telemetry Functionality)

TABLE 9. PSI0_L AND PSI1_L DEFINITION

22:24 Load line slope trim

25:26 Offset Trim [1:0]

FUNCTION BIT

DESCRIPTION

PSI0_L

PSI1_L

10 Power State Indicate level 0. When this signal is

asserted (active Low), the processor is in a low

enough power state for the ISL95712 to take action

to boost efficiency by dropping phases.

27

Acknowledge bit

20 Power State Indicate level 1. When this signal is

asserted (active Low), the processor is in a low

enough power state for the ISL95712 to take action

to boost efficiency by dropping phases and entering

1-Phase DE.

FN8566 Rev 1.00

November 2, 2015

Page 21 of 35

ISL95712

Dynamic Load Line Slope Trim

Telemetry

The ISL95712 supports the SVI2 ability for the processor to

manipulate the load line slope of the Core and Northbridge VRs

independently using the serial VID interface. The slope

manipulation applies to the initial load line slope. A load line

slope trim will typically coincide with a VOTF change. See

Table 10 for more information about the load line slope trim

feature of the ISL95712. The Disable LL selection is not

recommended unless operation without a LL is required and

considered during the compensation of the VR.

The ISL95712 can provide voltage and current information to the

AMD CPU through the telemetry system outlined by the AMD

SVI2 specification. The telemetry data is transmitted through the

SVC and SVT lines of the SVI2 interface.

Current telemetry is based on a voltage generated across a

133kΩ resistor placed from the IMON pin to GND. The current

flowing out of the IMON pin is proportional to the load current in

the VR. The I

current defined in “Voltage Regulation and Load

sum

Line Implementation” on page 12, provides the base conversion

from the load current to the internal amplifier created I

TABLE 10. LOAD LINE SLOPE TRIM DEFINITION

sum

current. The I

sum

current is then divided down by a factor of 4 to

LOAD LINE SLOPE TRIM [2:0]

DESCRIPTION

create the IMON current, which flows out of the IMON pin. The

current will measure 36µA when the load current is at full

000

001

010

011

100

101

110

111

Disable LL

I

sum

load based on a droop current designed for 45µA at the same

load current. The difference between the I current and the

-40% mΩ Change

-20% mΩ Change

No Change

sum

droop current is provided in Equation 2. The IMON current will

measure 11.25µA at full load current for the VR and the IMON

voltage will be 1.2V. The load percentage, which is reported by

the IC is based on the this voltage. When the load is 25% of the

full load, the voltage on the IMON pin will be 25% of 1.2V or 0.3V.

+20% mΩ Change

+40% mΩ Change

+60% mΩ Change

+80% mΩ Change

The SVI interface allows the selection of no telemetry, voltage

only, or voltage and current telemetry on either or both of the VR

outputs. The TFN bit along with the Core and Northbridge domain

selector bits are used by the processor to change the

Dynamic Offset Trim

functionality of telemetry, see Table 12 for more information.

The ISL95712 supports the SVI2 ability for the processor to

manipulate the output voltage offset of the Core and Northbridge

VRs. This offset is in addition to any output voltage offset set via

the COMP resistor reader. The dynamic offset trim can disable

the COMP resistor programmed offset of either output when

Disable All Offset is selected.

TABLE 12. TFN TRUTH TABLE

TFN, CORE, NB

BITS [21, 6, 7]

1,0,1

DESCRIPTION

Telemetry is in voltage and current mode. Therefore,

voltage and current are sent for VDD and VDDNB

domains by the controller.

TABLE 11. OFFSET TRIM DEFINITION

1,0,0

Telemetry is in voltage mode only. Only the voltage of

VDD and VDDNB domains is sent by the controller.

OFFSET TRIM [1:0]

DESCRIPTION

Disable All Offset

-25mV Change

0mV Change

00

01

10

11

1,1,0

1,1,1

Telemetry is disabled.

Reserved

+25mV Change

FN8566 Rev 1.00

November 2, 2015

Page 22 of 35

ISL95712

PMBus Interface

The ISL95712 includes a PMBus interface, which allows for user

programmability of numerous operating parameters and for

monitoring various parameters of the Core and NB regulators.

The PMBus address for the ISL95712 is 1001111.

TABLE 13. PMBus READ AND WRITE REGISTERS

COMMAND

CODE

ACCESS

R

DEFAULT

01h

COMMAND NAME

DESCRIPTION

9Bh

D0h

D1h

D2h

MANUFACTURER REVISION

Silicon revision starts at 01h

Reserved

R/W

00h

FAULT_STATUS_2

BIT VALUE

BIT

0

1

5 (Read Only)

ISL95712 Enabled

ISL95712 Fault

Disabled

4

3

2

1

0

No Fault

Core OV

NB OV

Core OCP

NB OCP

CML. Indicates that an

unsupported command

is received or a write

commandtoaread-only

register or PEC does not

match

D3h

D4h

D5h

D6h

D7h

D8h

D9h

DAh

DBh

DCh

DDh

DEh

R

xxh

READ_VOUT_CORE

READ_IOUT_CORE

Read the Core Voltage in ADC format. Each LSB is 6.25mV

Read Core Current in ADC format. FFh = 100% (7.5µA on IMON)

Reserved

R

xxh

READ_VOUT_NB

READ_IOUT_NB

Read the NB voltage in ADC format. Each LSB is 6.25mV

Read NB load current in ADC format. FFh = 100% (7.5µA on IMON)

Reserved

R/W

00h

LOCK_SVID

BIT[0] VALUE

0

FUNCTIONALITY

Execute SVI2 Commands. PMBus commands DFh

through E4h are not executed. These registers can

still be read and written to.

1

Execute PMBus commands DFh through E4h

while ignoring SVI2 commands.

DFh

E0h

R/W

08h

00h

SET_VID_CORE

OFFSET_CORE

Set Core VID, default set to 800mV. Each LSB is 6.25mV. Metal VID

level is determined by SVC/SVD logic levels at power-up.

Set Core offset. The offset range is from -250mV to +200mV. This is a

2’s complement number. Bit[7] is the sign bit.

FN8566 Rev 1.00

November 2, 2015

Page 23 of 35

ISL95712

TABLE 13. PMBus READ AND WRITE REGISTERS (Continued)

COMMAND NAME

COMMAND

CODE

ACCESS

R/W

DEFAULT

0fh

DESCRIPTION

FUNCTIONALITY

E1h

LOADLINE_PWRSTATE_CORE

BIT

[4:2]

Load line slope trim. Refer to Table 10 for proper

usage.

1

0

Sets PSI0 power state. Refer to Table 9 for proper

usage.

Sets PSI1 power state. Refer to Table 9 for proper

usage.

E2h

E3h

E4h

R/W

08h

00h

0fh

SET_VID_NB

OFFSET_NB

Set NB VID, default set to 800mV. Each LSB is 6.25mV. Metal VID level

is determined by SVC/SVD logic levels at power-up.

Set NB offset. The offset range is from -250mV to +200mV. This is a

2’s complement number. Bit[7] is the sign bit.

LOADLINE_PWRSTATE_NB

BIT

FUNCTIONALITY

[4:2]

Load line slope trim. Refer to Table 10 for proper

usage.

1

0

Sets PSI0 power state. Refer to Table 9 for proper

usage.

Sets PSI1 power state. Refer to Table 9 for proper

usage.

When the voltage on the IMON pin meets the overcurrent

threshold of 1.5V, this triggers an OCP event. Within 2µs of

detecting an OCP event, the controller asserts VR_HOT_L low to

communicate to the AMD CPU to throttle back. A fault timer

begins counting while IMON is at or above the 1.5V threshold. The

fault timer lasts 7.5µs to 11µs and then the controller takes action

by tri-stating the active channels. This provides the CPU time to

recover and reduce the load current. If the OCP conditions are

relieved, then the fault timer is cleared and VR_HOT_L is taken

high clearing the fault condition. If the load current is not reduced

and the OCP condition is maintained, the output voltage will fall

below the undervoltage threshold due to the lack of switching or a

way-overcurrent fault could occur. Either of these fault conditions

will cause the controller to drop PGOOD of that output. When

PGOOD is taken low, a fault flag from this VR is sent to the other

VR and it is shut down within 10µs and PGOOD of the other output

is taken low.

Protection Features

Core VR and Northbridge VR both provide overcurrent,

current-balance, undervoltage and overvoltage fault protections.

The controller also provides over-temperature protection. The

following discussion is based on Core VR and also applies to the

Northbridge VR.

Overcurrent

The IMON voltage provides a means of determining the load

current at any moment in time. The Overcurrent Protection (OCP)

circuitry monitors the IMON voltage to determine when a fault

occurs. Based on the previous description in “Voltage Regulation

and Load Line Implementation” on page 12, the current which

flows out of the IMON pin is proportional to the I

current. The

current is created from the sensed voltage across C , which is

sum

I

sum

n

a measure of the load current based upon the sensing element

selected. The IMON current is generated internally and is 1/4 of

The ISL95712 also features a Way-Overcurrent [WOC] feature,

which immediately takes the controller into shutdown. This

protection is also referred to as fast overcurrent protection for

short-circuit protection. If the IMON current reaches 15µA, WOC is

triggered. Active channels are tri-stated and the controller is

placed in shutdown and PGOOD is pulled low. There is no fault

timer on the WOC fault, the controller takes immediate action. The

other controller output is also shut down within 10µs.

the I

current. The EDC or IDDspike current value for the AMD

sum

CPU load is used to set the maximum current level for droop and

the IMON voltage of 1.2V, which indicates 100% loading for

telemetry. The I

current level at maximum load, or IDDspike, is

sum

36µA and this translates to an IMON current level of 9µA. The

IMON resistor is 133kΩ and the 9µA flowing through the IMON

resistor results in a 1.2V level at maximum loading of the VR.

The overcurrent threshold is 1.5V on the IMON pin. Based on a

1.2V IMON voltage equating to 100% loading, the additional 0.3V

provided above this level equates to a 25% increase in load current

before an OCP fault is detected. The EDC or IDDspike current is

used to set the 1.2V on IMON for full load current. Thus the OCP

level is 1.25 times the EDC or IDDspike current level. This

additional margin above the EDC or IDDspike current allows the

AMD CPU to enter and exit the IDDspike performance mode

without issue unless the load current is out of line with the

IDDspike expectation, thus the need for overcurrent protection.

Current-Balance

The controller monitors the ISENx pin voltages to determine

current-balance protection. If the ISENx pin voltage difference is

greater than 9mV for 1ms, the controller will declare a fault and

latch off.

FN8566 Rev 1.00

November 2, 2015

Page 24 of 35

ISL95712

Undervoltage

If the VSEN voltage falls below the output voltage VID value plus

any programmed offsets by -325mV, the controller declares an

undervoltage fault. The controller deasserts PGOOD and

tri-states the power MOSFETs.

INTERNAL TO

ISL95712

+V

VR_HOT_L

30µA

R

Overvoltage

If the VSEN voltage exceeds the output voltage VID value plus any

programmed offsets by +325mV, the controller declares an

overvoltage fault. The controller deasserts PGOOD and turns on

the low-side power MOSFETs. The low-side power MOSFETs

remain on until the output voltage is pulled down below the VID

set value. Once the output voltage is below this level, the lower

gate is tri-stated. If the output voltage rises above the overvoltage

threshold again, the protection process is repeated. This behavior

provides the maximum amount of protection against shorted

high-side power MOSFETs while preventing output ringing below

ground.

NTC

MONITOR

R

p

+

NTC

V

R

NTC

-

WARNING SHUTDOWN

640mV 580mV

R

s

FIGURE 17. CIRCUITRY ASSOCIATED WITH THE THERMAL MONITOR

FEATURE OF THE ISL95712

As the board temperature rises, the NTC thermistor resistance

decreases and the voltage at the NTC pin drops. When the

voltage on the NTC pin drops below the over-temperature trip

threshold, then VR_HOT is pulled low. The VR_HOT signal is used

to change the CPU operation and decrease power consumption.

With the reduction in power consumption by the CPU, the board

temperature decreases and the NTC thermistor voltage rises.

Once the over-temperature threshold is tripped and VR_HOT is

taken low, the over-temperature threshold changes to the reset

level. The addition of hysteresis to the over-temperature

threshold prevents nuisance trips. Once both pin voltages exceed

the over-temperature reset threshold, the pull-down on VR_HOT

is released. The signal changes state and the CPU resumes

normal operation. The over-temperature threshold returns to the

trip level.

Thermal Monitor [NTC, NTC_NB]

The ISL95712 features two thermal monitors using an external

resistor network, which includes an NTC thermistor to monitor

motherboard temperature and alert the AMD CPU of a thermal

issue. Figure 17 shows the basic thermal monitor circuit on the

Core VR NTC pin. The Northbridge VR features the same thermal

monitor. The controller drives a 30µA current out of the NTC pin

and monitors the voltage at the pin. The current flowing out of

the NTC pin creates a voltage that is compared to a warning

threshold of 640mV. When the voltage at the NTC pin falls to this

warning threshold or below, the controller asserts VR_HOT_L to

alert the AMD CPU to throttle back load current to stabilize the

motherboard temperature. A thermal fault counter begins

counting toward a minimum shutdown time of 100µs. The

thermal fault counter is an up/down counter, so if the voltage at

the NTC pin rises above the warning threshold, it will count down

and extend the time for a thermal fault to occur. The warning

threshold does have 20mV of hysteresis.

Table 14 summarizes the fault protections.

TABLE 14. FAULT PROTECTION SUMMARY

FAULT DURATION

BEFORE

PROTECTION

FAULT

RESET

If the voltage at the NTC pin continues to fall down to the

shutdown threshold of 580mV or below, the controller goes into

shutdown and triggers a thermal fault. The PGOOD pin is pulled

low and tri-states the power MOSFETs. A fault on either side will

shutdown both VRs.

FAULT TYPE

Overcurrent

PROTECTION ACTION

7.5µs to 11.5µs PWM tri-state

1ms

Phase Current

Unbalance

PWM tri-state, PGOOD

latched low

Way-Overcurrent

(1.5xOC)

ENABLE

toggle or

VDD

Undervoltage

-325mV

PGOOD latched low.

PWM tri-state.

Immediately

100µs min

toggle

Overvoltage

+325mV

PGOOD latched low.

Actively pulls the output

voltage to below VID

value, then tri-state.

NTC Thermal

PGOOD latched low.

PWM tri-state.

FN8566 Rev 1.00

November 2, 2015

Page 25 of 35

ISL95712

and R connected to the pads to accurately sense the inductor

Fault Recovery

o

current by sensing the DCR voltage drop. The R

and R

sum

o

All of the previously described fault conditions can be reset by

bringing ENABLE low or by bringing VDD below the POR

threshold. When ENABLE and VDD return to their high operating

levels, the controller resets the faults and soft-start occurs.

resistors are connected in a summing network as shown and

feed the total current information to the NTC network (consisting

of R

, R and R ) and capacitor C . R is a negative

ntcs ntc

p

n

ntc

temperature coefficient (NTC) thermistor, used to temperature

compensate the inductor DCR change.

Interface Pin Protection

The inductor output side pads are electrically shorted in the

schematic but have some parasitic impedance in actual board

layout, which is why one cannot simply short them together for

the current-sensing summing network. It is recommended to use

The SVC and SVD pins feature protection diodes, which must be

considered when removing power to VDD and VDDIO, but leaving

it applied to these pins. Figure 18 shows the basic protection on

the pins. If SVC and/or SVD are powered but VDD is not, leakage

current will flow from these pins to VDD.

1Ω~10ΩR to create quality signals. Since R value is much

o

smaller than the rest of the current sensing circuit, the following

analysis ignores it.

The summed inductor current information is presented to the

INTERNAL TO

ISL95712

capacitor C . Equations 22 through 26 describe the frequency

n

domain relationship between inductor total current I (s) and C

o

n

VDD

voltage V (s):

Cn











R

DCR

------------------------------------------ -------------

ntcnet

V

R

s =



 I s  A s

SVC, SVD





(EQ. 22)

Cn

o

cs

R

N

sum

N

--------------

+

R

ntcnet

R

+ R   R

ntc p

ntcs

----------------------------------------------------

=

(EQ. 23)

(EQ. 24)

GND

ntcnet

R

+ R

ntc p

ntcs

s

------

1 +



L

FIGURE 18. PROTECTION DEVICES ON THE SVC AND SVD PINS

----------------------

1 +

A

s =

cs

L

s

------------



sns

Key Component Selection

Inductor DCR Current-Sensing Network

DCR

-------------

=



(EQ. 25)

(EQ. 26)

L

1

PHASE1 PHASE2 PHASE3 PHASE4

R_SUM

--------------------------------------------------------

=

sns

R

sum

N

--------------

R



ntcnet

------------------------------------------

 C

R_SUM

n

R

sum

N

--------------

R

+

ntcnet

I_SUM+

R_SUM

Where N is the number of phases.

Transfer function A (s) always has unity gain at DC. The inductor

cs

DCR value increases as the winding temperature increases,

R_NTCS

L

+

giving higher reading of the inductor DC current. The NTC R

CNVCN

-

ntc

R_P

value decrease as its temperature decreases. Proper selection of

, R , R and R parameters ensures that V

R_NTC

R_O

DCR

R

sum ntcs ntc Cn

p

RI

represents the inductor total DC current over the temperature

range of interest.

R_O

I_SUM-

There are many sets of parameters that can properly

temperature-compensate the DCR change. Since the NTC

network and the R

resistors form a voltage divider, V is

sum

always a fraction of the inductor DCR voltage. It is recommended

cn

to have a higher ratio of V to the inductor DCR voltage so the

I_O

cn

droop circuit has a higher signal level to work with.

FIGURE 19. DCR CURRENT-SENSING NETWORK

A typical set of parameters that provide good temperature

compensation are: R

= 3.65kΩ, R = 11kΩ, R = 2.61kΩ

Figure 19 shows the inductor DCR current-sensing network for a

4-phase solution. An inductor current flows through the DCR and

sum

p

ntcs

and R = 10kΩ (ERT-J1VR103J). The NTC network parameters

ntc

may need to be fine tuned on actual boards. One can apply full

creates a voltage drop. Each inductor has two resistors in R

sum

FN8566 Rev 1.00

November 2, 2015

Page 26 of 35

ISL95712

load DC current and record the output voltage reading

i

immediately; then record the output voltage reading again when

the board has reached the thermal steady state. A good NTC

network can limit the output voltage drift to within 2mV. It is

recommended to follow the Intersil evaluation board layout and

current sensing network parameters to minimize engineering time.

o

V

o

V

(s) also needs to represent real-time I (s) for the controller to

Cn

o

achieve good transient response. Transfer function A (s) has a

cs

FIGURE 22. LOAD TRANSIENT RESPONSE WHEN C IS TOO LARGE

pole 

and a zero w . One needs to match  and  so

sns

n

sns

L

A

(s) is unity gain at all frequencies. By forcing  equal to 

cs

L

sns

and solving for the solution, Equation 27 gives C value.

n

i

o

L

i

--------------------------------------------------------------

C

=

L

n

R

sum

N

(EQ. 27)

--------------

R



ntcnet

------------------------------------------

 DCR

R

sum

--------------

R

+

ntcnet

N

V

o

For example, given N = 4, R

sum

= 3.65kΩ, R = 11kΩ,

p

RING

BACK

R

= 2.61kΩ, R = 10kΩ, DCR = 0.88mΩ and L = 0.36µH,

ntcs

ntc

Equation 27 gives C = 0.518µF.

n

FIGURE 23. OUTPUT VOLTAGE RING-BACK PROBLEM

Assuming the compensator design is correct, Figure 20 shows the

expected load transient response waveforms if C is correctly

n

selected. When the load current I

output voltage V

core

has a square change, the

also has a square response.

core

ISUM+

If C value is too large or too small, V (s) does not accurately

Cn

n

represent real-time I (s) and worsens the transient response.

Figure 21 shows the load transient response when C is too

n

o

R_ntcs

+

C_n.1

small. V

sags excessively upon load insertion and may create

core

V_cn

C_n.2

R_p

a system failure. Figure 22 shows the transient response when

C is too large. V is sluggish in drooping to its final value.

-

R_n

R_ntc

n

core

There is excessive overshoot if load insertion occurs during this

time, which may negatively affect the CPU reliability.

ISUM-

R_i

OPTIONAL

i

o

C_ip

R_ip

OPTIONAL

FIGURE 24. OPTIONAL CIRCUITS FOR RING-BACK REDUCTION

V

o

Figure 23 shows the output voltage ring-back problem during load

transient response. The load current i has a fast step change, but

o

FIGURE 20. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS

the inductor current i cannot accurately follow. Instead, i

L

responds in first-order system fashion due to the nature of the

current loop. The ESR and ESL effect of the output capacitors

i

o

makes the output voltage V dip quickly upon load current change.

o

However, the controller regulates V according to the droop current

o

i

, which is a real-time representation of i ; therefore, it pulls

droop

L

V back to the level dictated by i , causing the ring-back problem.

o

L

This phenomenon is not observed when the output capacitor has

very low ESR and ESL, as is the case with all ceramic capacitors.

V

o

Figure 24 shows two optional circuits for reduction of the

ring-back. C is the capacitor used to match the inductor time

constant. It usually takes the parallel of two (or more) capacitors

to get the desired value. Figure 24 shows that two capacitors

n

FIGURE 21. LOAD TRANSIENT RESPONSE WHEN C IS TOO SMALL

n

(C and C ) are in parallel. Resistor R is an optional

n.1 n.2

n

component to reduce the V ring-back. At steady state, C

+

o

n.1

C

provides the desired C capacitance. At the beginning of i

n.2

n o

FN8566 Rev 1.00

November 2, 2015

Page 27 of 35

ISL95712

change, the effective capacitance is less because R increases

n

R

sen

N

(EQ. 28)

(EQ. 29)

-------------

V

A

s =

 I s  A

s

Rsen

the impedance of the C branch. As Figure 21 shows, V tends

n.1

o

Cn

o

to dip when C is too small, and this effect reduces the V

n

o

1

ring-back. This effect is more pronounced when C is much

n.1

----------------------

1 +

s =

Rsen

s

larger than C . It is also more pronounced when R is bigger.

n.2

n

------------



However, the presence of R increases the ripple of the V signal

sns

n

if C is too small. It is recommended to keep C greater than

n.2 n.2

1

----------------------------



=

2200pF. R value usually is a few ohms. C , C and R values

n.1 n.2

(EQ. 30)

n

R

sum

N

should be determined through tuning the load transient response

waveforms on an actual board.

--------------

 C

n

Transfer function A

Current-sensing resistor R

variation over-temperature, so there is no need for the NTC

network.

(s) always has unity gain at DC.

Rsen

R

and C form an R-C branch in parallel with R , providing a

ip

value does not have significant

ip

i

sen

lower impedance path than R at the beginning of i change. R

i

o

ip

and C do not have any effect at steady state. Through proper

ip

selection of R and C values, i

ip ip

can resemble i rather than

o

droop

The recommended values are R

sum

= 1kΩ and C = 5600pF.

n

i , and V will not ring back. The recommended value for R is

L

o

ip

100Ω. C should be determined through tuning the load

transient response waveforms on an actual board. The

ip

Overcurrent Protection

Refer to Equation 2 on page 13 and Figures 19 and 25; resistor

R sets the I current, which is proportional to droop current

and IMON current. The OCP threshold is 1.5V on the IMON pin,

recommended range for C is 100pF~2000pF. However, it

ip

should be noted that the R - C branch may distort the i

i

sum

ip ip

droop

waveform. Instead of being triangular as the real inductor

which equates to an IMON current of 11.25µA using a 133kΩ

current, i

affect i

may have sharp spikes, which may adversely

droop

average value detection and therefore may affect

IMON resistor. The corresponding I

is 45µA, which results in

sum

droop

an I

of 56.25µA. At full load current, I

, the I

current

at OCP

sum

OCP accuracy. User discretion is advised.

droop

omax

is 45µA. The ratio of I

sum

is 36µA and the resulting I

droop

Resistor Current-Sensing Network

relative to full load current is 1.25. Therefore, the OCP current

trip level is 25% higher than the full load current.

PHASE1 PHASE2 PHASE3 PHASE4

For inductor DCR sensing, Equation 31 gives the DC relationship

of V (s) and I (s):

cn

o

L













R

DCR

N

ntcnet

------------------------------------------ -------------

V

=



 I

o

DCR

Cn

(EQ. 31)

R

sum

N

--------------

+

R

ntcnet

R_SUM

Substitution of Equation 31 into Equation 2 gives Equation 32:

R

5

4

1

R

DCR

ntcnet

I_SUM+

-- ----- ------------------------------------------ -------------

I

=



 I

(EQ. 32)

droop

o

R

N

i

sum

--------------

+

R

ntcnet

N

+

-

RSEN

VCN

CN

R_i

R_O

Therefore:

R

 DCR  I

o

I_SUM-

5

4

ntcnet

-- ---------------------------------------------------------------------------------



R

=

(EQ. 33)

i

R

sum

N







--------------

N  R

+

 I

ntcnet

droop



Substitution of Equation 23 and application of the OCP condition

in Equation 33 gives Equation 34:

I_O

R

+ R   R

ntc p

ntcs

----------------------------------------------------

 DCR  I

omax

R

+ R

ntc p

5

4

FIGURE 25. RESISTOR CURRENT-SENSING NETWORK

ntcs

-- ----------------------------------------------------------------------------------------------------------------------------

R

=



(EQ. 34)

i

R

+ R   R

R













ntcs

ntc

p

sum

---------------------------------------------------- --------------

N 

+

 I

Figure 25 shows the resistor current-sensing network for a

4-phase solution. Each inductor has a series current sensing

droopmax

R

+ R

p

N

ntcs

ntc

resistor, R . R

accurately capture the inductor current information. The R

and R are connected to the R

pads to

sen sum

o

sen

Where I

is the full load current and I

is the

droopmax

omax

sum

and C

n

corresponding droop current. For example, given N = 4,

= 3.65kΩ, R = 11kΩ, R = 2.61kΩ, R = 10kΩ,

and R resistors are connected to capacitor C . R

o

n

sum

R

sum

DCR = 0.88mΩ, I

p

ntcs ntc

form a filter for noise attenuation. Equations 28 through 30 give

= 100A and I = 45μA.

omax

Equation 34 gives R = 529Ω.

droopmax

the V (s) expression.

Cn

i

FN8566 Rev 1.00

November 2, 2015

Page 28 of 35

ISL95712

For resistor sensing, Equation 35 gives the DC relationship of

source (= VID) and output impedance Z (s). If Z (s) is equal to

out out

V

(s) and I (s).

the load line slope LL, i.e., a constant output impedance, then in

the entire frequency range, V will have a square response when

cn

o

R

sen

-------------

(EQ. 35)

V

=

 I

I has a square change.

Cn

o

N

Substitution of Equation 35 into Equation 2 gives Equation 36:

Z_out(s) = LL

i

o

R

5

4

1

R

sen

N

-- ----- -------------

I

=



 I

(EQ. 36)

droop

o

i

VR

VID

LOAD

V

o

Therefore:

R

 I

o

5

4

sen

(EQ. 37)

-- --------------------------

R

=



i

N  I

droop

FIGURE 26. VOLTAGE REGULATOR EQUIVALENT CIRCUIT

Substitution of Equation 37 and application of the OCP condition

in Equation 33 gives Equation 38:

Intersil provides a Microsoft Excel-based spreadsheet to help

design the compensator and the current sensing network so that

VR achieves constant output impedance as a stable system.

R

 I

omax

5

4

sen

-- --------------------------------------

R

=



(EQ. 38)

i

N  I

droopmax

A VR with active droop function is a dual-loop system consisting of

a voltage loop and a droop loop, which is a current loop. However,

neither loop alone is sufficient to describe the entire system. The

spreadsheet shows two loop gain transfer functions, T1(s) and

T2(s), that describe the entire system. Figure 27 conceptually

shows T1(s) measurement set-up, and Figure 28 conceptually

shows T2(s) measurement set-up. The VR senses the inductor

current, multiplies it by a gain of the load line slope, adds it on top

of the sensed output voltage, and then feeds it to the

compensator. T1 is measured after the summing node, and T2 is

measured in the voltage loop before the summing node. The

spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)

can actually be measured on an ISL95712 regulator.

Where I

is the full load current and I

is the

droopmax

omax

corresponding droop current. For example, given N = 4,

= 1mΩ, I = 100A and I = 45µA, Equation 38

R

sen

omax

droopmax

gives R = 694Ω.

i

Load Line Slope

See Figure 12 for load line implementation.

For inductor DCR sensing, substitution of Equation 32 into

Equation 3 gives the load line slope expression:

V

R

ntcnet

5

4

DCR

-- ------------------ ------------------------------------------ -------------

droop

R

------------------

LL =

=



(EQ. 39)

I

R

sum

N

o

i

--------------

+

R

ntcnet

N

V_O

L

For resistor sensing, substitution of Equation 36 into Equation 3

gives the load line slope expression:

Q1

i_O

V_IN

Q2

GATE

DRIVER

C_OUT

V

R

 R

sen droop

N  R

i

5

4

droop

(EQ. 40)

------------------

-- ---------------------------------------



LL =

=

I

o

Substitution of Equation 33 and rewriting Equation 39, or

substitution of Equation 37 and rewriting Equation 40, gives the

same result as in Equation 41:

LOAD LINE SLOPE

20ꢀΩ

+

I

-

o

EA

----------------

droop

MOD.

R

=

 LL

(EQ. 41)

droop

I

COMP

+

VID

ISOLATION

TRANSFORMER

One can use the full-load condition to calculate R

droop

. For

CHANNEL B

CHANNEL A

example, given I

= 100A, I

= 45µA and

LOOP GAIN =

omax

droopmax

= 4.67kΩ.

LL = 2.1mΩ, Equation 41 gives R

droop

CHANNEL A

CHANNEL B

It is recommended to start with the R

value calculated by

droop

NETWORK

ANALYZER

Equation 41 and fine-tune it on the actual board to get accurate

load line slope. One should record the output voltage readings at

no load and at full load for load line slope calculation. Reading

the output voltage at lighter load instead of full load will increase

the measurement error.

EXCITATION OUTPUT

FIGURE 27. LOOP GAIN T1(s) MEASUREMENT SET-UP

T1(s) is the total loop gain of the voltage loop and the droop loop.

It always has a higher crossover frequency than T2(s), therefore

has a higher impact on system stability.

Compensator

Figure 20 shows the desired load transient response waveforms.

Figure 26 shows the equivalent circuit of a Voltage Regulator

(VR) with the droop function. A VR is equivalent to a voltage

T2(s) is the voltage loop gain with closed droop loop, thus having

a higher impact on output voltage response.

FN8566 Rev 1.00

November 2, 2015

Page 29 of 35

ISL95712

Design the compensator to get stable T1(s) and T2(s) with sufficient

phase margin and an output impedance equal to or smaller than

the load line slope.

INTERNAL TO

ISL95712

L

V

O

+V

Q1

VR_HOT_L

30µA

R

GATE

DRIVER

Q2

I

O

V

IN

C

O

NTC

MONITOR

R

330kΩ

8.45kΩ

NTC

LOAD LINE SLOPE

+

20

+

SHUTDOWN

580mV

WARNING

640mV

R

s

-

EA

MOD.

+

COMP

VID

ISOLATION

TRANSFORMER

FIGURE 29. THERMAL MONITOR FEATURE OF THE ISL95712

CHANNEL B

CHANNEL A

LOOP GAIN =

Selection of the NTC thermistor can vary depending on how the

resistor network is configured. The equivalent resistance at the

typical thermal warning threshold voltage of 0.64V is defined in

Equation 42.

CHANNEL A

CHANNEL B

NETWORK

ANALYZER

EXCITATION OUTPUT

FIGURE 28. LOOP GAIN T2(s) MEASUREMENT SET-UP

0.64V

30A

---------------

= 21.3k

(EQ. 42)

Current Balancing

Refer to Figures 13 through 19 for information on current

balancing. The ISL95712 achieves current balancing through

matching the ISEN pin voltages. R

remove the switching ripple of the phase node voltages. It is

recommended to use a rather long R time constant,

The equivalent resistance at the typical thermal shutdown

threshold voltage of 0.58V required to shutdown both outputs is

defined in Equation 43.

and C form filters to

isen

0.58V

30A

---------------

= 19.3k

(EQ. 43)

C

isen isen

such that the ISEN voltages have minimal ripple and represent

the DC current flowing through the inductors. Recommended

The NTC thermistor value correlates to the resistance change

between the warning and shutdown thresholds and the required

temperature change. If the warning level is designed to occur at a

board temperature of +100°C and the thermal shutdown level at

a board temperature of +105°C, then the resistance change of

the thermistor can be calculated. For example, a Panasonic NTC

thermistor with B = 4700 has a resistance ratio of 0.03939 of its

nominal value at +100°C and 0.03308 of its nominal value at

+105°C. Taking the required resistance change between the

thermal warning threshold and the shutdown threshold and

dividing it by the change in resistance ratio of the NTC thermistor

at the two temperatures of interest, the required resistance of

the NTC is defined in Equation 44.

values are R = 10kΩ and C = 0.22µF.

s

Thermal Monitor Component Selection

The ISL95712 features two pins, NTC and NTC_NB, which are

used to monitor motherboard temperature and alert the AMD

CPU if a thermal issues arises. The basic function of this circuitry

is outlined in the “Thermal Monitor [NTC, NTC_NB]” on page 25.

Figure 29 shows the basic configuration of the NTC resistor,

R

, and offset resistor, R , used to generate the warning and

NTC

S

shutdown voltages at the NTC pin.

As the board temperature rises, the NTC thermistor resistance

decreases and the voltage at the NTC pin drops. When the

voltage on the NTC pin drops below the thermal warning

threshold of 0.640V, then VR_HOT_L is pulled low. When the

AMD CPU detects VR_HOT_L has gone low, it will begin throttling

back load current on both outputs to reduce the board

temperature.

21.3k – 19.3k

0.03939 – 0.03308

(EQ. 44)

-----------------------------------------------------

= 317k

The closest standard thermistor to the value calculated with

B = 4700 is 330kΩ. The NTC thermistor part number is

ERTJ0EV334J. The actual resistance change of this standard

thermistor value between the warning threshold and the

shutdown threshold is calculated in Equation 45.

If the board temperature continues to rise, the NTC thermistor

resistance will drop further and the voltage at the NTC pin could

drop below the thermal shutdown threshold of 0.580V. Once this

threshold is reached, the ISL95712 shuts down both Core and

Northbridge VRs indicating a thermal fault has occurred prior to

the thermal fault counter triggering a fault.

(EQ. 45)

330k  0.03939 – 330k  0.03308 = 2.082k

FN8566 Rev 1.00

November 2, 2015

Page 30 of 35

ISL95712

Since the NTC thermistor resistance at +105°C is less than the

required resistance from Equation 43, additional resistance in

series with the thermistor is required to make up the difference.

A standard resistor, 1% tolerance, added in series with the

thermistor will increase the voltage seen at the NTC pin. The

additional resistance required is calculated in Equation 46.

important to have a symmetrical layout for each power train,

preferably with the controller located equidistant from each

power train. Symmetrical layout allows heat to be dissipated

equally across all power trains. Keeping the distance between

the power train and the control IC short helps keep the gate drive

traces short. These drive signals include the LGATE, UGATE,

PGND, PHASE and BOOT.

19.3k – 10.916k = 8.384k

(EQ. 46)

GND

VIAS TO

GROUND

The closest, standard 1% tolerance resistor is 8.45kΩ.

OUTPUT

CAPACITORS

PLANE

The NTC thermistor is placed in a hot spot on the board, typically

near the upper MOSFET of Channel 1 of the respective output.

The standard resistor is placed next to the controller.

SCHOTTKY

DIODE

VOUT

PHASE

NODE

LOW-SIDE

MOSFETs

INDUCTOR

Layout Guidelines

PCB Layout Considerations

HIGH-SIDE

MOSFETs

INPUT

CAPACITORS

VIN

FIGURE 30. TYPICAL POWER COMPONENT PLACEMENT

POWER AND SIGNAL LAYERS PLACEMENT ON THE PCB

As a general rule, power layers should be close together, either

on the top or bottom of the board, with the weak analog or logic

signal layers on the opposite side of the board. The ground-plane

layer should be adjacent to the signal layer to provide shielding.

When placing MOSFETs, try to keep the source of the upper

MOSFETs and the drain of the lower MOSFETs as close as

thermally possible (see Figure 30). Input high-frequency

capacitors should be placed close to the drain of the upper

MOSFETs and the source of the lower MOSFETs. Place the output

inductor and output capacitors between the MOSFETs and the

load. High-frequency output decoupling capacitors (ceramic)

should be placed as close as possible to the decoupling target

(microprocessor), making use of the shortest connection paths to

any internal planes. Place the components in such a way that the

area under the IC has less noise traces with high dV/dt and di/dt,

such as gate signals and phase node signals.

COMPONENT PLACEMENT

There are two sets of critical components in a DC/DC converter;

the power components and the small signal components. The

power components are the most critical because they switch

large amounts of energy. The small signal components connect

to sensitive nodes or supply critical bypassing current and signal

coupling.

The power components should be placed first and these include

MOSFETs, input and output capacitors, and the inductor. It is

Table 15 shows layout considerations for the ISL95712

controller by pin.

TABLE 15. LAYOUT CONSIDERATIONS FOR THE ISL95712 CONTROLLER

PIN NUMBER

BOTTOM PAD

SYMBOL

GND

LAYOUT GUIDELINES

Connect this ground pad to the ground plane through a low impedance path. A minimum of 5 vias are recommended to

connect this pad to the internal ground plane layers of the PCB.

1

ISEN3_NB Each ISEN pin has a capacitor (C

) decoupling it to VSUMN_NB, then through another capacitor (C

isen

) to GND.

vsumn_nb

Place C

capacitors as close as possible to the controller and keep the following loops small:

isen

1. Any ISENx_NB pin to another ISENx_NB pin

2. Any ISENx_NB pin to GND

2

NTC_NB

The NTC thermistor must be placed close to the thermal source that is monitored to determine Northbridge thermal

throttling. Placement at the hottest spot of the Northbridge VR is recommended. Additional standard resistors in the

resistor network on this pin should be placed near the IC.

3

4

IMON_NB Place the IMON_NB resistor close to this pin and make a tight GND connection.

SVC Use good signal integrity practices and follow AMD recommendations.

VR_HOT_L Follow AMD recommendations. Placement of the pull-up resistor near the IC is recommended.

5

6

SVD

VDDIO

SVT

Use good signal integrity practices and follow AMD recommendations.

No special considerations.

7

8

9

ENABLE

PWROK

IMON

10

11

Use good signal integrity practices and follow AMD recommendations.

Place the IMON resistor close to this pin and make a tight GND connection.

FN8566 Rev 1.00

November 2, 2015

Page 31 of 35

ISL95712

TABLE 15. LAYOUT CONSIDERATIONS FOR THE ISL95712 CONTROLLER (Continued)

LAYOUT GUIDELINES

PIN NUMBER

12

SYMBOL

NTC

The NTC thermistor must be placed close to the thermal source that is monitored to determine Core thermal throttling.

Placement at the hottest spot of the Core VR is recommended. Additional standard resistors in the resistor network on

this pin should be placed near the IC.

13

14

15

16

ISEN4

ISEN3

ISEN2

ISEN1

Each ISEN pin has a capacitor (C

) decoupling it to V

SUMN

and then through another capacitor (C ) to GND. Place

vsumn

isen

capacitors as close as possible to the controller and keep the following loops small:

C

isen

1. Any ISEN pin to another ISEN pin

2. Any ISEN pin to GND

The red traces in the following drawing show the loops to be minimized.

P hase1

L ₃

R _isen

R _o

IS E N 4

IS E N 3

IS E N 2

C _isen

P hase 1

R _isen

L ₃

L₂

L ₁

R _o

V

P hase 2

R _isen

P hase 3

R _isen

IS E N 1

G N D

V _{S U M N}

C _{vsu m n}

17

18

ISUMP

ISUMN

Place the current sensing circuit in general proximity of the controller.

Place capacitor C very close to the controller.

Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.

n

Each phase of the power stage sends a pair of V

in parallel fashion with decent width (>20mil).

and V

signals to the controller. Run these two signals traces

SUMP

SUMN

IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on

a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed

on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two

preferred ways of routing current sensing traces.

INDUCTOR

VIAS

CURRENT-SENSING TRACES

19

20

21

22

VSEN

RTN

FB

Place the filter on these pins in close proximity to the controller for good coupling.

Place the compensation components in general proximity of the controller.

VDD

A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close

proximity to the pin with the filter resistor nearby the IC.

23

24

25

PGOOD

COMP

No special consideration.

Place the compensation components in general proximity of the controller.

Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.

BOOT1

FN8566 Rev 1.00

November 2, 2015

Page 32 of 35

ISL95712

TABLE 15. LAYOUT CONSIDERATIONS FOR THE ISL95712 CONTROLLER (Continued)

LAYOUT GUIDELINES

PIN NUMBER

SYMBOL

PHASE1

UGATE1

26

27

These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing

these signals near sensitive analog signal traces or crossing over them. Routing PHASE1 to the Core VR Channel 1 high-side

MOSFET source pin instead of a general connection to PHASE1 copper is recommended for better performance.

28

29

30

31

LGATE1

BOOT2

Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.

Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.

PHASE2

UGATE2

These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing

these signals near sensitive analog signal traces or crossing over them. Routing PHASE2 to the Core VR Channel 2 high-side

MOSFET source pin instead of a general connection to PHASE2 copper is recommended for better performance.

32

VDDP

A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close

proximity to the pin.

33

34

35

36

LGATE2

Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.

LGATE1_NB Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.

PHASE1_NB These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing

these signals near sensitive analog signal traces or crossing over them. Routing PHASE1_NB to the high-side MOSFET

UGATE1_NB

source pin instead of a general connection to the PHASE1_NB copper is recommended for better performance.

37

38

39

40

41

42

43

44

45

46

47

48

49

50

BOOT1_NB Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.

PWM3

PWM4

No special considerations.

PWM2_NB No special considerations.

PWM3_NB No special considerations.

I2CLK

I2DATA

PROG

Use good signal integrity practices

No special considerations.

PGOOD_NB No special consideration.

COMP_NB Place the compensation components in general proximity of the controller.

FB_NB

VSEN_NB Place the filter on this pin in close proximity to the controller for good coupling.

ISUMN_NB Place the current sensing circuit in general proximity of the controller.

Place capacitor C very close to the controller.

Place the NTC thermistor next to NB VR Channel 1 inductor so it senses the inductor temperature correctly.

n

ISUMP_NB

Each phase of the power stage sends a pair of V

in parallel fashion with decent width (>20mil).

and V

signals to the controller. Run these two signals traces

SUMP

SUMN

IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on

a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed

on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two

preferred ways of routing current sensing traces.

INDUCTOR

VIAS

CURRENT-SENSING TRACES

51

52

ISEN1_NB Each ISEN pin has a capacitor (C

) decoupling it to VSUMN_NB, then through another capacitor (C

) to GND.

vsumn_nb

isen

Place C

isen

capacitors as close as possible to the controller and keep the following loops small:

ISEN2_NB

1. Any ISENx_NB pin to another ISENx_NB pin

2. Any ISENx_NB pin to GND

FN8566 Rev 1.00

November 2, 2015

Page 33 of 35

ISL95712

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest revision.

DATE

REVISION

CHANGE

November 2, 2015

FN8566.1 On page 1 under Features, added “Serial VID clock frequency range 100kHz to 25MHz” below “Supports AMD SVI

2.0 serial data bus interface and PMBus”.

Updated Package Outline Drawing L52.6X6A to the latest revision. Changes are as follows:

-Added tolerance ± values.

March 26, 2014

FN8566.0 Initial Release

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8566 Rev 1.00

November 2, 2015

Page 34 of 35

ISL95712

Package Outline Drawing

L52.6X6A

52 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE CHAMFERED CORNER LEADS

Rev 1, 7/14

4X 4.8

48X 0.40

6.00 ± 0.05

A

6

B

PIN #1

INDEX AREA

40

52

1

6

39

PIN 1

INDEX AREA

4.70 ± 0.10

27

13

(4X)

0.15

14

26

4X SEE

DETAIL "Y"

0.10

0.05

C A B

C

TOP VIEW

52x0.40

BOTTOM VIEW

4

52x0.20

SEE DETAIL "X"

0.10 C

SEATING PLANE

0.08 C

C

(5.80 TYP)

0.900 ±0.10

(

4.70)

SIDE VIEW

(48x0.40)

R0.100 TYP.

(52x0.20)

(52x0.60)

0.165 TYP.

5

C

0.2 REF

0.00 MIN.

0.05 MAX.

0.165 TYP

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

DETAIL "Y"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

3.

4.

Unless otherwise specified, tolerance: Decimal ± 0.05

Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN8566 Rev 1.00

November 2, 2015

Page 35 of 35


型号：	ISL95712HRZ
厂家：	RENESAS TECHNOLOGY CORP
描述：	Multiphase PWM Regulator for AMD Fusionâ¢ Desktop CPUs Using SVI 2.0 开关
文件：	总35页 (文件大小：1616K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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