ISL98608_技术文档

DATASHEET

ISL98608IIH

High Efficiency Single Inductor Positive/Negative Power Supply

FN8724

Rev.2.00

Sep 26, 2017

The ISL98608IIH is a high efficiency power supply for small

Features

size displays, such as smart phones and tablets requiring

±supply rails. It integrates a boost regulator, LDO, and inverting

charge pump that are used to generate two output rails:

+5V (default) and -6 (default). The ±5V output voltages can be

• Two outputs:

- VP = +5V (default)

- VN = -5V (default)

2

adjusted from ±4.5V up to ±7V with 50mV steps using the I C

• 2.5V to 5.5V input voltage range

interface.

• ±4.5 to ±7V wide output range

The device integrates synchronous rectification MOSFETs for

the boost regulator and inverting charge pump, which

maximizes conversion efficiency.

• Supports 200mA current between VP and VN

• >89% efficiency with 12mA load between VP and VN

2

The ISL98608IIH integrates all compensation and feedback

components, which minimizes BOM count and reduces the

solution PCB size to 18mm .

• 18mm solution PCB area

• Fully integrated FETs for synchronous rectification

• Integrated compensation and feedback circuits

2

The input voltage range, high efficiency operation and very low

shutdown current make the device ideal for use in single cell

Li-ion battery operated applications.

2

• I C adjustable output voltages and settings

• Integrated VP/VN discharge resistors

• 1µA shutdown supply current

The ISL98608IIH is offered in a 1.744mm x1.744mm WLCSP

package, and the device is specified for operation across the

-40°C to +85°C ambient temperature range.

• Programmable turn-on and turn-off sequencing

• 1.744mm x1.744mm, 4x4 array WLCSP with 0.4mm pitch

Applications

• TFT-LCD smart phone displays

• Small size/handheld displays

• Hi-Fi audio amplifier supply

Typical Application Circuits

VIN

2.5V TO 5.5V

L

1

VIN

C_IN

LXP

SCL

SDA

VBSTCP

VBST

PROCESSOR

ENP

C_VBST

ENN

CP

CN

C_CP

ISL98608IIH

C_VN

-5V

VN

NEGATIVE SUPPLY

POSITIVE SUPPLY

VSUB

LCD PANEL

VP

+5V

AGND

PGND

C_VP

FIGURE 1. TYPICAL APPLICATION CIRCUIT: TFT-LCD SMART PHONE DISPLAY

FN8724 Rev.2.00

Sep 26, 2017

Page 1 of 33

ISL98608IIH

Typical Application Circuits(Continued)

VIN

2.5V TO 5.5V

L

1

VIN

C

IN

LXP

SCL

SDA

ENP

ENN

VBSTCP

VBST

PROCESSOR

C

VBST

CP

CN

ISL98608IIH

C

CP

C

VN

NEGATIVE SUPPLY

VN

VSUB

AMPLIFIER

VP

AGND

PGND

POSITIVE SUPPLY

C

VP

FIGURE 2. TYPICAL APPLICATION CIRCUIT: HI-FI AUDIO AMPLIFIER POWER SUPPLY

Block Diagram

VIN

LXP

VIN

VBSTCP

VBST

CP

VBST

PWM/

PFM

OSCILLATOR

VN

LOGIC

CN

LOGIC

PGND

CURRENT LIMIT

UVP

VN

-60%

UVP

+60%

COMP

VREF

VSUB

COMP

GM

VREF

GM

SCL

I²C CONTROL

DAC

SDA

ENP

ENN

DAC

EN/ SEQUENCING

SETTINGS

VP

LDO

DAC

FIGURE 3. BLOCK DIAGRAM

FN8724 Rev.2.00

Sep 26, 2017

Page 2 of 33

ISL98608IIH

Table of Contents

Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Application Circuit Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2

I C Digital Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Register Descriptions and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Register Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Display Power Supply Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Regulator Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

VP and VN Headroom Voltage and Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Negative Charge Pump Operation (VN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

VN and VBST PFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

VP/VN Output Hi-Z Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power-On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Enable Timing Control Options for VP and VN Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Fault Protection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

General Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

ISL98608IIH Specific Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

ISL98608IIH Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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Sep 26, 2017

Page 3 of 33

ISL98608IIH

Application Circuit Diagram

L1

2.2µH OR 4.7µH

C_VBST

VIN

4.7µF/10V/0603

OR

10µF/10V/0402

1

2

3

4

A

PGND

AGND

VIN

LXP

VBST

VBSTCP

C_VP

4.7µF/10V/0603

OR

10µF/10V/0402

B

C

CP

VP

SCL

VN

ENN

C_CP-CN

4.7µF/10V/0603

OR

VIN

C_VIN

SDA

PGNDCP

PROCESSOR

4.7µF/10V/0603

OR

10µF/10V/0402

D

ENP

VSUB

CN

C_VN

4.7µF/10V/0603

OR

10µF/10V/0402

Ordering Information

PART NUMBER

PART

TEMP RANGE

TAPE AND REEL

(Units)

PACKAGE

(RoHS Compliant)

PKG.

DWG. #

(Notes 1, 2, 3)

MARKING

(°C)

ISL98608IIHZ-T

608H

Evaluation Board

-40 to +85

3k

16 Ball (4x4 bump, 0.4mm pitch) WLCSP

W4x4.16G

ISL98608HEVAL1Z

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets; molding compounds/die attach materials and

SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free

WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), see the product information page for ISL98608IIH. For more information on MSL, see tech brief TB363.

TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS

VIN

(V)

VBST VOLTAGE

(V)

VP VOLTAGE

(V)

VN VOLTAGE

(V)

PART NUMBER

ISL98608

MAXIMUM OUTPUT CURRENT (mA)

2.5 to 5

100

200

5.65

5.4

5.5

5

-5.5

-5

ISL98608IIH

2.5 to 5.5

FN8724 Rev.2.00

Sep 26, 2017

Page 4 of 33

ISL98608IIH

Pin Configuration

ISL98608IIH

(16 BUMP, 4x4 ARRAY, 0.4MM PITCH WLCSP)

TOP VIEW

1.744 mm

1

2

3

4

A

LXP

PGND

VBST

VBSTCP

VP

ENN

SDA

B

C

AGND

VIN

CP

PGNDCP

CN

SCL

D

VN

ENP

VSUB

Pin Descriptions

PIN NUMBER

PIN NAME

DESCRIPTION

A1

A2

PGND

LXP

Power ground for the boost converter.

Switch node for boost converter. Connect an inductor between the VIN and LXP pins for boost converter

operation.

A3

A4

VBST

Boost Converter Output. The boost converter output supplies the power to the negative charge pump

and LDO. Connect a 4.7µF/0603 or 10µF/0402 capacitor to ground.

VBSTCP

Charge pump input. This pin must be connected to VBST on the PCB, so that the boost regulator

provides the input voltage supply for the charge pump.

B1

B2

B3

B4

C1

C2

C3

C4

D1

D2

D3

AGND

ENN

VP

Analog Ground

VBST and VN enable input. (Note 4)

Positive regulator output. Connect a 4.7µF/0603 or 10µF/0402 capacitor to ground.

Charge pump flying capacitor positive connection. Place a capacitor between CP and CN.

Input supply voltage. Connect a 4.7µF/0603 or 10µF/0402 bypass capacitor from VIN to ground.

CP

VIN

2

SDA

SCL

Serial data connection for I C Interface. If this pin not used, connect this pin to VIN.

2

Serial data connection for I C Interface. If this pin not used, connect this pin to VIN.

PGNDCP

ENP

VSUB

VN

Power ground for the VN regulator.

VBST and VP enable input. (Note 4)

Substrate connection. VSUB must be the most negative potential on the IC, connect VSUB to VN.

Negative charge pump output. Connect a 4.7µF/0603 or 10µF/0402 capacitor to ground. Connecting

either two 4.7µF/0603 or 10µF/0402 capacitors to ground will lower the negative charge pump

output voltage ripple.

D4

CN

Charge pump flying capacitor negative connection. Place a capacitor between CP and CN.

NOTE:

4. This pin has 1MΩ (typical) pull-down to AGND.

FN8724 Rev.2.00

Sep 26, 2017

Page 5 of 33

ISL98608IIH

V

Absolute Maximum Ratings

Thermal Information

VBST, VBSTCP, CP, VP to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 8.5V

VN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -8.5V

VIN, SCL, SDA, ENN, ENP to AGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V

LXP to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VBST + 0.3V

CN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VN - 0.3V to PGND + 0.3V

Maximum Average Current

Thermal Resistance (Typical)

4x4 Bump 0.4mm pitch WLCSP (Notes 5, 6)

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493



_JA(°C/W)

76



_JB(°C/W)

18

Out of VBST Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A

Into LXP Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A

Into CN, CP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1A

ESD Rating

Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 3000V

Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 300V

Charged Device Model (Tested per JESD22-C101F). . . . . . . . . . . . 1000V

Latch-up (Tested per JESD78D; Class II) . . . . . . . . . . . . . . . . . . . . . . 100mA

Recommended Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V

VP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +7V

VN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-4.5V to -7V

VBST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.65V to +7.3V

Output Current Maximum (between VP and VN) . . . . . . . . . . . . . . . 200mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

5.  is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

6. For  , the "board temp" is taken on the board near the edge of the package, on a copper trace at the center of one side. See tech brief TB379,

JB

Electrical Specifications

V

= 3.7V, unless otherwise noted. Typical specifications are characterized at T = +25°C unless

A

IN

otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +85°C.

MIN

MAX

PARAMETER

GENERAL

DESCRIPTION

TEST CONDITIONS

(Note 7)

TYP

(Note 7) UNIT

V

Supply Voltage Range

2.5

5.5

V

IN

V

Minimum Supply Voltage (Note 9) At 200mA

3

V

IN

I

Supply Current

ENP = ENN = SDA = SCL = 3.7V

Enabled, LXP not switching

700

µA

IN

I

V

Supply Current when Shutdown ENP = ENN = SDA = SCL = 0V

1

µA

V

SHUTDN

IN

V

Undervoltage Lockout Threshold

Undervoltage Lockout Hysteresis

V

rising

IN

2.32

216

2.44

UVLO

V

mV

UVLO_HYS

BOOST REGULATOR (VBST)

V

VBST Output Voltage

Register 0x06 = 0x00, 10mA load

2.5V < V < 4.6V, Register 0x06 = 0x00

5.4

V

%

V

VBST

V

VBST Output Voltage Accuracy

-2.5

2.5

7.3

VBSTA

VBSTR

IN

V

VBST Output Voltage Programmable Programmable in 50mV steps

Range

4.65

I

Boost nFET Current Limit

1.2

1.45

1.7

A

LIM_VBST

I

VBST Output Current

2.5V < V <5V, VBST = 5.4V, Register 0x06 = 0x00)

IN

350

mA

mΩ

VBSTO

r

Low-Side Switch ON-Resistance

T = +25°C, I

A

= 100mA,

110

145

ON_VBSTL

LOAD_VBST

LXP to PGND

r

High-Side Switch ON-Resistance

T = +25°C, I

A

= 100mA,

mΩ

ON_VBSTH

LOAD_VBST

LXP to VBST

I

LXP Leakage Current

VLXP = 6V, ENP = ENN = 0V

Boost frequency = 1.45MHz

Boost frequency = default

10

µA

%

L_LXP

D

Boost Minimum Duty Cycle

Boost Maximum Duty Cycle

Boost Switching Frequency

Boost Soft-Start Time

12.5

91

MIN

D

%

MAX

f

1.3

1.45

0.59

1.6

MHz

ms

SWV_VBST

t

C

= 10µF (not derated), VIN > V

UVLO

0.85

SS_VBST

VBST

FN8724 Rev.2.00

Sep 26, 2017

Page 6 of 33

ISL98608IIH

Electrical Specifications

V

= 3.7V, unless otherwise noted. Typical specifications are characterized at T = +25°C unless

IN A

otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)

MIN

MAX

PARAMETER

DESCRIPTION

TEST CONDITIONS

(Note 7)

TYP

-5

(Note 7) UNIT

NEGATIVE REGULATOR (VN)

V

VN Output Voltage

VN = -5V, Register 0x08 = 0x00 no load

Programmable in 50mV steps

V

VN

V

VN Output Voltage Programmable

Range

-7

-2

V

VNR

-4.5

V

VN Output Voltage Accuracy

VN = -5V, Register 0x08 = 0x00, Register 0x06 = 0x00,

2

%

ACC_VN

-100mA < I

< 0mA

LOAD_VN

f

Charge Pump Switching Frequency CP Frequency = default, 50% duty cycle

1.3

1.45

1.6

10

MHz

µA

SW_VN

I

Charge Pump Leakage Current

VN Discharge Resistance

VN Soft-Start Time

CP pin, CP = 6V, ENN = 0V

VN = -1V

L_CP

R

35

Ω

DCH_VN

t

C

= 10µF (not derated), VN = -5V, Register

VN

1.96

2.39

ms

SS_VN

0x08 = 0x00, Register 0x05 b = 0

7

POSITIVE REGULATOR (VP)

V

VP Output Voltage

VP = 5V, Register 0x09 = 0x00, no load

Programmable in 50mV steps

5

V

VP

V

VP Output Voltage Programmable

Range

VPR

4.5

7

V

VP Output Voltage Accuracy

VP = 5V, Register 0x09 = 0x00, Register 0x06 = 0x00,

-2

2

%

ACC_VP

0mA < I

< 100mA

LOAD_VP

V

VP Dropout Voltage

VP Leakage Current

VP Discharge Resistance

VP Soft-Start

I

= 100mA

100

2

mV

µA

Ω

DRP_VP

LOAD_VP

I

VP pin, VP = 0V, ENP = 0V

VP = 1V

L_VP

R

80

DCH_VP

t

C

b

= 10µF (not derated), VP = 5V, Register 0x05

1.23

1.53

ms

SS_VP

VP

= 0

7

PROTECTION

T

Thermal Shutdown Temperature

Thermal Shutdown Hysteresis

VBST Undervoltage Limit

Die temperature (rising) when the device will

disable/shutdown all outputs until it cools by T

150

20

°C

OFF

°C

HYS

T

Die temperature below T °C when the device will

OFF

re-enable the outputs after shutdown

HYS

V

70% of VBST

60% of VP

V

UVP_VBST

V

VP Undervoltage Protection

Threshold

UVP_VP

V

VN Undervoltage Protection

Threshold

60% of VN

100

V

UVP_VN

V

Undervoltage Delay

Undervoltage delay for VBST, VN, VP

µs

UVDELAY

LOGIC/DIGITAL

V

Logic Input Low Voltage

Logic Input High Voltage

ENN, ENP, SCL, SDA

0.4

V

IL

V

IH

1.1

2

f

I C SCL Clock Frequency

(Note 8)

400

kHz

µs

CLK

t

Debounce Time

ENN, ENP

10

1

d

R

Internal Pull-Down Resistance

ENN, ENP

MΩ

EN

NOTES:

7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

2

8. For more detailed information regarding I C timing characteristics refer to Table 2 on page 17.

9. Parameters established by bench testing and/or design. Not production tested.

FN8724 Rev.2.00

Sep 26, 2017

Page 7 of 33

ISL98608IIH

Typical Performance Curves T = +25°C, V = 3.7V, L = 1239AS-H-2R2M (2.5mmx2mm), C

= 10µF/0402,

VBST

A

IN

1

C

= 10µF/0402, C = 2 x 10µF/0402, C = 10µF/0402 unless otherwise noted.

VP

VN CP

90

88

86

84

82

80

78

76

74

72

70

7.2

7.0

6.8

6.6

6.4

6.2

6.0

5.8

5.6

5.4

5.2

5.0

4.8

4.6

4.4

4.2

4.0

V

= 4.35V

2.5V

IN

V

= 3.7V

IN

5V

V

= 3V

IN

3.7V

0

0.04

0.08

0.12

0.16

0.2

0

10

20

30

40

50

60

REGISTER 0x09(dec)

LOAD (A)

FIGURE 4. DISPLAY POWER SYSTEM EFFICIENCY, VP/VN = ±5V

FIGURE 5. VP OUTPUT VOLTAGE RANGE

CH2 = 200mV/DIV (AC), CH4 = 50mA/DIV

7.2

7.0

6.8

6.6

6.4

6.2

6.0

5.8

VBST

2.5V

5.6

5.4

5.2

3.7V

VBST OUTPUT CURRENT

5.0

5V

4.8

4.6

4.4

4.2

4.0

0

10

20

30

40

50

60

REGISTER 0x08 (dec)

40µs/DIV

FIGURE 7. VBST LOAD TRANSIENT, VBST = 5.15V

FIGURE 6. VN OUTPUT VOLTAGE RANGE

CH2 = 50mV/DIV (AC), CH3 = 2V/DIV

CH4 = 200mA/DIV

6.1

6.0

5.9

5.8

5.7

5.6

5.5

5.4

5.3

VBST

LX

2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4

INDUCTOR CURRENT

2µs/DIV

V

(V)

IN

FIGURE 8. VBST, V HEADROOM TRACKING, VBST = 5.4V

IN

FIGURE 9. VBST RIPPLE, 10mA LOAD, VBST = 5.4, V = 3V

IN

FN8724 Rev.2.00

Sep 26, 2017

Page 8 of 33

ISL98608IIH

Typical Performance Curves T = +25°C, V = 3.7V, L = 1239AS-H-2R2M (2.5mmx2mm), C

= 10µF/0402,

A

IN

1

VBST

C

= 10µF/0402, C = 2 x 10µF/0402, C = 10µF/0402 unless otherwise noted. (Continued)

VP

VN CP

CH2 = 50mV/DIV (AC), CH3 = 2V/DIV

CH4 = 200mA/DIV

CH2 = 50mV/DIV (AC), CH3 = 2V/DIV

CH4 = 200mA/DIV

VBST

LX

INDUCTOR CURRENT

500ns/DIV

FIGURE 11. VBST RIPPLE, 10mA LOAD, VBST = 5.4V, V = 3.7V

IN

FIGURE 10. VBST RIPPLE, 450mA LOAD, VBST = 5.4V, V = 3V

IN

CH2 = 50mV/DIV (AC), CH3 = 2V/DIV

CH4 = 200mA/DIV

VBST

CH2 = 50mV/DIV (AC), CH3 = 2V/DIV

CH4 = 200mA/DIV

VBST

INDUCTOR CURRENT

LX

500ns/DIV

FIGURE 12. VBST RIPPLE, 10mA LOAD, VBST = 5.65V

FIGURE 13. VBST RIPPLE, 150mA LOAD, VBST = 5.65V

CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)

VP

CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)

VP

VN

20µs/DIV

FIGURE 15. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 20mA LOAD,

FIGURE 14. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 5mA LOAD,

= 3V

V

= 3V

V

IN

FN8724 Rev.2.00

Sep 26, 2017

Page 9 of 33

ISL98608IIH

Typical Performance Curves T = +25°C, V = 3.7V, L = 1239AS-H-2R2M (2.5mmx2mm), C

= 10µF/0402,

VBST

A

IN

1

C

= 10µF/0402, C = 2 x 10µF/0402, C = 10µF/0402 unless otherwise noted. (Continued)

VP

VN CP

CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)

VP

VN

1µs/DIV

20µs/DIV

FIGURE 17. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 200mA LOAD,

= 3V

FIGURE 16. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 100mA LOAD,

= 3V

V

IN

CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)

VP

VN

20µs/DIV

FIGURE 19. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 20mA LOAD,

= 3.7V

FIGURE 18. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 5mA LOAD,

= 3.7V

V

IN

CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)

VP

VN

20µs/DIV

1µs/DIV

FIGURE 20. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 100mA LOAD,

= 3.7V

FIGURE 21. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 200mA LOAD,

= 3.7V

V

IN

FN8724 Rev.2.00

Sep 26, 2017

Page 10 of 33

ISL98608IIH

Typical Performance Curves T = +25°C, V = 3.7V, L = 1239AS-H-2R2M (2.5mmx2mm), C

= 10µF/0402,

VBST

A

IN

1

C

= 10µF/0402, C = 2 x 10µF/0402, C = 10µF/0402 unless otherwise noted. (Continued)

VP

VN CP

CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)

VP

VN

20µs/DIV

FIGURE 22. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 5mA LOAD,

= 4.35V

FIGURE 23. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 20mA LOAD,

= 4.35V

V

IN

CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)

VP

VN

1µs/DIV

20µs/DIV

FIGURE 25. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 200mA LOAD,

= 4.35V

FIGURE 24. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 100mA LOAD,

= 4.35V

V

IN

CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)

VP

VN

20µs/DIV

FIGURE 27. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 20mA LOAD,

= 5V

FIGURE 26. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 5mA LOAD,

= 5V

V

IN

FN8724 Rev.2.00

Sep 26, 2017

Page 11 of 33

ISL98608IIH

Typical Performance Curves T = +25°C, V = 3.7V, L = 1239AS-H-2R2M (2.5mmx2mm), C

= 10µF/0402,

VBST

A

IN

1

C

= 10µF/0402, C = 2 x 10µF/0402, C = 10µF/0402 unless otherwise noted. (Continued)

VP

VN CP

CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)

VP

VN

1µs/DIV

20µs/DIV

FIGURE 29. VP/VN (±7V) OUTPUT VOLTAGE RIPPLE, 100mA LOAD

FIGURE 28. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 100mA LOAD,

= 5V

V

IN

CH1 = 50mV/DIV (AC)

CH3 = 100mV/DIV (AC)

VP

CH4 = 100mA/DIV

CH1 = 50mV/DIV (AC)

CH3 = 100mV/DIV (AC)

CH4 = 100mA/DIV

VP

VN

OUTPUT CURRENT BETWEEN VP AND VN

80µs/DIV

OUTPUT CURRENT BETWEEN VP AND VN

80µs/DIV

FIGURE 31. VP AND VN LOAD TRANSIENT, VP/VN = ±5V, V = 4.35V

IN

FIGURE 30. VP AND VN LOAD TRANSIENT, VP/VN = ±5V, V = 3.7V

IN

CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV

VP

CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV

VP

VN

INDUCTOR CURRENT

1ms/DIV

FIGURE 33. VP AND VN (±5V) SOFT-START AT 3.7V INPUT VOLTAGE,

FIGURE 32. VP AND VN (±5V) SOFT-START AT 2.5V INPUT VOLTAGE,

VP/VN SEQUENCED (Reg 0x04 = 0)

4

FN8724 Rev.2.00

Sep 26, 2017

Page 12 of 33

ISL98608IIH

Typical Performance Curves T = +25°C, V = 3.7V, L = 1239AS-H-2R2M (2.5mmx2mm), C

= 10µF/0402,

VBST

A

IN

1

C

= 10µF/0402, C = 2 x 10µF/0402, C = 10µF/0402 unless otherwise noted. (Continued)

VP

VN CP

CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV

VP

VN

INDUCTOR CURRENT

1ms/DIV

FIGURE 34. VP AND VN (±5V) SOFT-START AT 5V INPUT VOLTAGE,

FIGURE 35. VP AND VN (±5V) SHUTDOWN, VP/VN SEQUENCED

VP/VN SEQUENCED (Reg 0x04 = 0)

(Reg 0x05 = 0)

4

CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV

VP

VN

VP

VN

INDUCTOR CURRENT

1ms/DIV

INDUCTOR CURRENT

1ms/DIV

FIGURE 36. VP AND VN (±5V) SOFT-START AT 2.5V INPUT VOLTAGE,

FIGURE 37. VP AND VN (±5V) SOFT-START AT 3.7V INPUT VOLTAGE,

VP/VN START TOGETHER (Reg 0x04 = 1)

4

CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV

VP

CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV

VP

VN

INDUCTOR CURRENT

1ms/DIV

FIGURE 38. VP AND VN (±5V) SOFT-START AT 5V INPUT VOLTAGE,

FIGURE 39. VP AND VN (±5V) SHUTDOWN, VP/VN SHUTDOWN

VP/VN START TOGETHER (Reg 0x04 = 1)

TOGETHER (Reg 0x05 = 1)

4

FN8724 Rev.2.00

Sep 26, 2017

Page 13 of 33

ISL98608IIH

Typical Performance Curves T = +25°C, V = 3.7V, L = 1239AS-H-2R2M (2.5mmx2mm), C

= 10µF/0402,

VBST

A

IN

1

C

= 10µF/0402, C = 2 x 10µF/0402, C = 10µF/0402 unless otherwise noted. (Continued)

VP

VN CP

-4.90

-4.92

-4.94

-4.96

-4.98

-5.00

-5.02

-5.04

-5.06

-5.08

-5.10

5.10

5.08

5.06

5.04

5.02

5.00

4.98

4.96

4.94

4.92

4.90

V

= 4.35V

IN

V

= 4.35V

IN

V

= 3V

IN

V

= 3V

IN

V

= 3.7V

IN

V

= 3.7V

0.09

IN

0.01

0.05

0.13

0.17

0.21

0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21

LOAD (A)

FIGURE 40. VN LOAD REGULATION, -5V

FIGURE 41. VP LOAD REGULATION, 5V

FN8724 Rev.2.00

Sep 26, 2017

Page 14 of 33

ISL98608IIH

50mV resolution. The output load capability of the VN regulator is

200mA. Similar to the VP regulator, the VN regulator also

integrates a discharge resistor and the value of discharge resistor

is 35Ω. The VN is an ideal solution for negative supply due to low

ripple, fast load transient response and higher efficiency.

Application Information

Description

The ISL98608IIH is a display PMIC and can be used to supply

power to an LCD display. Figure 42 shows the typical system

application block diagram. For display power, the ISL98608IIH

integrates a boost regulator (VBST), low dropout linear regulator

(VP) and an inverting charge pump regulator (VN). The boost

voltage is generated from a battery voltage ranging from 2.5V to

5.5V and boost regulator output can be programmed from 4.60V

to 7.3V. The VBST regulator integrates low-side NFET and

high-side PFET MOSFETs for synchronous rectification.

Modes of Operation

SHUTDOWN MODE

The ISL98608IIH is in shutdown mode when the enable pins,

namely ENN and ENP are pulled low. When the ENN and ENP

pins are all pulled low, all the regulators are powered off and the

IC is placed in shutdown mode where the current consumed from

the battery is only 1µA (typical).

The output voltage of VBST is the input to the linear regulator

(VP). The VBST output and VP regulator input are connected

internally in the IC. The VP regulator supplies a positive voltage in

the range of +4.5V to +7V with 50mV resolution. The output load

capability of the VP regulator is 200mA. 80Ωdischarge resistor

discharges residual voltage when the power-off sequence is

initiated, which helps avoid ghost image issues. The LDO is an

ideal solution for the positive supply due to its low ripple, fast

load transient response, higher efficiency and low dropout

voltage.

OPERATING MODE

The IC is in normal operating mode when the ENN and ENP are

pulled high and the current consumed from the battery is only

1mA (excluding VBST and VN switching current). After the

ENN/ENP signals are pulled high, VBST, VP and VN go through

power-on sequencing. Refer to “Power-On/Off Sequence” on

page 23 for more details.

The VN voltage is generated by a regulated inverting charge

pump topology. VBSTCP is the input to the inverting charge

pump, which should be connected to the VBST pin on the PCB.

The VN regulator supplies negative voltage from -7V to -4.5V with

LCD PANEL/HI-Fi AUDIO AMPLIFIER

+

-

VP

VN

2.5V to 5.5V

VIN

ENN

ENP

APPLICATIONS

PROCESSOR

ISL98608IIH

I²C

FIGURE 42. TYPICAL SYSTEM APPLICATION BLOCK DIAGRAM

FN8724 Rev.2.00

Sep 26, 2017

Page 15 of 33

ISL98608IIH

START

VIN < ~2.0V

YES

NO

I²C Reboot

Reset

Shutdown Mode

NO

VIN >

UVLO(2.3V)

YES

ENP or ENN =

HIGH

NO

YES

VBST EN

bit = HIGH

NO

YES

Soft-Start VBST

ENP and VP

EN bit = HIGH

ENN and VN

EN bit = HIGH

YES

Soft-Start VP

Is VP Soft

Start Active

NO

VN Pre-charging

Optional 2ms delay

2ms delay

Soft-Start VN

Normal VP Mode

Normal VN Mode

YES

ENP and VP

EN bit = HIGH

ENN and VN

EN bit = HIGH

NO

VP UVP

YES

VN UVP

YES

NO

EN VP Discharge

Optional 2ms delay

UVP = VBST, VP and VN Power-OFF

Wait 2ms

YES

ENP and ENN

= LOW

YES

NO

Disable VP

Disable VN and

enagage discharge

NO

VP and VN

disabled?

YES

Disable VBST

Optional 2ms delay : If register 0x02 b<6> is set to

“1” then 2ms delay is performed on both VP and VN.

FIGURE 43. START-UP FUNCTIONAL BLOCK DIAGRAM

FN8724 Rev.2.00

Sep 26, 2017

Page 16 of 33

ISL98608IIH

2

STOP condition is signified by a LOW to HIGH transition on the

SDA line while SCL is HIGH. See timing specifications in Table 2.

I C Digital Interface

2

The ISL98608IIH uses a standard I C interface bus for

communication. The two-wire interface links a Master(s) and

uniquely addressable Slave devices. The Master generates clock

signals and is responsible for initiating data transfers. The serial

clock is on the SCL line and the serial data (bidirectional) is on

the SDA line. The ISL98608IIH supports clock rates up to 400kHz

(Fast mode) and is backwards compatible with standard 100kHz

clock rates (Standard mode).

The Master always initiates START and STOP conditions. After a

START condition, the bus is considered “busy.” After a STOP

condition, the bus is considered “free.” The ISL98608IIH also

supports repeated STARTs, where the bus will remain busy for

continued transaction(s).

DATA VALIDITY

The data on the SDA line must be stable (clearly defined as HIGH

or LOW) during the HIGH period of the clock signal. The state of

the SDA line can only change when the SCL line is LOW (except to

create a START or STOP condition). See timing specifications in

Table 2.

The SDA and SCL lines must be HIGH when the bus is free - not in

use. An external pull-up resistor (typically 2.2kΩto 4.7kΩ) or

current source is required for SDA and SCL.

2

The ISL98608IIH meets standard I C timing specifications, see

Figure 44 and Table 2, which show the standard timing

definitions and specifications for I C communication.

The voltage levels used to indicate a logical ‘0’ (LOW) and logical

2

‘1’ (HIGH) are determined by the V and V thresholds,

IL IH

respectively, see the “Electrical Specifications” table on page 7.

START AND STOP CONDITION

2

All I C communication begins with a START condition (indicating

BYTE FORMAT

the beginning of a transaction) and ends with a STOP condition

(signaling the end of the transaction).

Every byte transferred on SDA must be 8 bits in length. After

every byte of data sent by the transmitter there must be an

Acknowledge bit (from the receiver) to signify that the previous

8 bits were transferred successfully. Data is always transferred

on SDA with the Most Significant Bit (MSB) first. See

“Acknowledge (ACK)” on page 18.

A START condition is signified by a HIGH to LOW transition on the

serial data line (SDA) while the serial clock line (SCL) is HIGH. A

t_BUF

V_IH

SDA

V_IL

t_r

t_f

t_SU:STA

t_HD:STA

t_SU:STO

t_r

t_f

V_IH

SCL

V_IL

t_SU:DAT

t_HD:DAT

START

STOP

START

2

FIGURE 44. I C TIMING DEFINITIONS

2

TABLE 2. I C TIMING CHARACTERISTICS

FAST-MODE

MIN

STANDARD-MODE

PARAMETER

SYMBOL

MAX

MIN

0

MAX

UNIT

kHz

µs

SCL Clock Frequency

f

0

400

100

SCL

Set-Up Time for a START Condition

Hold Time for a START Condition

Set-Up Time for a STOP Condition

t

0.6

-

4.7

4.0

4.7

250

0

-

SU:STA

HD:STA

t

0.6

-

µs

t

0.6

-

µs

SU:STO

Bus Free Time between a STOP and START Condition

Data Set-Up Time

t

1.3

-

µs

BUF

t

100

-

ns

SU:DAT

HD:DAT

Data Hold Time

t

0

20 + 0.1C

-

µs

Rise Time of SDA and SCL (Note 10)

Fall Time of SDA and SCL (Note 10)

Capacitive Load on Each Bus Line (SDA/SCL)

NOTE:

t

300

400

-

1000

300

400

ns

r

f

b

-

ns

C

-

pF

b

10. C = Total capacitance of one bus line in pF.

b

FN8724 Rev.2.00

Sep 26, 2017

Page 17 of 33

ISL98608IIH

To access the ISL98608IIH, the 7-bit Device Address is 0x29

(0101001x), located in MSB bits . The eighth bit of the

ACKNOWLEDGE (ACK)

7

1

Each 8-bit data transfer is followed by an Acknowledge (ACK) bit

from the receiver. The Acknowledge bit signifies that the previous

8 bits of data was transferred successfully (master to slave or

slave to master).

Device Address byte (LSB bit ) indicates the direction of

0

transfer, READ or WRITE (R/W). A “0” indicates a WRITE

operation - the Master will transmit data to the ISL98608IIH

(receiver). A “1” indicates a Read operation - the Master will

receive data from the ISL98608IIH (transmitter) (see Figure 45).

When the Master sends data to the Slave (e.g., during a WRITE

th

transaction), after the 8 bit of a data byte is transmitted, the

th

B₇

B₆

B₅

B₄

B₃

B₂

B₁

B₀

Master tri-states the SDA line during the 9 clock. The Slave

0

1

0

1

0

1

R/W

device acknowledges that it received all 8 bits by pulling down

the SDA line, generating an ACK bit.

READ = 1

WRITE = 0

DEVICE ADDRESS = 0X29

When the Master receives data from the Slave (e.g., during a data

th

READ transaction), after the 8 bit is transmitted, the Slave

FIGURE 45. DEVICE ADDRESS BYTE FORMAT

th

tri-states the SDA line during the 9 clock. The Master

acknowledges that it received all 8 bits by pulling down the SDA

line, generating an ACK bit.

Write Operation

2

NOT ACKNOWLEDGE (NACK)

A WRITE sequence requires an I C START condition, followed by

a valid Device Address Byte with the R/W bit set to ‘0’, a valid

Register Address Byte, a Data Byte and a STOP condition. After

each valid byte is sent, the ISL98608IIH (slave) responds with an

ACK. When the Write transaction is completed, the Master should

generate a STOP condition. For sent data to be latched by the

ISL98608IIH, the STOP condition should occur after a full byte (8

bits) is sent and ACK. If a STOP is generated in the middle of a

byte transaction, the data will be ignored. See Figure 46 on

A Not Acknowledge (NACK) is generated when the receiver does

not pull-down the SDA line during the acknowledge clock (i.e.,

SDA line remains HIGH during the 9 clock). This indicates to the

Master that it can generate a STOP condition to end the

transaction and free the bus.

th

A NACK can be generated for various reasons, for example:

2

• After an I C device address is transmitted, there is NO receiver

2

page 19 for the ISL98608IIH I C Write protocol.

with that address on the bus to respond.

• The receiver is busy performing an internal operation (e.g.,

reset, recall, etc) and cannot respond.

Read Operation

A READ sequence requires the Master to first write to the

ISL98608IIH to indicate the Register Address/pointer to read

from. First, Send a START condition, followed by a valid Device

Address Byte with the R/W set to ‘0’ and then a valid Register

Address Byte. Then the Master generates either a Repeat START

condition or a STOP condition followed by a new START condition

and a valid Device Address Byte with the R/W bit set to ‘1’. Then

the ISL98608IIH is ready to send data to the Master from the

requested Register Address.

• The Master (acting as a receiver) needs to indicate the end of a

transfer with the Slave (acting as a transmitter).

DEVICE ADDRESS AND R/W BIT

Data transfers follow the format shown in Figures 46 and 47 on

page 19. After a valid START condition, the first byte sent in a

transaction contains the 7-bit Device (Slave) Address plus a

direction (R/W) bit. The Device Address identifies which device

2

(of up to 127 devices on the I C bus) the Master wishes to

The ISL98608IIH sends out the Data Byte by asserting control of

the SDA pin while the Master generates clock pulses on the SCL

pin. When transmission of the desired data is complete, the

Master generates a NACK condition followed by a STOP condition

and this completes the I C Read sequence. See Figure 47 on

page 19 for the ISL98608IIH I C Read protocol.

communicate with.

After a START condition, the ISL98608IIH monitors the first 8 bits

(Device Address Byte) and checks for its 7-bit Device Address in

the MSBs. If it recognizes the correct Device Address, it will ACK

and becomes ready for further communication. If it does not see

its Device Address, it will sit idle until another START condition is

issued on the bus.

2

FN8724 Rev.2.00

Sep 26, 2017

Page 18 of 33

ISL98608IIH

DEVICE

ADDRESS

REGISTER

POINTER

DATA

STOP

START

W

SDA

(FROM

MASTER)

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7 6 5 4 3 2 1 0

DEVICE ADDRESS = 0X29

SDA

(FROM

SLAVE)

WRITE

DATA

A

SCL

(FROM

MASTER)

7

6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

2

FIGURE 46. I C WRITE TIMING DIAGRAM

DEVICE

ADDRESS

REGISTER

POINTER

START

W

STOP

SDA

(FROM

MASTER)

NOTE: First send register pointer to

indicate the READ-back starting location

7

6

5

4

3

2

1

0

A

7 6 5 4 3 2 1 0

DEVICE ADDRESS = 0X29

WRITE

REGISTER

POINTER

SDA

(FROM

SLAVE)

A

This STOP condition is optional (not

required) to do READ-back. The device

also supports repeated STARTs.

SCL

(FROM

MASTER)

7

6

5

4

3

2

1

0

A 7 6 5 4 3 2 1 0

DEVICE

ADDRESS

DATA

STOP

START

R

SDA

(FROM

7

6

5

4

3

2

1

0

A

MASTER)

DEVICE ADDRESS = 0X29

(NO ACK)

SDA

(FROM

SLAVE)

READ

DATA

A

7

6

5

4

3

2

1

0

SCL

(FROM

MASTER)

7

6

5

4

3

2

1

0

A

1

0

A

2

FIGURE 47. I C READ TIMING DIAGRAM

FAULT

Register Descriptions and Addresses

The “FAULT” register (Register Address 0x04) can be used to read

back the current fault status of the IC. The fault conditions that

can be read back by I C are VBST undervoltage fault, VP

undervoltage fault, VN undervoltage fault and over-temperature

protection (OTP) fault.

The “Register Map” on page 21 contains the detailed register

map, with descriptions and addresses for ISL98608IIH registers.

Each volatile register is one byte (8-bit) in size. When writing data

to adjust register settings using I C, the data is latched-in after

the 8th bit (LSB) is received.

2

If FAULT register bit (OTP status bit) is latched high for an

0

OTP fault, it can be reset by simultaneously cycling ENP and ENN.

The ISL98608IIH has default register settings that are applied at

IC power-up, and in some cases, updated based on fuse values at

first enable. The default register settings are indicated with BOLD

face text.

If FAULT register bit (VBST status bit) is latched high for a

1

VBST undervoltage fault, it can be reset by cycling ENP and ENN

together.

NOTE: To clear/reset all the volatile registers to the default values, power

cycle VIN or clear the register 0x04 bit .

7

If FAULT register bit (VN status bit) is latched high for a VN

2

undervoltage fault, it can be reset by cycling ENN.

Register Functions

If FAULT register bit (VP status bit) is latched high for a VP

3

undervoltage fault, it can be reset by cycling ENP.

The ISL98608IIH has various registers that can be used to adjust

and control IC operating voltages, modes, thresholds and

sequences.

FN8724 Rev.2.00

Sep 26, 2017

Page 19 of 33

ISL98608IIH

respective soft-start sequence.

All fault bits can be cleared by cycling VIN or with a software

reboot (clearing register 0x04 bit<b ). This will reset the entire

part to default settings and disable all outputs until they have

sequenced up again.

7>

Output Voltage Calculation for VBST, VP and VN

The expected output voltage for each regulator can be

determined using Equations 1 through 3. Note, N is the 5-bit

register settings from 0x06, 0x08 and 0x09 in decimal.

ENABLE

The “ENABLE” register (Register Address 0x05) can be used to

control the enable/disable state of the boost (VBST), positive

LDO (VP) and negative charge pump (VN). This can also be used

to sequence the regulators. Refer to “Enable Timing Control

Options for VP and VN Regulators” on page 26 for details

regarding the control of output regulators using the enable and

I C control. Using this register the VP and VN pull-down resistor

can be enabled or disabled, soft-start time of VP and VN can be

adjusted and the timing of VP sequencing can be adjusted.

The expected VBST voltage can be determined using Equation 1.

(EQ. 1)

VBSTV = VBSTDefaultV + N  50mV

Once the maximum VBST voltage is reached, the algorithm will

wrap around to give VBST voltage from 4.65V to 5.1V.

2

The expected VP voltage can be determined using Equation 2.

·

(EQ. 2)

VPV = VPDefaultV + N  50mV

Bit<4> of ENABLE register controls the delay between the ENP

signal going low and the VP regulator power-off. If Bit<4> is set to

0, the VP regulator is disabled 2ms after ENP going low. If Bit<4>

is set to 1, the VP regulator is disabled as soon as ENP goes low.

Once the maximum VP voltage is reached, the algorithm will

wrap around to give VP voltage from 4.50V to 4.95V.

The expected VN voltage can be determined using Equation 3.

·

(EQ. 3)

VNV = VNDefaultV – N  50mV

Bit<5> of ENABLE register controls shutdown behavior of VBST,

VP and VN regulators after OTP or UV event. If Bit<5> is set to 1,

then VBST, VP and VN regulators are shut off after OTP or UV

event. To turn on the regulators, IC should be out of fault

condition and ENP and ENN signals are recycled. Regulators can

Once the minimum VN voltage is reached, the algorithm will

wrap around to give VN voltage from -4.50V to -4.95V.

Example Calculations:

2

also be turned on by recycling the enable bit in the I C register. If

If N = 10 (decimal) VBST(Default) = 5.15V, VP/VN(Default) = ±5V:

VBSTV = 5.15V + 10  50mV = 5.65V

Bit<5> is set to 0, then regulators will turn back on as soon as

fault condition is removed.

Bit<6> controls the VN and VP discharge resistor. If Bit<6> is

programmed to “0”, then it will enable the discharge resistor

where as “1” will disable the discharge resistor.

VPV = 5V + 10  50mV = 5.5V

VNV = -5V – 10  50mV = -5.5V

Bit<7> controls the soft-start time of VN and VP regulators. If

Bit<7> is set to “0”, then soft-start time of VN is 1.8ms and for VP

is 1.2ms whereas when set to “1”, soft-start time of both VP and

VN regulator is 0.7ms.

The default output voltage of VBST, VP, and VN regulators can be

determined by factory configurable settings. The output voltage

2

can be changed using I C control when V > POR (Power-On

IN

Reset) voltage. When powered up, Registers 0x06, 0x08, and

0x09 read value 0x00 and VBST, VN, VP voltage levels are at

VBST/VN/VN VOLTAGE

2

respective default voltage. Using I C control, the voltage can be

The output voltages of VBST, VP and VN regulators can be

changed using the registers “VBST Voltage”, “VP Voltage” and

“VN Voltage,” respectively. VBST voltage is at Register Address

0x06, VN voltage is at Register Address 0x08 and VP voltage is at

Register Address 0x09. The output voltages of all regulators can

changed by changing the value of Registers 0x06, 0x08, and

0x09. As V < POR (Power-On Reset) voltage, Registers 0x06,

IN

0x08, and 0x09 read 0x00.

VBST CONTROL

2

In addition to output voltage adjustments, key operation

be changed from their default values using I C.

2

parameters can be changed using I C to optimize the

• The VBST regulator can be programmed from +4.65V to +7.3V

• The VP regulator can be programmed from +4.5V to +7V

• The VN regulator can be programmed from -7V to -4.5V

• All are adjustable with 50mV step size.

ISL98608IIH performance.

The “VBST CNTRL and VBST/VN Frequency” register (Register

Address 0x0D) can be used to control boost PFM mode, boost

FET slew rate and switching frequency of the boost and charge

pump.

Once the maximum VBST voltage (7.3V) is reached the algorithm

will wrap around to give VBST voltage from 4.65V to 5.1V.

Similarly, when maximum VP and VN voltage are reached (±7V),

the algorithm will wrap around to give VP/VN voltage from ±4.5V

to ±4.95V.

To determine the expected output voltage for a specific register

value, see the following section “Output Voltage Calculation for

VBST, VP and VN”.

NOTE: Output voltage registers should not be changed during their

FN8724 Rev.2.00

Sep 26, 2017

Page 20 of 33

ISL98608IIH

Negative Charge Pump Operation (VN)

The ISL98608IIH uses a negative charge pump with internal

switches to create the VN voltage rail. The charge pump input

voltage VBSTCP comes from the boost regulator output, VBST.

Display Power Supply Function

Description

Regulator Output Enable/Disable

Regulation is achieved through a classic voltage mode

architecture where an internally compensated integrator output

is compared with the voltage ramp to set a duty cycle. The duty

cycle controls the amount of time the output capacitor is charged

during each switching cycle. The maximum duty cycle is 50%.

The charge pump output capacitor (placed on the VN pin) is

pumped through internal current source to minimize system

noise.

The boost converter, VBST, will be enabled whenever either ENP

or ENN is HIGH and the VBST enable bit in the ENABLE

0

register is set to ‘1’. To disable the boost (and effectively VP and

VN), ENN and ENP must be LOW, or its enable bit set to ‘0’.

The negative charge pump, VN, is enabled whenever ENN is HIGH

and the VN enable bit in the ENABLE register is set to ‘1’. To

1

disable, ENN must be LOW, or its enable bit set to ‘0’.

The LDO, VP, is enabled whenever ENP is HIGH and the VP enable

VN and VBST PFM

Bit in the ENABLE register is set to ‘1’. To disable ENP must

2

be LOW, or its enable bit set to ‘0’.

The ISL98608IIH features light-load Pulse Frequency Modulation

(PFM) mode for both the boost regulator and the charge pump, to

maximize efficiency at light loads.

All the ENABLE register bits are set to ‘1’ by default.

2

0

Note, ENP and ENN are logic level inputs with HIGH/LOW

The device always uses PWM mode at heavy loading, but will

automatically switch to PFM mode at light loads to optimize

efficiency. PFM capability is enabled using the respective PFM

mode enable/disable register bits.

thresholds defined by the V /V specifications, respectively.

IH IL

These inputs also have 1MΩ (typical) internal pull-down

resistance to ground. If the pins are left at high-impedance, they

will default to a LOW logic state. Refer to the “LOGIC/DIGITAL” on

page 7 of the “Electrical Specifications” table for more

information.

VBST PFM

In PFM mode, the boost can be configured to either use a fixed

peak current or to automatically select the optimal peak current

setting. The automatic, or “Auto” mode, is designed to

dynamically adjust the peak current to maintain boost output

voltage ripple at relatively fixed levels across input voltage, while

improving efficiency at low input voltages. This patent pending

architecture adjusts the peak current to keep the sum of inductor

ramp-up and ramp-down times to a constant value of

VP and VN Headroom Voltage and Output

Current

The VP and VN headroom voltage is defined as the difference

between the VBST target voltage and maximum of VP and |VN|

target voltages.

The headroom voltage must be set high enough so that both the

VP LDO and VN negative Charge Pump (CP) can maintain

regulation. The VBST voltage must be greater than the absolute

value of the VN regulation voltage (i.e., the headroom voltage has

to be >0V). Primarily, the minimum headroom voltage is a

function of the maximum application load current that the IC will

need to support. Fast output current peaks of only a few

microseconds should not be considered - those instantaneous

current peaks will be supported by the output capacitors and not

by the regulator. Equation 4 shows the minimum headroom

required depending upon the current.

approximately 1.3*T

. This scheme also gives more

PWM

consistent ripple part-to-part and keeps PWM/PFM hysteresis

defined in a smaller and more optimal band across operating

voltages. It is recommended to operate the part in this mode.

The VBST PFM mode features an ultrasonic Audio Band

Suppression (ABS) mode, which prevents the switching

frequency from falling below 30kHz to avoid audible noise. When

the time interval between two consecutive switching cycles in

PFM mode is more than 33ms (i.e., 30kHz frequency) the

regulator reduces the peak inductor current, to maintain the

frequency at 30kHz. If this is not sufficient, the regulator will add

low current reverse current cycles.

(EQ. 4)

HeadroomV  ImaxAX2.7

Note the headroom voltage should not be set overly high, since

increasing headroom generally yields lower efficiency

performance due to increased conduction losses.

VN PFM

The charge pump PFM mode works by increasing the minimum

pump on-time, and thereby the charge delivered per cycle, when

the load is low. This allows increased ripple to be traded off

against switching losses.

For very low duty cycle where the output voltage of the VBST is

very close to the input voltage, VBST starts to track the input

voltage with a fixed headroom of ~600mV. This feature avoids

the minimum duty cycle limitation from producing increased

ripple on VBST (which feeds through to VP/VN) and ensures

proper regulation of the VBST, VP and VN regulators.

For most applications, the ISL98608IIH default 400mV

headroom voltage setting provides optimal performance for DC

output current up to 200mA (maximum).

FN8724 Rev.2.00

Sep 26, 2017

Page 22 of 33

ISL98608IIH

Figure 51 shows the power-on sequence for the case when the

ENP and ENN all are tied together and VP/VN rail sequencing is

VP/VN Output Hi-Z Mode

The ISL98608IIH VP and VN regulator can be configured in a Hi-Z

disabled in register 0x04 by writing “1” and VP/VN soft-start

4

mode to prevent any leakage current flowing between VP and VN.

time is programmed to 0.7ms from register 0x05 by writing

7

2

Using I C register 0x05 can be used to disable the

6

“1”. The VBST soft-starts if the VIN voltage is higher than the

UVLO threshold and either ENN or ENP is high. When the VBST

soft-start is completed, the VP and VN regulator soft-starts in

0.7ms.

pull-down resistors on VP and VN giving a “Hi-Z” state of output.

Power-On/Off Sequence

The boost regulator used to generate VP/VN, VBST, is activated

when the VIN input voltage is higher than the UVLO threshold,

and either ENP or ENN is high, along with their respective I C

enable bits. To enable the VBST, Reg 0x05 should be 1

The VP/VN/VBST soft-start times quoted above (VBST = 0.47ms,

VP = 1.2ms and VN = 1.2ms or 1.8ms) are valid for the default

voltage levels (VSBT = 5.15V, VP = 5V and VN = -5V). These will

change with different voltages, as they are set to give a fixed

dv/dt.

2

0

(by default this bit is set to 1). The VP output is activated if ENP is

high, VBST has completed its soft-start and Reg 0x05 is 1

2

(by default this bit is set to 1). The VN charge pump is activated

2ms after VBST has completed soft-start and the ENN has been

pulled high, whichever comes later. To activate the VN regulator,

Figure 52 shows the power-on sequence for the case when the

ENP and ENN are controlled by two GPIOs and VP/VN rail

sequencing is enabled from register 0x04 <b4> by writing "0".

Also, VP soft-start time is programmed to 1.2ms and VN

soft-start time is programmed to 1.8ms from register 0x05 <b7>

by writing "0".

Reg 0x05 should also be 1 (by default this bit is set to 1).

1

Figure 48 shows the power-on sequence for the case when the

ENP and ENN all are tied together and VP/VN rail sequencing is

enabled in register 0x04 by writing “0” and VP soft-start

time is 1.2ms where as VN soft-start time is 1.8ms programmed

4

ENP or ENN going low will shut down VP or VN, respectively. If

both ENP and ENN are pulled low, then VP, VN and VBST are all

turned off. The VN regulator shuts off when ENN is pulled low. VP

and VBST power-off occurs 2ms after the ENP signal goes low

from register 0x05 by writing “1”. The VBST soft-starts if the

7

VIN voltage is higher than the UVLO threshold and either ENN or

ENP is high. When the VBST soft-start is completed, the VP

regulator soft-starts in 1.2ms. The VN power-on occurs 2ms after

VBST soft-start completes. The VN soft-start time takes 1.8ms.

The 2ms power-on delay between VP and VN can be disabled

(Register 0x05 = 0), (see Figure 53). If Register 0x05 = 1,

4

the VP and VN regulators will power off immediately when ENN

and ENP are pulled low (see Figure 54).

If VIN falls below UVLO while the IC is active, all active regulators

will be turned off at the same time (see Figure 55).

from register 0x04 by writing “1”.

4

Figure 49 shows the power-on sequence for the case when the

ENP and ENN all are tied together and VP/VN rail sequencing is

VP AND VN DISCHARGE RESISTOR

enabled in register 0x04 by writing “0” and VP/VN soft-start

4

The integrated discharge resistors on the VP and VN outputs are

80Ω (typical) and 35Ω (typical), respectively. The VP discharge

resistor is enabled for 2ms (by default) following when ENN goes

low. If ENP is still high, the VP discharge resistor is disabled 2ms

after ENN goes low. The VP discharge resistor will be re-enabled

when ENP goes low. If the same output capacitor (value, size,

rating) is used for VN and VP, the VN rail will discharge faster

than VP if they are both turned off at the same time. This is ideal

for applications that require the VN rail to go down before VP at

power-off.

time is programmed to 0.7ms from register 0x05 by writing

7

“1”. The VBST soft-starts if the VIN voltage is higher than the

UVLO threshold and either ENN or ENP is high. When the VBST

soft-start is completed, the VP regulator soft-starts in 0.7ms. The

VN power-on occurs 2ms after VBST soft-start completes. The VN

soft-start time takes 0.7ms. The 2ms power-on delay between VP

and VN can be disabled from register 0x04 by writing “1”.

4

Figure 50 shows the power-on sequence for the case when the

ENP and ENN all are tied together and VP/VN rail sequencing is

disabled in register 0x04 by writing “1” and VP/VN soft-start

4

time is programmed to 1.2ms from register 0x05 by writing

7

“0”. The VBST soft-starts if the VIN voltage is higher than the

UVLO threshold and either ENN or ENP is high. When the VBST

soft-start is completed, the VP and VN regulator soft-starts in

1.2ms.

FN8724 Rev.2.00

Sep 26, 2017

Page 23 of 33

ISL98608IIH

UVLO

VIN

ENP/ENN

VBST

0.47ms

VBST

POWER-GOOD

1.2ms

0.7ms

VP

VN

VP

VN

1.8ms

0.7ms

2ms

FIGURE 48. POWER-ON SEQUENCE – ACTIVATED BY ONE GPIO FOR

FIGURE 49. POWER-ON SEQUENCE – ACTIVATED BY ONE GPIO FOR

ENN AND ENP, REGISTER 0x04 = 0 AND

4

0x05 = 0

7

0x05 = 1

7

UVLO

VIN

ENP/ENN

0.47ms

ENP/ENN

0.47ms

VBST

POWER-GOOD

2ms

VP

VN

VP

VN

0.7ms

1.2ms

FIGURE 50. POWER-ON SEQUENCE – ACTIVATED BY ONE GPIO FOR

FIGURE 51. POWER-ON SEQUENCE – ACTIVATED BY ONE GPIO FOR

ENN AND ENP, REGISTER 0x04 = 1 AND

4

0x05 = 0

0x05 = 1

7

FN8724 Rev.2.00

Sep 26, 2017

Page 24 of 33

ISL98608IIH

UVLO

VIN

UVLO

VIN

ENN/ENP

ENP

ENN

NO DISCHARGE RESISTOR ON VBST

VBST

0.47ms

2ms

VBST

POWER-GOOD

VBST

POWER-GOOD

VP

PULL TO GND (80 TYP)

PULL TO GND (35 TYP)

2ms

1.8ms

VN

1.2ms

VN

FIGURE 53. POWER-OFF SEQUENCE - ACTIVATED BY TWO GPIOs ENN

FIGURE 52. POWER-ON SEQUENCE – ACTIVATED BY TWO GPIOs FOR

AND ENP, REGISTER 0x05 = 0

ENN AND ENP, REGISTER 0x04 = 0 AND

4

0x05 = 0

7

VIN

UVLO

VIN

UVLO

ENP

ENN

ENN/ENP

NO DISCHARGE RESISTOR ON VBST

VBST

NO DISCHARGE RESISTOR ON VBST

VBST

POWER-GOOD

VBST

POWER-GOOD

VP

PULL TO GND (80 TYP)

PULL TO GND (35  TYP)

PULL TO GND (80 TYP)

VP

VN

PULL TO GND (35 TYP)



VN

FIGURE 55. POWER-OFF SEQUENCE - ACTIVATED BY VIN FALLING

BELOW UVLO

FIGURE 54. POWER-OFF SEQUENCE - ACTIVATED BY TWO GPIOs ENN

AND ENP, REGISTER 0x05 = 1

4

FN8724 Rev.2.00

Sep 26, 2017

Page 25 of 33

ISL98608IIH

Figure 56 shows a 14ms delay between when VP and VN turn-on.

The 14ms time is an example delay to show the power-on

Enable Timing Control Options for VP and VN

Regulators

2

sequencing possibility through I C. This delay is set between the

2

There are several ways to control enable sequencing of the VP

separate I C writes to set the enable bits in register 0x02. If both

2

and VN regulators: I C control, and dual or single GPIO control.

enable bits were set to ‘1’ in the same I C transaction (same

byte) and ENN and ENP are high, then both VP and VN regulators

will start power-on sequencing at the same time (when the data

is latched at the STOP condition). The VN will come up 2ms after

2

I C CONTROL

2

By using I C, the sequencing of the VP and VN regulator can be

controlled by writing to register 0x02. Bit controls the VN

regulator and controls the VP regulator. Setting the bits to

2

‘1’ will enable the regulator and setting to ‘0’ will shut off/disable

the regulator. Delaying the writes for setting bit and

(using separate I C transactions) will delay the turn-on/off

sequence of VP and VN accordingly. When using I C to control

the sequencing, ENN and ENP should be pulled low before writing

to the I C register to disable the VP and VN regulators and then

VP if register 0x02 is low and with VP if high.

1

6

Figure 57 shows a 14ms delay between the VP and VN turn-off.

The 14ms time is an example delay to show the power-off

1

2

sequencing possibility using I C.

2

Figures 58 (zoom in) and 59 (zoom out) show a typical I C data

transfer to the ENABLE register. In this example, VP and VN

regulators are enabled by writing data 0x07 to register address

2

ENN and ENP can go high before the I C is used to enable them.

0x02. The VP regulator will be enabled first after the I C STOP

condition, followed by the VN regulator after the internal 2ms

delay.

VP = 2V/DIV

VN = 2V/DIV

VP = 2V/DIV

VN = 2V/DIV

VP

+5V

VP

+5V

0V

VN

-5V

4ms/DIV

2

FIGURE 56. ON SEQUENCE, I C CONTROL

FIGURE 57. OFF SEQUENCE, I C CONTROL

0V

0x02

0x07

0x52

SCL = 2V/DIV (DC)

SDA = 2V/DIV (DC)

VP = 1V/DIV

SCL = 2V/DIV (DC)

SDA = 2V/DIV (DC)

VP = 1V/DIV

VN = 1V/DIV

VN = 1V/DV

0V

-5V

0V

500µs/DIV

50µs/DIV

2

FIGURE 58. I C SEQUENCE AND VP RESPONSE

FIGURE 59. I C SEQUENCE AND VP/VN RESPONSE

FN8724 Rev.2.00

Sep 26, 2017

Page 26 of 33

ISL98608IIH

SEPARATE ENP AND ENN PINS (2 GPIO CONTROL)

TIE ENP AND ENN TOGETHER (1 GPIO CONTROL)

Using two separate GPIO’s, and controlling the timing between

the ENP and ENN pins, the turn-on/off events can be controlled.

The method to control turn-on/off by GPIO is valid when the

respective enable bits in the ENABLE register at Register Address

0x02 are set to ‘1’ (default). Thus, this method can be used with

There is also an option to sequence the VN and VP regulators if

there is only a single GPIO available in the system. The method to

control turn-on/off by GPIO is valid when the respective enable

bits in the ENABLE register at Register Address 0x02 are set to

‘1’ (default). Therefore, this method can be used with no I C

communication.

2

no I C communication.

Figure 60 shows a 6ms delay (example) between the ENP and

ENN rise.

If the ENP and ENN are tied together and both pulled high and

register 0x02 = “0”, then there is a default delay sequence

6

in the IC. VP will come up first and after 2ms VN will soft-start.

For turn off, VN will power-off first, and VP starts to shut down

2ms after VN starts to power-off.

Figure 61 shows a 13ms delay (example) between the ENP and

ENN fall.

Figure 62 shows turn-on when the ENN and ENP pins are tied

together. There is a 2ms delay between VP and VN turning on.

Figure 63 shows turn-off when the ENN and ENP are tied

together.

VP = 2V/DIV (DC)

VN = 2V/DIV (DC)

+5V

VP

ENN = 2V/DIV (DC)

ENP = 2V/DIV (DC)

ENP

VP = 2V/DIV (DC)

0V

VN = 2V/DIV (DC)

ENN = 2V/DIV (DC)

ENP = 2V/DIV (DC)

0V

VN

0V

ENN

0V

-5V

2ms/DIV

1ms/DIV

FIGURE 60. ON SEQUENCE, 2 GPIO CONTROL

FIGURE 61. OFF SEQUENCE, 2 GPIO CONTROL

VP = 2V/DIV (DC)

VN = 2V/DIV (DC)

VP

+5V

VP

ENN = 2V/DIV (DC)

ENP = 2V/DIV (DC)

ENP

0V

VN

0V

VP = 2V/DIV (DC)

VN = 2V/DIV (DC)

ENN = 2V/DIV (DC)

ENP = 2V/DIV (DC)

VN

ENN

0V

ENN

-5V

1ms/DIV

FIGURE 62. ON SEQUENCE, 1 GPIO CONTROL

FIGURE 63. OFF SEQUENCE, 1 GPIO CONTROL

FN8724 Rev.2.00

Sep 26, 2017

Page 27 of 33

ISL98608IIH

Depending on which regulator(s) fault, bit(s) , , or

in the FAULT register will be latched to ‘1’ for VP, VN and VBST

faults, respectively. The bit(s) are reset/cleared by cycling both

ENN and ENP (set LOW, then HIGH) at the same time or by

cycling VIN power.

Fault Protection and Monitoring

The ISL98608IIH features extensive protections to automatically

handle failure conditions and protect the IC and application from

damage.

3

2

1

OVERCURRENT PROTECTION (OCP)

Undervoltage protection can be disabled by making selection

from register 0x05.

The overcurrent protection limits the VBST nMOSFET current on a

cycle-by-cycle basis. When the nMOSFET current reaches the

current limit threshold, the nMOSFET is turned off for the

remainder of that cycle. Overcurrent protection does not disable

any of the regulators. Once the fault is removed, the IC will

continue with normal operation.

5

Component Selection

The design of the boost converter is simplified by an internal

compensation scheme, which allows an easy system design

without complicated calculations. Select component values

using the following recommendations.

UNDERVOLTAGE LOCKOUT (UVLO)

If the input voltage (V ) falls below the V

IN UVLO_HYS

level of ~2.3V

Input Capacitor

It is recommended that a 10µF X5R/X7R or equivalent ceramic

capacitor is placed on the VIN input supply to ground.

(typical), the VBST, VP and VN regulators will be disabled. All the

rails will restart with normal soft-start operation when the V

IN

). Refer to the

input voltage is applied again (rising V > V

IN UVLO

“Electrical Specifications” table on page 6 for the UVLO

specifications.

Inductor

First, determine the minimum inductor saturation current

required for the application.

2

Note, the I C registers (logic) are not cleared/reset to default by

the falling V UVLO. The logic states are retained if V remains

IN IN

above 2V (typical). Once V falls below 2V, all logic is reset. V

IN IN

should fall below 2V (ideally to GND) before power is reapplied to

ensure a full power cycle/reset of the device.

The ISL98608IIH operates in Continuous Conduction Mode (CCM)

at higher load current and in Discontinuous Conduction Mode

(DCM) at lighter loads. In CCM, we can calculate the peak

inductor current using Equations 5 through 9.

OVER-TEMPERATURE PROTECTION (OTP)

Given these parameters:

The ISL98608IIH has a hysteretic over-temperature protection

threshold set at +150°C (typical). If this threshold is reached, the

VBST, VP and VN regulators are disabled immediately. As soon as

temperature falls by 20°C (typical) then all the regulators

automatically restart.

• Input Voltage = V

IN

• Output Voltage = V

O

• Duty Cycle = D

All register bits, except for Bit of the FAULT register

0

• Switching Frequency = f

SW

(Register Address 0x04), remain unaffected during an OTP fault

• t

SW

= 1/f

SW

event. When an OTP event occurs, FAULT register bit is

0

Then the inductor ripple can be calculated as:

latched to ‘1’. This bit is reset/cleared by cycling both ENN and

ENP (set LOW, then HIGH) at the same time, or by cycling VIN



(EQ. 5)

(EQ. 6)

I

= V  D  L f



SW

P-P

IN

2

power. Bit can also be reset after it is read twice by I C. A

0

2

single I C read will return the bit value (status) and a second read

Where D = 1 - (V /V ), then rewrite Equation 5:

IN

O

will reset only the OTP bit.



V

O

I

= V  V – V   L f



P-P

IN

O

IN

SW

Output undervoltage protection is disabled during an OTP event.

Since the output voltages decrease during an OTP event because

the regulators are disabled, this will not trigger a UVP fault.

The average inductor current is equal to the average input

current, where I

converter.

can be calculated from the efficiency of the

IAVG

UNDERVOLTAGE PROTECTION (UVP)



Efficiency

(EQ. 7)

(EQ. 8)

I

= V

I

  V

IN

IAVG

O

The ISL98608IIH includes output undervoltage protection.

Undervoltage protection disables the regulator whenever the

output voltage of VBST or VP falls below 60% of its set/regulated

voltage, or the output voltage of VN goes above 60% of its

set/regulated voltage, for 100µs or more. If the output voltage

exceeds the 60% condition for less than 100µs, no fault will

occur.

To find the peak inductor current write the expression as:

I

= I

 2 + I

P-P IAVG

Pk

Substituting Equations 6 and 7 in Equation 8 to calculate I

:

Pk



EFF

IN

I

= 0.5 V

V – V   L f

V

 + V

I

  V

PK

IN

O

IN

SW

O

(EQ. 9)

FN8724 Rev.2.00

Sep 26, 2017

Page 28 of 33

ISL98608IIH

The effective capacitance at the nominal output voltage should

be ≥2.2µF for VBST and VP regulators, and ≥4.4µF for VN. It is

recommended to use a 10µF X5R 10V or equivalent ceramic

output capacitor for both VBST and VP outputs to provide a

minimum of 2.2µF effective capacitance. For the VN output, it is

recommended to use one or two 10µF X5R 10V or equivalent

ceramic output capacitors. Using two VN output capacitors

results in <50mV peak-to-peak output voltage ripple with input

voltages from 2.5V to 5V.

EXAMPLE FOR VBST REGULATOR

Consider the following parameters in the steady state VLED

boost regulator operating in CCM mode.

V

= 2.5V

= 5.3V

IN

O

I

= 0.100A

O

f

= 1.45MHz

SW

Table 4 shows the recommended capacitors for various

regulators in ISL98608IIH.

Efficiency = 80%

L = 2.2µH

Note, capacitors have a voltage coefficient. The effective

capacitance will reduce (derate) as the operating voltage/bias

increases. Always refer to the manufacturer's derating

information to determine effective capacitance for the operating

conditions.

Substituting previous parameters in Equation 9 gives us:

I

= 0.472A

Pk

The VBST regulator can be configured to either use a fixed peak

current or to automatically select the optimal peak current

setting. The automatic mode is designed to dynamically adjust

the peak current to maintain boost output voltage ripple at a

relatively fixed value across input voltage, while improving

efficiency at low input voltages.

TABLE 4. RECOMMENDED OUTPUT CAPACITORS

CAPACITOR PART

NUMBER

VALUE

(µF)

SIZE

QUANTITY

, C ,

GRM155R61A106ME11

(Murata)

10

0402 x5: C , C

IN VBST VP

, C

C

VN CP

In order to avoid the inductor core saturation, the saturation

current of the inductor selected should be higher than the greater

of the peak inductor current (for CCM) and the peak current in

PFM mode and current limit of the regulators. It is recommended

to use an inductor that has saturation current rating higher than

current limit of the boost regulator.

x1: C (x2 for

VN

minimum ripple)

GRM188R61C475KAAJ

(Murata)

4.7

0603 x5: C , C , C ,

IN VBST VP

C

, C

VN CP

x1: C (x2 for

VN

minimum ripple)

Auto PFM mode provides maximum efficiency using 2.2µH for

the VBST regulator. L = 2.2µH is the optimal value for the VBST

regulator.

General Layout Guidelines

When designing the printed circuit board (PCB) layout for the

ISL98608IIH, it is very important to understand the power

requirements of the system. Some general best practices should

be adhered to in order to create an optimal PCB layout:

Table 3 shows the recommended inductors for the VBST boost

regulator.

TABLE 3. RECOMMENDED INDUCTORS FOR VBST REGULATOR

INDUCTOR PART

NUMBER

INDUCTANCE

(µH)

DCR

(mΩ)

I

FOOTPRINT

SIZE

SAT

(A)

1. Careful consideration should be taken with any traces

carrying AC signals. AC current loops should be kept as short

and tight as possible. The current loop generates a magnetic

field, which can couple to another conductor, inducing

unwanted voltage. Components should be placed such that

current flows through them in a straight line as much as

possible. This will help reduce size of loops and reduce the

EMI from the PCB.

VLF302510MT-2R2M

(TDK)

2.2

70

1.23

2.00

1.20

3025

2520

2016

DFE252012C

(Toko)

90

TFM201610G-2R2M

(TDK)

150

2. If trace lengths are long, the resistance of the trace increases

and can cause some reduction in IC efficiency and can also

cause system instability. Traces carrying power should be

made wide and short.

Output Capacitor

The output capacitor supplies current to the load during transient

conditions and reduces the ripple voltage at the output. Output

ripple voltage consists of two components:

3. In discontinuous conduction mode, the direction of the

current is interrupted every few cycles. This may result in large

di/dt (transient load current). When injected in the ground

plane the current may cause voltage drops, which can

interfere with sensitive circuitry. The analog ground and

power ground of the IC should be connected very close to the

IC to mitigate this issue.

1. The voltage drop due to the inductor ripple current flowing

through the ESR of the output capacitor.

2. Charging and discharging of the output capacitor.

For low ESR ceramic capacitors, the output ripple is dominated

by the charging and discharging of the output capacitor. The

voltage rating of the output capacitor should be greater than the

maximum output voltage.

4. One plane/layer in the PCB is recommended to be a

dedicated ground plane. A large area of metal will have lower

resistance, which reduces the return current impedance.

FN8724 Rev.2.00

Sep 26, 2017

Page 29 of 33

ISL98608IIH

More ground plane area minimizes parasitics and avoids

5. Bump D3 is output of the negative charge pump (VN) and

bump D2 is its substrate connection (VSUB). It is highly

recommended that D3 and D2 are shorted together with a

short and thick trace. It is recommended that 2x10μF/10V

capacitors are placed on VN to minimize output ripple.

Additionally, it will help minimize noise that may be coupled

from the high frequency ripple of the charge pump.

corruption of the ground reference.

5. Low frequency digital signals should be isolated from any

high frequency signals generated by switching frequency and

harmonics. PCB traces should not cross each other. If they

must cross due to the layout restriction, then they must cross

perpendicularly to reduce the magnetic field interaction.

6. Bumps B3 is output of the VP regulator. A 10μF/10V

6. The amount of copper that should be poured (thickness)

depends upon the power requirement of the system.

Insufficient copper will increase resistance of the PCB, which

will increase heat dissipation.

capacitor should be placed between VP and power ground.

7. Bump B4 is charge pump positive connection and bump D4 is

charge pump negative connection. A 10μF/10V capacitor

should be placed between bump B4 and D4. The capacitor

between bump B4 and D4 charges and discharges every cycle

and handles high current surges. The capacitor should be

placed between CP and CN using short and thick trace.

7. Generally, vias should not be used to route high current paths.

8. While designing the layout of switched controllers, do not use

the auto routing function of the PCB layout software. Auto

routing connects the nets with the same electrical name and

does not account for ideal trace lengths and positioning.

8. Digital input pins ENN, ENP, SDA and SCL should be isolated

from the high di/dt and dv/dt signals. Otherwise, it may cause

a glitch on those inputs.

ISL98608IIH Specific Layout Guidelines

2

9. I C signals, if not used, should be tied to VIN.

1. The input capacitor should be connected to the VIN pin (C1)

with the smallest trace possible. This helps reject high

frequency disturbances and promotes good regulation of the

VBST, VP and VN regulators.

10. Analog ground (AGND) and power ground (PGND) of the IC

should be connected to each other. It is crucial to connect

these two grounds at the location very close to the IC. The

regulator should be referenced to the correct ground plane

with the short and thick traces. For example, PGND is the

power ground for VBST regulator, a capacitor should be

placed between VBST and PGND with short and thick trace.

All the ground bumps namely PGND, AGND and PGNDCP

should be connected with a network of ground plane.

2. The inductor for VBST regulator should be connected between

VIN and LXP pin with a short and wide trace to reduce the

board parasitics. Careful consideration should be made in

selecting the inductor as it may cause electromagnetic

interference, which could affect IC functionality. A shielded

inductor is recommended.

11. One plane/layer in the PCB is recommended to be a

dedicated ground plane.

3. Bump VBSTCP is input to the charge pump regulator. This pin

must be connected to VBST on the PCB, so that the boost

regulator provides the input voltage supply for the charge

pump. The CSP bumps for VBST and VBSTCP are A3 and A4

respectively. These two bumps should be connected/shorted

to each other on the PCB with a short and thick trace to avoid

parasitic inductance and resistance. A 10μF/10V capacitor

should be used on trace connecting bump A3 and A4 to

PGND. The distance of the capacitor from the bump A3 and

A4 is critical - it should be placed very close to the IC with a

short and thick trace.

12. The solder pad on the PCB should not be larger than the

solder mask opening for the ball pad on the package. The

optimal solder joint strength, it is recommended a 1:1 ratio

for the two pads.

Figure 64 on page 31 shows the recommended PCB layout for a

typical ISL98608IIH application.

4. The current return path for VBST boost regulator should be

small as possible. The bump A1 is PGND. It is power ground

for VBST regulator. A 10μF/10V capacitor should be placed

between VBST and PGND.

FN8724 Rev.2.00

Sep 26, 2017

Page 30 of 33

ISL98608IIH

ISL98608IIH Layout

VBST INDUCTOR

VP CAPACITOR

VBST/VBSTCP

CAPACITOR

VIN CAPACITOR

CP-CN CAPACITOR

VN/VSUB CAPACITOR

FIGURE 64. ISL98608IIH RECOMMENDED PCB LAYOUT

FN8724 Rev.2.00

Sep 26, 2017

Page 31 of 33

ISL98608IIH

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that

you have the latest revision.

DATE

REVISION

FN8724.2

CHANGE

Sep 26, 2017

Updated default value of Register 0x06 = 0x00 throughout the datasheet

In the Electrical Specification table on page, updated bit <b7> for register 0x05 to 0 from 1

Label of LXLED changed to LX in figures 8-13

Eq 1, 2, and 3 have been modified

A detailed description of default value of registers 0x06, 0x08 and 0x09 has been added before "VBST

CONTROL" section

Modified equations in Register 0x06, 0x08 and 0x09 in Register Map

Updated POD W4x4.16G from rev 0 to rev 1. Changes since rev 0:

Updated Typical Recommended Land Pattern Ball values:

-Changed inner measurement from "0.240" to "0.215"

-Changed outer measurement from "0.290" to "0.265"

Added 4, 5, and 6 note markers.

Added Notes 1 and 6.

Switched order of Notes 3 and 4.

Removed old Note 5.

Dec 23, 2015

Apr 1, 2015

FN8724.1

FN8724.0

Updated the input voltage range from “2.5V to 5V” to “2.5V to 5.5V” throughout the datasheet.

In the “Register Map” on page 21, updated BIT<b0> for Register 0x04 changing from “130°C” to “150°C”.

Initial release

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.

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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

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For information regarding Intersil Corporation and its products, see www.intersil.com

FN8724 Rev.2.00

Sep 26, 2017

Page 32 of 33

ISL98608IIH

For the most recent package outline drawing, see W4x4.16G.

Package Outline Drawing

W4x4.16G

16 BALL WLCSP WITH 0.4mm PITCH 4x4 ARRAY (1.740mm x 1.740mm)

Rev 1, 9/16

X

0.400

1.740 ±0.030

Y

D

C

B

16X0.265 ±0.035

1.740 ±0.030

A

0.270

(4X)

0.10

1

2

3

4

0.200

PIN 1 (A1 CORNER)

0.270

TOP VIEW

BOTTOM VIEW

Z

SEATING PLANE

3

PACKAGE OUTLINE

0.05

Z

0.215

0.265

0.400

4

0.265 ±0.035

0.10

0.05

Z X Y

Z

5

6

NSMD

0.200 ±0.030

0.50 ±0.050

TYPICAL RECOMMENDED LAND PATTERN

SIDE VIEW

NOTES:

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASMEY 14.5-1994.

3. Primary datum Z and seating plane are defined by the

spherical crowns of the bump.

4. Dimension is measured at the maximum bump diameter

parallel to primary datum Z.

5. Bump position designation per JESD 95-1, SPP-010.

6. NSMD refers to non-solder mask defined pad design per

Intersil techbrief, TB451.

FN8724 Rev.2.00

Sep 26, 2017

Page 33 of 33


型号：	ISL98608
厂家：	RENESAS TECHNOLOGY CORP
描述：	High Efficiency Single Inductor Positive/Negative Power Supply
文件：	总33页 (文件大小：2660K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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