M16C26A [RENESAS]
16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES; 16位单片机M16C族/ M16C / Tiny系列
| 型号： | M16C26A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/Tiny SERIES |
| 文件： | 总352页 (文件大小：2586K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REJ09B0202-0200
M16C/26A Group
(M16C/26A, M16C/26B, M16C/26T)
16
Hardware Manual
M16C FAMILY / M16C/Tiny SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev. 2.00
Revision Date: Feb.15, 2007
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the M16C/26A Group (M16C/26A, M16C/26B, and M16C/26T). Make sure to
refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the
Renesas Technology Web site.
Document Type
Description
Document Title
Document No.
Hardware manual Hardware specifications (pin assignments,
memory maps, peripheral function
M16C/26A Group This hardware
(M16C/26A,
M16C/26B,
M16C/26T)
manual
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on Hardware Manual
using peripheral functions.
Software manual Description of CPU instruction set
M16C/60,
REJ09B0137
M16C/20,
M16C/Tiny Series
Software Manual
Application note Information on using peripheral functions and
application examples
Available from Renesas
Technology Web site.
Sample programs
Information on writing programs in assembly
language and C
Renesas
Product specifications, updates on documents,
technical update etc.
2. Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1) Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers
The indication “2” is appended to numeric values given in binary format. However, nothing is appended to the
values of single bits. The indication “16” is appended to numeric values given in hexadecimal format. Nothing
is appended to numeric values given in decimal format.
Examples Binary: 112
Hexadecimal: EFA016
Decimal: 1234
3. Register Notation
The symbols and terms used in register diagrams are described below.
*1
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
XXX
Address
XXX
After Reset
0016
0
RW
RW
Bit Symbol
XXX0
Bit Name
XXX bits
Function
*2
b1 b0
1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
XXX1
(b2)
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
*3
Reserved bits
XXX bits
Set to 0.
RW
(b3)
XXX4
XXX5
*4
Function varies according to the operating
mode.
RW
WO
RW
RO
XXX6
XXX7
0: XXX
1: XXX
XXX bit
*1
*2
Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3
*4
• Reserved bit
Reserved bit. Set to specified value.
• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual modes.
4. List of Abbreviations and Acronyms
Abbreviation
Full Form
ACIA
bps
Asynchronous Communication Interface Adapter
bits per second
CRC
DMA
DMAC
GSM
Hi-Z
Cyclic Redundancy Check
Direct Memory Access
Direct Memory Access Controller
Global System for Mobile Communications
High Impedance
IEBus
I/O
Inter Equipment bus
Input/Output
IrDA
LSB
Infrared Data Association
Least Significant Bit
MSB
NC
Most Significant Bit
Non-Connection
PLL
Phase Locked Loop
PWM
SFR
SIM
Pulse Width Modulation
Special Function Registers
Subscriber Identity Module
Universal Asynchronous Receiver/Transmitter
Voltage Controlled Oscillator
UART
VCO
All trademarks and registered trademarks are the property of their respective owners.
IEBus is a registered trademark of NEC Electronics Corporation.
Table of Contents
Quick Reference by Address_______________________ B-1
1. Overview ______________________________________ 1
1.1 Applications ................................................................................................................... 1
1.2 Performance Outline ..................................................................................................... 2
1.3 Block Diagram ............................................................................................................... 4
1.4 Product List ................................................................................................................... 6
1.5 Pin Assignments.......................................................................................................... 11
1.6 Pin Description ............................................................................................................ 15
2. Central Processing Unit (CPU) ____________________ 17
2.1 Data Registers (R0, R1, R2 and R3)........................................................................... 17
2.2 Address Registers (A0 and A1) ................................................................................... 17
2.3 Frame Base Register (FB) .......................................................................................... 18
2.4 Interrupt Table Register (INTB) ................................................................................... 18
2.5 Program Counter (PC) ................................................................................................ 18
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ...................................... 18
2.7 Static Base Register (SB) ........................................................................................... 18
2.8 Flag Register (FLG) .................................................................................................... 18
2.8.1 Carry Flag (C Flag) .............................................................................................. 18
2.8.2 Debug Flag (D Flag) ............................................................................................ 18
2.8.3 Zero Flag (Z Flag) ............................................................................................... 18
2.8.4 Sign Flag (S Flag) ................................................................................................ 18
2.8.5 Register Bank Select Flag (B Flag)...................................................................... 18
2.8.6 Overflow Flag (O Flag)......................................................................................... 18
2.8.7 Interrupt Enable Flag (I Flag) ............................................................................... 18
2.8.8 Stack Pointer Select Flag (U Flag)....................................................................... 18
2.8.9 Processor Interrupt Priority Level (IPL)................................................................ 18
2.8.10 Reserved Area ................................................................................................... 18
3. Memory ______________________________________ 19
4. Special Function Registers (SFRs) _________________ 20
A-1
5. Reset ________________________________________ 26
5.1 Hardware Reset ..........................................................................................................26
5.1.1 Hardware Reset 1 ................................................................................................ 26
5.1.2 Hardware Reset 2 ................................................................................................ 26
5.2 Software Reset............................................................................................................ 27
5.3 Watchdog Timer Reset................................................................................................ 27
5.4 Oscillation Stop Detection Reset................................................................................. 27
5.5 Voltage Detection Circuit ............................................................................................. 29
5.5.1 Voltage Down Detection Interrupt ....................................................................... 32
5.5.2 Limitations on Exiting Stop Mode........................................................................ 34
5.5.3 Limitations on Exiting Wait Mode ........................................................................ 34
6. Processor Mode _______________________________ 35
7. Clock Generation Circuit _________________________ 38
7.1 Main Clock .................................................................................................................. 45
7.2 Sub Clock ....................................................................................................................46
7.3 On-chip Oscillator Clock.............................................................................................. 47
7.4 PLL Clock ....................................................................................................................47
7.5 CPU Clock and Peripheral Function Clock ................................................................. 49
7.5.1 CPU Clock ...........................................................................................................49
7.5.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32) ....... 49
7.5.3 ClockOutput Function .......................................................................................... 49
7.6 Power Control ............................................................................................................. 50
7.6.1 Normal Operation Mode....................................................................................... 50
7.6.2 Wait Mode ............................................................................................................ 51
7.6.3 Stop Mode...........................................................................................................53
7.7 System Clock Protective Function .............................................................................. 57
7.8 Oscillation Stop and Re-oscillation Detect Function ................................................... 57
7.8.1 Operation When the CM27 bit is set to "0" (Oscillation Stop Detection Reset) ... 58
7.8.2 Operation When the CM27 bit is set to "1"
(Oscillation Stop and Re-oscillation Detect Interrupt) .................. 58
7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function......................... 59
8. Protection ____________________________________ 60
9. Interrupt ______________________________________ 61
9.1 Type of Interrupts ........................................................................................................ 61
9.1.1 Software Interrupts............................................................................................... 62
9.1.2 Hardware Interrupts ............................................................................................. 63
A-2
9.2 Interrupts and Interrupt Vector .................................................................................... 64
9.2.1 Fixed Vector Tables.............................................................................................. 64
9.2.2 Relocatable Vector Tables ................................................................................... 65
9.3 Interrupt Control ..........................................................................................................66
9.3.1 I Flag ....................................................................................................................69
9.3.2 IR Bit ....................................................................................................................69
9.3.3 ILVL2 to ILVL0 Bits and IPL .................................................................................69
9.4 Interrupt Sequence......................................................................................................70
9.4.1 Interrupt Response Time...................................................................................... 71
9.4.2 Variation of IPL when Interrupt Request is Accepted ........................................... 71
9.4.3 Saving Registers.................................................................................................. 72
9.4.4 Returning from an Interrupt Routine .................................................................... 74
9.5 Interrupt Priority...........................................................................................................74
9.5.1 Interrupt Priority Resolution Circuit ...................................................................... 74
9.6 _I_N__T__ Interrupt ................................................................................................................76
______
9.7 NMI Interrupt ...............................................................................................................77
9.8 Key Input Interrupt....................................................................................................... 77
9.9 Address Match Interrupt .............................................................................................. 78
10. Watchdog Timer ______________________________ 80
10.1 Count Source Protective Mode .................................................................................81
11. DMAC ______________________________________ 82
11.1 Transfer Cycles.........................................................................................................87
11.2. DMA Transfer Cycles................................................................................................89
11.3 DMA Enable...............................................................................................................90
11.4 DMA Request ............................................................................................................ 90
11.5 Channel Priority and DMA Transfer Timing .............................................................. 91
12. Timer _______________________________________ 92
12.1 Timer A .....................................................................................................................94
12.1.1. Timer Mode ....................................................................................................... 97
12.1.2. Event Counter Mode ......................................................................................... 98
12.1.3. One-shot Timer Mode ..................................................................................... 103
12.1.4. Pulse Width Modulation (PWM) Mode ............................................................ 105
12.2 Timer B ................................................................................................................... 108
12.2.1 Timer Mode ..................................................................................................... 111
12.2.2 Event Counter Mode ........................................................................................ 112
12.2.3 Pulse Period and Pulse Width Measurement Mode ....................................... 113
12.2.4 A/D Trigger Mode ............................................................................................ 115
A-3
12.3 Three-phase Motor Control Timer Function ............................................................ 117
12.3.1 Position-data-retain Function ........................................................................... 128
12.3.2 Three-phase/Port Output Switch Function ....................................................... 130
13. Serial I/O ___________________________________ 132
13.1. UARTi (i=0 to 2)...................................................................................................... 132
13.1.1. Clock Synchronous serial I/O Mode................................................................ 142
13.1.2. Clock Asynchronous Serial I/O (UART) Mode ................................................ 150
2
13.1.3 Special Mode 1 (I C bus mode)(UART2)......................................................... 158
13.1.4 Special Mode 2 (UART2) ................................................................................. 168
13.1.5 Special Mode 3 (IE Bus mode )(UART2) ........................................................ 173
13.1.6 Special Mode 4 (SIM Mode) (UART2) ............................................................ 175
14. A/D Converter _______________________________ 180
14.1 Operation Modes..................................................................................................... 186
14.1.1 One-Shot Mode................................................................................................ 186
14.1.2 Repeat mode ................................................................................................... 188
14.1.3 Single Sweep Mode ........................................................................................ 190
14.1.4 Repeat Sweep Mode 0 .................................................................................... 192
14.1.5 Repeat Sweep Mode 1 .................................................................................... 194
14.1.6 Simultaneous Sample Sweep Mode ................................................................ 196
14.1.7 Delayed Trigger Mode 0................................................................................... 199
14.1.8 Delayed Trigger Mode 1................................................................................... 205
14.2 Resolution Select Function ..................................................................................... 211
14.3 Sample and Hold..................................................................................................... 211
14.4 Power Consumption Reducing Function ................................................................. 211
14.5 Output Impedance of Sensor under A/D Conversion .............................................. 212
15. CRC Calculation Circuit _______________________ 213
15.1. CRC Snoop ............................................................................................................ 213
16. Programmable I/O Ports _______________________ 216
16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)........................................... 216
16.2 Port Pi Register (Pi Register, i = 1, 6 to 10) ............................................................ 216
16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers) ... 216
16.4 Port Control Register............................................................................................... 217
16.5 Pin Assignment Control register (PACR)................................................................. 217
16.6 Digital Debounce function ....................................................................................... 217
17. Flash Memory Version_________________________ 230
17.1 Flash Memory Performance .................................................................................... 230
17.1.1 Boot Mode....................................................................................................... 231
A-4
17.2 Memory Map ...........................................................................................................232
17.3 Functions To Prevent Flash Memory from Rewriting............................................... 235
17.3.1 ROM Code Protect Function............................................................................ 235
17.3.2 ID Code Check Function.................................................................................. 235
17.4 CPU Rewrite Mode .................................................................................................237
17.4.1 EW0 Mode ....................................................................................................... 238
17.4.2 EW1 Mode ....................................................................................................... 238
17.5 Register Description ................................................................................................ 239
17.5.1 Flash memory control register 0 (FMR0) ......................................................... 239
17.5.2 Flash memory control register 1 (FMR1) ......................................................... 240
17.5.3 Flash memory control register 4 (FMR4) ......................................................... 240
17.6 Precautions in CPU Rewrite Mode.......................................................................... 245
17.6.1 Operation Speed.............................................................................................. 245
17.6.2 Prohibited Instructions ..................................................................................... 245
17.6.3 Interrupts..........................................................................................................245
17.6.4 How to Access .................................................................................................245
17.6.5 Writing in the User ROM Space ....................................................................... 245
17.6.6 DMA Transfer ................................................................................................... 246
17.6.7 Writing Command and Data............................................................................. 246
17.6.8 Wait Mode ........................................................................................................ 246
17.6.9 Stop Mode........................................................................................................ 246
17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode ... 246
17.7 Software Commands............................................................................................... 247
17.7.1 Read Array Command (FF16) .......................................................................... 247
17.7.2 Read Status Register Command (7016)........................................................... 247
17.7.3 Clear Status Register Command (5016)........................................................... 248
17.7.4 Program Command (4016) ............................................................................... 248
17.7.5 Block Erase ......................................................................................................249
17.8 Status Register........................................................................................................ 251
17.8.1 Sequence Status (SR7 and FMR00 Bits ) ....................................................... 251
17.8.2 Erase Status (SR5 and FMR07 Bits) ............................................................... 251
17.8.3 Program Status (SR4 and FMR06 Bits)........................................................... 251
17.8.4 Full Status Check............................................................................................. 252
17.9 Standard Serial I/O Mode........................................................................................ 254
17.9.1 ID Code Check Function.................................................................................. 254
17.9.2 Example of Circuit Application in Standard Serial I/O Mode ............................ 258
17.10 Parallel I/O Mode .................................................................................................. 260
17.10.1 ROM Code Protect Function.......................................................................... 260
A-5
18. Electrical Characteristics _______________________ 261
18.1. M16C/26A, M16C/26B (Normal version)................................................................ 261
18.2. M16C/26T (T version) ............................................................................................ 280
19. Usage Notes ________________________________ 299
19.1 SFR ......................................................................................................................... 299
19.1.1 Precaution for 48-pin package ......................................................................... 299
19.1.2 Precaution for 42-pin package ......................................................................... 299
19.1.3 Register Setting ............................................................................................... 299
19.2 PLL Frequency Synthesizer .................................................................................... 300
19.3 Power Control ......................................................................................................... 301
19.4 Protect .....................................................................................................................303
19.5 Interrupts ................................................................................................................. 304
19.5.1 Reading address 0000016 ....................................................................................................304
19.5.2 Setting the SP .................................................................................................. 304
19.5.3 The _N__M___I_ Interrupt ............................................................................................. 304
19.5.4 Changing the Interrupt Generation Factor ....................................................... 304
19.5.5 _I_N__T__ Interrupt ..................................................................................................... 305
19.5.6 Rewrite the Interrupt Control Register ............................................................. 306
19.5.7 Watchdog Timer Interrupt................................................................................. 306
19.6 DMAC...................................................................................................................... 307
19.6.1 Write to DMAE Bit in DMiCON Register .......................................................... 307
19.7 Timer ....................................................................................................................... 308
19.7.1 Timer A............................................................................................................. 308
19.7.2 Timer B............................................................................................................. 311
19.7.3 Three-phase Motor Control Timer Function ..................................................... 312
19.8 Serial I/O ................................................................................................................. 313
19.8.1 Clock-Synchronous Serial I/O.......................................................................... 313
19.8.2 Serial I/O (UART Mode) ................................................................................... 314
19.9 A/D Converter.......................................................................................................... 315
19.10 Programmable I/O Ports ....................................................................................... 317
19.11 Electric Characteristic Differences Between Mask ROM
and Flash Memory Version Microcomputers .................. 318
19.12 Mask ROM Version ............................................................................................... 319
19.12.1 Internal ROM area ......................................................................................... 319
19.12.2 Reserve bit ..................................................................................................... 319
A-6
19.13 Flash Memory Version .......................................................................................... 320
19.13.1 Functions to Inhibit Rewriting Flash Memory ................................................. 320
19.13.2 Stop mode......................................................................................................320
19.13.3 Wait mode ......................................................................................................320
19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode... 320
19.13.5 Writing command and data ............................................................................ 320
19.13.6 Program Command........................................................................................ 320
19.13.7 Operation speed ............................................................................................320
19.13.8 Instructions prohibited in EW0 Mode ............................................................. 320
19.13.9 Interrupts........................................................................................................ 321
19.13.10 How to access.............................................................................................. 321
19.13.11 Writing in the user ROM area....................................................................... 321
19.13.12 DMA transfer ................................................................................................ 321
19.13.13 Regarding Programming/Erasure Times and Execution Time ..................... 321
19.13.14 Definition of Programming/Erasure Times ................................................... 322
19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle product .. 322
19.13.16 Boot Mode.................................................................................................... 322
19.14 Noise .....................................................................................................................323
19.15 Instruction for a Device Use .................................................................................. 324
Appendix 1. Package Dimensions___________________ 325
Appendix 2. Functional Difference __________________ 326
Appendix 2.1 Differences between M16C/26A, M16C/26B, and M16C/26T................... 326
Appendix 2.2 Differences between M16C/26A Group and M16C/26 Group ................... 327
Register Index __________________________________ 328
A-7
Quick Reference by Address
Register
Symbol
Page
Register
Symbol
INT3IC
Page
67
Address
Address
000016
000116
000216
000316
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
35
35
Processor mode register 0
000516 Processor mode register 1
PM0
INT3 interrupt control register
000416
PM1
CM0
CM1
System clock control register 0
System clock control register 1
000616
40
41
000716
000816
INT5 interrupt control register
INT4 interrupt control register
UART2 Bus collision detection interrupt control register BCNIC
DMA0 interrupt control register
DMA1 interrupt control register
INT5IC
INT4IC
67
67
67
67
67
67
67
67
000916 Address match interrupt enable register AIER
79
60
000A16
Protect register
PRCR
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
DM0IC
DM1IC
42
Oscillation stop detection register
CM2
Key input interrupt control register
A/D conversion interrupt control register
UART2 transmit interrupt control register
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
Watchdog timer start register
Watchdog timer control register
WDTS
WDC
81
81
UART2 receive interrupt control register
UART0 transmit interrupt control register
67
67
Address match interrupt register 0
RMAD0
79
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
67
67
67
67
67
67
67
67
67
67
67
67
67
67
Address match interrupt register 1
RMAD1
79
Voltage detection register 1
Voltage detection register 2
VCR1
VCR2
30
30
PLL control register 0
PLC0
PM2
44
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
INT0IC
INT1IC
INT2IC
Processor mode register 2
Voltage down detection interrupt register D4INT
36, 43
30
002116 DMA0 source pointer
SAR0
81
002216
002316
002416
DMA0 destination pointer
DAR0
86
86
85
002516
002616
002716
002816
DMA0 transfer counter
TCR0
002916
002A16
002B16
002C16
DMA0 control register
DM0CON
002D16
002E16
002F16
003016
003116
86
DMA1 source pointer
SAR1
003216
003316
003416
003516
DMA1 destination pointer
DAR1
TCR1
86
86
003616
003716
003816
DMA1 transfer counter
003916
003A16
003B16
003C16
DMA1 control register
DM1CON
85
003D16
003E16
003F16
NOTE:
1. The blank areas are reserved and cannot be accessed by users.
B-1
Quick Reference by Address
Register
Symbol
Page
Register
Symbol
Page
122
Address
Address
008016
008116
008216
008316
008416
008516
008616
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
Timer A1-1 register
TA11
122
122
Timer A2-1 register
Timer A4-1 register
TA21
TA41
119
120
121
121
121
122
129
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
INVC0
INVC1
IDB0
IDB1
DTT
01B016
01B116
01B216
01B316
(2)
(2)
Timer B2 interrupt occurrence frequency set counter ICTB2
Flash memory control register 4
FMR4
242
241
241
01B416
Position-data-retain function contol register PDRF
01B516
Flash memory control register 1
FMR1
FMR0
01B616
01B716
Flash memory control register 0
(2)
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
131
035816 Port function contol register
PFCR
035916
035A16
035B16
035C16
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
035D16
035E16 Interrupt request cause select register 2
IFSR2A
IFSR
68
68, 76
Interrupt request cause select register
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
025A16
131
41
139, 226
43
Three phase protect control register
TPRC
ROCR
PACR
PCLKR
025B16
025C16
On-chip oscillator control register
Pin assignment control register
Peripheral clock select register
025D16
025E16
025F16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
141
141
140
140
137
136
UART2 special mode register 4
UART2 special mode register 3
U2SMR4
U2SMR3
037416
037516
037616
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate generator
U2SMR2
U2SMR
U2MR
037716
037816
U2BRG
037916
037A16
UART2 transmit buffer register
U2TB
136
037B16
138
139
UART2 transmit/receive control register 0
U2C0
U2C1
037C16
033D16
033E16
033F16
UART2 transmit/receive control register 1
037D16
227
227
037E16
NMI digital debounce register
P1 digital debounce register
NDDR
P17DDR
136
UART2 receive buffer register
U2RB
037F16
7
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. This register is included in the flash memory version.
B-2
Quick Reference by Address
Register
Symbol
TABSR
Page
Register
Symbol
AD0
Page
Address
038016
Address
95, 110,
124
Count start flag
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
A/D register 0
A/D register 1
A/D register 2
A/D register 3
A/D register 4
A/D register 5
A/D register 6
184
184
184
184
184
r
0)
96
038116 Clock prescaler reset flag
038216 One-shot start flag
038316 Trigger select register
038416 Up-down flag
038516
CPSRF
ONSF
TRGSR
UDF
AD1
AD2
AD3
AD4
AD5
AD6
96, 124
95
038616
95
Timer A0 register
TA0
038716
038816
95, 122
Timer A1 register
TA1
TA2
038916
184
184
184
038A16
95, 122
95
Timer A2 register
038B16
038C16
Timer A3 register
038D16
TA3
TA4
TB0
TB1
TB2
A/D register 7
AD7
038E16
95, 122
110
Timer A4 register
038F16
039016
Timer B0 register
039116
A/D trigger control register
A/D convert status register 0
A/D control register 2
ADTRGCON
ADSTAT0
ADCON2
183
184
182
039216
110
Timer B1 register
039316
039416
110, 124
Timer B2 register
182
182
039516
A/D control register 0
A/D control register 1
ADCON0
ADCON1
039616 Timer A0 mode register
039716 Timer A1 mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
94
94, 125
94, 125
94
Timer A2 mode register
039816
039916
039A16
039B16
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
94, 125
109
109
109, 125
123, 185
039C16 Timer B1 mode register
039D16 Timer B2 mode register
039E16
Timer B2 special mode register
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
137
136
224
223
UART0 transmit/receive mode register
UART0 bit rate generator
U0MR
U0BRG
Port P1 register
P1
03E316 Port P1 direction register
PD1
136
UART0 transmit buffer register
U0TB
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
138
139
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
U0C0
U0C1
136
UART0 receive buffer register
U0RB
137
136
UART1 transmit/receive mode register
UART1 bit rate generator
U1MR
U1BRG
136
UART1 transmit buffer register
U1TB
03EC16
03ED16
03EE16
224
Port P6 register
Port P7 register
Port P6 direction register
P6
P7
PD6
PD7
P8
138
139
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
U1C0
U1C1
224
223
223
224
03EF16 Port P7 direction register
03F016 Port P8 register
136
138
UART1 receive buffer register
U1RB
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
Port P9 register
Port P8 direction register
P9
PD8
UART transmit/receive control register 2
UCON
224
223
223
224
Port P9 direction register
Port P10 register
PD9
P10
CRC snoop address register
CRC mode register
CRCSAR
CRCMR
214
214
223
Port P10 direction register
PD10
03B816 DMA0 request cause select register
DM0SL
DM1SL
84
85
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
DMA1 request cause select register
03FC16 Pull-up control register 0
03FD16 Pull-up control register 1
03FE16 Pull-up control register 2
03FF16 Port control register
PUR0
PUR1
PUR2
PCR
225
225
225
226
CRC data register
CRC input register
CRCD
CRCIN
214
214
NOTE:
1. The blank areas are reserved and cannot be accessed by users.
B-3
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1. Overview
The M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) is a single-chip control MCU, fabricated using
high-performance silicon gate CMOS technology, embedding the M16C/60 Series CPU core. The M16C/
26A Group (M16C/26A, M16C/26B, M16C/26T) is housed in 42-pin and 48-pin plastic molded packages.
This MCU combines advanced instruction manipulation capabilities to process complex instructions by less
bytes and execute instructions at higher speed. The M16C/26A Group (M16C/26A, M16C/26B, M16C/
26T) has a multiplier and DMAC adequate for office automation, communication devices and industrial
equipment, and other high-speed processing applications. The M16C/26A and M16C/26B have normal
version. The M16C/26T has T version and V version.
1.1 Applications
Audio, cameras, office/communications/portable/ equipment, air-conditioning equipment, home appli-
ances, etc.
page 1
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1.2 Performance Outline
Table 1.1 and 1.2 outline performance overview of the M16C/26A Group (M16C/26A, M16C/26B, M16C/
26T).
Table 1.1. M16C/26A Group(M16C/26A, M16C/26B, M16C/26T) Performance (48-Pin Package)
Item
Specification
CPU
Basic instructions
Minimun instruction
execution time
91 instructions
(3)
41.7 ns (f(BCLK) = 24MH
Z
, VCC = 4.2 to 5.5 V)
, VCC = 3.0 to 5.5 V)
100 ns (f(BCLK) = 10MH , VCC = 2.7 to 5.5 V)
50 ns (f(BCLK) = 20MH
(M16C/26B)
(M16C/26A, M16C/26B, M16C/26T(T-ver.))
(M16C/26A , M16C/26B)
50 ns (f(BCLK) = 20MH
Z
Z
Z
, VCC = 4.2 to 5.5 V -40 to 105°C)
(M16C/26T(V-ver.))
(M16C/26T(V-ver.))
62.5 ns (f(BCLK) = 16MH
Single-chip mode
1 Mbyte
Z
, VCC = 4.2 to 5.5 V -40 to 125°C)
Operating mode
Address space
Memory capacity
I/O ports
ROM/RAM: See 1.4 Product Information
Peripheral
Function
39 I/O pins
Multifunction timers
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase motor control timer
Serial I/O
2 channels (UART, clock synchronous serial I/O)
2
(1)
1 channel (UART, clock synchronous, I C bus, or IEBus
)
A/D converter
DMAC
10 bit A/D Converter : 1 circuit, 12 channels
2 channels
CRC calcuration circuit
Watchdog timer
Interrupts
1 circuit (CRC-CCITT and CRC-16) with MSB/LSB selectable
15 bits x 1 channel (with prescaler)
20 internal and 8 external sources, 4 software sources,
Interrupt priority level: 7
Clock generation circuit
4 circuits
Main clock oscillation circuit(*), Sub-clock oscillation circuit(*)
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resister.
Oscillation stop detection
Voltage detection circuit
Power supply voltage
Main clock oscillation stop, re-oscillation detection function
On-chip (M16C/26A, M16C/26B), not on-chip (M16C/26T)
Electrical
VCC = 4.2 to 5.5 V (f(BCLK) = 24 MHZ)(3)
VCC = 3.0 to 5.5 V (f(BCLK) = 20 MHZ)
VCC = 2.7 to 5.5 V (f(BCLK) = 10 MHZ)
VCC = 3.0 to 5.5 V
(M16C/26B)
Characteristics
(M16C/26A, M16C/26B)
(M16C/26T(T-ver.))
(M16C/26T(V-ver.))
VCC = 4.2 to 5.5 V
Power consumption
20 mA (Vcc = 5 V, f(BCLK) = 24 MHz) (M16C/26B)
16 mA (Vcc = 5 V, f(BCLK) = 20 MHz)
25 µA (f(XCIN) = 32 KHz on RAM)
3 µA (Vcc = 3 V, f(XCIN) = 32 KHz, in wait mode)
0.7 µA (Vcc = 3 V, in stop mode)
Flash Memory Programming /erasure
2.7 to 5.5 V (M16C/26A, M16C/26B)
Version
voltage
3.0 to 5.5 V (M16C/26T(T-ver.)) 4.2 to 5.5 V (M16C/26T(V-ver.))
100 times (all area) or 1,000 times (block 0 to 3)
/ 10,000 times (block A, block B)(2)
Programming /erasure
endurance
Operating Ambient Temperature
-20 to 85°C / -40 to 85°C (2)
(M16C/26A , M16C/26B)
(M16C/26T(T-ver.))
(M16C/26T(V-ver.))
-40 to 85°C
-40 to 105°C / -40 to 125°C
48-pin plastic molded QFP
Package
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. See Tables 1.7 to 1.10 Product Code for the program and erase endurance, and operating ambient temperature.
3. The PLL frequency synthesizer is used to run the M16C/26B at f(BCLK) = 24 MHz.
page 2
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 1.2. Performance outline of M16C/26A group (M16C/26A, M16C/26B) (42-pin package)
Item
Performance
CPU
Basic instructions
Minimun instruction
execution time
91 instructions
41.7 ns (f(BCLK) = 24 MHz (3), VCC = 4.2 to 5.5 V
50 ns (f(BCLK) = 20 MH , VCC = 3.0 to 5.5 V)
, VCC = 2.7 to 5.5 V)
(M16C/26B)
(M16C/26A, M16C/26B)
(M16C/26A, M16C/26B)
Z
100 ns (f(BCLK) = 10 MH
Single-chip mode
1M byte
Z
Operation mode
Address space
Memory capacity
Port
ROM/RAM: See 1.4 Product Information
Peripheral
function
33 I/O pins
Multifunction timer
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 3 channels
Three-phase motor control timer
Serial I/O
1 channel (UART, clock synchronous serial I/O)
1 channel (UART, clock synchronous, I2C bus, or IEBus(1)
10 bit A/D converter: 1 circuit, 10 channels
2 channels
)
A/D converter
DMAC
CRC calcuration circuit
Watchdog timer
Interrupt
1 circuits (CRC-CCITT and CRC-16) with MSB/LSB selectable
15 bits x 1 channel (with prescaler)
18 internal and 8 external sources, 4 software sources,
Interrupt priority level: 7
Clock generation circuit
4 circuits
Main clock(*), Sub-clock(*)
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resister.
Main clock oscillation stop, re-oscillation detection function
On-chip
Oscillation stop detection
Voltage detection circuit
Supply voltage
Electrical
VCC = 4.2 to 5.5 V (f(BCLK) = 24 MHZ)(3)
VCC = 3.0 to 5.5 V (f(BCLK) = 20 MHZ)
VCC = 2.7 to 5.5 V (f(BCLK) = 10 MHZ)
(M16C/26B)
(M16C/26A, M16C/26B)
Characteristics
Power Consumption
20 mA (Vcc = 5 V, f(BCLK) = 24 MHz) (M16C/26B)
16 mA (Vcc = 5 V, f(BCLK) = 20 MHz)
25 µA (f(XCIN) = 32 KHz on RAM)
3 µA (Vcc = 3 V, f(XCIN) = 32 KHz, in wait mode)
0.7 µA (Vcc = 3 V, in stop mode)
Flash memory Programming/erasure
voltage
2.7 to 5.5 V
Programming/erasure
endurance
100 times (all area) or 1,000 times (block 0 to 3)
/ 10,000 times (block A, block B)(2)
-20 to 85°C / -40 to 85°C (2)
Operating Ambient Temperature
Package
42-pin plastic molded SSOP
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. See Tables 1.7 and 1.8 Product Code for the program and erase endurance, and operating ambient tempera-
ture.
3. The PLL frequency synthesizer is used to run the M16C/26B at f(BCLK) = 24 MHz.
page 3
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1.3 Block Diagram
Figure 1.1 and 1.2 show block diagrams of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 48-
pin package and 42-pin package.
3
8
8
8
4
8
Port P9
Port P8
Port P7
Port P10
Port P6
Port P1
Peripheral functions
Clock generation circuit
Timer (16-bit)
Output (timer A): 5channels
Input (timer B): 3 channels
UART or
clock synchronous serial I/O
(8 bits X 3 channels)
XIN-XOUT
XCIN-XCOUT
On-Chip Oscillator
PLL frequency synthesizer
Three-phase motor
control circuit
10-bit A/D converter
12 channels
M16C/60 series CPU core
Memory
R0H
R1H
R0L
R1L
SB
ROM(1)
RAM(2)
Watchdog timer
(15 bits)
USP
ISP
R2
R3
DMAC
(2 channels)
INTB
PC
FLG
A0
A1
FB
Multiplier
CRC calculation circuit
(CCITT, CRC-16 )
NOTES:
1: ROM size depends on the MCU type.
2: RAM size depends on the MCU type.
Figure 1.1 Block Diagram(48-pin Package)
page 4
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
3
4
8
8
2
8
Port P9
Port P8
Port P7
Port P10
Port P6
Port P1
Peripheral functions
Clock generation circuit
Timer (16-bit)
Output (timer A): 5channels
Input (timer B): 3 channels
UART or
clock synchronous serial I/O
(8 bits X 2 channels)
XIN-XOUT
XCIN-XCOUT
On-Chip Oscillator
PLL frequency synthesizer
Three-phase motor
control circuit
10-bit A/D converter
10 channels
M16C/60 series CPU core
Memory
R0H
R1H
R0L
R1L
ROM(1)
RAM(2)
SB
Watchdog timer
(15 bits)
USP
ISP
R2
R3
DMAC
(2 channels)
INTB
PC
FLG
A0
A1
FB
Multiplier
CRC calculation circuit
(CCITT, CRC-16 )
NOTES:
1: ROM size depends on the MCU type.
2: RAM size depends on the MCU type.
Figure 1.2 Block Diagram( 42-pin Package)
page 5
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1.4 Product List
Tables 1.3 to 1.6 lists product information, Figure 1.3 shows a product numbering system, Table 1.7 lists
the product code, and Figure 1.4 shows the marking.
Table 1.3 M16C/26A
Current as of Feb., 2007
ROM
Capacity
RAM
Capacity
Type Number
Package Type
Remarks
Product Code
M30260F3AGP
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
24K + 4K
48K + 4K
64K + 4K
24K + 4K
48K + 4K
64K + 4K
24K
1K
2K
2K
1K
2K
2K
1K
2K
2K
1K
2K
2K
M30260F6AGP
PLQP0048KB-A (48P6Q-A)
U3, U5, U7, U9
M30260F8AGP
Flash
memory
M30263F3AFP
M30263F6AFP
PRSP0042GA-B (42P2R)
PLQP0048KB-A (48P6Q-A)
PRSP0042GA-B (42P2R)
U5, U9
U3, U5
U5
M30263F8AFP
M30260M3A-XXXGP
M30260M6A-XXXGP
M30260M8A-XXXGP
M30263M3A-XXXFP
M30263M6A-XXXFP
M30263M8A-XXXFP
48K
64K
Mask ROM
24K
48K
64K
(N): New
Table 1.4 M16C/26B
Current as of Feb., 2007
ROM
Capacity
RAM
Capacity
Type Number
Package Type
Remarks
Product Code
M30260F8BGP
M30263F8BFP
(N)
(N)
64K + 4K
64K + 4K
2K
2K
PLQP0048KB-A (48P6Q-A)
PRSP0042GA-B (42P2R)
U7
U9
Flash
memory
(N): New
Table 1.5 M16C/26T T-ver.
Current as of Feb., 2007
ROM
Capacity
RAM
Capacity
Type Number
Package Type
Remarks
Product Code
M30260F3TGP
M30260F6TGP
M30260F8TGP
NOTE:
24K + 4K
48K + 4K
64K + 4K
1K
2K
2K
Flash
memory
PLQP0048KB-A (48P6Q-A)
U3, U7
1. Available in flash memory version only.
Table 1.6 M16C/26T V-ver.
Current as of Feb., 2007
ROM
Capacity
RAM
Capacity
Type Number
Package
Remarks
Product Code
U3, U7
Flash
memory
M30260F8VGP
NOTE:
64K + 4K
2K
PLQP0048KB-A (48P6Q-A)
1. Available in flash memory version only.
page 6
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Type No. M 3 0 2 6 0 M 8 A - XXX G P - U3
Product code:
See Tables 1.7 to 1.10
Package type:
GP: PLQP0048KB-A (48P6Q) (M16C/26A, M16C/26B, M16C/26T)
FP: PRSP0042GA-B (42P2R) (M16C/26A, M16C/26B)
ROM number:
ROM number is omitted in flash memory version
Version:
A
B
T
V
: M16C/26A
: M16C/26B
: M16C/26T T-ver.
: M16C/26T V-ver.
ROM / RAM capacity:
3: (24K+4K) bytes (1) / 1K bytes
6: (48K+4K) bytes (1) / 2K bytes
8: (64K+4K) bytes (1) / 2K bytes
NOTE:
1. Only flash memory version exists in "+4K bytes"
Memory type:
M: Mask ROM version
F: Flash memory version
Pin count (The value itself has no specific meaning)
M16C/26A Group
M16C Family
Figure 1.3 Product Numbering System
page 7
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 1.7 Product Code (Flash Memory Version) - M16C/26A, M16C/26B
Internal ROM
Internal ROM
(Program Space: Blocks 0 to 3)
(Data Space: Blocks A and B)
Product
Code
Operating Ambient
Package
Program and
Temperature
Erase
Program and
Temperature
Erase
Temperature
Range
Range
Endurance
Endurance
U3
-40 to 85ºC
-20 to 85ºC
-40 to 85ºC
-20 to 85ºC
100
100
0 to 60ºC
U5
U7
U9
Lead free
0 to 60ºC
1,000
-40 to 85ºC
-20 to 85ºC
10,000
Table 1.8 Product Code (Mask ROM Version - M16C/26A)
Product
Code
Operating Ambient
Temperature
Package
Lead free
U3
-40ºC to 85ºC
-20ºC to 85ºC
U5
NOTE:
1. The lead contained products, D3, D5, D7, and D9 are put together with U3, U5, U7, and U9 respectively.
Lead-free products can be mounted by both conventional Sn-Pb paste and Lead-free paste (Sn-Ag-Cu
plating).
Table 1.9 Product Code (Flash Memory Version) - M16C/26T T-ver.
Internal ROM
Internal ROM
(Program Space: Blocks 0 to 3)
(Data Space: Blocks A and B)
Product
Code
Operating Ambient
Temerature
Package
Lead free
Programming
Temperature
and erasure
range
Programming
Temperature
and erasure
range
endurance
endurance
U3
U7
100
100
0ºC to 60ºC
1,000
-40ºC to 85ºC
10,000
-40ºC to 85ºC
Table 1.10 Product Code (Flash Memory Version) - M16C/26T V-ver.
Internal ROM
Internal ROM
(Program Space: Blocks 0 to 3)
(Data Space: Blocks A and B)
Product
Code
Operating Ambient
Temerature
Package
Lead free
Programming
Temperature
and erasure
range
Programming
Temperature
and erasure
range
endurance
endurance
U3
U7
100
100
0ºC to 60ºC
1,000
-40ºC to 125ºC
10,000
-40ºC to 125ºC
page 8
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26A, M16C/26B
Product Name : indicates M30260F8AGP
0260F8A
A U3
Chip Version and Product Code:
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
XXXXX
U3 : Indicates Product code (see Table 1.7 Product Code)
Date Code (5 digits) fi indicates manufacturing management code
(2) Flash memory version, PRSP0042GA-B (42P2R), M16C/26A, M16C/26B
Product Name : indicates M30263F8AFP
M30263F8AFP
A U3
Chip Version and Product Code:
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
XXXXXXX
U3 : Indicates Product code (see Table 1.7 Product Code)
Date Code (7 digits) fi indicates manufacturing management code
(3) MASK ROM version, PLQP0048KB-A (48P6Q), M16C/26A
Product Name : indicates M30260M8AGP
0260M8A
001A U3
XXXXX
ROM number, Chip Version and Product Code:
001: Indicates ROM Number
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
U3 : Indicates Product code (see Table 1.8 Product Code)
Date Code (5 digits) fi indicates manufacturing management code
(4) MASK ROM version, PRSP0042GA-B (42P2R), M16C/26A
Product Name and ROM number
M30263M8A and FP are indicated of Produnct name
001 is indicated of ROM number
M30263M8A-001FP
A U3
Chip Version and Product Code:
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
XXXXXXX
U3 : Indicates Product code (see Table 1.8 Product Code)
Date Code (7 digits) fi indicates manufacturing management code
Figure 1.4 Marking Diagram (M16C/26A , M16C/26B)
page 9
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T T-ver.
0260F8T
Product Name : indicates M30260F8TGP
A U3
Chip Version and Product Code:
A : Indicates chip version
XXXXX
The first edition is shown to be blank and continues
with A and B.
U3 : Indicates product code (see Table 1.9 Product Code)
Date Code (5 digits) fi indicates manufacturing management code
(2) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T V-ver.
0260F8V
A U3
Product Name : indicates M30260F8VGP
Chip Version and Product Code:
A : Indicates chip version
XXXXX
The first edition is shown to be blank and continues
with A and B.
U3 : Indicates product code (see Table 1.10 Product Code)
Date Code (5 digits) fi indicates manufacturing management code
Figure 1.5 Marking Diagram (M16C/26T)
page 10
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1.5 Pin Assignments
Figures 1.6 and 1.7 show the Pin Assignments (top view).
P10
P10
P10
7
/AN
/AN
/AN
7
/KI
/KI
/KI
3
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
P7
1
/RxD
/CLK
/CTS
/TA2OUT/W
2
/TA0IN/SCL
/TA1OUT/V/RxD
/RTS /TA1IN/V/TxD
2/CLK1
P72
2
1
6
5
6
5
2
1
P7
P7
3
4
2
2
1
P10
4
/AN
4
/KI
0
P10
P10
P10
3/AN
2/AN
1
/AN
3
2
1
P75
/TA2IN/W
/TA3OUT
/TA3IN
P76
P77
AVss
P8
0
1
/TA4OUT/U
/TA4IN/U
/INT
P10
0/AN
0
P8
V
REF
P82
0
AVcc
P83
/INT
1
P9
3
/AN24
P84/INT2/ZP
NOTE:
1. Set PACR2 to PACR0 bit in the PACR register
to "100 " before you input and output it after
2
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the pins are disabled.
Package: PLQP0048KB-A (48P6Q)
Figure 1.6 Pin Assignment for 48-Pin Package (Top View)
page 11
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 1.11 Pin Characteristics for 48-Pin Package
Pin
No.
Control
Pin
Interrupt
Pin
Port
Timer Pin
UART Pin
Analog Pin
1
2
P92
P91
P90
TB2IN
AN3
AN3
AN3
2
1
0
TB1IN
TB0IN
3
CLKOUT
4
CNVss
5
X
CIN
P8
7
6
6
XCOUT
P8
7
RESET
8
XOUT
9
Vss
10
XIN
11 Vcc
12
P85
P84
P83
P82
P81
P80
P77
P76
P75
P74
P73
P72
P71
NMI
SD
ZP
13
INT
INT
INT
2
1
0
14
15
16
TA4IN / U
TA4OUT / U
TA3IN
17
18
19
TA3OUT
20
TA2IN / W
TA2OUT / W
TA1IN / V
TA1OUT / V
TA0IN
21
22
CTS
2
/ RTS
2
/ T
X
D1
23
CLK
2
/ RX
D1
24
RX
D2
/ SCL
2
/ CLK
1
25
P70
P67
P66
P65
P64
P63
P62
P61
P60
P17
P16
P15
TA0OUT
T
T
X
X
D
2
1
/ SDA2 / RTS1 / CTS1 / CTS0 / CLKS1
26
D
27
RXD1
28
CLK
1
1
29
RTS
/ CTS
/ CTS
1
/ CTS0 / CLKS1
30
TXD0
31
RXD0
32
CLK
0
0
33
RTS
0
34
INT
INT
INT
5
4
3
IDU
IDW
IDV
35
36
ADTRG
37
P10
P10
P10
P10
P10
P10
P10
7
6
5
4
3
2
1
KI
KI
KI
KI
3
2
1
0
AN
AN
AN
AN
AN
AN
AN
7
6
5
4
3
2
1
38
39
40
41
42
43
44 AVss
45
P10
0
AN0
46
VREF
47 AVcc
48
P93
AN24
page 12
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
P10
P10
P10
P10
P10
P10
P10
1
/AN
/AN
/AN
/AN
/AN
/AN
/AN
1
AVSS
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
2
2
P100/AN0
V
REF
3
3
3
AVCC
1/TB1IN/AN31
4
4
/KI
/KI
/KI
/KI
0
4
5
5
1
P9
5
P9
0
/TB0IN/AN30/CLKout
CNVSS
6
6
2
6
7
7
3
7
P15
/INT
3
/ADTRG/IDV
P8
7
/XCIN
8
P1
P1
6
7
/INT
/INT
4
5
/IDW
/IDU
P86
/XCOUT
9
RESET
10
11
12
13
14
15
16
17
18
19
20
21
P64
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
X
V
OUT
SS
P65
/CLK
1
XIN
P66
/RxD
1
P6
P7
P7
7
/TxD
/TxD
/RxD
/CLK
/CTS
/TA2OUT/W
1
V
CC
0
2
/SDA
/SCL
/TA1OUT/V/RxD
/RTS /TA1IN/V/TxD
2
/TA0OUT/CTS
1/RTS1/CTS0/CLKS1
P8
5
/NMI/SD
P84
/INT /ZP
2
1
2
2
/TA0IN/CLK
1
P8
P8
3
/INT
1
0
P72
2
1
2/INT
P73
2
2
1
P81
/TA4IN/U
/TA4OUT/U
P7 /TA3IN
P7
P7
P7
4
P8
0
5
/TA2IN/W
7
6
/TA3OUT
NOTE:
1. Set PACR2 to PACR0 bit in the PACR register
to "001 " before you input and output it after
2
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the pins are disabled.
Package: PRSP0042GA-B (42P2R)
Figure 1.7 Pin Assignment for 42-Pin Package (Top View)
page 13
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 1.12 Pin Characteristics for 42-Pin Package
Pin
No.
Control
Pin
Interrupt
Pin
Port
Timer Pin
UART Pin
Analog Pin
1
2
3
4
5
6
7
8
9
AVss
P10
0
AN
0
VREF
AVCC
P9
1
0
TB1IN
AN3
1
0
P9
TB0IN
CLKOUT
AN3
CNVss
XCIN
P8
7
6
XCOUT
P8
10 RESET
11
12 Vss
XOUT
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
X
IN
VCC
P85
P84
P83
P82
P81
P80
P77
P76
P75
P74
P73
P72
P71
NMI
SD
ZP
INT
INT
INT
2
1
0
TA4IN / U
TA4OUT / U
TA3IN
TA3OUT
TA2IN / W
TA2OUT / W
TA1IN / V
TA1OUT / V
TA0IN
CTS
2
/ RTS
2
/ T
X
D
1
CLK
2
/ RX
D1
RX
D2
/ SCL
2
/ CLK
1
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
P7
P6
P6
P6
P6
P1
P1
P1
0
7
6
5
4
7
6
5
TA0OUT
T
T
X
X
D
2
1
/ SDA2 / RTS1 / CTS1 / CTS0 / CLKS1
D
RXD1
CLK
1
1
RTS
/ CTS1/ CTS0 / CLKS1
INT
INT
INT
5
4
3
IDU
IDW
IDV
ADTRG
P10
P10
P10
P10
P10
P10
P10
7
6
5
4
3
2
1
KI
KI
KI
KI
3
2
1
0
AN
AN
AN
AN
AN
AN
AN
7
6
5
4
3
2
1
page 14
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1.6 Pin Description
Table 1.13 Pin Description (48-Pin and 42-Pin Packages)
Classification Pin Name I/O Type
Description
Power Supply
I
Apply 0V to the Vss pin. Apply following voltage to the Vcc pin.
VCC, VSS
2.7 to 5.5 V (M16C/26A, M16C/26B), 3.0 to 5.5 V (M16C/26T T-ver.), 4.2
to 5.5 V (M16C/26T V-ver.)
Analog Power
Supply
Supplies power to the A/D converter. Connect the AVCC pin to VCC and
AVCC
I
the AVSS pin to VSS
AVSS
___________
____________
Reset Input
CNVSS
RESET
CNVSS
XIN
The MCU is in a reset state when "L" is applied to the RESET pin
Connect the CNVSS pin to VSS
I
I
I
Main Clock
Input
I/O pins for the main clock oscillation circuit. Connect a ceramic resonator
or crystal oscillator between XIN and XOUT. To apply external clock, apply
it to XIN and leave XOUT open. If XIN is not used (for external oscillator or
external clock), connect XIN pin to VCC and leave XOUT open
I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator
between XCIN and XCOUT
Main Clock
Output
XOUT
O
Sub Clock Input XCIN
I
Sub Clock Output
XCOUT
O
O
I
Clock Output
CLKOUT
Outputs the clock having the same frequency as f1, f8, f32, or fC
______
________
INT Interrupt
INT0 to INT5
Input pins for the _I_N__T__ interrupt. INT2 can be used for Timer A Z-phase
________
________
Input
function
_______
_N__M___I_ interrupt input pin. _N__M___I_ cannot be used as I/O port while the three-phase
motor control is enabled. Apply a stable "H" to _N__M___I_ after setting it's direction
register to "0" when the three-phase motor control is enabled
Input pins for the key input interrupt
_______
NMI Interrupt
Input
NMI
I
_____
_____
Key Input Interrupt
KI0 to KI3
TA0OUT to
TA4OUT
TA0IN to
TA4IN
I
Timer A
I/O pins for the timer A0 to A4
I/O
Input pins for the timer A0 to A4
I
Input pin for Z-phase
ZP
I
I
Timer B
TB0IN to
TB1IN
Timer B0 to B1 input pins
___
___
Three-Phase
Output pins for the three-phase motor control timer
I/O pins for the three-phase motor control timer
U, U, V, V,
O
___
Motor Control W, W
Timer Output
Serial I/O
IDU, IDW,
_____
I/O
IDV, SD
_________
_________
Input pins to control data transmission
Output pins to control data reception
Inputs and outputs the transfer clock
Inputs serial data
CTS1 to CTS2
I
O
I/O
I
_________
_________
RTS1 to RTS2
CLK1 to CLK2
RxD1 to RxD2
TxD1 to TxD2
CLKS1
Outputs serial data
O
O
I
Output pin for transfer clock
Reference
VREF
Applies reference voltage to the A/D converter
Voltage Input
A/D Converter
Analog input pins for the A/D converter
AN0 to AN7
I
AN30 to AN31
___________
ADTRG
I
Input pin for an external A/D trigger
I/O Ports
I/O ports for CMOS. Each port can be programmed for input or output
under the control of the direction register. An input port can be set, by
program, for a pull-up resistor available or for no pull-up resister available
in 3-bit units
P15 to P17
I/O
CMOS I/O ports which have a direction register determines an individual
pin used as an input port or an output port. A pull-up resistor is selectable
for every 4 input ports
P64 to P67
P70 to P77
P80 to P87
I/O
P10
0 to P107
P90 to P91
I : Input
O : Output
I/O : Input and output
page 15
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 1.13 Pin Description ( 48-pin packages only) (Continued)
Classification Pin Name I/O Type
Description
_________
Serial I/O
CTS0
I
O
I/O
I
Inputs pin to control data transmission
Output pin to control data reception
Inputs and outputs the transfer clock
Inputs serial data
_________
RTS0
CLK0
RxD0
TxD0
TB2IN
O
I
Outputs serial data
Timer B
Timer B2 input pin
A/D Converter AN24
AN32
I
Analog input pins for the A/D converter
CMOS I/O ports which have a direction register determines an individual
pin used as an input port or an output port. A pull-up resistor is selectable
for every 4 input ports
I/O Ports
P60 to P63
P92 to P93
I/O
I : Input
O : Output
I/O : Input and output
page 16
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
2. CPU
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The register bank is comprised of seven registers (R0, R1, R2, R3,
A0, A1 and FB) out of 13 registers. There are two sets of register bank.
b31
b15
b8b7
b0
R2
R3
R0H(R0's high bits) R0L(R0's low bits)
R1H(R1's high bits)R1L(R1's low bits)
Data registers (1)
R2
R3
A0
A1
FB
Address registers (1)
Frame base registers (1)
b19
b15
b0
INTBH
INTBL
Interrupt table register
Program counter
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
b0
PC
b15
USP
User stack pointer
Interrupt stack pointer
Static base register
SB
b15
b0
b0
FLG
Flag register
b15
b8 b7
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1. CPU Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address regis-
ter relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as
A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
page 17
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
2. CPU
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to 0.
2.8.3 Zero Flag (Z Flag)
This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.
2.8.4 Sign Flag (S Flag)
This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1.
2.8.6 Overflow Flag (O Flag)
This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1.
The I flag is cleared to 0 when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0; USP is selected when the U flag is 1.
The U flag is cleared to 0 when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write 0. When read, its content is undefined.
page 18
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
3. Memory
3. Memory
Figure 3.1 is a memory map of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T). The M16C/26A
Group provides 1-Mbyte address space addresses 0000016 to FFFFF16.
The internal ROM is allocated lower address, beginning with address FFFFF16. For example, a 64-Kbyte
internal ROM area is allocated in addresses F000016 to FFFFF16. The flash memory version has two sets
of 2-Kbyte internal ROM area, block A and block B, for data space. These blocks are allocated addresses
F00016 to FFFF16.
The fixed interrupt vectors are allocated addresses FFFDC16 to FFFFF16 and they store the start address
of each interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 0040016. For example, a 1-Kbyte
internal RAM area is allocated in addresses 0040016 to 007FF16. The internal RAM is used for temporarily
storing data. The area is also used as stacks when subroutines are called or interrupt requests are ac-
knowledged.
The SFR is allocated addresses 0000016 to 003FF16. The peripheral function control registers are allo-
cated here. All blank spaces within SFR location are reserved and cannot be accessed by users.
The special page vectors are allocated addresses FFE0016 to FFFDB16. They are used for the JMPS
instruction and JSRS instruction. Refer to the Renesas publication M16C/60 and M16C/20 Series Soft-
ware Manual for details.
0000016
SFR
FFE0016
0040016
Internal RAM
XXXXX16
0F00016
0FFFF16
Special page
vector table
Reserved
Internal ROM
Internal RAM
(1)
Size
Address XXXXX16
007FF16
Internal ROM
(Data space)
Size
Address YYYYY16
FA00016
1K bytes
2K bytes
24K bytes
FFFDC16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
00BFF16
48K bytes
64K bytes
F400016
F000016
Reserved
YYYYY16
FFFFF16
Watchdog timer
Internal ROM(2)
(Program space)
DBC
NMI
Reset
FFFFF16
NOTE:
1. Block A (2 Kbytes) and block B (2 Kbytes).
2. Do not write to the internal ROM in Mask ROM version.
Figure 3.1 Memory Map
page 19
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
4. SFRs
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
4. Special Function Registers (SFRs)
(1)
Table 4.1 SFR Information(1)
Address
Register
Symbol
After reset
000016
000116
000216
000316
000416
000516
000616
Processor mode register 0
Processor mode register 1
System clock control register 0
PM0
PM1
CM0
0016
00001000
01001000
2
2
(5)
011010002(M16C/26T)
00100000
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
System clock control register 1
CM1
2
Address match interrupt enable register
Protect register
AIER
PRCR
XXXXXX00
XX000000
2
2
Oscillation stop detection register(2)
CM2
0X000000
2
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
XX16
00XXXXXX
0016
2
0016
X016
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1 (3, 4)
Voltage detection register 2 (3, 4)
VCR1
VCR2
00001000
0016
2
PLL control register 0
PLC0
0001X0102
Processor mode register 2
Low voltage detection interrupt register(4)
PM2
D4INT
SAR0
XXX00000
0016
2
002016 DMA0 source pointer
XX16
002116
XX16
002216
XX16
002316
002416 DMA0 destination pointer
002516
DAR0
XX16
XX16
XX16
002616
002716
002816 DMA0 transfer counter
002916
TCR0
XX16
XX16
002A16
002B16
002C16 DMA0 control register
002D16
DM0CON
SAR1
00000X002
002E16
002F16
003016 DMA1 source pointer
003116
XX16
XX16
XX16
003216
003316
003416 DMA1 destination pointer
003516
DAR1
XX16
XX16
XX16
003616
003716
003816 DMA1 transfer counter
003916
TCR1
XX16
XX16
003A16
003B16
003C16 DMA1 control register
DM1CON
00000X002
003D16
003E16
003F16
NOTES:
1. The blank spaces are reserved. No access is allowed.
2. Bits CM27, CM21, and CM20 do not change at oscillation stop detection reset.
3. The VCR1 and VCR2 registers do not change at software reset, watchdog timer reset, and oscillation stop detection reset.
4. Registers VCR1, VCR2, and D4INT cannot be used in M16C/26T.
5. M16C/26A, M16C/26B
X : Undefined
page 20
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
4. SFRs
(1)
Table 4.2 SFR Information(2)
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Register
Symbol
INT3IC
After reset
XX00X000
INT3 interrupt control register
2
INT5 interrupt control register
INT4 interrupt control register
INT5IC
INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XX00X000
XX00X000
2
2
UART2 Bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Key input interrupt control register
A/D conversion interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
TimerA0 interrupt control register
TimerA1 interrupt control register
TimerA2 interrupt control register
TimerA3 interrupt control register
TimerA4 interrupt control register
TimerB0 interrupt control register
TimerB1 interrupt control register
TimerB2 interrupt control register
INT0 interrupt control register
XX00X000
XX00X000
XX00X000
2
INT1 interrupt control register
INT2 interrupt control register
2
2
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
NOTE:
1. Blank spaces are reserved. No access is allowed.
X: Undefined
page 21
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
4. SFRs
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1)
Table 4.3 SFR Information(3)
Address
008016
008116
008216
008316
008416
008516
008616
Register
Symbol
After reset
~
~
~
~
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
Flash memory control register 4
(2)
(2)
(2)
FMR4
FMR1
FMR0
010000002
Flash memory control register 1
Flash memory control register 0
000XXX0X
0116
2
~
~
~
~
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
Three phase protect control register
TPRC
0016
On-chip oscillator control register
Pin assignment control register
Peripheral clock select register
ROCR
PACR
PCLKR
X0000101
0016
00000011
2
2
~
~
~
~
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
NMI digital debounce register
NDDR
P17DDR
FF16
FF16
Port1
7
digital debounce register
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. This register is included in the flash memory version.
X: Undefined
page 22
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
4. SFRs
(1)
Table 4.4 SFR Information(4)
Address
Register
Symbol
After reset
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
NOTE:
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
TA11
TA21
TA41
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
00111111
00111111
XX16
XX16
XXXX0000
Three phase PWM control register 0
Three phase PWM control register 1
Three phase output buffer register 0
Three phase output buffer register 1
Dead time timer
INVC0
INVC1
IDB0
IDB1
DTT
2
2
Timer B2 Interrupt occurrence frequency set counter
Position-data-retain function control register
ICTB2
PDRF
2
Port function control register
PFCR
001111112
(2)
Interrupt request cause select register 2
Interrupt request cause select register
IFSR2A
IFSR
XXXXXXX0
0016
2
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
0016
000X0X0X
X0000000
X0000000
0016
XX16
XXXXXXXX
XXXXXXXX
00001000
00000010
2
2
2
U2BRG
U2TB
UART2 transmit buffer register
2
2
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
U2C0
U2C1
U2RB
2
2
XXXXXXXX
XXXXXXXX
2
2
1. Blank spaces are reserved. No access is allowed.
2. Write "1" to bit 0 after reset.
X : Undefined
page 23
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
4. SFRs
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1)
Table 4.5 SFR Information(5)
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Register
Symbol
After reset
Count start flag
TABSR
CPSRF
ONSF
TRGSR
UDF
0016
0XXXXXXX
0016
0016
0016
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-dowm flag
2
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
00XX0000
00XX0000
00XX0000
2
2
2
Timer B2 special mode register
X00000002
UART0 transmit/receive mode register
UART0 bit rate register
UART0 transmit buffer register
U0MR
U0BRG
U0TB
0016
XX16
XXXXXXXX
XXXXXXXX
2
2
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
U0C0
U0C1
U0RB
00001000
00000010
2
2
XXXXXXXX
XXXXXXXX
0016
XX16
XXXXXXXX
2
2
UART1 transmit/receive mode register
UART1 bit rate register
UART1 transmit buffer register
U1MR
U1BRG
U1TB
2
2
XXXXXXXX
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
U1C0
U1C1
U1RB
00001000
00000010
2
2
XXXXXXXX
XXXXXXXX
2
2
UART transmit/receive control register 2
UCON
X0000000
2
CRC snoop address register
CRC mode register
CRCSAR
CRCMR
DM0SL
DM1SL
CRCD
XX16
00XXXXXX
0XXXXXX0
2
2
DMA0 request cause select register
DMA1 request cause select register
CRC data register
0016
0016
XX16
XX16
XX16
CRC input register
CRCIN
NOTE:
1. Blank spaces are reserved. No access is allowed.
X : Undefined
page 24
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
4. SFRs
(1)
Table 4.6 SFR Information(6)
Address
03C016 A/D register 0
Register
Symbol
AD0
After Reset
XXXXXXXX
2
03C116
XXXXXXXX
2
03C216 A/D register 1
03C316
AD1
AD2
AD3
AD4
AD5
AD6
AD7
XXXXXXXX2
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
2
2
2
2
2
2
2
2
2
2
2
2
2
03C416 A/D register 2
03C516
03C616 A/D register 3
03C716
03C816 A/D register 4
03C916
03CA16 A/D register 5
03CB16
03CC16 A/D register 6
03CD16
03CE16 A/D register 7
03CF16
03D016
03D116
03D216 A/D trigger control register
03D316 A/D status register 0
03D416 A/D control register 2
ADTRGCON
ADSTAT0
ADCON2
0016
00000X00
0016
2
03D516
03D616 A/D control register 0
03D716 A/D control register 1
ADCON0
ADCON1
00000XXX
0016
2
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
Port P1 register
P1
XX16
0016
03E216
03E316
Port P1 direction register
PD1
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
P6
P7
PD6
PD7
P8
XX16
XX16
0016
0016
XX16
03ED16
03EE16
03EF16
03F016
Port P8 register
03F116
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
P9
XXXXXXXX
0016
2
03F216
PD8
PD9
P10
03F316
XXXX0000
XX16
2
03F416
03F516
03F616
Port P10 direction register
PD10
0016
03F716
03F816
03F916
03FA16
03FB16
03FC16
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
Port control register
PUR0
PUR1
PUR2
PCR
0016
0016
0016
0016
03FD16
03FE16
03FF16
NOTE:
1. Blank spaces are reserved. No access is allowed.
X: Undefined
page 25
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
5. Reset
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
5. Reset
There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla-
tion stop detection reset.
5.1 Hardware Reset
There are two types of hardware resets: a hardware reset 1 and a hardware reset 2.
5.1.1 Hardware Reset 1
____________
____________
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the
power supply voltage is within the recommended operating condition, the pins are initialized (see
____________
Table 5.1.1.1 Pin Status When RESET Pin Level is “L”). The internal on-chip oscillator is initialized
and used as CPU clock.
____________
When the input level at the RESET pin is released from “L” to “H”, the CPU and SFR are initialized,
and the program is executed starting from the address indicated by the reset vector. The internal RAM
____________
is not initialized. If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM
becomes indeterminate.
Figure 5.1.1.1 shows the example reset circuit. Figure 5.1.1.2 shows the reset sequence. Table
____________
5.1.1.1 shows the status of the other pins while the RESET pin is “L”. Figure 5.1.1.3 shows the CPU
register status after reset. Refer to “SFR Map” for SFR status after reset.
1. When the power supply is stable
____________
(1) Apply an “L” signal to the RESET pin.
(2) Wait td(ROC) or more.
____________
(3) Apply an “H” signal to the RESET pin.
2. Power on
____________
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condition.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Wait td(ROC) or more.
____________
(5) Apply an “H” signal to the RESET pin.
5.1.2 Hardware Reset 2
Note
M16C/26T does not use this function.
This reset is generated by the microcomputer’s internal voltage detection circuit. The voltage detec-
tion circuit monitors the voltage supplied to the VCC pin.
If the VC26 bit in the VCR2 register is set to “1” (reset level detection circuit enabled), the microcom-
puter is reset when the voltage at the VCC input pin drops below Vdet3.
Conversely, when the input voltage at the VCC pin rises to Vdet3r or more, the pins and the CPU and
SFR are initialized, and the program is executed starting from the address indicated by the reset
vector. It takes about td(S-R) before the program starts running after Vdet3r is detected. The initialized
pins and registers and the status thereof are the same as in hardware reset 1.
The microcomputer cannot exit stop mode by voltage down detection reset (hardware reset 2).
page 26
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
5. Reset
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Recommended
operating
voltage
V
CC
0V
V
CC
RESET
RESET
0V
Equal to or less
than 0.2VCC
Equal to or less
than 0.2VCC
More than td(ROC) + td(P-R)
Figure 5.1.1.1. Example Reset Circuit
5.2 Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,
CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset
vector.
The device will reset using on-chip oscillator as the CPU clock.
At software reset, some SFR’s are not initialized. Refer to “SFR”.
5.3 Watchdog Timer Reset
When the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcomputer
initializes its pins, CPU and SFR if the watchdog timer underflows.
The device will reset using on-chip oscillator as the system clock. Then the program is executed starting
from the address indicated by the reset vector.
At watchdog timer reset, some SFR’s are not initialized. Refer to “SFR”.
5.4 Oscillation Stop Detection Reset
When the CM20 bit in the CM2 register is set to “1”(oscillation stop, re-oscillation detection function
enabled) and the CM27 bit is set to “0” (reset at oscillation stop detection), the microcomputer initializes
its pins, CPU and SFR, coming to a halt if it detects main clock oscillation circuit stop. Refer to the section
“oscillation stop, re-oscillation detection function”.
At oscillation stop detection reset, some SFR’s are not initialized. Refer to the section “SFR”.
page 27
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
5. Reset
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
V
CC
ROC
td(P-R)
More than
td(ROC)
RESET
CPU clock
28 cycles
CPU clock
FFFFC16
Content of reset vector
Address
FFFFE16
Figure 5.1.1.2. Reset Sequence
____________
Table 5.1.1.1. Pin Status When RESET Pin Level is “L”
Status
Pin name
P1, P6 to P10
Input port (high impedance)
b15
b0
000016
Data register(R0)
Data register(R1)
Data register(R2)
000016
000016
000016
000016
000016
000016
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
b19
b0
b0
0000016
Interrupt table register(INTB)
Program counter(PC)
Content of addresses FFFFE16 to FFFFC16
b15
User stack pointer(USP)
000016
000016
000016
Interrupt stack pointer(ISP)
Static base register(SB)
b15
b0
b0
Flag register(FLG)
000016
b15
b8 b7
IPL
U
I
O B S Z D C
Figure 5.1.1.3. CPU Register Status After Reset
page 28
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
5. Reset
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
5.5 Voltage Detection Circuit
Note
VCC=5 V is assumed. Voltage Detection Circuit is not available in M16C/26T.
The voltage detection circuit has circuits to monitor the input voltage at the VCC pin, each checking the input
voltage with respect to Vdet3, and Vdet4, respectively. Use the VC26 to VC27 bits in the VCR2 register to
select whether or not to enable these circuits.
Use the reset level detection circuit for hardware reset 2.
The voltage down detection circuit can be set to detect whether the input voltage is equal to or greater than
Vdet4 or less than Vdet4 by monitoring the VC13 bit in the VCR1 register. Furthermore, a voltage down
detection interrupt can be generated.
VCR2 Register
RESET
b7 b6
Brown-out Detect Reset
(Hardware Reset 2
1 shot
>T
Release Wait Time)
td(S-R)
Reset level
detection circuit
Q
+
>Vdet3
E
CM10 Bit=1
(Stop Mode)
Internal Reset Signal
(“L” active)
+
VCC
Low Voltage
Detect Signal
>Vdet4
Noise Rejection
E
VCR1 Register
Low voltage
b3
detection circuit
VC13 Bit
Figure 5.5.1. Voltage Detection Circuit Block
page 29
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
5. Reset
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Voltage detection register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VCR1
Address
001916
After reset (2)
000010002
0 0 0 0
0 0 0
Bit name
F unction
RW
RW
Bit symbol
(b2-b0)
Reserved bit
Must set to “0”
Voltage down monitor flag
(1)
0:VCC < Vdet4
1:VCC ≥ Vdet4
VC13
RO
RW
Reserved bit
Must set to “0”
(b7-b4)
NOTES:
1. The VC13 bit is useful when the VC27 bit in the VCR2 register is set to "1" (voltage down detection circuit
enable). The VC13 bit is always "1" (VCC ≥ Vdet4) when the VC27 bit in the VCR2 register is set to "0"
(voltage down detection circuit disable).
2. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Voltage detection register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VCR2
Address
001A16
After reset (5)
0016
0 0 0 0 0 0
Bit name
RW
RW
Bit symbol
(b5-b0)
Function
Must set to “0”
Reserved bit
0: Disable reset level detection
circuit
1: Enable reset level detection
circuit
VC26
Reset level monitor bit
(2, 3, 6)
RW
RW
0: Disable voltage down
detection circuit
1: Enable voltage down
detection circuit
VC27
Voltage down monitor
bit (4, 6)
NOTES:
1. Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
2. When not in stop mode, to use hardware reset 2, set the VC26 bit to “1” (reset level detection circuit enable).
3. VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc pin
becomes lower than Vdet3.)
4. When the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to
“1” (voltage down detection interrupt enable), set the VC27 bit to “1” (voltage down detection circuit enable).
5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
6. The detection circuit does not start operation until td(E-A) elapses after the VC26 bit, or VC27 bit are set to
“1”.
Voltage down detection interrupt register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
D4INT
Address
001F16
After reset
0016
Bit symbol
D40
RW
RW
Bit name
Function
0 : Disable
1 : Enable
interrupt enable bit (5)
0: Disable (do not use the voltage
down detection
interrupt to get out of stop mode)
1: Enable (use the voltage down
detection interrupt to get
out of stop mode)
STOP mode deactivation
control bit
(4)
D41
RW
Voltage change detection flag
(2)
0: Not detected
1: Vdet4 passing detection
RW
(3)
D42
D43
DF0
DF1
RW
(3)
0: Not detected
1: Detected
WDT overflow detect flag
Sampling clock select bit
b5b4
RW
RW
00 : CPU clock divided by 8
01 : CPU clock divided by 16
10 : CPU clock divided by 32
11 : CPU clock divided by 64
Nothing is assigned. When write, set to “0”. When read, its
content is “0”.
(b7-b6)
NOTES:
1. Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
2. Useful when the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled). If the
VC27 bit is set to “0” (voltage down detection circuit disable), the D42 bit is set to “0” (Not detect).
3. This bit is set to “0” by writing a “0” in a program. (Writing a “1” has no effect.)
4. If the voltage down detection interrupt needs to be used to get out of stop mode again after once used for
that purpose, reset the D41 bit by writing a “0” and then a “1”.
5. The D40 bit is effective when the VC27 bit in the VCR2 register is set to “1”. To set the D40 bit to “1”, follow
the procedure described below.
(1) Set the VC27 bit to “1”.
(2) Wait for td(E-A) until the detection circuit is actuated.
(3) Wait for the sampling time (refer to “Table 5.5.1.2 Sampling Clock Periods”).
(4) Set the D40 bit to “1”.
Figure 5.5.2. VCR1 Register, VCR2 Register, and D4INT Register
page 30
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
5. Reset
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
5.0V
5.0V
Vdet4
Vdet3r
Vdet3
VCC
Vdet3s
VSS
RESET
Internal Reset Signal
VC13 bit in
VCR1 register
Indefinite
Indefinite
Set to “1” by program (reset level detect circuit enable)
VC26 bit in
VCR2 register (1)
Set to “1” by program
(voltage down detect circuit enable)
VC27 bit in
VCR2 register
Indefinite
NOTES :
1. VC26 bit is invalid (the microcomputer is not reset even if input voltage of VCC pin
becomes lower than Vdet3).
Figure 5.5.3. Typical Operation of Hardware Reset 2
page 31
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
5. Reset
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
5.5.1 Voltage Down Detection Interrupt
If the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled), the voltage
down detection interrupt request is generated when the voltage applied to the VCC pin crosses the
Vdet4 voltage level. The voltage down detection interrupt shares the same interrupt vector with the
watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to “1” (enabled) to use the voltage down detection interrupt to exit
stop mode.
The D42 bit in the D4INT register is set to “1” as soon as the voltage applied to the VCC pin reaches
Vdet4 due to the voltage rise and voltage drop. When the D42 bit changes “0” to “1”, the voltage down
detection interrupt request is generated. Set the D42 bit to “0” by program. However, when the D41
bit is set to “1” and the microcomputer is in stop mode, the voltage down detection interrupt request is
generated regardless of the D42 bit state if the voltage applied to the VCC pin is detected to be above
Vdet4. The microcomputer then exits stop mode.
Table 5.5.1.1 shows how the voltage down detection interrupt request is generated.
The DF1 to DF0 bits in the D4INT register determine the sampling period that detects the voltage
applied to the VCC pin reaches Vdet4. Table 5.5.1.2 shows the sampling periods.
Table 5.5.1.1 Voltage Down Detection Interrupt Request Generation Conditions
Operation Mode
VC27 Bit
D40 Bit
D41 Bit
D42 Bit
CM02 Bit
VC13 Bit
Normal
Operation
Mode(1)
0 to 1(3)
1 to 0(3)
0 to 1(3)
1 to 0(3)
0 to 1
0 to 1
0
Wait Mode(2)
1
1
1
0
0 to 1
0 to 1
Stop Mode(2)
NOTES:
1
– : “0”or “1”
1. The status except the wait mode and stop mode is handled as the normal mode.(Refer to 7. Clock generating circuit)
2. Refer to 5.5.2 Limitations on stop mode, 5.5.3 Limitations on wait mode.
3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.
See the Figure 5.5.1.2 Voltage Down Detection Interrupt Generation Circuit Operation Example for details.
Table 5.5.1.2 Sampling Periods
Sampling Period (µs)
CPU
Clock
(MHz)
DF1 to DF0=00
DF1 to DF0=01
DF1 to DF0=10
DF1 to DF0=11
(CPU clock divided by 8) (CPU clock divided by 16) (CPU clock divided by 32) (CPU clock divided by 64)
16
3.0
6.0
12.0
24.0
page 32
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
5. Reset
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Voltage down detection interrupt generation circuit
DF1, DF0
00b
01b
10b
11b
The D42 bit is set to “0” (not detected)
by program. the VC27 bit is set to “0”
(voltage down detect circuit disabled),
the D42 bit is set to “0”.
Voltage Down Detection Circuit
VC27
D4INT clock(the
clock with which it
operates also in
wait mode)
1/8
1/2
1/2
1/2
Watchdog
timer interrupt
signal
D42
VC13
VCC
+
-
Noise
Rejection
Noise Rejection
Circuit
Digital
Filter
Voltage down
detection signal
VREF
(Rejection Range:200 ns)
Voltage down
detection
The Voltage down detection
signal becomes “H” when the
VC27 bit is set to “0” (disabled)
Non-maskable
interrupt signal
D41
interrupt signal
CM10
Oscillation stop,
re-oscillation
detection
CM02
interrupt signal
WAIT instruction(wait mode)
Watchdog Timer Block
D43
D40
Watchdog timer
underflow signal
This bit is set to “0”(not detected) by program.
Figure 5.5.1.1 Power Supply Down Detection Interrupt Generation Block
VCC
VC13 bit in VCR1 register
sampling
sampling
sampling
sampling
No voltage down detection interrupt signals are
generated when the D42 bit is “1”.
Output of the digital filter (2)
D42 bit in D4INT register
Set to “0” by program (not detected)
Voltage down detection
interrupt signal
NOTES :
1. D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled).
2. Output of the digital filter is shown in Figure 5.5.1.1.
Figure 5.5.1.2 Power Supply Down Detection Interrupt Generation Circuit Operation Example
page 33
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
5. Reset
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
5.5.2 Limitations on Exiting Stop Mode
The voltage down detection interrupt is immediately generated and the microcomputer exits stop
mode if the CM10 bit in the CM1 register is set to “1” under the conditions below.
• the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled),
• the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled),
• the D41 bit in the D4INT register is set to “1” (voltage down detection interrupt is used to exit stop
mode), and
• the voltage applied to the VCC pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”)
If the microcomputer is set to enter stop mode when the voltage applied to the VCC pin drops below
Vdet4 and to exit stop mode when the voltage applied rises to Vdet4 or above, set the CM10 bit to “1”
when VC13 bit is “0” (VCC < Vdet4).
5.5.3 Limitations on Exiting Wait Mode
The voltage down detection interrupt is immediately generated and the microcomputer exits wait
mode If WAIT instruction is executed under the conditions below.
• the CM02 bit in the CM0 register is set to “1” (stop peripheral function clock),
• the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled),
• the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled),
• the D41 bit in the D4INT register is set to “1” (voltage down detection interrupt is used to exit wait
mode), and
• the voltage applied to the VCC pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”)
If the microcomputer is set to enter wait mode when the voltage applied to the VCC pin drops below
Vdet4 and to exit wait mode when the voltage applied rises to Vdet4 or above, perform WAIT instruc-
tion when VC13 bit is “0” (VCC < Vdet4).
page 34
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
6. Processor Mode
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
6. Processor Mode
The microcomputer supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers.
Processor Mode Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM0
Address
000416
After Reset
0016
0 0 0 0
0 0 0
Bit Symbol
(b2-b0)
Bit Name
Function
RW
RW
Reserved bit
Set to "0"
The microcomputer is reset when
this bit is set to "1". When read,
its content is "0".
PM03
Software reset bit
Reserved bit
RW
RW
Set to "0"
(b7-b4)
NOTES:
1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
Processor Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
000516
After Reset
00001000
0
0
0 0
1
2
Bit Symbol
PM10
Bit Name
Function
RW
RW
Flash data block access
bit (2)
0: Disabled
1: Enabled (3)
Set to "0"
Reserved bit
RW
RW
RW
RW
RW
(b1)
Watchdog timer function
select bit
0 : Watchdog timer interrupt
1 : Watchdog timer reset (4)
PM12
Reserved bit
Reserved bit
Wait bit (5)
Set to "1"
Set to "0"
(b3)
(b6-b4)
PM17
0 : No wait state
1 : Wait state (1 wait)
NOTES:
1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
2. To access the two 2K-byte data spaces in data block A and data block B, set the PM10 bit to "1". The PM10
bit is not available in mask version.
3. When the FMR01 bit in the FMR0 register is set to "1" (enables CPU rewrite mode), the PM10 bit is
automatically set to "1".
4. Set the PM12 bit to "1" by program. (Writing "0" by program has no effect)
5. When the PM17 bit is set to "1" (wait state), one wait is inserted when accessing the internal RAM or the
internal ROM.
Figure 6.1 PM0 Register, PM1 Register
page 35
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
6. Processor Mode
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Processeor Mode Register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
001E16
After Reset
XXX000002
0
PM2
Bit Symbol
PM20
Bit Name
Function
RW
RW
Specifying wait when
accessing SFR during PLL
operation(2)
0: 2 wait
1: 1 wait
0: Clock is protected by PRCR
register
1: Clock modification disabled
System clock protective bit(3,4)
PM21
PM22
RW
0: CPU clock is used for the
watchdog timer count source
1: On-chip oscillator clock is used RW
for the watchdog timer count
source
WDT count source
protective bit (3,5)
Reserved bit
Set to “0”
RW
RW
(b3)
0: P8
5 function (NMI disable)
P85/NMI configuration bit(6,7)
PM24
1: NMI function
Nothing is assigned. When write, set to“0”.
When read,its content is indeterminate
(b7-b5)
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
2. The PM20 bit become effective when PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20 bit
when the PLC07 bit is set to "0" (PLL off). Set the PM20 bit to "0" (2 waits) when PLL clock > 16 MHz.
3. Once this bit is set to “1”, it cannot be set to “0” by program.
4. Writing to the following bits has no effect when the PM21 bit is set to “1”:
CM02 bit in the CM0 register
CM05 bit in the CM0 register (main clock is not halted)
CM07 bit in the CM0 register (CPU clock source does not change)
CM10 bit in the CM1 register (stop mode is not entered)
CM11 bit in the CM1 register (CPU clock source does not change)
CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in the PLC0 register (PLL frequency synthesizer setting do not change)
When the PM21 bit is set to "1", do not execute the WAIT instruction.
5. Setting the PM22 bit to “1” results in the following conditions:
- The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or
PLL clock) (system clock of count source selected by the CM21 bit is valid)
- The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count
source.
- The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered)
- The watchdog timer does not stop in wait mode.
6. For NMI function, the PM24 bit must be set to “1”(NMI function). Once this bit is set to “1”, it cannot be cleared to
“0” by program.
7. SD input is valid regardless of the PM24 setting.
Figure 6.2 PM2 Register
page 36
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
6. Processor Mode
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to
interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and periph-
eral bus. Figure 6.3 shows the block diagram of the internal bus.
RAM
ROM
CPU address bus
CPU data bus
Memory address bus
CPU
BIU
Memory data bus
DMAC
Timer
WDT
CPU clock
Serial I/O
ADC
Clock
generation
circuit
Peripheral function
.
.
.
.
I/O
Figure 6.3 Bus Block Diagram
The number of bus cycle varies by the internal bus. Table 6.1 lists the accessible area and bus cycle.
Table 6.1 Accessible Area and Bus Cycle
Accessible Area
PM20 bit = 0 (2 waits)
PM20 bit = 1 (1 wait)
PM17 bit = 0 (no wait)
PM17 bit = 1 (1 wait)
Bus Cycle
3 CPU clock cycles
2 CPU clock cycles
1 CPU clock cycle
2 CPU clock cycles
SFR
ROM/RAM
page 37
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7. Clock Generation Circuit
The clock generation circuit contains four oscillator circuits as follows:
(1) Main clock oscillation circuit
(2) Sub clock oscillation circuit
(3) On-chip oscillator (available at reset, oscillation stop detect function)
(4) PLL frequency synthesizer
Table 7.1 lists the clock generation circuit specifications. Figure 7.1 shows the clock generation circuit.
Figures 7.2 to 7.6 show the clock-related registers.
Table 7.1. Clock Generation Circuit Specifications
Main clock
oscillation circuit
PLL frequency
synthesizer
Sub clock
oscillation circuit
Item
On-chip oscillator
• CPU clock source • CPU clock source • CPU clock source
• CPU clock source
Use of clock
• Peripheral function • Timer A, B's clock • Peripheral function clock source • Peripheral function clock
clock source
source
• CPU and peripheral function
clock sources when the main
clock stops oscillating
source
M16C/26A
M16C/26T
Clock frequency 0 to 20 MHz
32.768 kHz
• Selectable source frequency:
10 to 20 MHz
(
)
f1(ROC), f2(ROC), f3(ROC)
• Selectable divider:
by 2, by 4, by 8
10 to 24 MHz (M16C/26B)
• Ceramic oscillator • Crystal oscillator
• Crystal oscillator
Usable oscillator
X
IN, XOUT
XCIN, XCOUT
Pins to connect
oscillator
Available
Stopped
Available
Available
Stopped
Available
Oscillation stop,
restart function
M16C/26A
M16C/26B
Oscillating
Oscillator status
after reset
Oscillating
(
)
(CPU clock source)
Stopped(M16C/26T)
Other
Externally derived clock can be input
page 38
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
PCLK5=0,CM01-CM00=00
2
I/O ports
PCLK5=0,CM01-CM00=01
2
Sub-clock
generating circuit
CLKOUT
PCLK5=1,
PCLK5=0,
CM01-CM00=00
2
X
CIN
X
COUT
PCLK5=0,
CM01-CM00=11
CM01-CM00=10
2
2
f
C32
1/32
CM04
f
f
1
PCLK0=1
Sub-clock
2
PCLK0=0
f
C
f
8
On-chip
oscillator
clock
CM21
f
32
f
AD
f
1SIO
PCLK1=1
PCLK1=0
f2SIO
f
8SIO
CM10=1(stop mode)
S
R
Q
PLL
frequency
synthesizer
X
IN
XOUT
f
32SIO
e
b
c
D4INT clock
CPU clock
CM07=0
a
d
PLL
CM21=1
CM21=0
clock
Main
clock
1
0
fC
Main clock
generating circuit
BCLK
CM11
CM07=1
CM05
CM02
S
R
Q
WAIT instruction
c
e
b
1/2
1/2
1/2
1/2
1/2
a
1/32
RESET
1/2
1/4
1/8
1/16
CM06=0
Software reset
NMI
CM17-CM16=11
2
CM06=1
2
CM06=0
CM17-CM16=10
Interrupt request level judgment output
d
CM00, CM01, CM02, CM04, CM05, CM06, CM07: CM0 register bits
CM10, CM11, CM16, CM17: CM1 register bits
PCLK0, PCLK1, PCLK5: PCLKR register bits
CM21, CM27 : CM2 register bits
CM06=0
CM17-CM16=01
2
CM06=0
CM17-CM16=00
2
Details of divider
Oscillation stop, re-oscillation detection circuit
On-chip Oscillator
ROCR1-ROCR0=00
2
f
1(ROC)
Reset
generating
circuit
CM27=0
CM27=1
Pulse generation
circuit for clock
edge detection
and charge,
Oscillation stop
detection reset
Charge,
discharge
circuit
1/2
1/2
1/2
Main
clock
f
2(ROC)
ROCR1-ROCR0=01
2
Oscillation stop,
re-oscillation
Oscillation stop,
re-oscillation
discharge control
ROCR3-ROCR2=11
2
detection signal
detection interrupt
generating circuit
f
3(ROC)
ROCR1-ROCR0=11
2
ROCR3-ROCR2=10
2
On-chip
oscillator
clock
ROCR3-ROCR2=01
2
CM21 switch signal
PLL frequency synthesizer
Programmable
counter
1/2
PLL clock
Voltage
control
oscillator
(VCO)
Charge
pump
Phase
comparator
Main clock
Internal low-
pass filter
Figure 7.1. Clock Generation Circuit
page 39
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
System clock control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
After reset
01001000
01101000
2
2
(M16C/26A, M16C/26B)
(M16C/26T)
Bit symbol
CM00
Function
RW
RW
Bit name
Clock output function
select bit
Refer to Table 7.5.3.1 Function of the CLKout pin
CM01
CM02
RW
RW
RW
RW
RW
WAIT peripheral function
clock stop bit (10)
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (8)
0 : LOW
1 : HIGH
X
CIN-XCOUT drive capacity
select bit (2)
CM03
CM04
Port X
(2)
C select bit
0 : I/O port P86, P87
1 : XCIN-XCOUT generation function (9)
0 : On
1 : Off (4, 5)
Main clock stop bit
(3, 10, 12, 13)
CM05
CM06
0 : CM16 and CM17 valid
1 : Division by 8 mode
Main clock division select
bit 0 (7, 13, 14)
RW
RW
0 : Main clock, PLL clock, or on-chip oscillator clock
1 : Sub-clock
System clock select bit
(6, 10, 11, 12)
CM07
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. The CM03 bit is set to "1" (high) when the CM04 bit is set to "0" (I/O port) or the microcomputer goes to a stop mode.
3. This bit is provided to stop the main clock when the low power dissipation mode or on-chip oscillator low power dissipation
mode is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the
following setting is required:
(1) Set the CM07 bit to "1" (Sub-clock select) or the CM21 bit in the CM2 register to "1" (on-chip oscillator select) with the sub-
clock stably oscillating.
(2) Set the CM20 bit in CM2 register to "0" (Oscillation stop, re-oscillation detection function disabled).
(3) Set the CM05 bit to "1" (Stop).
4. During external clock input, only the clock oscillation buffer is turned off and clock input is accepted.
5. When CM05 bit is set to "1", the XOUT pin goes "H". Furthermore, because the internal feedback resistor remains connected, the
X
IN pin is pulled "H" to the same level as XOUT via the feedback resistor.
6. After setting the CM04 bit to "1" (XCIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching the
CM07 bit from "0" to "1" (sub-clock).
7. When entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip oscillator low power mode, the
CM06 bit is set to "1" (divide-by-8 mode).
8. The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to "1" (peripheral clock turned
off when in wait mode).
9. To use a sub-clock, set this bit to "1". Also make sure ports P86 and P87 are directed for input, with no pull-ups.
10. When the PM21 bit of PM2 register is set to "1" (clock modification disable), writing to the CM02, CM05, and CM07 bits has no
effect.
11. If the PM21 bit needs to be set to "1", set the CM07 bit to "0"(main clock) before setting it.
12. To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to "0" (oscillate).
(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(3) Set the CM11, CM21 and CM07 bits all to "0".
13. When the CM21 bit is set to "0" (on-chip oscillaor turned off) and the CM05 bit is set to "1" (main clock turned off), the CM06 bit is
fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
14. To return from on-chip oscillator mode to high-speed or middle-speed mode set the CM06 and CM15 bits both to "1".
Figure 7.2. CM0 Register
page 40
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
System clock control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
After reset
0
0
0
00100000
2
Bit symbol
CM10
Bit name
Function
RW
RW
All clock stop control bit
(4, 6)
0 : Clock on
1 : All clocks off (stop mode)
System clock select bit 1
(6, 7)
0 : Main clock
1 : PLL clock (5)
CM11
RW
Reserved bit
Must set to “0”
RW
RW
(b4-b2)
CM15
X
IN-XOUT drive capacity
0 : LOW
1 : HIGH
select bit (2)
b7 b6
Main clock division
select bits (3)
0 0 : No division mode
CM16
CM17
RW
RW
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).
2. When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
speed mode, the CM15 bit is set to “1” (drive capability high).
3. Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
4. If the CM10 bit is “1” (stop mode), XOUT goes “H” and the internal feedback resistor is disconnected. The XCIN and XCOUT pins
are placed in the high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit in the CM2 register is set
to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
5. After setting the PLC07 bit in the PLC0 register to “1” (PLL operation), wait until Tsu (PLL) elapses before setting the CM11 bit
to “1” (PLL clock).
6. When the PM21 bit in the PM2 register is set to “1” (clock modification disable), writing to the CM10, CM011 bits has no effect.
When the PM22 bit in the PM2 register is set to “1” (watchdog timer count source is on-chip oscillator clock), writing to the CM10
bit has no effect.
7. Effective when CM07 bit is “0” and CM21 bit is “0” .
Figure 7.3. CM1 Register
(1)
On-chip Oscillator Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ROCR
Address
025C16
After Reset
X0000101
0 0
0
2
Bit Symbol
Bit Name
Function
RW
RW
b1 b0
Frequency select bits
0 0: f
0 1: f
1
2
(ROC)
(ROC)
ROCR0
ROCR1
1 0: Do not set to this value
RW
1 1: f3 (ROC)
b3 b2
Divider select bits
0 0: Do not set to this value
0 1: divide by 2
1 0: divide by 4
ROCR2
ROCR3
(b6-b4)
(b7)
RW
RW
RW
1 1: divide by 8
Set to 0
Reserved bit
Nothing is assigned. When write, set to 0. When read, its
content is undefined
NOTE:
1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable).
Figure 7.4. ROCR Register
page 41
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Oscillation stop detection register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
000C16
After reset
0X0000102(11)
0
0
CM2
Bit symbol
CM20
Bit name
Function
RW
RW
0: Oscillation stop, re-oscillation
detection function disabled
1: Oscillation stop, re-oscillation
detection function enabled
Oscillation stop, re-
oscillation detection bit
(7, 9, 10, 11)
System clock select bit 2
(2, 3, 6, 8, 11, 12 )
0: Main clock or PLL clock
1: On-chip oscillator clock
(On-chip oscillator oscillating)
CM21
CM22
RW
RW
0: Main clock stop or re-oscillation
not detected
1: Main clock stop or re-oscillation
detected
Oscillation stop, re-
oscillation detection flag
(4)
0: Main clock oscillating
1: Main clock not oscillating
X
(5)
IN monitor flag
RO
CM23
Reserved bit
Must set to “0”
RW
(b5-b4)
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
(b6)
Operation select bit
(when an oscillation stop,
re-oscillation is detected)
(11)
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation
detection interrupt
CM27
RW
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).
2. When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to
“1”(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit
isautomatically set to “1” (on-chip oscillator clock) if the main clock stop is detected.
3. If the CM20 bit is set to “1” and the CM23 bit is set to “1” (main clock not oscillating), do not set the CM21 bit to “0”.
4. This flag is set to “1” when the main clock is detected to have stopped or when the main clock is detected to
haverestarted oscillating. When this flag changes state from “0” to “1”, an oscillation stop, reoscillation detection interrupt
isgenerated. Use this flag in an interrupt routine to discriminate the causes of interrupts between theoscillation
stop,reoscillation detection interrupts and the watchdog timer interrupt. The flag is cleared to “0” by writing a “0” in
aprogram. (Writing a “1” has no effect. Nor is it cleared to “0” by an oscillation stop or an oscillation restart
detectiointerrupt request acknowledged.) If when the CM22 bit is set to "1" an oscillation stop or an oscillation restart is
detected, no oscillation stop, reoscillation detection interrupts are generated.
5. Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main
clockstatus.
6. Effective when the CM07 bit in the CM0 register is set to “0”.
7. When the PM21 bit in the PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no effect.
8. When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to “1”
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is set to “1” (the CPU clock source is PLL clock), the
CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is set to “0” under these conditions,
oscillation stop, re-oscillation detection interrupt occur at main clock stop detection; it is, therefore, necessary to set the
CM21 bit to “1” (on-chip oscillator clock) inside the interrupt routine.
9. Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit back to "1”
(enable).
10. Set the CM20 bit to “0” (disable) before setting the CM05 bit in the CM0 register.
11. The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
12. When the CM21 bit is set to "0" (on-chip oscillator turned off) and the CM05 bit is set to "1" (main clock turned off), the
CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).
Figure 7.5. CM2 Register
page 42
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Peripheral Clock Select Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PCLKR
Address
025E16
After Reset
00000011
2
0
0
0 0 0
Bit Symbol
PCLK0
Bit Name
Function
RW
RW
Timers A, B clock select bit
(Clock source for the timers A,
B, the timer S, the dead timer,
SI/O3, SI/O4 and multi-master
I2C bus)
0: f
1: f
2
1
SI/O clock select bit
(Clock source for UART0 to
UART2)
0: f
1: f
2
1
SIO
SIO
PCLK1
RW
Reserved bit
Set to 0
RW
RW
RW
(b4-b2)
PCLK5
Clock output function
expansion select bit
Refer to Table 7.5.3.1
Reserved bit
Set to 0
(b7-b6)
NOTE:
1. Write to this register after setting the PRC0 bit in PRCR register to 1 (write enable).
(1)
Processeor Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM2
Address
001E16
After Reset
0
XXX00000
2
Bit Symbol
PM20
Bit Name
Function
RW
RW
Specifying wait when
0: 2 waits
1: 1 wait
(2)
accessing SFR
0: Clock is protected by PRCR
register
1: Clock modification disabled
System clock protective
PM21
PM22
RW
RW
(3,4)
bit
0: CPU clock is used for the
watchdog timer count source
1: On-chip oscillator clock is used
for the watchdog timer count
source
WDT count source
protective bit(3,5)
Reserved bit
Set to 0
RW
RW
(b3)
0: P85 function (NMI disabled)
P85/NMI configuration bit(6,7)
PM24
1: NMI function
Nothing is assigned. When write, set to 0.
When read, thecontent is undefined
(b7-b5)
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable).
2. The PM20 bit becomes effective when PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20
bit when the PLC07 bit is set to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.
3. Once this bit is set to 1, it cannot be cleared to 0 by program.
4. Writting to the following bits has no effect when the PM21 bit is set to 1:
CM02 bit in the CM0 register
CM05 bit in the CM0 register (main clock is not halted)
CM07 bit in the CM0 register (CPU clock source does not change)
CM10 bit in the CM1 register (stop mode is not entered)
CM11 bit in the CM1 register (CPU clock source does not change)
CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in the PLC0 register (PLL frequency synthesizer setting do not change)
Do not execute WAIT instruction when the PM21 bit is set to 1.
5. Setting the PM22 bit to 1 results in the following conditions:
•
The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or
PLL clock) (system clock of count source selected by the CM21 bit is valid)
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer
count source.
• The CM10 bit in the CM1 register cannnot be written. (Writing 1 has no effect, stop mode is not entered.)
• The watchdog timer does not stop in wait mode.
6. For NMI function, the PM24 bit must be set to 1(NMI function). Once this bit is set to 1, it cannot be set to 0 by
program.
7. SD input is valid regardless of the PM24 setting.
Figure 7.6. PCLKR Register and PM2 Register
page 43
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
PLL control register 0 (1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PLC0
Address
001C16
After reset
0001 X010
2
0
0 1
Bit
Bit name
Function
RW
RW
symbol
b2 b1b0
PLL multiplying factor
select bit (3)
PLC00
0 0 0: Do not set
0 0 1: Multiply by 2
0 1 0: Multiply by 4
0 1 1:
PLC01
PLC02
RW
RW
1 0 0:
1 0 1:
1 1 0:
1 1 1:
Do not set
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b3)
(b4)
RW
RW
Reserved bit
Reserved bit
Must set to "1"
Must set to "0"
(b6-b5)
0: PLL Off
1: PLL On
Operation enable bit
(4)
RW
PLC07
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. When the PM21 bit in the PM2 register is "1" (clock modification disable), writing to this register has
no effect.
3. These three bits can only be modified when the PLC07 bit is set to "0" (PLL turned off). The value once
written to this bit cannot be modified.
4. Before setting this bit to "1" , set the CM07 bit to "0" (main clock), set the CM17 and CM16 bits to
"002" (main clock undivided mode), and set the CM06 bit to "0" (CM16 and CM17 bits enable).
Figure 7.7. PLC0 Register
page 44
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
The following describes the clocks generated by the clock generation circuit.
7.1 Main Clock
The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for
the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a
resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor,
which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power
consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally
generated clock to the XIN pin. Figure 7.1.1 shows the examples of main clock connection circuit.
The main clock after reset oscillates in the M16C/26A and M16C/26B, but stop in the M16C/26T.
The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to “1” (main
clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or on-chip
oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains
on, XIN is pulled “H” to XOUT via the feedback resistor.
During stop mode, all clocks including the main clock are turned off. Refer to 7.6 power control.
If the main clock is not used, it is recommended to connect the XIN pin to VCC to reduce power consump-
tion during reset.
MCU
MCU
(Built-in Feedback Resistor)
(Built-in Feedback Resistor)
CIN
XIN
External Clock
X
IN
V
V
CC
SS
Oscillator
Rd(1)
X
OUT
C
OUT
XOUT Open
VSS
NOTE:
1. Insert a damping resistor if required. Resistance value varies depending on the oscillator setting.
Use resistance value recommended by the oscillator manufacturer. If the oscillator manufacturer
recommends that a feedback resistor be added to the chip externally, insert a feedback resistor
between XIN and XOUT
.
2. The external clock should not be stopped when it is connected to the XIN pin and the main clock is
selected as the CPU clock.
Figure 7.1.1. Examples of Main Clock Connection Circuit
page 45
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7.2 Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the
CPU clock, as well as the timer A and timer B count sources.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT
pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator
circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub clock
oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure
7.2.1 shows the examples of sub clock connection circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillator
circuit.
To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to “1 ” (sub clock) after the sub
clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to 7.6 Power Control.
MCU
MCU
(Built-in Feedback Resistor)
(Built-in Feedback Resistor)
C
CIN
XCIN
External Clock
XCIN
V
V
CC
SS
Oscillator
XCOUT
RC
d(1)
CCOUT
XCOUT Open
VSS
NOTE:
1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting.
Use values recommended by each oscillator manufacturer.
Place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends
placing the resistor externally.
Figure 7.2.1. Examples of Sub Clock Connection Circuit
page 46
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7.3 On-chip Oscillator Clock
This clock is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and
peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for
the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to
10.1 Count source protective mode).
The on-chip oscillator clock after reset oscillates. The on-chip oscillator clock f2(ROC) divided by 16 is used
for the CPU clock. It can also be turned off by setting the CM21 bit in the CM2 register to “0” (main clock or
PLL clock). If the main clock stops oscillating when the CM20 bit in the CM2 register is “1” (oscillation stop,
re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop, re-oscillation detection
interrupt), the on-chip oscillator automatically starts operating, supplying the necessary clock for the micro-
computer.
7.4 PLL Clock
The PLL clock is generated from the main clock by a PLL frequency synthesizer. This clock is used as the
clock source for the CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL
frequency synthesizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is
used as the clock source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the
CM11 bit in the CM1 register to “1”.
Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0”
(PLL stops). Figure 7.4.1 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits in the PLC0 register)
(However, 10 MHz ≤ PLL clock frequency ≤ 20 MHz in M16C/26A and M16C/26T, 10 MHz ≤ PLL clock
frequency ≤ 24 MHz in M16C/26B)
The PLC02 to PLC00 bits can be set only once after reset. Table 7.4.1 shows the example for setting PLL
clock frequencies.
Table 7.4.1. Example for Setting PLL Clock Frequencies
X
IN
PLC02
PLC01
PLC00
Multiplying factor
PLL clock
(MHz)
(1)
(MHz)
10
5
0
0
0
1
1
0
2
4
20
NOTE:
1. 10 MHz ≤ PLL clock frequency ≤ 20 MHz in M16C/26A and M16C/26T, 10 MHz ≤ PLL clock
frequency ≤ 24 MHz in M16C/26B)
page 47
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
START
Set the CM07 bit to “0” (main clock), the CM17 to CM16
bits to “00 ”(main clock undivided), and the CM06 bit to “0”
2
(1)
(CM16 and CM17 bits enabled).
Set the PLC02 to PLC00 bits (multiplying factor).
(To select a 16 MHz < PLL clock)
Set the PM20 bit to “0” (2-wait states).
Set the PLC07 bit to “1” (PLL operation).
Wait until the PLL clock becomes stable (tsu(PLL)).
Set the CM11 bit to “1” (PLL clock for the CPU clock source).
END
NOTE:
1. PLL operation mode can be entered from high speed mode.
Figure 7.4.1. Procedure to Use PLL Clock as CPU Clock Source
page 48
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7.5 CPU Clock and Peripheral Function Clock
The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the periph-
eral functions.
7.5.1 CPU Clock
This is the operating clock for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock
or the PLL clock.
If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in
CM0 register and the CM17 to CM16 bits in CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0”
and the CM17 and CM16 bits to “002” (undivided).
After reset, the on-chip oscillator clock divided by 16 provides the CPU clock.
Note that when entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip
oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to “1” (main clock
turned off) in low-speed mode, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode).
7.5.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)
These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or on-chip oscillator clock
divided by i. The clock fi is used for Timer A and Timer B while fiSIO is used for UART0 to UART2.
Additionally, the f1 and f2 clocks are also used for dead time timer.
The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the A/
D converter.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO and fAD clocks are turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can only be used
when the sub clock is on.
7.5.3 ClockOutput Function
The f1, f8, f32 or fC clock can be output from the CLKOUT pin. Use the PCLK5 bit in the PCLKR register and
CM01 to CM00 bits in the CM0 register to select. Table 7.5.3.1 shows the function of the CLKOUT pin.
Table 7.5.3.1 The function of the CLKOUT pin
PCLK5
CM01
CM00
The function of the CLKOUT pin
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I/O port P90
fC
f8
f32
f1
Do not set
Do not set
Do not set
page 49
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7.6 Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes
are referred to as normal operation mode here.
7.6.1 Normal Operation Mode
Normal operation mode is further classified into seven modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU
clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are
turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a
sufficient wait time in a program until it becomes oscillating stably.
Note that operation modes cannot be changed directly from low power dissipation mode to on-chip oscil-
lator mode or on-chip oscillator low power dissipation mode. Nor can operation modes be changed
directly from on-chip oscillator mode or on-chip oscillator low power dissipation mode to low power dissi-
pation mode.
When the CPU clock source is changed from the on-chip oscillator to the main clock, change the opera-
tion mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the CM06 bit
in the CM0 register was set to “1”) in the on-chip oscillator mode.
7.6.1.1 High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
7.6.1.2 PLL Operation Mode
The main clock multiplied by 2 or 4 provides the PLL clock, and this PLL clock serves as the CPU
clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. PLL operation
mode can be entered from high speed mode. If PLL operation mode is to be changed to wait or stop
mode, first go to high speed mode before changing.
7.6.1.3 Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used
as the count source for timers A and B.
7.6.1.4 Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit is set to “0” (on-chip oscillator turned off), and the on-chip oscillator
clock is used when the CM21 bit is set to “1” (on-chip oscillator oscillating).
The fC32 clock can be used as the count source for timers A and B.
7.6.1.5 Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides
the CPU clock. The fC32 clock can be used as the count source for timers A and B. Peripheral function
clock can use only fC32.
Simultaneously when this mode is selected, the CM06 bit in the CM0 register becomes “1” (divided by
8 mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divided by 8) mode is to be selected when the main clock is operated next.
page 50
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7.6.1.6 On-chip Oscillator Mode
The selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock.
The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock
is on, fC32 can be used as the count source for timers A and B. The on-chip oscillator frequency can be
selected ROCR3 to ROCR0 bits in ROCR register. When the operation mode is returned to the high
and medium speed modes, set the CM06 bit to “1” (divided by 8 mode).
7.6.1.7 On-chip Oscillator Low Power Dissipation Mode
The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be
selected as in the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the
peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for timers A and
B.
Table 7.6.1.1. Setting Clock Related Bit and Modes
CM2 register
CM1 register
CM0 register
Modes
CM21
CM11
CM17, CM16
CM07
CM06
CM05
CM04
PLL operation mode
High-speed mode
0
0
0
0
0
0
1
0
0
0
0
0
002
002
012
102
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Medium-
speed
mode
divided by 2
0
divided by 4
divided by 8
divided by 16
0
0
112
0
Low-speed mode
0
1
1
Low power dissipation mode
divided by 1
1(1)
0
1(1)
0
1
1
1
1
1
1
002
012
102
On-chip
oscillator
mode
(3)
divided by 2
0
0
divided by 4
0
0
divided by 8
1
0
divided by 16
112
(2)
0
0
On-chip oscillator low power
dissipation mode
1
(2)
NOTES:
1. When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low power
dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously.
2. The divide-by-n value can be selected the same way as in on-chip oscillator mode.
3. On-chip oscillator frequency can be any of those described in the section 7.6.1.6 On-chip Oscillator Mode.
7.6.2 Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. However, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watch-
dog timer count source), the watchdog timer remains active. Because the main clock, sub clock, on-chip
oscillator clock and PLL clock all are on, the peripheral functions using these clocks keep operating.
7.6.2.1 Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,
f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power consumption reduced
that much. However, fC32 remains on.
7.6.2.2 Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
When the CM11 bit is set to “1” (CPU clock source is the PLL clock), be sure to clear the CM11 bit to
“0” (CPU clock source is the main clock) before going to wait mode. The power consumption of the
chip can be reduced by clearing the PLC07 bit to “0” (PLL stops).
page 51
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7.6.2.3 Pin Status During Wait Mode
Table 7.6.2.3.1 lists pin status during wait mode.
Table 7.6.2.3.1 Pin Status in Wait Mode
Pin
Status
I/O ports
CLKOUT
Retains status before wait mode
Does not stop
When fC selected
Does not stop when the CM02 bit is set to “0”.
When f1, f8, f32 selected
Retains status before wait mode when the CM02 bit is set to “1”
.
7.6.2.4 Exiting Wait Mode
______
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral func-
tion interrupt.
______
If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before execut-
ing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If the CM02 bit is set to “0” (peripheral
function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit
wait mode. If the CM02 bit is set to “1” (peripheral function clocks turned off during wait mode), the
peripheral functions using the peripheral function clocks stop operating, so that only the peripheral
functions clocked by external signals can be used to exit wait mode.
Table 7.6.2.4.1 lists the interrupts to exit wait mode.
Table 7.6.2.4.1. Interrupts to Exit Wait Mode
Interrupt
CM02=0
CM02=1
NMI interrupt
Serial I/O interrupt
Can be used
Can be used
Can be used when operating
with internal or external clock
Can be used when operating
with external clock
key input interrupt
Can be used
Can be used
(Do not use)
A/D conversion
interrupt
Can be used in one-shot mode
or single sweep mode
Timer A interrupt
Timer B interrupt
Can be used in all modes
Can be used in event counter
mode or when the count
source is fC32
INT interrupt
Can be used
Can be used
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.
1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the periph
eral function interrupt to be used to exit wait mode.
Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0
bits to “0002” (interrupt disable).
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit wait mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt routine is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU
clock that was on when the WAIT instruction was executed.
page 52
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7.6.3 Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the internal
RAM is retained. When applying 2.7 or less voltage to Vcc pin, make sure Vcc≥VRAM.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
______
• NMI interrupt
• Key interrupt
______
• INT interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is selected)
• Voltage down detection interrupt
(refer to 5.5.1 Voltage Down Detection Interrupt for an operating condition)
7.6.3.1 Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to “1” (all
clocks turned off). At the same time, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode)
and the CM15 bit in the CM10 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit to “0” (oscillation stop, re-oscillation detection function
disable).
Also, if the CM11 bit is “1” (PLL clock for the CPU clock source), set the CM11 bit to “0” (main clock for
the CPU clock source) and the PLC07 bit to “0” (PLL turned off) before entering stop mode.
7.6.3.2 Pin Status during Stop Mode
The I/O pins retain their status held just prior to entering stop mode.
7.6.3.3 Exiting Stop Mode
______
The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral func-
tion interrupt.
______
If the microcomputer is to be moved out of stop mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the
CM10 bit to “1”.
If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the
following before setting the CM10 bit to “1”.
1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the
peripheral function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0
bits to “0002”.
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit stop mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt service routine is executed.
______
Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is
determined by the CPU clock that was on when the microcomputer was placed into stop mode as
follows:
If the CPU clock before entering stop mode was derived from the sub clock
If the CPU clock before entering stop mode was derived from the main clock
:
:
sub clock
main clock divide-by-8
If the CPU clock before entering stop mode was derived from the on-chip oscillator clock: on-chip oscillator clock
divide-by-8
page 53
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. Figure
7.6.1.1 shows the state transition in normal operation mode.
Table 7.6.1 shows a state transition matrix describing allowed transition and setting. The vertical line
shows current state and horizontal line shows state after transition.
Normal operation mode
CPU operation stopped
All oscillators stopped
WAIT
instruction
CM10=1(6)
Interrupt
Medium-speed mode
(divided-by-8 mode)
Stop mode
Wait mode
Interrupt
Interrupt
CM07=0
CM06=1
CM05=0
CM11=0
WAIT
instruction
High-speed, medium-
speed mode
Stop mode
Wait mode
CM10=1(6)
Interrupt
CM10=1
(5)
(1, 2)
PLL operation
mode
WAIT
CM10=1(6)
instruction
Stop mode
Stop mode
Stop mode
Low-speed mode
Wait mode
Wait mode
Wait mode
Interrupt
Interrupt
(7)
WAIT
instruction
CM10=1(6)
Low power dissipation mode
Interrupt
Interrupt
CM10=1(6)
Interrupt(4)
CM21=1
CM21=0
WAIT
instruction
On-chip oscillator low power
dissipation mode
Interrupt
On-chip oscillator mode
(selectable frequency)
WAIT
CM10=1(6)
Interrupt(4)
instruction
Stop mode
Wait mode
Interrupt
On-chip oscillator
mode (f2(ROC)/16)
CM05, CM06, CM07: Bits in the CM0 register
CM10, CM11: Bits in the CM1 register
Reset
: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.
NOTES:
1. Do not go directly from PLL operation mode to wait or stop mode.
2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
3. When the PM21 bit is set to 0 (system clock protective function unused).
4. The on-chip oscillator clock divided by 8 provides the CPU clock.
5. Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21 bit is set to 0 (on-chip oscillator
turned off). When the clock generated externally is input to the XCIN pin, transit to stop mode with this process.
6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to 0 (oscillation stop and oscillation restart detection
function disabled).
7. The CM06 bit is set to 1 (divide-by-8).
Figure 7.6.1. State Transition to Stop Mode and Wait Mode
page 54
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Main clock oscillation
On-chip oscillator clock
oscillation
On-chip oscillator low power
dissipation mode
Middle-speed mode
(divide by 4)
Middle-speed mode Middle-speed mode
PLL operation mode
Middle-speed mode
(divide by 2)
On-chip oscillator mode
PLC07=1
CM11=1
(5)
High-speed mode
CPU clock: f(XIN)
(divide by 8)
CPU clock: f(XIN)/8
CM07=0
(divide by 16)
CPU clock: f(PLL)
CM07=0
CPU clock
CPU clock
CM21=0
(2, 6)
CM05=0
CPU clock: f(XIN)/2
CPU clock: f(XIN)/4
CPU clock: f(XIN)/16
CM07=0
f(ROC)
f(ROC)
CM07=0
CM06=0
CM17=0
CM16=0
CM07=0
CM06=0
CM17=0
CM16=1
CM07=0
CM06=0
CM17=1
CM16=0
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16
CM06=0
CM06=0
CM17=1
CM16=1
CM17=0
PLC07=0
CM11=0
(5)
CM05=1
(1)
CM16=0
CM06=1
CM21=1
CM04=1
CM04=0
CM04=1
CM04=0
CM04=1
CM04=0
CM04=1
CM04=0
On-chip oscillator
low power
dissipation mode
PLL operation
mode
On-chip oscillator
mode
Middle-speed mode
(divide by 4)
Middle-speed mode Middle-speed mode
Middle-speed mode
(divide by 2)
High-speed mode
PLC07=1
CM11=1
(5)
(divide by 8)
(divide by 16)
CM21=0
(2, 6)
CPU clock
CPU clock
CPU clock: f(PLL)
CM07=0
CM05=0
CPU clock: f(XIN)
CM07=0
CPU clock: f(XIN)/2
CM07=0
CPU clock: f(XIN)/4
CM07=0
CPU clock: f(XIN)/8
CM07=0
CPU clock: f(XIN)/16
CM07=0
f(ROC)
f(ROC)
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16
f(ROC)/2
f(ROC)/4
f(ROC)/8
f(ROC)/16
CM06=0
CM06=0
CM06=0
CM06=0
CM17=1
CM16=0
CM06=0
CM17=1
CM16=1
CM17=0
PLC07=0
CM11=0
(5)
CM17=0
CM16=0
CM17=0
CM16=1
CM16=0
CM06=1
CM21=1
CM05=1
(1)
CM07=1
(3)
CM07=0
(2, 4)
CM07=0
(4)
CM07=1
(3)
Low-speed
mode
Low-speed mode
CM21=0
CPU clock: f(XCIN)
CM07=0
CPU clock: f(XCIN)
CM07=0
CM21=1
CM05=1
(1, 7)
CM05=0
Low power dissipation mode
CPU clock: f(XCIN)
CM07=0
CM06=1
CM15=1
Sub clock oscillation
: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.
NOTES:
1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Wait for the main clock oscillation stabilization time before switching over. Set the CM15 bit in the CM1 register to 1 (drive capacity High) until main clock oscillation is stabilized.
3. Switch clock after oscillation of sub-clock is sufficiently stable.
4. Change bits CM17 and CM16 before changing the CM06 bit.
5. The PM20 bit in the PM2 register becomes effective when the PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20 bit when the PLC07 bit is set to 0 (PLL off).
Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.
6. Set the CM06 bit to 1 (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
7. When the CM21 bit is set to 0 (on-chip oscillator turned off) and the CM05 bit is set to 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode) and the
CM15 bit is fixed to 1 (drive capability High).
Figure 7.6.1.1. State Transition in Normal Mode
page 55
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 7.6.1. Allowed Transition and Setting
State after transition
On-chip oscillator
low power
dissipation mode
On-chip oscillator
mode
PLL operation
mode
High-speed mode,
middle-speed mode
2
Low power
dissipation mode
Low-speed mode
Stop mode
2
Wait mode
High-speed mode,
middle-speed mode
7
3
1
8
(9)
--
(13)
(15)
(8)
--
--
--
--
--
(16)
(17)
2
Low-speed mode
1, 6
(11)
1
(8)
--
--
--
(16)
(17)
(17)
--
Low power dissipation
mode
1
(10)
--
(16)
2
PLL operation mode
3
--
--
--
--
(12)
On-chip oscillator mode
4
7
1
1
8
--
--
--
--
(14)
(9)
(11)
(16)
(17)
(17)
--
On-chip oscillator
low power dissipation
mode
1
--
--
--
(10)
(16)
8
Stop mode
5
5
5
(18)
(18)
(18)
(18)
(18)
(18)
(18)
Wait mode
(18)
(18)
(18)
--
NOTES:
--: Cannot transit
1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as a clock for the timers A and B.
3. PLL operation mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to 1 (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM06 bit is set to 1 (division by 8 mode).
6. If the CM05 bit is set to 1 (main clock stop), then the CM06 bit is set to 1 (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
Sub clock oscillating
Sub clock turned off
Divided Divided
Divided
by 2
Divided
by 2
Divided
by 8
Divided
by 4
Divided
by 16
No
division
Divided
by 4
No
division
by 8
by 16
(4)
(5)
(5)
(7)
(6)
(1)
--
--
--
--
--
--
--
--
No division
Divided by 2
(3)
(3)
(3)
(3)
(2)
--
(7)
(7)
(6)
(6)
(6)
(1)
--
(4)
(4)
(4)
--
--
(1)
--
--
--
Divided by 4
Divided by 8
Divided by 16
(5)
(5)
--
--
--
(1)
--
--
(7)
--
--
--
--
(1)
(6)
(6)
(6)
(6)
--
--
(4)
(5)
(5)
(7)
(7)
(7)
No division
Divided by 2
(2)
--
--
--
(3)
(3)
(3)
(3)
Divided by 4
Divided by 8
Divided by 16
--
(2)
--
--
--
(4)
(4)
(4)
--
--
(2)
--
--
(5)
(5)
--
--
--
(2)
(7)
--: Cannot transit
9. ( ) : setting method. Refer to following table.
Setting
Operation
Sub clock turned off
Sub clock oscillating
CM04, CM05, CM06, CM07 : Bits in the CM0 register
CM10, CM11, CM16, CM17 : Bits in the CM1 register
CM04 = 0
CM04 = 1
(1)
(2)
CM20, CM21
PLC07
: Bits in the CM2 register
: Bit in the PLC0 register
CM06 = 0,
(3)
CPU clock no division mode
CPU clock division by 2 mode
CM17 = 0 , CM16 = 0
CM06 = 0,
CM17 = 0 , CM16 = 1
(4)
CM06 = 0,
CM17 = 1 , CM16 = 0
CM06 = 0,
CM17 = 1 , CM16 = 1
CPU clock division by 4 mode
CPU clock division by 16 mode
CPU clock division by 8 mode
(5)
(6)
CM06 = 1
CM07 = 0
CM07 = 1
CM05 = 0
CM05 = 1
(7)
Main clock, PLL clock,
or on-chip oscillator clock selected
(8)
Sub clock selected
(9)
Main clock oscillating
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
Main clock turned off
PLC07 = 0,
CM11 = 0
PLC07 = 1,
CM11 = 1
Main clock selected
PLL clock selected
CM21 = 0
CM21 = 1
Main clock or PLL clock selected
On-chip oscillator clock selected
Transition to stop mode
Transition to wait mode
Exit stop mode or wait mode
CM10 = 1
wait instruction
Hardware interrupt
page 56
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7.7 System Clock Protective Function
When the main clock is selected for the CPU clock source, this function protects the clock from modifica-
tions in order to prevent the CPU clock from becoming halted by run-away.
If the PM21 bit in the PM2 register is set to “1” (clock modification disabled), the following bits are protected
against writes:
• CM02, CM05, and CM07 bits in CM0 register
• CM10, CM11 bits in CM1 register
• CM20 bit in CM2 register
• All bits in PLC0 register
Before the system clock protective function can be used, the following register settings must be made while
the CM05 bit in the CM0 register is “0” (main clock oscillating) and CM07 bit is “0” (main clock selected for
the CPU clock source):
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM2 register).
(2) Set the PM21 bit in the PM2 register to “1” (disable clock modification).
(3) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM2 register).
Do not execute the WAIT instruction when the PM21 bit is set to “1”.
7.8 Oscillation Stop and Re-oscillation Detect Function
The oscillation stop and re-oscillation detect function allows the detection of main clock oscillation stop and
reoscillation. At oscillation stop or re-oscillation detection, reset or oscillation stop, re-oscillation detection
interrupt are generated. Depending on the CM27 bit in the CM2 register. The oscillation stop detection
function can be enabled and disabled by the CM20 bit in the CM2 register. Table 7.8.1 lists a specification
overview of the oscillation stop and re-oscillation detect function.
Table 7.8.1. Specification Overview of Oscillation Stop and Re-oscillation Detect Function
Item
Specification
Oscillation stop detectable clock and
frequency bandwidth
f(XIN) ≥ 2 MHz
Enabling condition for oscillation stop, Set the CM20 bit to “1”(enable)
re-oscillation detection function
Operation at oscillation stop,
re-oscillation detection
•Reset occurs (when the CM27 bit is set to "0")
•Oscillation stop, re-oscillation detection interrupt occurs(when the CM27 bit is
set to "1")
page 57
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7.8.1 Operation When the CM27 bit is set to "0" (Oscillation Stop Detection Reset)
When main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection
function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. SFR,
5. Reset).
This status is reset with hardware reset 1 or hardware reset 2. Also, even when re-oscillation is detected,
the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (During
main clock stop, do not set the CM20 bit to “1” and the CM27 bit to “0”.)
7.8.2 Operation When the CM27 bit is set to "1" (Oscillation Stop and Re-oscillation
Detect Interrupt)
When the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop and
re-oscillation detect function enabled), the system is placed in the following state if the main clock comes
to a halt:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the CPU clock and
clock source for peripheral functions in place of the main clock.
• CM21 bit is set to "1" (on-chip oscillator clock for CPU clock source)
• CM22 bit is set to "1" (main clock stop detected)
• CM23 bit is set to "1" (main clock stopped)
When the PLL clock corresponds to the CPU clock source and the CM20 bit is “1”, the system is placed
in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1”
(on-chip oscillator clock) inside the interrupt routine.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit is set to "1" (main clock stop detected)
• CM23 bit is set to "1" (main clock stopped)
• CM21 bit remains unchanged
When the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from the
stop condition:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit is set to "1" (main clock re-oscillation detected)
• CM23 bit is set to "0" (main clock oscillation)
• CM21 bit remains unchanged
page 58
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
7. Clock Generation Circuit
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function
• The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter-
rupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read
the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
• Where the main clock re-oscillated after oscillation stop, return the main clock to the CPU clock and
peripheral function clock source in the program. Figure 7.8.3.1 shows the procedure for switching the
clock source from the on-chip oscillator to the main clock.
• Simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the CM22 bit be-
comes “1”. When the CM22 bit is set at “1”, oscillation stop, re-oscillation detection interrupt are dis-
abled. By setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection interrupt
are enabled.
• If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscilla-
tion detection interrupt request is generated. At the same time, the on-chip oscillator starts oscillating.
In this case, although the CPU clock is derived from the sub clock as it was before the interrupt oc-
curred, the peripheral function clocks now are derived from the on-chip oscillator clock.
• To enter wait mode while using the oscillation stop, re-oscillation detection function, set the CM02 bit to
“0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop, re-oscillation detection function is provided in preparation for main clock stop
due to external factors, set the CM20 bit to “0” (Oscillation stop, re-oscillation detection function dis-
abled) where the main clock is stopped or oscillated in the program, that is where the stop mode is
selected or the CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit
to “0”.
Switch to the main clock
Determine several times whether
the CM23 bit is set to 0
No
(main clock oscillates)
Yes
Set the CM06 bit to 1
(divide-by-8 mode)
Set the CM22 bit to 0
("oscillatin stop, re-oscillation" not detected)
Set the CM21 bit to 0
(main clock or PLL clock)
CM06: Bit in the CM0 register
End
CM23 to CM21: Bits in the CM2 register
NOTE:
1. If the clock source for CPU clock is to be changed to PLL clock, set to PLL operation
mode after set to high-speed mode.
Figure 7.8.3.1. Procedure to Switch Clock Source From On-chip Oscillator to Main Clock
page 59
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
8. Protection
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
8. Protection
Note
The PRC3 bit in the PRCR register is not available in M16C/26T.
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by
the PRCR register.
• Registers protected by PRC0 bit: CM0, CM1, CM2, PLC0, ROCR and PCLKR registers
• Registers protected by PRC1 bit: PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers
• Registers protected by PRC2 bit: PD9, PACR and NDDR registers
• Registers protected by PRC3 bit: VCR2 and D4INT registers
Set the PRC2 bit to “1” (write enabled) and then write to SFR area, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction. The PRC0, PRC1 and PRC3 bits are not automati-
cally cleared to “0” by writing to any address. They can only be cleared in a program.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
After reset
XX000000
0
0
2
Bit symbol
PRC0
Bit name
Function
RW
RW
Enable write to CM0, CM1, CM2,
ROCR, PLC0 and PCLKR registers
Protect bit 0
0 : Write protected
1 : Write enabled
Enable write to PM0, PM1, PM2,
TB2SC, INVC0 and INVC1
registers
PRC1
Protect bit 1
RW
RW
0 : Write protected
1 : Write enabled
Enable write to PD9, PACR and
NDDR registers
PRC2
PRC3
Protect bit 2
Protect bit 3
Reserved bit
0 : Write protected
1 : Write enabled
Enable write to VCR2 and D4INT
registers
RW
RW
0 : Write protected
1 : Write enabled
Must set to "0"
(b5-b4)
(b7-b6)
Nothing is assigned. When write, set to "0". When read, its
content is indeterminate.
NOTE:
1. The PRC2 bit is set to "0" if data is written to the SFR area after the PRC2 bit is set to "1". The
PRC0, PRC1 and PRC3 bits are not automatically set to "0". Set them to "0" by program.
Figure 8.1. PRCR Register
page 60
of 329
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9. Interrupt
Note
The 42-pin package does not use UART0 transmission interrupt and UART0 reception interrupt of
peripheral function.
M16C/26T does not use voltage down detection interrupt.
9.1 Type of Interrupts
Figure 9.1.1 shows types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
Software
BRK instruction
(Non-maskable interrupt)
INT instruction
_______
NMI
DBC (2)
________
Interrupt
Watchdog timer
Special
Oscillation stop and re-oscillation
detection
(Non-maskable interrupt)
Low voltage detection
Single step (2)
Hardware
Address match
Peripheral function (1)
(Maskable interrupt)
NOTES:
1. Peripheral function interrupts are generated by the microcomputer's internal functions.
2. Do not normally use this interrupt because it is provided exclusively for use by development tools.
Figure 9.1.1. Interrupts
• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
page 61
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.1.1 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
9.1.1.1 Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
9.1.1.2 Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the opera-
tion resulted in an overflow). The following are instructions whose O flag changes by arithmetic: ABS,
ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
9.1.1.3 BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
9.1.1.4 INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63
can be specified for the INT instruction. Because software interrupt Nos. 4, 8 to 31 are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be
executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not
change state during instruction execution, and the SP then selected is used.
page 62
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.1.2 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
9.1.2.1 Special Interrupts
Special interrupts are non-maskable interrupts.
_______
9.1.2.1.1 NMI Interrupt
_______
_______
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details
_______
_______
about the NMI interrupt, refer to the section 9.7 NMI Interrupt.
________
9.1.2.1.2 DBC Interrupt
This interrupt is exclusively for debugger, do not use in any other circumstances.
9.1.2.1.3 Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to the section 10. Watchdog Timer.
9.1.2.1.4 Oscillation Stop and Re-oscillation Detection Interrupt
Generated by the oscillation stop and re-oscillation detection function. For details about the oscilla-
tion stop and re-oscillation detection function, refer to the section 7. Clock Generating Circuit.
9.1.2.1.5 Voltage Down Detection Interrupt
Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to the
section 5.5 Voltage Detection Circuit.
9.1.2.1.6 Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development tools.
9.1.2.1.7 Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 or RMAD1 register, if the corresponding enable bit (the AIER0 or AIER1 bit
in the AIER register) is set to “1”. For details about the address match interrupt, refer to the section
9.9 Address Match Interrupt.
9.1.2.2 Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in Table 9.2.2.1
Relocatable Vector Tables. For details about the peripheral functions, refer to the description of
each peripheral function in this manual.
page 63
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.2 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 9.2.1 shows the interrupt vector.
MSB
LSB
Low address
Mid address
Vector address (L)
Vector address (H)
0 0 0 0
0 0 0 0
High address
0 0 0 0
Figure 9.2.1. Interrupt Vector
9.2.1 Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 9.2.1.1 lists the
fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to the section 17.3 Flash Memory
Rewrite Disabling Function.
Table 9.2.1.1. Fixed Vector Tables
Interrupt source
Vector table addresses
Address (L) to address (H)
Remarks
Reference
Undefined instruction FFFDC16 to FFFDF16
Interrupt on UND instruction
M16C/60, M16C/20
serise software
maual
Overflow
FFFE016 to FFFE316
FFFE416 to FFFE716
Interrupt on INTO instruction
If the contents of address
FFFE716 is FF16, program ex-
ecution starts from the address
shown by the vector in the
relocatable vector table.
BRK instruction
Address match
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
Address match interrupt
Single step (1)
Watchdog timer
Oscillation stop and
re-oscillation detection
Voltage down
Watchdog timer
Clock generating circuit
Voltage detection circuit
detection
________
DBC (1)
FFFF416 to FFFF716
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
_______
_______
NMI
NMI interrupt
Reset (2)
Reset
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development tools.
2. The b3 to b0 in address 0FFFFF16 are reserve bits. Set these bits to “11112”.
page 64
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.2.2 Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector
table area. Table 9.2.2.1 lists the relocatable vector tables. Setting an even address in the INTB register
results in the interrupt sequence being executed faster than in the case of odd addresses.
Table 9.2.2.1. Relocatable Vector Tables
Vector address (1)
Address (L) to address (H)
Software interrupt
number
Reference
Interrupt source
(4)
M16C/60, M16C/20
series software
manual
+0 to +3 (000016 to 000316
)
BRK instruction
0
(Reserved)
1 to 3
4
+16 to +19 (001016 to 001316
)
INT interrupt
INT3
(Reserved)
5 to 7
+32 to +35 (002016 to 002316
+36 to +39 (002416 to 002716
)
)
8
9
(2)
(2)
INT5
INT4
INT interrupt
Serial I/O
DMAC
+40 to +43 (002816 to 002B16
)
10
11
UART 2 bus collision detection (5)
DMA0
+44 to +47 (002C16 to 002F16
)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
+48 to +51 (003016 to 003316
+52 to +55 (003416 to 003716
)
DMA1
Key input interrupt
A/D convertor
)
Key input interrupt
A/D
+56 to +59 (003816 to 003B16
)
UART2 transmit, NACK2 (3)
UART2 receive, ACK2 (3)
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
+60 to +63 (003C16 to 003F16
)
+64 to +67 (004016 to 004316
+68 to +71 (004416 to 004716
+72 to +75 (004816 to 004B16
)
)
Serial I/O
)
+76 to +79 (004C16 to 004F16
)
+80 to +83 (005016 to 005316
+84 to +87 (005416 to 005716
+88 to +91 (005816 to 005B16
)
)
)
Timer A1
+92 to +95 (005C16 to 005F16
+96 to +99 (006016 to 006316
)
Timer A2
Timer A3
)
Timer
+100 to +103 (006416 to 006716
+104 to +107 (006816 to 006B16
)
)
Timer A4
Timer B0
+108 to +111 (006C16 to 006F16
)
Timer B1
+112 to +115 (007016 to 007316
+116 to +119 (007416 to 007716
+120 to +123 (007816 to 007B16
)
Timer B2
)
INT0
INT1
INT2
INT interrupt
)
+124 to +127 (007C16 to 007F16
)
32
to
M16C/60, M16C/20
series software
manual
+128 to +131 (008016 to 008316
to
+252 to +255 (00FC16 to 00FF16
)
Software interrupt
NOTES:
(4)
63
)
1. Address relative to address in INTB.
2. Set the IFSR6 and IFSR7 bits in the IFSR register.
3. During I2C bus mode, NACK and ACK interrupts comprise the interrupt source.
4. These interrupts cannot be disabled using the I flag.
5. Bus collision detection:
During IEBus mode, this bus collision detection constitutes the cause of an interrupt.
During I2C bus mode, however, a start condition or a stop condition detection constitutes the cause of an interrupt.
page 65
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.3 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and the ILVL2 to ILVL0 bits in the each interrupt control register to
enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each
interrupt control register.
Figure 9.3.1 shows the interrupt control registers.
Figure 9.3.2 shows the IFSR, IFSR2A registers.
page 66
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Interrupt control register (2)
Symbol
Address
004A16
004B16, 004C16
004D16
After reset
BCNIC
DM0IC, DM1IC
KUPIC
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
ADIC
004E16
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
005A16 to 005C16
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Bit symbol
ILVL0
Bit name
Function
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
RW
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL2
IR
RW
0 : Interrupt not requested
1 : Interrupt requested
RW
(1)
Interrupt request bit
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
(b7-b4)
NOTES:
1.This bit can only be reset by writing “0” (Do not write “1”).
2. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see 19.5 Interrupts.
Symbol
INT3IC
INT5IC
INT4IC
INT0IC to INT2IC
Address
004416
004816
004916
After reset
XX00X0002
XX00X0002
XX00X0002
b7 b6 b5 b4 b3 b2 b1 b0
0
005D16 to 005F16 XX00X0002
Bit symbol
ILVL0
Bit name
Function
RW
RW
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1
ILVL2
RW
RW
IR
Interrupt request bit
Polarity select bit
0: Interrupt not requested
1: Interrupt requested
RW
(1)
POL
0 : Selects falling edge (3)
1 : Selects rising edge
RW
RW
Reserved bit
Must always be set to “0”
(b5)
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
RW
(b7-b6)
when read are indeterminate.
NOTES:
1. This bit can only be reset by writing “0” (Do not write “1”).
2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register.
For details, see 19.5 Interrupts.
3. If the IFSRi bit (i = 0 to 5) in the IFSR register is “1” (both edges), set the POL bit in the INTiIC register to “0” (falling
edge).
Figure 9.3.1. Interrupt Control Registers
BCNIC, DM0IC, DM1IC, KUPIC, ADIC, S0TIC to S2TIC, S0RIC to S2RIC, TA0IC to TA4IC, TB0IC TO
TB2IC, INT3IC, INT4IC, INT5IC, INT0IC to INT2IC
page 67
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
035F16
After reset
0016
Bit symbol
Bit name
Function
RW
RW
IFSR0
INT0 interrupt polarity
switching bit
0 : One edge
1 : Both edges (1)
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges (1)
RW
RW
RW
INT2 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(1)
(1)
INT3 interrupt polarity
switching bit
0 : One edge
1 : Both edges
INT4 interrupt polarity
switching bit
0 : One edge
1 : Both edges
RW
RW
RW
RW
(1)
(1)
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
Interrupt request cause
select bit
0 : Reserved
1 : INT4
Interrupt request cause
select bit
0 : Reserved
1 : INT5
NOTE:
1. When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register is set to
“0” (= falling edge).
Interrupt request cause select register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR2A
Address
035E16
After reset
XXXXXXX0
1
2
Bit symbol
Bit name
Function
Must be set to “1”.
RW
RW
Reserved bit
IFSR20
(b7-b1)
(1)
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
NOTE:
1. Set this bit to "1" before you enable interrupt after resetting.
Figure 9.3.2. IFSR Register and IFSR2A Register
page 68
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.3.1 I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the
maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
9.3.2 IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
9.3.3 ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 9.3.3.1 shows the settings of interrupt priority levels and Table 9.3.3.2 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag is set to “1”
· IR bit is set to “1”
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 9.3.3.2. Interrupt Priority Levels
Enabled by IPL
Table 9.3.3.1. Settings of Interrupt Priority
Levels
Interrupt priority
level
Priority
order
ILVL2 to ILVL0 bits
IPL
Enabled interrupt priority levels
000
001
010
011
100
101
110
111
2
Level 0 (interrupt disabled)
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
000
001
010
011
100
101
110
111
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
page 69
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.4 Interrupt Sequence
An interrupt sequence (the devicebehavior from the instant an interrupt is accepted to the instant the inter-
rupt routine is executed) is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 9.4.1 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading
the address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not
requested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
(1)
temporary register
.
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(1)
(4) The CPU’s internal temporary register
is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
NOTE:
1. This register cannot be used by user.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CPU clock
Address bus
Data bus
Address
000016
Indeterminate(1)
Indeterminate(1)
SP-2
SP-4
vec
vec+2
PC
Interrupt
information
SP-2
SP-4
vec
vec+2
contents contents contents contents
RD(2)
WR(2)
Indeterminate(1)
NOTES:
1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the
instruction queue buffer is ready to accept instructions.
2. RD is the internal signal which is set to “L” when the internal memory is read out and WR is the
internal signal which is set to “L” when the internal memory is written.
Figure 9.4.1. Time Required for Executing Interrupt Sequence
page 70
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.4.1 Interrupt Response Time
Figure 9.4.1.1 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes the time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of the time from when an interrupt request is generated till
when the instruction then executing is completed ((a) in Figure 9.4.1.1) and the time during which the
interrupt sequence is executed ((b) in Figure 9.4.1.1).
Interrupt request generated
Interrupt request acknowledged
Time
Instruction in
interrupt routine
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
(a) The time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) The time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address SP value
Without wait
Even
Even
Odd
Even
Odd
18 cycles
19 cycles
19 cycles
20 cycles
Even
Odd
Odd
Figure 9.4.1.1. Interrupt response time
9.4.2 Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 9.4.2.1 is set in the IPL. Shown in Table 9.4.2.1 are the IPL values of software and special
interrupts when they are accepted.
Table 9.4.2.1. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources
Level that is set to IPL
_______
Watchdog timer, NMI, Oscillation stop and re-oscillation detection,
7
voltage down detection
_________
Not changed
Software, address match, DBC, single-step
page 71
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.4.3 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
9.4.3.1 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Stack
Stack
Address
MSB
Address
MSB
LSB
LSB
[SP]
New SP value
m – 4
m – 3
m – 2
m – 1
m
m – 4
m – 3
m – 2
m – 1
m
PC
L
PCM
FLG
L
FLG
H
PCH
[SP]
SP value before
interrupt request is
accepted.
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
m + 1
m + 1
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 9.4.3.1. Stack Status Before and After Acceptance of Interrupt Request
page 72
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1)
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
,
(1)
at the time of acceptance of an interrupt request, is even or odd. If the stack pointer is even, the FLG
register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time.
Figure 9.4.3.2 shows the operation of the saving registers.
NOTE:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
Stack
Sequence in which order
registers are saved
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
PC
L
(2) Saved simultaneously,
all 16 bits
PC
M
FLG
L
(1) Saved simultaneously,
all 16 bits
FLG
H
PC
H
[SP]
(Even)
Finished saving registers
in two operations.
(2) SP contains odd number
Address
Stack
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
PC
L
(3)
PC
M
(4)
Saved, 8 bits at a time
FLG
L
(1)
(2)
FLG
H
PC
H
[SP]
(Odd)
Finished saving registers
in four operations.
NOTE:
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 9.4.3.2. Operation of Saving Register
page 73
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.4.4 Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt se-
quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt
request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
9.5 Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.5.1
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
NMI
High
DBC
Watchdog Timer,
Oscillation stop and re-oscillation
detection,
voltage down detection
Peripheral function
Single step
Low
Address match
Figure 9.5.1. Hardware Interrupt Priority
9.5.1 Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 9.5.1.1 shows the circuit that judges the interrupt priority level.
page 74
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Priority level of each interrupt
Level 0 (initial value)
Highest
INT1
Timer B2
Timer B0
Timer A3
Timer A1
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
UART1 reception
UART0 reception
UART2 reception, ACK2
A/D conversion
DMA1
Priority of peripheral function interrupts
(if priority levels are same)
UART 2 bus collision
INT5
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission, NACK2
Key input interrupt
DMA0
Lowest
INT4
IPL
Interrupt request level resolution output to clock
generating circuit (Fig.7.1.)
Interrupt
request
accepted
I flag
Address match
Watchdog timer
Oscillation stop and
re-oscillation detection
Voltage down detection
DBC
NMI
Figure 9.5.1.1. Interrupts Priority Select Circuit
page 75
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.6 _I_N__T__ Interrupt
_______
INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSRi bit in the IFSR register.
________
________
________
To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to "1" (=INT4). To use the INT5 interrupt, set
________
the IFSR7 bit in the IFSR register to "1" (=INT5).
After modifiying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to "0" (=interrupt not requested)
before enabling the interrupt.
________
The INT5 input has an effective digital debounce function for a noize rejection. Refer to 16.6 Digital
________
Debounce function for this detail. When using INT5 interrupt to exit stop mode, set the P17DDR register
to "FF16" before entering stop mode.
Figure 9.6.1 shows the IFSR register.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
035F16
After reset
0016
Bit symbol
Bit name
Function
RW
RW
IFSR0
INT0 interrupt polarity
switching bit
0 : One edge
1 : Both edges (1)
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges (1)
RW
RW
RW
INT2 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(1)
(1)
INT3 interrupt polarity
switching bit
0 : One edge
1 : Both edges
INT4 interrupt polarity
switching bit
0 : One edge
1 : Both edges
RW
RW
RW
RW
(1)
(1)
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
Interrupt request cause
select bit
0 : Reserved
1 : INT4
Interrupt request cause
select bit
0 : Reserved
1 : INT5
NOTE:
1. When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register is set to
“0” (= falling edge).
Figure 9.6.1. IFSR Register
page 76
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
______
9.7 NMI Interrupt
_______
_______
An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the
_______
______
NMI interrupt was enabled by writing a “1” to PM24 bit in the PM2 register. The NMI interrupt is a non-
maskable interrupt, once it is enabled.
_______
The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register.
_______
NMI is disabled by default after reset (the pin is a GPIO pin, P85) and can be enabled using PM24 bit in the
PM2 register. Once enabled, it can only be disabled by a reset signal.
_______
The NMI input has an effective digital debounce function for a noise rejection. Refer to 16.6 Digital
_______
Debounce Function for this detail. When using NMI interrupt to exit stop mode, set the NDDR register to
"FF16" before entering stop mode.
9.8 Key Input Interrupt
Of P104 to P107, a key input interrupt is generated when input on any of the P104 to P107 pins which has
had the PD10_4 to PD10_7 bits in the PD10 register set to “0” (= input) goes low. Key input interrupts can
be used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode.
However, if you intend to use the key input interrupt, do not use P104 to P107 as analog input ports. Figure
9.8.1 shows the block diagram of the key input interrupt. Note, however, that while input on any pin which
has had the PD10_4 to PD10_7 bits set to “0” (= input mode) is pulled low, inputs on all other pins of the port
are not detected as interrupts.
PU25 bit in the
PD10 register
Pull-up
KUPIC register
transistor
PD10_7 bit in the
PD10 register
PD10_7 bit in the PD10 register
KI3
KI2
PD10_6 bit in the
PD10 register
Pull-up
transistor
Key input interrupt
request
Interrupt control circuit
Pull-up
transistor
PD10_5 bit in the
PD10 register
KI1
KI0
PD10_4 bit in the
PD10 register
Pull-up
transistor
Figure 9.8.1. Key Input Interrupt
page 77
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
9.9 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi
register. Use the AIER register’s AIER0 and AIER1 bits to enable or disable the interrupt. Note that the
address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the
PC that is saved to the stack area varies depending on the instruction being executed (refer to “Saving
Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 9.9.1 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Figure 9.9.1 shows the AIER, RMAD0 and RMAD1 registers.
Table 9.9.1. Value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Value of the PC that is
Instruction at the address indicated by the RMADi register
saved to the stack area
• 2-byte op-code instruction
The address
• 1-byte op-code instructions which are followed:
indicated by the
RMADi register +2
ADD.B:S
OR.B:S
STNZ.B
CMP.B:S
JMPS
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8
SUB.B:S
MOV.B:S
STZX.B
PUSHM
JSRS
#IMM8,dest
#IMM8,dest
#IMM81,#IMM82,dest
src
AND.B:S #IMM8,dest
STZ.B
#IMM8,dest
POPM dest
#IMM8
MOV.B:S
#IMM,dest (However, dest=A0 or A1)
The address
indicated by the
RMADi register +1
Instructions other than the above
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
Op-code is an abbreviation of Operation Code. It is a portion of instruction code.
Refer to Chapter 4 Instruction Code/Number of Cycles in M16C/60, M16C/20 Series Software Manual. Op-code is shown
as a bold-framed figure directly below the Syntax.
Table 9.9.2. Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources Address match interrupt enable bit Address match interrupt register
Address match interrupt 0
Address match interrupt 1
AIER0
AIER1
RMAD0
RMAD1
page 78
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
9. Interrupt
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
After reset
XXXXXX00
2
Bit symbol
AIER0
Bit name
Function
RW
RW
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Address match interrupt 1
enable bit
AIER1
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
(b7-b2)
Address match interrupt register i (i = 0 to 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
After reset
X0000016
X0000016
b0
Function
Setting range
0000016 to FFFFF16
RW
RW
Address setting register for address match interrupt
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Figure 9.9.1. AIER Register, RMAD0 and RMAD1 Registers
page 79
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
10. Watchdog Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
10. Watchdog Timer
The watchdog timer is the function that detects when a program is out of control. Use the watchdog timer is
recommended to improve reliability of the system. The watchdog timer contains a 15-bit counter which is
decremented by the CPU clock that the prescaler divides. The PM12 bit in the PM1 register determines whether
to generate a watchdog timer interrupt request or reset the watchdog timer when the watchdog timer underflows.
The PM12 bit can only be set to “1” (reset). Once the PM12 bit is set to “1”, it cannot be changed to “0” (watchdog
timer interrupt) by program. Refer to “5.3 Watchdog Timer Reset” for watchdog timer reset.
When the main clock, on-chip oscillator clock, or PLL clock runs as CPU clock, the WDC7 bit in the WDC register
determines whether the prescaler divides the clock by 16 or 128. When the sub clock runs as CPU clock, the
prescaler divides the clock by 2 regardless of the WDC7 bit setting. Watchdog timer cycle is calculated as
follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.
With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
Watchdog timer period =
CPU clock
With sub-clock chosen for CPU clock
Prescaler dividing (2) X Watchdog timer count (32768)
Watchdog timer period =
CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer
period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that
the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start
counting by writing to the WDTS register.
Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the
beginning of the watchdog timer interrupt routine.
In stop mode, wait mode and when erase/program opration is excuting in EW1 mode without erase suspend
requeired, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the
modes or state are released.
Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related registers.
Prescaler
CM07 = 0
WDC7 = 0
1/16
PM12 = 0
CM07 = 0
WDC7 = 1
Watchdog timer
interrupt request
PM22 = 0
PM22 = 1
1/128
1/2
CPU clock
Watchdog timer
CM07 = 1
PM12 = 1
Reset
On-chip oscillator clock
Set to 7FFF16
Write to WDTS register
Internal reset signal
(low active)
Figure 10.1. Watchdog Timer Block Diagram
page 80
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
10. Watchdog Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
After Reset
00XXXXXX
0 0
2
Bit Symbol
Bit Name
Function
RW
RO
(b4-b0)
High-order bit of watchdog timer
Reserved bit
Set to “0”
0: Divided by 16
RW
RW
(b6-b5)
WDC7
Prescaler select bit
1: Divided by 128
Watchdog Timer Start Register
b7
b0
Symbol
WDTS
Address
000E16
After Reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
RW
WO
this register. The watchdog timer value is always initialized to “7FFF 16
”
regardless of whatever value is written.
Figure 10.2 WDC Register and WDTS Register
10.1 Count Source Protective Mode
In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer
can be kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count
source).
(4) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
Setting the PM22 bit to “1” results in the following conditions
• The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main
clock or PLL clock) (system clock of count source selected by the CM21 bit is valid)
• The on-chip oscillator starts oscillating, and the in-chip oscillator clock becomes the watchdog timer count
source.
Watchdog timer count (32768)
Watchdog timer period =
on-chip oscillator clock
• The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode.
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
page 81 of 329
11. DMAC
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
11. DMAC
Note
Do not use UART0 transfer and UART0 reception interrupt request as a DMA request in the 42-pin
package.
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by
the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of
a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time
after a DMA request is generated. Figure 11.1 shows the block diagram of the DMAC. Table 11.1 shows the
DMAC specifications. Figures 11.2 to 11.4 show the DMAC-related registers.
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016
DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416
DMA0 forward address pointer (20) (1)
)
)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016
DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416
DMA1 forward address pointer (20) (1)
(addresses 002916, 002816
)
)
)
DMA0 transfer counter TCR0 (16)
)
DMA1 transfer counter reload register TCR1 (16)
(addresses 003916, 003816
DMA latch high-order bits
DMA latch low-order bits
DMA1 transfer counter TCR1 (16)
Data bus low-order bits
Data bus high-order bits
NOTE:
1. Pointer is incremented by a DMA request.
Figure 11.1 DMAC Block Diagram
A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0,1), as well as by an
interrupt request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits in the
DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I
flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt
request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not
affect interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON
register is set to “1” (DMA enabled). However, if the cycle in which a DMA request is generated is faster
than the DMA transfer cycle, the number of transfer requests generated and the number of times data is
transferred may not match. For details, refer to 11.4 DMA Requests.
page 82
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
11. DMAC
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 11.1 DMAC Specifications
Item
Specification
No. of channels
2 (cycle steal method)
Transfer memory space
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
________
(1, 2)
DMA request factors
Falling edge of INT0 or INT1
________ ________
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
A/D conversion interrupt requests
Software triggers
Channel priority
Transfer unit
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
Transfer address direction
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer mode Single transfer Transfer is completed when the DMAi transfer counter (i = 0,1)
underflows after reaching the terminal count.
Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is con
tinued with it.
DMA interrupt request generation timing When the DMAi transfer counter underflowed
DMA startup
Data transfer is initiated each time a DMA request is generated when the
DMAE bit in the DMAiCON register is set to “1” (enabled).
DMA shutdown Single transfer • When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
Repeat transfer When the DMAE bit is set to “0” (disabled)
When a data transfer is started after setting the DMAE bit to “1” (en
abled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
N OTES:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 002016 to 003F16) are accessed by the DMAC.
page 83
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
11. DMAC
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
DMA0 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0SL
Address
03B816
After reset
0016
Bit symbol
DSEL0
Bit name
Function
RW
RW
RW
DMA request cause
select bit
Refer to note
DSEL1
DSEL2
DSEL3
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b5-b4)
DMS
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
RW
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
Software DMA
request bit
DSR
DSEL3 to DSEL0 bits are “0001 2”
(software trigger).
The value of this bit when read is “0” .
NOTE:
1. The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS=0(basic cause of request)
DMS=1(extended cause of request)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
–
–
–
–
–
–
Two edges of INT0 pin
–
–
–
–
–
–
–
–
–
Timer B2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
A/D conversion
UART1 transmit
Figure 11.2 DM0SL Register
page 84
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
11. DMAC
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
DMA1 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM1SL
Address
03BA16
After reset
0016
Function
Bit name
Bit symbol
DSEL0
RW
RW
RW
RW
DMA request cause
select bit
Refer to note
DSEL1
DSEL2
DSEL3
(b5-b4)
DMS
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
RW
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
Software DMA
request bit
DSR
DSEL3 to DSEL0 bits are “0001 2”
(software trigger).
The value of this bit when read is “0” .
NOTE:
1. The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS=0(basic cause of request)
DMS=1(extended cause of request)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
–
–
–
–
–
–
–
Two edges of INT1
–
–
–
–
–
–
–
–
Timer B2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive/ACK2
A/D conversion
UART1 receive
DMAi control register(i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0CON
DM1CON
Address
002C16
003C16
After reset
00000X00
00000X00
2
2
Bit symbol
Bit name
Function
RW
RW
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
DMBIT
DMASL
DMAS
DMAE
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
RW
RW
(1)
0 : DMA not requested
1 : DMA requested
DMA request bit
DMA enable bit
0 : Disabled
1 : Enabled
RW
RW
RW
Source address direction
select bit (2)
0 : Fixed
1 : Forward
DSD
DAD
Destination address
direction select bit (2)
0 : Fixed
1 : Forward
Nothing is assigned. When write, set to “0”. When
read, its content is “0”.
(b7-b6)
NOTES:
1.The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
2. At least one of the DAD and DSD bits must be “0” (address direction fixed).
Figure 11.3 DM1SL Register, DM0CON Register, and DM1CON Register
page 85
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
11. DMAC
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
DMAi source pointer (i = 0, 1) (1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
After reset
Indeterminate
Indeterminate
Setting range
0000016 to FFFFF16
Function
Set the source address of transfer
RW
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
NOTE:
1. If the DSD bit in the DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is “0” (DMA disabled). If the DSD bit is set to “1” (forward direction), this register can be written to
at any time. If the DSD bit is set to “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer
can be read from this register. Otherwise, the value written to it can be read.
DMAi destination pointer (i = 0, 1)(1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
After reset
Indeterminate
Indeterminate
Setting range
0000016 to FFFFF16
Function
Set the destination address of transfer
RW
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
NOTE:
1. If the DAD bit in the DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is “0”(DMA disabled).If the DAD bit is set to “1” (forward direction), this register can be written to at
any time. If the DAD bit is set to “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can
be read from this register. Otherwise, the value written to it can be read.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
After reset
Indeterminate
Indeterminate
Setting range
Function
RW
RW
Set the transfer count minus 1. The written value is
stored in the DMAi transfer counter reload register, and
when the DMAE bit in the DMiCON register is set to “1”
(DMA enabled) or the DMAi transfer counter
underflows when the DMASL bit in the DMiCON
register is “1” (repeat transfer), the value of the DMAi
transfer counter reload register is transferred to the
DMAi transfer counter. When read, the DMAi transfer
counter is read.
000016 to FFFF16
Figure 11.4 SAR0 and SAR1, DAR0 and DAR1, TCR0 and TCR1 Registers
page 86
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
11. DMAC
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
11.1 Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write)
bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of
transfer. Furthermore, the bus cycle itself is extended by a software wait.
11.1.1 Effect of Source and Destination Addresses
If the transfer unit is 16 bits and the source address of transfer begins with an odd address, the source
read cycle consists of one more bus cycle than when the source address of transfer begins with an even
address.
Similarly, if the transfer unit is 16 bits and the destination address of transfer begins with an odd address,
the destination write cycle consists of one more bus cycle than when the destination address of transfer
begins with an even address.
11.1.2 Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of bus
cycles required for that access increases by an amount equal to software wait states.
Figure 11.1.1 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the
destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle
changing accordingly. When calculating transfer cycles, take into consideration each condition for the
source read and the destination write cycle, respectively. For example, when data is transferred in 16 bit
units and when both the source address and destination address are an odd address ((2) in Figure 11.1.1),
two source read bus cycles and two destination write bus cycles are required.
page 87
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
11. DMAC
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
CPU clock
Address
bus
Dummy
cycle
Destination
CPU use
Source
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
Destination
CPU use
Source
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address
CPU clock
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
CPU use
Destination
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source + 1
Source
CPU use
Destination
(3) When the source read cycle under condition (1) has one wait state inserted
CPU clock
Dummy
cycle
Address
bus
Destination
Source
CPU use
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
Destination
CPU use
Source
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
CPU clock
Address
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
bus
RD signal
WR signal
Data
bus
Dummy
cycle
Destination
CPU use
CPU use
Source
Source + 1
NOTE:
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 11.1.1 Transfer Cycles for Source Read
page 88
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
11. DMAC
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
11.2. DMA Transfer Cycles
Any combination of even or odd transfer read and write adresses is possible. Table 11.2.1 shows the
number of DMA transfer cycles. Table 11.2.2 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 11.2.1 DMA Transfer Cycles
Transfer unit
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
Access address
Even
No. of read cycles
No. of write cycles
1
1
1
2
1
1
1
2
Odd
Even
Odd
Table 11.2.2 Coefficient j, k
Internal area
Internal ROM, RAM
No wait With wait
SFR
1 wait
2 wait
(1)
(1)
3
j
1
1
2
2
2
2
3
k
NOTE:
1. Depends on the set value of PM20 bit in PM2 register.
page 89
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
11. DMAC
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
11.3 DMA Enable
When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON
register is “1” (forward) or the DARi register value when the DAD bit in the DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However,
if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
11.4 DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS
and DSEL3 to DSEL0 bits in the DMiSL register (i = 0, 1) on either channel. Table 11.4.1 shows the timing
at which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is set
to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in a
program (it can only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 11.4.1 Timing at Which the DMAS Bit Changes State
DMAS bit in the DMiCON register
DMA factor
Timing at which the bit is set to “1” Timing at which the bit is set to “0”
When the DSR bit in the DMiSL
register is set to “1”
• Immediately before a data transfer starts
• When set by writing “0” in a program
Software trigger
Peripheral function
When the interrupt control register
for the peripheral function that is
selected by the DSEL3 to DSEL0
and DMS bits in the DMiSL register
has its IR bit set to “1”
page 90
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
11. DMAC
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
11.5 Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are de-
tected active in the same sampling period (one period from a falling edge to the next falling edge of CPU
clock), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA
requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes DMAC
operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 11.5.1
shows an example of DMA transfer effected by external factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request
are generated simultanelously. After one DMA0 transfer is completed, a bus arbitration is returned to the
CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is
completed, the bus arbitration is again returned to the CPU.
In addition, DMA requsts cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 11.5.1, occurs more than one time, the DAMS bit is set to "0" as soon
as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
An example where DMA requests for external causes are detected active at the same
CPU clock
DMA0
Obtainment
of the bus
right
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 11.5.1 DMA Transfer by External Factors
page 91
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12. Timer
Note
The TB2IN pin is not available in the 42-pin package. Do not use functions associated with the TB2IN
pin.
Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as
either timer A (five) and timer B (three). The count source for each timer acts as a clock, to control such
timer operations as counting, reloading, etc. Figures 12.1 and 12.2 show block diagrams of timer A and
timer B configuration, respectively.
f
2
PCLK0 bit = "0"
f
Clock prescaler
1/2
1/8
• Main clock
• PLL clock
• On-chip
1 or f2
f
1
f
C32
1/32
XCIN
PCLK0 bit = "1"
f
Reset
8
oscillator clock
Set the CPSR bit in the
CPSRF register to “1”
(= prescaler reset)
f
32
1/4
f8 f32 fC32
f
1 or f2
• Timer mode
• One-shot timer mode
• Pulse Width Measuring (PWM) mode
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer A0
Noise
filter
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A1
Noise
filter
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A2
Noise
filter
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A3
Noise
filter
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A4
Noise
filter
• Event counter mode
Timer B2 overflow or underflow
Figure 12.1. Timer A Configuration
page 92
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
f
2
PCLK0 bit = "0"
Clock prescaler
1/2
1/8
• Main clock
• PLL clock
• On-chip
f
1 or f2
f
1
f
C32
1/32
XCIN
PCLK0 bit = "1"
f
Reset
8
Set the CPSR bit in the
CPSRF register to “1”
(= prescaler reset)
oscillator clock
f
32
1/4
f
1 or f2 f8 f32 fC32
Timer B2 overflow or underflow ( to Timer A count source)
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B0 interrupt
Noise
filter
Timer B0
TB0IN
TB1IN
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B1 interrupt
Timer B2 interrupt
Noise
filter
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB2IN
Timer B2
• Event counter mode
Figure 12.2. Timer B Configuration
page 93
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.1 Timer A
Figure 12.1.1 shows a block diagram of the timer A. Figures 12.1.2 to 12.1.4 show registers related to the
timer A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of
other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count
“000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f1 or f2
Low-order
8 bits
High-order
8 bits
f8
• Timer
(gate function)
f
32
Reload register
f
C32
Clock selection
• Event counter
Counter
Polarity
selection
Up-count/down-count
TAiIN
(i = 0 to 4)
Always counts down except
in event counter mode
TABSR register
Clock selection
TAi
Addresses
TAj
TAk
(1)
TB2 overflow
(1)
TAj overflow
Timer A0 038716 - 038616
Timer A1 038916 - 038816
Timer A2 038B16 - 038A16
Timer A3 038D16 - 038C16
Timer A4 038F16 - 038E16
Timer A4 Timer A1
Timer A0 Timer A2
Timer A1 Timer A3
Timer A2 Timer A4
Timer A3 Timer A0
To external
trigger circuit
Down count
(j = i – 1. Note, however, that j = 4 when i = 0)
UDF register
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
NOTE:
1. Overflow or underflow
Figure 12.1.1. Timer A Block Diagram
Timer Ai mode register (i=0 to 4)
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Bit symbol
TMOD0
Bit name
Operation mode select bit
Function
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
TMOD1
RW
MR0
MR1
MR2
MR3
TCK0
TCK1
RW
RW
RW
RW
Function varies with each
operation mode
RW
RW
Function varies with each
operation mode
Count source select bit
Figure 12.1.2. TA0MR to TA4MR Registers
page 94
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer Ai register (i= 0 to 4) (1)
Symbol
Address
After reset
(b15)
b7
(b8)
b0 b7
TA0
TA1
TA2
TA3
TA4
038716, 038616
038916, 038816
038B16, 038A16
038D16, 038C16
038F16, 038E16
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b0
Function
RW
RW
Setting range
Mode
Timer
mode
Divide the count source by n + 1 where n =
set value
000016 to FFFF16
Event
counter
mode
Divide the count source by FFFF 16 – n + 1
000016 to FFFF16
RW
WO
where n = set value when counting up or
(5)
by n + 1 when counting down
One-shot
Divide the count source by n where n = set
000016 to FFFF16
(2, 4)
timer mode value and cause the timer to stop
Modify the pulse width as follows:
PWM period: (216 – 1) / fj
High level PWM pulse width: n / fj
Pulse width
modulation
mode
000016 to FFFE16
(3, 4)
WO
WO
(16-bit PWM) where n = set value, fj = count source
frequency
Modify the pulse width as follows:
modulation PWM period: (28 – 1) x (m + 1)/ fj
0016 to FE16
Pulse width
(High-order address)
0016 to FF16
mode
(8-bit PWM)
High level PWM pulse width: (m + 1)n / fj
where n = high-order address set value,
m = low-order address set value, fj =
count source frequency
(Low-order address)
(3, 4)
NOTES:
1. The register must be accessed in 16 bit units.
2.: If the TAi register is set to ‘000016,’ the counter does not work and timer Ai interrupt requests are
not generated either. Furthermore, if “pulse output” is selected, no pulses are output from the
TAiOUT pin.
3. If the TAi register is set to ‘000016,’ the pulse width modulator does not work, the output level on
the TAiOUT pin remains low, and timer Ai interrupt requests are not generated either. The same
applies when the 8 high-order bits of the timer TAi register are set to ‘0016’ while operating as an
8-bit pulse width modulator.
4. Use the MOV instruction to write to the TAi register.
5. The timer counts pulses from an external device or overflows or underflows in other timers.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
After reset
0016
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
0 : Stops counting
RW
RW
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
1 : Starts counting
RW
RW
RW
RW
RW
RW
RW
Up/down flag (1)
Symbol
UDF
Address
038416
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0UD
TA1UD
TA2UD
TA3UD
TA4UD
Bit name
Function
RW
RW
Timer A0 up/down flag
0 : Down count
1 : Up count
RW
RW
RW
RW
Timer A1 up/down flag
Timer A2 up/down flag
Enabled by setting the TAiMR
register’s MR2 bit to “0”
(= switching source in UDF
register) during event counter
mode.
Timer A3 up/down flag
Timer A4 up/down flag
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
Timer A2 two-phase pulse
signal processing select bit
TA2P
TA3P
TA4P
WO
Timer A3 two-phase pulse
signal processing select bit
WO
WO
(2, 3)
Timer A4 two-phase pulse
signal processing select bit
NOTES:
1. Use MOV instruction to write to this register.
2. Make sure the port direction bits for the TA2IN to TA4I
(input mode).
N
and TA2OUT to TA4OUT pins are set to “0”
Figure 12.1.3. TA0 to TA4 Registers, TABSR Register, and UDF Register
page 95
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
One-shot start flag
Symbol
ONSF
Address
038216
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
RW
Bit symbol
Bit name
Function
The timer starts counting by setting
this bit to “1” while the TMOD1 to
TMOD0 bits in the TAiMR register
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
(i = 0 to 4) is set to ‘102’ (= one-
RW
RW
RW
shot timer mode) and the MR2 bit
in the TAiMR register is set to “0”
(=TAiOS bit enabled). When read,
its content is “0”.
0 : Z-phase input disabled
1 : Z-phase input enabled
TAZIE
RW
RW
Z-phase input enable bit
b7 b6
TA0TGL
Timer A0 event/trigger
select bit
(1)
0 0 : Input on TA0IN is selected
(2)
(2)
(2)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
TA0TGH
RW
NOTES:
1. Make sure the PD7_1 bit in the PD7 register is set to “0” (= input mode).
2. Overflow or underflow.
Trigger select register
Symbol
TRGSR
Address
038316
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA1TGL
Bit name
Function
RW
RW
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (1)
(2)
(2)
(2)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
TA1TGH
TA2TGL
RW
RW
b3 b2
Timer A2 event/trigger
select bit
0 0 : Input on TA2IN is selected (1)
0 1 : TB2 overflow is selected (2)
(2)
(2)
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
TA2TGH
TA3TGL
TA3TGH
RW
RW
RW
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (1)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
(2)
(2)
(2)
b7 b6
Timer A4 event/trigger
select bit
TA4TGL
TA4TGH
RW
RW
0 0 : Input on TA4IN is selected (1)
(2)
(2)
(2)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
NOTES:
1. Make sure the port direction bits for the TA1IN to TA4IN pins are set to “0” (= input mode).
2. Overflow or underflow.
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
After reset
0XXXXXXX
2
Bit symbol
Bit name
Nothing is assigned.
When write, set to “0”. When read, their contents are
Function
RW
RW
(b6-b0)
CPSR
indeterminate.
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
Clock prescaler reset flag
(When read, its content is “0”.)
Figure 12.1.4. ONSF Register, TRGSR Register, and CPSRF Register
page 96
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.1.1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 12.1.1.1). Figure 1.2.1.1.1
shows TAiMR register in timer mode.
Table 12.1.1.1. Specifications in Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
•
When the timer underflows, it reloads the reload register contents and continues counting
Divide ratio
1/(n+1) n: set value of TAi register (i= 0 to 4) 000016 to FFFF16
Count start condition
Count stop condition
Set TAiS bit in the TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
I/O port or gate input
I/O port or pulse output
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Gate function
Select function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When not counting, the pin outputs a low.
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
0
0 0
Bit symbol
Bit name
Function
RW
RW
RW
b1 b0
TMOD0
TMOD1
MR0
Operation mode
select bit
0 0 : Timer mode
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output
Pulse output function
select bit
RW
(TAiOUT pin is a pulse output pin)
b4 b3
Gate function select bit
MR1
MR2
0 0 : Gate function not available
}
RW
RW
0 1 :
(TAiIN pin functions as I/O port)
1 0 : Counts while input on the TAi IN pin
is low (1)
1 1 : Counts while input on the TAi IN pin
is high (1)
MR3
RW
RW
Must be set to “0” in timer mode
b7 b6
TCK0
Count source select bit
0 0 : f
0 1 : f
1
8
or f2
TCK1
1 0 : f32
1 1 : fC32
RW
NOTE:
1.The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 12.1.1.1. Timer Ai Mode Register in Timer Mode
page 97
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.1.2. Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 12.1.2.1 lists specifica-
tions in event counter mode (when not processing two-phase pulse signal). Table 12.1.2.2 lists specifica-
tions in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4).
Figure 12.1.2.1 shows TAiMR register in event counter mode (when not processing two-phase pulse
signal). Figure 12.1.2.2 shows TA2MR to TA4MR registers in event counter mode (when processing two-
phase pulse signal with the timers A2, A3 and A4).
Table 12.1.2.1. Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item
Specification
Count source
• External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected
in program)
• Timer B2 overflows or underflows,
timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,
timer Ak (k=i+1, except k=0 if i=4) overflows or underflows
• Up-count or down-count can be selected by external signal or program
• When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Count operation
Divided ratio
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Count start condition
Count stop condition
Set TAiS bit in the TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
I/O port or count source input
I/O port, pulse output, or up/down-count select input
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Free-run count function
Select function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
• Pulse output function
Whenever the timer underflows or underflows, the output polarity of TAiOUT
pin is inverted . When not counting, the pin outputs a low.
page 98
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer Ai mode register (i=0 to 4)
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
0
0 1
RW
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
MR0
RW
RW
Operation mode select bit
0 1 : Event counter mode (1)
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output
Pulse output function
select bit
RW
RW
(TAiOUT pin functions as pulse output pin)
MR1
MR2
Count polarity
select bit (2)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : UDF register
1 : Input signal to TAiOUT pin (3)
RW
RW
RW
MR3
Must be set to “0” in event counter mode
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK1
Can be “0” or “1” when not using two-phase pulse signal
processing
RW
NOTES:
1. During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
2. Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘00 ’ (TAiIN pin input).
2
3. Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port
direction bit for TAiOUT pin must be set to “0” (= input mode).
Figure 12.1.2.1. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
page 99
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 12.1.2.2. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4)
Item
Count source
Count operation
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 4)
• Up-count or down-count can be selected by two-phase pulse signal
• When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divide ratio
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Count start condition
Count stop condition
Set TAiS bit in the TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Two-phase pulse input
Two-phase pulse input
Count value can be read by reading timer A2, A3 or A4 register
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
(Transferred to counter when reloaded next)
(1)
Select function
• Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN
(j=2, 3) pin when input signals on TAjOUT pin is “H”.
TAjOUT
TAjIN
(j=2,3)
Up-
count
Up-
count
Up-
count count
Down- Down- Down-
count count
• Multiply-by-4 processing operation (timer A3 and timer A4)
If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the
input signal on TAkOUT pin is “H”, the timer counts up rising and falling
edges on TAkOUT and TAkIN pins. If the phase relationship is such that
TAkIN pin goes “L” when the input signal on TAkOUT pin is “H”, the timer
counts down rising and falling edges on TAkOUT and TAkIN pins.
TAkOUT
Count down all edges
Count up all edges
TAkIN
(k=3,4)
Count up all edges
Count down all edges
• Counter initialization by Z-phase input (timer A3)
The timer count value is initialized to 0 by Z-phase input.
NOTE:
1. Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to
multiply-by-4 processing operation.
page 100
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer Ai mode register (i=2 to 4)
(When using two-phase pulse signal processing)
Symbol
TA2MR to TA4MR
Address
039816 to 039A16
After reset
0016
b6 b5 b4 b3 b2 b1 b0
0
1 0 0 0 1
RW
Bit symbol
Bit name
Operation mode select bit
Function
0 1 : Event counter mode
b1 b0
TMOD0
TMOD1
RW
RW
MR0
MR1
MR2
To use two-phase pulse signal processing, set this bit to “0”.
RW
RW
RW
RW
RW
To use two-phase pulse signal processing, set this bit to “0”.
To use two-phase pulse signal processing, set this bit to “1”.
MR3
To use two-phase pulse signal processing, set this bit to “0”.
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK0
Two-phase pulse signal
processing operation
select bit (1, 2)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
RW
NOTES:
1. TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, Timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
2. If two-phase pulse signal processing is desired, following register settings are required:
• Set the TAiP bit in the UDF register to “1” (two-phase pulse signal processing function enabled).
• Set the TAiTGH and TAiTGL bits in the TRGSR register to ‘00
2’ (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode).
Figure 12.1.2.2. TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase
pulse signal processing with timer A2, A3 or A4)
page 101
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal process-
_______
ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Counter initialization by Z-phase input is enabled by writing “000016” to the TA3 register and setting
the TAZIE bit in ONSF register to “1” (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-
sen to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width
_______
applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.1.2.1.1
shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
(1)
INT2
(Z phase)
Input equal to or greater than one clock cycle
of count source
m
m+1
1
2
3
4
5
Timer A3
NOTE:
1. This timing diagram is for the case where the POL bit in the INT2IC register is set to “1” (= rising edge).
Figure 12.1.2.1.1. Two-phase Pulse (A phase and B phase) and the Z Phase
page 102
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.1.3. One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.1.3.1.) When the
trigger occurs, the timer starts up and continues operating for a given period. Figure 12.1.3.1 shows the
TAiMR register in one-shot timer mode.
Table 12.1.3.1. Specifications in One-shot Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
•
When the counter reaches 000016, it stops counting after reloading a new value
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
n : set value of TAi register 000016 to FFFF16
Divide ratio
1/n
However, the counter does not work if the divide-by-n value is set to 000016.
TAiS bit in the TABSR register is set to “1” (start counting) and one of the
following triggers occurs.
Count start condition
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• The TAiOS bit in the ONSF register is set to “1” (= timer starts)
• When the counter is reloaded after reaching “000016”
• TAiS bit is set to “0” (= stop counting)
Count stop condition
Interrupt request generation timing When the counter reaches “000016”
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
I/O port or trigger input
I/O port or pulse output
An indeterminate value is read by reading TAi register
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Pulse output function
Select function
The timer outputs a low when not counting and a high when counting.
page 103
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
39616 to 039A16
After reset
0016
0
1
0
Bit symbol
Bit name
RW
RW
RW
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
1 0 : One-shot timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output
RW
(TAiOUT pin functions as a pulse output pin)
(2)
MR1
MR2
0 : Falling edge of input signal to TAiIN pin
1 : Rising edge of input signal to TAi IN pin
External trigger select
bit
(2)
RW
RW
(1)
Trigger select bit
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
MR3
RW
RW
Must be set to “0” in one-shot timer mode
b7 b6
TCK0
Count source select bit
0 0 : f1 or f2
0 1 : f8
TCK1
1 0 : f32
1 1 : fC32
RW
NOTES:
1. Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘002’ (TAiIN pin input).
2. The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 12.1.3.1. TAiMR Register in One-shot Timer Mode
page 104
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.1.4. Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.1.4.1). The counter
functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.1.4.1 shows
TAiMR register in pulse width modulation mode. Figures 12.1.4.2 and 12.1.4.3 show examples of how a
16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates.
Table 12.1.4.1. Specifications in Pulse Width Modulation Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count (operating as an 8-bit or a 16-bit pulse width modulator)
The timer reloads a new value at a rising edge of PWM pulse and continues counting
•
• The timer is not affected by a trigger that occurs during counting
16-bit PWM
• High level width
• Cycle time (2 -1) / fj fixed
n / fj
n : set value of TAi register (i=o to 4)
fj: count source frequency (f1, f2, f8, f32, fC32)
16
8-bit PWM
•
•
High level width n x (m+1) / fj n : set value of TAi register high-order address
Cycle time (2 -1) x (m+1) / fj m : set value of TAi register low-order address
8
Count start condition
• TAiS bit in theTABSR register is set to “1” (= start counting)
• The TAiS bit is set to "1" and external trigger input from the TAiIN pin
• The TAiS bit is set to "1" and one of the following external triggers occurs
Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
TAiS bit is set to “0” (= stop counting)
Count stop condition
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function
TAiOUT pin function
Read from timer
I/O port or trigger input
Pulse output
An indeterminate value is read by reading TAi register
Write to timer
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
page 105
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer Ai mode register (i= 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
1
1
1
Bit symbol
Bit name
Function
RW
RW
RW
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 1 : PWM mode
0: Pulse is not output (TAiOUT pin functions as I/O port)
1: Pulse is output (TAiOUT pin functions as a pulse output
pin)
Pulse output funcion
select bit
MR0
MR1
RW
(2)
(2)
External trigger select
bit (1)
0: Falling edge of input signal to TAiIN pin
1: Rising edge of input signal to TAiIN pin
RW
RW
MR2
MR3
Trigger select bit
0 : Write “1” to TAiS bit in the TASF register
1 : Selected by TAiTGH to TAiTGL bits
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
16/8-bit PWM mode
select bit
RW
RW
RW
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
NOTES:
1. Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘002’ (TAiIN pin input).
2. The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 12.1.4.1. TAiMR Register in Pulse Width Modulation Mode
page 106
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1 / fi X
(2 16 – 1)
Count source
“H”
“L”
Input signal to
TAiIN pin
Trigger is not generated by this signal
1 / f
j
X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
IR bit in the
TAiIC register
fj
: Frequency of count source
(f , f , f , f32, fC32
1
2
8
)
Set to “0” upon accepting an interrupt request or by writing in program
i = 0 to 4
NOTES:
1. n = 000016 to FFFE16
2. This timing diagram is for the case where the TAi register is set to "000316", the TAiTGH and TAiTGL bits in
the ONSF or TRGSR register is set to "00 " (TAiIN pin input), the MR1 bit in the TAiMR register is set to "1"
.
2
(rising edge), and the MR2 bit in the TAiMR register is set to "1" (trigger selected by TAiTGH and TAiTGL bits).
Figure 12.1.4.2. Example of 16-bit Pulse Width Modulator Operation
1 / fj
X (m + 1) X (2 8 – 1)
Count source (1)
“H”
“L”
Input signal to
TAiIN pin
1 / fj X (m + 1)
“H”
“L”
Underflow signal of
8-bit prescaler (2)
1 / fj X (m + 1) X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
IR bit in the
TAiIC register
fj
: Frequency of count source
(f , f , f , f32, fC32
Set to “0” upon accepting an interrupt request or by writing in program
1
2
8
)
i = 0 to 4
NOTES:
1. The 8-bit prescaler counts the count source.
2. The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
3. m = 0016 to FF16; n = 0016 to FE16
4. This timing diagram is for the case where the TAi register is set to "020216", the TAiTGH and TAiTGL bits in the
ONSF or TRGSR register is set to "00 " (TAiIN pin input), the MR1 bit in the TAiMR register is set to "0"(falling
.
2
edge), and the MR2 bit in the TAiMR register is set to "1" (trigger selected by TAiTGH and TAiTGL bits).
Figure 12.1.4.3. Example of 8-bit Pulse Width Modulator Operation
page 107
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.2 Timer B
Note
The TB2IN pin for Timer B2 is not available in 42-pin package.
[Precautions when using Timer B2]
• Event Counter Mode
The external input signals cannot be counted. Set the TCK1 bit in the
TB2MR register to “1” when using the Event Count Mode.
• Pulse Period/Pulse Width Measurement Mode
This mode connot be used.
Figure 12.2.1 shows a block diagram of the timer B. Figures 12.2.2 and 12.2.3 show registers related to the
timer B.
Timer B supports the following four modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0 to
2) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
• A/D trigger mode: The timer starts counting by one trigger until the count value becomes 000016.
This mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A/D
converter to start A/D conversion.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
Reload register
• Timer mode
• Pulse period/, pulse width measuring mode
• A/D trigger mode
f
1
or f
2
8
f
Clock selection
f32
• Event counter
Counter
fC32
Polarity switching,
edge pulse
TABSR register
TBiIN
(i = 0 to 2)
Counter reset circuit
TBi
Can be selected in
onlyevent counter mode
Address
TBj
TBj overflow (1)
(j = i – 1, except j = 2 if i = 0)
Timer B0
Timer B1
Timer B2
039116
039316
039516
-
-
-
039016
039216
039416
Timer B2
Timer B0
Timer B1
NOTE:
1. Overflow or underflow.
Figure 12.2.1. Timer B Block Diagram
page 108
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer Bi mode register (i=0 to 2)
Symbol
Address
After reset
b7 b6 b5 b4 b3 b2 b1 b0
TB0MR to TB2MR 039B16 to 039D16 00XX0000
2
Bit symbol
TMOD0
Function
Bit name
RW
RW
b1 b0
Operation mode select bit
0 0 : Timer mode or A/D trigger mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
TMOD1
RW
MR0
MR1
MR2
RW
RW
Function varies with each operation
mode
RW
(1)
(2)
RO
MR3
TCK0
TCK1
RW
RW
Function varies with each operation
mode
Count source select bit
Figure 12.2.2. TB0MR to TB2MR Registers
page 109
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer Bi register (i=0 to 2)(1)
Symbol
Address
After reset
(b15)
b7
(b8)
b0 b7
TB0
TB1
TB2
039116, 039016 Indeterminate
039316, 039216 Indeterminate
039516, 039416 Indeterminate
b0
Function
Setting range
Mode
RW
RW
Timer mode
Divide the count source by n + 1
where n = set value
000016 to FFFF16
Event counter
mode
Divide the count source by n + 1
where n = set value (2)
000016 to FFFF16
RW
Pulse period
Measures a pulse period or width
modulation mode,
RO
Pulse width
modulation mode
Divide the count source by n + 1 where
n = set value and cause the timer stop
A/D trigger
mode (3)
000016 to FFFF16
RW
NOTES:
1. The register must be accessed in 16 bit units.
2. The timer counts pulses from an external device or overflows or underflows of other timers.
3. When this mode is used combining delayed trigger mode 0, set the larger value than the value of the timer
B0 register to the timer B1 register.
Count start flag
Symbol
TABSR
Address
038016
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0S
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Clock prescaler reset flag
Symbol
CPSRF
Address
038116
After reset
0XXXXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
Bit name
Function
RW
RW
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
(b6-b0)
CPSR
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, the value of this bit is “0”.)
Clock prescaler reset flag
Figure 12.2.3. TB0 to TB2 Registers, TABSR Register, CPSRF Register
page 110
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.2.1 Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 12.2.1.1). Figure 12.2.1.1
shows TBiMR register in timer mode.
Table 12.2.1.1 Specifications in Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1) n: set value of TBi register (i= 0 to 2)
000016 to FFFF16
(1)
Count start condition
Count stop condition
Set TBiS bit to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Read from timer
Write to timer
I/O port
Count value can be read by reading TBi register
•
When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
NOTE:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
Timer Bi mode register (i= 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB0MR to TB2MR
Address
039B16 to 039D16
After reset
00XX00002
0
0
Bit symbol
Bit name
Function
0 0 : Timer mode or A/D trigger mode
RW
RW
RW
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
RW
RW
Has no effect in timer mode
Can be set to “0” or “1”
MR1
TB0MR register
Must be set to “0” in timer mode
MR2
RW
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3
When write in timer mode, set to “0”. When read in timer mode, its
content is indeterminate.
RO
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
1
8
or f2
RW
RW
1 0 : f32
1 1 : fC32
Figure 12.2.1.1 TBiMR Register in Timer Mode
page 111
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.2.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 12.2.2.1) . Figure 12.2.2.1 shows TBiMR register in event counter mode.
Table 12.2.2.1 Specifications in Event Counter Mode
Item
Specification
• External signals input to TBiIN pin (i=0 to 2) (effective edge can be selected
in program)
Count source
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0)
• Down-count
Count operation
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1)
n: set value of TBi register
000016 to FFFF16
(1)
Count start condition
Count stop condition
Set TBiS bit to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Read from timer
Write to timer
Count source input
Count value can be read by reading TBi register
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
NOTE:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
Timer Bi mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
00XX0000
TB0MR to TB2MR 039B16 to 039D16
2
0
1
RW
RW
RW
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode select bit
0 1 : Event counter mode
b3 b2
MR0
Count polarity select
bit (1)
0 0 : Counts external signal's
falling edges
RW
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set
MR1
MR2
RW
RW
TB0MR register
Must be set to “0” in timer mode
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate.
MR3
RO
Has no effect in event counter mode.
Can be set to “0” or “1”.
TCK0
TCK1
RW
0 : Input from TBiIN pin (2)
Event clock select
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0)
RW
NOTES:
1. Effective when the TCK1 bit is set to “0” (input from TBiIN pin). If the TCK1 bit is set to “1” (TBj overflow or underflow), these bits
can be set to “0” or “1”.
2. The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Figure 12.2.2.1 TBiMR Register in Event Counter Mode
page 112
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.2.3 Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 12.2.3.1). Figure 12.2.3.1 shows TBiMR register in pulse period and pulse
width measurement mode. Figure 12.2.3.2 shows the operation timing when measuring a pulse period.
Figure 12.2.3.3 shows the operation timing when measuring a pulse width.
Table 12.2.3.1 Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of mea-
surement pulse. The counter value is set to “000016” to continue counting.
(3)
Count start condition
Count stop condition
Set TBiS (i=0 to 2) bit to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
(1)
Interrupt request generation timing • When an effective edge of measurement pulse is input
• Timer overflow. When an overflow occurs, MR3 bit in the TBiMR register is
set to “1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no over-
flow) by writing to TBiMR register at the next count timing or later after MR3
bit was set to “1”. At this time, make sure TBiS bit is set to “1” (start count-
ing).
TBiIN pin function
Read from timer
Measurement pulse input
(2)
Contents of the reload register (measurement result) can be read by reading TBi register
Write to timer
NOTES:
Value written to TBi register is written to neither reload register nor counter
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.
3. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
Timer Bi mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB0MR to TB2MR
Address
039B16 to 039D16
After reset
00XX00002
1
0
Bit symbol
Bit name
Function
RW
RW
RW
b1 b0
TMOD0
Operation mode
select bit
1 0 : Pulse period / pulse width
measurement mode
TMOD1
MR0
b3 b2
Measurement mode
select bit
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
RW
MR1
MR2
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Must not be set.
RW
RW
TB0MR register
Must be set to “0” in pulse period and pulse width measurement mode
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its content turns out to be
indeterminate.
Timer Bi overflow
flag
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
MR3
RO
(1)
Count source
select bit
TCK0
RW
0 0 : f
0 1 : f
1
8
or f2
1 0 : f32
1 1 : fC32
TCK1
RW
NOTE:
1. This flag is indeterminate after reset. When the TBiS bit is set to "1" (start counting), the MR3 bit is cleared to “0” (no overflow) by writing to the
TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit cannot be set to “1” in a program. The
TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
Figure 12.2.3.1 TBiMR Register in Pulse Period and Pulse Width Measurement Mode
page 113
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Count source
“H”
Measurement pulse
“L”
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(2)
(1)
(1)
Timing at which counter
reaches “000016
”
“1”
“0”
TBiS bit
“1”
“0”
IR bit in the TBiIC
register
Set to “0” upon accepting an interrupt request or by writing in
program
“1”
“0”
MR3 bit in theTBiMR
register
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
i = 0 to 2
NOTES:
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “00
from falling edge to falling edge of the measurement pulse).
2
” (measure the interval
Figure 12.2.3.2 Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
“L”
Transfer
(indeterminate
value)
Transfer
(measured value)
Transfer
(measured
value)
Transfer
(measured value)
Reload register counter
transfer timing
(1)
(1)
(1)
(1)
(2)
Timing at which counter
reaches “000016
”
“1”
“0”
TBiS bit
“1”
“0”
IR bit in the TBiIC
register
Set to “0” upon accepting an interrupt request or by
writing in program
“1”
“0”
MR3 bit in the TBiMR
register
The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.
i = 0 to 2
NOTES:
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “10
2
” (measure the
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of
the measurement pulse).
Figure 12.2.3.3 Operation timing when measuring a pulse width
page 114
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.2.4 A/D Trigger Mode
A/D trigger mode is used as conversion start trigger for A/D converter in simultaneous sample sweep
mode of A/D conversion or delayed trigger mode 0. This mode is used as conversion start trigger of A/D
converter. A/D trigger mode is used in Timer B0 and Timer B1. In this mode, the timer starts counting by
one trigger until the count value becomes 000016. Figure 12.2.4.1 shows the TBiMR register in A/D
trigger mode and figure 12.2.4.2 shows the TB2SC register.
Table 12.2.4.1 A/D Trigger Mode Specifications
Item
Count Source
Count Operation
Specification
f1, f2, f8, f32, and fC32
• Down count
• When the timer underflows, reload register contents are reloaded before
stopping counting
• When a trigger is generated during the count operation, the count is not
affected
Divide Ratio
1/(n+1) n: Setting value of TBi register (i=0,1)
000016-FFFF16
Count Start Condition
When the TBiS (i=0,1) bit in the TABSR register is "1"(count started), TBiEN
(i=0,1) bit in TB2SC register is "1", and the following trigger is generated.
(Selection based on TB2SEL bit in the TB2SC register)
• Timer B2 overflow or underflow
• Underflow of Timer B2 interrupt generation frequency counter setting
• After the count value is 000016 and reload register contents are reloaded
• Set the TBiS bit to "0"(count stopped)
Count Stop Condition
(1)
Interrupt Request
Timer underflows
Generation Timing
TBiIN Pin Function
Read From Timer
I/O port
Count value can be read by reading TBi register
• When writing in the TBi register during count stopped.
Value is written to both reload register and counter
• When writing in the TBi register during count.
Value is written to only reload register (Transfered to counter when reloaded next)
(2)
Write To Timer
NOTES:
1. A/D conversion is started by the timer underflow. For details refer to Section 14. A/D Converter.
2. When using in delayed trigger mode 0, set the larger value than the value of the timer B0 register
to the timer B1 register.
page 115
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer Bi mode register (i= 0 to 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB0MR to TB1MR
Address
039B16 to 039C16
After reset
00XX0000
2
0
0
Bit symbol
Bit name
Function
0 0 : Timer mode or A/D trigger mode
RW
RW
RW
b1 b0
TMOD0
TMOD1
MR0
Operation Mode Select Bit
RW
RW
Invalid in A/D trigger mode
Either "0" or "1" is enabled
MR1
TB0MR register
Set to “0” in A/D trigger mode
MR2
RW
TB1MR register
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3
When write in A/D trigger mode, set to “0”. When read in A/D
trigger mode, its content is indeterminate.
RO
b7 b6
Count Source Select Bit
TCK0
TCK1
0 0 : f
0 1 : f
1
8
or f2
RW
RW
(1)
1 0 : f32
1 1 : fC32
NOTE:
1. When this bit is used in delayed trigger mode 0, set the same count source to the timer B0 and timer B1.
Figure 12.2.4.1 TBiMR Register in A/D Trigger Mode
(1)
Timer B2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2SC
Address
039E16
After reset
X0000000
0
0
2
RW
RW
Bit symbol
PWCOM
Bit name
Function
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 Reload Timing
(2)
Switch Bit
Three-Phase Output Port 0 : Three-phase output forcible cutoff
IVPCR1
SD Control Bit 1
(3, 4, 7)
by SD pin input (high impedance)
disabled
RW
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
Timer B0 Operation Mode 0 : Other than A/D trigger mode
Select Bit 1 : A/D trigger mode (5)
TB0EN
TB1EN
RW
RW
RW
Timer B1 Operation Mode 0 : Other than A/D trigger mode
Select Bit
1 : A/D trigger mode (5)
(6)
TB2SEL Trigger Select Bit
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
Reserved bits
Must set to "0"
RW
(b6-b5)
(b7)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this bit to
"0" (timer B2 underflow).
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5 bit to
"0" (= input mode).
4. Related pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). When a high-level ("H") signal is applied to the SD
pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state.
If a low-level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0).
At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1
bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those
pins is used.
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the
INV02 bit to "1" (three-phase motor control timer function).
7. Refer to 16.6 Digital Debounce function for SD input.
Figure 12.2.4.2 TB2SC Register
page 116
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.3 Three-phase Motor Control Timer Function
Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.3.1 lists the
specifications of the three-phase motor control timer function. Figure 12.3.1 shows the block diagram for
three-phase motor control timer function. Also, the related registers are shown on Figure 12.3.2 to Figure
12.3.8.
Table 12.3.1. Three-phase Motor Control Timer Function Specifications
Item
Specification
___
___
___
Three-phase waveform output pin
Six pins (U, U, V, V, W, W)
_____
(1)
Forced cutoff input
Input “L” to SD pin
Used Timers
Timer A4, A1, A2 (used in the one-shot timer mode)
___
Timer A4: U- and_U__-phase waveform control
Timer A1: V- and V-phase waveform control
___
Timer A2: W- and W-phase waveform control
Timer B2 (used in the timer mode)
Carrier wave cycle control
Dead timer timer (3 eight-bit timer and shared reload register)
Dead time control
Output waveform
Triangular wave modulation, Sawtooth wave modification
Enable to output “H” or “L” for one cycle
Enable to set positive-phase level and negative-phase
level respectively
Carrier wave cycle
Triangular wave modulation: count source x (m+1) x 2
Sawtooth wave modulation: count source x (m+1)
m: Setting value of TB2 register, 0 to 65535
Count source: f1, f2, f8, f32, fC32
Three-phase PWM output width
Triangular wave modulation: count source x n x 2
Sawtooth wave modulation: count source x n
n: Setting value of TA4, TA1 and TA2 register (of TA4,
TA41, TA1, TA11, TA2 and TA21 registers when setting
the INV11 bit to “1”), 1 to 65535
Count source: f1, f2, f8, f32, fC32
Dead time active disable function
Count source x p, or no dead time
p: Setting value of DTT register, 1 to 255
Count source: f1, f2, f1 divided by 2, f2 divided by 2
Eable to select “H” or “L”
Active level
Positive and negative-phase concurrent
Positive and negative-phases concurrent active disable function
Positive and negative-phases concurrent active detect function
For Timer B2 interrupt, select a carrier wave cycle-to-cycle
basis through 15 times carrier wave cycle-to-cycle basis
Interrupt frequency
NOTES:
_____
1. When the INV02 bit in the INVC0 register is set to “1” (three-phase motor control timer function), the SD
_____
function of the P85/SD pin is enabled. At this time, the P85 pin cannot be used as a programmable I/O
_____
_____
port. When the SD function is not used, apply “H” to the P85/SD pin.
_____
2. When the IVPCR1 bit in the TB2SC register is set to “1” (enable three-phase output forced cutoff by SD
_____
pin input), and “L” is applied to the SD pin, the related pins enter high-impedance state regardless of the
functions which are used. When the IVPCR1 bit is set to “0” (disabled three-phase output forced cutoff
_____
_____
by SD pin input) and “L” is applied to the SD pin, the related pins can be selected as a programmable I/
O port and the setting of the port and port direction registers are enable.
Related pins
P72/C___L__K___2_/T___A__1__O__UT/V/RxD1
___
P73/CTS2/RTS2/TA1IN/V/TxD1
P74/TA2OUT/W
____
P75/TA2IN/W
P80/TA4OUT/U
___
P81/TA4IN/U
page 117
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Figure 12.3.1. Three-phase Motor Control Timer Functions Block Diagram
page 118
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Three-phase PWM control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
Address
034816
After reset
0016
Bit symbol
INV00
Bit name
Description
RW
RW
Effective interrupt output
polarity select bit
0: The ICTB2 counter is incremented by
one on the rising edge of the timer A1
reload control signal
1: The ICTB2 counter is incremented by
one on the falling edge of the timer A1
reload control signal
(3)
Effective interrupt output
specification bit
(2, 3)
0: ICTB2 counter incremented by 1 at a
timer B2 underflow
1: Selected by INV00 bit
INV01
RW
RW
(4)
Mode select bit
0: Three-phase motor control timer
function unused
1: Three-phase motor control timer
INV02
INV03
(5)
function
0: Three-phase motor control timer output
disabled (5)
1: Three-phase motor control timer output
(6)
Output control bit
RW
(10)
enabled
Positive and negative
phases concurrent output
disable bit
0: Simultaneous active output enabled
1: Simultaneous active output disabled
INV04
RW
RW
RW
Positive and negative
phases concurrent output
detect flag
0: Not detected yet
1: Already detected
INV05
INV06
INV07
(7)
0: Triangular wave modulation mode
(9)
Modulation mode select
1: Sawtooth wave modulation mode
bit
(8)
Setting this bit to “1” generates a transfer
trigger. If the INV06 bit is “1”, a trigger for
the dead time timer is also generated.
The value of this bit when read is “0”.
Software trigger select bit
RW
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable). Note also that INV00 to INV02,
INV04 and INV06 bits can only be rewritten when timers A1, A2, A4 and B2 are idle.
2. If this bit needs to be set to “1”, set any value in the ICTB2 register before writing to it.
3. Effective when the INV11 bit is set to “1” (three-phase mode 1). If INV11 is set to “0” (three-phase mode 0), the ICTB2
counter is incremented by “1” each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are set.
When setting the INV01 bit to “1”, set the timer A1 count start flag before the first timer B2 underflow.When the INV00 bit is
n
set to “1”, the first interrupt is generated when the timer B2 underflows n-1 times, if n is the value set in the ICTB2 counter.
Subsequent interrupts are generated every n times the timer B2 underflow.
4. Setting the INV02 bit to “1” activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter.
5. When the INV02 bit is set to “1”(theee-phase control timer functions) and the INV03 is set to "0"(three-phase motor control
timer output disabled), U, U, V, V, W and W pins, including pins shared with other output functions, enter a high-impedance
state.
6. The INV03 bit is set to “0” in the following cases:
• When reset
• When positive and negative go active (INV05="1") simultaneously while INV04 bit is set to “1”
• When set to “0” in a program
• When input on the SD pin changes state from “H” to “L” (The INV03 bit cannot be set to “1” when SD input is “L”.) When
both the INV04 and the INV05 bits are set to “1”, the INV03 bit is set to “0”.
7. Can only be set by writing “0” in a program, and cannot be set to “1”.
8. The effects of the INV06 bit are described in the table below.
Item
INV06=0
INV06=1
Mode
Sawtooth wave modulation mode
Transferred every transfer trigger
Triangular wave modulation mode
Transferred only once synchronously
with the transfer trigger after writing to
the IDB0 to IDB1 registers
Timing at which transferred from IDB0 to
IDB1 registers to three-phase output shift
register
Timing at which dead time timer trigger is
generated when INV16 bit is “0”
Synchronous with the falling edge of
timer A1, A2, or A4 one-shot pulse
Synchronous with the transfer
trigger and the falling edge of timer
A1, A2, or A4 one-shot pulse
Has no effect
Effective when INV11 is “1” and INV06
is “0”
INV13 bit
Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when INV10 is “1”
9. If the INV06 bit is “1”, set the INV11 bit to “0” (three-phase mode 0) and set the PWCON bit to “0” (timer B2 reloaded by a
timer B2 underflow).
10. Individual pins can be disabled using PFCR register.
Figure 12.3.2. INVC0 Register
page 119
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Three-phase PWM control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC1
Address
034916
After reset
0
0016
Bit symbol
INV10
Bit name
Description
RW
RW
Timer A1, A2, A4 start
trigger signal select bit
0: Timer B2 underflow
1: Timer B2 underflow and write to the
TB2 register
(2)
Timer A1-1, A2-1, A4-1
0: Three-phase mode 0
1: Three-phase mode 1
(4)
INV11
INV12
RW
RW
control bit
(3)
Dead time timer count
source select bit
0 : f
1 : f
1
1
or f
2
divided by 2 or f
2
divided by 2
0: Timer A1 reload control signal is “0”
1: Timer A1 reload control signal is “1”
Carrier wave detect flag
(5)
INV13
RO
0 : Output waveform “L” active
1 : Output waveform “H” active
INV14
INV15
Output polarity control bit
Dead time invalid bit
RW
RW
0: Dead time timer enabled
1: Dead time timer disabled
Dead time timer trigger
select bit
0: Falling edge of timer A4, A1 or A2
one-shot pulse
1: Rising edge of three-phase output shift
register (U, V or W phase) output
INV16
(b7)
RW
RW
(6)
This bit should be set to “0”
Reserved bit
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable). Note also that this register
can only be rewritten when timers A1, A2, A4 and B2 are idle.
2. A start trigger is generated by writing to the TB2 register only while timer B2 stops.
3. The effects of the INV11 bit are described in the table below.
Item
INV11=0
Three-phase mode 0
INV11=1
Mode
Three-phase mode 1
Used
Effect
TA11, TA21, TA41 registers
INV00 bit, INV01 bit
Not used
Has no effect. ICTB2 counted every time
timer B2 underflows regardless of
whether the INV00 to INV01 bits are set.
Effective when INV11 bit is set to “1”
and INV06 bit is set to “0”
INV13 bit
Has no effect
4. If the INV06 bit is set to “1” (sawtooth wave modulation mode), set this bit to “0” (three-phase mode 0). Also, if the
INV11 bit is “0”, set the PWCON bit to “0” (timer B2 reloaded by a timer B2 underflow).
5. The INV13 bit is effective only when the INV06 bit is set to “0” (triangular wave modulation mode) and the INV11 bit is
set to “1” (three-phase mode 1).
6. If all of the following conditions hold true, set the INV16 bit to “1” (dead time timer triggered by the rising edge of
three-phase output shift register output)• The INV15 bit is set to “0” (dead time timer enabled)• When the INV03 bit is
set to “1” (three-phase motor control timer output enabled), the Dij bit and DiBj bit (i:U, V, or W, j: 0 to 1) have always
different values (the positive-phase and negative-phase always output different levels during the period other than
dead time).
Conversely, if either one of the above conditions holds false, set the INV16 bit to “0” (dead time timer triggered by the
falling edge of one-shot pulse).
Figure 12.3.3. INVC1 Register
page 120
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Three-phase output buffer register(i=0,1) (1)
b7
b5 b4 b3 b2 b1 b0
Symbol
IDB0
Address
034A16
034B16
When reset
00111111
00111111
2
IDB1
2
Bit symbol
DUi
Bit name
Function
RW
RW
Write the output level
U phase output buffer i
U phase output buffer i
V phase output buffer i
V phase output buffer i
W phase output buffer i
W phase output buffer i
0: Active level
1: Inactive level
DUBi
DVi
RW
RW
RW
RW
RW
RO
When read, these bits show the three-phase
output shift register value.
DVBi
DWi
DWBi
Nothing is assigned. When write, set to "0". When read,
these contents are "0".
(b7-b6)
NOTE:
1. The IDB0 and IDB1 register values are transferred to the three-phase shift register by a transfer trigger. The value
written to the IDB0 register aftera transfer trigger represents the output signal of each phase, and the next value written
to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents the output signal of each
phase.
Dead time timer (1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DTT
Address
034C16
When reset
Indeterminate
Function
Setting range
1 to 255
RW
WO
Assuming the set value = n, upon a start trigger the timer starts
counting the count souce selected by the INV12 bit and stops
after counting it n times. The positive or negative phase
whichever is going from an inactive to an active level changes
at the same time the dead time timer stops.
NOTES:
1. Use MOV instruction to write to this register.
2. Effective when the INV15 bit is set to “0” (dead time timer enable). If the INV15 bit is set to “1”, the dead time timer is
disabled and has no effect.
Timer B2 Interrupt Occurrences Frequency Set Counter
b7 b6 b5 b4 b3
b0
Symbol
ICTB2
Address
034D16
After Reset
Indeterminate
RW
WO
Function
Setting Range
1 to 15
If the INV01 bit is "0" (ICTB2 counter counted every
time timer B2 underflows), assuming the set value
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow.
If the INV01 bit is "1" (ICTB2 counter count timing
selected by the INV00 bit), assuming the set value
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow that meets the
(1)
condition selected by the INV00 bit.
Nothing is assigned. When write, set to "0". When read, its content is
indeterminate.
NOTE:
1. Use MOV instruction to write to this register.
If the INV01 bit is set to "1", make sure the TB2S bit also is set to "0" (timer B2 count stopped) when writing to
this register. If the INV01 bit is set to "0", although this register can be written even when the TB2S bit is set to
"1" (timer B2 count start), do not write synchronously with a timer B2 underflow.
Figure 12.3.4. IDB0 Register, IDB1Register, DTT Register, and ICTB2 Register
page 121
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer Ai, Ai-1 register (i=1, 2, 4) (1, 2, 3, 4, 5)
Symbol
Address
After reset
TA1
TA2
TA4
TA11 (6,7)
TA21 (6,7)
TA41 (6,7)
038916-038816
038B16-038A16
038F16-038E16
034316-034216
034516-034416
034716-034616
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
(b15)
b7
(b8)
b0 b7
b0
Function
Setting range
RW
WO
000016 to FFFF16
Assuming the set value = n, upon a start trigger the timer
starts counting the count source and stops after counting
it n times. The positive and negative phases change at
the same time timer A, A2 or A4 stops.
NOTES:
1. The register must be accessed in 16 bit units.
2. When the timer Ai register is set to "000016", the counter does not operate and a timer Ai interrupt does not
occur.
3.Use MOV instruction to write to these registers.
4. If the INV15 bit is "0" (dead time timer enable), the positive or negative phase whichever is going from an
inactive to an active level changes at the same time the dead time timer stops.
5. If the INV11 bit is "0" (three-phase mode 0), the TAi register value is transferred to the reload register by a
timer Ai (i = 1, 2 or 4) start trigger. If the INV11 bit is "1" (three-phase mode 1), the TAi1 register value is
transferred to the reload register by a timer Ai start trigger first and then the TAi register value is transferred
to the reload register by the next timer Ai start trigger. Thereafter, the TAi1 register and TAi register values
are transferred to the reload register alternately.
6. Do not write to TAi1 registers synchronously with a timer B2 underflow In three-phase mode 1.
7. Write to the TAi1 register as follows:
(1) Write a value to the TAi1 register
(2) Wait for one cycle of timer Ai count source.
(3) Write the same value to the TAi1 register again.
Figure 12.3.5. TA1, TA2, TA4, TA11, TA21 and TA41 Registers
page 122
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer B2 Special Mode Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2SC
Address
039E16
After Reset
X0000000
0 0
2
RW
RW
Bit Symbol
PWCON
Bit Name
Timer B2 reload timing
(2)
Function
0: Timer B2 underflow
1: Timer A output at odd-numbered
switch bit
Three-phase output port
SD control bit 1
(3, 4, 7)
0: Three-phase output forcible cutoff by SD pin input
(high impedance) disabled
1: Three-phase output forcible cutoff by SD pin input RW
(high impedance) enabled
IVPCR1
Timer B0 operation mode
select bit
0: Other than A/D trigger mode
RW
TB0EN
TB1EN
1: A/D trigger mode
(5)
Timer B1 operation mode 0: Other than A/D trigger mode
select bit
RW
RW
1: A/D trigger mode
(5)
(6)
TB2SEL Trigger select bit
0: TB2 interrupt
1: Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
Reserved bits
(b6-b5)
Set to 0
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
(b7)
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
2. If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer
B2 underflow).
3. When setting the IVPCR1 bit to 1 (three-phase output forcible cutoff by SD pin input enabled), Set the PD8
mode).
5 bit to 0 (= input
4. Related pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). When a high-level ("H") signal is applied to the SD pin
and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state. If a low-
level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0). At this time,
when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1 bit is set to 1,
pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those pins is used.
5. When this bit is used in delayed trigger mode 0, set bits TB0EN and TB1EN to 1 (A/D trigger mode).
6. When setting the TB2SEL bit to 1 (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), set the INV02
bit to 1 (three-phase motor control timer function).
The effect of SD pin input is below.
1.Case of INV03 = 1(Three-phase motor control timer output enabled)
SD pin inputs(3)
IVPCR1 bit
Status of U/V/W pins
Remarks
1
H
Three-phase PWM output
High impedance(4)
(Three-phase output
forcrible cutoff enable)
Three-phase output
forcrible cutoff
L(1)
H
0
Three-phase PWM output
Input/output port(2)
(Three-phase output
forcrible cutoff disable)
L(1)
NOTES:
1. When "L" is applied to the SD pin, INV03 bit is changed to 0 at the same time.
2. The value of the port register and the port direction register becomes effective.
3. When SD function is not used, set to 0 (Input) in PD85 and pullup to "H" in SD pin from outside.
4. To leave the high-impedance state and restart the three-phase PWM signal output after the three-phase PWM signal
output forced cutoff, set the IVPCR1 bit to 0 after the SD pin input level becomes high (“H”).
2.Case of INV03 = 0(Three-phase motor control timer output disabled)
Status of U/V/W pins
Remarks
IVPCR1 bit
SD pin inputs
Peripheral input/output
or input/output port
1
H
L
(Three-phase output
forcrible cutoff enable)
Three-phase output
forcrible cutoff(1)
High impedance
Peripheral input/output
or input/output port
0
H
L
(Three-phase output
forcrible cutoff disable)
Peripheral input/output
or input/output port
NOTE:
1. The three-phase output forcrible cutoff function becomes effective if the INPCR1 bit is set to 1 (three-phase output
forcrible cutoff function enable) even when the INV03 bit is 0 (three-phase motor control timer output disalbe)
Figure 12.3.6. TB2SC Registers
page 123
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer B2 register (1)
Symbol
TB2
Address
After reset
(b15)
(b8)
b0
039516 to 039416 Indeterminate
b7
b0 b7
Function
Setting range
RW
RW
000016 to FFFF16
Divide the count source by n + 1 where n = set value.
Timer A1, A2 and A4 are started at every occurrence of
underflow.
NOTE:
1. The register must be accessed in 16 bit units.
Trigger select register
b7 b6 b5 b4 b3 b2 b1
b0
Symbol
TRGSR
Address
038316
After reset
0016
Bit name
Function
To use the V-phase output control
circuit, set these bits to “012”(TB2
underflow).
RW
Bit symbol
TA1TGL
Timer A1 event/trigger
select bit
RW
RW
TA1TGH
TA2TGL
Timer A2 event/trigger
select bit
To use the W-phase output control
circuit, set these bits to “012”(TB2
underflow).
RW
RW
RW
RW
TA2TGH
TA3TGL
TA3TGH
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (1)
0 1 : TB2 overflow is selected (2)
1 0 : TA2 overflow is selected (2)
1 1 : TA4 overflow is selected (2)
Timer A4 event/trigger
select bit
TA4TGL
TA4TGH
To use the U-phase output control
circuit, set these bits to “012”(TB2
underflow).
RW
RW
NOTES:
1. Set the corresponding port direction bit to “0” (input mode).
2. Overflow or underflow
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
After reset
0016
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Figure 12.3.7. TB2 Register, TRGSR Register, and TABSR Register
page 124
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Timer Ai mode register
Symbol
TA1MR
TA2MR
TA4MR
Address
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
039716
039816
039A16
0
1 0
0
1
0016
0016
Bit symbol
Bit name
Function
RW
RW
RW
TMOD0
TMOD1
MR0
Must set to “10
2
” (one-shot timer mode) for
the three-phase motor control timer function
Operation mode
select bit
Must set to “0” for the three-phase motor
control timer function
Pulse output function
select bit
MR1
MR2
Has no effect for the three-phase motor
control timer function
External trigger select
bit
RW
RW
Must set to “1” (selected by event/trigger
select register) for the three-phase motor
control timer function
Trigger select bit
MR3
Must set to “0” for the three-phase motor control timer function
RW
RW
b7 b6
TCK0
Count source select bit
0 0 : f
0 1 : f
1
8
or f2
TCK1
1 0 : f32
1 1 : fC32
RW
Timer B2 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2MR
Address
039D16
After reset
00XX0000
0
0 0
2
Bit symbol
Bit name
Function
RW
RW
RW
TMOD0
TMOD1
MR0
Set to “00
2
” (timer mode) for the three-
phase motor control timer function
Operation mode select bit
RW
RW
Has no effect for the three-phase motor control timer function.
When write, set to “0”. When read, its content is indeterminate.
MR1
Must set to “0” for the three-phase motor control timer function
MR2
MR3
RW
RO
When write in three-phase motor control timer function, write “0”.
When read, its content is indeterminate.
b7 b6
Count source select bit
TCK0
TCK1
RW
RW
0 0 : f
0 1 : f
1 0 : f32
1
8
or f2
1 1 : fC32
Figure 12.3.8. TA1MR, TA2MR, TA4MR, and TB2MR Registers
page 125
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
The three-phase motor control timer function is enabled by setting the INV02 bit in the VC0 register to “1”.
When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to
__
___
___
control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated dead-
time timer. Figure 12.3.9 shows the example of triangular modulation waveform, and Figure 12.3.10 shows
the example of sawtooth modulation waveform.
Triangular waveform as a Carrier Wave
Triangular wave
Signal wave
TB2S bit in the
TABSR register
Timer B2
Start trigger signal
for timer A4(1)
p
p
n
n
m
m
Timer A4
one-shot pulse(1)
Rewrite registers IDB0 and IDB1
U phase
output signal (1)
Transfer the values
to the three-phase
output shift register
U phase
output signal (1)
U phase
INV14 = 0
(“L” active)
U phase
U phase
Dead time
INV14 = 1
(“H” active)
Dead time
U phase
INV13
(INV11=1(three-phase
mode 1))
NOTE:
1. Internal signals. See Figure 12.3.1.
The above applies under the following conditions:
INVC0 = 00XX11XX (X varies depending on each system) and INVC1 = 010XXXX02.
2
Examples of PWM output change are:
(2)When INV11 = 0 (three-phase mode 0)
· INV01 = 0, ICTB2 = 116 (the timer B2 interrupt is generated
whenever timer B2 underflows)
(1)When INV11 = 1 (three-phase mode 1)
· INV01 = 0 and ICTB2 = 216 (the timer B2 interrupt is generated
every two times the timer B2 underflows),
· Default value of the timer: TA4 = m. The TA4 register is changed
whenever the timer B2 interrupt is generated.
First time: TA4 = m. Second tim:, TA4 = n.
Third time: TA4 = n. Fourth time: TA4 = p.
Fifth time: TA4 = p.
or INV01 = 1, INV00 = 1, and ICTB2=116 (the timer B2 interrupt is
generated at the falling edge of the timer A1 reload control signal.)
· Default value of the timer: TA41 = m, TA4 = m.
Registers TA4 and TA41 are changed whenever the timer B2
interrupt is generated.
· Default values of registers IDB0 and IDB1:
DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1.
First time, TA41 = n, TA4 = n. Second time, TA41 = p, TA4 = p.
· Default values of registers IDB0 and IDB1:
They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0
when the sixth timer B2 interrupt is generated.
DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1.
They are changed to DU0 = 1, DUB0 = 0, DU1= 1 and DUB1 = 0
when the third timer B2 interrupt is generated.
The value written to registers TA4 and TA41 becomes effective at the rising edge of the timer A1 reload control signal.
Figure 12.3.9. Triangular Wave Modulation Operation
page 126
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Carrier wave: sawtooth waveform
Carrier wave
Signal wave
Timer B2
Start trigger signal
for timer A4*
Timer A4
one-shot pulse*
Rewriting IDB0, IDB1 registers
Transfer to three-phase
output shift register
U phase
output signal *
U phase
output signal *
U phase
U phase
INV14 = 0
(“L” active)
Dead time
Dead time
U phase
U phase
INV14 = 1
(“H” active)
* Internal signals. See the block diagram of the three-phase motor control timer function.
Shown here is a typical waveform for the case where INVC0= 01XX110X2 (X = set as suitable for the
system) and INVC1 = 010XXX00 . An example for changing PWM outputs is shown below.
2
• Initial values of IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1. The register values are
changed to DU0=1, DUB0=0, DU1=1, DUB1=1 a timer B2 interrupt occurs.
Figure 12.3.10. Sawtooth Wave Modulation Operation
page 127
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.3.1 Position-data-retain Function
This function is used to retain the position data synchronously with the three-phase waveform
output.There are three position-data input pins for U, V, and W phases.
A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected
by the retain-trigger polarity select bit(bit 3 of the position-data-retain function control register, at address
034E16). This bit selects the retain trigger to be the falling edge of each positive phase, or the rising edge
of each positive phase.
12.3.1.1 Operation of the Position-data-retain Function
Figure 12.3.1.1.1 shows a usage example of the position-data-retain function (U phase) when the
retain trigger is selected as the falling edge of the positive signal.
(1) At the falling edge of the U-phase waveform ouput, the state at pin IDU is transferred to the U-
phase position data retain bit ( bit2 at address 034E16 ).
(2) Until the next falling edge of the Uphase waveform output,the above value is retained.
1
2
Carrier wave
U-phase waveform output
U-phase waveform output
Pin IDU
PDRU bit in the RDRF register
NOTE:
Transferred
Transferred
Transferred
Transferred
1. The retain trigger is the falling edge of the positive signal.
Figure 12.3.1.1.1 Usage Example of Position-data-retain Function ( U phase )
page 128
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.3.1.2 Position-data-retain Function Control Register
Figure 12.3.1.2.1 shows the structure of the position-data-retain function contol register.
Position-data-retain function control register (1)
b7
b3 b2 b1 b0
Symbol
PDRF
Address
034E16
When reset
XXXX 0000
2
Bit symbol
PDRW
Bit name
Function
RW
RO
Input level at pin IDW is read out.
0: "L" level
W-phase position
data retain bit
1: "H" level
Input level at pin IDV is read out.
0: "L" level
1: "H" level
V-phase position
data retain bit
PDRV
PDRU
PDRT
(b7-b4)
RO
RO
RW
Input level at pin IDU is read out.
0: "L" level
1: "H" level
U-phase position
data retain bit
Retain-trigger
polarity select bit
0: Rising edge of positive phase
1: Falling edge of positive phase
Nothing is assigned. When write, set to "0". When read,
contents are indeterminate.
NOTE:
1. This register is valid only in the three-phase mode.
Figure 12.3.1.2.1. PDRF Register
12.3.1.2.1 W-phase Position Data Retain Bit (PDRW)
This bit is used to retain the input level at pin IDW.
12.3.1.2.2 V-phase Position Data Retain Bit (PDRV)
This bit is used to retain the input level at pin IDV.
12.3.1.2.3 U-phase Position Data Retain Bit (PDRU)
This bit is used to retain the input level at pin IDU.
12.3.1.2.4 Retain-trigger Polarity Select Bit (PDRT)
This bit is used to select the trigger polarity to retain the position data.
When this bit is set to "0", the rising edge of each positive phase selected.
When this bit is set to "1", the falling edge of each pocitive phase selected.
page 129
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
12.3.2 Three-phase/Port Output Switch Function
When the INVC03 bit in the INVC0 register set to “1”(Timer output enabled for three-phase motor control)
and setting the PFCi (i=0 to 5) in the PFCR register to “0”(I/O port), the three-phase PWM output pin (U,
__
__
___
U, V, V, W and W) functions as I/O port. Each bit in the PFCi bits (i=0 to 5) is applicable for each one of
three-phase PWM output pins. Figure 12.3.2.1 shows the example of three-phase/port output switch
function. Figure 12.3.2.2 shows the PFCR register and the three-phase protect control register.
Timer B2
U phase
Functions as port P7
2
V Phase
W phase
Functions as port P7
4
Writing PFCR register(1)
PFC0 bit : "1"
Writing PFCR register(1)
PFC0 bit : "1"
PFC2 bit : "1"
PFC4 bit : "0"
PFC2 bit : "0"
PFC4 bit : "1"
NOTE:
1. A hazard may be generated at the output signal, depending on the output switch timing. Also, do not generate (short) be switching to port output
during the dead time of three-phase output.
Figure 12.3.2.1. Usage Example of Three-phse/Port output switch function
page 130
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
12. Timer
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Port function control register (1)
b7
b5 b4 b3 b2 b1 b0
Symbol
PFCR
Address
035816
When reset
0011 1111
2
Bit symbol
PFC0
Bit name
Function
0: Input/Output port P8
1: Three-phase PWM output
(U phase output)
RW
RW
0
Port P80 output
function select bit
0: Input/Output port P8
1: Three-phase PWM output
(U phase output)
1
Port P8
function select bit
1 output
PFC1
PFC2
PFC3
PFC4
PFC5
(b7-b6)
RW
RW
RW
RW
RW
0: Input/Output port P7
2
Port P72 output
1: Three-phase PWM output
(V phase output)
function select bit
0: Input/Output port P7
3
Port P73 output
1: Three-phase PWM output
(V phase output)
function select bit
0: Input/Output port P7
4
Port P74 output
1: Three-phase PWM output
(W phase output)
function select bit
0: Input/Output port P7
5
Port P75 output
1: Three-phase PWM output
(W phase output)
function select bit
Nothing is assigned. When write, set to "0". When read,
these contents are "0".
NOTE:
1. This register is valid only when the INVC03 bit in the INVC0 register is set to "1"(Three-phase motor
control timer output enabled). Write to this register after setting the TPRC0 bit in the TPRC register to
"1" (write enable).
Three-phase protect control register
b7
b3 b2 b1 b0
Symbol
TPRC
Address
025A16
When Reset
0016
Bit Symbol
TPRC0
Bit Name
Function
RW
RW
Enable write to PFCR register
0: Write protected
1: Write enabled
Three-phase
protect control bit
Nothing is assigned. When write, set to "0". When read,
the contents are "0".
(b7-b1)
Figure 12.3.2.2. PFCR Register, and TPRC Register
page 131
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13. Serial I/O
Note
UART0 is not available in the 42-pin package.
Serial I/O is configured with three channels: UART0 to UART2.
13.1. UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each
other.
Figure 13.1.1 shows the block diagram of UARTi. Figures 13.1.2 and 13.1.3 shows the block diagram of
the UARTi transmit/receive.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
2
•
•
•
•
Special mode 1 (I C bus mode) : UART2
Special mode 2 : UART2
Special mode 3 (Bus collision detection function, IEBus mode) : UART2
Special mode 4 (SIM mode) : UART2
Figures 13.1.4 to 13.1.9 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
page 132
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
PCLK1=0
PCLK1=1
f
2SIO
1SIO
1/2
1/8
f
1SIO or f2SIO
Main clock, PLL clock,
or on-chip oscillator clock
f
f8SIO
f
32SIO
1/4
(UART0)
RxD0
TxD
0
SMD2 to SMD0
UART reception
Clock source selection
CLK1 to CLK0
Receive
clock
1/16
1/16
1/2
Reception
control circuit
Clock synchronous
type
00
01
10
External
2
Transmit/
receive
unit
U0BRG
register
f
1SIO or
f
f
2SIO
8SIO
32SIO
Internal
2
CKDIR=0
CKDIR=1
UART transmission
2
Transmit
clock
f
1 / (n0+1)
Transmission control
circuit
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
Clock synchronous type
CKPOL
CKDIR=1
(when internal clock is selected)
CLK
polarity
reversing
circuit
CLK0
CTS/RTS disabled
CTS/RTS selected
CRS=1
RTS
0
CTS0 / RTS
0
CRS=0
V
CC
CTS/RTS disabled
RCSP=0
RCSP=1
CRD=1
CRD=0
CTS
0
CTS0 from UART1
(UART1)
RxD
1
TxD1
SMD2 to SMD0
UART reception
Clock source selection
CLK1 to CLK0
Receive
clock
1/16
Reception
Clock synchronous
type
control circuit
Transmit/
receive
unit
00
01
10
2
U1BRG
register
f
1SIO or
f
f
2SIO
8SIO
32SIO
Internal
2
CKDIR=0
2
UART transmission
Transmit
clock
f
1/16
1/2
1 / (n1+1)
Transmission
control circuit
Clock synchronous
type
External
CKDIR=1
Clock synchronous type
(when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CKPOL
CKDIR=1
CLK
polarity
reversing
circuit
CLKMD0=0
CLKMD0=1
CLK
1
Clock output
pin select
CLKMD1=1
CTS/RTS selected
CRS=1
CTS/RTS disabled
CTS
1
0
/ RTS
1
/
RTS1
CTS
/ CLKS
1
CLKMD1=0
CRS=0
V
CC
CTS/RTS disabled
CTS1
CTS from UART0
RCSP=0
RCSP=1
CRD=1
CRD=0
0
(UART2)
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD
2
TxD
2
SMD2 to SMD0
UART reception
Clock source selection
CLK1 to CLK0
00
Receive
clock
1/16
1/16
Reception
Clock synchronous
type
control circuit
2
Transmit/
receive
unit
U2BRG
register
f
1SIO or
f
f
2SIO
8SIO
32SIO
01
2
Internal
CKDIR=0
CKDIR=1
UART transmission
102
Transmit
clock
f
1 / (n2+1)
Transmission
control circuit
Clock synchronous
type
External
Clock synchronous type
(when internal clock is selected)
1/2
CKDIR=0
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CKDIR=1
CKPOL
CLK
polarity
reversing
circuit
CLK2
CTS/RTS disabled
CTS/RTS
selected
CRS=1
CRS=0
RTS
2
CTS2 / RTS
2
V
CC
CTS/RTS disabled
CRD=1
CRD=0
CTS
2
i = 0 to 2
: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: Bits in the UiMR
n
i
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in the UiC0 resgister
CLKMD0, CLKMD1, RCSP: Bits in the UCON register
Figure 13.1.1. Block diagram of UARTi (i = 0 to 2)
page 133
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Clock
synchronous type
Clock
synchronous
type
PAR
disabled
UART (7 bits)
UART (8 bits)
UART (7 bits)
0
1SP
UARTi receive register
0
STPS=0
PRYE=0
PRYE=1
0
SP
SP
PAR
RxDi
1
STPS=1
1
1
2SP
UART
SMD2 to SMD0
enabled
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
UARTi receive
buffer register
0
0
0
0
0
0
0
D8
D7 D6 D5
D4 D3 D2
D1 D0
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
UARTiÜtransmit
buffer register
D7 D6 D5
D4 D3 D2
D1 D0
D8
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
UART (8 bits)
UART (9 bits)
SMD2 to SMD0
Clock synchronous
type
UART (9 bits)
1
UART
PRYE=1
1
PAR
1
enabled
STPS=1
STPS=0
2SP
PAR
SP
SP
TxDi
PRYE=0
0
0
0
UARTi transmit register
Clock
synchronous
type
UART (7 bits)
UART (8 bits)
1SP
PAR
disabled
UART (7 bits)
SP: Stop bit
PAR: Parity bit
0
Clock synchronous
type
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bit in the UiMR register
Figure 13.1.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
page 134
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
No reverse
IOPOL=0
RxD data
RxD2
reverse circuit
IOPOL=1
Reverse
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
PAR
disabled
1SP
UART(7 bits)
UARTi receive register
0
0
STPS=0
STPS=1
PRYE=0
PRYE=1
0
PAR
SP
SP
1
1
1
PAR
enabled
2SP
UART
Clock
synchronous type
SMD2 to SMD0
UART
(9 bits)
UART
(8 bits)
UART
(9 bits)
UART2 receive
buffer register
0
0
0
0
0
0
0
D
8
D
7
D
6
D5
D4
D3
D2
D1
D0
Address 037E16
Address 037F16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
UART2 transmit
buffer register
D7
D
6
D5
D
4
D
3
D
2
D1
D0
D
8
Address 037A16
Address 037B16
UART
(8 bits)
UART
(9 bits)
SMD2 to SMD0
UART
Clock
UART
PAR
enabled
synchronous type
(9 bits)
1
1
STPS=1
STPS=0
PRYE=1
PRYE=0
2SP
1
SP
SP
PAR
0
0
0
UART(7 bits)
UARTi transmit register
Clock
UART
(7 bits)
UART
(8 bits)
synchronous
type
PAR
disabled
1SP
0
Clock
synchronous type
Error signal output
disable
No reverse
U2ERE
=0
IOPOL
=0
TxD data
reverse circuit
Error signal
output circuit
TxD2
IOPOL
=1
U2ERE
=1
Reverse
Error signal output
enable
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bit in the U2MR register
U2ERE : Bit in the U2C1 register
Figure 13.1.3. Block diagram of UART2 transmit/receive unit
page 135
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
UARTi Transmit Buffer Register (i=0 to 2)(1)
Symbol
U0TB
U1TB
U2TB
Address
After Reset
(b15)
b7
(b8)
b0 b7
b0
03A316-03A216 Indeterminate
03AB16-03AA16 Indeterminate
037B16-037A16 Indeterminate
Function
RW
WO
Transmit data
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
NOTES:
1. Use MOV instruction to write to this register.
UARTi Receive Buffer Register (i=0 to 2)
(b8)
b0 b7
(b15)
b7
Symbol
U0RB
U1RB
U2RB
Address
03A716-03A616
03AF16-03AE16 Indeterminate
037F16-037E16 Indeterminate
After Reset
Indeterminate
b0
Bit
Symbol
Function
Bit Name
RW
RO
RO
Receive data (D
Receive data (D
7
8
to D0)
(b7-b0)
(b8)
)
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
(b10-b9)
ABT
0 : Not detected
1 : Detected
Arbitration lost detecting
flag (2)
RW
RO
RO
Overrun error flag (1)
0 : No overrun error
1 : Overrun error found
OER
FER
PER
SUM
(1)
Framing error flag
0 : No framing error
1 : Framing error found
(1)
Parity error flag
0 : No parity error
1 : Parity error found
RO
RO
(1)
Error sum flag
0 : No error
1 : Error found
NOTES:
1. When the SMD2 to SMD0 bits in the UiMR register are set to “000
2
” (serial I/O disabled) or the RE bit in the UiC1 register is set to “0” (reception
disabled), all of the SUM, PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER
bits are set to “0” (no error). Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.
2. The ABT bit is set to “0” by setting to “0” by program. (Writing “1” has no effect.)
Nothing is assigned at the bit 11 in the U0RB and U1RB registers. When write, set to "0". When read, its content is "0".
UARTi Baud Rate Generation Register (i=0 to 2)(1, 2, 3)
b7
b0
Symbol
U0BRG
U1BRG
U2BRG
Address
03A116
03A916
037916
After Reset
Indeterminate
Indeterminate
Indeterminate
Function
Setting Range
0016 to FF16
RW
WO
Assuming that set value = n, UiBRG divides the count source
by n + 1
NOTES:
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. Use MOV instruction to write to this register.
The transfer clock is shown below when the setting value in the UiBRG register is set as n.
(1) When the CKDIR bit in the UiMR register to “0” (internal clock)
• Clock synchronous serial I/O mode
: fj/(2(n+1))
• Clock asynchronous serial I/O (UART) mode : fj/(16(n+1))
(2) When the CKDIR bit in the UiMR register to “1” (external clock)
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O (UART) mode : fEXT/(16(n+1))
fj : f1SIO, f2SIO, f8SIO, f32SIO
EXT : Input from CLKi pin
3. Set the UiBRG register after setting the CLK1 and CLK0 bits in the UiC0 registers.
: fEXT
f
Figure 13.1.4. U0TB to U2TB registers, U0RB to U2RB registers, U0BRG to U2BRG registers
page 136
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
UARTi transmit/receive mode register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0MR, U1MR
Address
03A016, 03A816
After reset
0016
Bit
symbol
Function
Bit name
RW
RW
b2 b1 b0
SMD0
Serial I/O mode select bit
(2)
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set value other than the above
SMD1
SMD2
RW
RW
RW
RW
RW
Internal/external clock
select bit
0 : Internal clock
1 : External clock (1)
CKDIR
STPS
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Odd/even parity select bit
PRY
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
(b7)
Parity enable bit
Reserve bit
RW
RW
Write to "0"
NOTES:
1. Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
2. To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
After reset
0016
Bit
symbol
Function
Bit name
RW
RW
b2 b1 b0
SMD0
SMD1
Serial I/O mode select bit
(2)
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
(3)
0 1 0 : I2C bus mode
RW
RW
RW
RW
RW
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
SMD2
Internal/external clock
select bit
0 : Internal clock
1 : External clock (1)
CKDIR
STPS
PRY
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Odd/even parity select bit
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
Parity enable bit
RW
RW
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
IOPOL
NOTES:
1. Set the corresponding port direction bit for each CLK2 pin to “0” (input mode).
2. To receive data, set the corresponding port direction bit for each RxD2 pin to “0” (input mode).
3. Set the corresponding port direction bit for SCL2 and SDA2 pins to “0” (input mode).
Figure 13.1.5. U0MR to U2MR registers
page 137
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
UARTi Transmit/receive Control Rregister 0 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
00001000
U0C0 to U2C0 03A416, 03AC16, 037C16
2
Bit
Symbol
Bit Name
Function
RW
b1 b0
CLK0
BRG count source
select bit
RW
RW
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Do not set
(7)
CLK1
CRS
Effective when CRD is set to "0"
CTS/RTS function
select bit (3)
(1)
RW
RO
0 : CTS function is selected
1 : RTS function is selected
0 : Data in transmit register (during transmission)
1 : No data in transmit register
(transmission completed)
TXEPT Transmit register empty
flag
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
CTS/RTS disable bit
RW
RW
(P60, P64 and P73
can be used as I/O ports)(6)
Data output select bit(5)
0 : TxDi/SDA2 and SCL2 pins are CMOS output
NCH
1 : TxDi/SDA2 and SCL2 pins are N-channel open-drain output(4)
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
CKPOL CLK polarity select bit
RW
RW
UFORM Transfer format select bit
(2)
0 : LSB first
1 : MSB first
NOTES:
1. Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
2. Effective when the SMD2 to SMD0 bits in the UMR register to "001 "(clock synchronous serial I/O mode) or "010
transfer data 8 bits long). Set the UFORM bit to "1" when the SMD2 to SMD0 bits are set to "101
" (I2C bus mode) and "0" when
they are set to"100 " (UART mode transfer data 7 bits long) or "110 " ( UART mode transfer data 9 bits long).
3. CTS /RTS can be used when the CLKMD1 bit in the UCON register is set to “0” (only CLK output) and the RCSP bit in the
UCON register is set to “0” (CTS /RTS not separated).
4. SDA2 and SCL2 are effective when i = 2.
2
2" (UART mode
2
2
2
1
1
1
0
0
5. When the SMD2 to SMD0 bits in UiMR regiser are set to “0002” (serial I/O disable), do not set NCH bit to “1” (TxDi/SDA2 and
SCL2 pins are N-channel open-drain output).
6. When the U1MAP bit in PACR register is “1” (P73 to P70), CTS/RTS pin in UART1 is assigned to P70.
7. When the CLK1 and CLK0 bit settings are changed, set the UiBRG register.
UART Transmit/receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
After Reset
X0000000
2
Bit Symbol
U0IRS
Bit Name
Function
RW
RW
UART0 transmit interrupt 0: Transmit buffer empty (Tl = 1)
cause select bit 1: Transmission completed (TXEPT = 1)
UART1 transmit interrupt 0: Transmit buffer empty (Tl = 1)
U1IRS
RW
cause select bit
1: Transmission completed (TXEPT = 1)
UART0 continuous
receive mode enable bit
0: Continuous receive mode disabled
1: Continuous receive mode enable
U0RRM
U1RRM
RW
RW
UART1 continuous
receive mode enable bit
0: Continuous receive mode disabled
1: Continuous receive mode enabled
Effective when CLKMD1 bit is set to “1”
0: Clock output from CLK1
1: Clock output from CLKS1
UART1 CLK/CLKS
select bit 0
CLKMD0
CLKMD1
RW
RW
RW
0: Output from CLK1 only
1: Transfer clock output from multiple
pins function selected
UART1 CLK/CLKS
select bit 1 (1)
0: CTS/RTS shared pin
Separate UART0
CTS/RTS bit
RCSP
(b7)
1: CTS/RTS separated (CTS
from the P6 pin)(2)
0 supplied
4
Nothing is assigned. When write, set to “0”.
When read, the content is indeterminate
NOTES:
1. To use more than one transfer clock output pins, set the CKDIR bit in the U1MR register to “0” (internal clock).
2. When the U1MAP bit in PACR register is set to “1” (P7 to P7 ), CTS is supplied from the P7 pin.
3
0
0
0
Figure 13.1.6. U0C0 to U2C0 registers and UCON register
page 138
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
UARTi Transmit/receive Control Register 1 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0C1, U1C1
Address
03A516,03AD16
After Reset
00000010
2
Bit
Symbol
Function
Bit Name
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
RO
TI
Transmit buffer
empty flag
0 : Data in UiTB register
1 : No data in UiTB register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RO
Receive complete flag
0 : No data in UiRB register
1 : Data in UiRB register
Nothing is assigned.
When write, set “0”. When read, the contents are “0”.
(b7-b4)
UART2 Transmit/receive Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C1
Address
037D16
After Reset
00000010
2
Bit
Symbol
Function
Bit Name
RW
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
Transmit buffer
empty flag
0 : Data in U2TB register
1 : No data in U2TB register
TI
RO
RW
RO
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data in U2RB register
1 : Data in U2RB register
U2IRS UART2 transmit interrupt 0 : Transmit buffer empty (TI = 1)
RW
RW
cause select bit
1 : Transmit is completed (TXEPT = 1)
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
U2RRM UART2 continuous
receive mode enable bit
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
RW
RW
U2ERE Error signal output
enable bit
0 : Output disabled
1 : Output enabled
Pin Assignment Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbpl
PACR
Address
025D16
After Reset
0016
Bit Symbol
Bit Name
Function
RW
Pin enabling bit
PACR0
PACR1
PACR2
001 : 42 pin
100 : 48 pin
All other values are reserved. Do
not use.
RW
RW
RW
Reserved bits
Nothing is assigned. When write,
set to “0”. When read, its
content is “0”.
(b6-b3)
U1MAP
UART1 pins assigned to
UART1 pin remapping bit
RW
0 : P6
1 : P7
7
3
to P6
to P7
4
0
NOTES:
1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to "1"(write
enable).
Figure 13.1.7. U0C1 to U2C1 registers, PACR register
page 139
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
UART2 Special Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
037716
After Reset
X0000000
0
2
Bit
Symbol
Function
RW
Bit Name
0 : Other than I2C bus mode
1 : I2C bus mode
IICM
ABC
I2C bus mode select bit
RW
RW
Arbitration lost detecting
flag control bit
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
RW
(1)
BBS
Bus busy flag
Set to “0”
Reserved bit
RW
RW
(b3)
Bus collision detect
0 : Rising edge of transfer clock
sampling clock select bit 1 : Underflow signal of timer A0
ABSCS
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
ACSE
RW
RW
0 : Not synchronized to R
XDi
Transmit start condition
select bit
SSS
(b7)
1 : Synchronized to R
X
Di (2)
Nothing is assigned. When write, set “0”.
When read, its content is indeterminate.
NOTES:
1: The BBS bit is set to “0” by writing “0" by program. (Writing “1” has no effect).
2: When a transfer begins, the SSS bit is set to “0” (Not synchronized to RXDi).
UART2 Special Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
037616
After Reset
X0000000
2
Bit
Symbol
Bit Name
I C bus mode select bit 2 Refer to Table 13.12
Function
RW
RW
2
IICM2
CSC
SWC
ALS
Clock-synchronous bit
0 : Disabled
1 : Enabled
RW
RW
SCL
2
wait output bit
output stop bit
0 : Disabled
1 : Enabled
SDA
2
0 : Disabled
1 : Enabled
RW
RW
UART initialization bit
0 : Disabled
1 : Enabled
STAC
SWC2
SCL
2
wait output bit 2
output disable bit
0: Transfer clock
1: “L” output
RW
RW
0: Enabled
1: Disabled (high impedance)
SDA
2
SDHI
(b7)
Nothing is assigned. When write, set “0”.
When read, its content is indeterminate.
Figure 13.1.8. U2SMR register and U2SMR2 register
page 140
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
UART2 special mode register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
037516
After reset
000X0X0X
2
Bit
symbol
Bit name
Function
RW
Nothing is assigned.
(b0)
When write, set “0”. When read, its content is indeterminate.
CKPH
Clock phase set bit
0 : Without clock delay
1 : With clock delay
RW
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b2)
NODC Clock output select bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b4)
DL0
b7 b6 b5
SDA digital delay
setup bit (1, 2)
RW
RW
RW
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
DL1
DL2
NOTES:
1. The DL2 to DL0 bits are used to generate a delay in SDA2 output by digital means during I2C bus mode. In other than
I2C bus mode, set these bits to “000
” (no delay).
2
2. The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
UART2 Special Mode Register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
037416
After Reset
0016
U2SMR4
Function
Bit Symbol
STAREQ
Bit Name
RW
RW
Start condition
generate bit (1)
0: Clear
1: Start
Restart condition
generate bit (1)
0: Clear
1: Start
RSTAREQ
STPREQ
RW
RW
RW
RW
0: Clear
1: Start
Stop condition
0: Start and stop conditions not output
1: Start and stop conditions output
STSPSEL SCL
2
, SDA
ACK data bit
ACK data output
2 output
0: ACK
1: NACK
ACKD
0: Serial I/O data output
1: ACK data output
ACKC
SCLHI
SWC9
RW
RW
RW
0: Disabled
1: Enabled
SCL
SCL
2
2
output stop
wait bit 3
0: SCL
1: SCL
2
2
“L” hold disabled
“L” hold enabled
NOTE:
1. Set to “0” when each condition is generated.
Figure 13.1.9. U2SMR3 register and U2SMR4 register
page 141
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.1. Clock Synchronous serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 13.1.1.1
lists the specifications of the clock synchronous serial I/O mode. Table 13.1.1.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
Table 13.1.1.1. Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• The CKDIR bit in the UiMR(i=0 to 2) register is set to “0” (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
0016 to FF16
• The CKDIR bit is set to “1” (external clock ) : Input from CLKi pin
_______
_______
Transmission, reception control
Transmission start condition
• Selectable from CTS function, _R__T__S__ function or C___T__S__/RTS function disable
• Before transmission can start, the following requirements must be met (1)
_ The TE bit in the UiC1 register is set to "1" (transmission enabled)
_ The TI bit in the UiC1 register is set to "0" (data present in UiTB register)
_______
_______
_ If CTS function is selected, input on the CTSi pin is “L”
• Before reception can start, the following requirements must be met (1)
_ The RE bit in the UiC1 register is set to "1" (reception enabled)
_ The TE bit in the UiC1 register is set to "1" (transmission enabled)
_ The TI bit in the UiC1 register is set to "0" (data present in the UiTB register)
• For transmission, one of the following conditions can be selected
_ The UiIRS bit (3) is set to "0" (transmit buffer empty): when transferring data
from the UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending
data from the UARTi transmit register
Reception start condition
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
Select function
• Overrun error (2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic (UART2)
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
_______
• Separate CTS/_R__T__S__ pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
• UART1 pin remapping selection
The UART1 pin can be selected from the P67 to P64 or P73 to P70.
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the CKPOL bit in the UiC0 register “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
unchanged.
3. The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
page 142
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 13.1.1. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
UiTB(3)
UiRB(3)
Bit
0 to 7
Function
Set transmission data
0 to 7
Reception data can be read
Overrun error flag
OER
UiBRG
0 to 7
Set a transfer rate
UiMR(3)
SMD2 to SMD0
CKDIR
IOPOL(i=2)(4)
CLK1 to CLK0
CRS
Set to “0012”
Select the internal clock or external clock
Set to “0”
UiC0
Select the count source for the UiBRG register
_______
_______
Select CTS or RTS to use
TXEPT
CRD
Transmit register empty flag
_______
_______
Enable or disable the CTS or RTS function
Select TxDi pin output mode
NCH
CKPOL
UFORM
TE
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to “1” to enable transmission/reception
Transmit buffer empty flag
UiC1
TI
RE
Set this bit to “1” to enable reception
Reception complete flag
RI
U2IRS (1)
U2RRM (1)
U2LCH(3)
U2ERE(3)
0 to 7
Select the source of UART2 transmit interrupt
Set this bit to “1” to use UART2 continuous receive mode
Set this bit to “1” to use UART2 inverted data logic
Set to “0”
U2SMR
Set to “0”
U2SMR2
U2SMR3
0 to 7
Set to “0”
0 to 2
Set to “0”
NODC
Select clock output mode
4 to 7
Set to “0”
U2SMR4
UCON
0 to 7
Set to “0”
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
Select the source of UART0/UART1 transmit interrupt
Set this bit to “1” to use continuous receive mode
Select the transfer clock output pin when CLKMD1 = 1
Set this bit to “1” to output UART1 transfer clock from two pins
Set this bit to “1” to accept as input the UART0 _C__T__S____
0 signal from the P64 pin or P70 pin
7
Set to “0”
NOTES:
1. Set bit 4 and bit 5 in the U0C1 and U1C1 register are set to “0”. The U0IRS, U1IRS, U0RRM and U1RRM
bits are in the UCON register.
2. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock synchro-
nous serial I/O mode.
3. Set the bit 6 and bit 7 in the U0C1 and U1C1 register to "0".
4. Set the bit 7 in the U0MR and U1MR register to "0".
i=0 to 2
page 143
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 13.1.1.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
13.3 shows pin functions for the case where the multiple transfer clock output pin select function is dese-
lected. Table 13.1.1.4 lists the P64 pin functions during clock synchronous serial I/O mode.
Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi
pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)
(1)
Table 13.1.1.3. Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name
Function
Method of selection
TxDi (i = 0 to 2)
Serial data output
(Outputs dummy data when performing reception only)
(P6
3, P6
7, P7
6, P7
5, P7
0
1
2
)
)
)
RxDi
Serial data input
Set the PD6_2 bit and PD6_6 bit in the PD6 register, and PD7_1 bit in the PD7
register to "0"(Can be used as an input port when performing transmission only)
(P6 , P6
2
CLKi
(P6 , P6
Transfer clock output
Transfer clock input
Set the CKDIR bit in the UiMR register to "0"
1
Set the CKDIR bit in the UiMR register to "1"
Set the PD6_1 bit and PD6_5 bit in the PD6 register, and the PD7_2 bit in the
PD7 register to "0"
CTSi/RTSi
(P6 , P6 , P7
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "0"
CTS input
0
4
3
)
Set the PD6_0 bit and PD6_4 bit in the PD6 register’ is set to "0", the PD7_3
bit in the PD7 register to "0"
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "1"
RTS output
I/O port
Set the CRD bit in the UiC0 register to "1"
NOTE:
1. When the U1MAP bit in PACR register is “1” (P73 to P70), UART1 pin is assgined to P73 to P70.
(1)
Table 13.1.1.4. P64 Pin Functions
Pin function
Bit set value
U1C0 register
UCON register
PD6 register
PD6_4
CLKMD1 CLKMD0
0
RCSP
0
CRS
CRD
1
P6
4
Input: 0, Output: 1
0
0
0
0
1
0
0
0
1
0
0
0
0
CTS
RTS
CTS
1
1
0
(2)
0
1(3)
1
CLKS
1
NOTES:
1. When the U1MAP bit in PACR register is “1” (P7
2. In addition to this, set the CRD bit in the U0C0 register to “0” (CT0
U0C0 register to “1” (RTS selected).
3
to P7
0
), this table lists the P7
0 functions.
0
/RT0 enabled) and theCRS bit in the
0
0
3. When the CLKMD1 bit is set to "1" and the CLKMD0 bit is set to "0", the following logiclevels are output:
• High if the CLKPOL bit in the U1C0 register is set to "0"
• Low if the CLKPOL bit in the U1C0 register is set to "1"
page 144
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1) Example of Transmit Timing (Internal clock is selected)
Tc
Transfer clock
“1”
UiC1 register
“0”
“1”
“0”
“H”
Write data to the UiTB register
TE bit
UiC1 register
TI bit
Transferred from UiTB register to UARTi transmit register
CTSi
CLKi
TCLK
“L”
Stopped pulsing because CTSi = “H”
Stopped pulsing because the TE bit = “0”
TxDi
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
“1”
“0”
UiC0 register
TXEPT bit
“1”
“0”
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO
)
n: value set to UiBRG register
i: 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
• The CKDIR bit in the UiMR register is set to "0" (internal clock)
• The CRD bit in the UiC0 register is set to "0" (CTS/RTS enabled); CRS bit is set to "0" (CTS selected)
• The CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling edge and receive data taken in at the rising edge of the
transfer clock)
• The UiIRS bit is set to "0" (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the bit 0 in the UCON register
U1IRS bit is the bit 1 in the UCON register, and U2IRS bit is the bit 4 in the U2C1 register.
(2) Example of Receive Timing (External clock is selected)
“1”
UiC1 register
RE bit
“0”
“1”
UiC1 register
TE bit
“0”
“1”
“0”
“H”
Write dummy data to UiTB register
UiC1 register
TI bit
Transferred from UiTB register to UARTi transmit register
Even if the reception is completed, the RTS
does not change. The RTS becomes “L”
when the RI bit changes to “0” from “1”.
RTSi
CLKi
RxDi
“L”
1 / fEXT
Receive data is taken in
D0
D1
D2
D3
D
4
D5
D
6
D
0
D1
D2
D4
D5
D7
D3
Transferred from UARTi receive register
to UiRB register
Read out from UiRB register
“1”
“0”
UiC1 register
RI bit
“1”
“0”
SiRIC register
IR bit
Cleared to “0” when interrupt request is
accepted, or cleared to “0” by program
The above timing diagram applies to the case where the register bits are set
as follows:
• The CKDIR bit in the UiMR register is set to "1" (external clock)
• The CRD bit in the UiC0 register is set to "0"(CTS/RTS enabled);
The CRS bit is set to "1" (RTS selected)
• UiC0 register CKPOL bit is set to "0"(transmit data output at the falling edge and
receive data taken in at the rising edge of the transfer clock)
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
• UiC0 register TE bit is set to "1" (transmit enabled)
• UiC0 register RE bit is set to "1" (Receive enabled)
• Write dummy data to the UiTB register
fEXT: frequency of external clock
Figure 13.1.1.1. Typical transmit/receive timings in clock synchronous serial I/O mode
page 145
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.1.1 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
•Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “0002” (Serial I/O disabled)
(3) Set the SMD2 to SMD0 bits in the UiMR register to “0012” (Clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to “1” (reception enabled)
•Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register to “0002” (Serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “0012” (Clock synchronous serial I/O mode)
(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless to the TE bit in the UiC1
register.
13.1.1.2 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 13.1.1.2.1
shows the polarity of the transfer clock.
(1) When the CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLK
i
i
(2)
D0
D
1
D
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
TXD
D
0
D
1
D2
D
D
D
D
D
RXDi
(2) When the CKPOL bit in the UiC0 register is set to "1" (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
CLK
i
(3)
D
D
0
0
D
1
D
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
TXD
i
D
1
D2
D
D
D
D
D
RXDi
NOTES:
1. This applies to the case where the UFORM bit in the UiC0 register is set to "0" (LSB first) and the
UiLCH bit in the UiC1 register is set to "0" (no reverse).
2. When not transferring, the CLKi pin outputs a high signal.
3. When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 13.1.1.2.1. Polarity of transfer clock
page 146
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.1.3 LSB First/MSB First Select Function
Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 13.1.1.3.1
shows the transfer format.
(1) When the UFORM bit in the UiC0 register "0" (LSB first)
CLK
i
D0
D
1
D
2
D
3
D
4
D
5
5
D
6
D7
TXDi
D
1
D
2
D
3
D4
D
D
6
D7
D0
RXDi
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
CLK
i
D
7
7
D
6
D
5
D
4
D
3
D
2
2
D
1
D0
TXDi
D
6
D
5
D
4
D3
D
D
1
D0
D
RXDi
NOTE:
1. This applies to the case where the CKPOL bit in the UiC0 register is set to "0" (transmit
data output at the falling edge and the receive data taken in at the rising edge of the
transfer clock) and the UiLCH bit in the UiC1 register "0" (no reverse).
i = 0 to 2
Figure 13.1.1.3.1 Transfer format
13.1.1.4 Continuous receive mode
When the UiRRM bit (i = 0 to 2) is set to "1" (continuous receive mode), the TI bit in the UiC1 register
is set to “0” (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM
bit is set to "1", do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM
bits are the bit 2 and bit 3 in the UCON register, respectively, and the U2RRM bit is the bit 5 in the
U2C1 register.
page 147
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.1.5 Serial data logic switch function (UART2)
When the U2LCH bit in the U2C1 register is set to "1" (reverse), the data written to the U2TB register
has its logic reversed before being transmitted. Similarly, the received data has its logic reversed
when read from the U2RB register. Figure 13.1.1.4.1 shows serial data logic.
(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)
“H”
Transfer clock
“L”
“H”
TxD2
(no reverse)
D0
D1
D2
D3
D4
D5
D6
D7
“L”
(2) When the U2LCH bit in the U2C1 register is set to "1" (reverse)
“H”
Transfer clock
“L”
“H”
TxD2
(reverse)
D0
D1
D2
D3
D4
D5
D6
D7
“L”
NOTE:
1. This applies to the case where the CKPOL bit in the U2C0 register is set to "0"
(transmit data output at the falling edge and the receive data taken in at the rising
edge of the transfer clock) and the UFORM bit is set to "0" (LSB first).
Figure 13.1.1.4.1. Serial data logic switch timing
13.1.1.6 Transfer clock output from multiple pins function (UART1)
The CLKMD1 to CLKMD0 bits in the UCON register can choose one from two transfer clock output
pins. (See Figure 13.1.1.6.1) This function is valid when the internal clock is selected for UART1.
Microcomputer
T
X
D
1
(P6
7)
CLKS
CLK
1
1
(P6
(P6
4
)
)
5
IN
IN
CLK
CLK
Transfer enabled
when the CLKMD0
bit in the UCON
Transfer enabled
when the CLKMD0
bit in the UCON
register is set to "0"
register is set to "1"
NOTES:
1. This applies to the case where the CKDIR bit in the U1MRregister is set to "0" (internal clock) and
the CLKMD1 bit in the UCON register is set to "1" (transfer clock output from multiple pins).
2. This applies to the case where U1MAP bit in PACR register is set to “0” (P67 to P64).
Figure 13.1.1.6.1 Transfer Clock Output From Multiple Pins
page 148
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
_______ _______
13.1.1.7 CTS/RTS separate function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• The CRD bit in the U0C0 register is set to "0" (enables UART0 CTS/RTS)
_______
• The CRS bit in the U0C0 register is set to "1" (outputs UART0 RTS)
_______ _______
• The CRD bit in the U1C0 register is set to "0" (enables UART1 CTS/RTS)
_______
• The CRS bit in the U1C0 register is set to "0" (inputs UART1 CTS)
_______
• The RCSP bit in the UCON register is set to "1" (inputs CTS0 from the P64 pin)
• The CLKMD1 bit in the UCON register is set to "0" (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
IC
Microcomputer
TXD0 (P63)
IN
R
X
D0
(P62)
OUT
CLK
0
(P61
)
CLK
CTS
RTS
RTS
CTS
0
(P6
0)
0
(P64)
NOTE:
1. This applies to the case where U1MAP bit in PACR register is set to “0” (P67 to P64).
Figure 13.1.1.7.1. CTS/RTS separate function usage
page 149
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.2. Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 13.1.2.1 lists the specifications of the UART mode.
Table 13.1.2.1. UART Mode Specifications
Item
Specification
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
Transfer data format
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
Transfer clock
• The CKDIR bit in the UiMR(i=0 to 2) register is set to "0" (internal clock) : fj/(16(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
• CKDIR bit is set to “1” (external clock ) : fEXT/(16(n+1))
fEXT: Input from CLKi pin. n :Setting value of UiBRG register
0016 to FF16
0016 to FF16
Transmission, reception control • Selectable from CTS function, _R__T__S__ function or _C__T__S__/RTS function disable
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit in the UiC1 register is set to "1" (transmission enabled)
_______
_______
_ The TI bit in the UiC1 register "0" (data present in UiTB register)
_______
_______
_ If CTS function is selected, input “L” to the CTSi pin
• Before reception can start, the following requirements must be met
_ The RE bit in the UiC1 register is set to "1" (reception enabled)
_ Start bit detection
Reception start condition
• For transmission, one of the following conditions can be selected
_ The UiIRS bit (2) is set to "0" (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending
the UARTi transmit register
Interrupt request
generation timing
data from
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
• Overrun error (1)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch (UART2)
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch (UART2)
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
• Separate _C__T__S__/R___T__S__ pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
• UART1 pin remapping selection
The UART1 pin can be selected from the P67 to P64 or P73 to P70.
NOTES:
1. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
unchanged.
2. The U0IRS and U1IRS bits respectively are the bits "0" and "1" in the UCON register; the U2IRS bit is the bit 4 in
the U2C1 register.
page 150
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 13.1.2.2. Registers to Be Used and Settings in UART Mode
Register
UiTB
Bit
0 to 8
0 to 8
OER,FER,PER,SUM Error flag
Function
Set transmission data (1)
Reception data can be read (1)
UiRB
UiBRG
UiMR
0 to 7
Set a transfer rate
SMD2 to SMD0
Set these bits to ‘1002’ when transfer data is 7 bits long
Set these bits to ‘1012’ when transfer data is 8 bits long
Set these bits to ‘1102’ when transfer data is 9 bits long
Select the internal clock or external clock
CKDIR
STPS
Select the stop bit
PRY, PRYE
IOPOL(i=2)(4)
CLK0, CLK1
CRS
Select whether parity is included and whether odd or even
Select the TxD/RxD input/output polarity
UiC0
Select the count source for the UiBRG register
_______
_______
Select CTS or RTS to use
TXEPT
Transmit register empty flag
_______
_______
CRD
Enable or disable the CTS or RTS function
Select TxDi pin output mode
Set to “0”
NCH
CKPOL
UFORM
LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
bit to “0” when transfer data is 7 or 9 bits long.
UiC1
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS (2)
U2RRM (2)
U2LCH (3)
U2ERE (3)
0 to 7
Select the source of UART2 transmit interrupt
Set to “0”
Set this bit to “1” to use UART2 inverted data logic
Set to “0”
U2SMR
U2SMR2
U2SMR3
U2SMR4
UCON
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Set this bit to “1” to accept as input the UART0 _C__T__S____
0 signal from the P64 pin or P70 pin
7
Set to “0”
NOTES:
1. The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to
bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
2. Set the bit 4 to bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are included in the UCON register.
3. Set the bit 6 to bit 7 in the U0C1 and U1C1 registers to “0”.
4. Set the bit 7 the U0MR and U1MR registers to “0”.
i=0 to 2
page 151
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 13.1.2.3 lists the functions of the input/output pins during UART mode. Table 13.1.2.4 lists the P64
pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected
to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this
pin is in a high-impedance state.)
(1)
Table 13.1.2.3. I/O Pin Functions in UART mode
Pin name
Function
Method of selection
(Outputs "H" when performing reception only)
TxDi (i = 0 to 2)
Serial data output
(P6
3
, P6
7, P7
6, P7
5, P7
0
1
2
)
)
)
RxDi
(P6 , P6
Serial data input
PD6_2 bit, PD6_6 bit in the PD6 register and the PD7_1 bit in the PD7 register
(Can be used as an input port when performing transmission only)
2
CLKi
(P6 , P6
Input/output port
Set the CKDIR bit in the UiMR register to "0"
1
Set the CKDIR bit in the UiMR register to "1"
Set the PD6_1 bit and PD6_5 bit in the PD6 register to "0", PD7_2 bit in the PD7
register to "0"
Transfer clock input
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "0"
Set the PD6_0 bit and PD6_4 bit in the PD6 register to "0", the PD7_3 bit in the
PD7 register "0"
CTS input
CTSi/RTSi
(P6 , P6 , P7
0
4
3
)
RTS output
Set the CRD bit in the UiC0 register to "0"
Set the CRS bit in the UiC0 register to "1"
Input/output port
Set the CRD bit in the UiC0 register "1"
NOTE:
1. When the U1MAP bit in PACR register is set to “1” (P7
3
to P7
0
), UART1 pin is assgined to P73 to P70.
(1)
Table 13.1.2.4. P64 Pin Functions in UART mode
Pin function
Bit set value
U1C0 register
UCON register
PD6 register
PD6_4
CLKMD1
RCSP
CRS
CRD
P6
4
1
0
0
0
0
0
Input: 0, Output: 1
0
CTS
RTS
CTS
1
1
0
0
1
0
0
0
1
0
0
0
(2)
0
NOTES:
1. When the U1MAP bit in PACR register is “1” (P7
2. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS
register to “1” (RTS selected).
3
to P7
0
), this table lists the P7
0 functions.
0
/RTS enabled) and the CRS bit in the U0C0
0
0
page 152
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
Tc
Transfer clock
UiC1 register
“1”
TE bit
“0”
Write data to the UiTB register
UiC1 register
“1”
“0”
TI bit
Transferred from UiTB register to UARTi transmit register
“H”
“L”
CTSi
TxDi
Stopped pulsing
because the TE bit
= “0”
Start
bit
Parity Stop
bit bit
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D
7
P
SP
ST
D
0
D1
D2
D3
D4
D5
D7
P
SP
D6
D6
UiC0 register
TXEPT bit
“1”
“0”
“1”
“0”
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• Set the PRYE bit in the UiMR register to "1" (parity enabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTS/RTS enabled),
the CRS bit to "0" (CTS selected)
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO
EXT : frequency of UiBRG count source (external clock)
)
f
n : value set to UiBRG
i: 0 to 2
• Set the UiIRS bit to "1" (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
UiC1 register
Write data to the UiTB register
TE bit
“0”
“1”
UiC1 register
TI bit
“0”
Transferred from UiTB register to UARTi
transmit register
Start
bit
Stop Stop
bit bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
D8
SPSP ST
D0
D1
D2
D3
D4
D5
D7
D
8
SPSP
D6
D6
“1”
“0”
UiC0 register
TXEPT bit
“1”
“0”
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO
EXT : frequency of UiBRG count source (external clock)
The above timing diagram applies to the case where the register bits are set
as follows:
• Set the PRYE bit in the UiMR register to "0" (parity disabled)
• Set the STPS bit in the UiMR register to "1" (2 stop bits)
• Set the CRD bit in the UiC0 register to "1"(CTS/RTS disabled)
)
f
n : value set to UiBRG
i: 0 to 2
• Set the UiIRS bit to "0" (an interrupt request occurs when transmit buffer
becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Figure 13.1.2.1. Typical transmit timing in UART mode (UART0, UART1)
page 153
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
“1”
“0”
UiC1 register
RE bit
Stop bit
Start bit
Sampled “L”
D1
D7
RxDi
D0
Receive data taken in
Transfer clock
Read out from
UiRB register
Reception triggered when transfer clock
is generated by falling edge of start bit
Transferred from UARTi receive
register to UiRB register
“1”
UiC1 register
RI bit
“0”
“H”
“L”
RTSi
“1”
“0”
SiRIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” by program
The above timing diagram applies to the case where the register bits are set as follows:
• Set the PRYE bit in the UiMR register to "0"(parity disabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTSi/RTSi enabled), the CRS bit to "1" (RTSi selected)
i = 0 to 2
Figure 13.1.2.2. Receive Operation
13.1.2.1. Bit Rates
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 13.1.2.1.1 lists example of bit rate and settings.
Table 13.1.2.1.1 Example of Bit Rates and Settings
Bit Rate Count Source
Peripheral Function Clock : 16MHz Peripheral Function Clock : 20MHz
Set Value of BRG : n Actual Time (bps) Set Value of BRG : n Actual Time (bps)
(bps)
1200
of BRG
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
103(67h)
51(33h)
25(19h)
103(67h)
68(44h)
51(33h)
34(22h)
31(1Fh)
25(19h)
19(13h)
1202
2404
129(81h)
64(40h)
32(20h)
129(81h)
86(56h)
64(40h)
42(2Ah)
39(27h)
32(20h)
24(18h)
1202
2404
2400
4800
4808
4735
9600
9615
9615
14400
19200
28800
31250
38400
51200
14493
19231
28571
31250
38462
50000
14368
19231
29070
31250
37879
50000
page 154
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.2.2. Counter Measure for Communication Error
If a communication error occurs while transmitting or receiving in UART mode, follow the procedure
below.
• Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
• Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in UiMR register “0002” (Serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in UiMR register “0012”, “1012”, “1102”
(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiC1
register
13.1.2.3. LSB First/MSB First Select Function
As shown in Figure 14.1.2.3.1, use the UFORM bit in the UiC0 register to select the transfer format.
This function is valid when transfer data is 8 bits long.
(1) When the UFORM bit in the UiC0 register is set to "0" (LSB first)
CLK
i
ST
ST
D0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
P
P
SP
SP
TXDi
D0
D
1
D
2
D
3
D4
D
5
D
6
D7
RXDi
(2) When the UFORM bit in the UiC0 register "1" (MSB first)
CLK
i
T
X
D
i
ST
ST
D
6
D
5
D
4
D
3
D
2
D
1
D
0
P
P
SP
SP
D
7
R
X
D
i
D
6
D
5
D
4
D
3
D
2
D
1
D0
D
7
NOTE:
ST: Start bit
P: Parity bit
SP: Stop bit
1. This applies to the case where the CKPOL bit in the UiC0 register is set to "0"
(transmit data output at the falling edge and the receive data taken in at the rising
edge of the transfer clock), the UiLCH bit in the UiC1 register is set to "0" (no
reverse), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the PRYE
bit in the UiMR register is set to "1" (parity enabled).
i = 0 to 2
Figure 13.1.2.3.1. Transfer Format
page 155
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.2.4. Serial Data Logic Switching Function (UART2)
The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the U2RB register. Figure 13.1.2.4.1 shows serial
data logic.
(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)
“H”
Transfer clock
“L”
“H”
TxD
2
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(no reverse)
“L”
(2) When the U2LCH bit in the U2C1 register is set "1" (reverse)
“H”
Transfer clock
“L”
“H”
TxD
2
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(reverse)
“L”
NOTE:
ST: Start bit
P: Parity bit
SP: Stop bit
1. This applies to the case where the CKPOL bit in the U2C0 register is set to "0"
(transmit data output at the falling edge of the transfer clock), the UFORM bit in the
U2C0 register is set to "0" (LSB first), the STPS bit in the U2MR register is set to "0"
(1 stop bit) and the PRYE bit in the U2MR register is set to "1" (parity enabled).
Figure 13.1.2.4.1. Serial Data Logic Switching
13.1.2.5. TxD and RxD I/O Polarity Inverse Function (UART2)
This function inverses the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all
input/output data (including the start, stop and parity bits) are inversed. Figure 13.1.2.5.1 shows the
TXD pin output and RXD pin input polarity inverse.
(1) When the IOPOL bit in the U2MR register is set to "0" (no reverse)
“H”
Transfer clock
“L”
“H”
2
TxD
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(no reverse) “L”
“H”
RxD
2
“L”
(no reverse)
(2) When the IOPOL bit in the U2MR register is set to "1" (reverse)
“H”
Transfer clock
“L”
“H”
TxD
2
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(reverse) “L”
“H”
RxD
(reverse)
2
“L”
NOTE:
ST: Start bit
P: Parity bit
SP: Stop bit
1. This applies to the case where the UFORM bit in the U2C0 register is set to
"0"(LSB first), the STPS bit in the U2MR register is set to "0" (1 stop bit) and the
PRYE bit in the U2MR register is set to "1"(parity enabled).
Figure 13.1.2.5.1. TXD and RXD I/O Polarity Inverse
page 156
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
_______ _______
13.1.2.6. CTS/RTS Separate Function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• Set the CRD bit in the U0C0 register to "0" (enables UART0 CTS/RTS)
_______
• Set the CRS bit in the U0C0 register to "1"(outputs UART0 RTS)
_______ _______
• Set the CRD bit in the U1C0 register to "0" (enables UART1 CTS/RTS)
_______
• Set the CRS bit in the U1C0 register to "0" (inputs UART1 CTS)
_______
• Set the RCSP bit in the UCON register to "1" (inputs CTS0 from the P64 pin)
• Set the CLKMD1 bit in the UCON register to "0" (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
IC
Microcomputer
T
X
D
D
0
(P6
(P6
3
)
)
IN
R
X
0
2
OUT
RTS
CTS
0
(P6
(P6
0)
CTS
RTS
0
4)
NOTE:
1. This applies to the case where U1MAP bit in PACR register is set to “0” (P67 to P64).
_______ _______
Figure 13.1.2.6.1. CTS/RTS Separate Function
page 157
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
2
13.1.3 Special Mode 1 (I C bus mode)(UART2)
2
2
I C bus mode is provided for use as a simplified I C bus interface compatible mode. Table 13.1.3.1 lists
2
2
the specifications of the I C bus mode. Table 13.1.3.2 and 13.1.3.3 list the registers used in the I C bus
2
mode and the register values set. Table 13.1.3.4 lists the I C bus mode fuctions. Figure 13.1.3.1 shows
2
the block diagram for I C bus mode. Figure 13.1.3.2 shows SCL2 timing.
2
As shown in Table 13.1.3.2, the microcomputer is placed in I C bus mode by setting the SMD2 to SMD0
bits to ‘0102’ and the IICM bit to “1”. Because SDA2 transmit output has a delay circuit attached, SDA
output does not change state until SCL2 goes low and remains stably low.
2
Table 13.1.3.1. I C bus Mode Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• During master
The CKDIR bit in the U2MR register is set to “0” (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in the U2BRG register 0016 to FF16
• During slave
The CKDIR bit is set to “1” (external clock) : Input from SCL2 pin
Transmission start condition • Before transmission can start, the following requirements must be met (1)
_ The TE bit in the U2C1 register is set to "1" (transmission enabled)
_ The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
Reception start condition
• Before reception can start, the following requirements must be met (1)
_ The RE bit in the U2C1 register is set to "1" (reception enabled)
_ The TE bit in the U2C1 register is set to "1" (transmission enabled)
_ The TI bit in the U2C1 register is set to "0" (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Interrupt request
generation timing
Error detection
• Overrun error (2)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 8th bit of the next data
• Arbitration lost
Select function
Timing at which the ABT bit in the U2RB register is updated can be selected
• SDA2 digital delay
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
NOTES:
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
unchanged.
page 158
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Start and stop condition generation block
SDASTSP
SCLSTSP
IICM2=1
SDA2
DMA0, DMA1 request
STSPSEL=1
Delay
circuit
STSPSEL=0
Transmission
register
UART2 transmit,
NACK interrupt
request
ACKC=1
ACKD bit
ACKC=0
IICM=1 and
IICM2=0
UART2
SDHI
ALS
DMA0
D
Arbitration
Q
T
Noise
Filter
IICM2=1
UART2 receive,
ACK interrupt request,
DMA1 request
Reception register
UART2
IICM=1 and
IICM2=0
Start condition
detection
S
R
Bus
Q
busy
Stop condition
detection
NACK
D
Q
Q
T
Falling edge
detection
D
SCL2
ACK
T
R
Port register
(1)
IICM=0
I/O port
STSPSEL=0
9th bit
Q
Internal clock
Start/stop condition detection
interrupt request
SWC2
External
clock
CLK
control
UART2
IICM=1
STSPSEL=1
Noise
Filter
UART2
9th bit falling edge
SWC
R
S
This diagram applies to the case where the SMD2 to SMD0 bits in the the U2MR register is set to "010
register is set to "1".
2" and the IICM bit in the U2SMR
IICM
: Bit in the U2SMR
IICM2, SWC, ALS, SWC2, SDHI : Bits in the U2SMR2
STSPSEL, ACKD, ACKC
NOTE:
: Bits in the U2SMR4
1. If the IICM bit is set to "1", the pin can be read even when the PD7_1 bit is set to "1" (output mode).
2
Figure 13.1.3.1. I C bus Mode Block Diagram
page 159
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 13.1.3.2. Registers to Be Used and Settings in I2C bus Mode (1) (Continued)
Register
Bit
Function
Master
Set transmission data
Slave
Set transmission data
U2TB
(1)
0 to 7
U2RB
(1)
0 to 7
8
ABT
OER
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to ‘0102’
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
U2BRG 0 to 7
U2MR
(1)
SMD2 to SMD0
CKDIR
Set to ‘0102’
Set to “1”
Set to “0”
IOPOL
Set to “0”
Set to “0”
U2C0
CLK1, CLK0
Select the count source for the U2BRG
register
Invalid
CRS
TXEPT
CRD
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
NCH
Set to “1”
Set to “1”
CKPOL
UFORM
TE
Set to “0”
Set to “1”
Set to “0”
Set to “1”
U2C1
Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission
TI
RE
RI
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
U2IRS
U2RRM,
U2LCH, U2ERE
Set to “0”
Set to “0”
U2SMR IICM
ABC
Set to “1”
Set to “1”
Select the timing at which arbitration-lost Invalid
is detected
BBS
3 to 7
U2SMR2 IICM2
CSC
Bus busy flag
Set to “0”
Bus busy flag
Set to “0”
2
2
Refer to Table 13.1.3.4 I C bus Mode Functions
Set this bit to “1” to enable clock
synchronization
Refer to Table 13.1.3.4 I C bus Mode Functions
Set to “0”
SWC
Set this bit to “1” to have SCL2 output
fixed to “L” at the falling edge of the 9th
bit of clock
Set this bit to “1” to have SCL2 output
fixed to “L” at the falling edge of the 9th
bit of clock
ALS
Set this bit to “1” to have SDA2 output
stopped when arbitration-lost is detected
Set to “0”
Set to “0”
STAC
SWC2
Set this bit to “1” to initialize UART2 at
start condition detection
Set this bit to “1” to have SCL2 output
forcibly pulled low
Set this bit to “1” to have SCL2 output
forcibly pulled low
SDHI
7
Set this bit to “1” to disable SDA2 output Set this bit to “1” to disable SDA2 output
Set to “0”
Set to “0”
Set to “0”
U2SMR3 0, 2, 4 and NODC Set to “0”
2
2
CKPH
Refer to Table 13.1.3.4 I C bus Mode Functions
Refer to Table 13.1.3.4 I C bus Mode Functions
DL2 to DL0
Set the amount of SDA2 digital delay
Set the amount of SDA2 digital delay
NOTE:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C bus
mode.
page 160
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 13.1.3.3. Registers to Be Used and Settings in I2C bus Mode (2) (Continued)
Register
Bit
Function
Master
Set this bit to “1” to generate start
condition
Set this bit to “1” to generate restart
condition
Slave
U2SMR4 STAREQ
RSTAREQ
Set to “0”
Set to “0”
Set to “0”
STPREQ
Set this bit to “1” to generate stop
condition
STSPSEL
ACKD
Set this bit to “1” to output each condition Set to “0”
Select ACK or NACK
Select ACK or NACK
ACKC
SCLHI
Set this bit to “1” to output ACK data
Set this bit to “1” to have SCL2 output
stopped when stop condition is detected
Set to “0”
Set this bit to “1” to output ACK data
Set to “0”
SWC9
Set this bit to “1” to set the SCL2 to “L”
hold at the falling edge of the 9th bit of
clock
NOTE:
2
1. Not all bits in the register are described above. Set those bits to “0” when writing to the registers in I C
bus mode.
page 161
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
2
Table 13.1.3.4. I C bus Mode Functions
Clock synchronous serial I/O
mode (SMD2 to SMD0 = 001
IICM = 0)
I2C bus mode (SMD2 to SMD0 = 010
2
, IICM = 1)
IICM2 = 1
(UART transmit/ receive interrupt)
Function
2
,
IICM2 = 0
(NACK/ACK interrupt)
CKPH = 1
CKPH = 0
CKPH = 1
CKPH = 0
(Clock delay)
(No clock delay) (Clock delay) (No clock delay)
Factor of interrupt number
10 (1)
Start condition detection or stop condition detection
(Refer to Figure 13.1.3.2.1. STSPSEL Bit Function)
(Refer to Fig.13.1.3.2.)
Factor of interrupt number
15 (1)
(Refer to Fig.13.1.3.2.)
No acknowledgment
detection (NACK)
Rising edge of SCL2 9th bit
UART2 transmission
Transmission started or
completed (selected by U2IRS)
UART2 transmission UART2 transmission
Rising edge of
SCL 9th bit
UART2 transmission
Falling edge of SCL
next to the 9th bit
2
2
Factor of interrupt number UART2 reception
16 (1)
1(Refer to Fig.13.1.3.2.)
Acknowledgment detection
(ACK)
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Falling edge of SCL
2
9th bit
Rising edge of SCL
2
9th bit
Timing for transferring data
from the UART reception
shift register to the U2RB
register
Falling and rising
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Falling edge of
SCL2 9th bit
Rising edge of SCL
2
9th bit
edges of SCL
bit
2 9th
UART2 transmission
output delay
Delayed
Not delayed
TxD2 output
SDA
2
input/output
input/output
Functions of P7
0
pin
pin
pin
SCL
2
Functions of P7
Functions of P7
1
2
RxD2 input
(Cannot be used in I2C mode)
CLK2 input or output selected
Noise filter width
200ns
15ns
Read RxD2 and SCL
levels
2
pin Possible when the
corresponding port direction bit
= 0
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I2C bus mode (2)
CKPOL = 0 (H)
CKPOL = 1 (L)
Initial value of TxD2 and
SDA outputs
2
Initial and end values of
SCL
H
L
H
L
2
UART2 reception
DMA1 factor (Refer to Fig.
14.1.3.2.)
Acknowledgment detection
(ACK)
UART2 reception
Falling edge of SCL
2
9th bit
Store received data
1st to 8th bits are stored in
U2RB register bit 0 to bit 7
1st to 8th bits are stored in
U2RB register bit 7 to bit 0
1st to 7th bits are stored in U2RB register
bit 6 to bit 0, with 8th bit stored in U2RB
register bit 8
1st to 8th bits are
stored in U2RB
register bit 7 to bit 0
(3)
Read received data
Read U2RB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 (4)
U2RB register status is read
directly as is
NOTES:
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt
may inadvertently be set to 1 (interrupt requested). (Refer to “Notes on interrupts” in Usage Notes) If one of the bits
shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to clear
the IR bit to 0 (interrupt not requested) after changing those bits. SMD2 to SMD0 bits in the U2MR register, IICM bit
in the U2SMR register, IICM2 bit in the U2SMR2 register, CKPH bit in the U2SMR3 register
2. Set the initial value of SDA
disabled).
2 output while the SMD2 to SMD0 bits in the U2MR register is set to ‘0002’ (serial I/O
3. Second data transfer to U2RB register (Rising edge of SCL
2 9th bit)
4. First data transfer to U2RB register (Falling edge of SCL 9th bit)
2
page 162
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D1
D0
D
8 (ACK or NACK)
ACK interrupt (DMA
request) or NACK interrupt
b15
b9 b8 b7
b0
•••
D8 D7 D6 D5 D4 D3 D2 D1 D0
Data is transferred to the U2RB register
Contents of the U2RB register
(2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay)
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D1
D0
D
8
(ACK or NACK)
ACK interrupt (DMA
request) or NACK interrupt
b15
b9
b8 b7
b0
•••
D8
D7 D6 D5 D4 D3 D2 D1 D0
Data is transferred to the U2RB register
Contents of the U2RB register
(3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0"
1st
bit
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
SCL2
SDA2
D8
(ACK or NACK)
D7
D6
D5
D4
D3
D2
D1
D0
Receive interrupt
(DMA request)
Transmit interrupt
b15
b9
b8 b7
b0
Data is transferred to the U2RB register
•••
D0
D7 D6 D5 D4 D3 D2 D1
Contents of the U2RB register
(4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1"
1st
2nd
bit
3rd
bit
4th
bit
5th
bit
6th
bit
7th
bit
8th
bit
9th
bit
bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D
1
D0
D8
(ACK or NACK)
Transmit interrupt
Receive interrupt
(DMA request)
Data is transferred to the U2RB register Data is transferred to the U2RB register
b15
b9
b8 b7
b0
b15
b9
b8 b7
b0
•••
•••
D0
D7
D6
D5
D4
D3
D2
D1
D8 D7 D6 D5 D4 D3 D2 D1 D0
Contents of the U2RB register
Contents of the U2RB register
The above timing applies to the following setting :
• The CKDIR bit in the U2MR register is set to "1" (slave)
Figure 13.1.3.2. Transfer to U2RB Register and Interrupt Timing
page 163
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.3.1 Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDA2 pin changes state from high
to low while the SCL2 pin is in the high state. A stop condition-detected interrupt request is generated
when the SDA2 pin changes state from low to high while the SCL2 pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the BBS bit in the U2SMR register to determine which interrupt source is requesting the
interrupt.
3 to 6 cycles < setup time (1)
3 to 6 cycles < hold time (1)
Hold time
Setup time
SCL2
SDA2(Start condition)
SDA2(Stop condition)
NOTE:
1. When the PCLK1 bit in the PCLKR register is set to "1", the cycles indicates the f1SIO's
generation frequency cycles; when PCLK1 bit is set to "0", the cycles indicated the f2SIO's
generation frequency cycles.
Figure 13.1.3.1.1. Detection of Start and Stop Condition
13.1.3.2 Output of Start and Stop Condition
A start condition is generated by setting the STAREQ bit in the U2SMR4 register to “1” (start).
A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to “1” (start).
A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to “1” (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the U2SMR4 register to “1” (output).
Make sure that no interrupts or DMA transfers will occur between (1) and (2).
The function of the STSPSEL bit is shown in Table 13.1.3.2.1 and Figure 13.1.3.2.1.
page 164
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 13.1.3.2.1. STSPSEL Bit Functions
Function
STSPSEL = 0
STSPSEL = 1
Output of SCL2 and SDA2 pins
Output transfer clock and data/ The STAREQ, RSTAREQ and
Program with a port determines STPREQ bit determine how the
how the start condition or stop start condition or stop condition is
condition is output
Start/stop condition are de-
tected
output
Start/stop condition interrupt
request generation timing
Start/stop condition generation are
completed
(1) In slave mode,
CKDIR is set to "1" (external clock)
STPSEL bit
SCL2
0
1st
2nd
3rd
5th
6th
7th
8th
9th bit
4th
SDA2
Start condition detection
interrupt
Stop condition detection
interrupt
(2) In master mode,
CKDIR is set to "0" (internal clock), CKPH is set to "1"(clock delayed)
STPSEL bit
Set to "1" by
a program
Set to "0" by
a program
Set to "1" by
a program
Set to "0" by
a program
1st
2nd
3rd
5th
6th
7th
8th
9th bit
4th
SCL2
SDA2
Set STAREQ to "1" (start)
Set STPREQ
to "1" (start)
Stop condition detection
interrupt
Start condition detection
interrupt
Figure 13.1.3.2.1. STSPSEL Bit Functions
13.1.3.3 Arbitration
Unmatching of the transmit data and SDA2 pin input data is checked synchronously with the rising
edge of SCL2. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the
U2RB register is updated. If the ABC bit is set to "0" (updated bitwise), the ABT bit is set to “1” at the
same time unmatching is detected during check, and is cleared to “0” when not detected. In cases
when the ABC bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to
“1” (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be
updated bytewise, clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte,
before transferring the next byte.
Setting the ALS bit in the U2SMR2 register to “1” (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDA2 pin is placed in the high-impedance state at the same time the ABT bit
is set to “1” (unmatching detected).
page 165
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.3.4 Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 13.1.3.2.1.
The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal
SCL2) and an external clock supplied to the SCL2 pin. In cases when the CSC bit is set to “1” (clock
synchronization enabled), if a falling edge on the SCL2 pin is detected while the internal SCL2 is high,
the internal SCL2 goes low, at which time the U2BRG register value is reloaded with and starts count-
ing in the low-level interval. If the internal SCL2 changes state from low to high while the SCL2 pin is
low, counting stops, and when the SCL2 pin goes high, counting restarts.
In this way, the UART2 transfer clock is comprised of the logical product of the internal SCL2 and SCL2
pin signal. The transfer clock works from a half period before the falling edge of the internal SCL2 1st
th
bit to the rising edge of the 9 bit. To use this function, select an internal clock for the transfer clock.
The SWC bit in the U2SMR2 register allows to select whether the SCL2 pin should be fixed to or freed
from low-level output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the U2SMR4 register is set to “1” (enabled), SCL2 output is turned off (placed in the
high-impedance state) when a stop condition is detected.
Setting the SWC2 bit in the U2SMR2 register is set to "1" (0 output) makes it possible to forcibly output
a low-level signal from the SCL2 pin even while sending or receiving data. Clearing the SWC2 bit to “0”
(transfer clock) allows the transfer clock to be output from or supplied to the SCL2 pin, instead of
outputting a low-level signal.
If the SWC9 bit in the U2SMR4 register is set to “1” (SCL hold low enabled) when the CKPH bit in the
U2SMR3 register is set to "1", the SCL2 pin is fixed to low-level output at the falling edge of the clock
pulse next to the ninth. Setting the SWC9 bit is set to "0" (SCL hold low disabled) frees the SCL2 pin
from low-level output.
13.1.3.5 SDA Output
The data written to the bit 7 to bit 0 (D7 to D0) in the U2TB register is sequentially output beginning with
D7. The ninth bit (D8) is ACK or NACK.
2
The initial value of SDA2 transmit output can only be set when IICM is set to "1" (I C Bus mode) and
the SMD2 to SMD0 bits in the the U2MR register are set to ‘0002’ (serial I/O disabled).
The DL2 to DL0 bits in the U2SMR3 register allow to add no delays or a delay of 2 to 8 U2BRG count
source clock cycles to SDA2 output.
Setting the SDHI bit in the U2SMR2 register is set to "1" (SDA output disabled) forcibly places the
SDA2 pin in the high-impedance state. Do not write to the SDHI bit synchronously with the rising edge
of the UART2 transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).
13.1.3.6 SDA Input
When the IICM2 bit is set to "0", the 1st to 8th bits (D7 to D0) of received data are stored in the bit 7 to
bit 0 in the U2RB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit is set to "1", the 1st to 7th bits (D7 to D1) of received data are stored in the bit 6 to
bit 0 in the U2RB register and the 8th bit (D0) is stored in the bit 8 in the U2RB register. Even when the
IICM2 bit is set to "1", providing the CKPH bit to "1", the same data as when the IICM2 bit is set to "0"
can be read out by reading the U2RB register after the rising edge of the corresponding clock pulse of
9th bit.
page 166
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.3.7 ACK and NACK
If the STSPSEL bit in the U2SMR4 register is set to “0” (start and stop conditions not generated) and
the ACKC bit in the U2SMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the
U2SMR4 register is output from the SDA2 pin.
If the IICM2 bit is set to "0", a NACK interrupt request is generated if the SDA2 pin remains high at the
rising edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDA2 pin
is low at the rising edge of the 9th bit of transmit clock pulse.
If ACK2 is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
13.1.3.8 Initialization of Transmission/Reception
If a start condition is detected while the STAC bit is set to "1" (UART2 initialization enabled), the serial
I/O operates as described below.
- The transmit shift register is initialized, and the content of the U2TB register is transferred to the
transmit shift register. In this way, the serial I/O starts sending data synchronously with the next
clock pulse applied. However, the UART2 output value does not change state and remains the
same as when a start condition was detected until the first bit of data is output synchronously with
the input clock.
- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the
next clock pulse applied.
- The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCL2 pin is pulled low at the
falling edge of the ninth clock pulse.
Note that when UART2 transmission/reception is started using this function, the TI does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.
page 167
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.4 Special Mode 2 (UART2)
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 13.1.4.1 lists the specifications of Special Mode 2. Table 13.1.4.2 lists the registers
used in Special Mode 2 and the register values set. Figure 13.1.4.1 shows communication control ex-
ample for Special Mode 2.
Table 13.1.4.1. Special Mode 2 Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• Master mode
The CKDIR bit in the U2MR register is set to “0” (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register 0016 to FF16
• Slave mode
The CKDIR bit is set to “1” (external clock selected) : Input from CLK2 pin
Transmit/receive control
Controlled by input/output ports
Transmission start condition • Before transmission can start, the following requirements must be met (1)
_ The TE bit in the U2C1 register is set to "1" (transmission enabled)
_ The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
Reception start condition
• Before reception can start, the following requirements must be met (1)
_ The RE bit in the U2C1 register is set to "1" (reception enabled)
_ The TE bit in the U2C1 register is set to "1" (transmission enabled)
_ The TI bit in the U2C1 register is set to "0" (data present in the U2TB register)
• While transmitting, one of the following conditions can be selected
_ The U2IRS bit in the U2C1 register is set to "0" (transmit buffer empty): when trans-
ferring data from the U2TB register to the UART2 transmit register (at start of transmission)
_ The U2IRS bit is set to "1" (transfer completed): when the serial I/O finished sending
data from the UART2 transmit register
Interrupt request
generation timing
• While receiving
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Error detection
• Overrun error (2)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 7th bit of the next data
• Clock phase setting
Select function
NOTES:
Selectable from four combinations of transfer clock polarities and phases
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the U2C0 register “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the CKPOL bit in the U2C0 register “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
unchanged.
page 168
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
P13
P12
P93
P72(CLK2)
P71(RxD2)
P70(TxD2)
P72(CLK2)
P71(RxD2)
P70(TxD2)
Microcomputer
(Master)
Microcomputer
(Slave)
P93
P72(CLK2)
P71(RxD2)
P70(TxD2)
Microcomputer
(Slave)
Figure 13.1.4.1. Serial Bus Communication Control Example (UART2)
page 169
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 13.1.4.2. Registers to Be Used and Settings in Special Mode 2
Register
U2TB(1)
U2RB(1)
Bit
0 to 7
0 to 7
Function
Set transmission data
Reception data can be read
Overrun error flag
OER
U2BRG
0 to 7
Set a transfer rate
Set to ‘0012’
U2MR(1)
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
Set this bit to “0” for master mode or “1” for slave mode
Set to “0”
Select the count source for the U2BRG register
Invalid because CRD = 1
Transmit register empty flag
Set to “1”
U2C0
TXEPT
CRD
NCH
Select TxD2 pin output format
CKPOL
Clock phases can be set in combination with the CKPH bit in the U2SMR3
register
UFORM
TE
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
0 to 7
Set to “0”
U2C1
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select UART2 transmit interrupt cause
Set to “0”
U2SMR
Set to “0”
U2SMR2
U2SMR3
0 to 7
Set to “0”
CKPH
NODC
0, 2, 4 to 7
0 to 7
Clock phases can be set in combination with the CKPOL bit in the U2C0 register
Set to “0”
Set to “0”
Set to “0”
U2SMR4
NOTE:
1. Not all bits in the register are described above. Set those bits to “0” when writing to the registers in
Special Mode 2.
page 170
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.4.1 Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit
in the U2SMR3 register and the CKPOL bit in the U2C0 register.
Make sure the transfer clock polarity and phase are the same for the master and slave to communi-
cate.
13.1.4.1.1 Master (Internal Clock)
Figure 13.1.4.1.1.1 shows the transmission and reception timing in master (internal clock).
13.1.4.1.2 Slave (External Clock)
Figure 13.1.4.1.2.1 shows the transmission and reception timing (CKPH=0) in slave (external clock)
while Figure 13.1.4.1.2.2 shows the transmission and reception timing (CKPH=1) in slave (external
clock).
"H"
Clock output
"L"
(CKPOL=0, CKPH=0)
"H"
"L"
Clock output
(CKPOL=1, CKPH=0)
Clock output
(CKPOL=0, CKPH=1)
"H"
"L"
"H"
"L"
Clock output
(CKPOL=1, CKPH=1)
"H"
"L"
Data output timing
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Figure 13.1.4.1.1.1. Transmission and Reception Timing in Master Mode (Internal Clock)
page 171
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
"H"
Slave control input
"L"
"H"
Clock input
"L"
(CKPOL=0, CKPH=0)
"H"
"L"
Clock input
(CKPOL=1, CKPH=0)
"H"
"L"
Data output timing
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Indeterminate
Figure 13.1.4.1.2.1. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)
"H"
Slave control input
"L"
"H "
Clock input
"L"
(CKPOL=0, CKPH=1)
"H "
"L "
Clock input
(CKPOL=1, CKPH=1)
"H "
"L"
Data output timing
Data input timing
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D 7
.
Figure 13.1.4.1.2.2. Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
page 172
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.5 Special Mode 3 (IE Bus mode )(UART2)
In this mode, one bit of IE Bus is approximated with one byte of UART mode waveform.
Table 13.1.5.1 lists the registers used in IE Bus mode and the register values set. Figure 13.1.5.1 shows
the functions of bus collision detect function related bits.
If the TxD2 pin output level and RxD2 pin input level do not match, a UART2 bus collision detect interrupt
request is generated.
Table 13.1.5.1. Registers to Be Used and Settings in IE Bus Mode
Register
Bit
0 to 8
0 to 8
OER,FER,PER,SUM Error flag
Function
Set transmission data
Reception data can be read
U2TB
U2RB(1)
U2BRG
U2MR
0 to 7
Set a transfer rate
SMD2 to SMD0
CKDIR
STPS
Set to ‘1102’
Select the internal clock or external clock
Set to “0”
PRY
Invalid because PRYE=0
Set to “0”
PRYE
IOPOL
CLK1, CLK0
CRS
Select the TxD/RxD input/output polarity
Select the count source for the U2BRG register
Invalid because CRD=1
Transmit register empty flag
Set to “1”
U2C0
TXEPT
CRD
NCH
Select TxD2 pin output mode
Set to “0”
CKPOL
UFORM
TE
Set to “0”
U2C1
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
0 to 3, 7
ABSCS
ACSE
SSS
U2SMR
Set to “0”
Select the sampling timing at which to detect a bus collision
Set this bit to “1” to use the auto clear function of transmit enable bit
Select the transmit start condition
U2SMR2
U2SMR3
U2SMR4
0 to 7
Set to “0”
Set to “0”
Set to “0”
0 to 7
0 to 7
NOTE:
1. Not all bits in the registers are described above. Set those bits to “0” when writing to the registers in
IEBus mode.
page 173
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxD2
RxD2
Input to TA0IN
Timer A0
If ABSCS is set to "1", bus collision is determined when timer
A0 (one-shot timer mode) underflows
.
(2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit)
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxD2
RxD2
BCNIC register
IR bit (1)
If ACSE bit is set to "1"
automatically clear when bus collision
occurs), the TE bit is cleared to "0"
(transmission disabled) when
U2C1 register
TE bit
the IR bit in the BCNIC register is
set to "1" (unmatching detected).
(3) The SSS bit in the U2SMR register (Transmit start condition select)
If SSS bit is set to "0", the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
TxD2
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (1) of RxD2
CLK2
TxD2
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
(2)
RxD2
NOTES:
1. The falling edge of RxD2 when the IOPOL is set to "0"; the rising edge of RxD2 when the IOPOL is set to "1".
2. The transmit condition must be met before the falling.edge (Note 1) of RxD.
This diagram applies to the case where the IOPOL is set to "1" (reversed)
Figure 13.1.5.1. Bus Collision Detect Function-Related Bits
page 174
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.6 Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected.
Tables 13.1.6.1 lists the specifications of SIM mode. Table 13.1.6.2 lists the registers used in the SIM
mode and the register values set.
Table 13.1.6.1. SIM Mode Specifications
Item
Specification
Transfer data format
• Direct format
• Inverse format
Transfer clock
• The CKDIR bit in the U2MR register is set to “0” (internal clock) : fi/(16(n+1))
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in U2BRG register
• The CKDIR bit is set to “1” (external clock ) : fEXT/(16(n+1))
fEXT: Input from CLK2 pin. n: Setting value in U2BRG register
0016 to FF16
0016 to FF16
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit in the U2C1 register is set to "1" (transmission enabled)
_ The TI bit in the U2C1 register is set to "0" (data present in U2TB register)
Reception start condition
• Before reception can start, the following requirements must be met
_ The RE bit in the U2C1 register is set to "1" (reception enabled)
_ Start bit detection
Interrupt request
generation timing
• For transmission
When the serial I/O finished sending data from the U2TB transfer register (the U2IRS bit
is set to "1")
(2)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Error detection
• Overrun error (1)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set to "1" when any of the overrun, framing, and parity errors is encountered
NOTES:
1. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
unchanged.
2. A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmission com-
plete) and the U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be sure to clear
the IR bit to “0” (no interrupt request) after setting these bits.
page 175
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 13.1.6.2. Registers to Be Used and Settings in SIM Mode
Register
U2TB(1)
U2RB(1)
Bit
0 to 7
0 to 7
OER,FER,PER,SUM Error flag
Function
Set transmission data
Reception data can be read
U2BRG
U2MR
0 to 7
Set a transfer rate
Set to ‘1012’
Select the internal clock or external clock
Set to “0”
SMD2 to SMD0
CKDIR
STPS
PRY
Set this bit to “1” for direct format or “0” for inverse format
PRYE
Set to “1”
Set to “0”
IOPOL
U2C0
CLK1, CLK0
CRS
Select the count source for the U2BRG register
Invalid because CRD=1
TXEPT
CRD
Transmit register empty flag
Set to “1”
NCH
Set to “0”
CKPOL
UFORM
TE
Set to “0”
Set this bit to “0” for direct format or “1” for inverse format
U2C1
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS
U2RRM
U2LCH
U2ERE
Set to “1”
Set to “0”
Set this bit to “0” for direct format or “1” for inverse format
Set to “1”
Set to “0”
Set to “0”
Set to “0”
Set to “0”
U2SMR(1) 0 to 3
U2SMR2
U2SMR3
U2SMR4
0 to 7
0 to 7
0 to 7
NOTE:
1. Not all bits in registers are described above. Set those bits to “0” when writing to the registers in SIM
mode.
page 176
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1) Transmit Timing
Tc
Transfer Clock
"1"
TE bit in U2C1
Data is written to
the UARTi register
register
"0"
"1"
"0"
TI bit in U2C1
register
Data is transferred from the U2TB
register to the UART2 transmit
register
Stop
bit
Parity
bit
Start
bit
TxD
2
ST
D
0
D
1
D
2
2
D
3
3
D
4
4
D
5
5
D
7
7
P
SP
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
P
SP
D
6
6
D6
Parity Error Signal
returned from
Receiving End
An "L" signal is applied from the SIM
card due to a parity error
(1)
RxD2 pin Level
SP
ST
D
0
D
1
D
D
D
D
D
P
SP
ST
D0
D
1
D
2
D
3
D
4
D
5
D7
D
D6
An interrupt routine
detects "H" or "L"
An interrupt routine detects
"H" or "L"
TXEPT bit in U2
C0 register
"1"
"0"
IR bit in S2TIC
register
"1"
"0"
Set to "0" by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where data is
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO
)
f
EXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
TC
(2) Receive Timing
Transfer Clock
"1
RE bit in U2C1
"
register
"0
"
Parity Stop
Start
bit
bit
bit
Transmit Waveform
from the
Transmitting End
SP
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
D
7
P
SP
ST
ST
D
0
D
1
D
2
D
3
D
4
D
5
D7
P
P
D
6
D
6
TxD2
TxD
to a parity error
2 outputs "L" due
(2)
RxD2 pin Level
SP
ST
D0
D1
D2
D3
D4
D5
7
P
SP
D0
D1
D2
D3
D4
D5
D7
D6
D6
"1"
RI bit in U2C1
register
"0
"
Read the U2RB register
"1"
IR bit in S2RIC
register
"0"
Set to "0" by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where data is
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO
)
f
EXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
NOTES:
1. Because TxD
signal sent back from receiver.
2. Because TxD and RxD2 are connected, this is composite waveform consisting of the transmitter's transmit waveform
2 and RxD2 are connected, this is composite waveform consisting of the TxD2 output and the parity error
2
and the parity error signal received.
Figure 13.1.6.1. Transmit and Receive Timing in SIM Mode
page 177
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Figure 13.1.6.2 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.
Microcomputer
SIM card
TxD
2
2
RxD
Figure 13.1.6.2. SIM Interface Connection
13.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register’ to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 13.1.6.1.1. If the R2RB register is read
while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output
is returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.
“H”
Transfer
clock
“L”
“H”
ST
D0
D1
D2
D3
(1)
D4
D5
D6
D7
P
SP
RxD
TxD
2
“L”
“H”
“L”
2
“1”
“0”
U2C1 register
RI bit
This timing diagram applies to the case where the direct format is implemented.
ST: Start bit
P: Even Parity
SP: Stop bit
NOTE:
1. The output of microcomputer is in the high-impedance state
(pulled up externally).
Figure 13.1.6.1.1. Parity Error Signal Output Timing
page 178
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
13. Serial I/O
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
13.1.6.2 Format
• Direct Format
Set the PRY bit in the U2MR register to “1”, the UFORM bit in the U2C0 register to “0” and the U2LCH
bit in the U2C1 register to “0”.
• Inverse Format
Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”.
Figure 13.1.6.2.1 shows the SIM interface format.
(1) Direct format
“H”
Transfer
“L”
clcck
“H”
TxD
2
D0
D1
D2
D3
D4
D5
D6
D7
P
“L”
P : Even parity
(2) Inverse format
“H”
Transfer
“L”
clcck
“H”
TxD
2
D7
D6
D5
D4
D3
D2
D1
D0
P
“L”
P : Odd parity
Figure 13.1.6.2.1. SIM Interface Format
page 179
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14. A/D Converter
Note
P92 and P93 (AN32, AN24) are not available in the 42-pin package.
Do not use P92 and P93 (AN32, AN24) as analog input pins in the 42-pin package.
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107 (AN0 to
___________
AN7), P90 to P93 (AN30 to AN32, AN24). Similarly, ADTRG input shares the pin with P15. Therefore, when
using these inputs, make sure the corresponding port direction bits are set to “0” (input mode).
When not using the A/D converter, set the VCUT bit to “0” (VREF unconnected), so that no current will flow
from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the i bits in the A/D register for ANi, AN3i, and AN2i pins (i = 0 to 7).
Table 14.1 shows the A/D converter performance. Figure 14.1 shows the A/D converter block diagram
and Figures 14.2 to 14.4 show the A/D converter associated with registers.
Table 14.1 A/D Converter Performance
Item
Performance
Successive approximation (capacitive coupling amplifier)
0V to AVCC (VCC)
fAD/divided-by-2 or fAD/divided-by-3 or fAD/divided-by-4 or fAD/divided-by-6
or fAD/divided-by-12 or fAD
A/D Conversion Method
Analog Input Voltage (1)
Operating Clock fAD (2)
Resolution
8-bit or 10-bit (selectable)
Integral Nonlinearity Error When AVCC = VREF = 5V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±3LSB
When AVCC = VREF = 3.3V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±5LSB
Operating Modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat
sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1
8 pins (AN0 to AN7) + 3 pins (AN30 to AN32) + 1 pins (AN24) (48-pin package)
Analog Input Pins (3)
Conversion Speed Per Pin
8 pins (AN0 to AN7) + 2 pins (AN30, AN31)
(42-pin package)
• Without sample and hold function
8-bit resolution: 49 fAD cycles
• With sample and hold function
8-bit resolution: 28 fAD cycles 10-bit resolution: 33 fAD cycles
, 10-bit resolution: 59 fAD cycles
,
NOTES:
1. Not dependent on use of sample and hold function.
2. Set the φAD frequency to 10 MHz or less. For M16C/26B, set it to 12 MHz or less.
Without sample-and-hold function, set the fAD frequency to 250kHZ or more.
With the sample and hold function, set the fAD frequency to 1MHZ or more.
page 180
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D conversion rate
selection
CKS1=1
CKS1=0
CKS2=0
ø
AD
CKS0=1
CKS0=0
1/2
1/2
fAD
1/3
CKS2=1
V
REF
Resistor ladder
VCUT=0
VCUT=1
AVSS
Successive conversion register
ADCON1 register
(address 03D716
)
ADCON0 register
(address 03D616
)
Addresses
(03C116 to 03C016
(03C316 to 03C216
(03C516 to 03C416
(03C716 to 03C616
(03C916 to 03C816
)
)
)
)
)
A/D register 0(16)
A/D register 1(16)
A/D register 2(16)
A/D register 3(16)
A/D register 4(16)
A/D register 5(16)
A/D register 6(16)
A/D register 7(16)
Decoder
for A/D register
(03CB16 to 03CA16
(03CD16 to 03CC16
(03CF16 to 03CE16
)
)
)
Data bus high-order
Data bus low-order
V
ref
ADCON2 register
(address 03D416
)
Comparator 0
Decoder
for channel
selection
V
IN
CH2 to CH0
Port P10 group
=000
=001
=010
=011
=100
=101
=110
=111
2
2
2
2
2
2
2
2
AN
0
1
2
3
4
5
6
7
ADGSEL1 to ADGSEL0=002
AN
AN
AN
AN
AN
AN
AN
ADGSEL1 to ADGSEL0=01
ADGSEL1 to ADGSEL0=11
2
Port P9 group
CH2 to CH0
=000
=001
=010
2
2
2
SSE = 1
CH2 to CH0=001
AN30
AN31
2
(1)
AN32
2
Port P9 group
CH2 to CH0
=100
2
(1)
AN24
ADGSEL1 to ADGSEL0=00
ADGSEL1 to ADGSEL0=01
2
2
VIN1
Comparator 1
NOTE:
1. AN32 and AN24 are available for only 48-pin package.
Figure 14.1 A/D Converter Block Diagram
page 181
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
2
Bit symbol
Bit name
Function
RW
RW
Analog Input Pin Select
Bit
Function varies with each operation mode
CH0
CH1
RW
RW
RW
CH2
MD0
b4 b3
A/D Operation Mode
Select Bit 0
0 0 : One-shot mode or Delayed trigger mode 0,1
0 1 : Repeat mode
1 0 : Single sweep mode or
Simultaneous sample sweep mode
1 1 : Repeat sweep mode 0 or Repeat sweep
mode 1
MD1
RW
Trigger Select Bit
0 : Software trigger
1 : Hardware trigger
RW
RW
RW
TRG
A/D Conversion Start Flag
0 : A/D conversion disabled
1 : A/D conversion started
ADST
Frequency Select Bit 0
See Table 14.2 A/D Conversion
Frequency Select
CKS0
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
Bit symbol
Bit name
Function
RW
RW
A/D Sweep Pin Select Bit
Function varies with each operation mode
SCAN0
SCAN1
MD2
RW
RW
A/D Operation Mode
Select Bit 1
0 : Other than repeat sweep mode 1
1 : Repeat sweep mode 1
8/10-Bit Mode Select Bit
Frequency Select Bit 1
0 : 8-bit mode
1 : 10-bit mode
BITS
RW
RW
RW
See Table 14.2 A/D Conversion
Frequency Select
CKS1
V
REF Connect Bit
(2)
0 : VREF not connected
1 : VREF connected
VCUT
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A/D conversion
A/D control register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A/D Conversion Method
Select Bit
b2 b1
A/D Input Group Select Bit
ADGSEL0
ADGSEL1
0 0 : Select port P10 group
0 1 : Select port P9 group (AN3i)
1 0 : Do not set
RW
RW
RW
RW
1 1 : Select port P9 group (AN24)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
See Table 14.2 A/D Conversion
Frequency Select
CKS2
Trigger Select Bit
Function varies with each operation
mode
TRG1
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.2 ADCON0 to ADCON2 Registers
page 182
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D trigger control register (1,2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADTRGCON
Address
03D216
After reset
0016
Bit symbol
SSE
Bit name
Function
RW
RW
0 : Other than simultaneous sample sweep
mode or delayed trigger mode 0,1
1 : Simultaneous sample sweep mode or
delayed trigger mode 0,1
A/D Operation Mode
Select Bit 2
0 : Other than delayed trigger mode 0,1
1 : Delayed trigger mode 0,1
A/D Operation Mode
Select Bit 3
RW
DTE
Function varies with each operation mode
AN0 Trigger Select Bit
AN1 Trigger Select Bit
RW
RW
HPTRG0
Function varies with each operation mode
HPTRG1
(b7-b4)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
NOTES:
1. If the ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. Set “0016” in this register in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep
mode 1.
Figure 14.3 ADTRGCON Register
Table 14.2 A/D Conversion Frequency Select
CKS2 CKS1 CKS0
Ø
AD
0
0
0
Divided-by-4 of fAD
Divided-by-2 of fAD
0
0
0
1
1
0
fAD
0
1
1
0
1
0
Divided-by-12 of fAD
Divided-by-6 of fAD
1
1
1
0
1
1
1
0
1
Divided-by-3 of fAD
NOTE:
1. Set the φAD frequency to 10 MHz or less (12 MHz or less in M16C/26B). The φAD is selected with
combinations of the CKS0 bit in the ADCON0 register, CKS1 bit in the ADCON1 register, and the
CKS2 bit in the ADCON2 register.
page 183
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D conversion status register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADSTAT0
Address
03D316
After reset
0016
Bit symbol
ADERR0
Bit name
Function
RW
AN1 Trigger Status Flag
0 : AN1 trigger did not occur during
AN0 conversion
1 : AN1 trigger occured during AN0
conversion
RW
RW
ADERR1
Conversion Termination
Flag
0 : Conversion not terminated
1 : Conversion terminated by
Timer B0 underflow
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b2)
0 : Sweep not in progress
1 : Sweep in progress
Delayed Trigger Sweep
Status Flag
ADTCSF
RO
AN0 Conversion Status
Flag
0 : AN0 conversion not in progress
1 : AN0 conversion in progress
ADSTT0
ADSTT1
RO
RO
RW
RW
AN1 Conversion Status
Flag
0 : AN1 conversion not in progress
1 : AN1 conversion in progress
AN0 Conversion
Completion Status Flag
0 : AN0 conversion not completed
1 : AN0 conversion completed
ADSTRT0
ADSTRT1
AN1 Conversion
Completion Status Flag
0 : AN1 conversion not completed
1 : AN1 conversion completed
NOTE:
1. ADSTAT0 register is valid only when the DTE bit in the ADTRGCON register is set to “1”.
Symbol
AD0
Address
After reset
A/D Register i (i=0 to 7)
03C116 to 03C016 Indeterminate
03C316 to 03C216 Indeterminate
03C516 to 03C416 Indeterminate
03C716 to 03C616 Indeterminate
03C916 to 03C816 Indeterminate
03CB16 to 03CA16 Indeterminate
03CD16 to 03CC16 Indeterminate
03CF16 to 03CE16 Indeterminate
AD1
AD2
AD3
AD4
AD5
AD6
AD7
(b15)
b7
(b8)
b0 b7
b0
Function
RW
When the BITS bit in the ADCON1
register is “1” (10-bit mode)
When the BITS bit in the ADCON1
register is “0” (8-bit mode)
Eight low-order bits of
A/D conversion result
A/D conversion result
RO
RO
Two high-order bits of
A/D conversion result
When read, its content is
indeterminate
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Figure 14.4 ADSTAT0 Register and AD0 to AD7 Registers
page 184
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1)
Timer B2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2SC
Address
039E16
After reset
X0000000
0
0
2
RW
RW
Bit symbol
PWCOM
Bit name
Function
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 Reload Timing
(2)
Switch Bit
Three-Phase Output Port 0 : Three-phase output forcible cutoff
IVPCR1
SD Control Bit 1
(3, 4, 7)
by SD pin input (high impedance)
disabled
RW
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
Timer B0 Operation Mode 0 : Other than A/D trigger mode
Select Bit 1 : A/D trigger mode (5)
TB0EN
TB1EN
TB2SEL
RW
RW
RW
Timer B1 Operation Mode 0 : Other than A/D trigger mode
Select Bit
1 : A/D trigger mode (5)
(6)
0 : TB2 interrupt
Trigger Select Bit
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
Reserved bits
Must set to "0"
RW
(b6-b5)
(b7)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this bit to
"0" (timer B2 underflow).
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5 bit to
"0" (= input mode).
4. Related pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). When a high-level ("H") signal is applied to the SD
pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state.
If a low-level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0).
At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1
bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those
pins is used.
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the
INV02 bit to "1" (three-phase motor control timer function).
7. Refer to 16.6 Digital Debounce function for SD input.
Figure 14.5 TB2SC Register
page 185
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14.1 Operation Modes
14.1.1 One-Shot Mode
In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table
14.1.1.1 shows the one-shot mode specifications. Figure 14.1.1.1 shows the operation example in one-
shot mode. Figure 14.1.1.2 shows the ADCON0 to ADCON2 registers in one-shot mode.
Table 14.1.1.1 One-shot Mode Specifications
Item
Specification
Function
The CH2 to CH0 bits in the ADCON0 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
a selected pin is once converted to a digital code
A/D Conversion Start
Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
___________
The ADTRG pin input changes state from “H” to “L” after setting the
ADST bit to “1” (A/D conversion started)
A/D Conversion Stop
Condition
• A/D conversion completed (If a software trigger is selected, the ADST bit is
set to “0” (A/D conversion halted)).
• Set the ADST bit to “0”
Interrupt Request Generation Timing A/D conversion completed
Analog Input Pin
Select one pin from AN0 to AN7, AN30 to AN32, AN24
Readout of A/D Conversion Result Readout one of the AD0 to AD7 registers that corresponds to the selected pin
•Example when selecting AN2 to an analog input pin (Ch2 to CH0=0102)
A/D conversion started
A/D pin input voltage
sampling
AN
0
1
2
3
4
5
6
7
A/D pin conversion
AN
AN
AN
AN
AN
AN
AN
A/D interrupt request generated
Figure 14.1.1.1 Operation Example in One-Shot Mode
page 186
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
0
0
Bit symbol
Bit name
Function
RW
RW
b2 b1 b0
Analog Input Pin
Select Bit (2, 3)
0 0 0 : Select AN
0 0 1 : Select AN
0 1 0 : Select AN
0 1 1 : Select AN
1 0 0 : Select AN
1 0 1 : Select AN
1 1 0 : Select AN
1 1 1 : Select AN
0
1
2
3
4
5
6
7
CH0
CH1
RW
RW
CH2
b4 b3
MD0
MD1
RW
RW
A/D Operation Mode
Select Bit 0 (3)
0 0 : One-shot mode or delayed trigger mode
0,1
Trigger Select Bit
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
TRG
RW
RW
RW
A/D Conversion Start
Flag
0 : A/D conversion disabled
1 : A/D conversion started
ADST
See Table 14.2 A/D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
NOTES:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN30 to AN32 and AN24 can be used in the same way as AN
ADCON2 register to select the desired pin.
0 to AN7 . Use the ADGSEL1 to ADGSEL0 bits in the
3. After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using an another instruction.
A/D control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
Bit name
Function
RW
RW
A/D Sweep Pin
Select Bit
Invalid in one-shot mode
SCAN0
SCAN1
MD2
RW
A/D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
RW
RW
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
REF Connect Bit (2)
RW
RW
VCUT
V
1 : VREF connected
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting A/D
conversion.
A/D control register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A/D Conversion Method
Select Bit
b2 b1
A/D Input Group Select
Bit
ADGSEL0
ADGSEL1
0 0 : Select port P10 group (AN
0 1 : Select port P9 group (AN 3i
1 0 : Do not set
1 1 : Select port P9 group (AN 24
i
)
RW
RW
RW
RW
)
)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
See Table 14.2 A/D Conversion
Frequency Select
CKS2
Trigger Select Bit 1
Set to "0" in one-shot mode
RW
TRG1
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.1.2 ADCON0 to ADCON2 Registers in One-Shot Mode
page 187
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14.1.2 Repeat mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table
14.1.2.1 shows the repeat mode specifications. Figure 14.1.2.1 shows the operation example in repeat
mode. Figure 14.1.2.2 shows the ADCON0 to ADCON2 registers in repeat mode.
Table 14.1.2.1 Repeat Mode Specifications
Item
Specification
Function
The CH2 to CH0 bits in the ADCON0 register and the ADGSEL1 to ADGSEL0
bits in the ADCON2 register select pins. Analog voltage applied to a selected
pin is repeatedly converted to a digital code
A/D Conversion Start
Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A/D conversion started)
A/D Conversion Stop Condition Set the ADST bit to “0” (A/D conversion halted)
Interrupt Request Generation Timing None generated
Analog Input Pin
Select one pin from AN0 to AN7, AN30 to AN32 and AN24
Readout of A/D Conversion Result Readout one of the AD0 to AD7 registers that corresponds to the selected pin
•Example when selecting AN2 to an analog input pin (Ch2 toCH0=0102)
A/D pin input voltage
sampling
A/D pin conversion
A/D conversion started
AN
0
1
2
3
4
5
6
7
AN
AN
AN
AN
AN
AN
AN
Figure 14.1.2.1 Operation Example in Repeat Mode
page 188
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
0
1
Bit symbol
Bit name
Function
RW
RW
b2 b1 b0
Analog Input Pin
Select Bit (2, 3)
0 0 0 : Select AN
0 0 1 : Select AN
0 1 0 : Select AN
0 1 1 : Select AN
1 0 0 : Select AN
1 0 1 : Select AN
1 1 0 : Select AN
1 1 1 : Select AN
0
1
2
3
4
5
6
7
CH0
CH1
RW
RW
CH2
b4 b3
RW
RW
MD0
MD1
A/D Operation Mode
Select Bit 0 (3)
0 1 : Repeat mode
Trigger Select Bit
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
TRG
RW
RW
RW
A/D Conversion Start
Flag
0 : A/D conversion disabled
1 : A/D conversion started
ADST
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
NOTES:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN30 to AN32 and AN24 can be used in the same way as AN
ADCON2 register to select the desired pin.
0 to AN7. Use the ADGSEL1 to ADGSEL0 bits inthe
3. After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using an another instruction.
A/D control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
Bit name
Function
RW
RW
A/D Sweep Pin
Select Bit
Invalid in repeat mode
SCAN0
SCAN1
MD2
RW
RW
A/D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
RW
RW
RW
BITS
Refer to Table 14.2 A/D Conversion
CKS1
Frequency Select Bit 1
REF connect bit (2)
Frequency Select
VCUT
V
1 : VREF connected
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A/D conversion.
A/D control register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A/D Conversion Method
Select Bit
b2 b1
A/D Input Group Select
Bit
ADGSEL0
ADGSEL1
RW
RW
RW
RW
0 0 : Select port P10 group (AN i)
0 1 : Select port P9 group (AN 3i
1 0 : Do not set
1 1 : Select port P9 group (AN 24
)
)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
See Table 14.2 A/D Conversion
Frequency Select
CKS2
Trigger Select Bit 1
Set to "0" in repeat mode
RW
TRG1
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.2.2 ADCON0 to ADCON2 Registers in Repeat Mode
page 189
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14.1.3 Single Sweep Mode
In single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital
code. Table 14.1.3.1 shows the single sweep mode specifications. Figure 14.1.3.1 shows the operation
example in single sweep mode. Figure 14.1.3.2 shows the ADCON0 to ADCON2 registers in single
sweep mode.
Table 14.1.3.1 Single Sweep Mode Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the selected pins is converted one-by-one to a digital code
A/D Conversion Start Condition • When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A/D conversion started)
A/D Conversion Stop Condition • A/D conversion completed(When selecting a software trigger, the ADST bit
is set to “0” (A/D conversion halted)).
• Set the ADST bit to “0”
Interrupt Request Generation Timing A/D conversion completed
Analog Input Pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),
(1)
AN0 to AN7 (8 pins)
Readout of A/D Conversion Result Readout one of the AD0 to AD7 registers that corresponds to the selected pin
NOTE:
1. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to
the same group.
•Example when selecting AN0 to AN3 to analog input pins (SCAN1 to SCAN0=012)
A/D pin input voltage
sampling
A/D pin conversion
A/D conversion started
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
A/D interrupt request generated
Figure 14.1.3.1 Operation Example in Single Sweep Mode
page 190
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
1
0
2
Bit symbol
Bit name
Function
RW
RW
Analog Input Pin
Select Bit
Invalid in single sweep mode
CH0
CH1
RW
RW
CH2
b4 b3
MD0
MD1
RW
RW
A/D Operation Mode
Select Bit 0
1 0 : Single sweep mode or simultaneous
sample sweep mode
Trigger Select Bit
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
TRG
RW
RW
RW
A/D Conversion Start
Flag
0 : A/D conversion disabled
1 : A/D conversion started
ADST
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
Bit name
Function
RW
RW
When selecting single sweep mode
A/D Sweep Pin
SCAN0
(2)
b1 b0
Select Bit
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
MD2
RW
RW
A/D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
RW
RW
RW
BITS
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
(3)
VCUT
V
REF Connect Bit
1 : VREF connected
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN30 to AN32 can be used in the same way as AN
register to select the desired pin.
0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2
3. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREFconnected), wait for 1 µs or more before starting A/D
conversion.
A/D control register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A/D Conversion Method
Select Bit
b2 b1
A/D Input Group
Select Bit
ADGSEL0
ADGSEL1
0 0 : Select port P10 group (AN
0 1 : Select port P9 group (AN 3i
1 0 : Do not set
1 1 : Do not set
i
)
RW
RW
RW
RW
)
Reserved Bit
Set to “0”
(b3)
Refer to Table 14.2 A/D Conversion
Frequency Select
Frequency Select Bit 2
CKS2
Trigger Select Bit 1
Set to "0" in single sweep mode
RW
TRG1
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.3.2 ADCON0 to ADCON2 Registers in Single Sweep Mode
page 191
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14.1.4 Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a
digital code. Table 14.1.4.1 shows the repeat sweep mode 0 specifications. Figure 14.1.4.1 shows the
operation example in repeat sweep mode 0. Figure 14.1.4.2 shows the ADCON0 to ADCON2 registers in
repeat sweep mode 0.
Table 14.1.4.1 Repeat Sweep Mode 0 Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the selected pins is repeatedly converted to a digital code
A/D Conversion Start Condition • When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
• When the TRG bit in the ADCON0 register is “1” (Hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A/D conversion started)
A/D Conversion Stop Condition Set the ADST bit to “0” (A/D conversion halted)
Interrupt Request Generation Timing None generated
Analog Input Pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),
(1)
AN0 to AN7 (8 pins)
Readout of A/D Conversion Result Readout one of the AD0 to AD7 registers that corresponds to the selected pin
NOTE:
1. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to
the same group.
•Example when selecting AN0 to AN3 to analog input pins (SCAN1 to SCAN0=012)
A/D pin input voltage
sampling
A/D conversion started
A/D pin conversion
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
Figure 14.1.4.1 Operation Example in Repeat Sweep Mode 0
page 192
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
RW
RW
Analog Input Pin
Select Bit
Invalid in repeat sweep mode 0
CH0
CH1
RW
RW
CH2
b4 b3
MD0
MD1
RW
RW
A/D Operation Mode
Select Bit 0
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Trigger Select Bit
TRG
ADST
CKS0
RW
A/D Conversion Start
Flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
Frequency Select Bit 0
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
Bit name
A/D Sweep Pin
Function
RW
RW
When selecting repeat sweep mode 0
SCAN0
(2)
b1 b0
Select Bit
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
MD2
RW
A/D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
RW
RW
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
(3)
RW
RW
VCUT
V
REF Connect Bit
1 : VREF connected
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN30 to AN32 can be used in the same way as AN
register to select the desired pin.
0 to AN7. Use the ADGSEL1 to ADGSET0 bits in the ADCON2
3. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting A/D
conversion.
A/D control register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A/D Conversion Method
Select Bit
b2 b1
A/D Input Group
Select Bit
ADGSEL0
ADGSEL1
0 0 : Select port P10 group (AN
0 1 : Select port P9 group (AN 3i
1 0 : Do not set
i
)
RW
RW
RW
RW
)
1 1 : Do not set
Reserved Bit
Set to “0”
(b3)
Refer to Table 14.2 A/D Conversion
Frequency Select
Frequency Select Bit 2
CKS2
Trigger Select Bit 1
Set to "0" in repeat sweep mode 0
RW
TRG1
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.4.2 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 0
page 193
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14.1.5 Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltages applied to the all selected pins are converted to a digital code,
with mainly used in the selected pins. Table 14.1.5.1 shows the repeat sweep mode 1 specifications.
Figure 14.1.5.1 shows the operation example in repeat sweep mode 1. Figure 14.1.5.2
ADCON0 to ADCON2 registers in repeat sweep mode 1.
shows the
Table 14.1.5.1 Repeat Sweep Mode 1 Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register mainly select pins. Analog voltage
applied to the all selected pins is repeatedly converted to a digital code
Example : When selecting AN0
Analog voltage is converted to a digital code in the following order
AN0
AN1
AN0
AN2
AN0
AN3, and so on.
A/D Conversion Start Condition • When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A/D conversion started)
A/D Conversion Stop Condition Set the ADST bit to “0” (A/D conversion halted)
Interrupt Request Generation Timing None generated
Analog Input Pins Mainly Select from AN0 (1 pins), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins),
(1)
Used in A/D Conversions AN0 to AN3 (4 pins)
Readout of A/D Conversion Result Readout one of the AD0 to AD7 registers that corresponds to the selected pin
NOTE:
1. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to
the same group.
•Example when selecting AN0 to analog input pins (SCAN1 to SCAN0=002)
A/D pin input voltage
sampling
A/D pin conversion
A/D conversion started
AN
0
1
2
3
4
5
6
7
AN
AN
AN
AN
AN
AN
AN
Figure 14.1.5.1 Operation Example in Repeat Sweep Mode 1
page 194
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
1
1
Bit symbol
Bit name
Function
RW
RW
Analog Input Pin
Select Bit
Invalid in repeat sweep mode 1
CH0
CH1
RW
RW
CH2
b4 b3
MD0
MD1
RW
RW
A/D Operation Mode
Select Bit 0
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Trigger Select Bit
TRG
ADST
CKS0
RW
A/D Conversion Start
Flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
Frequency Select Bit 0
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
1
Bit symbol
Bit name
Function
RW
RW
When selecting repeat sweep mode 1
b1 b0
A/D Sweep Pin
SCAN0
(2)
Select Bit
0 0 : AN0 (1 pin)
0 1 : AN0 to AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
SCAN1
MD2
RW
RW
A/D Operation Mode
Select Bit 1
1 : Repeat sweep mode 1
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
RW
RW
RW
BITS
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
(3)
VCUT
VREF Connect Bit
1 : VREF connected
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN30 to AN32 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2
register to select the desired pin.
3. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A/D conversion.
A/D control register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D4h
After reset
00h
0
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A/D Conversion Method
Select Bit
b2 b1
A/D Input Group
Select Bit
ADGSEL0
ADGSEL1
0 0 : Select port P10 group (AN i)
0 1 : Select port P9 group (AN 3i)
1 0 : Do not set
RW
RW
RW
RW
1 1 : Do not set
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS2
Trigger Select Bit 1
Set to "0" in repeat sweep mode 1
RW
TRG1
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.5.2 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 1
page 195
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14.1.6 Simultaneous Sample Sweep Mode
In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-by-
one to a digital code. At this time, the input voltage of AN0 and AN1 are sampled simultaneously using two
circuits of sample and hold circuit. Table 14.1.6.1 shows the simultaneous sample sweep mode specifica-
tions. Figure 14.1.6.1 shows the operation example in simultaneous sample sweep mode. Figure
14.1.6.2 shows ADCON0 to ADCON2 registers and Figure 14.1.6.3 shows ADTRGCON registers in
simultaneous sample sweep mode. Table 14.1.6.2 shows the trigger select bit setting in simultaneous
sample sweep mode. In simultaneous sample sweep mode, Timer B0 underflow can be selected as a
trigger by combining software trigger, ADTRG trigger, Timer B2 underflow, Timer B2 interrupt generation
frequency setting counter underflow or A/D trigger mode of Timer B.
Table 14.1.6.1 Simultaneous Sample Sweep Mode Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the selected pins is converted one-by-one to a digital code. At this time, the
input voltage of AN0 and AN1 are sampled simultaneously.
When the TRG bit in the ADCON0 register is "0" (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
When the TRG bit in the ADCON0 register is "1" (hardware trigger)
The trigger is selected by TRG1 and HPTRG0 bits (See Table 14.1.6.2)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A/D conversion started)
A/D Conversion Start Condition
Timer B0, B2 or Timer B2 interrupt generation frequency setting counter
underflow after setting the ADST bit to “1” (A/D conversion started)
A/D conversion completed (If selecting software trigger, the ADST bit is
automatically set to "0".
A/D Conversion Stop Condition
Set the ADST bit to "0" (A/D conversion halted)
Interrupt Generation Timing A/D conversion completed
Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or
(1)
AN0 to AN7 (8 pins)
Readout of A/D conversion result Readout one of the AN0 to AN7 registers that corresponds to the selected pin
NOTE:
1. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to
the same group.
•Example when selecting AN
0
to AN
3
to analog input pins (SCAN1 to SCAN0=01
2
)
A/D pin input voltage
sampling
A/D pin conversion
A/D conversion started
AN
0
1
2
3
4
5
6
7
AN
AN
AN
AN
AN
AN
AN
A/D interrupt request generated
Figure 14.1.6.1 Operation Example in Simultaneous Sample Sweep Mode
page 196
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
1
0
2
Bit symbol
Bit name
Function
RW
RW
Analog Input Pin
Select Bit
Invalid in simultaneous sample sweep mode
CH0
CH1
RW
RW
CH2
b4 b3
RW
RW
MD0
MD1
A/D Operation Mode
Select Bit 0
1 0 : Single sweep mode or simultaneous
sample sweep mode
Refer to Table 14.1.6.2 Trigger Select Bit
Setting in Simultaneous Sample Sweep
Mode
Trigger Select Bit
TRG
ADST
CKS0
RW
A/D Conversion Start Fag 0 : A/D conversion disabled
1 : A/D conversion started
RW
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
Frequency Select Bit 0
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
Bit name
Function
RW
RW
When selecting simultaneous sample sweep
A/D Sweep Pin
mode
SCAN0
(2)
Select Bit
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
MD2
RW
RW
A/D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
RW
RW
RW
BITS
Refer to Table 14.2 A/D Conversion
CKS1
Frequency Select Bit 1
(3)
Frequency Select
VCUT
V
REF Connect Bit
1 : VREF connected
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN30 to AN32 can be used in the same way as AN
register to select the desired pin.
0 to AN7. Use the ADGSEL1 to ADGSET0 bits in the ADCON2
3. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A/D conversion.
A/D control register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
1
Bit symbol
SMP
Bit name
Function
RW
RW
Set to “1” in simultaneous sample
A/D Conversion Method
Select Bit
sweep mode
b2 b1
A/D Input Group
Select Bit
ADGSEL0
ADGSEL1
0 0 : Select port P10 group (AN
0 1 : Select port P9 group (AN 3i
1 0 : Do not set
i
)
RW
RW
RW
RW
)
1 1 : Do not set
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS2
Refer to Table 14.1.6.2 Trigger Select Bit
Setting in Simultaneous Sample Sweep
Mode
Trigger select bit 1
RW
TRG1
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTE:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.6.2 ADCON0 to ADCON2 Registers for Simultaneous Sample Sweep Mode
page 197
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D trigger control register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADTRGCON
Address
03D216
After reset
0
0
1
0016
Bit symbol
SSE
Bit name
Function
RW
RW
1 : Simultaneous sample sweep mode
or delayed trigger mode 0, 1
A/D Operation Mode
Select Bit 2
0 : Any mode other than delayed trigger
mode 0,1
A/D Operation Mode
Select Bit 3
DTE
RW
RW
RW
Refer to Table 14.1.6.2 Trigger Select
Bit Setting in Simultaneous Sample
Sweep Mode
AN0 Trigger Select Bit
HPTRG0
Set to "0" in simultaneous sample
sweep mode
AN1 Trigger Select Bit
HPTRG1
(b7-b4)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
NOTE:
1. If ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.6.3 ADTRGCON Register in Simultaneous Sample Sweep Mode
Table 14.1.6.2 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode
TRIGGER
Software trigger
TRG
TRG1 HPTRG0
-
-
-
0
1
1
Timer B0 underflow (1)
1
0
ADTRG
0
1
Timer B2 or Timer B2 interrupt generation frequency
setting counter underflow (2)
1
0
NOTE:
1. A count can be started for Timer B2, Timer B2 interrupt generation frequency setting counter underflow or
the INT5 pin falling edge as count start conditions of Timer B0.
2.Select Timer B2 or Timer B2 interrupt generation frequency setting counter using the TB2SEL bit in the
TB2SC register.
page 198
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14.1.7 Delayed Trigger Mode 0
In delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a
digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The
Timer B0 underflow starts a single sweep conversion. After completing the AN0 pin conversion, the AN1
pin is not sampled and converted until the Timer B1 underflow is generated. When the Timer B1 under-
flow is generated, the single sweep conversion is restarted with the AN1 pin. Table 14.1.7.1 shows the
delayed trigger mode 0 specifications. Figure 14.1.7.1 shows the operation example in delayed trigger
mode 0. Figure 14.1.7.2 and Figure 14.1.7.3 show each flag operation in the ADSTAT0 register that
corresponds to the operation example. Figure 14.1.7.4 shows the ADCON0 to ADCON2 registers in
delayed trigger mode 0. Figure 14.1.7.5 shows the ADTRGCON register in delayed trigger mode 0 and
Table 14.1.7.2 shows the trigger select bit setting in delayed trigger mode 0.
Table 14.1.7.1 Delayed Trigger Mode 0 Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits in
the ADCON2 register select pins. Analog voltage applied to the input voltage of the
selected pins are converted one-by-one to the digital code. At this time, Timer B0 under
flow generation starts AN0 pin conversion. Timer B1 underflow generation starts con
version after the AN1 pin. (1)
A/D Conversion Start
AN0 pin conversion start condition
•When Timer B0 underflow is generated if Timer B0 underflow is generated again
before Timer B1 underflow is generated , the conversion is not affected
•When Timer B0 underflow is generated during A/D conversion of pins after the AN1
pin, conversion is halted and the sweep is restarted from AN0 pin
AN1 pin conversion start condition
•When Timer B1 underflow is generated during A/D conversion of the AN0 pin, the
input voltage of the AN1 pin is sampled. The AN1 conversion and the rest of the
sweep start when AN0 conversion is completed.
A/D Conversion Stop
Condition
•When single sweep conversion from the AN0 pin is completed
(2)
•Set the ADST bit to "0" (A/D conversion halted)
Interrupt Request
Generation Timing
Analog Input Pin
A/D conversion completed
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and
(3)
AN0 to AN7 (8 pins)
Readout of A/D Conversion Result Readout one of the AN0 to AN7 registers that corresponds to the selected pins
NOTES:
1. Set the larger value than the value of the timer B0 register to the timer B1 register.
2. Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 0. When write “1”, unexpected
interrupts may be generated.
3. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to the same
group.
page 199
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
•Example when selecting AN0 to AN3 to analog input pins (SCAN1 to SCAN0=012)
•Example 1: When Timer B1 underflow is generated during AN0 pin conversion
A/D pin input
voltage sampling
Timer B0 underflow
Timer B1 underflow
A/D pin conversion
AN
AN
AN
AN
0
1
2
3
•Example 2: When Timer B1 underflow is generated after AN0 pin conversion
Timer B0 underflow
Timer B1 underflow
AN
AN
AN
AN
0
1
2
3
•Example 3: When Timer B0 underflow is generated during A/D conversion of any pins except AN0 pin
Timer B0 underflow
Timer B0 underflow
(Abort othrt pins conversion)
Timer B1 underflow
Timer B1 under flow
AN
AN
AN
AN
0
1
2
3
•Example 4: When Timer B0 underflow is generated again before Timer B1 underflow is generated
after Timer B0 underflow generation
Timrt B0 underflow
Timer B0 underflow
(An interrupt does not affect A/D conversion)
Timer B1 underflow
AN
AN
AN
AN
0
1
2
3
Figure 14.1.7.1 Operation Example in Delayed Trigger Mode 0
page 200
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
•Example when selecting AN0 to AN3 to analog input pins (SCAN1 to SCAN0=012)
•Example 1: When Timer B1 underflow is generated during AN0 pin conversion
A/D pin input
voltage sampling
Timer B0 underflow
Timer B1 underflow
A/D pin conversion
AN0
AN1
AN2
AN3
"1"
ADST flag
"0"
Do not set to "1" by program
"1"
ADERR0 flag
"0"
"1"
ADERR1 flag
"0"
"1"
ADTCSF flag
"0"
"1"
ADSTT0 flag
"0"
"1"
ADSTT1 flag
"0"
"1"
ADSTRT0 flag
"0"
Set to “0" by program
"1"
ADSTRT1 flag
"0"
"1"
IR bit in the ADIC
register
"0"
Set to "0" by an interrupt request acknowledgement or a program
•Example 2: When Timer B1 underflow is generated after AN0 pin conversion
Timer B0 underflow
Timer B1 underflow
AN0
AN1
AN2
AN3
"1"
ADST flag
"0"
Do not set to "1" by program
"1"
ADERR0 flag
"0"
"1"
ADERR1 flag
"0"
"1"
ADTCSF flag
"0"
"1"
ADSTT0 flag
"0"
"1"
ADSTT1 flag
"0"
"1"
ADSTRT0 flag
"0"
Set to "0" by program
"1"
ADSTRT1 flag
"0"
IR bit in the ADIC
"1"
register
"0"
Set to "0" by an interrupt request acknowledgement or a program
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
Figure 14.1.7.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation
Example in Delayed Trigger Mode 0 (1)
page 201
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
•Example 3: When Timer B0 underflow is generated during A/D pin conversion of any pins except AN0 pin
Timer B0 underflow
(Abort othrt pins conversion )
A/D pin input
voltage sampling
Timer B0 underflow
Timer B1 underflow
Timer B1 underflow
A/D pin conversion
AN0
AN1
AN2
AN3
"1"
"0"
ADST flag
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
IR bit in the ADIC"1"
"0"
register
Set to "0" by interrupt request acknowledgement or a program
•Example 4: After Timer B0 underflow is generated and when Timer B0 underflow is generated again
before Timer B1 underflow is genetaed
Timrt B0 underflow
Timer B0 underflow
(An interrupt does not affect A/D conversion)
Timer B1 underflow
AN0
AN1
AN2
AN3
"1"
ADST flag
"0"
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
-
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
"1"
"0"
IR bit in the ADIC
register
Set to "0" by interrupt request acknowledgement or a program
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
Figure 14.1.7.3 Each Flag Operation in ADSTAT0 Register Associated with the Operation
Example in Delayed Trigger Mode 0 (2)
page 202
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
0
0
0 1 1 1
Bit symbol
Bit name
Function
RW
RW
b2 b1 b0
Analog Input Pin
Select Bit
CH0
CH1
1 1 1 : Set to "111b" in delayed trigger
mode 0
RW
RW
CH2
b4 b3
RW
RW
MD0
MD1
A/D Operation Mode
Select Bit 0
0 0 : One-shot mode or delayed trigger mode
0,1
Trigger Select Bit
Refer to Table 14.1.7.2 Trigger Select Bit
Setting in Delayed Trigger Mode 0
TRG
RW
RW
RW
A/D Conversion Start
0 : A/D conversion disabled
1 : A/D conversion started
ADST
(2)
Flag
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
NOTES:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. Do not write “1” in delayed trigger mode 0. When write, set to "0".
A/D control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
Bit name
Function
When selecting delayed trigger sweep mode 0
RW
RW
A/D Sweep Pin
SCAN0
(2)
b1 b0
Select Bit
0 0: AN
0 1: AN
1 0: AN
1 1: AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
MD2
RW
RW
A/D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
RW
RW
RW
BITS
Refer to Table 14.2 A/D Conversion
CKS1
Frequency Select Bit 1
(3)
Frequency Select
VCUT
V
REF Connect Bit
1 : VREF connected
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN30 to AN32 can be used in the same way as AN
register to select the desired pin.
0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2
3. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A/D conversion.
A/D control register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
0
1
Bit symbol
SMP
Bit name
Function
RW
RW
A/D Conversion Method
1 : With sample and hold
(2)
Select Bit
b2 b1
A/D Input Group
Select Bit
ADGSEL0
ADGSEL1
0 0 : Select port P10 group (AN
0 1 : Select port P9 group (AN 3i
1 0 : Do not set
1 1 : Do not set
i
)
RW
RW
RW
RW
)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS2
Refer to Table 14.1.7.2 Trigger Select Bit
Setting in Delayed Trigger Mode 0
Trigger Select Bit 1
RW
TRG1
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. Set to “1” in delayed trigger mode 0.
Figure 14.1.7.4 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 0
page 203
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D trigger control register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADTRGCON
Address
03D216
After reset
1
1
1
1
0016
Bit symbol
SSE
Bit name
Function
RW
Simultaneous sample sweep mode or
delayed trigger mode 0,1
A/D Operation Mode
Select Bit 2
RW
Delayed trigger mode 0, 1
A/D Operation Mode
Select Bit 3
DTE
RW
RW
RW
Refer to Table 14.1.7.2 Trigger Select
Bit Setting in Delayed Trigger Mode 0
AN0 Trigger Select Bit
HPTRG0
HPTRG1
AN1 Trigger Select Bit
Refer to Table 14.1.7.2 Trigger Select
Bit Setting in Delayed Trigger Mode 0
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
NOTE:
1. If ADTRGCON reigster is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.7.5 ADTRGCON Register in Delayed Trigger Mode 0
Table 14.1.7.2 Trigger Select Bit Setting in Delayed Trigger Mode 0
Trigger
HPTRG1
1
TRG
0
TRG1
0
HPTRG0
1
Timer B0, B1 underflow
page 204
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14.1.8 Delayed Trigger Mode 1
In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a
digital code. When the input of the ADTRG pin (falling edge) changes state from “H” to “L”, a single sweep
conversion is started. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted
until the second ADTRG pin falling edge is generated. When the second ADTRG falling edge is generated,
The single sweep conversion of the pins after the AN1 pin is restarted. Table 14.1.8.1 shows the delayed
trigger mode 1 specifications. Figure 14.1.8.1 shows the operation example of delayed trigger mode 1.
Figure 14.1.8.2 to Figure 14.1.8.3 show each flag operation in the ADSTAT0 register that corresponds to
the operation example. Figure 14.1.8.4 shows the ADCON0 to ADCON2 registers in delayed trigger
mode 1. Figure 14.1.8.5 shows the ADTRGCON register in delayed trigger mode 1 and Table 15.1.8.2
shows the trigger select bit setting in delayed trigger mode 1.
Table 14.1.8.1 Delayed Trigger Mode 1 Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits
in the ADCON2 register select pins. Analog voltages applied to the selected pins are
converted one-by-one to a digital code. At this time, the ADTRG pin
falling edge starts AN0 pin conversion and the second ADTRG pin falling edge starts
conversion of the pins after AN1 pin
A/D Conversion Start
Condition
AN0 pin conversion start condition
The ADTRG pin input changes state from “H” to “L” (falling edge)(1)
AN1 pin conversion start condition (2)
The ADTRG pin input changes state from “H” to “L” (falling edge)
•When the second ADTRG pin falling edge is generated during or after A/D
conversion of the AN0 pin, input voltage of AN1 pin is sampled at the time of ADTRG
falling edge. The conversion of AN1 and the rest of the sweep starts when AN0
conversion is completed.
•When the ADTRG pin falling edge is generated again during single sweep conver
sion of pins after the AN1 pin, the conversion is not affected
A/D Conversion Stop
Condition
•A/D conversion completed
(3)
•Set the ADST bit to "0" (A/D conversion halted)
Interrupt Request
Generation Timing
Analog Input Pin
Single sweep conversion completed
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and
AN0 to AN7 (8 pins)(4)
Readout of A/D Conversion Result Readout one of the AN0 to AN7 registers that corresponds to the selected pins
NOTES:
___________
1. Do not generate the next ADTRG pin falling edge after the AN1 pin conversion is started until all selected pins
___________
complete A/D conversion. When an ADTRG pin falling edge is generated again during A/D conversion, its trigger
___________
is ignored. The falling edge of ADTRG pin, which was input after all selected pins complete A/D conversion, is
considered to be the next AN0 pin conversion start condition.
___________
___________
2. The ADTRG pin falling edge is detected synchronized with the operation clock φAD. Therefore, when the ADTRG pin
falling edge is generated in shorter periods than φAD, the second _A__D__T__R__G__ pin falling edge may not be detected. Do
___________
not generate the ADTRG pin falling edge in shorter periods than φAD.
3. Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write “1”, unexpected
interrupts may be generated.
4. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to the same
group.
page 205
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
•Example when selecting AN0 to AN3 to analog input pins (SCAN1 to SCAN0=012)
•Example 1: When ADTRG pin falling edge is generated during AN0 pin conversion
A/D pin input
voltage sampling
A/D pin conversion
ADTRG pin input
AN
0
1
2
3
AN
AN
AN
•Example 2: When ADTRG pin falling edge is generated again after AN0 pin conversion
ADTRG pin input
AN
0
1
2
3
AN
AN
AN
•Example 3: When ADTRG pin falling edge is generated more than two times after AN0 pin conversion
ADTRG pin input
(valid after single sweep conversion)
AN
0
1
2
3
(invalid)
AN
AN
AN
Figure 14.1.8.1 Operation Example in Delayed Trigger Mode1
page 206
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
•Example when selecting AN0 to AN3 to analog input pins (SCAN1 to SCAN0=012)
•Example 1: When ADTRG pin falling edge is generated during AN0 pin conversion
A/D pin input
voltage sampling
A/D pin conversion
ADTRG pin input
AN0
AN1
AN2
AN3
"1"
ADST flag
"0"
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
IR bit in the ADIC"1"
"0"
register
Set to "0" by interrupt request acknowledgement or a program
•Example 2: When ADTRG pin falling edge is generated again after AN0 pin conversion
ADTRG pin input
AN0
AN1
AN2
AN3
"1"
"0"
ADST flag
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
IR bit in the ADIC
register
"1"
"0"
Set to "0" by interrupt request acknowledgment or a program
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
Figure 14.1.8.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example
in Delayed Trigger Mode 1 (1)
page 207
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
•Example 3: When ADTRG input falling edge is generated more than two times after AN0 pin conversion
A/D pin input
voltage sampling
A/D pin conversion
ADTRG pin input
(valid after single sweep conversion)
AN
0
1
2
3
(invalid)
AN
AN
AN
"1"
"0"
ADST flag
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
"1"
"0"
IR bit in the ADIC
register
Set to "0" when interrupt request acknowledgement or a program
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
Figure 14.1.8.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example
in Delayed Trigger Mode 1 (2)
page 208
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D control register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
0
0
0 1 1 1
Bit symbol
Bit name
Function
RW
RW
b2 b1 b0
Analog Input Pin
Select Bit
1 1 1 : Set to "111b" in delayed trigger
mode 1
CH0
CH1
RW
RW
CH2
b4 b3
RW
RW
MD0
MD1
A/D Operation Mode
Select Bit 0
0 0 : One-shot mode or delayed trigger mode
0,1
Trigger Select Bit
Refer to Table 14.1.8.2 Trigger Select Bit
Setting in Delayed Trigger Mode 1
TRG
RW
RW
RW
A/D Conversion Start
0 : A/D conversion disabled
1 : A/D conversion started
ADST
(2)
Flag
Refer to Table 14.2 A/D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
NOTES:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. Do not write “1” in delayed trigger mode 1. When write, set to "0".
A/D control register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
Bit name
Function
When selecting delayed trigger mode 1
RW
RW
A/D Sweep Pin
SCAN0
(2)
b1 b0
Select Bit
0 0: AN
0 1: AN
1 0: AN
1 1: AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
MD2
RW
RW
A/D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
RW
RW
RW
BITS
Refer to Table 14.2 A/D Conversion
CKS1
Frequency Select Bit 1
REF Connect Bit (3)
Frequency Select
VCUT
V
1 : VREF connected
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN30 to AN32 can be used in the same way as AN
register to select the desired pin.
0 to AN7. Use the ADGSEL1 to ADGSET0 bits in the ADCON2
3. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before startingA/D
conversion.
A/D control register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
1
0
1
Bit symbol
SMP
Bit name
Function
RW
RW
A/D Conversion Method
1 : With sample and hold
(2)
Select Bit
b2 b1
A/D Input Group
Select Bit
ADGSEL0
ADGSEL1
0 0 : Select port P10 group (AN
0 1 : Select port P9 group (AN 3i
1 0 : Do not set
i
)
RW
RW
RW
RW
)
1 1 : Do not set
Reserved Bit
Set to “0”
(b3)
Refer to Table 14.2 A/D Conversion
Frequency Select
Frequency Select Bit 2
CKS2
Refer to Table 14.1.8.2 Trigger Select Bit
Setting in Delayed Trigger Mode 1
Trigger Select Bit 1
RW
TRG1
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
NOTES:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. Set to “1” in delayed trigger mode 1.
Figure 14.1.8.4 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 1
page 209
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
A/D trigger control register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADTRGCON
Address
03D216
After reset
1
1
0
0
0016
Bit symbol
SSE
Bit name
Function
RW
RW
Simultaneous sample sweep mode or
delayed trigger mode 0,1
A/D Operation Mode
Select Bit 2
Delayed trigger mode 0, 1
A/D Operation Mode
Select Bit 3
DTE
RW
Refer to Table 14.1.8.2 Trigger Select
Bit Setting in Delayed Trigger Mode 1
AN0 Trigger Select Bit
HPTRG0
HPTRG1
RW
RW
Refer to Table 14.1.8.2 Trigger Select
Bit Setting in Delayed Trigger Mode 1
AN1 Trigger Select Bit
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
NOTE:
1. If ADTRGCON is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.8.5 ADTRGCON Register in Delayed Trigger Mode 1
Table 14.1.8.2 Trigger Select Bit Setting in Delayed Trigger Mode 1
Trigger
HPTRG1
0
TRG
0
TRG1
1
HPTRG0
0
ADTRG
page 210
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14.2 Resolution Select Function
The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to “1” (10-bit
precision), the A/D conversion result is stored into bits 0 to 9 in the A/D register i (i=0 to 7). When the BITS
bit is set to “0” (8-bit precision), the A/D conversion result is stored into bits 0 to 7 in the ADi register.
14.3 Sample and Hold
When the SMP bit in the ADCON 2 register is set to “1” (with the sample and hold function), A/D conver-
sion rate per pin increases to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. The
sample and hold function is available in one-shot mode, repeat mode, single sweep mode, repeat sweep
mode 0 and repeat sweep mode 1. In these modes, start A/D conversion after selecting whether the
sample and hold circuit is to be used or not. In simultaneous sample sweep mode, delayed trigger mode
0 or delayed trigger mode 1, set to use the Sample and Hold function before starting A/D conversion.
14.4 Power Consumption Reducing Function
When the A/D converter is not used, the VCUT bit in the ADCON1 register isolates the resistor ladder of
the A/D converter from the reference voltage input pin (VREF). Power consumption is reduced by shutting
off any current flow into the resistor ladder from the VREF pin.
When using the A/D converter, set the VCUT bit to “1” (VREF connected) before setting the ADST bit in the
ADCON0 register to “1” (A/D conversion started). Do not set the ADST bit and VCUT bit to “1” simulta-
neously, nor set the VCUT bit to “0” (VREF unconnected) during A/D conversion.
page 211
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
14. A/D Converter
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
14.5 Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 14.5.1 has to be
completed within a specified period of time. T (sampling time) as the specified time. Let output imped-
ance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of
the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256
in the 8-bit mode).
1
t
c(R0+R)
VC is generally VC = VIN{1-e
}
X
X
Y
And when t = T, VC=VIN-
VIN=VIN(1-
)
Y
T
=
1
X
Y
c(R0+R)
e
1
X
Y
-
T = ln
C(R0+R)
T
Hence,
R0 = -
- R
X
Y
C•ln
Figure 14.5.1 shows analog input pin and externalsensor equivalent circuit. When the difference be-
tween VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins. VC changes
from 0 to VIN-(0.1/1024) VIN in timer T. (0.1/1024) means that A/D precision drop due to insufficient
capacitor chage is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is
the value of absolute precision added to 0.1LSB. When f(XIN) = 10MHz, T=0.3µs in the A/D conversion
mode with sample & hold. Output inpedance R0 for sufficiently charging capacitor C within time T is
determined as follows.
T = 0.3µs, R = 7.8kΩ, C = 1.5pF, X = 0.1, and Y = 1024. Hence,
-6
0.3X10
3
3
R0 = -
- 7.8 X 10
13.9 X 10
0.1
-12
1.5X10 •ln
1024
Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D con-
verter turns out of be approximately 13.9kΩ.
Microcomputer
Sensor equivalent
circuit
R (7.8kΩ) (1)
R0
VIN
(1)
Sampling time
C (1.5pF)
3
VC
Sample-and-hold function enabled:
Sample-and-hold function disabled:
φAD
2
φAD
NOTES:
1. Reference value
Figure 14.5.1 Analog Input Pin and External Sensor Equivalent Circuit
page 212
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
15. CRC Calculation Circuit
15. CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses
16
12
5
16
15
2
a generator polynomial of CRC_CCITT (X + X + X + 1) or CRC-16 (X + X + X + 1) to generate
CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of bytes. The code
is updated in the CRC data register everytime one byte of data is transferred to a CRC input register. The
data register needs to be initialized before use. Generation of CRC code for one byte of data is completed
in two machine cycles.
Figure 15.1 shows the block diagram of the CRC circuit. Figure 15.2 shows the CRC-related registers.
Figure 15.3 shows the calculation example using the CRC_CCITT operation.
15.1. CRC Snoop
The CRC circuit includes the ability to snoop reads and writes to certain SFR addresses. This can be
used to accumulate the CRC value on a stream of data without using extra bandwidth to explicitly write
data into the CRCIN register. All SFR addresses after 002016 are subject to the CRC snoop. The CRC
snoop is useful to snoop the writes to a UART TX buffer, or the reads from a UART RX buffer.
To snoop an SFR address, the target address is written to the CRC snoop Address Register (bits 9 to
0 in the CRCSAR register). The two most significant bits in this register enable snooping on reads or
writes to the target address. If the target SFR is written to by the CPU or DMA, and the CRC snoop write
bit is set (the CRCSW bit is set to "1"), the CRC will latch the data into the CRCIN register. The new
CRC code will be set in the CRCD register.
Similarly, if the target SFR is read by the CRC or DMA, and the CRC snoop read bit is set (the CRCSR
bit is set to "1"), the CRC will latch the data from the target into the CRCIN register and calculate the
CRC.
The CRC circuit can only calculate CRC codes on data byte at a time. Therefore, if a target SFR is
accessed in a word (16 bit) bus cycle, only the byte of data going to or from the target snooped into
CRCIN, the other byte of the word access is ignored.
Data bus high-order
Data bus low-order
Eight low-order bits
CRCD register (16)
Eight high-order bits
(Address 03BD16, 03BC16
)
SnoopB
lock
CRC code generating circuit
Snoop Address
Equal?
16
12
5
16
15
2
x
+ x + x + 1 OR
x
+ x + x + 1
CRC input register (8)
(Address 03BE16
)
Snoop
enable
Address Bus
Figure 15.1 CRC circuit block diagram
page 213
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
15. CRC Calculation Circuit
CRC Data Register
(b15)
b7
(b8)
b0 b7
Symbol
CRCD
Address
03BD16 to 03BC16
After Reset
Undefined
b0
Function
RW
RW
Setting Range
CRC calculation result output
000016 to FFFF16
CRC Input Register
b7
b0
Symbol
CRCIN
Address
03BE16
After Reset
Undefined
Setting Range
Function
RW
RW
Data input
0016 to FF16
CRC Mode Register
b7
b0
Symbol
CRCMR
Address
03B616
After Reset
0XXXXXX0
2
Bit Symbol
BitName
Function
RW
RW
0: X16+X12+X5+1 (CRC-CCITT)
1: X16+X15+X2+1 (CRC-16)
CRCmodepolynomial
selectionbit
CRCPS
Nothing is assigned. If necessary, set to 0.
(b6-b1)
When read, the content is undefined
0: LSB first
1: MSB first
CRCMS CRCmodeselectionbit
RW
SFR Snoop Address Register
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
After Reset
CRCSAR
03B516 to 03B416
00XXXXXX XXXXXXXX2
Bit Symbol
CRCSAR9-0
Bit Name
Function
RW
RW
CRC mode polynomial
selection bit
SFR address to snoop
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
(b13-b10)
CRCSR
CRC snoop on read
enable bit
0: Disabled
1: Enabled(1)
RW
RW
CRC snoop on write
enable bit
0: Disabled
1: Enabled(1)
CRCSW
NOTE:
1. Set bits CRCSR and CRCSW to 0 if the PLC07 bit in the PLC0 register is set to 1 (PLL on) and the PM20 bit in
the PM2 register is set to 0 (SFR access 2 wait).
Figure 15.2. CRCD, CRCIN, CRCMR, CRCSAR Register
page 214
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
15. CRC Calculation Circuit
b15
b0
(1) Setting 000016 (initial value)
CRD data register CRCD
[03BD16, 03BC16
]
b7
b0
(2) Setting 0116
CRC input register CRCIN
[03BE16
]
2 cycles
After CRC calculation is complete
b0
b15
CRD data register CRCD
[03BD16, 03BC16
118916
]
Stores CRC code
The code resulting from sending 0116 in LSB first mode is (10000 0000).This the CRC code in the generating polynomial,
16
12
5
(X + X + X + 1), becomes the remainder resulting from dividing(1000 0000)X16 by ( 1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
Modulo-2 operation is
operation that complies
with the law given below.
LSB
MSB
MSB
1000 1000
1 0001 0000 0010 0001
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
LSB
9
8
1
1
Thus the CRC code becomes ( 1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary, set the CRC mode
selection bit to "1". CRC data register stores CRC code for MSB first mode.
b7
b0
CRC input register CRCIN
[03BE16
(3) Setting 2316
]
After CRC calculation is complete
b15
b0
CRD data register CRCD
[03BD16, 03BC16
0A4116
]
Stores CRC code
Figure 15.3. CRC Calculation
page 215
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
16. Programmable I/O Ports
Note
P60 to P63, P92 and P93 are not available in the 42-pin package.
The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 39 lines P15 to
P17, P6, P7, P8, P90 to P93, P10 for the 48-pin package, or 33 lines P15 to P17, P64 to P67, P7, P8, P90 to
P91, P10 for the 42-pin package. Each port can be set for input or output every line by using a direction
register, and can also be chosen to be or not be pulled high in sets of 4 lines.
Figures 16.1 to 16.4 show the I/O ports. Figure 16.5 shows the I/O pins.
Each pin functions as an I/O port, a peripheral function input/output.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin
is used as a peripheral function input, set the direction bit for that pin to “0” (input mode). Any pin used as an
output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set.
16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)
Figure 16.1.1 shows the direction registers.
This register selects whether the I/O port is to be used for input or output. The bits in this register corre-
spond one for one to each port.
16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)
Figure 16.2.1 shows the Pi registers.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the output data and a circuit to read the pin status. For ports
set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data
can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data
can be written to the port latch by writing to the Pi register. The data written to the port latch is output from
the pin. The bits in the Pi register correspond one for one to each port.
16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
Figure 16.3.1 shows the PUR0 to PUR2 registers.
The PUR0 to PUR2 registers select whether the ports, divided into groups of four ports, are pulled up or not.
The ports, selected by setting the bits in registers PUR2 to PUR0 to “1” (pull-up), are pulled up when the
direction registers are set to “0” (input mode). The ports are pulled up regardless of their function.
page 216
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
16.4 Port Control Register
Figure 16.4.1 shows the port control register.
When the P1 register is read after setting the PCR0 bit in the PCR register to “1”, the corresponding port
latch can be read no matter how the PD1 register is set.
16.5 Pin Assignment Control register (PACR)
Figure 16.5.1 shows the PACR. After reset set the PACR2 to PACR0 bit before you input and output it to
each pin. When the PACR register isn’t set up, the input and output function of some of the pins doesn’t
work.
PACR2 to PACR0 bits: control the pins enabled for use.
At reset, these bits are “000”.
In 48-pin package, set these bits to “1002”.
In 42-pin package, set these bits to “0012”.
U1MAP: controls the assignment of UART1 pins.
If the U1MAP bit is set to “0” (P67 to P64) the UART1 functions are mapped to P64/CTS1/RTS1,
P65/CLK1, P66/RxD1, and P67/TxD1.
If the U1MAP bit is set to “1” (P73 to P70) the UART1 functions are mapped to P70/CTS1/RTS1,
P71/CLK1, P72/RxD1, and P73/TxD1.
PACR is write protected by PRC2 bit in the PRCR register. PRC2 bit must be set immediately before the
write to PACR.
16.6 Digital Debounce function
Two digital debounce function circuits are provided. Level is determined when level is held, after applying
either a falling edge or rising edge to the pin, longer than the programmed filter width time. This enables
noise reduction.
________
_______ _____
This function is assigned to INT5/INPC17 and NMI/SD. Digital filter width is set in the NDDR register and
the P17DDR register respectively. Additionally, a digital debounce function is disabled to the port P17
input and port P85 input. Figure 16.6.1 shows the NDDR register and the P17DDR register.
Filter width :
(n+1) × 1/ f8 n: count value set in the NDDR register and P17DDr register
The NDDR register and the P17DDR register decrement count value with f8 as the count source. The
NDDR register and the P17DDR register indicate count time. Count value is reloaded if a falling edge or
a rising edge is applied to the pin.
The NDDR register and the P17DDR register can be set 0016 to FF16 when using the digital debounce
function. Setting to FF16 disables the digital filter. See Figure 16.6.2 for details.
page 217
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Pull-up selection
Direction register
P100 to P103
Port latch
Data bus
(1)
Analog input
Pull-up selection
Direction register
(inside dotted-line not included)
P15, P16
Port P1 control register
Data bus
(inside dotted-line included)
Port latch
(1)
P17
Input to respective peripheral functions
Digital
INPC17/INT5
debounce
Pull-up selection
Direction
register
"1"
P60, P61, P64, P65, P74 to P76,
P80, P81
Output
Port latch
Data bus
(1)
Input to respective peripheral functions
NOTE:
1.
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 16.1. I/O Ports (1)
page 218
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Pull-up selection
Direction
register
P70 to P73
"1"
Output
Port latch
Data bus
(1)
Switching
between
CMOS and
Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P82 to P84
Port latch
Data bus
(1)
Input to respective peripheral functions
Pull-up selection
Direction register
P62
, P6
6
, P7
7
Port latch
Data bus
(1)
Input to respective peripheral functions
NOTE:
1.
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 16.2. I/O Ports (2)
page 219
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Pull-up selection
Direction register
P63, P67
“1”
Output
Port latch
Data bus
(1)
Switching between CMOS and Nch
Pull-up selection
NMI Enable
P85
Direction register
Port latch
Data bus
(1)
Digital Debounce
NMI Interrupt Input
NMI Enable
SD
Pull-up selection
Direction register
P9
P10
1
, P9
2,
4
to P107
Data bus
Port latch
(1)
Analog input
Input to respective peripheral functions
NOTE:
1.
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 16.3. I/O Ports (3)
page 220
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Pull-up selection
Direction register
P9
0
(inside dotted-line
included)
1
P93
(inside dotted-line
not included)
Output
Data bus
Port latch
(1)
Analog input
Input to respective peripheral functions
Pull-up selection
Direction register
P87
Data bus
Port latch
(1)
fc
Rf
Pull-up selection
Direction register
Rd
P86
Data bus
Port latch
(1)
NOTE:
1.
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 16.4. I/O Ports (4)
page 221
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
CNVSS
CNVSS signal input
(1)
(1)
RESET
RESET signal input
NOTE:
1.
symbolizes a parasitic diode. Make sure the
input voltage on each port will not exceed Vcc.
Figure 16.5. I/O Pins
page 222
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Port Pi direction register (i=6 to 8, and 10) (1)
Symbol
PD6 to PD8
PD10
Address
03EE16, 03EF16, 03F216
03F616
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
0016
Bit symbol
Bit name
direction bit
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
PDi_0
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
PDi_7
Port Pi
0
1
2
3
4
5
6
7
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
direction bit
direction bit
direction bit
direction bit
direction bit
direction bit
direction bit
(Functions as an output port)
(i = 6 to 8, and 10)
NOTE:
1. Ports must be enabled using the PACR register.
In 48-pin package, set PACR2, PACR1, PACR0 to "100
In 42-pin package, set PACR2, PACR1, PACR0 to "001
2
"
"
2
Port P1 direction register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD1
Address
03E316
After reset
0016
RW
Bit symbol
(b4-b0)
Bit name
Function
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
PD1_5
PD1_6
PD1_7
Port P1
Port P1
Port P1
5
6
7
direction bit
direction bit
direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
RW
RW
RW
(Functions as an output port)
NOTE:
1. Ports must be enabled using the PACR register.
In 48-pin package, set PACR2, PACR1, PACR0 to "100
In 42-pin package, set PACR2, PACR1, PACR0 to "001
2
"
"
2
Port P9 direction register (1,2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD9
Address
03F316
After reset
XXXX0000
2
RW
RW
RW
Bit symbol
PD9_0
Bit name
Function
Port P9
Port P9
Port P9
Port P9
0
direction bit
direction bit
direction bit
direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
PD9_1
1
2
3
PD9_2
RW
RW
(Functions as an output port)
PD9_3
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
(B7-b4)
NOTE:
1. Make sure the PD9 register is written to by the next instruction after setting the PRC2 bit in the PRCR
register to "1" (write enabled).
2. Ports must be enabled using the PACR register.
Figure 16.1.1. PD1, PD6, PD7, PD8, PD9, and PD10 Registers
page 223
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Port Pi register (i=6 to 8 and 10) (1)
Symbol
P6 to P8
P10
Address
03EC16, 03ED16, 03F016
03F416
After reset
Indeterminate
Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Pi_0
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
Port Pi0 bit
Port Pi1 bit
Port Pi2 bit
Port Pi3 bit
Port Pi4 bit
Port Pi5 bit
Port Pi6 bit
Port Pi7 bit
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
0 : “L” level
1 : “H” level
Pi_6
(1)
Pi_7
(i = 6 to 8 and 10)
NOTE:
1. Ports must be enabled using the PACR register.
In 48-pin package, set PACR2, PACR1, PACR0 to "1002"
In 42-pin package, set PACR2, PACR1, PACR0 to "0012"
(1)
Port P1 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P1
Address
03E116
After reset
Indeterminate
RW
Bit symbol
Bit name
Function
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
(b4-b0)
The pin level on any I/O port which is
P1_5
P1_6
P1_7
Port P15 bit
Port P16 bit
Port P17 bit
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
RW
RW
RW
0 : “L” level
1 : “H” level
NOTE:
1. Ports must be enabled using the PACR register.
In 48-pin package, set PACR2, PACR1, PACR0 to "1002"
In 42-pin package, set PACR2, PACR1, PACR0 to "0012"
(1)
Port P9 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P9
Address
03F116
After reset
Indeterminate
RW
RW
Bit symbol
Bit name
Function
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
P9_0
Port P90 bit
P9_1
P9_2
Port P91 bit
Port P92 bit
Port P93 bit
RW
RW
RW
0 : “L” level
1 : “H” level
P9_3
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
(b7-b4)
NOTE:
1. Ports must be enabled using the PACR register.
In 48-pin package, set PACR2, PACR1, PACR0 to "1002"
In 42-pin package, set PACR2, PACR1, PACR0 to "0012"
Figure 16.2.1. P1, P6, P7, P8, P9, and P10 Registers
page 224
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
After reset
0016
Bit symbol
(b2-b0)
PU03
Bit name
Function
RW
RW
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
0 : Not pulled high
1 : Pulled high (1)
P15 to P17 pull-up
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
(b7-b4)
NOTE:
1. The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
After reset
00000000
2
Bit symbol
(b3-b0)
Bit name
Function
RW
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
PU14
PU15
PU16
PU17
P6
P6
P7
P7
0
4
0
4
to P6
to P6
to P7
to P7
3
7
3
7
pull-up
pull-up
pull-up
pull-up
RW
RW
RW
RW
0 : Not pulled high
1 : Pulled high (1)
NOTE:
1. The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FE16
After reset
0016
Bit symbol
PU20
Bit name
Function
RW
RW
RW
RW
P8
0
to P8
3
pull-up
0 : Not pulled high
1 : Pulled high (1)
PU21
PU22
P8
P9
4
0
to P8
to P9
7
3
pull-up
pull-up
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
(b3)
PU24
PU25
P10
P10
0
4
to P10
to P10
3
7
pull-up
pull-up
0 : Not pulled high
1 : Pulled high (1)
RW
RW
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
(b7-b6)
NOTE:
1. The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Figure 16.3.1. PUR0 to PUR2 Registers
page 225
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Port control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbpl
PCR
Address
03FF16
After reset
0016
Bit symbol
PCR0
Bit name
Function
RW
Port P1 control bit
Operation performed when the P1
register is read
0: When the port is set for input,
the input levels of P10 to P17
pins are read. When set for
output, the port latch is read.
1: The port latch is read
RW
regardless of whether the port
is set for input or output.
Nothing is assigned. In an attempt to write to these bits,
write “0”. The value, if read, turns out to be “0”.
(b7-b1)
Figure 16.4.1. PCR Register
Pin Assignment Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbpl
PACR
Address
025D16
After Reset
0016
Bit Symbol
Bit Name
Function
RW
Pin enabling bit
PACR0
PACR1
PACR2
001 : 42 pin
100 : 48 pin
All other values are reserved. Do
not use.
RW
RW
RW
Reserved bits
Nothing is assigned. When write,
set to “0”. When read, its
content is “0”.
(b6-b3)
U1MAP
UART1 pins assigned to
UART1 pin remapping bit
RW
0 : P6
1 : P7
7
3
to P6
to P7
4
0
NOTES:
1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to "1"(write
enable).
Figure 16.5.1. PACR Register
page 226
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
NMI Digital Debounce Register (1,2)
b7
b0
Symbol
NDDR
Address
033E16
After Reset
FF16
Function
Setting Range
0016 to FF16
RW
RW
If the set value =n,
- n = 0 to FE16; a signal with pulse width, greater than
(n+1)/f8, is input into NMI / SD
- n = FF16; the digital debounce filter is disabled and all
signals are input
NOTES:
1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to "1"(write
enable).
2. When using the NMI interrupt to exit from stop mode, set the NDDR registert to "FF16" before entering
stop mode.
P1
7
Digital Debounce Register(1)
b7
b0
Symbol
P17DDR
Address
033F16
After Reset
FF16
Function
Setting Range
0016 to FF16
RW
RW
If the set value =n,
- n = 0 to FE16; a signal with pulse width, greater than
(n+1)/f8, is input into INPC17/ INT5
- n = FF16; the digital debounce filter is disabled and all
signals are input
NOTE:
1. When using the INT5 interrupt to exit from stop mode, set the P17DDR registert to "FF16" before entering
stop mode.
Figure 16.6.1. NDDR and P17DDR Registers
page 227
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Digital Debounce Filter
Clock
f8
P85 / P17
Data Bus
Port In
Signal Out
To NMI and SD / INT5 and INPC17
Data Bus
Reload Value
(write)
Count Value
(read)
f8
Reload Value
Port In
FF
03
Signal Out
Count Value
03
02
01
00
FF
02
01
03
FF
3
1
2
4
5
Reload Value
(continued)
03
FF
Port In
(continued)
Signal Out
(continued)
01
FF
Count Value
(continued)
03
02
00
FF
03
02
FF
6
8
7
9
1. (Condition after reset). Reload = FF, Port In = signal Out continuosly.
2. Reload = 03. At edge of Port In != Signal Out, Counter gets Reload Value and
stats counting down.
3. Port In = Signal Out, counting stops.
4. At edge of Port In != Signal Out, Counter gets Reload Value and starts counting.
5. Counter underflows, stops, and Port In is driven to Signal Out.
6. At edge of Port In != Signal Out, counter gets Reload Value and starts counting.
7. Counter underflows, stops, and Port In is driven to Signal Out.
8. At edge of Port In != Signal Out, counter gets Reload Value and starts counting.
9. FF is written to Reload Value. Counter is stopped and loaded with FF.
Port In = Signal Out continuously.
Figure 16.6.2. Functioning of Digital Debounce Filter
page 228
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
16. Programmable I/O Ports
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 16.1. Unassigned Pin Handling in Single-chip Mode
Pin name
Connection
After setting for input mode, connect every pin to V SS via a resistor(pull-down);
or after setting for output mode, leave these pins open. (1, 2, 4)
Ports P1, P6 to P10
(3)
X
OUT
IN
Open
Connect via resistor to V CC (pull-up) (5)
Connect to VCC
X
AVCC
AVSS, VREF
Connect to VSS
NOTES:
1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until it is
switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode. Futhermore,
by considering a possibility that the contents of the direction registers could be changed by noise or noise-
induced runaway, it is recommended that the contents of the direction registers be periodically reset in software,
for the increased reliability of the program.
2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2
cm).
3. With external clock or VCC input to XIN pin.
4. When using the 48-pin package, set PACR2, PACR1, PACR0 to "100
PACR2, PACR1, PACR0 to "001 ".
2".When using the 42-pin package, set
2
5. When the main clock oscillation circuit is not used, set the CM05 bit in the CM0 register to “0” (main clock stops)
to reduce power consumption.
Microcomputer
Port P1, P6 to P10
(1)
(Input mode)
·
·
·
·
·
·
(Input mode)
(Output mode)
Open
X
IN
X
OUT
Open
V
CC
AVCC
AVSS
V
REF
V
SS
In single-chip mode
NOTE:
1. When using the 48-pin package, set PACR2, PACR1, PACR0 to "100
When using the 42pin-package, set PACR2, PACR1, PACR0 to "001 ".
2
".
2
Figure 16.7. Unassigned Pins Handling
page 229
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17. Flash Memory Version
17.1 Flash Memory Performance
The flash memory version is functionally the same as the mask ROM version except that it internally con-
tains flash memory.
In the flash memory version, the flash memory can perform in three rewrite mode : CPU rewrite mode,
standard serial I/O mode and parallel I/O mode.
Table 17.1 shows the flash memory version specifications. (Refer to Table 1.1 or Table 1.2 for the items not
listed in Table 17.1.)
Table 17.1. Flash Memory Version Specifications
Item
Specification
Flash memory operating mode
3 modes (CPU rewrite, standard serial I/O, parallel I/O)
Erase block
See Figure 17.2.1 to 17.2.3 Flash Memory Block Diagram
In units of word
Program method
Block erase
Erase method
Program, erase control method
Program and erase controlled by software command
All user blocks are write protected by bit FMR16.
Protect method
In addition, the block 0 and block 1 are write protected by bit FMR02
Number of commands
5 commands
Block 0 to 3 (program area)
(2)
100 times, 1,000 times (See Tables 1.7, 1.9, and 1.10)
100 times, 10,000 times (See Tables 1.7, 1.9, and 1.10)
Program/Erase
Endurance(1)
Block A and B (data are)
20 years (Topr = 55°C)
Data Retention
ROM code protection
NOTES:
Parallel I/O and standard serial I/O modes are supported.
1. Program and erase endurance definitionProgram and erase endurance are the erase endurance of each block. If
the program and erase endurance are n times (n=100,1,000,10,000), each block can be erased n times. For
example, if a 2-Kbyte block A is erased after writing 1 word data 1024 times, each to different addresses, this is
counted as one program and erasure.However, data cannot be written to the same address more than once
without erasing the block. (Rewrite disabled)
2. To use the limited number of erasure efficiently, write to unused address within the block instead of rewrite. Erase
block only after all possible address are used. For example, an 8-word program can be written 128 times before
erase is necessary. Maintaining an equal number of erasure between Block A and B will also improve efficiency.
We recommend keeping track of the number of times erasure is used.
page 230
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
Parallel I/O mode
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 17.2. Flash Memory Rewrite Modes Overview
Flash memory
rewrite mode
Function
CPU rewrite mode
Standard serial I/O mode
The user ROM area is rewrit-
ten when the CPU executes
software command
EW0 mode:
Rewrite in area other than
flash memory
The user ROM area is rewrit- The user ROM area is rewrit-
ten using a dedicated serial ten using a dedicated paral-
programmer.
lel programmer
Standard serial I/O mode 1:
Clock synchronous serial
I/O
Standard serial I/O mode 2:
UART
EW1 mode:
Rewrite in flash memory
Area which
can be rewritten
Operation
mode
User ROM area
Single chip mode
User ROM area
Boot mode
User ROM area
Parallel I/O mode
ROM
None
Serial programmer
Parallel programmer
programmer
17.1.1 Boot Mode
The MCU enters boot mode when a hardware reset is performed while a high-level ("H") signal is applied
to pins CNVSS and P86 or while an "H" signal is applied to pins CNVSS and P16 and a low-level ("L")
signal is applied to the P85. A program in the boot ROM area is executed.
The boot ROM area is reserved. The boot ROM area stores the rewrite control program for a standard
serial I/O mode before shipping. Do not rewrite the boot ROM area.
page 231
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.2 Memory Map
The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 17.2.1 to
17.2.3 show the flash memory block diagram. The user ROM area has space to store the microcomputer
operation program in single-chip mode and a separate 2-Kbyte space as the block A and B.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite,
standard serial input/output, and parallel input/output modes. However, if block 0 and 1 are rewritten in
CPU rewrite mode, setting the FMR02 bit in the FMR0 register to “1” (block 0, 1 rewrite enabled) and the
FMR16 bit in the FMR1 register to “1”(blocks 0 to 3 rewrite enabled) enable rewriting. Also, if blocks 2 to 3
are rewritten in CPU rewrite mode, setting the FMR16 bit in the FMR1 register to “1” (blocks 0 to 3 rewrite
enabled) enables writing. Setting the PM10 bit in the PM1 register to “1”(data area access enabled) for
block A and B enables to use.
00F00016
Block B :2K bytes (2)
00F7FF16
00F80016
Block A :2K bytes (2)
00FFFF16
0F000016
Block 3 : 32K bytes (5)
NOTES:
0F7FFF16
0F800016
1. To specify a block, use the maximum even address in the block.
2. Blocks A and B are enabled to use when the PM10 bit in the PM1
register is set to "1".
3. Blocks 0 and 1 are enabled for programs and erases when the
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
4. The boot ROM area is reserved. Do not access.
5. Blocks 2 and 3 are enabled for programs and erases when the
FMR16 bit in the FMR1 register is set to "1". (CPU rewrite mode
only)
Block 2 : 16K bytes (5)
0FBFFF16
0FC00016
Block 1 : 8K bytes (3)
0FDFFF16
0FE00016
0FF00016
4K bytes (4)
0FFFFF16
Block 0 : 8K bytes (3)
User ROM area
0FFFFF16
Boot ROM area
Figure 17.2.1. Flash Memory Block Diagram (ROM capacity 64K byte)
page 232
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
00F00016
00F7FF16
Block B :2K bytes (2)
00F80016
Block A :2K bytes (2)
00FFFF16
0F400016
Block 3 : 16K bytes (5)
NOTES:
1. To specify a block, use the maximum even address in the block.
2. Blocks A and B are enabled to use when the PM10 bit in the PM1
register is set to "1".
0F7FFF16
0F800016
3. Blocks 0 and 1 are enabled for programs and erases when the
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
4. The boot ROM area is reserved. Do not access.
5. Blocks 2 and 3 are enabled for programs and erases when the
FMR16 bit in the FMR1 register is set to "1". (CPU rewrite mode
only)
Block 2 : 16K bytes (5)
0FBFFF16
0FC00016
Block 1 : 8K bytes (3)
0FDFFF16
0FE00016
0FF00016
4K bytes (4)
0FFFFF16
Block 0 : 8K bytes (3)
0FFFFF16
User ROM area
Boot ROM area
Figure 17.2.2. Flash Memory Block Diagram (ROM capacity 48K byte)
page 233
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
00F00016
Block B :2K bytes (2)
00F7FF16
00F80016
Block A :2K bytes (2)
00FFFF16
NOTES:
1. To specify a block, use the maximum even address in the block.
2. Blocks A and B are enabled to use when the PM10 bit in the PM1
register is set to "1".
3. Blocks 0 and 1 are enabled for programs and erases when the
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
4. The boot ROM area is reserved. Do not access.
5. Blocks 2 are enabled for programs and erases when the FMR16 bit
in the FMR1 register is set to "1". (CPU rewrite mode only)
0FA00016
Block 2 : 8K bytes (5)
Block 1 : 8K bytes (3)
0FBFFF16
0FC00016
0FDFFF16
0FE00016
0FF00016
4K bytes (4)
0FFFFF16
Block 0 : 8K bytes (3)
User ROM area
0FFFFF16
Boot ROM area
Figure 17.2.3. Flash Memory Block Diagram (ROM capacity 24K byte)
page 234
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.3 Functions To Prevent Flash Memory from Rewriting
The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code
check function for standard input/output mode to prevent the flash memory from reading or rewriting.
17.3.1 ROM Code Protect Function
The ROM code protect function disables reading or changing the contents of the on-chip flash memory in
parallel I/O mode. Figure 17.3.1.1 shows the ROMCP address. The ROMCP address is located in a user
ROM area.
To enable ROM code protect, set the ROMCP1 bit to “002”, “012”, or “102” and set the bit 5 to bit 0 to
“1111112”.
To cancel ROM code protect, erase the block including the the ROMCP address in CPU rewrite mode or
standard serial I/O mode.
17.3.2 ID Code Check Function
Use the ID code check function in standard serial input/output mode. Unless the flash memory is blank,
the ID codes sent from the programmer and the seven bytes ID codes written in the flash memory are
compared to see if they match. If the ID codes do not match, the commands sent from the programmer
are not acknowledged. The ID code consists of 8-bit data, starting with the first byte, into addresses,
0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. The flash memory
has a program with the ID code set in these addresses.
page 235
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(5)
ROM Code Protect Control Address
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ROMCP
Address
0FFFFF16
Factory Setting
FF16
1
1
1
1
1
1
(4)
RW
RW
Bit Symbol
(b5-b0)
Bit Name
Function
Set to 1
Reserved Bit
b7 b6
ROM Code Protect Level
1 Set Bit (1, 2, 3, 4)
ROMCP1
RW
RW
00:
01: Enables protect
10:
11: Disables protect
}
NOTES:
1. When the ROM code protect is active by the ROMCP1 bit setting, the flash memory is protected
against reading or rewriting in parallel I/O mode.
2. Set the bit 5 to bit 0 to 111111
0 are set to values other than 111111
ROMCP1 bit to a value other than 11
2
when the ROMCP1 bit is set to a value other than 11
2. If the bit 5 to bit
2
, the ROM code protection may not become active by setting the
2.
3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard
serial I/O mode or CPU rewrite mode.
4. The ROMCP address is set to FF16 when a block, including the ROMCP address, is erased.
5. When a value of the ROMCP address is 0016 or FF16, the ROM code protect function is disabled.
Figure 17.3.1.1. ROMCP Address
Address
Undefined instruction vector
Overflow vector
ID1
ID2
0FFFDF16 to 0FFFDC16
0FFFE316 to 0FFFE016
0FFFE716 to 0FFFE416
0FFFEB16 to 0FFFE816
0FFFEF16 to 0FFFEC16
0FFFF316 to 0FFFF016
0FFFF716 to 0FFFF416
0FFFFB16 to 0FFFF816
0FFFFF16 to 0FFFFC16
BRK instruction vector
Address match vector
ID3
ID4
Single step vector
Watchdog timer vector
DBC vector
ID5
ID6
ID7
NMI vector
Reset vector
ROMCP
4 bytes
Figure 17.3.2.1. Address for ID Code Stored
page 236
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.4 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands.
Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board
without using a ROM programmer, etc. Verify the Program and the Block Erase commands are executed
only on blocks in the user ROM area.
For interrupts requested during an erasing operation in CPU rewrite mode, the M16C/26A Group flash
module offers an erase-suspend function which the erasing operation to be suspended, and access made
available to the flash. Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU
rewrite mode. Table 17.4.1 shows the differences between erase-write 0 (EW0) and erase-write 1 (EW1)
modes. 1 wait is required for the CPU erase-write control.
Table 17.4.1. EW0 Mode and EW1 Mode
Item
Operation mode
Area where
EW0 mode
Single chip mode
User ROM area
EW1 mode
Single chip mode
User ROM area
rewrite control
program can be placed
Area where
The rewrite control program must be The rewrite control program can be
rewrite control
program can be
executed
transferred to any area other than
the flash memory (e.g., RAM) before
being executed
executed in the user ROM area
Area which can be
rewritten
User ROM area
User ROM area
However, this excludes blocks
with the rewrite control program
• Program, block erase command
Cannot be executed in a block having
the rewrite control program
• Read status register command
Can not be used
Software command
Restrictions
None
Mode after programming Read Status Register mode
or erasing
Read Array mode
CPU state during auto-
write and auto-erase
Operation
Hold state (I/O ports retain the state
before the command is executed
(1)
Flash memory status
detection
• Read the FMR00, FMR06 and
FMR07 bits in the FMR0 register by FMR06, and FMR07 bits in a program
Read the FMR0 register's FMR00,
(2)
a program
• Execute the read status register
command and read the SR7, SR5
and SR4 bits
Condition for transferring
to erase-suspend (3)
Set the FMR40 and FMR41 bits in
The FMR40 bit in the FMR4 register
the FMR4 register to "1" by program. is set to "1" and the interrupt request of
NOTES:
1. Do not generate a DMA transfer.
2. Block 1 and 0 are enabled to rewrite by setting the FMR02 bit in the FMR0 register to "1" and
setting the FMR16 bit in the FMR1 register to "1". Block 2 to 3 are enabled to rewrite by setting the
FMR16 bit in the FMR1 register to "1".
3. The time, until entering erase suspend and reading flash is enabled, is maximum td (SR-ES) after
satisfying the conditions.
page 237
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.4.1 EW0 Mode
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU
rewrite mode enabled) and is ready to acknowledge the software commands. EW0 mode is selected by
setting the FMR11 bit in the FMR1 register to “0”.
When setting the FMR01 bit to “1”, set to “1” after first writing “0”. The software commands control pro-
gramming and erasing. The FMR0 register or the status register indicates whether a programming or
erasing operations is completed.
When entering the erase-suspend during the auto-erasing, set the FMR40 bit to “1” (erase-suspend
enabled) and the FMR41 bit to “1” (suspend request). And wait for td(SR-ES). After verifying the FMR46
bit is set to “1” (auto-erase stop), access to the user ROM area. When setting the FMR41 bit to “0” (erase
restart), auto-erasing is restarted.
17.4.2 EW1 Mode
EW1 mode is selected by setting the FMR11 bit to “1” after the FMR01 bit is set to “1”. (set to “1” after first
writing “0”). The FMR0 register indicates whether or not a programming or an erasing operation is com-
pleted. Do not execute the software commands of read status register in EW1 mode.
When an erase/program operation is initiated the CPU halts all program execution until the operation is
completed or erase-suspend is requested.
When enabling an erase suspend function, set the FMR40 bit to “1” (erase suspend enabled) and ex-
ecute block erase commands. Also, preliminarily set an interrupt to enter the erase-suspend to an inter-
rupt enabled status. After td(SR-ES) from an interrupt request and entering erase suspend, an interrupt
can be acknowledged.
When an interrupt request is generated, the FMR41 bit is automatically set to “1” (suspend request) and
an auto-erasing is halted. If an auto-erasing is not completed (the FMR00 bit is “0”) after an interrupt
process completed, set the FMR41 bit to “0” (erase restart) and execute block erase commands again.
page 238
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.5 Register Description
Figure 17.5.1 shows the flash memory control register 0 and flash memory control register 1. Figure 17.5.2
shows the flash memory control register 4.
17.5.1 Flash memory control register 0 (FMR0)
•FMR 00 Bit
This bit indicates the operation status of the flash memory. The bit is “0” during programming, erasing,
or erase-suspend mode; otherwise, the bit is “1”.
•FMR01 Bit
The microcomputer enables to acknowledge commands by setting the FMR01 bit to “1” (CPU rewrite
mode). To set this bit to “1”, it is necessary to set to “1” after first setting to “0”. Set this bit to “0” by only
writing “0”.
•FMR02 Bit
The combined setting of the FMR02 bit and the FMR16 bit enable to program and erase in the user
ROM area. See Table 17.5.2.1 for setting details. To set this bit to “1”, it is necessary to set to “1” after
first setting to “0”. Set this bit to “0” by only writing “0”. This bit is enabled only when the FMR01 bit is
“1” (CPU rewrite mode enable).
•FMSTP Bit
This bit resets the flash memory control circuits and minimizes power consumption in the flash
memory. Access to the flash memory is disabled when the FMSTP bit is set to “1”. Set the FMSTP bit
by a program in a space other than the flash memory.
Set the FMSTP bit to “1” if one of the following occurs:
•A flash memory access error occurs during erasing or programming in EW0 mode (FMR00 bit does
not switch back to “1” (ready)).
•Low-power consumption mode or on-chip oscillator low-power consumption mode is entered.
Figure 17.5.1.3 shows a flow chart illustrating how to start and stop the flash memory before and after
entering low power mode. Follow the procedure on this flow chart.
To enter stop or wait mode when CPU rewrite mode is disabled, do not set the FMR0 register. The
flash memory is automatically turned off when entering and turned back on when exiting.
•FMR06 Bit
This is a read-only bit indicating an auto-program operation status. This bit is set to “1” when a pro-
gram error occurs; otherwise, it is set to “0”. For details, refer to 17.8.4 Full Status Check.
•FMR07 Bit
This is a read-only bit indicating an auto-erase operation status. The bit is set to “1” when an erase
error occurs; otherwise, it is set to “0”. For details, refer to 17.8.4 Full Status Check.
Figure 17.5.1.1 shows a EW0 mode set/reset flowchart, figure 17.5.1.2 shows a EW1 mode set/reset
flowchart.
page 239
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.5.2 Flash memory control register 1 (FMR1)
•FMR11 Bit
EW1 mode is entered by setting the FMR11 bit to “1” (EW1 mode). This bit is enabled only when the
FMR01 bit is “1”.
•FMR16 Bit
The combined setting of the FMR02 bit and the FMR16 bit enables to program and erase in the user
ROM area. To set this bit to “1”, it is necessary to set to “1” after first setting to “0”. Set this bit to “0” by
only writing “0”. This bit is enabled only when the FMR01 bit is “1”.
•FMR17 Bit
If FMR17 bit is “1” (with wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the
access to block A and block B. Regardless of the content of the FMR17 bit, access to other block and
the internal RAM is determined by PM17 bit setting.
Set this bit to “1” (with wait state) when rewriting more than 100 times (U7 and U9).
Table 17.5.2.1. Protection using FMR16 and FMR02
FMR16
FMR02 Block A, Block B
Block 0, Block 1 other user block
0
0
1
1
0
1
0
1
write enabled
write enabled
write enabled
write enabled
write disabled
write disabled
write disabled
write enabled
write disabled
write disabled
write enabled
write enabled
17.5.3 Flash memory control register 4 (FMR4)
•FMR40 Bit
The erase-suspend function is enabled by setting the FMR40 bit is set to “1” (enabled).
•FMR41 Bit
When setting the FMR41 bit to “1” in a program during auto-erasing in EW0 mode the flash module
enters erase suspend mode. In EW1 mode, the FMR41 bit is automatically set to “1” (suspend re-
quest) when an interrupt request of an enabled interrupt is generated, the FMR41 bit is automatically
set to “1” (suspend request) and when an auto-erasing operation is restarted, set the FMR41 bit to “0”
(erase restart).
•FMR46 Bit
The FMR46 bit is set to “0” during auto-erasing execution and set to “1” during erase-suspend mode.
Do not access to flash memory while this bit is “0”.
page 240
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR0
Address
01B716
After reset
00000001
2
0
0
Bit symbol
Bit name
Function
RW
RO
0: Busy (during writing or erasing)
1: Ready
RY/BY status flag
FMR00
FMR01
0: Disables CPU rewrite mode
(Disables software command)
1: Enables CPU rewrite mode
(Enables software commands)
CPU rewrite mode select bit
(1)
RW
Block 0, 1 rewrite enable bit
(2)
Set write protection for user ROM area
(see Table 17.5.2.1)
FMR02
FMSTP
RW
0: Starts flash memory operation
1: Stops flash memory operation
(Enters low-power consumption state
and flash memory reset)
Flash memory stop bit
(3, 5)
RW
RW
Reserved bit
Set to “0”
(b5-b4)
FMR06
0: Terminated normally
1: Terminated in error
Program status flag
(4)
RO
RO
0: Terminated normally
1: Terminated in error
FMR07
Erase status flag
(4)
NOTES:
1. When setting this bit to “1”, set to “1” immdediately after setting it first to “0”. Do not generate an interrupt
or a DMA transfer between setting the bit to “0” and setting it to “1”. Set this bit while the P8 /NMI/SD pin
5
is “H” when selecting the NMI function. Set by program in a space other than the flash memory in EW0
mode. Set this bit to read alley mode and “0”
2. Set this bit to “1” immediately after setting it first to “0” while the FMR01 bit is set to “1”. Do not generate
an interrupt or a DMA transfer between setting this bit to “0” and setting it to “1”.
3. Set this bit in a pace other than the flash memory by program. When this bit is set to 1, access to flash
memory will be denied. To set this bit to 0 after setting it to 1, wait for 10 µsec. or more after setting it to
1. To read data from flash memory after setting this bit to 0, maintain tps wait time before accessing
flash memory.
4. This bit is set to “0” by executing the clear status command.
5. This bit is enabled when the FMR01 bit is set to “1” (CPU rewrite mode). This bit can be set to “1” when
the FMR01 bit is set to “0”. However, the flash memory does not enter low-power consumption status
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR1
Address
01B516
After reset
000XXX0X
2
0
Bit symbol
Bit name
Function
RW
Reserved bit
When read, its content is indeterminate RO
(b0)
EW1 mode select bit (1)
0: EW0 mode
1: EW1 mode
FMR11
RW
Reserved bit
When read, its content is indeterminate
RO
(b3-b2)
(b4)
Nothing is assigned. When write, set to “0”.
When read, its contect is indeterminate.
Reserved bit
Set to “0”
RW
RW
(b5)
Block 0 to 3 rewrite enable
bit (2)
Set write protection for user ROM area
(see Table 17.5.2.1)
0: Disable
FMR16
1: Enable
Block A, B access wait bit
(3)
0: PM17 enabled
1: With wait state (1 wait)
FMR17
RW
NOTES:
1. Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA transfer
between setting the bit to “0” and setting it to “1”. Set this bit while the P8 /NMI/SD pin is “H” when the
5
NMI function is selected. If the FMR01 bit is set to “0”, the FMR01 bit and FMR11 bit are both set to “0”
2. Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA transfer
after setting to “0”.
3. When rewriting more than 100 times, set this bit to “1” (with wait state). When the FMR17 bit is “1” (with
wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the access to the block A and
B. Regardless of the content of the FMR17 bit, access to other block and the internal RAM is
determined be PM17 bit setting.
Figure 17.5.1. FMR0 and FMR1 register
page 241
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Flash Memory Control Register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR4
Address
01B316
After Reset
01000000
0
0 0 0 0
2
Bit Symbol
Bit Name
Function
RW
RW
Erase suspend function
0: Disabled
1: Enabled
FMR40
FMR41
(1)
enable bit
Erase suspend
0: Erase restart
1: Suspend request
RW
RO
(2)
request bit
Reserved bit
Erase status
Set to 0
(b5-b2)
FMR46
0: During auto-erase operation
1: Auto-erase stop
(erase suspend mode)
RO
Reserved bit
Set to 0
(b7)
RW
NOTES:
1. Set the FMR40 bit to 1 immediately after setting it first to 0. Do not generate any interrupt or DMA
transfer between setting the bit to 0 and setting it to 1. Set by program in space other than the flash
memory in EW mode 0.
2. The FMR41 bit is valid only when the FMR40 bit is set to 1. The FMR41 bit can be written only
between executing an erase command and completing erase (this bit is set to 0 other than the
above duration). The FMR41 bit can be set to 0 or 1 by program in EW mode 0. In EW mode 1, the
FMR41 bit is automatically set to 1 when the FMR40 bit is 1 and a maskable interrupt is generated
during erasing. The FMR41 bit cannot be set to 1 by program (it can be set to 0 by program).
Figure 17.5.2. FMR4 register
page 242
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
EW0 mode operation procedure
Rewrite control program
Set the FMR01 bit to “1” after writing “0”
(CPU rewrite mode enabled) (2)
Single-chip mode
Set CM0, CM1, and PM1 registers (1)
Execute software commands
Transfer a rewrite control program to internal RAM
area
Execute the Read Array command (3)
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Jump to the rewrite control program transfered to an
internal RAM area (in the following steps, use the
rewrite control program internal RAM area)
Jump to a specified address in the flash memory
NOTES:
1. Select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and CM17 to 16 bits in the CM1
register. Also, set the PM17 bit in the PM1 register to “1” (with wait state).
2. Set the FMR01 bit to “1” immediately after setting it to “0”. Do not generate an interrupt or a DMA transfer between
setting the bit to “0” and setting it to “1”. Set the FMR01 bit in a space other than the internal flash memory. Also,
set only when the P85/NMI/SD pin is “H” at the time of the NMI function selected.
3. Disables the CPU rewrite mode after executing the read array command.
Figure 17.5.1.1. Setting and Resetting of EW0 Mode
EW mode 1 operation procedure
Program in ROM
Single-chip mode
(1)
Set CM0, CM1, and PM1 registers
Set the FMR01 bit to “1” (CPU rewrite mode
enabled) after writing “0”
Set the FMR11 bit to “1” (EW mode 1) after writing
(2, 3)
“0”
Execute software commands
Set the FMR01 bit to “0”
(CPU rewrite mode disabled)
NOTES:
1. Select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and CM17 to 16 bits.
in the CM1 register. Also, set the PM17 bit in the PM1 register to “1” (with wait state).
2. Set the FMR01 bits to “1” immediately after setting it to “0”. Do not generate an interrupt or a DMA
transfer between setting the bit to “0” and setting the bit to “1”. Set the FMR01 bit in a space other
than the internal flash memory. Set only when the P85/NMI/SD pin is “H” at the time of the NMI
function selected.
3. Set the FMR11 bit to "1" immediately after setting it to "0" while the FMR01 bit is set to "1". Do not
generate an interrupt or a DMA transfer between setting the FMR11 bit to "0" and setting it to "1".
Figure 17.5.1.2. Setting and Resetting of EW1 Mode
page 243
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Low power consumption
mode program
Transfer a low power internal consumption mode
program to RAM area
Set the FMR01 bit to “1” after setting “0”
(CPU rewrite mode enabled)
Set the FMSTP bit to “1” (flash memory stopped.
Low power consumption state)(1)
Jump to the low power consumption mode
program transferred to internal RAM area.
(In the following steps, use the low-power
consumption mode program or internal RAM area)
Switch the clock source of CPU clock.
Turn main clock off. (2)
Process of low power consumption mode or
on-chip oscillator low power consumption mode
Start main clock oscillation wait until oscillation stabilizes
switch the clock source of the CPU clock (2)
Set the FMSTP bit to “0” (flash memory operation)
Set the FMR01 bit to “0”
(CPU rewrite mode disabled)
(3)
Wait until the flash memory circuit stabilizes (tPS)
Jump to a desired address in the flash memory
NOTES:
1. Set the FMRSTP bit to “1” after setting the FMR01 bit to “1”(CPU rewrite mode).
2. Wait until the clock stabilizes to switch the clock source of the CPU clock to the main clock or the sub clock.
3. Add a tPS wait time by a program. Do not access the flash memory during this wait time.
Figure 17.5.1.3. Processing Before and After Low Power Dissipation Mode
page 244
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.6 Precautions in CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
17.6.1 Operation Speed
When CPU clock source is the main clock, before entering CPU rewrite mode (EW0 or EW1 mode),
select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16
bits in the CM1 register. Also, when selecting f3(ROC) of a on-chip oscillator as a CPU clock source,
before entering CPU rewrite mode (EW0 or EW1 mode), the ROCR3 to ROCR2 bits in the ROCR
register set the CPU clock division rate to “divide-by-4” or “divide-by-8”.
On both cases, set the PM17 bit in the PM1 register to “1” (with wait state).
17.6.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because the CPU tries to read data in the
flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK in-
struction
17.6.3 Interrupts
EW0 Mode
• To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the
RAM area.
_______
• The NMI and watchdog timer interrupts can be used since the FMR0 and FMR1 registers are
forcibly reset when either interrupt is generated. However, the jump addresses for each interrupt
service routines to the fixed vector table are set and interrupt programs are required. Flash
memory rewrite operation is halted when the NMI or watchdog timer interrupt is generated. Set the
FMR01 bit to “1” and execute the rewrite and erase program again after exiting the interrupt rou-
tine.
• The address match interrupt can not be used since the CPU tries to read data in the flash memory.
EW1 Mode
• Do not acknowledge any interrupts with vectors in the relocatable vector table or the address
match interrupt during the auto-program or erase-suspend function.
17.6.4 How to Access
To set the FMR01, FMR02, FMR11 or FMR16 bit to “1”, write “1” after first setting the bit to “0”. Do not
generate an interrupt or a DMA transfer between the instruction to set the bit to “0” and the instruction
_______
to set it to “1”. When the NMI function is selected, set the bit while an “H” signal is applied to the P85/
_______ _____
NMI/SD pin.
17.6.5 Writing in the User ROM Space
17.6.5.1 EW0 Mode
• If the supply voltage drops while rewriting the block where the rewrite control program is stored,
the flash memory can not be rewritten, because the rewrite control program is not correctly rewrit-
ten. If this error occurs, rewrite the user ROM area in standard serial I/O mode or parallel I/O
mode.
17.6.5.2 EW1 Mode
• Do not rewrite the block where the rewrite control program is stored.
page 245
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.6.6 DMA Transfer
In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0”.
(the auto-programming or auto-erasing duration ).
17.6.7 Writing Command and Data
Write the command code and data to even addresses in the user ROM area.
17.6.8 Wait Mode
When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the
WAIT instruction.
17.6.9 Stop Mode
When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable the DMA
transfer before setting the CM10 bit to “1” (stop mode).
17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consump-
tion Mode
If the CM05 bit is set to “1” (main clock stopped), do not execute the following commands.
• Program
• Block erase
page 246
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.7 Software Commands
Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing
a command code, 8 high-order bits (D15–D8) are ignored.
Table 17.7.1. Software Commands
First bus cycle
Address
Second bus cycle
Address
Command
Data
(D15 to D
Data
(D15 to D
Mode
Mode
Read
0
)
0)
Write
Write
Write
Write
Write
Read array
X
X
xxFF16
xx7016
xx5016
xx4016
xx2016
X
SRD
Read status register
Clear status register
Program
X
WA
BA
WD
WA
X
Write
Write
Block erase
xxD016
SRD: Status register data (D7 to D0)
WA : Write address (However,even address)
WD : Write data (16 bits)
BA : Highest-order block address (However,even address)
X : Any even address in the user ROM area
xx : 8 high-order bits of command code (ignored)
17.7.1 Read Array Command (FF16)
This command reads the flash memory.
By writing command code ‘xxFF16’ in the first bus cycle, read array mode is entered. Content of a
specified address can be read in 16-bit unit after the next bus cycle. The microcomputer remains in
read array mode until an another command is written. Therefore, contents of multiple addresses can
be read consecutively.
17.7.2 Read Status Register Command (7016)
This command reads the status register.
By writing command code ‘xx7016’ in the first bus cycle, the status register can be read in the second
bus cycle (Refer to 17.8 Status Register). Read an even address in the user ROM area. Do not
execute this command in EW1 mode.
page 247
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.7.3 Clear Status Register Command (5016)
This command clears the status register to “0”.
By writing ‘xx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4
to SR5 bits in the status register are set to “0”.
17.7.4 Program Command (4016)
The program command writes 2-byte data to the flash memory. By writing ‘xx4016’ in the first bus cycle
and data to the write address specified in the second bus cycle, the auto-programming/erasing (data
prorgramming and verify) start. Set the address value specified in the first bus cycle to same and even
address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register
indicates whether an auto-programming operation has been completed. The FMR00 bit is set to “0”
during the auto-programming and “1” when the auto-programming operation is completed. After the
auto-programming operation is completed, the FMR06 bit in the FMR0 register indicates whether or
not the auto-programming operation has been completed as expected. (Refer to 17.8.4 Full Status
Check). Also, each block disables writing (Refer to “Table 17.5.2.1”). Do not write additions to the
address which is already programmed. When commands other than a program command are ex-
ecuted immediately after a program command, set the same address as the write address specified in
the second bus cycle of the program command, to the specified address value in the first bus cycle of
the following command. In EW1 mode, do not execute this command on the blocks where the rewrite
control program is allocated. In EW0 mode, the microcomputer enters read status register mode as
soon as the auto-programming operation starts and the status register can be read. The SR7 bit in the
status register is set to “0” as soon as the auto-programming operation starts. This bit is set to “1”
when the auto-programming operation is completed. The microcomputer remains in read status regis-
ter mode until the read array command is written. After completion of the auto-programming operation,
the status register indicates whether or not the auto-programming operation has been completed as
expected.
Start
Write command code ‘xx4016’ to
(1)
the write address
Write data to the write address(1)
NO
FMR00=1?
YES
Full status check (2)
Program
completed
NOTE:
1: Write the command code and data at even address.Note 2: Refer to "Figure 17.8.4.1. Full Status
Check and Handling Procedure for Each Error"
Figure 17.7.4.1. Flow Chart of Program Command
page 248
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.7.5 Block Erase
By writing ‘xx2016’ in the first bus cycle and ‘xxD016’ in the second bus cycle to the highest-order (even
addresse of a block) and the auto-programming/erasing (erase and erase verify) start. The FMR00 bit
in the FMR0 register indicates whether the auto-programming operation has been completed. The
FMR00 bit is set to “0” (busy) during the auto-erasing operation and “1” (ready) when the auto-erasing
operation is completed. When using the erase-suspend function in EW0 mode, the FMR46 bit in the
FMR4 register indicates whether a flash memory has entered erase-suspend mode. The FMR46 bit is
set to “0” during auto-erasing operation and “1” when the auto-erasing operation is completed (enter-
ing erase-suspend). After the completion of an auto-erasing operation, the FMR07 bit in the FMR0
register indicates whether or not the auto erasing-operation has been completed as expected. (Refer
to 17.8.4 Full Status Check). Also, each block disables erasing. (Refer to “Table 17.5.2.1”). Figure
17.7.5.1 shows a flow chart of the block erase command programming when not using the erase-
suspend function. Figure 17.7.5.2 shows a flow chart of the block erase command programming when
using an erase-suspend function. In EW1 mode, do not execute this command on the block where the
rewrite control program is allocated. In EW0 mode, the microcomputer enters read status register
mode as soon as the auto-erasing operation starts and the status register can be read. The SR7 bit in
the status register is set to “0” as soon as the auto-erasing operation starts. This bit is set to “1” when
the auto-erasing operation is completed. The microcomputer remains in read status register mode
until the read array command is written. Also excute the clear status register command and block
erase command at least 3 times until an erase error is not generated when an erase error is gener-
ated.
Start
(1)
Write command code ‘xx2016
’
Write ‘xxD016’ to the highest-order
block address(1)
NO
FMR00=1?
YES
Full status check(2,3)
Block erase completed
NOTES:
1. Write the command code and data at even address.
2. Refer to "Figure 17.8.4.1. Full Status Check and Handling Porcedure for Each Error".
3. Execute the clear status register command and block erase command at least 3 times until an erase error is
not generated when an erase error is generated.
Figure 17.7.5.1. Flow Chart of Block Erase Command (when not using erase suspend function)
page 249
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(EW0 mode)
Interrupt service routine (3)
FMR41=1
Start
FMR40=1
Write the command code ‘xx2016
’
(1)
NO
FMR46=1?
Write ‘xxD016’ to the highest-order
block address (1)
YES
Access Flash Memory
NO
FMR00=1?
FMR41=0
Return
YES
Full status check(2,4)
(Interrupt service routine end)
Block erase completed
(EW1 mode)
Start
Interrupt service routine (3)
Access Flash Memory
FMR40=1
Write the command code ‘xx2016
’
Return
(1)
(Interrupt service routine end)
Write ‘xxD016’ to the highest-order
(1)
block address
FMR41=0
NO
FMR00=1?
YES
Full status check(2,4)
Block erase completed
NOTES:
1. Write the command code and data to even address.
2. Execute the clear status register command and block erase command at least 3 times until an erase
error is not generated when an erase error is generated.
3. In EW0 mode, allocate an interrupt vector table of an interrupt, to be used, to a RAM area.
4. Refer to "Figure 17.8.4.1 Full Status Check and Handling Procedure for Each Error."
Figure 17.7.5.2. Block Erase Command (at use erase suspend)
page 250
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.8 Status Register
The status register indicates the operating status of the flash memory and whether an erasing or a pro-
gramming operates normally and an error ends. The FMR00, FMR06, and FMR07 bits in the FMR0
register indicate the status of the status register.
Table 17.8.1 shows the status register.
In EW0 mode, the status register can be read in the following cases:
(1) When a given even address in the user ROM area is read after writing the read status register
command
(2) When a given even address in the user ROM area is read after executing the program or block
erase command but before executing the read a rray command.
17.8.1 Sequence Status (SR7 and FMR00 Bits )
The sequence status indicates the operating status of the flash memory. This bit is set to “0” (busy)
during an auto-programming and auto-erasing and “1” (ready) as soon as these operations are com-
pleted. This bit indicates “0” (busy) in erase-suspend mode.
17.8.2 Erase Status (SR5 and FMR07 Bits)
Refer to 17.8.4 Full Status Check.
17.8.3 Program Status (SR4 and FMR06 Bits)
Refer to 17.8.4 Full Status Check.
Table 17.8.1. Status Register
Bits in the
FMR0
register
Value
after
reset
Bits in the
SRD register
Contents
Status name
"0"
Busy
-
"1"
Ready
-
SR7 (D
SR6 (D
SR5 (D
SR4 (D
SR3 (D
SR2 (D
SR1 (D
SR0 (D
7)
6)
5)
4)
3)
2)
1)
0)
Sequence status
Reserved
FMR00
1
Erase status
Program status
Reserved
Completed normally
Completed normally
FMR07
FMR06
0
0
Terminated by error
Terminated by error
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
• D7 to D0: Indicates the data bus which is read out when executing the read status register command.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the clear status register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is 1, the program, and block erase command are not
acknowledged.
page 251
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.8.4 Full Status Check
When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur-
rence of each specific error. Therefore, execution results can be verified by checking these status bits
(full status check). Table 17.8.4.1 shows errors and the status of FMR0 register. Figure 17.8.4.1
shows a flow chart of the full status check and handling procedure for each error.
Table 17.8.4.1. Errors and FMR0 Register Status
FMR0 register
(SRD register)
status
FMR06
Error
Error occurrence condition
FMR07
(SR5)
1
(SR4)
1
Command
• When any commands are not written correctly
sequence error • A value other than ‘xxD016’ or ‘xxFF16’ is written in the second
(1)
bus cycle of the block erase command
• When the block erase command is executed on protected blocks
• When the program command is executed on protected blocks
1
0
0
1
Erase error
• When the block erase command is executed on unprotected
blocks but the blocks are not automatically erased correctly
Program error • When the program command is executed on unprotected blocks
but the blocks are not automatically programmed correctly.
NOTE:
1. The flash memory enters read array mode by writing command code ‘xxFF16’ in the second bus
cycle of these commands. The command code written in the first bus cycle becomes invalid.
page 252
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Full status check
FMR06 =1
YES
(1) Execute the clear status register command and set
the status flag to “0” whether the command is
entered.
Command
sequence error
and
FMR07=1?
(2) Reexecute the command after checking that it is
entered correctly or the program command or the
block erase command is not executed for the
blocks which are protected.
NO
(1) Execute the clear status register command and set
the erase status flag to “0”.
NO
FMR07=0?
Erase error
(2) Reexecute the block erase command.
(3) Execute (1) and (2) at least 3 times until an erase
error is not generated.
YES
Note 1: If the error still occurs, the block can not be
used.
[During programming]
(1) Execute the clear status register command and set
the program status flag to “0”.
(2) Reexecute the Program command.
NO
FMR06=0?
YES
Program error
Note 2: If the error still occurs, the block can not be
used.
Full status check completed
Note 3: If the FMR06 or FMR07 bits is “1”, any of the Program or Block Erase command can not
be aknowledged. Execute the clear status register command before executing those
commands.
Figure 17.8.4.1. Full Status Check and Handling Procedure for Each Error
page 253
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.9 Standard Serial I/O Mode
In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is
mounted on-board by using a serial programmer which is applicable for the M16C/26A group. For more
information about serial programmers, contact the manufacturer of your serial programmer. For details on
how to use the serial programmer, refer to the user’s manual included with your serial programmer.
Table 17.9.1 shows pin functions (flash memory standard serial input/output mode). Figures 17.9.1 and
17.9.2 show pin connections for standard serial input/output mode.
17.9.1 ID Code Check Function
This function determines whether the ID codes sent from the serial programmer and those written in the
flash memory match. (Refer to 17.3 Functions To Prevent Flash Memory from Rewriting.)
page 254
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 17.9.1. Pin Functions (Flash Memory Standard Serial I/O Mode)
Pin
Name
Description
I/O
Apply the voltage guaranteed for Program and Erase to Vcc pin and 0
V to Vss pin.
VCC,VSS
Power input
CNVSS
RESET
CNVSS
I
I
Connect to Vcc pin.
Reset input
Reset input pin. While RESET pin is "L" level, wait for td(ROC).
Connect a ceramic resonator or crystal oscillator between X IN and
XOUT pins. To input an externally generated clock, input it to X IN pin
and open XOUT pin.
XIN
Clock input
I
XOUT
Clock output
O
AVCC, AVSS
Analog power supply input
Connect AVss to Vss and AVcc to Vcc, respectively.
Enter the reference voltage for AD from this pin.
Input "H" or "L" level signal or open.
VREF
Reference voltage input
Input port P1
I
I
P15, P17
P16
I
P16 input
Connect this pin to Vcc while RESET is low. (2)
Input "H" or "L" level signal or open.
P60 to P63
P64
Input port P6
I
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitor signal output pin for boot program
operation check
BUSY output
O
Standard serial I/O mode 1: Serial clock input pin
Standard serial I/O mode 2: Input "L".
P65
SCLK input
I
P66
RxD input
I
O
I
Serial data input pin
P67
TxD output
Input port P7
Serial data output pin
(1)
P70 to P77
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
P80 to P84,
P87
Input port P8
I
P85
P86
RP input
CE input
I
I
I
Connect this pin to Vss while RESET is low. (2)
Connect this pin to Vcc while RESET is low. (2)
Input "H" or "L" level signal or open.
Input port P9
Input port P10
P90 to P93,
P100 to P107
I
Input "H" or "L" level signal or open.
NOTES:
1. When using standard serial input/output mode 1, to input “H” to the TxD pin is necessary while the
___________
RESET pin is “L”. Therefore, connect this pin to VCC via a resistor. Adjust the pull-up resistor value on
a system not to affect a data transfer after reset, because this pin changes to a data-output pin
2. Set following either or both
_____
•Connect the CE pin to VCC.
_____
•Connect the RP pin to VSS and the P16 pin to VCC.
page 255
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
Vss
2
3
4
Vcc
5
6
7
M16C/26A Group
8
9
(1)
(1)
(M16C/26A)
(Flash memory version)
PRSP0042GA-B (42P2R)
CE
RP
P1
6
10
RESET
11
12
13
14
15
16
17
18
19
20
21
BUSY
RxD
Connect
oscillator
circuit
SCLK
TxD
(1)
Mode setup method
Signal
CNVss
Reset
Value
Vcc
Vss to Vcc
NOTE:
1. Set following either or both in serial I/O mode while the RESET pin is held “L”.
Connect the CE pin to VCC
Connect the RP pin to VSS and the P1
.
6
pin to VCC.
Figure 17.9.1. Pin Connections for Serial I/O Mode (1)
page 256
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
37
38
39
40
41
24
23
22
21
20
19
18
17
16
15
14
13
42
M16C/26A Group
(M16C/26A, M16C/26B, M16C/26T)
43
44
(Flash memory version)
PLQP0048KB-A (48P6Q)
45
46
47
48
Mode setup method
Signal
CNVss
Reset
Value
Vcc
Vss to Vcc
Connect
oscillator
circuit
NOTE:
1. Set following either or both in serial I/O mode while the RESET pin is held “L”.
Connect the CE pin to VCC
Connect the RP pin to VSS and the P1
.
6
pin to VCC.
Figure 17.9.2. Pin Connections for Serial I/O Mode (2)
page 257
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.9.2 Example of Circuit Application in Standard Serial I/O Mode
Figure 17.9.2.1 shows an example of a circuit application in standard serial I/O mode 1 and Figure
17.9.2.2 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's
manual for a serial writer to handle pins controlled by the serial writer.
Microcomputer
(1)
SCLK
SCLK input
P86(CE)
TXD
(1)
TxD output
P16
CNVss
BUSY
RxD
BUSY output
RxD input
Reset input
RESET
User reset
singnal
P85(RP)
(1)
(1) Controlling pins and external circuits vary with the serial programmer. For more
information, refer to the user's manual included with the serial programmer.
(2) In this example, a selector controls the input voltage applied to CNVss to switch
between single-chip mode and standard serial I/O mode.
(3) In standard serial input/output mode 1, if the user reset signal becomes “L” while
the microcomputer is communicating with the serial programmer, break the
connection between the user reset signal and the RESET pin using a jumper
switch.
NOTE:
1. Set following either or both
• Connect the CE pin to VCC
• Connect the RP pin to VSS and the P16 pin to VCC
Figure 17.9.2.1. Circuit Application in Standard Serial I/O Mode 1
page 258
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Microcomputer
(1)
SCLK
TxD
P86(CE)
TxD output
(1)
BUSY
RxD
Monitor output
RxD input
P16
CNVss
P85(RP)
(1)
(1) In this example, a selector controls the input voltage applied to CNVss to switch
between single-chip mode and standard serial I/O mode.
NOTE:
1. Set following either or both
• Connect the CE pin to VCC
• Connect the RP pin to VSS and the P16 pin to VCC
Figure 17.9.2.2. Circuit Application in Standard Serial I/o Mode 2
page 259
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
17. Flash Memory Version
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
17.10 Parallel I/O Mode
In parallel input/output mode, the user ROM can be rewritten using a parallel programmer which is appli-
cable for the M16C/26A group. For more information about the parallel programmer, contact your parallel
programmer manufacturer. For details on how to use the parallel programmer, refer to the user’s manual of
the parallel programmer.
17.10.1 ROM Code Protect Function
The ROM code protect function prevents the flash memory from being read or rewritten. (Refer to 17.3
Function to Prevent Flash Memory from Rewriting.)
page 260
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
18. Electrical Characteristics
Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor
for electrical characteristics of V-ver.
18.1. M16C/26A, M16C/26B (Normal version)
Table 18.1. Absolute Maximum Ratings
Symbol
Parameter
Condition
Value
Unit
V
V
CC
Supply Voltage
VCC = AVCC
-0.3 to 6.5
AVCC
Analog Supply Voltage
VCC = AVCC
-0.3 to 6.5
V
V
I
Input Voltage
P1
5
0
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7
,
-0.3 to VCC+0.3
V
P8
to P8
7
, P9
to P9
3
, P10
0
to P10
7,
X
IN, VREF, RESET, CNVSS
V
O
Output Voltage P1
5
0
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7
,
-0.3 to VCC+0.3
300
V
P8
to P8
7
, P9
to P93, P100 to P107,
X
OUT
Pd
Power Dissipation
-40 < Topr < 85° C
mW
Topr
Operating
Ambient
Temperature
during CPU operation
-20 to 85 /
-40 to 85(1)
° C
during flash memory
program and erase
operation
Program Space
(Block 0 to Block 3)
0 to 60
° C
° C
Data Space
(Block A, Block B)
0 to 60 /
-20 to 85 /
-40 to 85(1)
Tstg
Storage Temperature
-65 to 150
° C
NOTE:
1. Refer to Tables 1.7 and 1.8.
page 261
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(
1)
Table 18.2. Recommended Operating Conditions
Standard
Unit
Symbol
Parameter
Min.
2.7
Typ.
Max.
5.5
VCC
Supply Voltage
V
V
AVCC
Analog Supply Voltage
VCC
V
SS
Supply Voltage
0
V
V
V
AVSS
Analog Supply Voltage
0
V
IH
Input High ("H") P1
Voltage
5
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7
,
0.7 VCC
V
CC
CC
P80
to P8
7
, P9
to P9
3
, P10
0
to P10
7
0.8 VCC
0
V
V
V
XIN, RESET, CNVSS
V
IL
Input Low ("L")
Voltage
P15
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
0.3 VCC
P80
to P8
7
, P9
0
to P9
3
, P10
0 to P10
7
0
0.2 VCC
-10.0
V
XIN, RESET, CNVSS
IOH(peak)
IOH(avg)
IOL(peak)
I
OL(avg)
Peak Output High
("H") Current
P15
P80
P15
P80
P15
P80
P15
P80
to P1
to P8
to P1
to P8
to P1
to P8
to P1
to P8
7
, P6
, P9
, P6
, P9
, P6
, P9
, P6
, P9
0
0
0
0
0
0
0
0
to P6
to P9
to P6
to P9
to P6
to P9
to P6
to P9
7
, P7
, P10
, P7
, P10
, P7
, P10
, P7
, P10
0
to P7
7
,
mA
7
3
0
to P10
7
7
7
7
Average Output
High ("H") Current
7
7
0
to P7
7
,
-5.0
10.0
5.0
mA
mA
mA
7
3
0
to P10
Peak Output Low
("L") Current
7
7
0
to P77,
7
3
0
to P10
Average Output
Low ("L") Current
7
7
0
to P77,
7
3
0 to P10
f(XIN
)
Main Clock Input Oscillation Frequency(4)
0
0
20
MHz
MHz
kHz
V
CC= 3.0 to 5.5 V
CC= 2.7 to 3.0 V
V
33 X VCC-80
f(XCIN
)
Sub Clock Oscillation Frequency
32.768
50
2
f
1(ROC) On-chip Oscillator Frequency 1
0.5
1
1
2
MHz
MHz
MHz
MHz
f2(ROC) On-chip Oscillator Frequency 2
f3(ROC) On-chip Oscillator Frequency 3
4
8
16
26
24
f(PLL)
PLL Clock Oscillation Frequency(4)
VCC = 4.2 to 5.5 V (M16C/26B)
VCC = 3.0 to 4.2 V (M16C/26B)
VCC = 3.0 to 5.5 V (M16C/26A)
VCC= 2.7 to 3.0 V
10
10
10
10
0
3.33 X VCC+10 MHz
20
MHz
MHz
MHz
MHz
ms
33 X VCC-80
M16C/26A
M16C/26B
20
24
20
50
f(BCLK) CPU Operation Clock Frequency
0
t
SU(PLL) Wait Time to Stabilize PLL Frequency
Synthesizer
V
CC=5.0V
CC=3.0V
V
ms
NOTES:
1. Referenced to VCC = 2.7 to 5.5 V at Topr = -20 to 85 ° C / -40 to 85 ° C unless otherwise specified.
2. The mean output current is the mean value within 100 ms.
3. The total IOL(peak) for all ports must be 80 mA or less. The total IOH(peak) for all ports must be -80 mA or less.
4. Relationship among main clock oscillation frequency, PLL clock oscillation frequency and supply voltage.
Main clock input oscillation frequency
PLL clock oscillation frequency (M16C/26A)
PLL clock oscillation frequency (M16C/26B)
3.33 x VCC+10 MH
Z
33.3 x VCC-80 MH
Z
33.3 x VCC-80 MHZ
24.0
20.0
33.3 x VCC-80 MH
Z
20.0
20.0
10.0
0.0
10.0
0.0
10.0
0.0
2.7 3.0
5.5
2.7 3.0
5.5
2.7 3.0
4.2 5.5
VCC[V] (main clock: no division)
VCC[V] (PLL clock oscillation)
V
CC[V] (PLL clock oscillation)
page 262
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 18.3. A /D Conversion Characteristics(1)
Standard
Symbol
-
Parameter
Measurement Condition
Unit
Bits
Min. Typ. Max.
10
Resolution
V
V
V
V
V
V
V
REF = VCC
REF = VCC = 5V
±3 LSB
±5 LSB
±2 LSB
±3 LSB
±5 LSB
10 bit
8 bit
Integral Nonlinearity
Error
INL
REF = VCC = 3.3 V
REF = VCC = 3.3 V, 5 V
REF = VCC = 5 V
10 bit
8 bit
-
Absolute Accuracy
REF = VCC = 3.3 V
REF = VCC = 3.3 V, 5 V
±2 LSB
±1 LSB
±3 LSB
±3 LSB
DNL
Differential Nonlinearity Error
Offset Error
-
-
Gain Error
R
LADDER
Resistor Ladder
V
V
REF =
V
CC
10
40
kΩ
µs
10-bit Conversion Time
Sample & Hold Function Available
t
t
CONV
CONV
REF = VCC = 5 V, φAD = 10 MHz
REF = VCC = 5 V, φAD = 10 MHz
3.3
8-bit Conversion Time
Sample & Hold Function Available
µs
V
2.8
V
REF
IA
Reference Voltage
2.0
0
V
CC
V
V
V
Analog Input Voltage
V
REF
NOTES:
1. Referenced to VCC=AVCC=VREF= 3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 ° C / -40 to 85° C unless otherwise
specified.
2. Keep φAD frequency at 10 MHz or less (12 MHz or less in M16C/26B). Additionally, divide the fAD if VCC is less than
4.2V, and make φAD frequency equal to or lower than fAD/2.
3. When sample & hold function is disabled, keep φAD frequency at 250 kHz or more in addition to the limitation in Note 2.
When sample & hold function is enabled, keep φAD frequency at 1 MHz or more in addition to the limitation in Note 2.
4. When sample & hold function is enabled, sampling time is 3/ φAD frequency.
When sample & hold function is disabled, sampling time is 2/ φAD frequency.
page 263
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1)
Table 18.4. Flash Memory Version Electrical Characteristic
:
Program Space and Data Space for U3 and U5, Program Space for U7 and U9
Standard
Typ.(2)
100/1000(4, 11)
Symbol
Parameter
Program and Erase Endurance(3)
Unit
Min.
Max.
cycles
-
-
-
µs
Word Program Time (VCC=5.0V, Topr=25° C)
75
600
9
Block Erase Time
(VCC=5.0V, Topr=25° C)
2-Kbyte Block
8-Kbyte Block
16-Kbyte Block
32-Kbyte Block
0.2
0.4
0.7
1.2
s
s
9
9
s
9
s
td(SR-ES) Duration between Suspend Request and Erase Suspend
8
ms
µs
years
t
PS
Wait Time to Stabilize Flash Memory Circuit
Data Hold Time (5)
15
-
20
(6)
(7)
Table 18.5. Flash Memory Version Electrical Characteristics : Data Space for U7 and U9
Standard
Typ.(2)
10000(4, 10)
Symbol
Parameter
Program and Erase Endurance(3, 8, 9)
Unit
Min.
Max.
cycles
-
-
-
µs
Word Program Time (VCC=5.0V, Topr=25° C)
100
0.3
s
Block Erase Time (VCC=5.0V, Topr=25° C)
(2-Kbyte block)
td(SR-ES) Duration between Suspend Request and Erase Suspend
8
ms
µs
t
PS
Wait Time to Stabilize Flash Memory Circuit
Data Hold Time (5)
15
-
20
years
NOTES:
1. Referenced to VCC = 2.7 to 5.5 V at Topr = 0 to 60° C (program space), -40 to 85° C (data space), unless
otherwise specified.
2. VCC = 5.0 V; Topr = 25° C
3. Program and erase endurance is defined as number of program-erase cycles per block.
If program and erase endurance is n cycle (n = 100, 1000, 10000), each block can be erased and programmed n
cycles.
For example, if a 2-Kbyte block A is erased after programming one-word data to each address 1,024 times,
this counts as one program and erase endurance. Data cannot be programmed to the same address more than
once without erasing the block. (rewrite prohibited).
4. Number of E/W cycles for which operation is guranteed (1 to minimum value are guaranteed).
5. Topr = 55° C
6. Referenced to VCC = 2.7 to 5.5 V at Topr = -40 to 85° C (U7) / -20 to 85° C ( U9) unless otherwise specified.
7. Table 18.5 applies for data space in U7 and U9 when program and erase endurance is more than 1,000 cycles.
Otherwise, use Table 18.4.
8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites,
write to unused word addresses within the block instead of rewrite. Erase block only after all possible addresses
are used. For example, an 8-word program can be written 128 times maximum before erase becomes necessary.
Maintaining an equal number of times erasure between block A and block B will also improve efficiency. It is
recommended to track the total number of erasure performed per block and to limit the number of erasure.
9. Execute the clear status register command and block erase command at least 3 times until an erase error is not
generated when an erase error is generated.
10. When executing more than 100 times rewrites, set one wait state per block access by setting the FMR17 bit in
the FMR1 register 1 to "1" (wait state). When accessing to all other blocks and internal RAM, wait state can be
set by the PM17 bit, regardless of the FMR17 bit setting value.
11. The program and erase endurance is 100 cycles for program space and data space in U3 and U5; 1,000
cycles for program space in U7 and U9.
12. Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Erase suspend
request
(interrupt request)
FMR46
td(SR-ES)
page 264
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1, 3
)
Table 18.6. Voltage Detection Circuit Electrical Characteristics
Standard
Symbol
Parameter
Measurement Condition
Unit
Min. Typ. Max.
Vdet4
Low Voltage Detection Voltage(1)
Reset Level Detection Voltage(1)
Low Voltage Reset Hold Voltage(2)
Low Voltage Reset Release Voltage
3.2
2.3
3.8 4.45
V
V
V
V
Vdet3
2.8
3.4
1.7
3.5
VCC=0.8 to 5.5V
Vdet3s
Vdet3r
NOTES:
2.35 2.9
1. Vdet4 >Vdet3
2. Vdet3s is the minmum voltage to maintain "hardware reset 2".
3. The voltage detection circuit is designed to use when VCC is set to 5V.
4. If the supply power voltage is greater than the reset level detection voltage when the reset level detection
voltage is less than 2.7V, the operation at f(BCLK) ≤ 10MHz is guranteed. However, A/D conversion, serial I/O,
flash memory program and erase are excluded.
Table 18.7. Power Supply Circuit Timing Characteristics
Standard
Symbol
Parameter
Measurement Condition
VCC = 2.7 to 5.5 V
Unit
Min. Typ. Max.
td(P-R) Wait Time to Stabilize Internal Supply Voltage when Power-on
td(ROC) Wait Time to Stabilize Internal On-chip Oscillator when Power-on
td(R-S) STOP Release Time
2
ms
µs
µs
µs
ms
µs
40
150
150
td(W-S) Low Power Dissipation Mode Wait Mode Release Time
td(S-R) Hardware Reset 2 Release Wait Time
VCC = Vdet3r to 5.5 V
VCC = 2.7 to 5.5 V
6(1)
20
20
td(E-A) Voltage Detection Circuit Operation Start Time
NOTES:
1. When VCC=5V
t
t
d(P-R)
VCC
ROC
Wait time to stabilize internal
supply voltage when power-on
d(ROC)
td(P-R)
td(ROC)
Wait time to stabilize internal
on-chip oscillator when power-
on
RESET
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
t
t
d(R-S)
STOP release time
d(W-S)
Low power dissipation mode
wait mode release time
CPU clock
(a)
(b)
t
t
d(R-S)
d(W-S)
t
d(S-R)
Brown-out detection
reset (hardware reset 2)
release wait time
Vdet3r
V
CC
td(S-R)
CPU clock
t
d(E-A)
Voltage detection circuit
operation start time
VC26, VC27
Stop
Operate
Voltage Detection Circuit
t
d(E-A)
page 265
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
(
1)
Table 18.8. Electrical Characteristics
Standard
Unit
V
Symbol
Parameter
Condition
Min. Typ. Max.
V
OH
OH
Output High P1
5
0
5
0
to P1
to P8
to P1
to P8
7
7
7
7
, P6
, P9
, P6
, P9
0
0
0
0
to P6
to P9
to P6
to P9
7
3
7
3
, P7
, P10
, P7
, P10
0
to P7
to P10
to P7
to P10
7
,
I
I
OH = -5 mA
V
CC
V
CC
-
2.0
("H") Voltage
P8
0
7
Output High P1
0
7,
OH =-200 µA
V
CC
V
V
VCC
-
0.3
V
("H") Voltage
P8
0
7
I
I
OH = -1mA
V
V
CC
CC
High Power
Low Power
High Power
Low Power
VCC
-
2.0
Output High ("H") Voltage
Output High ("H") Voltage
XOUT
OH = -0.5mA
VCC
-
2.0
V
OH
No load applied
No load applied
2.5
1.6
XCOUT
V
V
V
OL
OL
Output Low P1
5
0
5
0
to P1
to P8
to P1
to P8
7
7
7
7
, P6
, P9
, P6
, P9
0
0
0
0
to P6
to P9
to P6
to P9
7
3
7
3
, P7
0
to P7
7,
I
OL = 5 mA
2.0
("L") Voltage
P8
, P10
, P7
, P10
0
to P10
7
P1
P8
0
to P7
7,
I
OL = 200 µA
0.45
V
V
Output Low
("L") Voltage
V
0
to P10
7
I
I
OL = 1 mA
2.0
2.0
High Power
Low Power
High Power
Low Power
Output Low ("L") Voltage
Output Low ("L") Voltage
XOUT
OL = 0.5 mA
V
OL
No load applied
No load applied
0
0
XCOUT
V
V
VT+-VT- Hysteresis
0.2
1.0
TA0IN-TA4IN, TB0IN-TB2IN, INT
0
-INT
5
, NMI, ADTRG
,
CTS -CTS , CLK -CLK , TA2OUT-TA4OUT, KI
0
2
0
2
0-KI3,
RXD0-RXD2
V
V
T+-VT- Hysteresis
T+-VT- Hysteresis
0.2
0.2
2.5
0.8
V
RESET
XIN
V
µA
I
IH
Input High
("H") Current
P1
5
0
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7
,
V
V
V
I
=5V
5.0
P8
to P8
7
, P9
to P9
3
, P10
0
to P107,
XIN, RESET, CNVSS
µA
I
IL
Input Low
("L") Current
P15
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
I=0V
-5.0
P80
to P8
7
, P9
0
to P9
3
, P10
0
to P107,
XIN, RESET, CNVSS
R
PULLUP Pull-up
P15
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
I=0V
30
50 170 kΩ
Resistance
P80
to P8
7
, P9
0
to P9
3
, P10
0
to P10
7
RfXIN
1.5
15
MΩ
MΩ
V
Feedback Resistance
Feedback Resistance
RAM Standby Voltage
X
IN
CIN
RfXCIN
X
VRAM
In stop mode
2.0
NOTE:
1. Referenced to VCC=4.2 to 5.5V, VSS=0V at Topr=-20 to 85 ° C / -40 to 85 ° C, f(BCLK)=20MHz unless otherwise
specified.
page 266
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
(
1)
Table 18.9. Electrical Characteristics (2)
Standard
Symbol
Parameter
Measurement Condition
Unit
Min. Typ. Max.
I
CC
Power Supply
Current
(VCC= 4.0 to 5.5 V) other pins are
connected to VSS
Output pins are
left open and
Mask ROM
f(BCLK) = 20 MHz,
main clock, no division
12
17 mA
On-chip oscillation
1
mA
f
2(ROC) selected, f(BCLK) = 1 MHz
Flash memory
f(BCLK) = 24 MHz,
PLL operates (M16C/26B)
20
16
1
23 mA
19 mA
mA
f(BCLK) = 20 MHz, main clock,
no division
On-chip oscillator operates,
f
2(ROC) selected, f(BCLK) = 1 MHz
Flash memory
program
11
mA
f(BCLK) = 10 MHz, Vcc = 5.0 V
f(BCLK) = 10 MHz, Vcc = 5.0 V
Flash memory
erase
12
25
mA
µA
Mask ROM
f(BCLK) = 32 kHz,
In low-power consumption mode,
Program running on ROM(3)
µA
µA
µA
µA
On-chip oscillator operates,
30
25
f
2(ROC) selected, f(BCLK) = 1 MHz,
In wait mode
Flash memory
f(BCLK) = 32 kHz,
In low-power consumption mode,
Program running on RAM(3)
f(BCLK) = 32 kHz,
In low-power consumption mode,
Program running on flash memory(3)
450
50
On-chip oscillator operates,
f
2(ROC) selected, f(BCLK) = 1 MHz,
In wait mode
µA
µA
Mask ROM,
Flash memory
f(BCLK) = 32 kHz, In wait mode(2),
Oscillation capacity HIGH
f(BCLK) = 32 kHz, In wait mode(2),
Oscillation capacity LOW
10
3
µA
µA
µA
In stop mode, Topr = 25° C
0.8
0.7
1.2
3
4
8
Idet4
Low voltage detection dissipation current(4)
Reset level detection dissipation current(4)
Idet3
NOTES:
1. Referenced to VCC= 4.2 to 5.5 V, VSS= 0 V at Topr = -20 to 85° C / -40 to 85 ° C, f(BCLK) = 20 MHz unless otherwise
specified.
2. With one timer operates, using fC32
.
3. This indicates the memory in which the program to be executed exists.
4. Idet is dissipation current when the following bit is set to "1" (detection circuit enabled).
Idet4: VC27 bit in the VCR2 register
Idet3: VC26 bit in the VCR2 register
page 267
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
Timing Requirements
o
o
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.10. External Clock Input (XIN input)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc
External Clock Input Cycle Time
50
20
20
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
External Clock Input High ("H") Width
External Clock Input Low ("L") Width
External Clock Rise Time
9
9
tf
External Clock Fall Time
page 268
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
Timing Requirements
o
o
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.11. Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
40
Table 18.12. Timer A Input (Gating Input in Timer Mode)
Standard
Min. Max.
400
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.13. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.14. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.15. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN
)
t
h(TIN-UP)
400
Table 18.16. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
t
c(TA)
ns
ns
ns
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
t
su(TAIN-TAOUT
su(TAOUT-TAIN
)
)
t
page 269
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
Timing Requirements
o
o
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.17. Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
t
t
200
80
t
w(TBH)
t
w(TBL)
80
Table 18.18. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.19. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.20. A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 18.21. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
80
0
70
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 18.22. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
page 270
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
XIN input
t
f
t
w(H)
tw(L)
tr
t
c
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
tsu(UP-TIN)
th(TIN-UP)
edge is selected)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
t
su(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 18.1. Timing Diagram (1)
page 271
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
t
h(C–D)
t
w(INL)
INTi input
tw(INH)
Figure 18.2. Timing Diagram (2)
page 272
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
1)
Table 18.23. Electrical Characteristics (
Standard
Unit
V
Symbol
Parameter
Condition
OH=-1mA
Min. Typ. Max.
V
OH
Output High P1
5
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7
,
I
V
CC
VCC-
0.5
("H") Voltage
P80
to P8
7
, P9
to P9
3
, P10
0
to P10
7
I
I
OH=-0.1mA
V
CC
CC
High Power
Low Power
High Power
Low Power
V
CC
-
0.5
Output High ("H") Voltage
Output High ("H") Voltage
X
OUT
V
OH=-50µA
V
VCC
-
0.5
V
OH
OL
No load applied
No load applied
2.5
1.6
XCOUT
V
V
V
Output Low P1
5
to P17, P6
0
0
to P6
7
, P7
0
to P7
7,
I
OL=1mA
0.5
("L") Voltage
P80
to P87, P9
to P9
3
, P10
0
to P107
I
I
OL=0.1mA
0.5
0.5
High Power
Low Power
High Power
Low Power
Output Low ("L") Voltage
Output Low ("L") Voltage
X
OUT
V
OL=50µA
V
OL
No load applied
No load applied
0
0
XCOUT
V
V
V
T+-VT- Hysteresis
0.8
TA0IN-TA4IN, TB0IN-TB2IN, INT
0
-INT
5, NMI, ADTRG
,
CTS -CTS , CLK -CLK , TA2OUT-TA4OUT, KI
0
2
0
2
0-KI3,
RXD0-RXD2
V
V
T+-VT- Hysteresis
T+-VT- Hysteresis
1.8
0.8
V
RESET
XIN
V
µA
I
IH
Input High
("H") Current
P1
5
0
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7
,
V
V
V
I
=3V
4.0
P8
to P8
7
, P9
to P9
3
, P10
0
to P10
7
7
7
XIN, RESET, CNVSS
µA
I
IL
Input Low
("L") Current
P15
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
I=0V
-4.0
P80
to P8
7
, P9
0
to P9
3
, P10
0
to P10
XIN, RESET, CNVSS
R
PULLUP Pull-up
P15
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
I=0V
50
100 500 kΩ
Resistance
P80
to P8
7
, P9
0
to P9
3
, P10
0
to P10
RfXIN
3.0
25
MΩ
MΩ
V
Feedback Resistance
Feedback Resistance
RAM Standby Voltage
X
IN
CIN
RfXCIN
X
V
RAM
In stop mode
2.0
NOTE:
1. Referenced to VCC = 2.7 to 3.6 V, VSS = 0 V at Topr = -20 to 85 ° C / -40 to 85 ° C, f(BCLK) = 10 MHz unless otherwise
specified.
page 273
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
1)
Table 18.24. Electrical Characteristics (2) (
Standard
Symbol
Parameter
Measurement Condition
Unit
Min. Typ. Max.
I
CC
Power Supply
Current
(VCC= 2.7 to 3.6V) other pins are
connected to VSS
Output pins are Mask ROM
left open and
f(BCLK) = 10 MHz,
Main clock, no division
7
10 mA
On-chip oscillator operates,
1
mA
f
2(ROC) selected, f(BCLK) = 1 MHz
Flash memory f(BCLK) = 10 MHz,
Main clock, no division
7
12 mA
mA
On-chip oscillator operates,
1
f
2(ROC) selected, f(BCLK) = 1 MHz
Flash memory
program
10
mA
f(BCLK) = 10 MHz, Vcc = 3.0 V
f(BCLK) = 10 MHz, Vcc= 3.0 V
Flash memory
erase
11
25
mA
µA
Mask ROM
f(BCLK) = 32 kHz,
In low-power consumption mode,
Program running on ROM(3)
µA
µA
µA
µA
25
25
On-chip oscillator operates,
f
2(ROC) selected, f(BCLK) = 1 MHz,
In wait mode
Flash memory f(BCLK) = 32 kHz,
In low-power consumption mode,
Program running on RAM(3)
f(BCLK) = 32 kHz,
In low-power consumption mode,
Program running on flash memory(3)
450
45
On-chip oscillator operates,
f
2(ROC) selected, f(BCLK) = 1 MHz,
In wait mode
µA
µA
Mask ROM,
Flash memory Oscillation capacity HIGH
f(BCLK) = 32 kHz, In wait mode(2),
10
3
f(BCLK) = 32 kHz,In wait mode(2),
Oscillation capacity LOW
µA
µA
µA
While clock stops, Topr = 25° C
0.7
0.6
1.0
3
4
5
Idet4
Low voltage detection dissipation current(4)
Reset level detection dissipation current(4)
Idet3
NOTES:
1. Referenced to VCC= 2.7 to 3.6 V, VSS= 0 V at Topr = -20 to 85 ° C / -40 to 85 ° C, f(BCLK) = 10 MHz unless otherwise
specified.
2. With one timer operates, using fC32
.
3. This indicates the memory in which the program to be executed exists.
4. Idet is dissipation current when the following bit is set to 1 (detection circuit enabled).
Idet4: the VC27 bit of the VCR2 register
Idet3: the VC26 bit in the VCR2 register
page 274
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
Timing Requirements
o
o
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.25. External Clock Input (XIN input)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc
External Clock Input Cycle Time
100
40
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
External Clock Input High ("H") Width
External Clock Input Low ("L") Width
External Clock Rise Time
40
18
18
tf
External Clock Fall Time
page 275
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
Timing Requirements
o
o
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.26. Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
60
Table 18.27. Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
600
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
300
300
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.28. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.29. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.30. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN)
t
h(TIN-UP)
600
Table 18.31. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
t
c(TA)
µs
ns
ns
2
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
t
t
su(TAIN-TAOUT
)
)
500
500
su(TAOUT-TAIN
page 276
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
Timing Requirements
o
o
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.32. Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbo
Paramete
Uni
t
ns
Min.
150
Ma
x.
l
r
t
c(TB)
TBiIN input cycle time (counted on one edge)
t
w(TBH)
ns
ns
ns
ns
ns
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
60
60
tw(TBL)
tc(TB)
300
120
120
tw(TBH)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
tw(TBL)
Table 18.33. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.34. Timer B Input (Pulse Width Measurement Mode)
Standar
Symbol
Parameter
Unit
d
Mi
n.
Ma
x.
t
c(TB)
ns
ns
ns
600
TBiIN input cycle time
t
w(TBH)
300
300
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.35. A/D Trigger Input
Standar
d
Symbo
l
Paramete
Unit
Mi
n.
Ma
x.
r
t
c(AD)
ns
ns
1500
ADTRG input cycle time (trigger able minimum)
t
w(ADL)
200
ADTRG input LOW pulse width
Table 18.36. Serial I/O
Standard
Symbol
Parameter
Unit
Mi
Max.
n.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
300
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
150
150
t
t
t
d(C-Q)
h(C-Q)
160
0
100
90
t
su(D-C)
h(C-D)
RxDi input setup time
RxDi input hold time
t
_______
Table 18.37. External Interrupt INTi Input
Standard
Symbo
Paramete
Unit
Min.
380
380
Ma
x.
l
r
t
w(INH)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
w(INL)
page 277
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
XIN input
t
f
t
w(H)
tw(L)
tr
t
c
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During Event Counter Mode
TAiIN input
(When count on falling
th(TIN-UP) tsu(UP-TIN)
edge is selected)
TAiIN input
(When count on rising
edge is selected)
Two-Phase Pulse Input in Event Counter Mode
tc(TA)
TAiIN input
t
su(TAIN-TAOUT)
tsu(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
t
su(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 18.3. Timing Diagram (1)
page 278
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26A, M16C/26B)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
t
h(C–Q)
TxDi
RxDi
tsu(D–C)
td(C–Q)
t
h(C–D)
t
w(INL)
INTi input
tw(INH)
Figure 18.4. Timing Diagram (2)
page 279
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
18.2. M16C/26T (T version)
Table 18.38. Absolute Maximum Ratings
Symbol
Parameter
Condition
Value
Unit
V
V
CC
Supply Voltage
VCC = AVCC
-0.3 to 6.5
-0.3 to 6.5
AVCC
Analog Supply Voltage
VCC = AVCC
V
V
I
Input Voltage
P1
5
0
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7,
P8
to P8
7
, P9
0
to P9
3
, P10
0
to P10
7
,
-0.3 to VCC+0.3
-0.3 to VCC+0.3
V
V
X
IN, VREF, RESET, CNVSS
V
O
Output Voltage P1
5
0
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7,
P8
to P8
7
, P9
to P9
3
, P10
0
to P107,
X
OUT
Pd
Power Dissipation
-40 < Topr < 85° C
300
mW
during CPU operation
-40 to 85
° C
Program Space
(Block 0 to Block 3)
Operating
Ambient
Temperature
0 to 60
° C
during flash memory
program and erase
operation
Topr
Tstg
Data Space
(Block A, Block B)
-40 to 85
° C
° C
Storage Temperature
-65 to 150
page 280
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(
1)
Table 18.39. Recommended Operating Conditions
Standard
Unit
Symbol
Parameter
Min.
3.0
Typ.
Max.
5.5
V
CC
Supply Voltage
V
V
AVCC
Analog Supply Voltage
VCC
V
SS
Supply Voltage
0
V
V
V
AVSS
Analog Supply Voltage
0
V
IH
Input High ("H") P1
Voltage
5
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7
,
0.7 VCC
V
CC
CC
P80
to P8
7
, P9
to P9
3
, P10
0
to P107
0.8 VCC
0
V
V
V
XIN, RESET, CNVSS
V
IL
Input Low ("L")
Voltage
P15
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
0.3 VCC
P80
to P8
7
, P9
0
to P9
3
, P10
0
to P10
7
0
0.2VCC
-10.0
V
XIN, RESET, CNVSS
IOH(peak)
IOH(avg)
IOL(peak)
I
OL(avg)
Peak Output High
("H") Current
P1
P8
P1
P8
P1
P8
P1
P8
5
0
5
0
5
0
5
0
to P1
to P8
to P1
to P8
to P1
to P8
to P1
to P8
7
, P6
, P9
, P6
, P9
, P6
, P9
, P6
, P9
0
0
0
0
0
0
0
0
to P6
to P9
to P6
to P9
to P6
to P9
to P6
to P9
7
, P7
, P10
, P7
, P10
, P7
, P10
, P7
, P10
0
to P7
7
,
mA
7
3
0
to P107
Average Output
High ("H") Current
7
7
0
to P7
7
,
-5.0
10.0
5.0
mA
mA
mA
7
3
0
to P10
7
7
7
Peak Output Low
("L") Current
7
7
0
to P77,
7
3
0
to P10
Average Output
Low ("L") Current
7
7
0
to P77,
7
3
0 to P10
f(XIN
)
Main Clock Input Oscillation Frequency(4)
0
20
50
2
MHz
kHz
MHz
MHz
MHz
MHz
MHz
ms
f(XCIN
)
Sub Clock Oscillation Frequency
32.768
f
1(ROC) On-chip Oscillator Frequency 1
0.5
1
1
2
f2(ROC) On-chip Oscillator Frequency 2
4
f3(ROC) On-chip Oscillator Frequency 3
8
16
26
20
20
20
50
f(PLL)
f(BCLK) CPU Operation Clock Frequency
SU(PLL) Wait Time to Stabilize PLL Frequency Synthesizer
PLL Clock Oscillation Frequency(4)
10
0
t
V
CC = 5.0 V
VCC = 3.0 V
ms
NOTES:
1. Referenced to VCC = 3.0 to 5.5 V at Topr = -40 to 85 ° C unless otherwise specified.
2. The mean output current is the mean value within 100 ms.
3. The total IOL(peak) for all ports must be 80 mA or less. The total IOH(peak) for all ports must be -80 mA or less.
4. Relationship among main clock oscillation frequency, PLL clock oscillation frequency and supply voltage.
Main clock input oscillation frequency
20MHZ
PLL clock oscillation frequency
20MHZ
20.0
20.0
10.0
0.0
10.0
0.0
2.7
3.0
5.5
3.0
5.5
VCC[V] (main clock: no division)
VCC[V] (PLL clock oscillation)
page 281
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1)
Table 18.40. A/D Conversion Characteristics (
Standard
Symbol
-
Parameter
Measurement Condition
Unit
Min. Typ. Max.
10
Resolution
V
V
V
V
V
V
V
REF= VCC
Bits
LSB
LSB
LSB
LSB
LSB
REF= VCC= 5 V
±3
±5
±2
±3
±5
10 bit
8 bit
Integral Nonlinearity
Error
INL
REF= VCC= 3.3 V
REF = VCC = 3.3 V, 5 V
REF= VCC= 5 V
10 bit
8 bit
-
Absolute Accuracy
REF= VCC= 3.3 V
REF = VCC = 3.3 V, 5 V
±2
±1
±3
±3
LSB
LSB
LSB
LSB
kΩ
DNL
Differential Nonlinearity Error
Offset Error
-
-
Gain Error
R
LADDER
Resistor Ladder
VREF= VCC
10
40
10-bit Conversion Time
µs
µs
t
t
CONV
CONV
V
REF = VCC=5 V, φAD = 10 MHz
3.3
Sample & Hold Function Available
8-bit Conversion Time
Sample & Hold Function Available
VREF = VCC = 5 V, φAD = 10 MHz
2.8
V
V
REF
IA
Reference Voltage
2.0
0
V
CC
V
V
Analog Input Voltage
VREF
NOTES:
1. Referenced to VCC= AVCC= VREF= 3.3 to 5.5 V, VSS= AVSS= 0 V at Topr = -40 to 85° C unless otherwise
specified.
2. Keep φAD frequency at 10 MHz or less. Additionally, divide the fAD if VCC is less than 4.2 V, and make φAD
frequency equal to or lower than fAD/2.
3. When sample & hold function is disabled, keep φAD frequency at 250 kHz or more in addition to the limitation in Note 2.
When sample & hold function is enabled, keep φAD frequency at 1 MHz or more in addition to the limitation in Note 2.
4. When sample & hold function is enabled, sampling time is 3/ φAD frequency.
When sample & hold function is disabled, sampling time is 2/ φAD frequency.
page 282
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1)
Table 18.41. Flash Memory Version Electrical Characteristics
Program Space and Data Space for U3, Program Space for U7
:
Standard
Typ.(2)
100/1000(4, 11)
Symbol
Parameter
Program and Erase Endurance(3)
Word Program Time (VCC= 5.0 V, Topr = 25° C)
Unit
Min.
Max.
cycles
-
-
-
µs
75
600
9
Block Erase Time
2-Kbyte Block
0.2
0.4
0.7
1.2
s
s
(VCC= 5.0 V, Topr = 25° C)
8-Kbyte Block
16-Kbyte Block
32-Kbyte Block
9
9
s
9
s
td(SR-ES) Duration between Suspend Request and Erase Suspend
8
ms
µs
years
tPS
Wait Time to Stabilize Flash Memory Circuit
Data Hold Time (5)
15
-
20
(6)
(7)
Table 18.42. Flash Memory Version Electrical Characteristics : Data Space for U7
Standard
Typ.(2)
Symbol
Parameter
Program and Erase Endurance(3, 8, 9)
Unit
Min.
10000(4, 10)
Max.
cycles
-
-
-
µs
Word Program Time (VCC = 5.0 V, Topr = 25° C)
100
0.3
s
Block Erase Time (VCC = 5.0V, Topr = 25° C)
(2-Kbyte block)
td(SR-ES) Duration between Suspend Request and Erase Suspend
8
ms
µs
t
PS
Wait Time to Stabilize Flash Memory Circuit
Data Hold Time (5)
15
-
20
years
NOTES:
1. Referenced to VCC = 3.0 to 5.5 V at Topr = 0 to 60° C (program space)/ Topr = -40 to 85° C(data space), unless
otherwise specified.
2. VCC = 5.0 V; TOPR = 25° C
3. Program and erase endurance is defined as number of program-erase cycles per block.
If program and erase endurance is n cycle (n = 100, 1000, 10000), each block can be erased and programmed n
cycles.
For example, if a 2-Kbyte block A is erased after programming one-word data to each address 1,024 times,
this counts as one program and erase endurance. Data cannot be programmed to the same address more than
once without erasing the block. (rewrite prohibited).
4. Number of E/W cycles for which operation is guranteed (1 to minimum value are guranteed).
5. Topr = 55° C
6. Referenced to VCC = 3.0 to 5.5 V at Topr = -40 to 85° C unless otherwise specified.
7. Table 18.42 applies for data space in U7 when program and erase endurance is more than 1,000 cycles.
Otherwise, use Table 18.41.
8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites,
write to unused word addresses within the block instead of rewrite. Erase block only after all possible addresses
are used. For example, an 8-word program can be written 128 times maximum before erase becomes necessary.
Maintaining an equal number of times erasure between block A and block B will also improve efficiency. It is
recommended to track the total number of erasure performed per block and to limit the number of erasure.
9. If an erase error is generated during block erase, execute the clear status register command and block erase
command at least 3 times until an erase error is not generated.
10. When executing more than 100 times rewrites, set one wait state per block access by setting the FMR17 bit in
the FMR1 register to 1 (wait state). When accessing to all other blocks and internal RAM, wait state can be set
by the PM17 bit, regardless of the FMR17 bit setting value.
11. The program and erase endurance is 100 cycles for program space and data space in U3; 1,000 cycles
for program space in U7.
12. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for
further details on the E/W failure rate.
Erase suspend
request
(interrupt request)
FMR46
td(SR-ES)
page 283
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 18.43. Power Supply Circuit Timing Characteristics
Standard
Symbol
Parameter
Measurement Condition
Unit
Min. Typ. Max.
td(P-R) Wait Time to Stabilize Internal Supply Voltage when Power-on
td(ROC) Wait Time to Stabilize Internal On-chip Oscillator when Power-on
td(R-S) STOP Release Time(1)
2
ms
µs
40
VCC = 3.0 to 5.5V
1.5
250
ms
µs
td(W-S) Low Power Dissipation Mode Wait Mode Release Time
t
t
d(P-R)
VCC
ROC
Wait time to stabilize internal
supply voltage when power-on
d(ROC)
td(P-R)
td(ROC)
Wait time to stabilize internal
on-chip oscillator when power-
on
RESET
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
t
t
d(R-S)
STOP release time
d(W-S)
Low power dissipation mode
wait mode release time
CPU clock
(a)
(b)
t
t
d(R-S)
d(W-S)
page 284
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
(
1)
Table 18.44. Electrical Characteristics
Standard
Unit
V
Symbol
Parameter
Condition
OH= -5 mA
Min. Typ. Max.
V
OH
OH
Output High P1
5
0
5
0
to P1
to P8
to P1
to P8
7
7
7
7
, P6
, P9
, P6
, P9
0
0
0
0
to P6
to P9
to P6
to P9
7
3
7
3
, P7
, P10
, P7
, P10
0
to P7
to P10
to P7
to P10
7
,
I
I
V
CC
CC
V
CC
-
2.0
("H") Voltage
P8
0
7
Output High P1
0
7,
OH = -200 µA
V
V
V
VCC
-
0.3
V
("H") Voltage
P8
0
7
I
I
OH = -1 mA
V
V
CC
CC
High Power
Low Power
High Power
Low Power
VCC
-
2.0
Output High ("H") Voltage
Output High ("H") Voltage
XOUT
OH = -0.5 mA
VCC
-
2.0
VOH
No load applied
No load applied
2.5
1.6
XCOUT
V
V
V
OL
OL
Output Low P1
5
0
5
0
to P1
to P8
to P1
to P8
7
7
7
7
, P6
, P9
, P6
, P9
0
0
0
0
to P6
to P9
to P6
to P9
7
3
7
3
, P7
0
to P7
7,
I
OL = 5 mA
2.0
("L") Voltage
P8
, P10
, P7
, P10
0
to P10
7
P1
P8
0
to P7
7,
I
OL = 200 µA
0.45
V
V
Output Low
("L") Voltage
V
0
to P10
7
I
I
OL = 1 mA
2.0
2.0
High Power
Low Power
High Power
Low Power
Output Low ("L") Voltage
Output Low ("L") Voltage
XOUT
OL = 0.5 mA
VOL
No load applied
No load applied
0
0
XCOUT
V
V
VT+-VT- Hysteresis
0.2
1.0
TA0IN-TA4IN, TB0IN-TB2IN, INT
0
-INT
5
, NMI, ADTRG
,
CTS -CTS , CLK -CLK , TA2OUT-TA4OUT, KI
0
2
0
2
0-KI3,
RXD0-RXD2
V
T+-VT- Hysteresis
T+-VT- Hysteresis
0.2
0.2
2.5
0.8
V
RESET
V
XIN
V
µA
I
IH
Input High
("H") Current
P1
5
0
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7
,
V
V
V
I
I
I
= 5 V
= 0 V
= 0 V
5.0
P8
to P8
7
, P9
to P9
3
, P10
0
to P10
7
7
7
XIN, RESET, CNVSS
µA
I
IL
Input Low
("L") Current
P15
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
-5.0
P80
to P8
7
, P9
0
to P9
3
, P10
0
to P10
XIN, RESET, CNVSS
R
PULLUP Pull-up
P15
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
30
50 170 kΩ
Resistance
P80
to P8
7
, P9
0
to P9
3
, P10
0
to P10
RfXIN
1.5
15
MΩ
MΩ
V
Feedback Resistance
Feedback Resistance
RAM Standby Voltage
X
IN
CIN
RfXCIN
X
VRAM
In stop mode
2.0
NOTE:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40 to 85 ° C, f(BCLK) = 20 MHz unless otherwise specified.
page 285
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
(
1)
Table 18.45. Electrical Characteristics (2)
Standard
Unit
Symbol
Parameter
Measurement Condition
Min. Typ. Max.
I
CC
Power Supply
Current
(VCC=4.0 to 5.5V) other pins are
connected to VSS
Output pins are Flash memory f(BCLK) = 20 MHz,
16
19 mA
left open and
Main clock, no division
On-chip oscillator operates,
1
mA
f
2(ROC) selected, f(BCLK) = 1 MHz
Flash memory
program
11
mA
f(BCLK) = 10 MHz, Vcc = 5.0 V
f(BCLK) = 10 MHz, Vcc = 5.0 V
Flash memory
erase
12
25
mA
µA
Flash memory f(BCLK) = 32 kHz,
In low-power consumption mode,
Program running on RAM(3)
µA
µA
f(BCLK) = 32 kHz,
In low-power consumption mode,
Program running on flash memory(3)
450
50
On-chip oscillation,
f2(ROC) selected, f(BCLK) = 1 MHz,
In wait mode
f(BCLK) = 32 kHz, In wait mode(2),
Oscillation capacity HIGH
f(BCLK) = 32 kHz, In wait mode(2),
Oscillation capacity LOW
10
3
µA
µA
µA
While clock stops, Topr = 25° C
0.8
3
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40 to 85 ° C, f(BCLK) = 20 MHz unless otherwise specified.
2. With one timer operates, using fC32
3. This indicates the memory in which the program to be executed exists.
.
page 286
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
Timing Requirements
o
(VCC = 5V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.46. External Clock Input (XIN input)
Standard
Min. Max.
50
20
20
Symbol
Parameter
Unit
t
c
ns
ns
ns
ns
ns
External clock input cycle time
t
w(H
)
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
t
w(L)
t
r
9
9
t
f
External clock fall time
page 287
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
Timing Requirements
o
(VCC = 5V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.47. Timer A Input (Counter Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
100
40
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
40
Table 18.48. Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
400
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.49. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.50. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.51. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN
)
t
h(TIN-UP)
400
Table 18.52. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
t
c(TA)
ns
ns
ns
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
t
su(TAIN-TAOUT
su(TAOUT-TAIN
)
)
t
page 288
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
Timing Requirements
o
(VCC = 5V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.53. Timer B Input (Counter Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
t
c(TB)
100
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
t
t
200
80
t
w(TBH)
tw(TBL)
80
Table 18.54. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.55. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.56. A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
t
c(AD)
w(ADL)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
Table 18.57. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
80
0
70
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 18.58. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
page 289
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
XIN input
t
f
t
w(H)
tw(L)
tr
t
c
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
tsu(UP-TIN)
th(TIN-UP)
edge is selected)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
t
su(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 18.5. Timing Diagram (1)
page 290
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
RxDi
tsu(D–C)
td(C–Q)
t
h(C–D)
tw(INL)
INTi input
t
w(INH)
Figure 18.6. Timing Diagram (2)
page 291
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
1)
Table 18.59. Electrical Characteristics (
Standard
Unit
V
Symbol
Parameter
Condition
Min. Typ. Max.
V
OH
Output High P1
5
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7,
I
OH = -1 mA
V
CC
VCC-
0.5
("H") Voltage
P80
to P8
7
, P9
to P9
3
, P10
0
to P107
I
I
OH = -0.1 mA
V
CC
CC
High Power
Low Power
High Power
Low Power
V
CC
-
0.5
Output High ("H") Voltage
Output High ("H") Voltage
X
OUT
V
OH = -50 µA
V
VCC
-
0.5
V
V
OH
OL
No load applied
No load applied
2.5
1.6
XCOUT
V
V
Output Low P1
5
to P17, P6
0
0
to P6
7
, P7
0
to P7
7
,
I
OL = 1 mA
0.5
("L") Voltage
P80
to P87, P9
to P9
3
, P10
0
to P10
7
I
I
OL = 0.1 mA
0.5
0.5
High Power
Output Low ("L") Voltage
Output Low ("L") Voltage
X
OUT
V
OL= 50 µA
Low Power
High Power
Low Power
V
V
OL
No load applied
No load applied
0
0
XCOUT
V
V
T+-VT- Hysteresis
0.8
TA0IN-TA4IN, TB0IN-TB2IN, INT
0
-INT
5, NMI, ADTRG
,
CTS -CTS , CLK -CLK , TA2OUT-TA4OUT, KI
0
2
0
2
0-KI3,
RXD0-RXD2
V
V
T+-VT- Hysteresis
T+-VT- Hysteresis
1.8
0.8
V
RESET
XIN
V
µA
I
IH
Input High
("H") Current
P1
5
0
to P1
7
, P6
0
0
to P6
7
, P7
0
to P7
7
,
V
V
V
I
I
I
= 3 V
= 0 V
= 0 V
4.0
P8
to P8
7
, P9
to P9
3
, P10
0
to P10
7
7
7
XIN, RESET, CNVSS
µA
I
IL
Input Low
("L") Current
P15
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
-4.0
P80
to P8
7
, P9
0
to P9
3
, P10
0 to P10
XIN, RESET, CNVSS
R
PULLUP Pull-up
P15
to P1
7
, P6
0
to P6
7
, P7
0
to P7
7
,
50
100 500 kΩ
Resistance
P80
to P8
7
, P9
0
to P9
3
, P10
0
to P10
RfXIN
3.0
25
MΩ
MΩ
V
Feedback Resistance
Feedback Resistance
RAM Standby Voltage
X
IN
RfXCIN
XCIN
V
RAM
In stop mode
2.0
NOTE:
1. Referenced to VCC= 3.0 to 3.6 V, VSS= 0 V at Topr = -40 to 85 ° C, f(BCLK) = 20 MHz unless otherwise specified.
page 292
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
1)
Table 18.60. Electrical Characteristics (2) (
Standard
Unit
Symbol
Parameter
Measurement Condition
Min. Typ. Max.
I
CC
Power Supply
Current
(VCC=3.0 to 3.6V) other pins are
connected to VSS
Output pins are Flash memory f(BCLK) = 10 MHz,
7
12 mA
left open and
Main clock, no division
On-chip oscillator operates,
1
mA
f
2(ROC) selected, f(BCLK) = 1 MHz
Flash memory
program
10
mA
f(BCLK) = 10 MHz, Vcc = 3.0 V
f(BCLK) = 10MHz, Vcc = 3.0 V
Flash memory
erase
11
25
mA
µA
Flash memory f(BCLK) = 32 kHz,
In low-power consumption mode,
Program running on RAM(3)
µA
µA
f(BCLK) = 32 kHz,
In low-power consumption mode,
Program running on flash memory(3)
450
45
On-chip oscillator operates,
f
2(ROC) selected, f(BCLK) = 1 MHz,
In wait mode
f(BCLK) = 32 kHz, In wait mode(2),
Oscillation capacity HIGH
f(BCLK) = 32 kHz,In wait mode(2),
Oscillation capacity LOW
10
3
µA
µA
µA
While clock stops, Topr = 25° C
0.7
3
NOTES:
1. Referenced to VCC= 3.0 to 3.6 V, VSS= 0 V at Topr = -40 to 85 ° C, f(BCLK) = 20 MHz unless otherwise specified.
2. With one timer operates, using fC32
3. This indicates the memory in which the program to be executed exists.
.
page 293
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
Timing Requirements
o
(VCC = 3V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.61. External Clock Input (XIN input)
Standard
Symbol
Parameter
Unit
Min.
Max.
t
c
ns
ns
ns
ns
ns
External clock input cycle time
100
t
w(H
)
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
40
t
w(L)
40
t
r
18
18
t
f
External clock fall time
page 294
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
Timing Requirements
o
(VCC = 3V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.62. Timer A Input (Counter Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
150
60
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
60
Table 18.63. Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
600
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
300
300
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.64. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.65. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.66. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN)
t
h(TIN-UP)
600
Table 18.67. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
t
c(TA)
µs
ns
ns
2
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
t
t
su(TAIN-TAOUT
)
)
500
500
su(TAOUT-TAIN
page 295
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
Timing Requirements
o
(VCC = 3V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.68. Timer B Input (Counter Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
t
c(TB)
150
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
60
60
t
t
300
120
120
t
w(TBH)
tw(TBL)
Table 18.69. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.70. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.71. A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 18.72. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
160
0
100
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 18.73. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
page 296
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
XIN input
t
f
t
w(H)
tw(L)
tr
t
c
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During Event Counter Mode
TAiIN input
(When count on falling
th(TIN-UP) tsu(UP-TIN)
edge is selected)
TAiIN input
(When count on rising
edge is selected)
Two-Phase Pulse Input in Event Counter Mode
tc(TA)
TAiIN input
t
su(TAIN-TAOUT)
tsu(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
t
su(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 18.7. Timing Diagram (1)
page 297
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
18. Electrical Characteristics (M16C/26T)
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
VCC = 3V
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
tsu(D–C)
t
d(C–Q)
t
h(C–D)
t
w(INL)
INTi input
tw(INH)
Figure 18.8. Timing Diagram (2)
page 298
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19. Usage Notes
19.1 SFR
19.1.1 Precaution for 48-pin package
Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR
register to "1002".
19.1.2 Precaution for 42-pin package
Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR
register to "0012".
19.1.3 Register Setting
Immediate values should be set in the registers containing write-only bits. When establishing a new value
by modifying a previous value, write the previous value into RAM as well as the register. Change the
contents of the RAM and then transfer the new value to the register.
page 299
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.2 PLL Frequency Synthesizer
Stabilize supply voltage so that the standard of the power supply ripple is met.
Standard
Typ.
Symbol
Unit
Parameter
Min.
Max.
f
(ripple)
Power supply ripple allowable frequency(VCC
)
10
0.5
0.3
0.3
0.3
kHz
V
V
p-p(ripple)
Power supply ripple allowabled amplitude
voltage
(VCC=5V)
(VCC=3V)
(VCC=5V)
(VCC=3V)
V
V
CC(|∆V/∆T|)
Power supply ripple rising/falling gradient
V/ms
V/ms
f(ripple)
f(ripple)
Power supply ripple allowable frequency
(VCC
)
Vp-p(ripple)
Power supply ripple allowable amplitude
voltage
VCC
V
p-p(ripple)
Figure 19.1 Timing of Voltage Fluctuation
page 300
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.3 Power Control
1. When exiting stop mode by hardware reset, the device will startup using the on-chip oscillator.
2. Set the MR0 bit in the TAiMR register(i=0 to 4) to “0”(pulse is not output) to use the timer A to exit stop
mode.
3. When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not excute any
instructions which can generate a write to RAM between the JMP.B and WAIT instructions. Disable the
DMA transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT
instruction, insert at least 4 NOP instructions. When entering wait mode, the instruction queue reads
ahead the instructions following WAIT, and depending on timing, some of these may execute before the
microcomputer enters wait mode.
Program example when entering wait mode
Program Example:
JMP.B
L1
I
; Insert JMP.B instruction before WAIT instruction
L1:
FSET
WAIT
NOP
NOP
NOP
NOP
;
; Enter wait mode
; More than 4 NOP instructions
4. When entering stop mode, insert a JMP.B instruction immediately after executing an instruction which
sets the CM10 bit in the CM1 register to “1”, and then insert at least 4 NOP instructions. When entering
stop mode, the instruction queue reads ahead the instructions following the instruction which sets the
CM10 bit to “1” (all clock stops), and, some of these may execute before the microcomputer enters stop
mode or before the interrupt routine for returning from stop mode.
Program example when entering stop mode
Program Example:
FSET
BSET
JMP.B
I
CM10
L1
; Enter stop mode
; Insert JMP.B instruction
L1:
NOP
NOP
NOP
NOP
; More than 4 NOP instructions
page 301
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
5. Wait until the main clock oscillation stabilization time, before switching the CPU clock source to the
main clock.
Similarly, wait until the sub clock oscillates stably before switching the CPU clock source to the sub
clock.
6. Suggestions to reduce power consumption
(a) Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A
current flows in active I/O ports. A dash current may flow through the input ports in high impedance
state, if the input is floating. When entering wait mode or stop mode, set non-used ports to input and
stabilize the potential.
(b) A/D converter
When A/D conversion is not performed, set the VCUT bit in the ADCON1 register to “0” (no VREF
connection). When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after
setting the VCUT bit to “1” (VREF connection).
(c) Stopping peripheral functions
Use the CM02 bit in the CM0 register to stop the unnecessary peripheral functions during wait mode.
However, because the peripheral function clock (fC32) generated from the sub-clock does not stop,
this measure is not conducive to reducing the power consumption of the chip. If low speed mode or
low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not stop
peripheral function clocks in wait mode), before changing wait mode.
(d) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
page 302
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.4 Protect
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction.
page 303
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.5 Interrupts
19.5.1 Reading address 0000016
Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU
reads interrupt information (interrupt number and interrupt request priority level) from the address
0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or an
unexpected interrupt request is generated.
19.5.2 Setting the SP
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to ‘000016’
after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the pro-
gram may go out of control.
19.5.3 The _N__M___I_ Interrupt
_______
_______
1. The NMI interrupt is invalid after reset. The NMI interrupt becomes effective by setting to “1” the PM24
_______
bit in the PM2 register. Set the PM24 bit to "1" when a high-level signal ("H") is applied to the NMI pin.
_______
_______
If the PM24 bit is set to "1" when a low-level signal ("L") is applied, NMI interrupt is generated. Once NMI
interrupt is enabled, it will not be disabled unless a reset is applied.
_______
2. The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register.
_______
_______
3. When selecting NMI function, stop mode cannot be entered into while input on the NMI pin is low. This
_______
is because while input on the NMI pin is low the CM10 bit in the CM1 register is fixed to “0”.
_______
_______
4. When selecting NMI function, do not go to wait mode while input on the NMI pin is low. This is because
_______
when input on the NMI pin goes low, the CPU stops but CPU clock remains active; therefore, the current
consumption in the chip does not drop. In this case, normal condition is restored by an interrupt gener-
ated thereafter.
_______
_______
5. When selecting NMI function, the low and high level durations of the input signal to the NMI pin must
each be 2 CPU clock cycles + 300 ns or more.
_______
6. When using the NMI interrupt for exiting stop mode, set the NDDR register to “FF16” (disable digital
debounce filter) before entering stop mode.
19.5.4 Changing the Interrupt Generation Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor
for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt not
requested).
“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity
or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any
peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to
clear the IR bit for that interrupt to “0” (interrupt not requested) after making such changes. Refer to the
description of each peripheral function for details about the interrupts from peripheral functions.
Figure 19.2 shows the procedure for changing the interrupt generate factor.
page 304
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Changing the interrupt source
Disable interrupts (2, 3)
Change the interrupt generate factor (including a mode change of peripheral function)
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (3)
Enable interrupts (2, 3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed
NOTES:
1. The above settings must be executed individually. Do not execute two or more settings simultaneously
(using one instruction).
2. Use the I flag for the INTi interrupt (i = 0 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the peripheral function that
is the source of the interrupt in order not to generate an interrupt request before changing the interrupt
generate factor. In this case, if the maskable interrupts can all be disabled without causing a problem, use
the I flag. Otherwise, use the corresponding
3. Refer to 19.5.6 Rewrite the Interrupt Control Register for details about the instructions to use and the
notes to be taken for instruction execution.
Figure 19.2. Procedure for Changing the Interrupt Generate Factor
19.5.5 _I_N__T__ Interrupt
1. Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal
_______
_______
input to pins INT0 through INT5 regardless of the CPU operation clock.
2. If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0
(interrupt not requested) after changing any of those register bits.
3. When using the INT5 interrupt for exiting stop mode, set the P17DDR register to “FF16” (disable digital
debounce filter) before entering stop mode.
page 305
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.5.6 Rewrite the Interrupt Control Register
(1) The interrupt control register for any interrupt should be modified in places where no requests for that
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
instruction to be used.
Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown below
to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not re-
quested). Therefore, be sure to use the MOV instruction to clear the IR bit.
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as
you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewritten, due to the internal bus and the instruction queue buffer timing.
Example 1: Using the NOP instruction to keep the program waiting until the
interrupt control register is modified
INT_SWITCH1:
FCLR
AND.B
NOP
I
; Disable interrupts
;Set the TA0IC register to 0016
;
#00h, 0055h
NOP
FSET
I
; Enable interrupts
The number of NOP instruction is as follows.
PM20 = 1 (1 wait) : 2, PM20 = 0 (2 waits): 3
Example 2:Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR
AND.B
MOV.W MEM, R0
FSET
I
; Disable interrupts
; Set the TA0IC register to 0016
; Dummy read
#00h, 0055h
I
; Enable interrupts
Example 3:Using the POPC instruction to changing the I flag
INT_SWITCH3:
PUSHC FLG
FCLR
AND.B
POPC
I
; Disable interrupts
; Set the TA0IC register to 0016
; Enable interrupts
#00h, 0055h
FLG
19.5.7 Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
page 306
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.6 DMAC
19.6.1 Write to DMAE Bit in DMiCON Register
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.
(*1)
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously
.
(*2)
Step 2: Make sure that the DMAi is in an initial state
in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
Notes:
1. The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set to
“0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should be
written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit
immediately before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to
the DMAS bit in order to maintain a DMA request which is generated during execution.
2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a
value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state.
(If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is “1”.) If
the read value is a value in the middle of transfer, the DMAi is not in an initial state.
page 307
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.7 Timer
19.7.1 Timer A
19.7.1.1 Timer A (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count
starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the TAi register is read at the same time the counter is reloaded, the read value
is always “FFFF16”. If the TAi register is read after setting a value in it, but before the counter starts
counting, the read value is the one that has been set in the register.
_____
3. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT
pins go to a high-impedance state.
19.7.1.2 Timer A (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the
ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”
(count starts).
Always make sure the TAiMR register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits and
the TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether
after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the TAi register is read at the same time the counter is reloaded, the read value
is always “FFFF16” when the timer counter underflows and “000016” when the timer counter over-
flows. If the TAi register is read after setting a value in it, but before the counter starts counting, the
read value is the one that has been set in the register.
_____
3. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT
pins go to a high-impedance state.
page 308
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.7.1.3 Timer A (One-shot Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the
TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are
modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
2. When setting TAiS bit to “0” (count stop), the following occur:
• The counter stops counting and the content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to “1” (interrupt request).
3. Output in one-shot timer mode synchronizes with a count source internally generated. When the
external trigger has been selected, a maximun delay of one cycle of the count source occurs be-
tween the trigger input to TAiIN pin and output in one-shot timer mode.
4. The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change the operation mode from timer mode to one-shot timer mode.
• Change the operation mode from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have
been made.
5. When a trigger occurs while the timer is counting, the counter reloads the reload register value, and
continues counting after a second trigger is generated and the counter is decremented once. To
generate a trigger while counting, space more than one cycle of the timer count source from the first
trigger and generate again.
6. When selecting the external trigger for the count start conditions in timer A one-shot timer mode, do
generate an external trigger 300ns before the count value of timer A is set to “000016”. The one-shot
timer does not continue counting and may stop.
_____
7. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT
pins go to a high-impedance state.
page 309
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.7.1.4 Timer A (Pulse Width Modulation Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the
TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are
modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the PWM mode after reset.
• Change an operation mode from timer mode to PWM mode.
• Change an operation mode from event counter mode to PWM mode.
To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above
listed changes have been made.
3. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.
_____
4. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT
pins go to a high-impedance state.
page 310
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.7.2 Timer B
19.7.2.1 Timer B (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to “1” (count
starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
2. The counter value can be read out at any time by reading the TBi register. However, if this register
is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the TBi
register is read after setting a value in it but before the counter starts counting, the read value is the
one that has been set in the register.
19.7.2.2 Timer B (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to “1” (count
starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
2. The counter value can be read out at any time by reading the TBi register. However, if this register
is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the TBi
register is read after setting a value in it but before the counter starts counting, the read value is the
one that has been set in the register.
page 311
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)
1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2)
register before setting the TBiS bit in the TABSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register
while the TBiS bit is set to “1” (count starts), be sure to set the TM0D0, TM0D1, MR0, MR1, TCK0
and TCK1 bits to the same value as previously written and the MR2 bit to "0".
2. The IR bit in the TBiIC register (i=0 to 2) goes to “1” (interrupt request), when an effective edge of
a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be
determined by use of the MR3 bit in the TBiMR register within the interrupt routine.
3. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
input and a timer overflow occur at the same time, use another timer to count the number of times
timer B has overflowed.
4. To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and
counting the next count source after setting the MR3 bit to “1” (overflow).
5. Use the IR bit in the TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.
6. When the count is started and the first effective edge is input, an indeterminate value is transferred
to the reload register. At this time, timer Bi interrupt request is not generated.
7. The value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and
timer Bi interrupt request may be generated between the count start and an effective edge input.
8. For pulse width measurement, pulse widths are successively measured. Use program to check
whether the measurement result is an “H” level width or an “L” level width.
19.7.3 Three-phase Motor Control Timer Function
When the IVPCR1 bit in the TB2SC register is set to 1 (three-phase output forced cutoff by SD pin input
(high-impedance) enabled), the INV03 bit in the INVC0 register is set to 1 (three-phase motor control
_____
timer output enabled), and a low-level ("L") signal is applied to the SD pin while a three-phase PWM
___
___
___
signal is output, the MCU is forced to cutoff and pins U, U, V, V, W, and W are placed in a high-impedance
state and the INV03 bit is set to 0 (three-phase motor control timer output disabled).
___
___
___
To resume the three-phase PWM signal output from pins U, U, V, V, W, and W, set the INV03 bit to 1 and
_____
the IVPCR1 bit to 0 (three-phase output forced cutoff disabled) after the SD pin level becomes "H". Then
set the IVPCR1 bit to 1 (three-phase output forced cutoff enabled) in order to enable the three-phase
output forced cutoff function by input to the SD pin again.
_____
The INV03 bit cannot be set to 1 while an "L" signal is input to the SD pin. To set the INV03 bit to 1 after
forcible cutoff, write 1 to the INV03 bit and read the bit to ensure that it is set to 1 by program. Then set the
IVPCR1 bit to 1 after setting it to 0.
page 312
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.8 Serial I/O
19.8.1 Clock-Synchronous Serial I/O
19.8.1.1 Transmission/reception
_______
________
1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin
goes to “L” when the data-receivable status becomes ready, which informs the transmission side
________
that the reception has become ready. The output level of the RTSi pin goes to “H” when reception
________
________
starts. So if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can
_______
transmit and receive data with consistent timing. With the internal clock, the RTS function has no
effect.
_____
2. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
_________
(three-phase output forcible cutoff by input on SD pin enabled), the P73/RTS2/TxD1(when the
U1MAP bit in PACR register is “1”) and CLK2 pins go to a high-impedance state.
19.8.1.2 Transmission
When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0
register is set to “0” (transmit data output at the falling edge and the receive data taken in at the
rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0
register is set to “1” (transmit data output at the rising edge and the receive data taken in at the
falling edge of the transfer clock), the external clock is in the low state.
• The TE bit in the UiC1 register is set to “1” (transmission enabled)
• The TI bit in the UiC1 register is set to “0” (data present in UiTB register)
_______
_______
• If CTS function is selected, input on the CTSi pin is “L”
19.8.1.3 Reception
1. In operating the clock-synchronous serial I/O, operating the transmitter generates a clock for the
receiver shift register. Fix settings for transmission even when using the device only for reception.
Dummy data is output to the outside from the TxDi pin when receiving data.
2. When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission
enabled) and write dummy data to the UiTB register, and the clock for the receiver shift register will
thereby be generated. When an external clock is selected, set the TE bit to "1" and write dummy
data to the UiTB register, and the clock for the receiver shift register will be generated when the
external clock is fed to the CLKi input pin.
3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi
receive register while the RE bit in the UiC1 register (i = 0 to 2) is set to “1” (data present in the UiRB
register), an overrun error occurs and the OER bit in the UiRB register is set to “1” (overrun error
occurred). In this case, because the content of the UiRB register is indeterminate, a corrective
measure must be taken by programs on the transmit and receive sides so that the valid data before
the overrun error occurred will be retransmitted. Note that when an overrun error occurred, the IR
bit in the SiRIC register does not change state.
4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every
time reception is made.
5. When an external clock is selected, make sure the external clock is in high state if the CKPOL bit is
set to “0”, and in low state if the CKPOL bit is set to “1” before the following conditions are met:
• Set the RE bit in the UiC1 register to “1” (reception enabled)
• Set the TE bit in the UiC1 register to “1” (transmission enabled)
• Set the TI bit in the UiC1 register to “0” (data present in the UiTB register)
page 313
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.8.2 Serial I/O (UART Mode)
2
19.8.1.1 Special Mode 1 (I C bus Mode)
When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to “0”
and wait for more than half cycle of the transfer clock before setting each condition generate bit
(STAREQ, RSTAREQ and STPREQ) from “0” to “1”.
19.8.1.2 Special Mode 2
_______ _____
If a low-level signal is applied to the P85/NMI/SD pin when the IVPCR1 bit in the TB2SC register is set
_____
to "1" (three-phase output forcible cutoff by input on SD pin enabled), the P73/RTS2/TxD1(when the
U1MAP bit in PACR register is “1”) and CLK2 pins go to a high-impedance state.
19.8.1.3 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmis-
sion complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM
mode, be sure to clear the IR bit to “0” (no interrupt request) after setting these bits.
page 314
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.9 A/D Converter
1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before
a trigger occurs).
2. When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (VREF
connected), start A/D conversion after waiting 1 µs or longer.
3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi(i=0 to 7), AN24, AN3i(i=0 to 2)) each
and the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 19.4 is an
example connection of each pin.
4. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the TGR bit in ADCON0 register is set to "1" (external trigger), make sure the port
___________
direction bit for the ADTRG pin is set to “0” (input mode).
5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A/D input voltage goes low.)
6. The φAD frequency must be 10 MHz or less (12 MHz or less in M16C/26B). Without sample-and-hold
function, limit the φAD frequency to 250kHZ or more. With the sample and hold function, limit the φAD
frequency to 1MHZ or more.
7. When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits in the
ADCON0 register and the SCAN1 to SCAN0 bits in the ADCON1 register.
Microcomputer
V
CC
V
CC
V
V
CC
SS
AVCC
C4
V
REF
C2
C1
C3
AVSS
AN
i
AN
i: ANi(i=0 to 7), AN24, and AN3i (i=0 to 2)
NOTES:
1. C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference)
2. Use thick and shortest possible wiring to connect capacitors.
Figure 19.3. Use of capacitors to reduce noise
page 315
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
8. If the CPU reads the A/D register i (i = 0 to 7) at the same time the conversion result is stored in the A/
D register i after completion of A/D conversion, an incorrect value may be stored in the A/D register i.
This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for
CPU clock.
• When operating in one-shot mode, single-sweep mode, simultaneous sample sweep mode, delayed
trigger mode 0 or delayed trigger mode 1
Check to see that A/D conversion is completed before reading the target A/D register i. (Check the IR
bit in the ADIC register to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0
register to “0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The
contents of A/D register i irrelevant to A/D conversion may also become indeterminate. If while A/D
conversion is underway the ADST bit is cleared to “0” in a program, ignore the values of all A/D register
i.
10.When setting the ADST bit in the ADCON register to "0" to terminate a conversion forcefully by the
program in single sweep conversion mode, A/D delayed trigger mode 0 and A/D delayed trigger mode
1 during A/D conversion operation, the A/D interrupt request may be generated. If this causes a prob-
lem, set the ADST bit to "0" after the interrupt is disabled.
page 316
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.10 Programmable I/O Ports
_____
1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”
_____
(three-phase output forcible cutoff by input on SD pin enabled), the P72 to P75, P80 and P81 pins go to
a high-impedance state.
2. The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the
input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither
“high” nor “low”), the input level may be determined differently depending on which side—the program-
mable input/output port or the peripheral function—is currently selected.
3. When the INV03 bit in the INVC0 register is "1"(three-phase motor control timer output enabled), an "L"
_______ _____
input on the P85 /NMI/SD pin, has the following effect:
•When the IVPCR1 bit in the TB2SC register is set to “1” (three-phase output forcible cutoff by input
_____
__
__
___
on the SD pin enabled), the U/ U/ V/ V/ W/ W pins go to a high-impedance state.
_____
•When the IVPCR1 bit is set to “0” (three-phase output forcible cutoff by input on SD pin
__
__
___
disabled), the U/ U/ V/ V/ W/ W pins go to a normal port.
Therefore, the P85 pin can not be used as programmable I/O port when the INV03 bit is set to "1".
_____
_______ _____
When the SD function isn't used, set PD85 to “0” (Input) and pull the P85 /NMI/SD pin to “H” externally.
page 317
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.11 Electric Characteristic Differences Between Mask ROM and Flash Memory Ver-
sion Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin, noise
tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern,
etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests con-
ducted in the flash memory version.
page 318
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.12 Mask ROM Version
19.12.1 Internal ROM area
When using the masked ROM version, write nothing to internal ROM area. Writing to the area may
increase power consumption.
19.12.2 Reserve bit
The b3 to b0 in address 0FFFFF16 are reserved bits. Set these bits to “11112”.
page 319
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.13 Flash Memory Version
19.13.1 Functions to Inhibit Rewriting Flash Memory
ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716,
and 0FFFFB16. If wrong data is written to these addresses, the flash memory cannot be read or written in
standard serial I/O mode.
The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H)
of fixed vectors.The b3 to b0 in address 0FFFFF16 are reserved bits. Set these bits to “11112”.
19.13.2 Stop mode
When the microcomputer enters stop mode, execute the instruction which sets the CM10 bit to “1”(stop
mode) after setting the FMR01 bit to “0”(CPU rewrite mode disabled) and disabling the DMA transfer.
19.13.3 Wait mode
When the microcomputer enters wait mode, excute the WAIT instruction after setting the FMR01 bit to
“0”(CPU rewrite mode disabled).
19.13.4 Low power dissipation mode, on-chip oscillator low power dissipation mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
19.13.5 Writing command and data
Write the command code and data at even addresses.
19.13.6 Program Command
Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in the
first bus cycle is the same even address as the write address specified in the second bus cycle.
19.13.7 Operation speed
When CPU clock source is main clock, before entering CPU rewrite mode (EW0 or EW1 mode), select 10
MHz or less for BCLK using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1
register. Also, when CPU clock is f3(ROC) on-chip oscillator clock, before entering CPU rewrite mode
(EW0 or EW1 mode), set the ROCR3 to ROCR2 bits in the ROCR register to “divied by 4” or “divide by 8”.
On both cases, set the PM17 bit in the PM1 register to “1” (with wait state).
19.13.8 Instructions prohibited in EW0 Mode
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
page 320
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.13.9 Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used, providing that its vector
is transferred into the RAM area.
_______
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 regis-
ter are initialized when one of those interrupts occurs. The jump addresses for those interrupt
service routines should be set in the fixed vector table.
_______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is refer-
enced.
EW1 Mode
• Make sure that any interrupt which has a vector in the relocatable vector table or address match
interrupt will not be accepted during the auto program period or auto erase period with erase-
suspend function disabled.
_______
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table.
_______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.
19.13.10 How to access
To set the FMR01, FMR02, FMR11 or FMR16 bit to “1”, set the subject bit to “1” immediately after setting
to “0”. Do not generate an interrupt or a DMA transfer between the instruction to set the bit to “0” and the
_______
instruction to set the bit to “1”. When the PM24 bit is set to “1” (NMI funciton), apply a high-level (“H”)
_______
signal to the NMI pin to set those bits.
19.13.11 Writing in the user ROM area
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse-
quently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
19.13.12 DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR00 bit in the FMR0 register is set
to "0" (during the auto program or auto erase period).
19.13.13 Regarding Programming/Erasure Times and Execution Time
As the number of programming/erasure times increases, so does the execution time for software com-
mands (Program, and Block Erase).
_______
The software commands are aborted by hardware reset 1, hardware reset 2, NMI interrupt, and watchdog
timer interrupt. If a software command is aborted by such reset or interrupt, the affected block must be
erased before reexecuting the aborted command.
page 321
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.13.14 Definition of Programming/Erasure Times
"Number of programs and erasure" refers to the number of erasure per block.
If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times.
For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different
address, this is counted as one program and erasure. However, data cannot be written to the same
adrress more than once without erasing the block. (Rewrite prohibited)
19.13.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle products (U7, U9)
When Block A or B E/W cycles exceed 100, select one wait state per block access. When FMR17 is set
to "1", one wait state is inserted per access to Block A or B - regardless of the value of PM17. Wait state
insertion during access to all other blocks, as well as to internal RAM, is controlled by PM17 - regardless
of the setting of FMR17.
To use the limited number of erasure efficiently, write to unused address within the block instead of
rewite. Erase block only after all possible address are used. For example, an 8-word program can be
written 128 times before erase becomes necessary.
Maintaining an equal number of erasure between Block A and B will also improve efficiency.
We recommend keeping track of the number of times erasure is used.
19.13.16 Boot Mode
An indeterminate value is sometimes output in the I/O port until the internal power supply becomes stable
_____________
when "H" is applied to the CNVSS pin and "L" is applied to the RESET pin.
When setting the CNVSS pin to "H", the following procedure is required:
____________
(1) Apply an "L" signal to the RESET pin and the CNVSS pin.
(2) Bring VCC to more than 2.7V, and wait at least 2msec. (Internal power supply stable waiting time)
(3) Apply an "H" signal to the CNVSS pin.
____________
(4) Apply an "H" signal to the RESET pin.
When the CNVSS pin is “H” and RESET pin is “L”, P67 pin is connected to the pull-up resister.
page 322
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.14 Noise
Connect a bypass capacitor (approximately 0.1µF) across the VCC and VSS pins using the shortest and
thicker possible wiring. Figure 19.4 shows the bypass capacitor connection.
M16C/26A Group
(M16C/26A, M16C/26B, M16C/26T)
VSS
VCC
Connecting Pattern
Connecting Pattern
Bypass Capacitor
Figure 19.4 Bypass Capacitor Connection
page 323
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
19. Usage Notes
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
19.15 Instruction for a Device Use
When handling a device, extra attention is necessary to prevent it from crashing during the electrostatic
discharge period.
page 324
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
Appendix 1. Package Dimensions
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
NOTE)
1. DIMENSIONS " 1" AND " 2"
37
24
2. DIMENSION " 3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
A
6.9 7.0 7.1
6.9 7.0 7.1
Terminal cross section
48
13
HD
8.8 9.0 9.2
8.8
E
1
12
1.7
0.1 0.2
0.17 0.22 0.27
0.20
Index mark
ZD
A1
0
F
p
b1
c
0.145
0.125
0.09
0.20
L
c1
L1
0
8
e
x
0.5
y
*3
Detail F
0.08
0.10
p
y
ZD
ZE
L
0.75
0.75
0.5
0.35
0.65
L1
1.0
JEITA Package Code
RENESAS Code
PRSP0042GA-B
Previous Code
42P2R-E
MASS[Typ.]
0.6g
P-SSOP42-8.4x17.5-0.80
42
F
NOTE)
1. DIMENSIONS "1" AND "2"
2. DIMENSION " 3" DOES NOT
INCLUDE TRIM OFFSET.
1
A2
A1
Index mark
Reference
Symbol
*2
Min Nom Max
D
D
E
17.3 17.5 17.7
8.2 8.4 8.6
A2
A
2.0
2.4
A1
bp
c
0.05
0.25
0.13 0.15
bp
e
y
0.3 0.4
Detail F
0.2
HE
e
y
11.63 11.93 12.23
0.8
0.65
0.95
0.15
0.3 0.5 0.7
L
page 325
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
Appendix 2. Functional Difference
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Appendix 2. Functional Difference
Appendix 2.1 Differences between M16C/26A, M16C/26B, and M16C/26T
Item
M16C/26A, M16C/26B
M16C/26T
Main Clock during
and after Reset
Oscillating
(Default value “0” while and after the
Stoped
(Default value “1” while and after the
CM05 bit is reset.)
CM05 bit is reset.)
Voltage Detection
Circuit
Available
(VCR1 register, VCR2 register,
D4INT register)
Not available
(reserved register)
(Function of 001916,
001A16, 001F16)
Package
NOTE:
PLQP0048KB-A(48P6Q), PRSP0042GA-B(42P2R) PLP0048KB-A(48P6Q)
1. Since the emulator between the M16C/26A Group and M16C/29 Group are the same, all functions of
M16C/29 are built in the emulator. When evaluating M16C/26A Group, do not access to the SFR which
is not built in M16C/26A Group. Refer to Hardware Manual about detail and electrical characteristics.
page 326
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
Appendix 2. Functional Difference
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Appendix 2.2 Differences between M16C/26A Group and M16C/26 Group
Item
M16C/26A Group
M16C/26 Group
Clock Generation
Circuit
4 circuits (Main clock oscillation circuit, 3 circuits (Main clock oscillation circuit,
Sub clock oscillation circuit,
on-chip oscillator,
Sub clock oscillation circuit,
on-chip oscillator)
PLL frequency synthesizer)
System Clock
On-chip oscillator
Main clock
Source After Reset (Initial value "1" of CM21 bit)
(Initial value of the CM21
(Initial value "0" of CM21 bit)
bit in the CM2 register)
On-chip Oscillator Clock Selectable (8MHz/1MHz/500KHz)
PACR2 to PACR0 in Necessary to set after reset
Fixed (1MHz)
No PACR register
the PACR register
IFSR20 bit in the
IFSR2A register
External Interrupt
48pin:"1002", 42pin:"0012"
Necessary to set to "1" after reset
No IFSR2A register
________
8 causes (INT2 added)
7 causes
IVCC
________
13 pin (48-pin version) P84/INT2/ZP
Function
P70, P71
N-ch open drain output and CMOS
output are selectable by S/W
12 channels
N-ch open drain output
8 channels
A/D Input Pin
(48-pin version)
A/D operation Mode 8 modes (single, repeat, single sweep, 5 modes (single, repeat, single sweep,
repeat sweep mode 0, repeat sweep
mode 1, simultaneous sampling,
delayed trigger mode 0, delayed
trigger mode 1)
repeat sweep mode 0, repeat sweep
mode 1)
1 shunt current measurement function
is available
Timer B Operation 5 modes (timer, event counter, pulse
4 modes (timer, event counter, pulse
periods measurement, pulse width
measurment)
Mode
periods measurement, pulse width
measurment, A/D trigger)
1 shunt current measurement function
is available
CRC Calculation
Available (compatible to CRC-CCITT
and CRC-16 methods)
Not available
Three-phase motor •Waveform output/Switching port output •Waveform output/Switching port output
Control
by software is enabled
by software is disabled
•Position data retention function
•No position data retention function
_______ _____
Digital Debounce
Function
This function is in the NMI/SD pin and
INT5 pin
Not available
________
3 pin (48-pin version) P90/CLKOUT/TB0IN/AN30
P90/TB0IN
function
(CLKOUT: f1, f8, f32, and fC output)
UART1 Compatible Switching to P64 to P67 or P70 to P73
P64 to P67
pin
is enabled
Flash Memory
Protect Function
Protection to blocks 0, 1 by FMR02 bit
Protection to the blocks 0 to 3 by
FMR16 bit
Protection to blocks 0,1 by FMR02 bit
Package
NOTE:
PLQP0048KB-A(48P6Q), PRSP0042GA-B(42P2R) PLQP0048KB-A(48P6Q)
1. Since the emulator between the M16C/26A Group and M16C/29 Group are the same, all functions of
M16C/29 are built in the emulator. When evaluating M16C/26A Group, do not access to the SFR which
is not built in M16C/26A Group. Refer to Hardware Manual about detail and electrical characteristics.
page 327
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
Register Index
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Register Index
IFSR2A 68
INT0IC to INT2IC 67
INT3IC 67
A
AD0 to AD7 184
ADCON0 to ADCON2 182
ADIC 67
INT4IC 67
INT5IC 67
ADSTAT0 184
ADTRGCON 183
AIER 79
INVC0 119
INVC1 120
K
B
KUPIC 67
BCNIC 67
N
C
NDDR 227
CM0 40
O
CM1 41
CM2 42
ONSF 96
CPSRF 96, 110
CRCD 214
CRCIN 214
CRCMR 214
CRCSAR 214
P
P0 to P13 224
P17DDR 227
PACR 139, 226
PCLKR 43
D
PCR 226
D4INT 30
DAR0 86
PD0 to PD13 223
PDRF 129
DAR1 86
PFCR 131
DM0CON 85
DM0IC 67
DM0SL 84
DM1CON 85
DM1IC 67
DM1SL 85
DTT 121
PLC0 44
PM0 35
PM1 35
PM2 36, 43
PRCR 60
PUR0 to PUR2 225
R
F
RMAD0 79
RMAD1 79
ROCR 41
FMR0 241
FMR1 241
FMR4 242
ROMCP 236
I
S
ICTB2 121
IDB0 121
S0RIC to S2RIC 67
S0TIC to S2TIC 67
SAR0 86
IDB1 121
IFSR 68, 76
SAR1 86
page 328
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
Register Index
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
T
W
TA0 to TA4 95
TA0IC to TA4IC 67
TA0MR to TA4MR 94
TA1 122
WDC 81
WDTS 81
TA11 122
TA1MR 125
TA2 122
TA21 122
TA2MR 125
TA2MR to TA4MR 101
TA4 122
TA41 122
TA4MR 125
TABSR 95, 110, 124
TAiMR 99, 106
TB0 to TB5 110
TB0IC TO TB2IC 67
TB0MR to TB5MR 109
TB2 124
TB2MR 125
TB2SC 123, 185
TCR0 86
TCR1 86
TPRC 131
TRGSR 96, 124
U
U0BRG to U2BRG 136
U0C0 to U2C0 138
U0C1 to U2C1 139
U0MR to U2MR 137
U0RB to U2RB 136
U0TB to U2TB 136
U2SMR 140
U2SMR2 140
U2SMR3 141
U2SMR4 141
UCON 138
UDF 95
V
VCR1 30
VCR2 30
page 329
Rev. 2.00 Feb.15, 2007
REJ09B0202-0200
of 329
REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual
Rev.
Date
Description
Summary
Page
-
2.00 Feb.15,07
M16C/26B newly added, word standardized: on-chip oscillator, development tool
Overview
1
2 - 3
4 - 5
6
•Description partially deleted
•1.2 Performance Outline modified
•Figure 1.1 and 1.2 Block Diagrams updated
•1.4 Product List updated
7
•Figure 1.3 Product Numbering System updated
•Tables 1.7 to 1.10 Product Codes updated
8
12, 14 •Tables 1.11 and 1.12 Pin Characteristics newly added
15 - 16 •Tables 1.13 Pin Description newly added
SFRs
20
22
23
•Table 4.1 SFR Information(1) Note about WDC register is deleted
•Table 4.3 SFR Information(3) Value after reset for ROCR register modified
•Table 4.4 SFR Information(4) Note 2 added to IFSR2A register
Reset
28
29
•Figure 5.1.1.2. Reset Sequence Vcc line and ROC line are modified
•Figure 5.5.1. Voltage Detection Circuit Block WDC register’s block is deleted
Processor Mode
35
36
37
•Figure 6.1 PM1 Register Note 2 partially added
•Figure 6.2 PM2 Register newly added
•Figure 6.3 Bus Block Diagram and Table 6.1 Accessible Area and Bus Cycle
newly added
Clock Generation Circuit
41
43
•Figure 7.4 ROCR Register modified
•Figure 7.6 PM2 Register Notes 2, 5, 6 modified
45 - 46 •Figure 7.1.1 and 7.2.1 Examples of Main Clock Connection Circuit updated
47
•7.4 PLL Clock Description modified for M16C/26B
•Table 7.4.1 Example for Setting PLL Clock Frequencies Note 1 modified
•7.6.1 Normal Operation Mode Description modified
50
51
54
55
56
59
•Table 7.6.1.1 Setting Clock Related Bit and Modes modified
•Figure 7.6.1 State Transition to Stop Mode and Wait Mode modified
•Figure 7.6.1.1. State Transtion in Normal Mode modified
•Table 7.6.1 Allowed Transition and Setting modified, Notes 1 and 2 modified
•Figure 7.8.3.1 Procedure to Switch Clock Source From On-chip Oscillator
to Main Clock upadated
Protection
60
76
•Description partially modified
Interrupt
______
•9.6 INT Interrupt Description partially added
C-1
REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual
Rev.
Date
Description
Summary
Page
77
______
•9.7 NMI Interrupt Description partially added
•Table 9.9.1 Value of the PC that is saved to the stack area when an address
match interrupt request is accepted modified, note 1 added
Watchdog Timer
78
-
•Section of Cold Start/Warm Start deleted
80
•Description partially added
•Figure 10.1 Watchdog Timer Block Diagram partially modified
•Figure 10.2 WDC Register and WDTS Register notes deleted, WDC5 bit de-
leted
81
•10.1 Count source protective mode description partially added
Timer
108
•Description about A/D trigger mode modified
•Figure 12.2.1 Timber B Block Diagram A/D trigger mode added
•12.2.4 A/D Trigger Mode Description modified
•Figure 12.3.4 IDB0 Register, IDB1 Register, DTT Register, and ICTB2 Regis-
ter modified
115
121
123
131
•Figure 12.3.6 TB2SC Register modified, note 4 added
•Figure 12.3.2.2 TPRC Register bit map modified
Serial I/O
133
136
•Figure 13.1.1 Block Diagram of UARTi (i = 0 to 2) PLL clock added
•Figure 13.1.4 U0TB to U2TB Registers, U0RB to U2RB Registers, U0BRG to
U2BRG Registers modified, note 3 for UiBRG added
•Figure 13.1.6 U0C0 to U2C0 Registers Note 2 modified, note 7 added
•Figure 13.1.7 PACR Register note 1 modified
•Table 13.1.1.1 Clock Synchronous Serial I/O Mode Specification note 2 modi-
fied
138
139
142
145
•Figure 13.1.1.1 Typical Transmit/Receive Timings in Clock Synchronous
Serial I/O Mode partially modified
150
154
158
168
175
177
•Table 13.1.2.1 UART Mode Specifications Note 1 modified
•Figure 13.1.2.2 Receive Operation Figure modified
2
•Table 13.1.3.1 I C bus Mode Specifications note 2 modified
•Table 13.1.4.1 Special Mode 2 Specifications note 2 modified
•Table 13.1.6.1 SIM Mode Specifications note 1 modified
•Figure 13.1.6.1 Transmit and Receive Timing in SIM Mode timing modified
A/D Converter
180
183
205
212
•Table 14.1 A/D Converter Performance note 2 partially added
•Table 14.2 A/D Conversion Frequency Select note 1 partially added
•Table 14.1.8.1 Delayed Trigger Mode 1 Specifications note 1 modified
•Figure 14.5.1 Analog Input Pin and External Sensor Equivalent Circuit note
C-2
REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual
Rev.
Date
Description
Summary
Page
1 added
CRC Calculation Circuit
213
214
•15.1 CRC Snoop Description partially modified
•Figure 15.2 CRCSAR Register note 1 added
Programable I/O Ports
216
217
•16.3 Pull-up Control Register 0 to Pull-up Control Register 2 description
modified
•16.6 Digital Debounce function equation modified
218 - 221 •Figure 16.1 I/O Ports (1) to 16.4 I/O Ports (4) modified
227
•Figure 16.6.1 NDDR and P17DDR Registers equation modified, note 2 modi-
fied
Flash Memory Version
231
232
235
236
237
239
•17.1.1 Boot Mode newly added
•17.2 Memory Map partially deleted
•17.3.1 ROM Code Protect Function description modified
•Figure 17.3.1.1 ROMCP Address modified
•Table 17.4.1 EW0 Mode and EW1 Mode note 2 mark deleted
•17.5.1 Flash Memory Control Register 0 Description about low power con-
sumption mode or on-chip oscillator low-power consumption mode is entered
partially modified
240
241
•17.5.2 Flash Memory Control Register 1 Description about FMR17 bit modified
•Figure 17.5.1 FMR0 Register note 3 modified, FMR1 Register: bit map modi-
fied
242
243
•Figure 17.5.2 FMR4 Register note 2 modified
•Figure 17.5.1.2 Setting and Resetting of EW1 Mode note for single-chip mode
deleted, note 3 for FMR11 bit added
Electrical Characteristics
261
262
•Table 18.1 Absolute Maximum Ratings Rated value modifed, note 1 added
•Table 18.2 Recommended Operating Conditions value partially added, fig-
ures in note 4 partially added
263
264
•Table 18.3 A/D Conversion Characteristics note 4 modified
•Table 18.4 and Table 18.5 Flash Memory Version Electrical Characteristic
note 4 partially added, note 6 and note 7 modified
•Table 18.6 Voltage Detection Circuit Electrical Characteristics conditions modi-
fied
265
•Figure for td(P-R) and td(ROC) modified
267
274
•Table 18.9 eElectrical Characteristics (2) flash memory’s value for M16C/26B
added, note 5 deleted
•Table 18.24 Electrical Characteristics (2) note 5 deleted
C-3
REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual
Rev.
Date
Description
Summary
Page
283
•Tables 18.41 and 18.42 Flash Memory Version Electrical Characteristics note
4 , note 10, note 11 modified
284
286
293
•Figure for td(P-R) and td(ROC) modified
•Table 18.45 Electrical Characteristics note 4 deleted
•Table 18.60 Electrical Characteristics (2) note 4 deleted
Usage Notes
299
306
312
315
319
321
•19.1.3 Register Setting newly added
•19.5.6 Rewrite the Interrupt Control Register Example 1 modified
•19.7.3 Three-phase Motor Control Timer Function newly added
•19.9 A/D Converter Description of section 6 modified
•19.12.1 Internal ROM Area description partially added
•19.13.9 Interrupts description of EW1 Mode modified, note on watchdog timer
interrupts deleted
•19.13.10 How to Access description modified
Appendix 2. functional Difference
326
•Appendix 2.1 Differences between M16C/26A and M16C/26T description on
cold start/warm start detection function deleted
C-4
RENESAS 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER
HARDWARE MANUAL
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Publication Date: Rev.1.00 Mar.15, 2005
Rev.2.00 Feb.15, 2007
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
相关型号：
©2020 ICPDF网 联系我们和版权申明