M30260M8T-XXXGP-U3 [RENESAS]
16-BIT, MROM, 20MHz, MICROCONTROLLER, PQFP48, 7 X 7 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-48;
| 型号： | M30260M8T-XXXGP-U3 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 16-BIT, MROM, 20MHz, MICROCONTROLLER, PQFP48, 7 X 7 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-48 时钟 外围集成电路 |
| 文件： | 总26页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M16C/26A Group (M16C/26A, M16C/26T)
REJ03B0071-0040Z
Rev.0.40
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2004.07.30
1. Overview
The M16C/26A group (M16C/26A, M16C/26T) of single-chip microcomputers is built using the high-perfor-
mance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 42-pin and 48-
pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featur-
ing a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing
instructions at high speed. In addition, this microcomputer contains a multiplier and a DMAC which com-
bined with fast instruction processing capability, makes it suitable for control of various OA, communication,
and industrial equipment which requires high-speed arithmetic/logic operations.
There is a Normal-ver. for M16C/26A and T-ver. and v-ver. for M16C/26T.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment,
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
Rev.0.40 2004.07.30 page 1 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
1.2 Performance Outline
Table 1.1 lists performance outline of M16C/26A group (M16C/26A, M16C/26T) 48-pin device.
Table 1.2 lists performance outline of M16C/26A 42-pin device.
Table 1.1. Performance outline of M16C/26A group (48-pin device)(M16C/26A, M16C/26T)
Item
Performance
CPU
Number of basic instructions 91 instructions
Shortest instruction
50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V)
100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V)
50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105°C)
62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125°C)
Single chip mode
(M16C/26A, M16C/26T(T-ver.))
(M16C/26A)
(M16C/26T(V-ver.))
(M16C/26T(V-ver.))
Operation mode
Address space
Memory capacity
Port
1M byte
ROM/RAM : See the product list
Input/Output : 39 lines
Peripheral
function
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
Serial I/O
2 channels (UART, clock synchronous serial I/O)
2
1
2
1 channel (UART, clock synchronous, I C bus , or IEBus )
10 bit A/D Converter : 1 circuit, 12 channels
2 channels
A/D converter
DMAC
CRC calcuration circuit
Watchdog timer
Interrupt
2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable
15 bits x 1 channel (with prescaler)
20 internal and 8 external sources, 4 software sources, 7 levels
4 circuits
Clock generation circuit
Main clock(*), Sub-clock(*)
On-chip oscillator, PLL frequency synthesizer
(*)These circuit contain a built-in feedback resister.
Main clock oscillation stop, re-oscillation detection function
Oscillation stop detection
Low voltage detection circuit Available (M16C/26A) Not available (M16C/26T)
Electrical
Characteristics
Power supply voltage
VCC=3.0V to 5.5V (f(BCLK)=20MHZ)
VCC=2.7V to 5.5V (f(BCLK)=10MHZ)
VCC=3.0V to 5.5V
(M16C/26A)
(M16C/26T(T-ver.))
(M16C/26T(V-ver.))
VCC=4.2V to 5.5V
Power consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz on RAM)
1.8 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz, in wait mode)
0.7 µA (Vcc=3V, when stop mode)
Flash memory Program/erase voltage
2.7V to 5.5V (M16C/26A)
3.0V to 5.5V (M16C/26T(T-ver.))
4.2V to 5.5V (M16C/26T(V-ver.))
3
Number of program/erase
Operating ambient temperature
100 times ( Block A ,Block B : 10,000 times (option ) )
4
-20 to 85°C / -40 to 85°C
-40 to 85°C
(M16C/26A)
(M16C/26T(T-ver.))
(M16C/26T(V-ver.))
-40 to 105°C / -40 to 125°C
48-pin plastic molded QFP
Package
Notes:
2
1. I C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. If you desire this option, please so specify.
4. See Table 1.6 for the operating ambient temperature.
Rev.0.40 2004.07.30 page 2 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
Table 1.2. Performance outline of M16C/26A group (42-pin device) (M16C/26A)
Item
Performance
CPU
Number of basic instructions 91 instructions
Shortest instruction
50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V)
100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V)
Single chip mode
Operation mode
Address space
Memory capacity
Port
1M byte
ROM/RAM : See the product list
Input/Output : 33 lines
Peripheral
function
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
Serial I/O
1 channel (UART, clock synchronous serial I/O)
2
1
2
1 channel (UART, clock synchronous, I C bus , or IEBus )
10 bit A/D Converter : 1 circuit, 10 channels
2 channels
A/D converter
DMAC
CRC calcuration circuit
Watchdog timer
Interrupt
2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable
15 bits x 1 channel (with prescaler)
18 internal and 8 external sources, 4 software sources, 7 levels
4 circuits
Clock generation circuit
Main clock(*), Sub-clock(*)
On-chip oscillator, PLL frequency synthesizer
(*)These circuit contain a built-in feedback resister.
Main clock oscillation stop, re-oscillation detection function
Oscillation stop detection
Low voltage detection circuit Available
Electrical
Characteristics
Power supply voltage
Power consumption
VCC=3.0V to 5.5V (f(BCLK)=20MHZ)
VCC=2.7V to 5.5V (f(BCLK)=10MHZ)
16mA (Vcc=5V, f(BCLK)=20MHz)
25 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz on RAM)
1.8 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz, in wait mode)
0.7 µA (Vcc=3V, when stop mode)
Flash memory Program/erase voltage
Number of program/erase
Operating ambient temperature
Package
2.7V to 5.5V
3
100 times(all area) or 1,000 times(program ara)/10,000 times(data area)
-20 to 85°C / -40 to 85°C
42-pin plastic molded SSOP
3
Notes:
2
1. I C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. See Table 1.6 for the number of program/erase and the operating ambient temperature.
Rev.0.40 2004.07.30 page 3 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
1.3 Block Diagram
Figure 1.1 is a block diagram of the M16C/26A group, 48-pin device.
8
8
8
4
8
3
I/O
Port P6
Port P7
Port P8
Port P9
Port P10
Port P1
Ports
Internal Peripheral Functions
Timer
Serial Ports
System Clock Generator
IN-XOUT
CIN-XCOUT
PLL frequency synthesizer
On-chip Oscillator
A/D converter
(10bits x 12 channels)
Timer A0 (16 bits)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
U(S)ART/SIO (channel 0)
X
X
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I2C/IEbus
(channel 2)
DMAC (2 channels)
Watchdog Timer
(15bits)
CRC calculation circuit
(CCITT, CRC-16)
3-phase PWM
M16C/60 series 16-bit CPU Core
Memory
Program Counter
PC
Flash ROM
Registers
R0H
R0H
R1H
R0L
R0L
R1L
Stack Pointers
ISP
Flash ROM
(Data Flash)
R2
R3
A0
A1
FB
USP
Vector Table
INTB
RAM
Flag Register
FLG
Multiplier
SB
Figure 1.1. M16C/26A Group, 48-pin Block Diagram
Rev.0.40 2004.07.30 page 4 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
Figure 1.2 is a block diagram of the M16C/26A group, 42-pin device.
4
8
8
2
8
3
I/O
Port P6
Port P7
Port P8
Port P9
Port P10
Port P1
Ports
Internal Peripheral Functions
Timer
Serial Ports
System Clock Generator
IN-XOUT
CIN-XCOUT
PLL frequency synthesizer
On-chip Oscillator
A/D converter
(10bits x 10 channels)
Timer A0 (16 bits)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
U(S)ART/SIO (channel 0)
U(S)ART/SIO/I2C/IEbus
(channel 2)
X
X
DMAC (2 channels)
Watchdog Timer
(15bits)
CRC calculation circuit
(CCITT, CRC-16)
3-phase PWM
M16C/60 series 16-bit CPU Core
Memory
Program Counter
PC
Flash ROM
Registers
R0H
R0H
R1H
R0L
R0L
R1L
Stack Pointers
ISP
Flash ROM
(Data Flash)
R2
R3
A0
A1
FB
USP
Vector Table
INTB
RAM
Flag Register
FLG
Multiplier
SB
Figure 1.2. M16C/26A Group, 42-pin Block Diagram
Rev.0.40 2004.07.30 page 5 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
1.4 Product List
Tables 1.3 to 1.5 list the M16C/28 group products and Figure 1.3 shows the type numbers, memory sizes
and packages.
Table 1.3. Product List (1) -M16C/26A
Type No. ROM capacity
As of Jun 2004
RAM capacity
1K byte
1K byte
2K byte
2K byte
1K byte
1K byte
2K byte
2K byte
1K byte
1K byte
2K byte
2K byte
1K byte
1K byte
2K byte
2K byte
Package type
48P6Q
Remarks
M30260M3A-XXXGP (D) 24K byte
M30260M4A-XXXGP (D) 32K byte
M30260M6A-XXXGP (D) 48K byte
M30260M8A-XXXGP (D) 64K byte
M30263M3A-XXXFP (D) 24K byte
M30263M4A-XXXFP (D) 32K byte
M30263M6A-XXXFP (D) 48K byte
M30263M8A-XXXFP (D) 64K byte
Mask ROM Version
42P2R
M30260F3AGP
M30260F4AGP
M30260F6AGP
M30260F8AGP
M30263F3AFP
M30263F4AFP
M30263F6AFP
M30263F8AFP
(P) : under planning
(D) 24K + 4K byte
(D) 32K + 4K byte
(D) 48K + 4K byte
(D) 64K + 4K byte
(D) 24K + 4K byte
(D) 32K + 4K byte
(D) 48K + 4K byte
(D) 64K + 4K byte
48P6Q
42P2R
Flash ROM Version
(D) : under development
Table 1.4. Product List (2) -M16C/26T T-ver.
Type No. ROM capacity
As of Jun 2004
Remarks
RAM capacity
1K byte
1K byte
2K byte
2K byte
1K byte
1K byte
2K byte
2K byte
Package type
48P6Q
M30260M3T-XXXGP (P) 24K byte
M30260M4T-XXXGP (P) 32K byte
M30260M6T-XXXGP (P) 48K byte
M30260M8T-XXXGP (P) 64K byte
Mask ROM Version
M30260F3TGP
M30260F4TGP
M30260F6TGP
M30260F8TGP
(P) : under planning
(D) 24K + 4K byte
(D) 32K + 4K byte
(D) 48K + 4K byte
(D) 64K + 4K byte
Flash ROM Version
48P6Q
(D) : under development
NOTES: Specification of M16C/26T partly varies from the one of M16C/26A
Table 1.5. Product List (3) -M16C/26T V-ver.
As of Jun 2004
Type No.
ROM capacity
RAM capacity
1K byte
1K byte
2K byte
2K byte
1K byte
1K byte
2K byte
2K byte
Package type
Remarks
M30260M3V-XXXGP (P) 24K byte
M30260M4V-XXXGP (P) 32K byte
M30260M6V-XXXGP (P) 48K byte
M30260M8V-XXXGP (P) 64K byte
M30260F3VGP
M30260F4VGP
M30260F6VGP
M30260F8VGP
Mask ROM Version
48P6Q
(D) 24K + 4K byte
(D) 32K + 4K byte
(D) 48K + 4K byte
(D) 64K + 4K byte
Flash ROM Version
48P6Q
(P) : under planning
(D) : under development
NOTES: Specification of M16C/26T partly varies from the one of M16C/26A
Rev.0.40 2004.07.30 page 6 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
Type No.
M 3 0 2 6 0 M 8 A - XXX G P - D3
Product code:
See Table 1.6 Product code
Package type:
GP : Package 48P6Q (M16C/26A, M16C/26T)
FP : Package 42P2R (M16C/26A)
ROM number:
ROM number is omitted in flash memory version
Version:
A
T
V
: M16C/26A
: M16C/26T T-ver.
: M16C/26T V-ver.
ROM / RAM capacity:
3: (24K+4K) bytes (Note 1) / 1K bytes
4: (32K+4K) bytes (Note 1) / 1K bytes
6: (48K+4K) bytes (Note 1) / 2K bytes
8: (64K+4K) bytes (Note 1) / 2K bytes
Note 1: Only flash memory version exists in "+4K bytes"
Memory type:
M: Mask ROM version
F: Flash memory version
Shows pin count,
(The value itself has no specific meaning)
M16C/26A Group
M16C Family
Figure 1.3. Type No., Memory Size, and Package
Table 1.6. Product code (Flash memory version, M16C/26A)
Internal ROM
(Data area)
Internal ROM
(Program area)
Product
Code
Operating Ambient
Package
Temperature
Program and
Erase Endurance
Temperature
Range
Program and
Erase Endurance
Temperature
Range
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
D3
D5
D7
D9
U3
U5
U7
U9
0°C to 60°C
100
10,000
100
100
Lead-included
Lead-free
-40°C to 85°C
-20°C to 85°C
1,000
0°C to 60°C
0°C to 60°C
100
-40°C to 85°C
-20°C to 85°C
1,000
10,000
(MASK ROM version, M16C/26A)
Product
Code
Operating Ambient
Package
Temperature
-40°C to 85°C
D3
D5
U3
U5
Lead-included
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
Lead-free
Rev.0.40 2004.07.30 page 7 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
(1) Flash memory version, 48P6Q, M16C/26A
Product Name : indicates M30260F8AGP
Chip Version and Product Code:
0260F8A
A D3
A
Indicates chip version
XXXXX
The first edition is shown to be blank and continues
with A and B.
D3
Indicates Product code (see Table 1.6 Product Code)
Date Code (5 digits)
indicates manufacturing management code
(2) Flash memory version, 42P2R, M16C/26A
Product Name : indicates M30263F8AFP
Chip Version and Product Code:
M30263F8AFP
A D3
A
Indicates chip version
The first edition is shown to be blank and continues
with A and B.
XXXXXXX
D3
Indicates Product code (see Table 1.6 Product Code)
Date Code (7 digits)
indicates manufacturing management code
(3) MASK ROM version, 48P6Q, M16C/26A
Product Name : indicates M30260M8AGP
0260M8A
001A D3
XXXXX
ROM number, Chip Version and Product Code:
001 Indicates ROM Number
A
Indicates chip version
The first edition is shown to be blank and continues
with A and B.
D3
Indicates Product code (see Table 1.6 Product Code)
Date Code (5 digits)
indicates manufacturing management code
(4) MASK ROM version, 42P2R, M16C/26A
Product Name and ROM number
M30263M8A and FP are indicated of Produnct name
001 is indicated of ROM number
M30263M8A-001FP
A D3
Chip Version and Product Code:
A
Indicates chip version
XXXXXXX
The first edition is shown to be blank and continues
with A and B.
D3
Indicates Product code (see Table 1.6 Product Code)
Date Code (7 digits)
indicates manufacturing management code
Figure 1.4. Marking Diagram of Flash Memory versionfor M16C/26A (Top View)
Rev.0.40 2004.07.30 page 8 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
1.5 Pin Configuration
Figures 1.5 and 1.6 show the pin configurations (top view).
PIN CONFIGURATION (top view)(Note)
P10
P10
P10
7
/AN
/AN
/AN
7
/KI
/KI
/KI
3
37
38
24
23
P7
P7
1
/RxD
/CLK
2
/TA0IN/SCL/CLK
/TA1OUT/V/RxD
/RTS /TA1IN/V/TxD
/TA2OUT/W
1
2
2
1
6
5
6
5
2
1
39
40
41
22
21
20
P7
P7
3
4
/CTS
2
2
1
P10
4
/AN
4
/KI0
P10
P10
P10
3/AN
2/AN
1
/AN
3
2
1
P7
5
/TA2IN/W
/TA3OUT
/TA3IN
42
43
44
19
18
17
P76
P77
AVss
P8
0
1
/TA4OUT/U
/TA4IN/U
P10
0/AN
0
45
46
47
16
15
14
P8
V
REF
P8
P8
2
/INT
0
AVcc
3
/INT
1
P93
/AN24
P84/INT2/ZP
48
13
Note. Set PACR2 to PACR0 bit in the PACR register
to "100 " before you input and output it after
2
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the pins are disabled.
Package: 48P6Q
Figure 1.5. Pin Configuration (Top View) of M16C/26A Group, 48-pin Package
Rev.0.40 2004.07.30 page 9 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
PIN CONFIGURATION (top view)(Note)
P101/AN1
AVSS
P100/AN0
VREF
1
2
42
41
P102/AN2
P103/AN3
3
4
40
39
AVCC
P104/AN4/KI0
P105/AN5/KI1
P91/TB1IN/AN31
P90/TB0IN/AN30/CLKout
CNVSS
5
6
7
38
37
36
P106/AN6/KI2
P107/AN7/KI3
P15/INT3/ADTRG/IDV
P87/XCIN
8
9
10
35
34
33
P16/INT4/IDW
P17/INT5/IDU
P86/XCOUT
RESET
P64/CTS1/RTS1/CTS0/CLKS1
P65/CLK1
XOUT
VSS
11
12
13
32
31
30
XIN
P66/RxD1
P67/TxD1
VCC
14
15
16
29
28
27
P70/TxD2/SDA/TA0OUT/CTS1/RTS1/CTS0/CLKS1
P71/RxD2/SCL/TA0IN/CLK1
P72/CLK2/TA1OUT/V/RxD1
P85/NMI/SD
P84/INT2/ZP
P83/INT1
17
18
19
26
25
24
P82/INT0
P73/CTS2/RTS2/TA1IN/V/TxD1
P74/TA2OUT/W
P75/TA2IN/W
P81/TA4IN/U
P80/TA4OUT/U
P77/TA3IN
20
21
23
22
P76/TA3OUT
Note. Set PACR2 to PACR0 bit in the PACR register
to "001 " before you input and output it after
2
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the pins are disabled.
Package: 42P2R
Figure 1.6. Pin Configuration (Top View) of M16C/26A Group, 42-pin Package
Rev.0.40 2004.07.30 page 10 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
1.6 Pin Description
Table 1.6 and 1.7 describes the available pins.
Table 1.6. Pin Description(1)
Pin name Signal name I/O type
Function
VCC,VSS
Power supply
input
Apply 0V to the Vss pin, and the following voltage to the Vcc pin.
2.7 to 5.5V (M16C/26A)
3.0 to 5.5V (M16C/26T T-ver.)
4.2 to 5.5V (M16C/26T V-ver.)
CNVSS
CNVSS
Input
Input
Input
Output
Connect this pin to Vss.
____________
RESET
XIN
Reset input
Clock input
Clock output
"L" on this input resets the microcomputer.
These pins are provided for the main clock generating circuit input/output.
Connect a ceramic resonator or crystal between the XIN and the XOUT pins.
To use an externally derived clock, input it to the XIN pin and leave the XOUT
pin open. If XIN is not used (for external oscillator or external clock)
connect XIN pin to VCC and leave XOUT pin open.
This pin is a power supply input for the A/D converter. Connect this
pin to VCC.
XOUT
AVCC
Analog power
supply input
Analog power
supply input
Reference
AVSS
This pin is a power supply input for the A/D converter. Connect this
pin to VSS.
VREF
Input
This pin is a reference voltage input for the A/D converter.
Voltage input
I/O port P1
P15~P17
Input/
This is an 3-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output individually.
When used for input, a pull-up resister option can be selected for the
output
entire group of three pins. Additional software selectable secondary
______
functions are: 1) P15 to P17 can be configured as external INT interrupt
pins; 2) P15 to P17 can be configured as position-data-retain function
input pins,and; 3) P15 can input a trigger for the A/D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output individually.
When used for input, a pull-up resister option can be selected for the
entire group of four pins. Pins in this port also function as UART0 and
UART1 I/O, as selected by software.P60 to P63 are not available in the 42
pin version.
P60~P67
P70~P77
I/O port P6
Input/
output
I/O port P7
Input/
This is an 8-bit I/O port equivalent to P6. P7 can also function as I/O for
timer A0 to A3, as selected by software. Additional programming options
are: P70 to P73 can assume UART1 I/O or UART2 I/O capabilities, and
P72 to P75 can function as output pins for the three-phase motor control
timer.
output
Rev.0.40 2004.07.30 page 11 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
1. Overview
Table 1.7. Pin Description(2)
Pin name Signal name
I/O port P8
I/O type
Input/
Function
P80~P87
This is an 8-bit I/O port equivalent to P6. Additional software-selectable
secondary functions are: 1) P80 and P81 can act as either I/O for Timer
output
A4, or as output pins for the three-phase motor control timer; 2) P82 to
______
P84 can be configured as external INT interrupt pins. P84 can be used for
_______ _____
Timer A Zphase function; 3) P85 can be used as NMI/SD. P85 can not be
used as I/O port while the three-phase motor control is enabled. Apply a
stable "H" to P85 after setting the direction register for P85 to "0" when
the three-phase motor control is enabled, and; 4) P86 and P87 can serve
as I/O pins for the sub-clock generation circuit. In this latter case, a quartz
oscillator must be connented between P86 (XCOUT pin) and P87 (XCIN pin).
This is an 4-bit I/O port equivalent to P6. Additional software-selectable
secondary functions are: 1) P90 to P92 can act as Timer B0~B2 input
pins, and; 2) P90 to P93 can act as A/D converter input pins.
P90~P93
I/O port P9
Input/
output
P90 outputs a no-divide, divide-by-8 or divide-by-32 clock of XIN or a
clock of the same frequency as XCIN as selected by program. P92 to P93
are not available in the 42 pin version.
P100~P107 I/O port P10
Input/
This is an 8-bit I/O port equivalent to P6. This port can also function as
A/D converter input pins, as selected by software. Furthermore, P104 to
P107 can also function as input pins for the key input interrupt function.
output
Rev.0.40 2004.07.30 page 12 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
2. Central Processing Unit(CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
b15
b8b7
b0
R2
R3
R0H(R0's high bits) R0L(R0's low bits)
R1H(R1's high bits)R1L(R1's low bits)
Data registers (Note)
R2
R3
A0
A1
FB
Address registers (Note)
Frame base registers (Note)
b19
b15
b0
INTBH
INTBL
Interrupt table register
Program counter
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
b0
PC
b15
USP
User stack pointer
Interrupt stack pointer
Static base register
ISP
SB
b15
b0
b0
FLG
Flag register
b15
b8 b7
IPL
U
I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 2.1. Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-
bit data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.0.40 2004.07.30 page 13 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit(CPU)
M16C/26A Group (M16C/26A, M16C/26T)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”
.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
Rev.0.40 2004.07.30 page 14 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
3. Memory
M16C/26A Group (M16C/26A, M16C/26T)
3. Memory
Figure 3.1 is a memory map. The linear address space of 1M bytes extends from address 0000016 to
FFFFF16. The internal ROM is allocated in a lower address directiom beginning with address FFFFF16 . For
example, a 64-Kbyte internal ROM is allocated to the address from F000016 to FFFFF16.
The fixed interrupt vector table is allocated to the address from FFFDC16 to FFFFF16. Therefore store the
start address of each interrupt routine here. For details, refer to the "Interrupt".
These devices also contain two blocks of Flash ROM as Data Flash memory to store data. These two
blocks of 2K bytes are located from 0F00016 to 0FFFF16 on all versions.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 1-Kbyte internal RAM is allocated to the address from 0040016 to 007FF16. In addition to storing data, the
internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR is allocated to the address from 0000016 to 003FF16. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used
by the JMPS or JSRS instruction. For details, refer to the "M16C/60 and M16C/20 Series Software
Manual".
0000016
SFR
0040016
Internal RAM
XXXXX16
Reserved area
FFE0016
FFFDC16
0F00016
0FFFF16
Special page
vector table
Internal ROM
(Data area) (Note 1)
Internal RAM
Intrnal ROM
Size
Address XXXXX16 Size
Address YYYYY16
FA00016
Undefined Instruction
Overflow
1K byte
2K byte
007FF16
00BFF16
24K byte
32K byte
48K byte
64K byte
F800016
BRK instruction
Address match
Single step
F400016
Reserved area
F000016
Watchdog timer
DBC
YYYYY16
FFFFF16
Internal ROM
(Program area)(Note 2)
Note 1: Shown here is a Block A (2K bytes) and Block B (2K bytes).
(in the flash memory version)
Note 1: When using the masked ROM version, write nothing to
internal ROM area.
NMI
Reset
FFFFF16
Figure 3.1. Memory Map
Rev.0.40 2004.07.30 page 15 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
4. Special Function Register (SFR) MAP
4. Special Function Register (SFR) Map
Address
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
Register
Symbol
After reset
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
PM0
PM1
CM0
CM1
0016
00001000
01001000
00100000
2
2
2
Address match interrupt enable register
Protect register
AIER
PBCR
XXXXXX00
XX000000
2
2
Oscillation stop detection register
(Note 2)
CM2
0X000010
2
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
??16
00??????
0016
0016
2(Note3)
X016
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1
Voltage detection register 2
(Note 4,5)
(Note 4,5)
VCR1
VCR2
00001000
0016
2
PLL control register 0
PLC0
0001X0102
Processor mode register 2
PM2
XXX00000
2
001F16
002016
Power supply down detection interrupt register
DMA0 source pointer
(Note 5)
D4INT
SAR0
0016
??16
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
??16
X?16
DMA0 destination pointer
DMA0 transfer counter
DMA0 control register
DMA1 source pointer
DMA1 destination pointer
DMA1 transfer counter
DMA1 control register
DAR0
??16
??16
X?16
TCR0
??16
??16
DM0CON
SAR1
00000?002
??16
??16
X?16
DAR1
??16
??16
X?16
TCR1
??16
??16
DM1CON
00000?002
Note 1: The blank areas are reserved and cannot be used by users.
Note 2: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset..
Note 3: The WDC5 bit is "0" (cold start) immediately after power-on. It can only be set to "1" in a program.
It is set to "0" when the input voltage at the VCC pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is
set to "1" (2V detection circuit enable).
Note 4: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 5: This register can not use for M16C/26T
X : Nothing is mapped to this bit
? : Undefined
Rev.0.40 2004.07.30 page 16 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
4. Special Function Register (SFR) MAP
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Register
Symbol
INT3IC
After reset
INT3 interrupt control register
XX00?0002
INT5 interrupt control register
INT4 interrupt control register
INT5IC
INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XX00?0002
XX00?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XX00?0002
XX00?0002
XX00?0002
UART2 Bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
Key input interrupt control register
A/D conversion interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
TimerA0 interrupt control register
TimerA1 interrupt control register
TimerA2 interrupt control register
TimerA3 interrupt control register
TimerA4 interrupt control register
TimerB0 interrupt control register
TimerB1 interrupt control register
TimerB2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Note 1: The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
Rev.0.40 2004.07.30 page 17 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
4. Special Function Register (SFR) MAP
Address
008016
008116
008216
008316
008416
008516
008616
Register
Symbol
After reset
~
~
~
~
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
Flash memory control register 4
(Note 2)
(Note 2)
(Note 2)
FMR4
FMR1
FMR0
01000000
000???0?
0116
2
2
Flash memory control register 1
Flash memory control register 0
~
~
~
~
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
Three phase protect control register
TPRC
0016
On-chip oscillator control register
Pin assignment control register
Peripheral clock select register
ROCR
PACR
PCLKR
00000101
0016
00000011
2
2
~
~
~
~
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
NMI digital debounce register
NDDR
P17DDR
FF16
FF16
Port1
7
digital debounce register
Note 1: The blank areas are reserved and cannot be used by users.
Note 2: This register is included in the flash memory version.
X :Nothing is mapped to this bit
? : Undefined
Rev.0.40 2004.07.30 page 18 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
4. Special Function Register (SFR) MAP
Address
Register
Symbol
After reset
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
TA11
TA21
TA41
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
??16
X?16
XXXX0000
Three phase PWM control register 0
Three phase PWM control register 1
Three phase output buffer register 0
Three phase output buffer register 1
Dead time timer
INVC0
INVC1
IDB0
IDB1
DTT
Timer B2 Interrupt occurrence frequency set counter
Position-data-retain function control register
ICTB2
PDRF
2
Port function control register
PFCR
001111112
Interrupt request cause select register 2
Interrupt request cause select register
IFSR2A
IFSR
XXXXXXX0
0016
2
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
0016
000X0X0X
X0000000
X0000000
0016
??16
????????
XXXXXXX?
2
2
2
U2BRG
U2TB
UART2 transmit buffer register
2
2
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
U2C0
U2C1
U2RB
00001000
00000010
????????
2
2
2
?????XX?
2
Note 1 :The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
Rev.0.40 2004.07.30 page 19 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
4. Special Function Register (SFR) MAP
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Register
Symbol
After reset
Count start flag
TABSR
CPSRF
ONSF
TRGSR
UDF
0016
0XXXXXXX2
0016
0016
0016
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-dowm flag
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Timer B2 special mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
0016
0016
0016
0016
0016
00??00002
00?X00002
00?X00002
X00000002
UART0 transmit/receive mode register
UART0 bit rate register
UART0 transmit buffer register
U0MR
U0BRG
U0TB
0016
??16
????????2
XXXXXXX?2
000010002
000000102
????????2
?????XX?2
0016
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
U0C0
U0C1
U0RB
UART1 transmit/receive mode register
UART1 bit rate register
UART1 transmit buffer register
U1MR
U1BRG
U1TB
??16
????????2
XXXXXXX?2
000010002
000000102
????????2
?????XX?2
X00000002
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
U1C0
U1C1
U1RB
UART transmit/receive control register 2
UCON
CRC snoop address register
CRC mode register
CRCSAR
CRCMR
DM0SL
DM1SL
CRCD
??16
00XXXX??2
0XXXXXX02
DMA0 request cause select register
DMA1 request cause select register
CRC data register
0016
0016
??16
??16
??16
CRC input register
CRCIN
Note 1 :The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
Rev.0.40 2004.07.30 page 20 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
4. Special Function Register (SFR) MAP
Address
03C016 A/D register 0
Register
Symbol
AD0
After reset
????????
2
03C116
XXXXXX??
????????2
XXXXXX??
2
2
2
2
2
2
2
2
03C216 A/D register 1
03C316
AD1
AD2
AD3
AD4
AD5
AD6
AD7
03C416 A/D register 2
03C516
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
2
03C616 A/D register 3
03C716
2
03C816 A/D register 4
03C916
2
03CA16 A/D register 5
03CB16
2
03CC16 A/D register 6
03CD16
2
03CE16 A/D register 7
03CF16
2
03D016
03D116
03D216 A/D trigger control register
03D316 A/D status register 0
03D416 A/D control register 2
ADTRGCON
ADSTAT0
ADCON2
XXXX00002
00000X00
0016
2
03D516
03D616 A/D control register 0
03D716 A/D control register 1
ADCON0
ADCON1
00000???
0016
2
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
Port P1 register
P1
??16
0016
03E216
03E316
Port P1 direction register
PD1
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
Port P6 register
P6
??16
03ED16
Port P7 register
P7
??16
03EE16
Port P6 direction register
Port P7 direction register
Port P8 register
PD6
PD7
P8
0016
0016
??16
03EF16
03F016
03F116
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
P9
???X????
0016
000X0000
??16
2
2
03F216
PD8
PD9
P10
03F316
03F416
03F516
03F616
Port P10 direction register
PD10
0016
03F716
03F816
03F916
03FA16
03FB16
03FC16
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
Port control register
PUR0
PUR1
PUR2
PCR
0016
0016
0016
0016
03FD16
03FE16
03FF16
Note 1 :The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
Rev.0.40 2004.07.30 page 21 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
5. Package
5. Package
Recommended
48P6Q-A
Plastic 48pin 7✕7mm body LQFP
EIAJ Package Code
LQFP48-P-77-0.50
JEDEC Code
–
Weight(g)
–
Lead Material
Cu Alloy
MD
HD
D
48
37
I2
Recommended Mount Pad
1
36
25
F
Dimension in Millimeters
Symbol
Min
–
0
Nom
–
Max
1.7
0.2
–
0.27
0.175
7.1
7.1
–
9.2
9.2
0.65
–
0.75
–
A
A
1
0.1
1.4
0.22
0.125
7.0
7.0
0.5
9.0
9.0
0.5
1.0
0.6
0.25
–
A
2
–
12
b
0.17
0.105
6.9
6.9
–
8.8
8.8
0.35
–
0.45
–
–
–
0°
c
D
E
e
H
H
13
24
A
D
L
1
E
e
L
L1
Lp
A3
x
0.08
0.1
8°
y
y
–
–
L
b
Lp
x
M
Detail F
b2
–
1.0
–
0.225
–
7.4
7.4
–
–
–
–
I
2
M
M
D
E
–
Recommended
42P2R-E
Plastic 42pin 450mil SSOP
EIAJ Package Code
SSOP42-P-450-0.80
JEDEC Code
Weight(g)
Lead Material
Cu Alloy+42 Alloy
e
b2
–
–
42
22
Recommended Mount Pad
Dimension in Millimeters
F
Symbol
Min
–
0.05
–
0.25
0.13
17.3
8.2
–
11.63
0.3
–
–
–
–
0°
–
–
1.27
Nom
–
–
Max
2.4
–
A
A
A
1
21
1
2
G
D
2.0
0.3
0.15
17.5
8.4
0.8
11.93
0.5
1.765
0.75
–
–
A
b
0.4
0.2
17.7
8.6
–
12.23
0.7
–
c
D
E
e
H
L
A2
A1
e
b
E
y
L1
z
–
Z
1
0.9
0.15
10°
–
–
–
y
–
–
c
z
b2
0.5
11.43
–
Z
1
e1
Detail G
Detail F
I
2
Rev.0.40 2004.07.30 page 22 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
6. Functional differences
6. Functional differences
6.1 Functional differences between M16C/26A and M16C/26T
Item
M16C/26A
M16C/26T
Main Clock During Oscillating
Not oscillating
and After Reset
(Initial value of CM05 bit is set to “0”
during and after reset)
Available
(Initial value of CM05 bit is set to “1”
during and after reset)
Not available
Voltage Detection
Circuit
(Power supply detection register 1,
Power supply detection register 2,
Power supply down detection interrupt register)
48P6Q, 42P2R
(Reserved register)
(Function of 001916
,
001A16, 001F16
)
Package
48P6Q
Note. Since the emulator between the M16C/26A and M16C/29 group are same, all functions of M16C/29
are built in the emulator. When evaluating M16C/26A group, do not access to the SFR which is not
built in M16C/26A group.
Refer to Hardware Manual about detail and electrical characteristics.
Rev.0.40 2004.07.30 page 23 of 24
REJ03B0071-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26A Group (M16C/26A, M16C/26T)
6. Functional differences
6.2 Functional differences between M16C/26A and M16C/26
Item
M16C/26A
M16C/26
Clock Generation
Circuit
4 circuits (Main clock oscillation circuit, 3 circuits (Main clock oscillation circuit,
Sub clock oscillation circuit,
On-chip oscillator,
Sub clock oscillation circuit,
On-chip oscillator)
PLL frequency synthesizer)
System Clock
On-chip oscillator
Main clock
Source After Reset (Initial value "1" of CM21 bit)
(Initial value of the CM21
(Initial value "0" of CM21 bit)
bit in the CM2 register)
Internal RAM Retention Available
limit Detection Circuit (VC25 bit)
(The b5 bit in the VCR2 register)
Not available
(Reserved bit)
On-chip Oscillator Clock Selectable (8MHz/1MHz/500KHz)
PACR2 to PACR0 in Necessary to set after reset
Fixed (1MHz)
No PACR register
the PACR Register
48pin:"1002", 42pin:"0012"
IFSR20 Bit in the
IFSR2A Register
External Interrupt
Necessary to set to "1" after reset
No IFSR2A register
8 causes (INT2 added)
7 causes
IVCC
________ _____
13 pin (48-pin version) INT2/ZP
Function
P70, P71
N-ch open drain output and CMOS
output are selectable by S/W
12 channels
N-ch open drain output
8 channels
A/D Input Pin
(48-pin version)
A/D Operation Mode 8 modes (single, repeat, single sweep, 5 modes (single, repeat, single sweep,
repeat sweep mode 0, repeat sweep
mode 1, simultaneous sampling,
delayed trigger mode 0, delayed
trigger mode 1)
repeat sweep mode 0, repeat sweep
mode 1)
1 shunt current measurement function
is available
Timer B Operation 5 modes (timer, event counter, pulse
4 modes (timer, event counter, pulse
periods measurement, pulse width
measurment)
Mode
periods measurement, pulse width
measurment, A/D trigger)
1 shunt current measurement function
is available
CRC Calculation
Available (compatible to CRC-CCITT
and CRC-16 methods)
Not available
Three-Phase Motor •Waveform output/Switching port output •Waveform output/Switching port output
Control
by software is enabled
by software is disabled
•Position-data-retain function
•No position-data-retain function
_______ _____
Digital Debounce
Function
This function is in the NMI/SD pin and
INT5 pin
Not available
________
3 pin (48-pin version) P90/CLKOUT/TB0IN/AN30
P90/TB0IN
Function
(CLKOUT: f1, f8, f32, and fC output)
UART1 Compatible Switching to P64 to P67 or P70 to P73
P64 to P67
Pin
is enabled
Flash Memory
Protect Function
Protection to blocks 0, 1 by FMR02 bit
Protection to the blocks 0 to 3 by
FMR16 bit
Protection to blocks 0,1 by FMR02 bit
Package
48P6Q, 42P2R
48P6Q
Note. Since the emulator between the M16C/26A and M16C/29 group are same, all functions of M16C/29
are built in the emulator. When evaluating M16C/26A group, do not access to the SFR which is not
built in M16C/26A group.
Refer to Hardware Manual about detail and electrical characteristics.
Rev.0.40 2004.07.30 page 24 of 24
REJ03B0071-0040Z
REVISION HISTORY
M16C/26A Group (M16C/26A, M16C/26T) Short Sheet
Rev.
Date
Description
Summary
Page
0.20 Dec/ 01/ 03
0.30 Jun/15/04
First edition
All
1
Descriptions about M16C/26A and M16C/26AT are added.
The section “1. Overview” is partly revised.
2,3
4,5
6
Table 1.1 and 1.2 are partly revised. Note 2 in Table 1.1 and 1.2 are revised.
Figure 1.1 and 1.2 integrate descriptions.
The section “1.4 Product List” is partly revised.
Table 1.6 “Porduct code” is added.
7
8
Figure 1.4 “Marking Diagram of Flash Memory versionfor M16C/26A (Top View) ” is added.
Figure 1.5 to 1.6 are partly revised.
9,10
11
12
15
16
Table 1.6 is revised.
Table 1.7 is partly revised.
The Chapter ”3. Memory” is partly revised. Note 2 in Figure 3.1 is added.
The Chapter “4. Special Function Register” is partly revised.
23, 24 The Chaplte “6. Functional differences” is added.
0.40 Sep/30/04
All
M16C/26AT is changed to M16C/26T.
A-1
M16C/26A Group
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
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