M30281F6THP [RENESAS]
16-BIT, FLASH, 20MHz, MICROCONTROLLER, PQFP64, 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80;
| 型号： | M30281F6THP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 16-BIT, FLASH, 20MHz, MICROCONTROLLER, PQFP64, 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件： | 总415页 (文件大小：2531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REJ09B0047-0060Z
M16C/28 Group
Hardware Manual
16
M16C FAMILY / M16C/Tiny SERIES
Before using this material, please visit the our website to confirm that this is the most
current document available.
Rev. 0.60
Revision date: February. 01. 2004
www.renesas.com
Keep safety first in your circuit designs!
•
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ucts better and more reliable, but there is always the possibility that trouble may occur with
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Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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not convey any license under any intellectual property rights, or any other rights, belonging
to Renesas Technology Corporation or a third party.
• Renesas Technology Corporation assumes no responsibility for any damage, or infringe-
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programs, algorithms, or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, pro-
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due to product improvements or other reasons. It is therefore recommended that custom-
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he products contained therein.
How to Use This Manual
This hardware manual provides detailed information on features in the M16C/28 Group
microcomputer.
Users are expected to have basic knowledge of electric circuits, logical circuits and micro-
computer.
Each register diagram contains bit functions with the following symbols and descriptions.
*1
XXX register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
XXX
Address
XXX
After reset
0016
0
RW
RW
Bit symbol
XXX0
Bit name
XXX bit
Function
*2
b1 b0
1 0: XXX
0 1: XXX
1 0: Avoid this setting
1 1: XXX
XXX1
(b2)
RW
Nothing is assigned.
When write, should set to "0". When read, its content is indeterminate.
Reserved bit
XXX bit
Should set to "0"
RW
RW
WO
RW
RO
(b3)
XXX4
XXX5
*3
Function varies depending on each
operation mode
XXX6
XXX7
0: XXX
1: XXX
XXX bit
*1
Blank:Set to "0" or "1" according to your intended use
0:
1:
X:
Set to "0"
Set to "1"
Nothing is assigned
*2
*3
RW: Read and write
RO: Read only
WO: Write only
–:
Nothing is assigned
Terms to use here are explained as follows.
• Nothing is assigned
Nothing is assigned to the bit concerned. When write, set to "0" for new function
in future plan.
• Reserved bit
Reserved bit. Set the specified value.
• Avoid this setting
The operation at having selected is not guaranteed.
• Function varies depending on each operation mode
Bit function varies depending on peripheral function mode.
Refer to register diagrams in each mode.
M16C Family Documents
Document
Contents
Hardware overview
Short Sheet
Data Sheet
Hardware overview and electrical characteristics
Hardware specifications (pin assignments,
memory maps, specifications of peripheral func-
tions, electrical characteristics, timing charts)
Hardware Manual
Detailed description about instructions and mi-
crocomputer performance by each instruction
Software Manual
Application Note
• Application examples of peripheral functions
• Sample programs
• Introductory description about basic functions in
M16C family
• Programming method with the assembly and C
languages
Table of Contents
Quick Reference to Pages Classified by Address ......... B-1
1. Overview ............................................................................ 1
1.1 Applications............................................................................................... 1
1.2 Performance Outline................................................................................. 2
1.3 Block Diagram............................................................................................4
1.4 Product List ............................................................................................... 6
1.5 Pin Configuration .......................................................................................8
1.6 Pin Description.........................................................................................10
2. Central Processing Unit (CPU)....................................... 12
2.1 Data Registers (R0, R1, R2 and R3)........................................................12
2.2 Address Registers (A0 and A1)...............................................................12
2.3 Frame Base Register (FB) .......................................................................13
2.4 Interrupt Table Register (INTB) ...............................................................13
2.5 Program Counter (PC) .............................................................................13
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)................13
2.7 Static Base Register (SB)........................................................................13
2.8 Flag Register (FLG)..................................................................................13
2.8.1 Carry Flag (C Flag) ................................................................................................. 13
2.8.2 Debug Flag (D Flag) ............................................................................................... 13
2.8.3 Zero Flag (Z Flag) .................................................................................................. 13
2.8.4 Sign Flag (S Flag) ................................................................................................... 13
2.8.5 Register Bank Select Flag (B Flag)....................................................................... 13
2.8.6 Overflow Flag (O Flag) ........................................................................................... 13
2.8.7 Interrupt Enable Flag (I Flag) ................................................................................ 13
2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................ 13
2.8.9 Processor Interrupt Priority Level (IPL) ............................................................... 13
2.8.10 Reserved Area ...................................................................................................... 13
A-1
3. Memory ............................................................................ 14
4. Special Function Register (SFR) Map ........................... 15
5. Reset ................................................................................ 22
5.1 Hardware Reset........................................................................................22
5.1.1 Hardware Reset 1 ................................................................................................... 22
5.1.2 Hardware Reset 2 ................................................................................................... 22
5.2 Software Reset .........................................................................................23
5.3 Watchdog Timer Reset ............................................................................23
5.4 Oscillation Stop Detection Reset ...........................................................23
5.5 Voltage Detection Circuit.........................................................................25
5.5.1 Voltage Detection Interrupt ................................................................................... 28
5.5.1.1 Precautions .................................................................................................................. 28
5.5.1.1.1. Limitations on Stop Mode ...................................................................................................28
5.5.1.1.2. Limitations on WAIT Instruction.........................................................................................29
6. Processor Mode .............................................................. 30
7. Clock Generation Circuit ................................................ 31
7.1 Main Clock ................................................................................................38
7.2 Sub Clock .................................................................................................39
7.3 Ring Oscillator Clock...............................................................................40
7.4 PLL Clock..................................................................................................40
7.5 CPU Clock and Peripheral Function Clock............................................42
7.5.1 CPU Clock ...............................................................................................................42
7.5.2 Peripheral Function Clock
(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32) ...................... 42
7.6 Power Control ..........................................................................................43
7.6.1 Normal Operation Mode ........................................................................................ 43
7.6.1.1 High-speed Mode ........................................................................................................ 43
7.6.1.2 PLL Operation Mode ................................................................................................... 43
7.6.1.3 Medium-speed Mode .................................................................................................. 43
7.6.1.4 Low-speed Mode......................................................................................................... 43
7.6.1.5 Low Power Dissipation Mode .................................................................................... 43
A-2
7.6.1.6 Ring Oscillator Mode ................................................................................................... 44
7.6.1.7 Ring Oscillator Low Power Dissipation Mode........................................................... 44
7.6.2 Wait Mode ............................................................................................................... 44
7.6.2.1 Peripheral Function Clock Stop Function ................................................................ 44
7.6.2.2 Entering Wait Mode..................................................................................................... 44
7.6.2.3 Pin Status During Wait Mode ..................................................................................... 44
7.6.2.4 Exiting Wait Mode ....................................................................................................... 45
7.6.3 Stop Mode .............................................................................................................. 46
7.6.3.1 Entering Stop Mode ..................................................................................................... 46
7.6.3.2 Pin Status during Stop Mode...................................................................................... 46
7.6.3.3 Exiting Stop Mode........................................................................................................ 46
7.7 System Clock Protective Function.........................................................50
7.8 Oscillation Stop and Re-oscillation Detect Function ...........................50
7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) .................... 51
7.8.2 Operation When CM27 bit = 1
(Oscillation Stop and Re-oscillation Detect Interrupt)................. 51
7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function ..................... 52
8. Protection......................................................................... 53
9. Interrupts.......................................................................... 54
9.1 Type of Interrupts.....................................................................................54
9.1.1 Software Interrupts ................................................................................................ 55
9.1.1.1 Undefined Instruction Interrupt .................................................................................. 55
9.1.1.2 Overflow Interrupt........................................................................................................ 55
9.1.1.3 BRK Interrupt ............................................................................................................... 55
9.1.1.4 INT Instruction Interrupt.............................................................................................. 55
9.1.2 Hardware Interrupts ............................................................................................... 56
9.1.2.1 Special Interrupts......................................................................................................... 56
_______
9.1.2.1.1 NMI Interrupt .........................................................................................................................56
________
9.1.2.1.2 DBC Interrupt ........................................................................................................................56
9.1.2.1.3 Watchdog Timer Interrupt ....................................................................................................56
9.1.2.1.4 Oscillation Stop and Re-oscillation Detection Interrupt ................................................... 56
9.1.2.1.5 Voltage Down Detection Interrupt .......................................................................................56
9.1.2.1.6 Single-step Interrupt.............................................................................................................56
9.1.2.1.7 Address Match Interrupt ......................................................................................................56
9.1.2.2 Peripheral Function Interrupts ................................................................................... 56
9.2 Interrupts and Interrupt Vector ...............................................................57
A-3
9.2.1 Fixed Vector Tables................................................................................................ 57
9.2.2 Relocatable Vector Tables ..................................................................................... 58
9.3 Interrupt Control ......................................................................................59
9.3.1 I Flag ........................................................................................................................62
9.3.2 IR Bit ........................................................................................................................62
9.3.3 ILVL2 to ILVL0 Bits and IPL ................................................................................... 62
9.4 Interrupt Sequence ..................................................................................63
9.4.1 Interrupt Response Time ....................................................................................... 64
9.4.2 Variation of IPL when Interrupt Request is Accepted ......................................... 64
9.4.3 Saving Registers .................................................................................................... 65
9.4.4 Returning from an Interrupt Routine .................................................................... 67
9.5 Interrupt Priority.......................................................................................67
9.5.1 Interrupt Priority Resolution Circuit ..................................................................... 67
9.6 _I_N__T__ Interrupt .............................................................................................69
______
9.7 NMI Interrupt.............................................................................................70
9.8 Key Input Interrupt ...................................................................................70
9.9 Address Match Interrupt..........................................................................71
10. Watchdog Timer ............................................................ 73
11. DMAC.............................................................................. 75
11.1 Transfer Cycles .....................................................................................80
11.1.1 Effect of Source and Destination Addresses.................................................... 80
11.1.2 Effect of Software Wait ....................................................................................... 80
11.2. DMA Transfer Cycles ............................................................................82
11.3 DMA Enable ............................................................................................83
11.4 DMA Request ..........................................................................................83
11.5 Channel Priority and DMA Transfer Timing ........................................84
12. Timers............................................................................. 85
12.1 Timer A...................................................................................................87
12.1.1. Timer Mode ..........................................................................................................90
12.1.2. Event Counter Mode ........................................................................................... 91
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing.............................. 95
A-4
12.1.3. One-shot Timer Mode ......................................................................................... 96
12.1.4. Pulse Width Modulation (PWM) Mode ............................................................... 98
12.2 Timer B.................................................................................................101
12.2.1 Timer Mode ........................................................................................................ 103
12.2.2 Event Counter Mode .......................................................................................... 104
12.2.3 Pulse Period and Pulse Width Measurement Mode ....................................... 105
12.2.4 A-D Trigger Mode .............................................................................................. 107
12.3 Three-phase Motor Control Timer Function ..................................... 109
12.3.1 Position-data-retain Function ........................................................................... 120
12.3.1.1 Operation of the Position-data-retain Function .................................................... 120
12.3.1.2 Position-data-retain Function Control Register.................................................... 121
12.3.1.2.1 W-phase Position Data Retain Bit (PDRW) .....................................................................121
12.3.1.2.2 V-phase Position Data Retain Bit (PDRV) .......................................................................121
12.3.1.2.3 U-phase Position Data Retain Bit (PDRU) ......................................................................121
12.3.1.2.4 Retain-trigger Polarity Select Bit (PDRT) .......................................................................121
13. Timer S (Input Capture/Output Compare) ................. 122
13.1 Base Timer............................................................................................134
13.1.1 Base Timer Reset Register................................................................................ 138
13.2 Interrupt Operation ..............................................................................139
13.3 DMA Support ........................................................................................139
13.4 Time Measurement Function ............................................................. 140
13.5 Waveform Generation Function..........................................................144
13.5.1 Single-Phase Waveform Output Mode ............................................................. 145
13.5.2 Phase-Delayed Waveform Output Mode .......................................................... 147
13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode ............................ 149
13.6 I/O Port Function Select ......................................................................151
13.6.1 INPC17 Alternate Input Pin Selection............................................................... 152
13.6.2 Digital Debounce Function for Pin P17/_I_N__T__5__/INPC17 ..................................... 152
14. Serial I/O....................................................................... 153
14.1. UARTi (i=0 to 2) ...................................................................................153
14.1.1. Clock Synchronous serial I/O Mode ................................................................ 163
14.1.1.1 CLK Polarity Select Function.................................................................................. 167
14.1.1.2 LSB First/MSB First Select Function .................................................................... 167
14.1.1.3 Continuous receive mode ....................................................................................... 168
A-5
14.1.1.4 Serial data logic switch function (UART2)............................................................. 168
14.1.1.5 Transfer clock output from multiple pins function (UART1)................................ 168
_______ _______
14.1.1.6 CTS/RTS separate function (UART0) ..................................................................... 169
14.1.2. Clock Asynchronous Serial I/O (UART) Mode ................................................ 170
14.1.2.1. LSB First/MSB First Select Function .................................................................... 174
14.1.2.2. Serial Data Logic Switching Function (UART2) ................................................... 175
14.1.2.3. TxD and RxD I/O Polarity Inverse Function (UART2) .......................................... 175
_______ _______
14.1.2.4. CTS/RTS Separate Function (UART0) ................................................................... 176
14.1.3 Special Mode 1 (I2C Bus mode)(UART2) ......................................................... 177
14.1.3.1 Detection of Start and Stop Condition ................................................................... 183
14.1.3.2 Output of Start and Stop Condition ....................................................................... 183
14.1.3.3 Arbitration................................................................................................................. 184
14.1.3.4 Transfer Clock .......................................................................................................... 185
14.1.3.5 SDA Output............................................................................................................... 185
14.1.3.6 SDA Input.................................................................................................................. 185
14.1.3.7 ACK and NACK ....................................................................................................... 186
14.1.3.8 Initialization of Transmission/Reception .............................................................. 186
14.1.4 Special Mode 2 (UART2) .................................................................................... 187
14.1.4.1 Clock Phase Setting Function ............................................................................... 190
14.1.4.1.1 Master (Internal Clock) .....................................................................................................190
14.1.4.1.2 Slave (External Clock) ......................................................................................................190
14.1.5 Special Mode 3 (IE Bus mode)(UART2)........................................................... 192
14.1.6 Special Mode 4 (SIM Mode) (UART2)............................................................... 194
14.1.6.1 Parity Error Signal Output....................................................................................... 197
14.1.6.2 Format...................................................................................................................... 198
14.2 SI/O3 and SI/O4 ...................................................................................199
14.2.1 SI/Oi Operation Timing .............................................................................................. 202
14.2.2 CLK Polarity Selection .............................................................................................. 202
14.2.3 Functions for Setting an SOUTi Initial Value ........................................................... 203
15. A-D Converter .............................................................. 204
15.1 Operation Modes................................................................................. 210
15.1.1 One-Shot Mode................................................................................................... 210
15.1.2 Repeat mode....................................................................................................... 212
15.1.3 Single Sweep Mode........................................................................................... 214
15.1.4 Repeat Sweep Mode 0 ....................................................................................... 216
15.1.5 Repeat Sweep Mode 1 ....................................................................................... 218
15.1.6 Simultaneous Sample Sweep Mode ................................................................. 220
15.1.7 Delayed Trigger Mode 0 ..................................................................................... 223
15.1.8 Delayed Trigger Mode 1 ..................................................................................... 229
A-6
15.2 Resolution Select Function.................................................................235
15.3 Sample and Hold................................................................................. 235
15.4 Current Consumption Reducing Function ........................................235
15.5 Analog Input Pin and External Sensor Equivalent Circuit Example235
15.6 Precautions of Using A-D Converter..................................................236
16. Multi-master I2C bus Interface.................................... 237
16.1 I2C0 Data Shift Register (S00 register) ...............................................246
16.2 I2C0 Address Register (S0D0 register) ...............................................246
16.3 I2C0 Clock Control Register (S20 register) .......................................247
16.3.1 Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) .................................. 247
16.3.2 Bit 5: SCL mode specification bit (FAST MODE)........................................... 247
16.3.3 Bit 6: ACK bit (ACK BIT) ................................................................................... 247
16.3.4 Bit 7: ACK clock bit (ACK)................................................................................ 247
16.4 I2C0 Control Register 0 (S1D0 register) ............................................249
16.4.1 Bits 0 to 2: Bit counter (BC0–BC2) .................................................................. 249
16.4.2 Bit 3: I2C interface enable bit (ES0)................................................................. 249
16.4.3 Bit 4: Data format select bit (ALS) ................................................................... 249
16.4.4 Bit 6: I2C bus interface reset bit (IHR) ............................................................. 249
16.4.5 Bit 7: I2C bus interface pin input level select bit (TISS) ................................. 250
16.5 I2C0 Status Register (S10 register) ................................................... 251
16.5.1 Bit 0: Last receive bit (LRB) ............................................................................. 251
16.5.2 Bit 1: General call detection flag (ADR0) ........................................................ 251
16.5.3 Bit 2: Slave address comparison flag (AAS) .................................................. 251
16.5.4 Bit 3: Arbitration lost detection flag (AL)(Note 1)........................................... 251
16.5.5 Bit 4: I2C bus interface interrupt request bit (PIN) ......................................... 252
16.5.6 Bit 5: Bus busy flag (BB) .................................................................................. 252
16.5.7 Bit 6: Communication mode select bit (transfer direction select bit: TRX) . 253
16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST) ....... 253
16.6 I2C0 control register 1 (S3D0 register) .............................................254
16.6.1 Bit 0 : Interrupt enable bit by STOP condition (SIM ) ..................................... 254
16.6.2 Bit 1: Interrupt enable bit at the completion of data receive (WIT)............... 254
16.6.3 Bits 2,3 : Port function select bits PED, PEC ................................................. 255
16.6.4 Bits 4,5 : SDA/SCL logic output value monitor bits SDAM/SCLM ................ 256
A-7
16.6.5 Bits 6,7 : I2C system clock select bits ICK0, ICK1 .......................................... 256
16.6.6 The address receive in STOP mode/WAIT mode............................................ 256
16.7 I2C0 control register 2 (S3D0 register) ..............................................257
16.7.1 Bit0: Time out detection function enable bit (TOE)........................................ 258
16.7.2 Bit1: Time out detection flag (TOF ) ................................................................ 258
16.7.3 Bit2: time out detection period select bit (TOSEL) ........................................ 258
16.7.4 Bits 3,4,5: I2C system clock select bits (ICK2-4) ............................................ 258
16.7.5 Bit7: STOP condition detection interrupt request bit (SCPIN) ...................... 258
16.8 I2C0 START/STOP condition control registers (S2D0 register).......259
16.8.1 Bit0-Bit4: START/STOP condition setting bits (SSC0-SSC4) ........................ 259
16.8.2 Bit5: SCL/SDA interrupt pin polarity select bit (SIP)...................................... 259
16.8.3 Bit6 : SCL/SDA interrupt pin select bit (SIS)................................................... 259
16.8.4 Bit7: START/STOP condition generation select bit (STSPSEL).................... 259
16.9 START Condition Generation Method...............................................260
16.10 START condition duplicate protect function ...................................261
16.11 STOP Condition Generation Method ............................................... 261
16.12 START/STOP Condition Detect Operation.......................................263
16.13 Address Data Communication........................................................ 264
16.13.1 Example of Master Transmit .......................................................................... 264
16.13.2 Example of Slave Receive .............................................................................. 265
16.14 Usage precautions ............................................................................ 267
17. Programmable I/O Ports ............................................. 270
17.1 Port Pi Direction Register (PDi Register, i = 0 to 3, 6 to 10) .............270
17.2 Port Pi Register (Pi Register, i = 0 to 3, 6 to 10) ................................270
17.3 Pull-up Control Register 0 to Pull-up Control Register 2
(PUR0 to PUR2 Registers)........270
17.4 Port Control Register...........................................................................270
17.5 Pin Assignment Control register (PACR).......................................... 271
17.6 Digital Debounce function ..................................................................271
18. Electrical Characteristics ........................................... 284
18.1. Normal version ....................................................................................284
A-8
18.2. T version ..............................................................................................305
19. Flash Memory Version ................................................ 326
19.1 Flash Memory Performance ................................................................326
19.2 Memory Map .........................................................................................328
19.3 Functions To Prevent Flash Memory from Rewriting ...................... 331
19.3.1 ROM Code Protect Function ............................................................................. 331
19.3.2 ID Code Check Function.................................................................................... 331
19.4 CPU Rewrite Mode ...............................................................................333
19.4.1 EW0 Mode ...........................................................................................................334
19.4.2 EW1 Mode ...........................................................................................................334
19.5 Register Description............................................................................335
19.5.1 Flash memory control register 0 (FMR0): ........................................................ 335
•FMR 00 Bit ............................................................................................................................. 335
•FMR01 Bit .............................................................................................................................. 335
•FMR02 Bit .............................................................................................................................. 335
•FMSTP Bit.............................................................................................................................. 335
•FMR06 Bit .............................................................................................................................. 335
•FMR07 Bit .............................................................................................................................. 335
19.5.2 Flash memory control register 1 (FMR1): ........................................................ 336
•FMR11 Bit .............................................................................................................................. 336
•FMR16 Bit .............................................................................................................................. 336
•FMR17 Bit .............................................................................................................................. 336
19.5.3 Flash memory control register 4 (FMR4): ........................................................ 336
•FMR40 Bit .............................................................................................................................. 336
•FMR41 Bit .............................................................................................................................. 336
•FMR46 Bit .............................................................................................................................. 336
19.6 Precautions in CPU Rewrite Mode .................................................... 341
19.6.1 Operation Speed ................................................................................................ 341
19.6.2 Prohibited Instructions ...................................................................................... 341
19.6.3 Interrupts ............................................................................................................ 341
19.6.4 How to Access.................................................................................................... 341
19.6.5 Writing in the User ROM Space ........................................................................ 341
19.6.5.1 EW0 Mode................................................................................................................. 341
19.6.5.2 EW1 Mode................................................................................................................. 341
19.6.6 DMA Transfer ......................................................................................................342
19.6.7 Writing Command and Data .............................................................................. 342
A-9
19.6.8 Wait Mode ........................................................................................................... 342
19.6.9 Stop Mode ........................................................................................................... 342
19.6.10 Low Power Consumption Mode
and Ring Oscillator-Low Power Consumption Mode .................... 342
19.7 Software Commands ...........................................................................343
19.7.1 Read Array Command (FF16) ............................................................................. 343
19.7.2 Read Status Register Command (7016)............................................................. 343
19.7.3 Clear Status Register Command (5016) ............................................................ 344
19.7.4 Program Command (4016) .................................................................................. 344
19.7.5 Block Erase......................................................................................................... 345
19.8 Status Register.....................................................................................347
19.8.1 Sequence Status (SR7 and FMR00 Bits ) ......................................................... 347
19.8.2 Erase Status (SR5 and FMR07 Bits) ................................................................. 347
19.8.3 Program Status (SR4 and FMR06 Bits) ............................................................ 347
19.8.4 Full Status Check ............................................................................................... 348
19.9 Standard Serial I/O Mode ....................................................................350
19.9.1 ID Code Check Function.................................................................................... 350
19.9.2 Example of Circuit Application in Standard Serial I/O Mode ......................... 354
19.10 Parallel I/O Mode ................................................................................356
19.10.1 ROM Code Protect Function ........................................................................... 356
20. Package........................................................................ 357
Register Index ................................................................... 358
A-10
Quick Reference to Pages Classified by Address
Register
Symbol
Page
Register
Symbol
Page
Address
Address
000016
000116
000216
000316
000416
004016
004116
004216
004316
004416
004516
004616
30
30
Processor mode register 0
PM0
INT3 interrupt control register
IC/OC 0 interrupt control register
INT3IC
ICOC0IC
60
60
000516 Processor mode register 1
PM1
CM0
CM1
System clock control register 0
System clock control register 1
000616
000716
000816
33
34
IC/OC 1 interrupt control register
ICOC1IC
60
60
60
I2C-BUS interface interrupt control register IICIC
IC/OC base timer interrupt control register BTIC
004716
004816
004916
000916 Address match interrupt enable register AIER
000A16
SCLSDA interrupt control register
SCLDAIC
72
53
Protect register
PRCR
SI/O4 interrupt control register
INT5 interrupt control register
S4IC,
INT5IC
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
35
SI/O3 interrupt control register,
INT4 interrupt control register
UART2 Bus collision detection interrupt control register BCNIC
DMA0 interrupt control register
DMA1 interrupt control register
Key input interrupt control register
S3IC,
INT4IC
Oscillation stop detection register
CM2
60
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
Watchdog timer start register
Watchdog timer control register
WDTS
WDC
74
25, 74
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
DM0IC
DM1IC
KUPIC
Address match interrupt register 0
RMAD0
72
A-D conversion interrupt control register ADIC
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
Address match interrupt register 1
RMAD1
72
005316 UART1 transmit interrupt control register
005416 UART1 receive interrupt control register
005516
Voltage detection register 1
Voltage detection register 2
VCR1
VCR2
26
26
Timer A0 interrupt control register
Timer A1 interrupt control register
TA0IC
TA1IC
005616
005716
005816
005916
005A16
005B16
005C16
005D16
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
PLL control register 0
PLC0
PM2
37
Processor mode register 2
Voltage down detection interrupt register D4INT
36
26
002116 DMA0 source pointer
SAR0
79
60
60
60
002216
002316
002416
005E16 INT1 interrupt control register
005F16
INT2 interrupt control register
INT2IC
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
DMA0 destination pointer
DAR0
79
79
78
002516
002616
002716
002816
DMA0 transfer counter
TCR0
002916
002A16
002B16
002C16
DMA0 control register
DM0CON
002D16
002E16
002F16
003016
003116
79
DMA1 source pointer
SAR1
003216
003316
003416
003516
DMA1 destination pointer
DAR1
TCR1
79
79
003616
003716
003816
DMA1 transfer counter
003916
003A16
003B16
003C16
DMA1 control register
DM1CON
78
003D16
003E16
003F16
Note: The blank areas are reserved and cannot be accessed by users.
B-1
Quick Reference to Pages Classified by Address
Register
Symbol
Page
Register
TM/WG register 0
Symbol
Page
Address
Address
008016
008116
008216
008316
008416
008516
008616
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
G1TM0/G1PO0 129,130
G1TM1/G1PO1 129,130
G1TM2/G1PO2 129,130
G1TM3/G1PO3 129,130
G1TM4/G1PO4 129,130
G1TM5/G1PO5 129,130
G1TM6/G1PO6 129,130
G1TM7/G1PO7 129,130
TM/WG register 1
TM/WG register 2
TM/WG register 3
TM/WG register 4
TM/WG register 5
TM/WG register 6
TM/WG register 7
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
(Note 2)
Flash memory control register 4
FMR4
352
351
351
Flash memory control register 1 (Note 2) FMR1
Flash memory control register 0 FMR0
WG control register 0
WG control register 1
WG control register 2
WG control register 3
WG control register 4
WG control register 5
WG control register 6
WG control register 7
TM control register 0
TM control register 1
TM control register 2
TM control register 3
TM control register 4
TM control register 5
TM control register 6
TM control register 7
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
129
129
129
129
129
129
129
129
128
128
128
128
128
128
128
128
(Note 2)
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
Base timer register
G1BT
124
Base timer control register 0
Base timer control register 1
TM prescale register 6
TM prescale register 7
Function enable register
Function select register
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
124
126
128
128
131
131
G1FS
Base timer reset register
Divider register
G1BTRR
G1DV
127
125
34
281
36
Ring oscillator control register
Pin assignment control register
Peripheral clock select register
ROCR
PACR
PCLKR
I2C0 data shift register
S00
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
Interrupt request register
033116 Interrupt enable register 0
033216 Interrupt enable register 1
G1IR
G1IE0
G1IE1
132
241
133
133
I2C0 address register
I2C0 control register 0
I2C0 clock control register
S0D0
S1D0
S20
240
242
241
246
244
245
243
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
I2C0 start/stop condition control register S2D0
I2C0 control register 1
I2C0 control register 2
I2C0 status register
S3D0
S4D0
S10
02FE16
02FF16
282
282
033E16
NMI digital debounce register
NDDR
P17DDR
033F16
P17
digital debounce register
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: This register is included in the flash memory version.
B-2
Quick Reference to Pages Classified by Address
Register
Symbol
TABSR
Page
Register
Symbol
Page
Address
038016
Address
88, 102,
116
Count start flag
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
89, 102
038116 Clock prescaler reset flag
038216 One-shot start flag
038316 Trigger select register
038416 Up-down flag
038516
CPSRF
ONSF
TRGSR
UDF
114
Timer A1-1 register
TA11
89
89, 116
114
114
Timer A2-1 register
Timer A4-1 register
TA21
TA41
88
038616
88
Timer A0 register
TA0
111
112
113
113
113
113
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
INVC0
INVC1
IDB0
IDB1
DTT
038716
038816
88, 114
Timer A1 register
TA1
TA2
038916
038A16
88, 114
88
Timer A2 register
038B16
Timer B2 interrupt occurrence frequency set counter ICTB2
038C16
Timer A3 register
TA3
TA4
TB0
TB1
TB2
Position-data-retain function contol register
PDRF
038D16
121
038E16
88, 114
Timer A4 register
038F16
039016
102
102
Timer B0 register
039116
039216
Timer B1 register
039316
039416
102, 116
Timer B2 register
039516
039616 Timer A0 mode register
039716 Timer A1 mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
87
87, 117
87, 117
87
Timer A2 mode register
039816
039916
039A16
039B16
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
87, 117
101
101
101, 117
108, 115
039C16 Timer B1 mode register
039D16 Timer B2 mode register
61
61, 69
200
Interrupt request cause select register 2
Interrupt request cause select register IFSR
SI/O3 transmit/receive register
IFSR2A
039E16
Timer B2 special mode register
S3TRR
039F16
03A016
158
157
UART0 transmit/receive mode register
U0MR
U0BRG
200
200
200
03A116
UART0 bit rate generator
SI/O3 control register
SI/O3 bit rate generator
S3C
S3BRG
S4TRR
03A216
157
UART0 transmit buffer register
U0TB
03A316
036416 SI/O4 transmit/receive register
03A416
036516
159
160
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
U0C0
U0C1
200
200
03A516
036616 SI/O4 control register
036716
S4C
S4BRG
SI/O4 bit rate generator
03A616
157
UART0 receive buffer register
U0RB
03A716
036816
03A816
158
157
036916
UART1 transmit/receive mode register
U1MR
U1BRG
03A916
036A16
UART1 bit rate generator
03AA16
036B16
157
UART1 transmit buffer register
U1TB
03AB16
036C16
03AC16
159
160
036D16
UART1 transmit/receive control register 0
U1C0
U1C1
03AD16
036E16
UART1 transmit/receive control register 1
03AE16
036F16
157
159
UART1 receive buffer register
U1RB
03AF16
037016
03B016
037116
UART transmit/receive control register 2
UCON
03B116
037216
03B216
037316
162
162
161
161
158
157
03B316
037416 UART2 special mode register 4
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
UART2 special mode register 3
03B416
037516
UART2 special mode register 2
03B516
037616
UART2 special mode register
03B616
037716
UART2 transmit/receive mode register
03B716
037816
UART2 bit rate generator
U2BRG
DM0SL
DM1SL
03B816 DMA0 request cause select register
03B916
77
78
037916
037A16
157
UART2 transmit buffer register
U2TB
03BA16
037B16
DMA1 request cause select register
159
160
UART2 transmit/receive control register 0
U2C0
U2C1
03BB16
03BC16
03BD16
03BE16
03BF16
037C16
UART2 transmit/receive control register 1
037D16
037E16
157
UART2 receive buffer register
U2RB
037F16
Note : The blank areas are reserved and cannot be accessed by users.
B-3
Quick Reference to Pages Classified by Address
Register
Symbol
AD0
Page
208
Address
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
AD1
AD2
AD3
AD4
208
208
208
208
A-D register 5
A-D register 6
AD5
AD6
208
208
208
A-D register 7
AD7
A-D trigger control register
A-D convert status register 0
A-D control register 2
ADTRGCON
ADSTAT0
ADCON2
207
208
206
206
206
A-D control register 0
A-D control register 1
ADCON0
ADCON1
279
279
278
278
279
279
278
278
03E016 Port P0 register
P0
03E116
03E216
03E316
03E416
Port P1 register
P1
Port P0 direction register
Port P1 direction register
Port P2 register
PD0
PD1
P2
P3
PD2
PD3
03E516 Port P3 register
Port P2 direction register
Port P3 direction register
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
279
279
278
278
279
279
278
278
279
Port P6 register
Port P7 register
Port P6 direction register
P6
P7
PD6
PD7
P8
03EF16 Port P7 direction register
03F016 Port P8 register
03F116
Port P9 register
P9
PD8
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
Port P8 direction register
Port P9 direction register
Port P10 register
PD9
P10
278
Port P10 direction register
PD10
03FC16 Pull-up control register 0
PUR0
PUR1
PUR2
PCR
280
280
280
281
03FD16
Pull-up control register 1
03FE16
03FF16
Pull-up control register 2
Port control register
Note : The blank areas are reserved and cannot be accessed by users.
B-4
M16C/28 Group
REJ09B0047-0060Z
Rev.0.60
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2004.02.01
1. Overview
The M16C/28 group of single-chip microcomputers is built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and is packaged in a 64-pin and 80-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and a DMAC which combined with fast instruction pro-
cessing capability, makes it suitable for control of various OA, communication, and industrial equipment
which requires high-speed arithmetic/logic operations.
1.1 Applications
Audio, cameras, office/communications/portable/industrial equipment,
home appliances (inverter solution), etc
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
Rev.0.60 2004.02.01 page 1 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.2 Performance Outline
Table 1.2.1 lists performance outline of M16C/28 group 80-pin device.
Table 1.2.2 lists performance outline of M16C/28 group 64-pin device.
Table 1.2.1. Performance outline of M16C/28 group (80-pin device)
Item
Performance
Number of basic instructions
Shortest instruction execution time
91 instructions
50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V)
100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V)
50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105°C)
62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125°C)
(See the product list)
(Normal-ver./T-ver.)
(Normal-ver.)
(V-ver.)
(V-ver.)
Memory
capacity
I/O port
ROM
RAM
(See the product list)
71 lines
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
TimerS (Input Capture/Output Compare)
:
16bit base timer x 1 channel (Input/Output x 8 channels)
Serial I/O
2 channels (UART0, UART1)
UART, clock synchronous
1 channel (UART2)
2
1
2
UART, clock synchronous, I C bus , or IEBus
2 channels (SI/O3, SI/O4)
Clock synchronous
1 channel (Multi-Master I C bus )
10 bits x 24 channels
2
1
A-D converter
DMAC
Watchdog timer
Interrupt
2 channels (trigger: 31 sources)
15 bits x 1 (with prescaler)
25 internal and 8 external sources, 4 software sources, 7 levels
Clock generation circuit
4 circuits
(These circuits contain a built-in feedback
resistor and external ceramic/quartz oscillator)
• Main clock
• Sub-clock
•
Ring oscillator(main-clock oscillation stop detect function)
• PLL frequency synthesizer
Present
VCC=3.0V to 5.5V (f(BCLK)=20MHZ)
VCC=2.7V to 5.5V (f(BCLK)=10MHZ)
VCC=3.0V to 5.5V
Low voltage detection circuit
Power supply voltage
(Normal-ver.)
(T-ver.)
(V-ver.)
VCC=4.2V to 5.5V
Flash memory Program/erase voltage
Number of program/erase
2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.)
100 times ( Block A ,Block B : 10,000 times (option ) )
3
Power consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz on RAM)
1.8 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz, in wait mode)
0.7 µA (Vcc=3V, when stop mode)
3
Operating ambient temperature
Package
-20 to 85°C / -40 to 85°C (option )
-40 to 85°C
-40 to 105°C / -40 to 125°C
80-pin plastic mold QFP
(Normal-ver.)
(T-ver.)
(V-ver.)
Notes:
2
1. I C Bus is a registered trademark of PHILIPS.
2. IEBus is a trademark of NEC Electronics Corporation.
3. If you desire this option, please so specify.
Rev.0.60 2004.02.01 page 2 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Table 1.2.2. Performance outline of M16C/28 group (64-pin device)
Item
Performance
Number of basic instructions
Shortest instruction execution time
91 instructions
50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V)
100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V)
50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105°C)
62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125°C)
(See the product list)
(Normal-ver./T-ver.)
(Normal-ver.)
(V-ver.)
(V-ver.)
Memory
capacity
I/O port
ROM
RAM
(See the product list)
55 lines
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
TimerS (Input Capture/Output Compare)
: 16bit base timer x 1 channel (Input/Output x 8 channels
2 channels (UART0, UART1)
)
Serial I/O
UART, clock synchronous
1 channel (UART2)
UART, clock synchronous, I C bus , or IEBus
1 channel (SI/O3)
2
1
2
Clock synchronous
1 channel (Multi-Master I C bus )
10 bits x 13 channels
2
1
A-D converter
DMAC
Watchdog timer
Interrupt
2 channels (trigger: 30 sources)
15 bits x 1 (with prescaler)
24 internal and 8 external sources, 4 software sources, 7 levels
Clock generation circuit
4 circuits
• Main clock
• Sub-clock
(These circuits contain a built-in feedback
resistor and external ceramic/quartz oscillator)
•
Ring oscillator(main-clock oscillation stop detect function)
• PLL frequency synthesizer
Present
VCC=3.0V to 5.5V (f(BCLK)=20MHZ)
VCC=2.7V to 5.5V (f(BCLK)=10MHZ)
VCC=3.0V to 5.5V
Low voltage detection circuit
Power supply voltage
(Normal-ver.)
(T-ver.)
(V-ver.)
VCC=4.2V to 5.5V
Flash memory Program/erase voltage
Number of program/erase
2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.)
100 times ( Block A ,Block B : 10,000 times (option ) )
3
Power consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz on RAM)
1.8 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz, in wait mode)
0.7 µA (Vcc=3V, when stop mode)
3
Operating ambient temperature
Package
-20 to 85°C / -40 to 85°C (option )
-40 to 85°C
-40 to 105°C / -40 to 125°C
64-pin plastic mold QFP
(Normal-ver.)
(T-ver.)
(V-ver.)
Notes:
2
1. I C Bus is a registered trademark of PHILIPS.
2. IEBus is a trademark of NEC Electronics Corporation.
3. If you desire this option, please so specify.
Rev.0.60 2004.02.01 page 3 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.3 Block Diagram
Figure 1.3.1 is a block diagram of the M16C/28 group, 80-pin device.
8
8
8
8
8
8
8
7
8
I/O
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Port P8
Port P9
Port P10
Ports
Internal Peripheral Functions
Timer
Timer S
Serial Ports
System Clock Generator
Timer A0 (16 bits)
U(S)ART/SIO (channel 0)
Xin-Xout
Xcin-Xcout
PLL frequency synthesizer
Input Capture (8 channels)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I2C/IEbus
(channel 2)
Output Compare (8 channels)
Ring Oscillator
A-D converter
(10bits x 24 channels)
SIO (channel 3)
Watchdog Timer
SIO (channel 4)
Multi-master I2C BUS
DMAC (2 channels)
3-phase PWM
Low voltage detect
M16C/60 series 16-bit CPU Core
Memory
Program Counter
PC
Flash ROM
Registers
R0H
R0H
R1H
R0L
R0L
R1L
Stack Pointers
ISP
Flash ROM
(Data Flash)
R2
R3
A0
A1
FB
USP
Vector Table
INTB
RAM
Flag Register
FLG
Multiplier
SB
Figure 1.3.1. M16C/28 Group, 80-pin Block Diagram
Rev.0.60 2004.02.01 page 4 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Figure 1.3.2 is a block diagram of the M16C/28 group, 64-pin device.
4
3
8
4
8
8
8
4
8
I/O
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Port P8
Port P9
Port P10
Ports
Internal Peripheral Functions
Timer
Timer S
Serial Ports
System Clock Generator
Timer A0 (16 bits)
U(S)ART/SIO (channel 0)
Xin-Xout
Xcin-Xcout
PLL frequency synthesizer
Input Capture (8 channels)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I2C/IEbus
(channel 2)
Output Compare (8 channels)
Ring Oscillator
A-D converter
(10bits x 13 channels)
SIO (channel 3)
Watchdog Timer
Multi-master I2C BUS
DMAC (2 channels)
3-phase PWM
Low voltage detect
M16C/60 series 16-bit CPU Core
Memory
Program Counter
PC
Flash ROM
Registers
R0H
R0H
R1H
R0L
R0L
R1L
Stack Pointers
ISP
Flash ROM
(Data Flash)
R2
R3
A0
A1
FB
USP
Vector Table
INTB
RAM
Flag Register
FLG
Multiplier
SB
Figure 1.3.2. M16C/28 Group, 64-pin Block Diagram
Rev.0.60 2004.02.01 page 5 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.4 Product List
Tables 1.4.1 to 1.4.3 list the M16C/28 group products and Figure 1.4.1 shows the type numbers, memory
sizes and packages.
Table 1.4.1. Product List (1) -Normal Version
As of November 2003
Type No.
ROM capacity
48K + 4K byte
64K + 4K byte
96K + 4K byte
48K + 4K byte
64K + 4K byte
96K + 4K byte
32K byte
RAM capacity
4K byte
4K byte
8K byte
4K byte
4K byte
8K byte
2K byte
4K byte
4K byte
2K byte
4K byte
4K byte
Package type
Remarks
M30280F6HP
**
**
**
**
**
**
*
M30280F8HP
80P6Q-A
M30280FAHP
Flash ROM Version
M30281F6HP
M30281F8HP
64P6Q-A
80P6Q-A
64P6Q-A
M30281FAHP
M30280M4-XXXHP
M30280M6-XXXHP
M30280M8-XXXHP
M30281M4-XXXHP
M30281M6-XXXHP
M30281M8-XXXHP
* : under planning
*
48K byte
*
64K byte
Mask ROM Version
*
32K byte
*
48K byte
*
64K byte
** : under development
Table 1.4.2. Product List (2) -T Version
As of November 2003
Type No.
M30280F6THP
ROM capacity
48K + 4K byte
64K + 4K byte
96K + 4K byte
48K + 4K byte
64K + 4K byte
96K + 4K byte
32K byte
RAM capacity
4K byte
4K byte
8K byte
4K byte
4K byte
8K byte
2K byte
4K byte
4K byte
2K byte
4K byte
4K byte
Package type
Remarks
**
**
**
**
**
**
*
M30280F8THP
80P6Q-A
64P6Q-A
80P6Q-A
64P6Q-A
M30280FATHP
Flash ROM Version
(T-version)
M30281F6THP
M30281F8THP
M30281FATHP
M30280M4T-XXXHP
M30280M6T-XXXHP
M30280M8T-XXXHP
M30281M4T-XXXHP
M30281M6T-XXXHP
M30281M8T-XXXHP
* : under planning
*
48K byte
*
64K byte
Mask ROM Version
(T-version)
*
32K byte
*
48K byte
*
64K byte
** : under development
Rev.0.60 2004.02.01 page 6 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Table 1.4.2. Product List (3) -V Version
As of November 2003
Type No.
M30280F6VHP
ROM capacity
48K + 4K byte
64K + 4K byte
96K + 4K byte
48K + 4K byte
64K + 4K byte
96K + 4K byte
32K byte
RAM capacity
4K byte
4K byte
8K byte
4K byte
4K byte
8K byte
2K byte
4K byte
4K byte
2K byte
4K byte
4K byte
Package type
Remarks
**
**
**
**
**
**
*
M30280F8VHP
80P6Q-A
M30280FAVHP
Flash ROM Version
(V-version)
M30281F6VHP
M30281F8VHP
64P6Q-A
80P6Q-A
64P6Q-A
M30281FAVHP
M30280M4V-XXXHP
M30280M6V-XXXHP
M30280M8V-XXXHP
M30281M4V-XXXHP
M30281M6V-XXXHP
M30281M8V-XXXHP
* : under planning
*
48K byte
*
64K byte
Mask ROM Version
(V-version)
*
32K byte
*
48K byte
*
64K byte
** : under development
Type No.
M 3 0 2 8 0 F 8 T H P
Package type:
HP : Package 80P6Q, 64P6Q
Version
(no): Normal version
T
V
: T version
: V version
ROM capacity / RAM capacity:
4: (32K) bytes /2K bytes
6: (48K+4K) bytes (Note 1)/4K bytes
8: (64K+4K) bytes (Note 1)/4K bytes
A: (96K+4K) bytes (Note 1)/8K bytes
C: (128K+4K) bytes (Note 1,2)/12K bytes
Note 1: Only flash memory version exists in "+4K bytes"
Note 2: Under planning
Memory type:
M: Mask ROM version
F: Flash memory version
Shows pin count
(The value itself has no specific meaning)
M16C/28 Group
M16C Family
Figure 1.4.1. Type No., Memory Size, and Package
Rev.0.60 2004.02.01 page 7 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.5 Pin Configuration
Figures 1.5.1 and 1.5.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
P63/TXD0
P06/AN06
61
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P30/CLK3
P05/AN05
P04/AN04
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P31/SIN3
P32/SOUT3
P03/AN03
P02/AN02
P33
P01/AN01
P34
P35
P00/AN00
P36
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P37
P64/RTS1/CTS1/CTS0/CLKS1
P65/CLK1
M30280Fx-XXXHP
P66/RXD1
P103/AN3
P102/AN2
P67/TXD1
P70/TXD2/SDA/TA0OUT
P101/AN1
{
/RTS1/CTS
1/CTS0/CLKS1
P71/RXD2/SCL/TA 0IN/CLK1
P72/CLK2/TA1OUT/V/RXD1
P73/CTS2/RTS2/TA1IN/V/TXD1
P74/TA2OUT/W
AVss
P100/AN0
VREF
AVcc
P97/AN27/SIN4
P75/TA2IN/W
P96/AN26/SOUT4
P76/TA3OUT
Package: 80P6Q-A
Note. Set PACR2 to PACR0 bit in the PACR register
to "011 " before you input and output it after
2
resetting to each pin. When the PACR register
isn’t set up, the input and output function of
some of the pins are disabled.
Figure 1.5.1. Pin Configuration (Top View) of M16C/28 Group, 80-pin Package
Rev.0.60 2004.02.01 page 8 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
PIN CONFIGURATION (top view)
P02/AN02
P30/CLK3
P31/SIN3
P32/SOUT3
P33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
P01/AN01
0
P0 /AN00
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
P64/RTS1/CTS1/CTS0/CLKS1
P65/CLK1
P66/RXD1
P67/TXD1
M30281Fx-XXXHP
P70/TXD2/SDA/TA0OUT
P102/AN2
{
/RTS1/CTS1/CTS0/CLKS1
P101/AN1
P71/RXD2/SCL/TA0IN/CLK1
P72/CLK2/TA1OUT/V/RXD1
P73/CTS2/RTS2/TA1IN/V/TXD1
AVss
59
60
61
62
63
64
P100/AN0
P74/TA2OUT/W
P75/TA2IN/W
P76/TA3OUT
P77/TA3IN
VREF
AVcc
P93/AN24
P92/TB2IN
Package: 64P6Q-A
Note. Set PACR2 to PACR0 bit in the PACR register to
"010 " before you input and output it after resetting
2
to each pin. When the PACR register isn’t set up,
the input and output function of some of the pins
are disabled.
Figure 1.5.2. Pin Configuration (Top View) of M16C/28 Group, 64-pin Package
Rev.0.60 2004.02.01 page 9 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.6 Pin Description
Table 1.6.1 and 1.6.2 describes the available pins.
Table 1.6.1 Pin Description(1)
Pin name Signal name
I/O type
Function
VCC,VSS
Power supply
input
Apply 0V to the Vss pin, and the following voltage to the Vcc pin.
2.7 to 5.5V (Normal-ver.)
3.0 to 5.5V (T-ver.)
4.2 to 5.5V (V-ver.)
CNVSS
CNVSS
Input
Connect this pin to Vss.
____________
RESET
XIN
Reset input
Clock input
Clock output
Input
"L" on this input resets the microcomputer.
These pins are provided for the main clock generating circuit input/
output. Connect a ceramic resonator or crystal between the XIN and
the XOUT pins. To use an externally derived clock, input it to the XIN
pin and leave the XOUT pin open. If XIN is not used (for external
oscillator or external clock) connect XIN pin to VCC and leave XOUT
pin open.
Input
XOUT
Output
AVCC
Analog power
supply input
Analog power
supply input
Reference
This pin is a power supply input for the A-D converter. Connect this
pin to VCC.
AVSS
This pin is a power supply input for the A-D converter. Connect this
pin to VSS.
VREF
Input
This pin is a reference voltage input for the A-D converter.
Voltage input
I/O port P0
P00~P07
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When used for input, a pull-up resister option can be
selected for the entire group of four pins.Software can also select
this port to function as A-D converter input pins. P04~P07 is not in 64
pin version.
P10~P17
I/O port P1
Input/output
Input/output
This is an 8-bit I/O port equivalent to P0. Additional software-select
able secondary functions are: 1) P10 to P13 can act as A-D converter
input pins; 2) P15 to P17 can be configured as external interrupt pins;
3) P15 to P17 can be configured as position-data-retain function
input pins,and; 4) P15 can input a trigger for the A-D converter.
P10~P14 is not in 64 pin version.
P20~P27
I/O port P2
This is an 8-bit I/O port equivalent to P0. Software can also select
this port to perform as I/O for the Timer S (all pins), and MultiMaster
2
I C Bus (P20 and P21 only)
P30~P37
P60~P67
P70~P77
I/O port P3
I/O port P6
I/O port P7
Input/output
Input/output
Input/output
This is an 8-bit I/O port equivalent to P0. P30 to P32 also function as
SIO3 I/O, as selected by software. P34~P37 is not in 64 pin version.
This is an 8-bit I/O port equivalent to P0. Pins in this port also func-
tion as UART0 and UART1 I/O, as selected by software.
This is an 8-bit I/O port equivalent to P0. P7 can also function as I/O
for timer A0-A3, as selected by software. Additional programming
options are: P70 to P73 can assume UART1 and UART2 I/O capa-
bilities, and P72 to P75 can function as output pins for the three-
phase motor control timer.
Rev.0.60 2004.02.01 page 10 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Table 1.6.2 Pin Description(2)
Pin name Signal name I/O type
I/O port P8
Function
P80~P87
Input/output
This is an 8-bit I/O port equivalent to P0. Additional software-select
able secondary functions are: 1) P80 and P81 can act as either I/O
for Timer A4, or as output pins for the three-phase motor control
timer; 2) P82 to P84 can be configured as external interrupt pins.
P84 can be used for Timer A Zphase function; 3) P85 can be used
_______ _____
as NMI/SD. P85 can not be used as I/O port while the three-phase
motor control is enabled. Apply a stable "H" to P85 after setting the
direction register for P85 to "0" when the three-phase motor control
is enabled, and; 4) P86 and P87 can serve as I/O pins for the
sub-clock generation circuit. In this latter case, a quartz oscillator
must be connented between P86 (XCOUT pin) and P87 (XCIN pin).
This is an 7-bit I/O port equivalent to P0. Additional software-select
able secondary functions are: 1) P90 to P92 can act as Timer B0~B2
input pins; 2) P93, P95 to P97 can act as A-D converter input pins,
and; 3) P96 to P97 can assume SI/O4 I/O. P95 to P97 is not in 64 pin
version.
P90~P93, I/O port P9
P95~P97
Input/output
Input/output
P100~P107 I/O port P10
This is an 8-bit I/O port equivalent to P0. This port can also function
as A-D converter input pins, as selected by software. Furthermore,
P104-P107 can also function as input pins for the key input interrupt
function.
Rev.0.60 2004.02.01 page 11 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit(CPU)
M16C/28 Group
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
b15
b8b7
b0
R2
R3
R0H(R0's high bits) R0L(R0's low bits)
R1H(R1's high bits)R1L(R1's low bits)
Data registers (Note)
R2
R3
A0
A1
FB
Address registers (Note)
Frame base registers (Note)
b19
b15
b0
INTBH
INTBL
Interrupt table register
Program counter
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
b0
PC
b15
USP
User stack pointer
Interrupt stack pointer
Static base register
ISP
SB
b15
b0
b0
FLG
Flag register
b15
b8 b7
IPL
U
I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 2.1. Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-
bit data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.0.60 2004.02.01 page 12 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
2. Central Processing Unit(CPU)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”
.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
Rev.0.60 2004.02.01 page 13 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
3. Memory
M16C/28 Group
3. Memory
Figure 3.1 is a memory map of the M16C/28 group. The linear address space of 1M bytes extends from
address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30280F8HP,there are
64 Kbytes of internal ROM from F000016 to FFFFF16.
The vector table for fixed interrupts, such as Reset and NMI, is mapped from FFFDC16 to FFFFF16. The
starting address of the interrupt routine is stored here.
The address of the vector table for timer interrupts,etc.,can be set as desired using the interrupt table
register(INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30280FAHP, 8K bytes of internal RAM is mapped to the
space from 0040016 to 023FF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
These devices also contain two blocks of Flash ROM as Data Flash memory to store data. These two
blocks of 2K bytes are located from 0F00016 to 0FFFF16 on all versions.
The SFR area is mapped from 0000016 to 003FF16. This area accommodates the control registers for
peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area
that is not occupied is reserved and cannot be used for other purposes.
The special page vector table is allocated to the address from FFE0016 to FFFDB16. This vector is used by
the JMPS or JSRS instruction. For details, refer to the "M16C/60 and M16C/20 Series Software Manual".
Internal RAM area
Internal ROM area
Memory size
Memory size
XXXXX16
00BFF16
013FF16
023FF16
YYYYY16
F800016
F400016
F000016
E800016
E000016
32K byte
48K byte
2K byte
4K byte
8K byte
0000016
0040016
64K byte
96K byte
(Note2)
128K byte
SFR area
Internal RAM area
FFE0016
FFFDC16
FFFFF16
XXXXX16
0F00016
0FFFF16
RESERVED
Special page
vector table
Internal ROM area
(data area)
(Note1)
Undefined instruction
Overflow
RESERVED
BRK instruction
Address match
Single step
Watchdog timer
YYYYY16
FFFFF16
DBC
Internal ROM area
(program area)
NMI
Reset
Note 1 : The block A (2K bytes) and block B (2K bytes) are shown
(only flash memory)
Note 2 : Under planning
Figure 3.1. Memory Map
Rev.0.60 2004.02.01 page 14 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
4. Special Function Register (SFR) Map
Address
Register Name
Acronym
Value after Reset
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
PM0
PM1
CM0
CM1
0016
00001000
01001000
00100000
2
2
2
Address match interrupt enable register
Protect register
AIER
PRCR
XXXXXX00
XX000000
2
2
Oscillation stop detection register
(Note 2)
CM2
0X000010
2
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
??16
00??????
0016
0016
2(Note 3)
X016
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1
Voltage detection register 2
(Note 4)
(Note 4)
VCR1
VCR2
00001000
0016
2
PLL control register 0
PLC0
0001X0102
Processor mode register 2
Voltage down detection interrupt register
DMA0 source pointer
PM2
D4INT
SAR0
XXX00000
0016
??16
2
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
??16
X?16
DMA0 destination pointer
DMA0 transfer counter
DMA0 control register
DMA1 source pointer
DMA1 destination pointer
DMA1 transfer counter
DMA1 control register
DAR0
TCR0
??16
??16
X?16
??16
??16
DM0CON
SAR1
00000?002
??16
??16
X?16
DAR1
??16
??16
X?16
TCR1
??16
??16
DM1CON
00000?002
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
Note 3: Tjhe WDC5 bit is "0" (cold start) immediately after power-on. It can only be set to "1" in a program. It is set to "0" when the input
voltage at the Vcc pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to "1"(RAM retention limit detection
circuit enable).
Note 4: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.1. SFR Map (1 of 7)
Rev.0.60 2004.02.01 page 15 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Register Name
Value after Reset
Address
004016
004116
004216
004316
004416
Acronym
INT3 interrupt control register
INT3IC
ICOC0IC
ICOC1IC, IICIC
BTIC, SCLDAIC
S4IC, INT5IC
S3IC, INT4IC
BCNIC
XX00?0002
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
IC/OC 0 interrupt control register
XXXX?000
XXXX?000
XXXX?000
2
2
2
IC/OC 1 interrupt control register, I2C-BUS interface interrupt control register
IC/OC base timer interrupt control register, SCLSDA interrupt control register
SI/O4 interrupt control register, INT5 interrupt control register
SI/O3 interrupt control register, INT4 interrupt control register
UART2 Bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
Key input interrupt control register
A-D conversion interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
XX00?000
XX00?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XX00?000
XX00?000
XX00?000
2
2
2
INT1 interrupt control register
INT2 interrupt control register
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Note 1: The blank areas are reserved and cannot be accessed by users.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.2. SFR Map (2 of 7)
Rev.0.60 2004.02.01 page 16 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Register Name
Acronym
Value after Reset
Address
008016
008116
008216
008316
008416
008516
008616
~
~
~
~
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
Flash memory control register 4
Flash memory control register 1
Flash memory control register 0
(Note 2)
(Note 2)
(Note 2)
FMR4
FMR1
FMR0
010000002
000???0?2
??0000012
~
~
~
~
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
Ring oscillator control register
Pin assignment control register
Peripheral clock select register
ROCR
PACR
PCLKR
000001012
0016
000000112
~
~
~
~
I2C0 data shift register
S00
??16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
I2C0 address register
S0D0
S1D0
S20
S2D0
S3D0
S4D0
S10
0016
0016
0016
000110102
001100002
0016
I2C0 control register 0
I2C0 clock control register
I2C0 start/stop condition control register
I2C0 control register 1
I2C0 control register 2
I2C0 status register
0001000X2
~
~
~
~
02FE16
02FF16
Note 1:The blank areas are reserved and cannot be accessed by users.
Note 2:This register is included in the flash memory version.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.3. SFR Map (3 of 7)
Rev.0.60 2004.02.01 page 17 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Register Name
Acronym
Value after Reset
Address
030016
TM/WG register 0
TM/WG register 1
TM/WG register 2
TM/WG register 3
TM/WG register 4
TM/WG register 5
TM/WG register 6
TM/WG register 7
G1TM0/G1PO0
G1TM1/G1PO1
G1TM2/G1PO2
G1TM3/G1PO3
G1TM4/G1PO4
G1TM5/G1PO5
G1TM6/G1PO6
G1TM7/G1PO7
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
0X00X000
0X00X000
0X00X000
0X00X000
0X00X000
0X00X000
0X00X000
0X00X000
0016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
WG control register 0
WG control register 1
WG control register 2
WG control register 3
WG control register 4
WG control register 5
WG control register 6
WG control register 7
TM control register 0
TM control register 1
TM control register 2
TM control register 3
TM control register 4
TM control register 5
TM control register 6
TM control register 7
Base timer register
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
G1BT
2
2
2
2
2
2
2
2
0016
0016
0016
0016
0016
0016
0016
??16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
??16
0016
0016
0016
0016
0016
0016
??16
Base timer control register 0
Base timer control register 1
TM prescale register 6
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
TM prescale register 7
Function enable register
Function select register
Base timer reset register
G1FS
G1BTRR
??16
0016
Divider register
G1DV
Interrupt request register
Interrupt enable register 0
Interrupt enable register 1
G1IR
G1IE0
G1IE1
??16
0016
0016
NMI digital debounce register
P17 digital debounce register
NDDR
P17DDR
FF16
FF16
Note 1:The blank areas are reserved and cannot be accessed by users.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.4. SFR Map (4 of 7)
Rev.0.60 2004.02.01 page 18 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Register Name
Acronym
Value after Reset
Address
034016
034116
034216
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
TA11
TA21
TA41
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
??16
X?16
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
INVC0
INVC1
IDB0
IDB1
DTT
Timer B2 interrupt occurrence frequency set counter
Position-data-retain function contol register
ICTB2
PDRF
XXXX0000
2
Interrupt request cause select register 2
Interrupt request cause select register
SI/O3 transmit/receive register
IFSR2A
IFSR
S3TRR
00XXXXXX
0016
??16
2(Note 2)
SI/O3 control register
SI/O3 bit rate generator
SI/O4 transmit/receive register
S3C
S3BRG
S4TRR
01000000
??16
??16
2
2
SI/O4 control register
SI/O4 bit rate generator
S4C
S4BRG
01000000
??16
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate generator
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
0016
000X0X0X
X0000000
X0000000
0016
??16
????????
XXXXXXX?
2
2
2
U2BRG
U2TB
UART2 transmit buffer register
2
2
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
U2C0
U2C1
U2RB
00001000
00000010
????????
2
2
2
?????XX?
2
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: Write "1" to bit 0 after reset.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.5. SFR Map (5 of 7)
Rev.0.60 2004.02.01 page 19 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Register Name
Acronym
Value after Reset
0016
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
Count start flag
TABSR
CPSRF
ONSF
TRGSR
UDF
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
0XXXXXXX
2
0016
0016
0016
Timer A0 register
Timer A1 register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
0016
038A16 Timer A2 register
038B16
038C16 Timer A3 register
038D16
038E16 Timer A4 register
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
039A16 Timer A4 mode register
039B16 Timer B0 mode register
039C16 Timer B1 mode register
039D16 Timer B2 mode register
039E16 Timer B2 special mode register
039F16
00??0000
2
00?X0000
00?X0000
X0000000
2
2
2
03A016
UART0 transmit/receive mode register
UART0 bit rate generator
UART0 transmit buffer register
U0MR
U0BRG
U0TB
0016
??16
????????
03A116
03A216
2
03A316
XXXXXXX?
2
03A416
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
U0C0
U0C1
U0RB
00001000
00000010
????????
2
2
2
03A516
03A616
03A716
?????XX?
0016
??16
2
03A816
UART1 transmit/receive mode register
UART1 bit rate generator
UART1 transmit buffer register
U1MR
U1BRG
U1TB
03A916
03AA16
????????
2
03AB16
XXXXXXX?
2
03AC16
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
U1C0
U1C1
U1RB
00001000
00000010
????????
2
2
2
03AD16
03AE16
03AF16
?????XX?
2
03B016
UART transmit/receive control register 2
UCON
X00000002
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
DMA0 request cause select register
DM0SL
DM1SL
0016
0016
03B916
03BA16
DMA1 request cause select register
03BB16
03BC16
03BD16
03BE16
03BF16
Note 1:The blank areas are reserved and cannot be accessed by users.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.6. SFR Map (6 of 7)
Rev.0.60 2004.02.01 page 20 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Address
Register Name
Acronym
Value after Reset
03C016
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
A-D trigger control register
A-D convert status register 0
A-D control register 2
ADTRGCON
ADSTAT0
ADCON2
XXXX00002
00000X002
0016
A-D control register 0
A-D control register 1
ADCON0
ADCON1
00000???2
0016
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
??16
??16
0016
0016
??16
??16
0016
0016
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
P6
P7
PD6
PD7
P8
??16
??16
0016
0016
??16
???X????2
0016
000X00002
??16
Port P9 register
P9
Port P8 direction register
Port P9 direction register
Port P10 register
PD8
PD9
P10
Port P10 direction register
PD10
0016
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
Port control register
PUR0
PUR1
PUR2
PCR
0016
0016
0016
0016
Note 1:The blank areas are reserved and cannot be accessed by users.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.7. SFR Map (7 of 7)
Rev.0.60 2004.02.01 page 21 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
5. Reset
5. Reset
There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla-
tion stop detection reset.
5.1 Hardware Reset
There are two types of hardware resets: a hardware reset 1 and a hardware reset 2.
5.1.1 Hardware Reset 1
____________
____________
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the
power supply voltage is within the recommended operating condition, the pins are initialized (see
____________
Table 5.1.1.1 Pin Status When RESET Pin Level is “L”). The internal ring oscillator is initialized and
used as sysem clock.
____________
When the input level at the RESET pin is released from “L” to “H”, the CPU and SFR are initialized,
and the program is executed starting from the address indicated by the reset vector. The internal RAM
____________
is not initialized. If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM
becomes indeterminate.
Figure 5.1.1.1 shows the example reset circuit. Figure 5.1.1.2 shows the reset sequence. Table
____________
5.1.1.1 shows the status of the other pins while the RESET pin is “L”. Figure 5.1.1.3 shows the CPU
register status after reset. Refer to “SFR Map” for SFR status after reset.
1. When the power supply is stable
____________
(1) Apply an “L” signal to the RESET pin.
(2) Wait td(ROC) or more.
____________
(3) Apply an “H” signal to the RESET pin.
2. Power on
____________
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condition.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Wait td(ROC) or more.
____________
(5) Apply an “H” signal to the RESET pin.
5.1.2 Hardware Reset 2
This reset is generated by the microcomputer’s internal voltage detection circuit. The voltage detec-
tion circuit monitors the voltage supplied to the VCC pin.
If the VC26 bit in the VCR2 register is set to “1” (reset level detection circuit enabled), the microcom-
puter is reset when the voltage at the VCC input pin drops below Vdet3.
Similarly, if the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit en-
abled), the microcomputer is reset when the voltage at the VCC input pin drops below Vdet2.
Conversely, when the input voltage at the VCC pin rises to Vdet3 or more, the pins and the CPU and
SFR are initialized, and the program is executed starting from the address indicated by the reset
vector. It takes about td(S-R) before the program starts running after Vdet3 is detected. The initialized
pins and registers and the status thereof are the same as in hardware reset 1.
Set the CM10 bit in the CM1 register to “1” (stop mode) after setting the VC25 bit to “1” (RAM retention
limit detection circuit enabled), and the microcomputer will be reset when the voltage at the VCC input
pin drops below Vdet2 and comes out of reset when the voltage at the VCC input pin rises above
Vdet3. During stop mode, the value set in the VC26 bit has no effect. Therefore, no reset is generated
even when the input voltage at the VCC pin drops to Vdet3 or less.
Rev.0.60 2004.02.01 page 22 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
5. Reset
Recommended
operating
voltage
V
CC
0V
V
CC
RESET
RESET
0V
Equal to or less
than 0.2VCC
Equal to or less
than 0.2VCC
More than td(ROC) + td(P-R)
Figure 5.1.1.1. Example Reset Circuit
5.2 Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,
CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset
vector. The device will reset using internal ring oscillator as the system clock.
At software reset, some SFR’s are not initialized. Refer to “SFR”.
5.3 Watchdog Timer Reset
When the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcomputer
initializes its pins, CPU and SFR if the watchdog timer underflows. The device will reset using internal ring
oscillator as the system clock. Then the program is executed starting from the address indicated by the
reset vector.
At watchdog timer reset, some SFR’s are not initialized. Refer to “SFR”.
5.4 Oscillation Stop Detection Reset
When the CM27 bit in the CM2 register is “0” (reset at oscillation stop detection), the microcomputer
initializes its pins, CPU and SFR, coming to a halt if it detects main clock oscillation circuit stop. Refer to
the section “oscillation stop, re-oscillation detection function”.
At oscillation stop detection reset, some SFR’s are not initialized. Refer to the section “SFR”.
Rev.0.60 2004.02.01 page 23 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
5. Reset
VCC
ROC
td(P-R)
More than
td(ROC)
RESET
CPU clock 28cycles
CPU clock
FFFFC16
Content of reset vector
Address
FFFFE16
Figure 5.1.1.2. Reset Sequence
____________
Table 5.1.1.1. Pin Status When RESET Pin Level is “L”
Status
Pin name
P0 to P3,
P6 to P10
Input port (high impedance)
b15
b0
000016
Data register(R0)
Data register(R1)
Data register(R2)
000016
000016
000016
000016
000016
000016
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
b19
b0
b0
0000016
Interrupt table register(INTB)
Program counter(PC)
Content of addresses FFFFE16 to FFFFC16
b15
User stack pointer(USP)
000016
000016
000016
Interrupt stack pointer(ISP)
Static base register(SB)
b15
b0
b0
Flag register(FLG)
000016
b15
b8 b7
IPL
U
I
O B S Z D C
Figure 5.1.1.3. CPU Register Status After Reset
Rev.0.60 2004.02.01 page 24 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
5. Reset
5.5 Voltage Detection Circuit
The voltage detection circuit has circuits to monitor the input voltage at the VCC pin, each checking the input
voltage with respect to Vdet2, Vdet3, and Vdet4, respectively. Use the VC25 to VC27 bits in the VCR2
register to select whether or not to enable these circuits.
The VC25 bit in the VCR2 register needs to be set to “1” (the internal RAM retention limit detection circuit
enable) when using hardware reset 2 in stop mode, or when using the WDC5 bit. WDC5 bit =“1” shows
state of the internal RAM retention.Use the reset level detection circuit for hardware reset 2.
The voltage down detection circuit can be set to detect whether the input voltage is equal to or greater than
Vdet4 or less than Vdet4 by monitoring the VC13 bit in the VCR1 register. Furthermore, a voltage down
detection interrupt can be generated.
WDC5 bit
Write to WDC register
S
R
Q
WARM/COLD
(Cold start, warm start)
Internal power on reset
VCR2 register
b7 b6 b5
RESET
Internal power supply
voltage stable time
1 shot
>T
+
td(S-R)
Vdet2
Half latch
E
Q
D
T
Q
+
Internal reset signal
(“L” active)
Vdet3
E
CM10 bit=1
(stop mode)
+
V
CC
Vdet4
Voltage down
detection interrupt
Noise rejection
E
VCR1 register
b3
VC13 bit
Figure 5.5.1. Voltage Detection Circuit Block
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
After reset
00XXXXXX (Note 2)
0
2
Bit symbol
Bit name
High-order bit of watchdog timer
Cold start / warm start 0 : Cold start
Function
RW
RO
(b4-b0)
WDC5
RW
RW
discrimination flag (Note 1, 2) 1 : Warm start
Reserved bit
Must set to “0”
(b6)
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
RW
Note 1: Writing to the WDC register causes the WDC5 bit to be set to “1” (warm start).
Note 2: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set
to “0” when the input voltage at the VCC pin drops to Vdet
is set to “1” (RAM retention limit detection circuit enable).
2 or less while the VC25 bit in the VCR2 register
Figure 5.5.2. WDC Register
Rev.0.60 2004.02.01 page 25 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
5. Reset
Voltage detection register 1
b7
b
b
b4
b
b
b1
b
Symbol
Address
001916
After reset (Note 2)
00001000
0 0 0 0
0 0 0
VCR1
2
Bit name
Function
RW
Bit symbol
(b2-b0)
Reserved bit
Must set to “0”
RW
RO
Voltage down monitor flag
(Note 1)
0:VCC < Vdet4
VC13
1:VCC ≥ Vdet4
Must set to “0”
RW
Reserved bit
(b7-b4)
Note 1: The VC13 bit is useful when the VC27 bit of VCR2 register is set to “1” (voltage down detection circuit
enable). The VC13 bit is always “1” (VCC≥ Vdet4) when the VC27 bit in the VCR2 register is set to “0” (voltage
down detection circuit disable).
Note 2: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Voltage detection register 2 (Note 1)
b7
b
b
b4
b
b
b1
b
Symbol
VCR2
Address
001A16
After reset (Note 6)
0016
0 0 0 0 0
Bit name
RW
RW
Bit symbol
(b4-b0)
Function
Must set to “0”
Reserved bit
0: Disable RAM retention limit
detection circuit
1: Enable RAM retention limit
detection circuit
0: Disable reset level detection
circuit
1: Enable reset level detection
circuit
RAM retention limit
detection monitor bit
(Notes 3, 4, 7)
VC25
RW
RW
VC26
VC27
Reset level monitor bit
(Notes 2, 3, 7)
0: Disable voltage down
detection circuit
1: Enable voltage down
detection circuit
Voltage down monitor
bit (Note 5)
RW
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: When not in stop mode, to use hardware reset 2, set the VC26 bit to “1” (reset level detection circuit enable).
Note 3: To use hardware reset 2 in stop mode, set the VC25 bit to “1” (RAM retention limit detection circuit enable).
VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc
becomes lower than Vdet3.)
1 pin
Note 4: To use the WDC5 bit in the WDC register, set the VC25 bit to “1” (RAM retention limit detection circuit enable).
Note 5: When the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to “1”
(voltage down detection interrupt enable), set the VC27 bit to “1” (voltage down detection circuit enable).
Note 6: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 7: The detection circuit does not start operation until td(E-A) elapses after the VC25 bit, VC26 bit, or VC27 bit are
Voltage down detection interrupt register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
D4INT
Address
001F16
After reset
0016
Bit symbol
D40
RW
RW
Bit name
Voltage down detection
Function
0 : Disable
1 : Enable
interrupt enable bit (Note 5)
0: Disable (do not use the voltage
down detection
interrupt to get out of stop mode)
1: Enable (use the voltage down
detection interrupt to get
out of stop mode)
STOP mode deactivation
control bit
(Note 4)
D41
RW
Voltage change detection flag
(Note 2)
0: Not detected
1: Vdet4 passing detection
RW
D42
D43
DF0
DF1
(Note 3)
0: Not detected
1: Detected
RW
(Note 3)
WDT overflow detect flag
Sampling clock select bit
b5b4
RW
RW
00 : CPU clock divided by 8
01 : CPU clock divided by 16
10 : CPU clock divided by 32
11 : CPU clock divided by 64
Nothing is assigned. When write, set to “0”. When read, its
content is “0”.
(b7-b6)
Note 1: Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).
Note 2: Useful when the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled). If the
VC27 bit is set to “0” (voltage down detection circuit disable), the D42 bit is set to “0” (Not detect).
Note 3: This bit is set to “0” by writing a “0” in a program. (Writing a “1” has no effect.)
Note 4: If the voltage down detection interrupt needs to be used to get out of stop mode again after once used for
that purpose, reset the D41 bit by writing a “0” and then a “1”.
Note 5: The D40 bit is effective when the VCR2 register VC27 bit = 1. To set the D40 bit to “1”, follow the
procedure described below.
(1) Set the VC27 bit to “1”.
(2) Wait for td(E-A) until the detection circuit is actuated.
(3) Wait for the sampling time (refer to “Table 5.5.1.2 Sampling Clock Periods”).
Figure 5.5.3. VCR1 Register, VCR2 Register, and D4INT Register
Rev.0.60 2004.02.01 page 26 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
5. Reset
(1) When stop mode is not used
5.0V
5.0V
Vdet4
Vdet3r
Vdet3
V
CC
Vdet2
Vdet3s
V
SS
RESET
Internal reset signal
VC13 bit
undefined
undefined
Set to “1” in a program (reset level detection circuit enable)
VC26 bit
VC25 bit
Set to “1” in a program
(RAM retention limit detection circuit enable)
undefined
undefined
Set to “1” in a program (warm start)
WDC5 bit
The above diagram applies to the following case:
• The CM10 bit in the CM1 register =0 (clock oscillating, not in stop mode)
• The VC27 bit in the VCR2 register is set to “1” after reset (voltage down detection circuit enabled)(to use VC13)
(1) When stop mode is used
5.0V
5.0V
Vdet4
Vdet3r
V
CC
Vdet2
Vdet3s
V
SS
RESET
Internal reset signal
Set to “1” in a program (warm start)
WDC5 bit
undefined
Set to “1” in a program (stop mode)
CM10 bit
VC13 bit
undefined
undefined
Set to “1” in a program
(RAM retention limit detection circuit enable)
undefined
VC25 bit
The above diagram applies to the following case:
• The VC27 bit in the VCR2 register is set to “1” after reset (voltage down detection circuit enabled)(to use VC13)
Figure 5.5.4. Typical Operation of Hardware Reset 2
Rev.0.60 2004.02.01 page 27 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
5. Reset
5.5.1 Voltage Detection Interrupt
A voltage down detection interrupt request is generated when the input voltage at the VCC pin rises to Vdet4
or more or drops below Vdet4 while the D40 bit in the D4INT register is set to “1” (voltage down detection
interrupt enable). The voltage down detection interrupt shares the interrupt vector with the watchdog timer
interrupt and oscillation stop, re-oscillation detection interrupt.
To use the voltage down detection interrupt to get out of stop mode, set the D41 bit in the D4INT register to
“1” (enable).
The D42 bit in the D4INT register becomes “1” when passing through Vdet4 is detected after the voltage
inputted to the VCC pin is up or down.
A voltage down detection interrupt is generated when the D42 bit changes state from “0” to “1”. The D42 bit
needs to be cleared to “0” by software. However, when D41 bit is “1” and the microcontroller is in stop
mode, if the voltage down detection interrupt occurs (due to voltage applied at VCC increases, passing
through Vdet4), the microcontroller awakes from stop mode with no regard to the status of the D42 bit.
Table 5.5.1.1 shows the voltage down detection interrupt request generation conditions.
It is possible to set the sampling clock detecting that the voltage applied to the VCC pin has passed through
Vdet4 with the DF1 to DF0 bits of D4INT register. Table 5.5.1.2 shows sampling clock periods.
Table 5.5.1.1. Voltage Detection Interrupt Request Generation Conditions
operation mode
VC27 bit
D40 bit
D41 bit
D42 bit
CM02 bit
VC13 bit
Normal
operation
mode(Note 1)
0 to 1 (Note 3)
0 to 1
0 to 1
(Note 3)
(Note 3)
(Note 3)
1 to 0
0 to 1
1 to 0
0 to 1
0
1
0
Wait mode
(Note 2)
1
1
Stop mode
(Note 2)
1
0 to 1
– : “0”or “1”
Note 1: The status except the wait mode and stop mode is handled as the normal mode.(Refer to “Clock generating circuit”)
Note 2: Refer to “Limitations on stop mode”, “Limitations on wait mode”.
Note 3: An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.
Refer to the “Figure 5.5.1.1.2.2.Voltage Down Detection Interrupt Generation Circuit Operation Example” for
details.
Table 5.5.1.2. Sampling Clock Periods
Sampling clock (µs)
CPU
clock
(MHz)
DF1 to DF0=00
DF1 to DF0=01
DF1 to DF0=10
DF1 to DF0=11
(CPU clock divided by 8) (CPU clock divided by 16) (CPU clock divided by 32) (CPU clock divided by 64)
16
3.0
6.0
12.0
24.0
5.5.1.1 Precautions
5.5.1.1.1. Limitations on Stop Mode
Before setting the CM10 bit in the CM1 register to “1”(stop mode), be sure to clear the CM02 bit in the
CM0 register to “0” (do not stop the peripheral function clock). If the CM10 bit in the CM1 register is set to
“1” (stop mode) when the VC13 bit in the VCR1 register is “1” (VCC ≥ Vdet4) while the VC27 bit in the
VCR2 register is “1” (voltage down detection circuit enable) and the D40 bit in the D4INT register is “1”
(voltage down detection interrupt enable) and D41 bit in the D4INT register is “1” (voltage down detection
interrupt is used to get out of stop mode), a voltage down detection interrupt is immediately generated,
causing the microcomputer to exit stop mode.
In systems where the microcomputer enters stop mode when the input voltage at the VCC pin drops below
Vdet4 and exits stop mode when the input voltage rises to Vdet4 or more, make sure the CM10 bit is set
to “1” when VC13 bit is “0” (VCC < Vdet4).
Rev.0.60 2004.02.01 page 28 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
5. Reset
5.5.1.1.2. Limitations on WAIT Instruction
If the WAIT instruction is executed when the VC13 bit in the VCR1 register is “1” (VCC ≥ Vdet4) while the
VC27 bit in the VCR2 register is “1” (voltage down detection circuit enable) and the D40 bit in the D4INT
register is “1” (voltage down detection interrupt enable), a voltage down detection interrupt is immediately
generated, causing the microcomputer to exit wait mode.
In systems where the microcomputer enters wait mode when the input voltage at the VCC pin drops below
Vdet4 and exits wait mode when the input voltage rises to Vdet4 or more, make sure the D42 bit is cleared
to "0" when VC13 bit is “0” (VCC < Vdet4) before executing the WAIT instruction.
Voltage down detection interrupt generation circuit
DF1, DF0
00
01
10
11
2
2
2
2
D42 bit is set to “0”(not detected) by
writing a “0” in a program. VC27 bit
Voltage down detection circuit
VC27
is set to “0” (voltage down detection
circuit disabled), the D42 bit is set to
“0”.
D4INT clock(the
clock with which it
operates also in
wait mode)
1/8
1/2
1/2
1/2
D42
Watchdog
timer interrupt
signal
VC13
V
V
CC
+
-
Noise
rejection
Noise rejection
circuit
Digital
filter
Voltage down
detection signal
REF
(Rejection wide:200 ns)
Voltage down
detection
“H” when VC27 bit= 0
(disabled)
Non-maskable
interrupt signal
D41
interrupt signal
CM10
Oscillation stop,
re-oscillation
detection
CM02
interrupt signal
WAIT instruction(wait mode)
Watchdog timer block
D43
D40
Watchdog timer
underflow signal
This bit is set to “0”(not detected) by writing a “0” in a program.
Figure 5.5.1.1.2.1. Voltage Down Detection Interrupt Generation Block
VCC
VC13 bit
sampling
sampling
sampling
sampling
No voltage down detection interrupt signals are
generated when the D42 bit is “H”.
Output of the digital filter (Note 2)
D42 bit
Set to “0” in a
program (not
detected)
Set to “0” in a
program (not
detected)
Voltage down detection
interrupt signal
Note 1 : D40 is “1”(voltage down detection interrupt enabled)
Note 2 : Output of the digital filter shown in Figure 1.5.8.
Figure 5.5.1.1.2.2. Voltage Down Detection Interrupt Generation Circuit Operation Example
Rev.0.60 2004.02.01 page 29 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
6. Processor Mode
6. Processor Mode
This device functions in single-chip mode only. Figures 6.1 and 6.2 detail the associated registers.
Processor mode register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM0
Address
000416
After reset
000000002
0 0 0 0
0 0 0
Bit symbol
(b2-b0)
Bit name
Function
RW
RW
Reserved bit
Should be set to "0".
Setting this bit to "1" resets the
microcomputer.
When read, its content is "0".
PM03
Software reset bit
Reserved bit
RW
RW
Should be set to "0".
(b7-b4)
Note: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Figure 6.1. PM0 Register
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
000516
After reset
00001000
2
0
0
1
Bit symbol
PM10
Bit name
Function
RW
Flash data block access
bit (Note 2)
0: Disabled
RW
RW
RW
RW
RW
RW
1: Enabled (Note 3)
Reserved bit
Should be set to "0".
(b1)
Watchdog timer function
select bit
0 : Watchdog timer interrupt
1 : Watchdog timer reset (Note 4)
PM12
Reserved bit
Reserved bit
Wait bit (Note 5)
Should be set to "1".
Should be set to "0".
(b3)
(b6-b4)
PM17
0 : No wait state
1 : With wait state (1 wait)
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: To access the two 2K-byte data areas in data block A and data block B, this bit must be set to "1".
Note 3: When CPU rewrite mode (FMR01="1"), this bit is automatically set to "1" during that time.
Note 4: PM12 bit is set to 1 by writing a 1 in a program. (Writing a 0 has no effect.)
Note 5: When PM17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal RAM or
the internal ROM.
Figure 6.2. PM1 Register
Rev.0.60 2004.02.01 page 30 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7. Clock Generation Circuit
The clock generation circuit contains four oscillator circuits as follows:
(1) Main clock oscillation circuit
(2) Sub clock oscillation circuit
(3) Variable ring oscillator (available at reset, oscillation stop detect function)
(4) PLL frequency synthesizer
Table 7.1 lists the clock generation circuit specifications. Figure 7.1 shows the clock generation circuit.
Figures 7.2 to 7.6 show the clock-related registers.
Table 7.1. Clock Generation Circuit Specifications
Main clock
PLL frequency
synthesizer
Sub clock
Item
Variable ring oscillator
CPU clock source
oscillation circuit
oscillation circuit
CPU clock source CPU clock source
CPU clock source
Use of clock
Peripheral function Timer A, B’s clock Peripheral function clock source Peripheral function clock
clock source
source
CPU and peripheral function
clock sources when the main
clock stops oscillating
source
10 to 20 MHz
Clock frequency 0 to 20 MHz
32.768 kHz
Selectable source frequency:
f
1(ROC), f2(ROC), f3(ROC)
Selectable divider:
by 2, by 4, by 8
Ceramic oscillator
Crystal oscillator
Crystal oscillator
Usable oscillator
X
IN, XOUT
XCIN, XCOUT
Pins to connect
oscillator
Presence
Stopped
Presence
Oscillating
Presence
Stopped
Presence
Oscillating
Oscillation stop,
restart function
Oscillator status
after reset
(CPU clock source)
Externally derived clock can be input
Other
Rev.0.60 2004.02.01 page 31 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
Sub-clock
generating circuit
X
CIN
XCOUT
f
C32
1/32
CM04
f
f
1
2
PCLK0=1
PCLK0=0
Sub-clock
f
C
f
8
Ring
oscillator
clock
Variable ring
oscillator
ROCR0,ROCR1
ROCR2, ROCR3
f
32
f
AD
Oscillation
stop, re-
oscillation
detection
circuit
f
1SIO
PCLK1=1
PCLK1=0
f2SIO
f
8SIO
CM10=1(stop mode)
S
R
Q
PLL
frequency
synthesizer
X
IN
X
OUT
f
32SIO
e
b
c
D4INT clock
CPU clock
CM07=0
a
d
PLL
CM21=1
CM21=0
Divider
clock
Main
clock
1
0
fC
Main clock
generating circuit
CM11
CM07=1
CM05
BCLK
CM02
S
R
Q
WAIT instruction
c
e
b
1/2
1/2
1/2
1/2
1/2
a
1/32
RESET
1/2
1/4
1/8
1/16
CM06=0
Software reset
NMI
CM17 CM16=11
2
CM06=1
2
CM06=0
CM17 CM16=10
Interrupt request level judgment output
d
CM02, CM04, CM05, CM06, CM07: CM0 register bits
CM10, CM11, CM16, CM17: CM1 register bits
PCLK0, PCLK1: PCLK register bits
CM06=0
CM17 CM16=01
2
CM21, CM27 : CM2 register bits
CM06=0
CM17 CM16=00
2
Details of divider
Oscillation stop, re-oscillation detection circuit
Variable Ring Oscillator
ROCR1 ROCR0=00
2
f
1(ROC)
Reset
generating
circuit
CM27=0
CM27=1
Pulse generation
circuit for clock
edge detection
and charge,
Oscillation stop
detection reset
Charge,
discharge
circuit
1/2
1/2
1/2
Main
clock
f
2(ROC)
ROCR1 ROCR0=01
2
Oscillation stop,
re-oscillation
Oscillation stop,
re-oscillation
discharge control
ROCR3 ROCR2=11
2
detection signal
detection interrupt
generating circuit
f
3(ROC)
ROCR1 ROCR0=11
2
ROCR3 ROCR2=10
2
Ring
ROCR3 ROCR2=01
2
oscillator
clock
CM21 switch signal
PLL frequency synthesizer
Programmable
counter
1/2
PLL clock
Voltage
control
oscillator
(VCO)
Charge
pump
Phase
comparator
Main clock
Internal low-
pass filter
Figure 7.1. Clock Generation Circuit
Rev.0.60 2004.02.01 page 32 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
After reset
010010002
0
0
Bit symbol
Bit name
Reserved bits
Function
RW
RW
Must set to "0"
(b1-b0)
CM02
Wait Mode peripheral function 0 : Do not stop peripheral function clock in wait mode
clock stop bit (Note 10) 1 : Stop peripheral function clock in wait mode (Note 8)
RW
RW
RW
RW
X
CIN-XCOUT drive capacity 0 : LOW
CM03
select bit (Note 2)
1 : HIGH
Port X
C
select bit
0 : I/O port P86, P87
CM04
CM05
1 : XCIN-XCOUT generation function(Note 9)
(Note 2)
Main clock stop bit
(Notes 3, 10, 12, 13)
0 : On (Note 4)
1 : Off (Note5)
Main clock division select 0 : CM16 and CM17 valid
CM06
CM07
RW
RW
bit 0 (Notes 7, 13, 14)
1 : Division by 8 mode
System clock select bit
(Notes 6, 10, 11, 12)
0 : Main clock, PLL clock, or ring oscillator clock
1 : Sub-clock
Note 1: Write to this register after setting the PRC0 bit of PRCR register to ì1î (write enable).
Note 2: The CM03 bit is set to ì1î (high) when the CM04 bit is set to ì0î (I/O port) or the microcomputer goes to a stop mode.
Note 3: This bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power dissipation mode
is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the
following setting is required:
(1) Set the CM07 bit to ì1î (Sub-clock select) or the CM21 bit of CM2 register to ì1î (Ring oscillator select) with the sub-cl ock
stably oscillating.
(2) Set the CM20 bit of CM2 register to ì0î (Oscillation stop, re-oscillation detection function disabled).
(3) Set the CM05 bit to ì1î (Stop).
Note 4: During external clock input, set to "0"(On).
Note 5: When CM05 bit is set to ì1, the XOUT pin goes ìHî. Furthermore, because the internal feedback resistor remains connected,
the XIN pin is pulled ìHî to the same level as XOUT via the feedback resistor.
Note 6: After setting the CM04 bit to ì1î (XCIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching
the CM07 bit from ì0î to ì1î (sub-clock).
Note 7: When entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator low power mode, the CM06
bit is set to ì1î (divide-by-8 mode).
Note 8: The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to ì1î (peripheral clock
turned off when in wait mode).
Note 9: To use a sub-clock, set this bit to ì1î. Also make sure ports P86 and P87 are directed for input, with no pull-ups.
Note 10: When the PM21 bit of PM2 register is set to ì1î (clock modification disable), writing to the CM02, CM05, and CM07 bits has
no effect.
Note 11: If the PM21 bit needs to be set to ì1î, set the CM07 bit to ì0î(main clock) before setting it.
Note 12: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to ì0î (oscillate).
(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(3) Set the CM11, CM21 and CM07 bits all to ì0î.
Note 13: When the CM21 bit = 0 (ring oscillaor turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1"
(divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
Note 14: To return from ring oscillator mode to high-speed or middle-speed mode set the CM06 and CM15 bits both to "1".
Figure 7.2. CM0 Register
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
After reset
0
0
0
00100000
2
Bit symbol
CM10
Bit
Function
RW
RW
name
All clock stop control bit
0 : Clock on
(Notes 4, 6)
1 : All clocks off (stop mode)
System clock select bit 1
(Notes 6, 7)
CM11
0 : Main clock
1 : PLL clock (Note 5)
RW
Reserved bit
Must set to “0”
RW
RW
(b4-b2)
CM15
X
IN-XOUT drive capacity
0 : LOW
1 : HIGH
select bit (Note 2)
b7 b6
Main clock division
select bits (Note 3)
0 0 : No division mode
CM16
CM17
RW
RW
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
speed mode, the CM15 bit is set to “1” (drive capability high).
Note 3: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
Note 4: If the CM10 bit is “1” (stop mode), XOUT goes “H” and the internal feedback resistor is disconnected. The XCIN and XCOUT
pins are placed in the high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit of CM2 register is
set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
Note 5: After setting the PLC07 bit in PLC0 register to “1” (PLL operation), wait until Tsu (PLL) elapses before setting the CM11 bit to
“1” (PLL clock).
Note 6: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM10, CM011 bits has no effect.
When the PM22 bit of PM2 register is set to “1” (watchdog timer count source is ring oscillator clock), writing to the CM10 bit
has no effect.
Note 7: Effective when CM07 bit is “0” and CM21 bit is “0” .
Figure 7.3. CM1 Register
Ring Oscillator Control register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ROCR
Address
025C16
After reset
00000101
0
0 0 0
2
Bit symbol
ROCR0
Bit name
Function
RW
RW
b1 b0
Frequency select bits
0 0 : f
0 1 : f
1
2
(ROC)
(ROC)
1 0 : not supported
1 1 : f3 (ROC)
ROCR1
RW
b3 b2
Divider select bits
0 0 : not supported
0 1 : divide by 2
1 0 : divide by 4
1 1 : divide by 8
ROCR2
ROCR3
RW
RW
(b7-b4)
Reserved bit
Must set to “0”
RW
Note 1 : Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Figure 7.4. ROCR Register
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
Oscillation stop detection register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
000C16
After reset
0X0000102
0
0
CM2
Bit symbol
CM20
Bit name
Function
RW
RW
0: Oscillation stop, re-oscillation
detection function disabled
1: Oscillation stop, re-oscillation
detection function enabled
Oscillation stop, re-
oscillation detection bit
(Notes 7, 9, 10, 11)
System clock select bit 2
(Notes 2, 3, 6, 8, 11, 12 )
0: Main clock or PLL clock
1: Ring oscillator clock
(Ring oscillator oscillating)
CM21
CM22
RW
RW
Oscillation stop, re-
oscillation detection flag
(Note 4)
0: Main clock stop,or re-oscillation
not detected
1: Main clock stop,or re-oscillation
detected
0: Main clock oscillating
1: Main clock not oscillating
X
IN monitor flag
RO
CM23
(Note 5)
Reserved bit
Must set to “0”
RW
(b5-b4)
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
(b6)
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation
detection interrupt
Operation select bit
(when an oscillation stop,
re-oscillation is detected)
(Note 11)
CM27
RW
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the
CM21 bit is automatically set to “1” (ring oscillator clock) if the main clock stop is detected.
Note 3: If the CM20 bit is “1” and the CM23 bit is “1” (main clock not oscillating), do not set the CM21 bit to “0”.
Note 4: This flag is set to “1” when the main clock is detected to have stopped or when the main clock is
detected to have restarted oscillating. When this flag changes state from “0” to “1”, an oscillation stop,
reoscillation restart detection interrupt is generated. Use this flag in an interrupt routine to discriminate
the causes of interrupts between the oscillation stop, reoscillation detection interrupts and the watchdog
timer interrupt. The flag is cleared to “0” by writing a “0” in a program. (Writing a “1” has no effect. Nor is
it cleared to “0” by an oscillation stop or an oscillation restart detection interrupt request acknowledged.)
If when the CM22 bit = 1 an oscillation stoppage or an oscillation restart is detected, no oscillation
stop, reoscillation restart detection interrupts are generated.
Note 5: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine
the main clock status.
Note 6: Effective when the CM07 bit of CM0 register is “0”.
Note 7: When the PM21 bit of PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no
effect.
Note 8: When the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1”
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is “1” (the CPU clock source is PLL
clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is “0”
under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop
detection; it is, therefore, necessary to set the CM21 bit to “1” (ring oscillator clock) inside the interrupt
routine.
Note 9: Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit
back to “1” (enable).
Note 10: Set the CM20 bit to “0” (disable) before setting the CM05 bit of CM0 register.
Note 11: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
Note 12: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off),
the CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).
Figure 7.5. CM2 Register
Rev.0.60 2004.02.01 page 35 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
Peripheral clock select register (Note)
Symbol
PCLKR
Address
025E16
When reset
00000011
b7 b6 b5 b4 b3 b2 b1 b0
2
0
0 0 0 0 0
Bit symbol
PCLK0
Bit name
Function
RW
RW
Timers A, B clock select bit
(Clock source for the
timers A, B, the timer S,
and the dead timer)
0 : f
1 : f
2
1
SI/O clock select bit
(Clock source for UART0
to UART2, SI/O3, SI/O4)
PCLK1
(b7-b2)
0 : f2SIO
1 : f1SIO
RW
RW
Reserved bit
Must set to “0”
Note: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Processeor mode register 2 (Note 1)
Symbol
PM2
Address
001E16
When reset
b7 b6 b5 b4 b3 b2 b1 b0
XXX00000
2
0
0
Bit symbol
PM20
Bit name
Function
RW
RW
Specifying wait when
accessing SFR during
PLL operation
0 : 2 wait
1 : 1 wait
(Note 2)
System clock protective bit
(Note 3,4)
PM21
PM22
0 : Clock is protected by PRCR
register
1 : Clock modification disabled
RW
RW
WDT count source
protective bit
0 : CPU clock is used for the
watchdog timer count source
1 : Ring oscillator clock is used
for the watchdog timer count
source
(Note 3,5)
Reserved bit
Must set to “0”
(b3)
RW
RW
P8
5
/NMI configuration bit
(Note 6,7)
0 : P8
5 function (NMI disable)
PM24
1 : NMI function
Nothing is assigned. When write, set to “0”. When read,
its content is indeterminate.
(b7-b5)
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Note 2: This bit can only be rewritten while the PLC07 bit is “0” (PLL turned off). Also, to select a 16MHz or
higher PLL clock or sytem clock, set this bit to “0” (2 wait).
Note 3: Once this bit is set to “1”, it cannot be cleared to “0” in a program.
Note 4: Setting the PM21 bit to “1” results in the following conditions:
• The BCLK is not halted by executing the WAIT instruction.
• Writting to the following bits has no effect.
CM02 bit of CM0 register
CM05 bit of CM0 register (main clock is not halted)
CM07 bit of CM0 register (CPU clock source does not change)
CM10 bit of CM1 register (stop mode is not entered)
CM11 bit of CM1 register (CPU clock source does not change)
CM20 bit of CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bit of PLC0 register (PLL frequency synthesizer setting do not change)
Note 5: Setting the PM22 bit to “1” results in the following conditions:
• The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source.
• The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode.
Note 6: For NMI function, the PM24 bit must be set to “1”(NMI function) in first instruction after rest. Once this bit is
set to “1”, it cannot be cleared to “0” in a program. When the PM24 bit is set to “1”, the P8
must be “0”.
5 direction register
Note 7: SD input is valid regardless of the PM24 setting.
Figure 7.6. PCLKR Register and PM2 Register
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
PLL control register 0 (Note 1, Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PLC0
Address
001C16
After reset
0001 X0102
0 0
1
Bit
Bit name
Function
RW
RW
symbol
b2 b1b0
PLL multiplying factor
select bit (Note 3)
PLC00
0 0 0: Do not set
0 0 1: Multiply by 2
0 1 0: Multiply by 4
0 1 1:
PLC01
PLC02
RW
RW
1 0 0:
1 0 1:
1 1 0:
1 1 1:
Do not set
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b3)
(b4)
RW
RW
Reserved bit
Reserved bit
Must set to "1"
Must set to "0"
(b6-b5)
0: PLL Off
1: PLL On
Operation enable bit
RW
PLC07
(Note 4)
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Note 2: When the PM21 bit of PM2 register is "1" (clock modification disable), writing to this register has no effect.
Note 3: These three bits can only be modified when the PLC07 bit = "0" (PLL turned off). The value once written to this bit
cannot be modified.
Note 4: Before setting this bit to "1" , set the CM07 bit to "0" (main clock), set the CM17 to CM16 bits to "00
(main clock undivided mode), and set the CM06 bit to "0" (CM16 and CM17 bits enable).
2"
Figure 7.7. PLC0 Register
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
The following describes the clocks generated by the clock generation circuit.
7.1 Main Clock
The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for
the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a
resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor,
which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power
consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally
generated clock to the XIN pin. Figure 7.1.1 shows the examples of main clock connection circuit.
The power consumption in the chip can be reduced by setting the CM05 bit of CM0 register to “1” (main
clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or ring
oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains
on, XIN is pulled “H” to XOUT via the feedback resistor.
During stop mode, all clocks including the main clock are turned off. Refer to “power control”.
If the main clock is not used, it is recommended to connect the XIN pin to VCC to reduce power consump-
tion during reset.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
IN
XOUT
X
IN
XOUT
Open
(Note)
R
d
Externally derived clock
V
CC
CIN
C
OUT
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 7.1.1. Examples of Main Clock Connection Circuit
Rev.0.60 2004.02.01 page 38 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7.2 Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for
the CPU clock, as well as the timer A and timer B count sources.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and
XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the
oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub
clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin.
Figure 7.2.1 shows the examples of sub clock connection circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscilla-
tor circuit.
To use the sub clock for the CPU clock, set the CM07 bit of CM0 register to “1 ” (sub clock) after the sub
clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to “power control”.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
CIN
XCOUT
X
CIN
XCOUT
Open
(Note)
R
Cd
Externally derived clock
CCIN
CCOUT
V
CC
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Figure 7.2.1. Examples of Sub Clock Connection Circuit
Rev.0.60 2004.02.01 page 39 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7.3 Ring Oscillator Clock
This clock is supplied by a variable ring oscillator. This clock is used as the clock source for the CPU and
peripheral function clocks. In addition, if the PM22 bit of PM2 register is “1” (ring oscillator clock for the
watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to “10.
Watchdog Timer • Count source protective mode”).
After reset, the ring oscillator clock divided by 16 is used for the CPU clock. It can also be turned on by
setting the CM21 bit of CM2 register to “1” (ring oscillator clock), and is used as the clock source for the
CPU and peripheral function clocks. If the main clock stops oscillating when the CM20 bit of CM2 register
is “1” (oscillation stop, re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop,
re-oscillation detection interrupt), the ring oscillator automatically starts operating, supplying the neces-
sary clock for the microcomputer.
7.4 PLL Clock
The PLL clock is generated from the main clock by a PLL frequency synthesizer. This clock is used as the
clock source for the CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL
frequency synthesizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is
used as the clock source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the
CM11 bit in the CM1 register to “1”.
Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0”
(PLL stops). Figure 7.4.1 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits PLC0 register
(However, 10 MHz ≤ PLL clock frequency ≤ 20 MHz)
The PLC02 to PLC00 bits can be set only once after reset. Table 7.4.1 shows the example for setting PLL
clock frequencies.
Table 7.4.1. Example for Setting PLL Clock Frequencies
X
IN
PLL clock
(MHz)(Note)
PLC02
PLC01
PLC00
Multiplying factor
(MHz)
10
5
0
0
0
1
1
0
2
4
20
Note: 10MHz ≤ PLL clock frequency ≤ 20MHz.
Rev.0.60 2004.02.01 page 40 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
START
Set the CM07 bit to “0” (main clock), the CM17 to CM16
bits to “002”(main clock undivided), and the CM06 bit to “0”
(CM16 and CM17 bits enabled). (Note)
Set the PLC02 to PLC00 bits (multiplying factor).
(To select a 16 MHz or higher PLL clock)
Set the PM20 bit to “0” (2-wait states).
Set the PLC07 bit to “1” (PLL operation).
Wait until the PLL clock becomes stable (tsu(PLL)).
Set the CM11 bit to “1” (PLL clock for the CPU clock source).
END
Note : PLL operation mode can be entered from high speed mode.
Figure 7.4.1. Procedure to Use PLL Clock as CPU Clock Source
Rev.0.60 2004.02.01 page 41 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7.5 CPU Clock and Peripheral Function Clock
The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the periph-
eral functions.
7.5.1 CPU Clock
This is the operating clock for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, ring oscillator clock or
the PLL clock.
If the main clock or ring oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in
CM0 register and the CM17 to CM16 bits in CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0”
and the CM17 to CM16 bits to “002” (undivided).
After reset, the ring oscillator clock divided by 16 provides the CPU clock.
Note that when entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator
low power dissipation mode, or when the CM05 bit of CM0 register is set to “1” (main clock turned off) in
low-speed mode, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode).
7.5.2 Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)
These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or ring oscillator clock by
dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial I/O.
The fAD clock is produced from the main clock, PLL clock or ring oscillator clock, and is used for the A-D
converter.
When the WAIT instruction is executed after setting the CM02 bit of CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO and fAD clocks are turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can only be used
when the sub clock is on.
Rev.0.60 2004.02.01 page 42 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7.6 Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes
are referred to as normal operation mode here.
7.6.1 Normal Operation Mode
Normal operation mode is further classified into seven modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU
clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are
turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a
sufficient wait time in a program until it becomes oscillating stably.
Note that operation modes cannot be changed directly from low speed or low power dissipation mode to
ring oscillator or ring oscillator low power dissipation mode. Nor can operation modes be changed directly
from ring oscillator or ring oscillator low power dissipation mode to low speed or low power dissipation
mode. When the CPU clock source is changed from the ring oscillator to the main clock, change the
operation mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the
CM06 bit of CM0 register was set to “1”) in the ring oscillator mode.
7.6.1.1 High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
7.6.1.2 PLL Operation Mode
The main clock multiplied by 2 or 4 provides the PLL clock, and this PLL clock serves as the CPU
clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. PLL operation
mode can be entered from high speed mode. If PLL operation mode is to be changed to wait or stop
mode, first go to high speed mode before changing.
7.6.1.3 Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used
as the count source for timers A and B.
7.6.1.4 Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit is set to “0” (ring oscillator turned off), and the ring oscillator clock is
used when the CM21 bit is set to “1” (ring oscillator oscillating).
The fC32 clock can be used as the count source for timers A and B.
7.6.1.5 Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides
the CPU clock. The fC32 clock can be used as the count source for timers A and B. Peripheral function
clock can use only fC32.
Simultaneously when this mode is selected, the CM06 bit of CM0 register becomes “1” (divided by 8
mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divided by 8) mode is to be selected when the main clock is operated next.
Rev.0.60 2004.02.01 page 43 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7.6.1.6 Ring Oscillator Mode
The selected ring oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The
ring oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on,
fC32 can be used as the count source for timers A and B. The ring oscillator frequency can be selected
using the ring oscillator control register (ROCR:025C16) bits 0 to 3. See Figure.7.4 for details. When
the operation mode is returned to the high and medium speed modes, set the CM06 bit to “1” (divided
by 8 mode).
7.6.1.7 Ring Oscillator Low Power Dissipation Mode
The main clock is turned off after being placed in ring oscillator mode. The CPU clock can be selected
as in the ring oscillator mode. The ring oscillator clock is the clock source for the peripheral function
clocks. If the sub clock is on, fC32 can be used as the count source for timers A and B.
Table 7.6.1.1. Setting Clock Related Bit and Modes
CM2 register
CM1 register
CM11 CM17, CM16
CM0 register
Modes
CM21
CM07
CM06
CM05
CM04
PLL operation mode
High-speed mode
0
0
0
0
0
0
1
0
0
0
0
0
00
00
01
10
2
2
2
2
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Medium-
speed
mode
divided by 2
divided by 4
divided by 8
divided by 16
112
Low-speed mode
1
1
Low power dissipation mode
1(Note 1) 1(Note 1)
divided by 1
1
1
1
1
1
1
00
01
10
2
0
0
0
0
0
0
1
Ring
oscillator
mode
(Note 3)
divided by 2
2
0
divided by 4
2
0
divided by 8
1
0
0
divided by 16
112
Ring oscillator low power
dissipation mode
(Note 2)
(Note 2)
Note 1: When the CM05 bit is set to ì1î (main clock turned off) in low-speed mode, the mode goes to low power
dissipation mode and CM06 bit is set to ì1î (divided by 8 mode) simultaneously.
Note 2: The divide-by-n value can be selected the same way as in ring oscillator mode.
Note 3: Variable ring oscillator frequency can be any of those described in the section "Variable Ring Oscillator Mode".
7.6.2 Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. However, if the PM22 bit of PM2 register is “1” (ring oscillator clock for the watchdog
timer count source), the watchdog timer remains active. Because the main clock, sub clock, ring oscillator
clock and PLL clock all are on, the peripheral functions using these clocks keep operating.
7.6.2.1 Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,
f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power consumption reduced
that much. However, fC32 remains on.
7.6.2.2 Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
When the CM11 bit = “1” (CPU clock source is the PLL clock), be sure to clear the CM11 bit to “0”
(CPU clock source is the main clock) before going to wait mode. The power consumption of the chip
can be reduced by clearing the PLC07 bit to “0” (PLL stops).
7.6.2.3 Pin Status During Wait Mode
The I/O port pins retain their status held just prior to wait mode.
Rev.0.60 2004.02.01 page 44 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7.6.2.4 Exiting Wait Mode
______
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral func-
tion interrupt.
______
If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before execut-
ing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function
clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait
mode. If CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral func-
tions using the peripheral function clocks stop operating, so that only the peripheral functions clocked
by external signals can be used to exit wait mode.
Table 7.6.2.4.1 lists the interrupts to exit wait mode.
Table 7.6.2.4.1. Interrupts to Exit Wait Mode
Interrupt
CM02=0
CM02=1
NMI interrupt
Serial I/O interrupt
Can be used
Can be used
Can be used when operating
with internal or external clock
Can be used when operating
with external clock
Multi-Master I2C
interrupt
Can be used
(Do not use)
key input interrupt
Can be used
Can be used
(Do not use)
A-D conversion
interrupt
Can be used in one-shot mode
or single sweep mode
Timer A interrupt
Timer B interrupt
Can be used in all modes
Can be used in event counter
mode or when the count
source is fC32
INT interrupt
Can be used
Can be used
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph
eral function interrupt to be used to exit wait mode.
Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0
bits to “0002” (interrupt disable).
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit wait mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt routine is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU
clock that was on when the WAIT instruction was executed.
Rev.0.60 2004.02.01 page 45 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7.6.3 Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the internal
RAM is retained. When applying 2.7 or less voltage to Vcc pin, make sure Vcc≥VRAM.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
______
• NMI interrupt
• Key interrupt
______
• INT interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is selected)
•
Voltage down detection interrupt (refer to “voltage down detection interrupt” for an operating condition)
7.6.3.1 Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode) and the
CM15 bit of CM10 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit to “0” (oscillation stop, re-oscillation detection function
disable).
Also, if the CM11 bit is “1” (PLL clock for the CPU clock source), set the CM11 bit to “0” (main clock for
the CPU clock source) and the PLC07 bit to “0” (PLL turned off) before entering stop mode.
7.6.3.2 Pin Status during Stop Mode
The I/O pins retain their status held just prior to entering stop mode.
7.6.3.3 Exiting Stop Mode
______
The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral func-
tion interrupt.
______
If the microcomputer is to be moved out of stop mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the
CM10 bit to “1”.
If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the
following before setting the CM10 bit to “1”.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph-
eral function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0
bits to “0002”.
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit stop mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt service routine is executed.
______
Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is
determined by the CPU clock that was on when the microcomputer was placed into stop mode as
follows:
If the CPU clock before entering stop mode was derived from the sub clock: sub clock
If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8
If the CPU clock before entering stop mode was derived from the ring oscillator clock: ring oscillator
clock divide-by-8
Rev.0.60 2004.02.01 page 46 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
Figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. Figure
7.6.1.1 shows the state transition in normal operation mode.
Table 7.6.1 shows a state transition matrix describing allowed transition and setting. The vertical line
shows current state and horizontal line shows state after transition.
Normaloperationmode
CPU operationstopped
Alloscillatorsstopped
WAIT
instruction
CM 10=1
Medium-speed mode
(divided-by-8mode)
Stopmode
Waitmode
Interrupt
Interrupt
Interrupt
CM07=0
CM06=1
CM05=0
CM11=0
CM10=1
(Note5)
WAIT
instruction
High-speed,medium-
speed mode
Stopmode
Waitmode
Interrupt
CM 10=1
CM 10=1
When
Notes1,2
low power
dissipation
mode
When
low-
speed
mode
PLLoperation
mode
WAIT
instruction
Low-speed,low power
dissipationmode
Stopmode
Stopmode
Waitmode
Waitmode
Interrupt
Interrupt
CM 10=1
WAIT
instruction
Ringoscillatorlow power
dissipationmode
Interrupt
Interrupt
CM21=1
CM21=0
Ringoscillatormode
(selectablefrequency)
WAIT
CM10=1
instruction
Stopmode
Waitmode
Interrupt
Interrupt
(Note4)
Ringoscillator
mode(f(ROC)/16)
2
Reset
Note 1: Do not go directly from PLL operation mode to wait or stop mode.
Note 2: PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
Note 3: When the PM21 bit = 0 (system clock protective function unused).
Note 4: The ring oscillator clock divided by 8 provides the CPU clock.
Note 5: Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21 = 1 (ring oscillator turned off).
Note 6: Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to "0" (oscillation stop and oscillation restart detection
function disabled).
Figure 7.6.1. State Transition to Stop Mode and Wait Mode
Rev.0.60 2004.02.01 page 47 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
Main clock oscillation
Ring oscillator clock
oscillation
Ring oscillator low power
dissipation mode
Middle-speed mode
(divide by 4)
Middle-speed mode Middle-speed mode
PLL operation mode
Middle-speed mode
(divide by 2)
Ring oscillator mode
PLC07=1
CM11=1
(Note 6)
High-speed mode
(divide by 8)
CPU clock: f(XIN)/8
CM07=0
(divide by 16)
CPU clock: f(PLL)
CM07=0
CPU clock
CPU clock
CM21=0
(Note 8)
CM05=0
CPU clock: f(XIN
)
CPU clock: f(XIN)/2
CPU clock: f(XIN)/4
CPU clock: f(XIN)/16
CM07=0
f(Ring)
f(Ring)
CM07=0
CM06=0
CM17=0
CM16=0
CM07=0
CM06=0
CM17=0
CM16=1
CM07=0
CM06=0
CM17=1
CM16=0
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM06=0
CM06=0
CM17=1
CM16=1
CM17=0
PLC07=0
CM11=0
(Note 7)
CM05=1
(Note 1)
CM16=0
CM06=1
CM21=1
CM04=1
CM04=0
CM04=1
CM04=0
CM04=1
CM04=0
CM04=1
CM04=0
Ring oscillator
low power
dissipation mode
PLL operation
mode
Ring oscillator
mode
Middle-speed mode
(divide by 4)
Middle-speed mode Middle-speed mode
Middle-speed mode
(divide by 2)
High-speed mode
PLC07=1
CM11=1
(Note 6)
(divide by 8)
(divide by 16)
CM21=0
(Note 8)
CPU clock
CPU clock
CPU clock: f(PLL)
CM07=0
CM05=0
CPU clock: f(XIN
)
CPU clock: f(XIN)/2
CM07=0
CPU clock: f(XIN)/4
CM07=0
CPU clock: f(XIN)/8
CM07=0
CPU clock: f(XIN)/16
CM07=0
f(Ring)
f(Ring)
CM07=0
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM06=0
CM06=0
CM06=0
CM06=0
CM17=1
CM16=0
CM06=0
CM17=1
CM16=1
CM17=0
PLC07=0
CM11=0
(Note 7)
CM17=0
CM16=0
CM17=0
CM16=1
CM16=0
CM06=1
CM21=1
CM05=1
(Note 1)
CM07=1
(Note 3)
CM07=0
(Note 2, Note 4)
Low-speed mode
Low-speed mode
CM21=0
CM21=1
CPU clock: f(XCIN
CM07=0
)
CPU clock: f(XCIN
)
CM07=0
CM05=1
(Note 1, Note 9)
CM05=0
Low power dissipation mode
CPU clock: f(XCIN
)
CM07=0
CM06=1
CM15=1
Sub clock oscillation
Notes:
1: Avoid making a transition when the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2: Wait for td(M-L) or the main clock oscillation stabilization time whichever is longer before switching over.
3: Switch clock after oscillation of sub-clock is sufficiently stable.
4: Change CM17 and CM16 before changing CM06.
5: Transit in accordance with arrow.
6: PLL operation mode can only be entered from high speed mode. Also, wait until the PLL clock is sufficiently stable before changing operation modes.
To select a 16 MHz or higher PLL clock, set the PM20 bit to “0” (SFR accessed with two wait states) before setting PLC07 to “1” (PLL operation).
7: PLL operation mode can only be changed to high speed mode. If the PM20 bit = 0 (SFR accessed with two wait states), set PLC07 to “0” (PLL turned off)
before setting the PM20 bit to “1” (SFR accessed with one wait state).
8: Set the CM06 bit to “1” (division by 8 mode) before changing back the operation mode from ring oscillator mode to high- or middle-speed mode.
9: When the CM21 bit = 0 (ring oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).
Figure 7.6.1.1. State Transition in Normal Mode
Rev.0.60 2004.02.01 page 48 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
Table 7.6.1. Allowed Transition and Setting
State after transition
Ring oscillator
low power
dissipation mode
Ring oscillator
mode
PLL operation
mode
High-speed mode,
middle-speed mode
2
Low power
dissipation mode
Low-speed mode
Stop mode
Wait mode
2
High-speed mode,
middle-speed mode
7
3
1
1
1
(9)
(13)
(16)
(16)
(16)
8
--
(15)
--
(17)
(17)
(17)
--
See Table A
2
Low-speed mode
1, 6
(11)
(8)
--
--
--
--
--
--
--
Low power dissipation
mode
(10)
--
--
--
2
PLL operation mode
3
(12)
--
--
--
Ring oscillator mode
4
1
1
1
(14)
8
(11)
(16)
--
--
--
--
--
(17)
(17)
--
See Table A
(10)
Ring oscillator
low power dissipation
mode
(16)
--
8
--
--
--
See Table A
Stop mode
5
5
5
(18)
(18)
(18)
(18)
(18)
(18)
(18)
Wait mode
(18)
(18)
(18)
Notes:
--: Cannot transit
1. Avoid making a transition when the CM21 bit is set to “1” (oscillation stop, re-oscillation detection function enabled).
Set the CM21 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Ring oscillator clock oscillates and stops in low-speed mode. In this mode, the ring oscillator can be used as peripheral function clock.
Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed mode.
4. Set the CM06 bit to “1” (division by 8 mode) before transiting from ring oscillator mode to high- or middle-speed mode.
5. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).
6. If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1” (division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.
Sub clock oscillating
Sub clock turned off
Divided Divided
Divided
by 2
Divided
by 2
Divided
by 8
Divided
by 4
Divided
by 16
No
division
Divided
by 4
No
division
by 8
by 16
(4)
(5)
(5)
(7)
(6)
(1)
--
--
--
--
--
--
--
--
No division
Divided by 2
(3)
(3)
(3)
(3)
(2)
--
(7)
(7)
(6)
(6)
(6)
(1)
--
(4)
(4)
(4)
--
--
(1)
--
--
--
Divided by 4
Divided by 8
Divided by 16
(5)
(5)
--
--
--
(1)
--
--
(7)
--
--
--
--
(1)
(6)
(6)
(6)
(6)
--
--
(4)
(5)
(5)
(7)
(7)
(7)
No division
Divided by 2
(2)
--
--
--
(3)
(3)
(3)
(3)
Divided by 4
Divided by 8
Divided by 16
--
(2)
--
--
--
(4)
(4)
(4)
--
--
(2)
--
--
(5)
(5)
--
--
--
(2)
(7)
--: Cannot transit
9. ( ) : setting method. Refer to following table.
Setting
Operation
CM04 = 0
CM04 = 1
Sub clock turned off
(1)
(2)
CM04, CM05, CM06, CM07 : bit of CM0 register
CM10, CM11, CM16, CM17 : bit of CM1 register
Sub clock oscillating
CM20, CM21
PLC07
: bit of CM2 register
: bit of PLC0 register
CM06 = 0,
CM17 = 0 , CM16 = 0
CM06 = 0,
CM17 = 0 , CM16 = 1
(3)
CPU clock no division mode
CPU clock division by 2 mode
(4)
CM06 = 0,
CM17 = 1 , CM16 = 0
CPU clock division by 4 mode
(5)
CM06 = 0,
CM17 = 1 , CM16 = 1
CPU clock division by 16 mode
CPU clock division by 8 mode
(6)
CM06 = 1
CM07 = 0
CM07 = 1
CM05 = 0
CM05 = 1
(7)
Main clock, PLL clock,
or ring oscillator clock selected
(8)
Sub clock selected
(9)
Main clock oscillating
Main clock turned off
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
PLC07 = 0,
CM11 = 0
PLC07 = 1,
CM11 = 1
Main clock selected
PLL clock selected
CM21 = 0
CM21 = 1
Main clock or PLL clock selected
Ring oscillator clock selected
Transition to stop mode
Transition to wait mode
Exit stop mode or wait mode
CM10 = 1
wait instruction
Hardware interrupt
Rev.0.60 2004.02.01 page 49 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7.7 System Clock Protective Function
When the main clock is selected for the CPU clock source, this function protects the clock from modifica-
tions in order to prevent the CPU clock from becoming halted by run-away.
If the PM21 bit of PM2 register is set to “1” (clock modification disabled), the following bits are protected
against writes:
• CM02, CM05, and CM07 bits in CM0 register
• CM10, CM11 bits in CM1 register
• CM20 bit in CM2 register
• All bits in PLC0 register
Before the system clock protective function can be used, the following register settings must be made while
the CM05 bit of CM0 register is “0” (main clock oscillating) and CM07 bit is “0” (main clock selected for the
CPU clock source):
(1) Set the PRC1 bit of PRCR register to “1” (enable writes to PM2 register).
(2) Set the PM21 bit of PM2 register to “1” (disable clock modification).
(3) Set the PRC1 bit of PRCR register to “0” (disable writes to PM2 register).
Do not execute the WAIT instruction when the PM21 bit is “1”.
7.8 Oscillation Stop and Re-oscillation Detect Function
The oscillation stop and re-oscillation detect function allows the detection of main clock oscillation stop and
reoscillation. At oscillation stop or re-oscillation detection, reset or oscillation stop, re-oscillation detection
interrupt are generated. Depending on the CM27 bit of CM2 register. The oscillation stop detection function
can be enabled and disabled by the CM20 bit in the CM2 register. Table 7.8.1 lists a specification overview
of the oscillation stop and re-oscillation detect function.
Table 7.8.1. Specification Overview of Oscillation Stop and Re-oscillation Detect Function
Item
Specification
Oscillation stop detectable clock and
frequency bandwidth
f(XIN) ≥ 2 MHz
Enabling condition for oscillation stop, Set CM20 bit to “1”(enable)
re-oscillation detection function
Operation at oscillation stop,
re-oscillation detection
•Reset occurs (when CM27 bit =0)
•Oscillation stop, re-oscillation detection interrupt occurs(when CM27 bit =1)
Rev.0.60 2004.02.01 page 50 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)
When main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection
function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to “SFR”,
“Reset”).
This status is reset with hardware reset 1 or hardware reset 2. Also, even when re-oscillation is detected,
the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (During
main clock stop, do not set the CM20 bit to “1” and the CM27 bit to “0”.)
7.8.2 Operation When CM27 bit = 1 (Oscillation Stop and Re-oscillation Detect Interrupt)
When the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop and
re-oscillation detect function enabled), the system is placed in the following state if the main clock comes
to a halt:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• The ring oscillator starts oscillation, and the ring oscillator clock becomes the CPU clock and clock
source for peripheral functions in place of the main clock.
• CM21 bit = 1 (ring oscillator clock for CPU clock source)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
When the PLL clock corresponds to the CPU clock source and the CM20 bit is “1”, the system is placed
in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1”
(ring oscillator clock) inside the interrupt routine.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
• CM21 bit remains unchanged
When the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from the
stop condition:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock re-oscillation detected)
• CM23 bit = 0 (main clock oscillation)
• CM21 bit remains unchanged
Rev.0.60 2004.02.01 page 51 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
7. Clock Generation Circuit
7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function
• The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter-
rupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read
the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
• Where the main clock re-oscillated after oscillation stop, return the main clock to the CPU clock and
peripheral function clock source in the program. Figure 7.8.3.1 shows the procedure for switching the
clock source from the ring oscillator to the main clock.
• Simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the CM22 bit be-
comes “1”. When the CM22 bit is set at “1”, oscillation stop, re-oscillation detection interrupt are dis-
abled. By setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection interrupt
are enabled.
• If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscilla-
tion detection interrupt request is generated. At the same time, the ring oscillator starts oscillating. In
this case, although the CPU clock is derived from the sub clock as it was before the interrupt occurred,
the peripheral function clocks now are derived from the ring oscillator clock.
• To enter wait mode while using the oscillation stop, re-oscillation detection function, set the CM02 bit to
“0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop, re-oscillation detection function is provided in preparation for main clock stop
due to external factors, set the CM20 bit to “0” (Oscillation stop, re-oscillation detection function dis-
abled) where the main clock is stopped or oscillated in the program, that is where the stop mode is
selected or the CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit
to “0”.
Main clock switch
Inspect the CM23 bit
1(Main clock stop)
0(Main clock oscillation)
Do this check a number of times
The main clock is confirmed to be active a number of times.
Set the CM22 bit to 0 (main clock stop,
re-oscillation not detected).
Set the CM21 bit to 0
(main clock for the CPU clock source)(Note)
All of CM21-23 are the CM2 register bits
End
Note: If the clock source for CPU clock is to be changed to PLL clock, set to PLL operation
mode after set to high-speed mode.
Figure 7.8.3.1. Procedure to Switch Clock Source From Ring Oscillator to Main Clock
Rev.0.60 2004.02.01 page 52 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
8. Protection
8. Protection
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by
the PRCR register.
• Registers protected by PRC0 bit: CM0, CM1, CM2, PLC0, ROCR and PCLKR registers
• Registers protected by PRC1 bit: PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers
• Registers protected by PRC2 bit: PD9 , PACR and S4C registers
• Registers protected by PRC3 bit: VCR2 and D4INT registers
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction. The PRC0, PRC1 and PRC3 bits are not automati-
cally cleared to “0” by writing to any address. They can only be cleared in a program.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
After reset
XX000000
0
0
2
Bit symbol
PRC0
Bit name
Function
RW
RW
Enable write to CM0, CM1, CM2,
ROCR, PLC0 and PCLKR registers
Protect bit 0
0 : Write protected
1 : Write enabled
Enable write to PM0, PM1, PM2,
TB2SC, INVC0 and INVC1
registers
PRC1
Protect bit 1
RW
RW
0 : Write protected
1 : Write enabled
Enable write to PD9, PACR
and S4C registers
PRC2
PRC3
Protect bit 2
Protect bit 3
Reserved bit
0 : Write protected
1 : Write enabled
Enable write to VCR2 and D4INT
registers
RW
RW
0 : Write protected
1 : Write enabled
Must set to 0
(b5-b4)
(b7-b6)
Nothing is assigned. When write, set to 0 . When read, its
content is indeterminate.
Note: The PRC2 bit is set to 0 by writing to any address after setting it to 1 . Other bits are not set to 0
by writing to any address, and must therefore be set in a program.
Figure 8.1. PRCR Register
Rev.0.60 2004.02.01 page 53 of N
REJ09B0047-0060Z
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
9. Interrupts
9.1 Type of Interrupts
Figure 9.1.1 shows types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
Software
(Non-maskable interrupt)
INT instruction
_______
NMI
________
Interrupt
DBC (Note 2)
Watchdog timer
Special
Oscillation stop and re-oscillation
detection
(Non-maskable interrupt)
Voltage down detection
Single step (Note 2)
Address match
Hardware
Peripheral function (Note 1)
(Maskable interrupt)
Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions.
Note 2: Do not normally use this interrupt because it is provided exclusively for use by development
support tools.
Figure 9.1.1. Interrupts
• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Rev.0.60 2004.02.01 page 54 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
9.1.1 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-
maskable interrupts.
9.1.1.1 Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
9.1.1.2 Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the
operation resulted in an overflow). The following are instructions whose O flag changes by arith-
metic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
9.1.1.3 BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
9.1.1.4 INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to
63 can be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be
executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does
not change state during instruction execution, and the SP then selected is used.
Rev.0.60 2004.02.01 page 55 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
9.1.2 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function inter-
rupts.
9.1.2.1 Special Interrupts
Special interrupts are non-maskable interrupts.
_______
9.1.2.1.1 NMI Interrupt
_______
_______
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details
_______
about the NMI interrupt, refer to the section "NMI interrupt".
________
9.1.2.1.2 DBC Interrupt
This interrupt is exclusively for debugger, do not use in any other circumstances.
9.1.2.1.3 Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer".
9.1.2.1.4 Oscillation Stop and Re-oscillation Detection Interrupt
Generated by the oscillation stop and re-oscillation detection function. For details about the oscilla-
tion stop and re-oscillation detection function, refer to the section "clock generating circuit".
9.1.2.1.5 Voltage Down Detection Interrupt
Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to the
section "voltage detection circuit".
9.1.2.1.6 Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
9.1.2.1.7 Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 or RMAD1 register, if the corresponding enable bit (AIER register’s AIER0
or AIER1bit) is set to “1”. For details about the address match interrupt, refer to the section “address
match interrupt”.
9.1.2.2 Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in “Table 1.11.2.
Relocatable Vector Tables”. For details about the peripheral functions, refer to the description of each
peripheral function in this manual.
Rev.0.60 2004.02.01 page 56 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
9.2 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 9.2.1 shows the interrupt vector.
MSB
LSB
Low address
Mid address
Vector address (L)
Vector address (H)
0 0 0 0
0 0 0 0
High address
0 0 0 0
Figure 9.2.1. Interrupt Vector
9.2.1 Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 9.2.1.1 lists
the fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of
fixed vectors are used by the ID code check function. For details, refer to the section "flash memory
rewrite disabling function".
Table 9.2.1.1. Fixed Vector Tables
Interrupt source
Vector table addresses
Address (L) to address (H)
Remarks
Reference
Undefined instruction FFFDC16 to FFFDF16
Interrupt on UND instruction
M16C/60, M16C/20
serise software
maual
Overflow
FFFE016 to FFFE316
FFFE416 to FFFE716
Interrupt on INTO instruction
If the contents of address
FFFE716 is FF16, program ex-
ecution starts from the address
shown by the vector in the
relocatable vector table.
BRK instruction
Address match
Single step (Note)
Watchdog timer
Oscillation stop and
re-oscillation detection
Voltage down
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
Address match interrupt
Watchdog timer
Clock generating circuit
Voltage detection circuit
detection
________
DBC (Note)
FFFF416 to FFFF716
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
_______
_______
NMI
NMI interrupt
Reset
Reset
Note: Do not normally use this interrupt because it is provided exclusively for use by development sup-
port tools.
Rev.0.60 2004.02.01 page 57 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
9.2.2 Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector
table area. Table 9.2.2.1 lists the relocatable vector tables. Setting an even address in the INTB
register results in the interrupt sequence being executed faster than in the case of odd addresses.
Table 9.2.2.1. Relocatable Vector Tables
Vector address (Note 1)
Address (L) to address (H)
Software interrupt
number
Reference
Interrupt source
(Note 5)
+0 to +3 (000016 to 000316
)
M16C/60, M16C/20
series software
manual
BRK instruction
0
1 to 3
4
(Reserved)
+16 to +19 (001016 to 001316
+20 to +23 (001416 to 001716
)
)
INT interrupt
Timer S
INT3
5
ICOC interrupt 0
(
Note 4
)
6
7
Timer S
+24 to +27 (001816 to 001B16
)
ICOC interrupt 1, I2C-BUS interface
ICOC base timer, SCL/SDA
Multi-Master I2C-BUS
interface
(Note 4
)
+28 to +31 (001C16 to 001F16
)
+32 to +35 (002016 to 002316
+36 to +39 (002416 to 002716
)
(Note 2)
SI/O3, INT4 (Note 2)
8
SI/O4, INT5
INT interrupt
Serial I/O
9
)
+40 to +43 (002816 to 002B16
)
UART 2 bus collision detection (Note 6)
DMA0
10
11
Serial I/O
DMAC
+44 to +47 (002C16 to 002F16
)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
+48 to +51 (003016 to 003316
)
DMA1
Key input interrupt
A-D convertor
+52 to +55 (003416 to 003716
)
Key input interrupt
A-D
+56 to +59 (003816 to 003B16
)
UART2 transmit, NACK2 (Note 3)
UART2 receive, ACK2 (Note 3)
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
+60 to +63 (003C16 to 003F16)
+64 to +67 (004016 to 004316
+68 to +71 (004416 to 004716
+72 to +75 (004816 to 004B16
)
)
Serial I/O
)
+76 to +79 (004C16 to 004F16
)
+80 to +83 (005016 to 005316
+84 to +87 (005416 to 005716
+88 to +91 (005816 to 005B16
)
)
)
Timer A1
+92 to +95 (005C16 to 005F16
+96 to +99 (006016 to 006316
+100 to +103 (006416 to 006716
+104 to +107 (006816 to 006B16
+108 to +111 (006C16 to 006F16
)
Timer A2
Timer A3
)
Timer
)
Timer A4
)
Timer B0
)
Timer B1
Timer B2
+112 to +115 (007016 to 007316
+116 to +119 (007416 to 007716
+120 to +123 (007816 to 007B16
)
)
INT0
INT1
)
INT interrupt
+124 to +127 (007C16 to 007F16
)
INT2
32
to
+128 to +131 (008016 to 008316
to
+252 to +255 (00FC16 to 00FF16
)
M16C/60, M16C/20
series software
manual
Software interrupt
(Note 5)
63
)
Note 1: Address relative to address in INTB.
Note 2: Use the IFSR register's IFSR6 and IFSR7 bits to select.
Note 3: During I2C Bus mode, NACK and ACK interrupts comprise the interrupt source.
Note 4: Use the IFSR2A register’s IFSR26 and IFSR27 bits to select.
Note 5: These interrupts cannot be disabled using the I flag.
Note 6: Bus collision detection : During IE Bus mode, this bus collision detection constitutes the cause of an interrupt.
During I2C Bus mode, however, a start condition or a stop condition detection constitutes
the cause of an interrupt.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
9.3 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in
which order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each
interrupt control register.
Figure 9.3.1 shows the interrupt control registers.
Also, the following interrupts share a vector and an interrupt control register.
________
•INT4 and SIO3
________
•INT5 and SIO4
•ICOC base timer and SCL/SDA
2
•ICOC interrupt 1 and I C-BUS interface
An interrupt request is set by the IFSR6, IFSR7 bits in the IFSR register and the IFSR26 and IFSR27 bits
in the IFSR2A register. Figure 9.3.2 shows the IFSR, IFSR2A registers.
Rev.0.60 2004.02.01 page 59 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
Interrupt control register (Note 2)
Symbol
ICOC0IC
ICOC1IC, IICIC (Note 3)
BTIC, SCLDAIC (Note 3)
BCNIC
DM0IC, DM1IC
KUPIC
Address
004516
004616
004716
004A16
004B16, 004C16
004D16
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
005A16 to 005C16
After reset
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
2
2
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Bit symbol
Bit name
Function
Interrupt priority level
select bit
ILVL0
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1
RW
RW
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
RW
(Note 1)
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
(b7-b4)
Note 1: This bit can only be reset by writing “0” (Do not write “1”).
Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see the “precautions for interrupts” of the Usage Notes Reference Book.
Note 3: Use the IFSR2A register to select.
Symbol
INT3IC
S4IC/INT5IC
S3IC/INT4IC
INT0IC to INT2IC
Address
004416
004816
004916
After reset
XX00X000
XX00X000
XX00X000
2
b7 b6 b5 b4 b3 b2 b1 b0
2
2
2
0
005D16 to 005F16 XX00X000
Bit symbol
ILVL0
Bit name
Function
RW
RW
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1
ILVL2
RW
RW
IR
Interrupt request bit
Polarity select bit
0: Interrupt not requested
1: Interrupt requested
RW
(Note 1)
POL
0 : Selects falling edge (Notes 3, 4)
1 : Selects rising edge
RW
RW
Reserved bit
Must always be set to “0”
(b5)
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
RW
(b7-b6)
Note 1: This bit can only be reset by writing “0” (Do not write “1”).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. For details, see the “precautions for interrupts” of the Usage Notes Reference Book.
Note 3: If the IFSR register’s IFSRi bit (i = 0 to 5) is “1” (both edges), set the INTiIC register’s POL bit to “0” (falling edge).
Note 4: Set the S3IC or S4IC register’s POL bit to “0” (falling edge) when the IFSR register’s IFSR6 bit = 0 (SI/O3
selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.
Figure 9.3.1. Interrupt Control Registers
Rev.0.60 2004.02.01 page 60 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
035F16
After reset
0016
Bit symbol
Bit name
Function
RW
RW
IFSR0
INT0 interrupt polarity
switching bit
0 : One edge
1 : Both edges (Note 1)
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges (Note 1)
RW
RW
RW
INT2 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
(Note 1)
INT3 interrupt polarity
switching bit
0 : One edge
1 : Both edges
INT4 interrupt polarity
switching bit
0 : One edge
1 : Both edges
RW
RW
RW
RW
(Note 1)
(Note 1)
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
Interrupt request cause
select bit
0 : SI/O3
1 : INT4
(Note 2)
Interrupt request cause
select bit
0 : SI/O4
1 : INT5
(Note 2)
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT5IC register’s POL bit
is set to “0” (= falling edge).
Note 2: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).
Interrupt request cause select register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR2A
Address
035E16
After reset
00XXXXX0
1
2
Bit symbol
Bit name
Function
Must be set to “1”.
RW
RW
Reserved bit
IFSR20
(Note 1)
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
(b5-b1)
IFSR26
Interrupt request cause
select bit
0 : ICOC base timer
1 : SCL/SDA
RW
RW
Interrupt request cause
select bit
0 : ICOC interrupt 1
1 : I2C-BUS interface
IFSR27
Note 1: Set this bit to "1" befor you enable interrupt after resetting.
Figure 9.3.2. IFSR Register and IFSR2A Register
Rev.0.60 2004.02.01 page 61 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
9.3.1 I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the
maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
9.3.2 IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
9.3.3 ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = “1”
· IR bit = “1”
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect
one another.
Table 9.3.3.2. Interrupt Priority Levels
Enabled by IPL
Table 9.3.3.1. Settings of Interrupt Priority
Levels
Interrupt priority
level
Priority
order
ILVL2 to ILVL0 bits
IPL
Enabled interrupt priority levels
000
001
010
011
100
101
110
111
2
Level 0 (interrupt disabled)
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
000
001
010
011
100
101
110
111
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
Rev.0.60 2004.02.01 page 62 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
9.4 Interrupt Sequence
An interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the
interrupt routine is executed) is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 9.4.1 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading
the address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not
requested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
(Note)
temporary register
.
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(Note)
(4) The CPU’s internal temporary register
is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
Note: This register cannot be used by user.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CPU clock
Address bus
Data bus
Address
000016
Indeterminate
Indeterminate
SP-2
SP-4
vec
vec+2
PC
Interrupt
information
SP-2
SP-4
vec
vec+2
contents contents contents contents
RD
Indeterminate
WR
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the
instruction queue buffer is ready to accept instructions.
Figure 9.4.1. Time Required for Executing Interrupt Sequence
Rev.0.60 2004.02.01 page 63 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
9. Interrupts
9.4.1 Interrupt Response Time
Figure 9.4.1.1 shows the interrupt response time. The interrupt response or interrupt acknowledge
time denotes time from when an interrupt request is generated till when the first instruction in the
interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is
generated till when the instruction then executing is completed ((a) in Figure 9.4.1.1) and the time
during which the interrupt sequence is executed ((b) in Figure 9.4.1.1).
Interrupt request generated
Interrupt request acknowledged
Time
Instruction in
interrupt routine
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
(a) The time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) The time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address SP value
Without wait
Even
Even
Odd
Even
Odd
18 cycles
19 cycles
19 cycles
20 cycles
Even
Odd
Odd
Figure 9.4.1.1. Interrupt response time
9.4.2 Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is
set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels
listed in Table 9.4.2.1 is set in the IPL. Shown in Table 9.4.2.1 are the IPL values of software and
special interrupts when they are accepted.
Table 9.4.2.1. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources
Level that is set to IPL
_______
Watchdog timer, NMI, Oscillation stop and re-oscillation detection,
7
voltage down detection
_________
Not changed
Software, address match, DBC, single-step
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9. Interrupts
9.4.3 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved.
Figure 9.4.3.1 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine.
Use the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Stack
Stack
Address
MSB
Address
MSB
LSB
LSB
[SP]
New SP value
m – 4
m – 3
m – 2
m – 1
m
m – 4
m – 3
m – 2
m – 1
m
PC
L
PC
M
FLG
L
FLG
H
PCH
[SP]
SP value before
interrupt request is
accepted.
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
m + 1
m + 1
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 9.4.3.1. Stack Status Before and After Acceptance of Interrupt Request
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9. Interrupts
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
(Note)
(Note)
SP
, at the time of acceptance of an interrupt request, is even or odd. If the stack pointer
is
even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8
bits at a time. Figure 9.4.3.2 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP
indicated by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Sequence in which order
registers are saved
Address
Stack
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
PC
L
(2) Saved simultaneously,
all 16 bits
PCM
FLG
L
(1) Saved simultaneously,
all 16 bits
FLG
H
PCH
[SP]
(Even)
Finished saving registers
in two operations.
(2) SP contains odd number
Address
Stack
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
PC
L
(3)
PCM
(4)
Saved, 8 bits at a time
FLG
L
(1)
(2)
FLG
H
PCH
[SP]
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 9.4.3.2. Operation of Saving Register
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9. Interrupts
9.4.4 Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt
sequence are restored from the stack by executing the REIT instruction at the end of the interrupt
routine. Thereafter the CPU returns to the program which was being executed before accepting the
interrupt request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
9.5 Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2
to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt
priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.5.1
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
NMI
High
DBC
Oscillation stop and re-oscillation
detection,
voltage down detection
Peripheral function
Single step
Low
Address match
Figure 9.5.1. Hardware Interrupt Priority
9.5.1 Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among
those requested.
Figure 9.5.1.1 shows the circuit that judges the interrupt priority level.
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9. Interrupts
Priority level of each interrupt
Level 0 (initial value)
INT1
Highest
Timer B2
Timer B0
Timer A3
Timer A1
ICOC interrupt 1, I2C-BUS interface
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
ICOC base timer, SCL/SDA
ICOC interrupt 0
UART1 reception
UART0 reception
UART2 reception, ACK2
A-D conversion
Priority of peripheral function interrupts
(if priority levels are same)
DMA1
UART 2 bus collision
SI/O4, INT5
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission, NACK2
Key input interrupt
DMA0
Lowest
SI/O3, INT4
IPL
Interrupt request level resolution output to clock
generating circuit (Fig.7.1.)
Interrupt
request
accepted
I flag
Address match
Watchdog timer
Oscillation stop and
re-oscillation detection
Voltage down detection
DBC
NMI
Figure 9.5.1.1. Interrupts Priority Select Circuit
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9. Interrupts
9.6 _I_N__T__ Interrupt
_______
INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSR register's IFSRi bit.
________
________
________
To use the INT4 interrupt, set the IFSR register's IFSR6 bit to "1" (=INT4). To use the INT5 interrupt, set the
________
IFSR register's IFSR7 bit to "1" (=INT5).
After modifiying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to "0" (=interrupt not requested)
before enabling the interrupt.
________
The INT5 input has an effective digital debounce function for a noise rejection. Refer to "17.6 Digital
Debounce function" for this detail.
Figure 9.6.1 shows the IFSR registers.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
035F16
After reset
0016
Bit symbol
Bit name
Function
RW
RW
IFSR0
INT0 interrupt polarity
switching bit
0 : One edge
1 : Both edges (Note 1)
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges (Note 1)
RW
RW
RW
INT2 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
(Note 1)
INT3 interrupt polarity
switching bit
0 : One edge
1 : Both edges
INT4 interrupt polarity
switching bit
0 : One edge
1 : Both edges
RW
RW
RW
RW
(Note 1)
(Note 1)
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
Interrupt request cause
select bit
0 : SI/O3
1 : INT4
(Note 2)
Interrupt request cause
select bit
0 : SI/O4
1 : INT5
(Note 2)
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT5IC register’s POL bit
is set to “0” (= falling edge).
Note 2: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).
Figure 9.6.1. IFSR Register
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9. Interrupts
______
9.7 NMI Interrupt
_______
_______
An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the
_______
______
NMI interrupt was enabled by writing a “1” to bit 4 of register PM2. The NMI interrupt is a non-maskable
interrupt, once it is enabled.
_______
The input level of this NMI interrupt input pin can be read by accessing the P8 register’s P8_5 bit.
_______
NMI is disabled by default after reset (the pin is a GPIO pin, P85) and can be enabled using bit 4 of PM2
register. Once enabled, it can only be disabled by a reset signal.
_______
The NMI input has an effective digital debounce function for a noise rejection. Refer to "17.6 Digital
Debounce function" for this detail.
9.8 Key Input Interrupt
Of P104 to P107, a key input interrupt is generated when input on any of the P104 to P107 pins which has
had the PD10 register’s PD10_4 to PD10_7 bits set to “0” (= input) goes low. Key input interrupts can be
used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode.
However, if you intend to use the key input interrupt, do not use P104 to P107 as analog input ports.
Figure 9.8.1 shows the block diagram of the key input interrupt. Note, however, that while input on any pin
which has had the PD10_4 to PD10_7 bits set to “0” (= input mode) is pulled low, inputs on all other pins
of the port are not detected as interrupts.
PUR2 register's PU25 bit
Pull-up
transistor
KUPIC register
PD10 register's
PD10_7 bit
PD10 register's PD10_7 bit
KI
3
PD10 register's
PD10_6 bit
Pull-up
transistor
Key input interrupt
request
Interrupt control circuit
KI
2
Pull-up
transistor
PD10 register's
PD10_5 bit
KI
1
PD10 register's
PD10_4 bit
Pull-up
transistor
KI
0
Figure 9.8.1. Key Input Interrupt
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9. Interrupts
9.9 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the
address indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi
register. Use the AIER register’s AIER0 and AIER1 bits to enable or disable the interrupt. Note that the
address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the
PC that is saved to the stack area varies depending on the instruction being executed (refer to “Saving
Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow
one of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 9.9.1 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Figure 9.9.1 shows the AIER, RMAD0 and RMAD1 registers.
Table 9.9.1. Value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Value of the PC that is
Instruction at the address indicated by the RMADi register
saved to the stack area
• 16-bit op-code instruction
The address
• Instruction shown below among 8-bit operation code instructions
indicated by the
RMADi register +2
ADD.B:S
OR.B:S
#IMM8,dest
#IMM8,dest
SUB.B:S
MOV.B:S
#IMM8,dest
#IMM8,dest
AND.B:S #IMM8,dest
STZ.B:S
#IMM8,dest
STNZ.B:S #IMM8,dest
STZX.B:S #IMM81,#IMM82,dest
CMP.B:S
JMPS
#IMM8,dest
#IMM8
PUSHM
JSRS
src
#IMM8
POPM dest
MOV.B:S
#IMM,dest (However, dest=A0 or A1)
The address
indicated by the
RMADi register +1
Instructions other than the above
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
Table 9.9.2. Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources Address match interrupt enable bit Address match interrupt register
Address match interrupt 0
Address match interrupt 1
AIER0
AIER1
RMAD0
RMAD1
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9. Interrupts
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
After reset
XXXXXX00
2
Bit symbol
AIER0
Bit name
Function
RW
RW
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Address match interrupt 1
enable bit
AIER1
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
(b7-b2)
Address match interrupt register i (i = 0 to 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
After reset
X0000016
X0000016
b0
Function
Setting range
0000016 to FFFFF16
RW
RW
Address setting register for address match interrupt
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Figure 9.9.1. AIER Register, RMAD0 and RMAD1 Registers
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10. Watchdog Timer
10. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per-
formed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit of PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it cannot be
set to “0” (watchdog timer interrupt) in a program. Refer to “5.3 Watchdog Timer Reset” for the details of
watchdog timer reset.
When the main clock source is selected for CPU clock, ring oscillator clock, PLL clock,the WDC register's
the WDC7 bit value for prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU clock,
the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calcu-
lated as given below. The period of watchdog timer is, however, subject to an error due to the prescaler.
With main clock source chosen for CPU clock, ring oscillator clock, PLL clock
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
Watchdog timer period =
CPU clock
With sub-clock chosen for CPU clock
Prescaler dividing (2) X Watchdog timer count (32768)
Watchdog timer period =
CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is re-
sumed from the held value when the modes or state are released.
Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related
registers.
• Count source protective mode
In this mode, a ring oscillator clock is used for the watchdog timer count source. The watchdog timer can be
kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit of PRCR register to “1” (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit of PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit of PM2 register to “1” (ring oscillator clock used for the watchdog timer count source).
(4) Set the PRC1 bit of PRCR register to “0” (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
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10. Watchdog Timer
Setting the PM22 bit to “1” results in the following conditions
• The ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count
source.
Watchdog timer count (32768)
Watchdog timer period =
ring oscillator clock
• The CM10 bit of CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode
entered.)
• The watchdog timer does not stop when in wait mode.
Prescaler
CM07 = 0
WDC7 = 0
1/16
PM12 = 0
CM07 = 0
WDC7 = 1
Watchdog timer
interrupt request
PM22 = 0
PM22 = 1
CPU
clock
1/128
1/2
Watchdog timer
CM07 = 1
PM12 = 1
Reset
Ring oscillator clock
Set to
“7FFF16”
Write to WDTS register
RESET
Figure 10.1. Watchdog Timer Block Diagram
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
After reset
00XXXXXX (Note 2)
0
2
Bit symbol
Bit name
High-order bit of watchdog timer
Cold start / warm start 0 : Cold start
Function
RW
RO
(b4-b0)
WDC5
RW
RW
discrimination flag (Note 1, 2) 1 : Warm start
Reserved bit
Must set to “0”
(b6)
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
RW
Note 1: Writing to the WDC register causes the WDC5 bit to be set to “1” (warm start).
Note 2: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set
to “0” when the input voltage at the VCC pin drops to Vdet
is set to “1” (RAM retention limit detection circuit enable).
2
or less while the VC25 bit in the VCR2 register
Watchdog timer start register (Note)
b7
b0
Symbol
WDTS
Address
000E16
After reset
Indeterminate
RW
WO
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16
”
regardless of whatever value is written.
Note : Write to the WDTS register after the watchdog timer interrupt occurs.
Figure 10.2. WDC Register and WDTS Register
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11. DMAC
M16C/28 Group
11. DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by
the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of
a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time
after a DMA request is generated. Figure 11.1 shows the block diagram of the DMAC. Table 11.1 shows the
DMAC specifications. Figures 11.2 to 11.4 show the DMAC-related registers.
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016
DMA0 destination pointer DAR0 (20)
)
(addresses 002616 to 002416
)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016
DMA1 destination pointer DAR1 (20)
(addresses 002916, 002816
)
)
DMA0 transfer counter TCR0 (16)
(addresses 003616 to 003416
)
DMA1 forward address pointer (20) (Note)
DMA1 transfer counter reload register TCR1 (16)
(addresses 003916, 003816
)
DMA latch high-order bits DMA latch low-order bits
DMA1 transfer counter TCR1 (16)
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 11.1 DMAC Block Diagram
A DMA request is generated by a write to the DMiSL register (i = 0,1)’s DSR bit, as well as by an interrupt
request which is generated by any function specified by the DMiSL register’s DMS and DSEL3 to DSEL0
bits. However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the
interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be
accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts,
the interrupt control register’s IR bit does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMiCON register’s DMAE bit =
“1” (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA
transfer cycle, the number of transfer requests generated and the number of times data is transferred may
not match. For details, refer to “DMA Requests”.
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11. DMAC
M16C/28 Group
Table 11.1 DMAC Specifications
Item
Specification
No. of channels
2 (cycle steal method)
Transfer memory space
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
________
DMA request factors
(Note 1, Note 2)
Falling edge of INT0 or INT1
Both edge of INT0 or INT1
________ ________
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrupt requests
A-D conversion interrupt requests
Timer S(ICOC) requests
Software triggers
Channel priority
Transfer unit
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
Transfer address direction
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer mode Single transfer Transfer is completed when the DMAi transfer counter (i = 0,1)
underflows after reaching the terminal count.
Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is con
tinued with it.
DMA interrupt request generation timing When the DMAi transfer counter underflowed
DMA startup
Data transfer is initiated each time a DMA request is generated when the
DMAiCON register’s DMAE bit = “1” (enabled).
DMA shutdown Single transfer • When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
Repeat transfer When the DMAE bit is set to “0” (disabled)
When a data transfer is started after setting the DMAE bit to “1” (en
Reload timing for forward ad-
dress pointer and transfer
counter
abled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
Notes:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 002016 to 003F16) are accessed by the DMAC.
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11. DMAC
M16C/28 Group
DMA0 request cause select register
Symbol
DM0SL
Address
03B816
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
DSEL0
Function
Bit name
RW
RW
RW
DMA request cause
select bit
Refer to note
DSEL1
DSEL2
RW
RW
DSEL3
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b5-b4)
DMS
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
RW
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
Software DMA
request bit
DSR
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .
Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS=0(basic cause of request)
DMS=1(extended cause of request)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
ICOC base timer
–
ICOC channel 0
ICOC channel 1
–
–
Two edges of INT0 pin
–
–
Timer B2
–
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
A-D conversion
UART1 transmit
ICOC channel 2
ICOC channel 3
ICOC channel 4
ICOC channel 5
ICOC channel 6
ICOC channel 7
Figure 11.2 DM0SL Register
Rev.0.60 2004.02.01 page 77 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
11. DMAC
M16C/28 Group
DMA1 request cause select register
Symbol
DM1SL
Address
03BA16
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Function
Bit symbol
DSEL0
RW
RW
DMA request cause
select bit
Refer to note
DSEL1
DSEL2
RW
RW
DSEL3
(b5-b4)
DMS
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
RW
Software DMA
request bit
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSR
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .
Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0 DMS=0(basic cause of request)
DMS=1(extended cause of request)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
ICOC base timer
–
ICOC channel 0
ICOC channel 1
–
SI/O3
SI/O4
Two edges of INT1
–
–
ICOC channel 2
ICOC channel 3
ICOC channel 4
ICOC channel 5
ICOC channel 6
ICOC channel 7
Timer B2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive/ACK2
A-D conversion
UART1 receive
DMAi control register(i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0CON
DM1CON
Address
002C16
003C16
After reset
00000X00
00000X00
2
2
Bit symbol
Bit name
Function
RW
RW
Transfer unit bit select bit 0 : 16 bits
1 : 8 bits
DMBIT
DMASL
DMAS
DMAE
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
RW
RW
(Note 1)
0 : DMA not requested
1 : DMA requested
DMA request bit
DMA enable bit
0 : Disabled
1 : Enabled
RW
RW
RW
Source address direction
select bit (Note 2)
0 : Fixed
1 : Forward
DSD
DAD
Destination address
direction select bit (Note 2)
0 : Fixed
1 : Forward
Nothing is assigned. When write, set to “0”. When
read, its content is “0”.
(b7-b6)
Note 1: The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
Note 2: At least one of the DAD and DSD bits must be “0” (address direction fixed).
Figure 11.3 DM1SL Register, DM0CON Register, and DM1CON Registers
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Preliminary specification
Specifications in this manual are tentative and subject to change.
11. DMAC
M16C/28 Group
DMAi source pointer (i = 0, 1) (Note)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
After reset
Indeterminate
Indeterminate
Setting range
0000016 to FFFFF16
Function
Set the source address of transfer
RW
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DSD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0” (DMA disabled).
If the DSD bit is “1” (forward direction), this register can be written to at any time.
If the DSD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi destination pointer (i = 0, 1)(Note)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
After reset
Indeterminate
Indeterminate
Setting range
0000016 to FFFFF16
RW
Function
Set the destination address of transfer
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DAD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0”(DMA disabled).
If the DAD bit is “1” (forward direction), this register can be written to at any time.
If the DAD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
After reset
Indeterminate
Indeterminate
Function
RW
Setting range
Set the transfer count minus 1. The written value
is stored in the DMAi transfer counter reload
register, and when the DMAE bit of DMiCON
register is set to “1” (DMA enabled) or the DMAi
transfer counter underflows when the DMASL bit
of DMiCON register is “1” (repeat transfer), the
value of the DMAi transfer counter reload register
is transferred to the DMAi transfer counter.
When read, the DMAi transfer counter is read.
000016 to FFFF16
RW
Figure 11.4 SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1 Registers
Rev.0.60 2004.02.01 page 79 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
11. DMAC
M16C/28 Group
11.1 Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination
write) bus cycle. The number of read and write bus cycles is affected by the source and destination
addresses of transfer. Furthermore, the bus cycle itself is extended by a software wait.
11.1.1 Effect of Source and Destination Addresses
If the transfer unit is 16 bits and the source address of transfer begins with an odd address, the source
read cycle consists of one more bus cycle than when the source address of transfer begins with an
even address.
Similarly, if the transfer unit is 16 bits and the destination address of transfer begins with an odd
address, the destination write cycle consists of one more bus cycle than when the destination address
of transfer begins with an even address.
11.1.2 Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of
bus cycles required for that access increases by an amount equal to software wait states.
Figure 11.1.1 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality,
the destination write cycle is subject to the same conditions as the source read cycle, with the transfer
cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for
the source read and the destination write cycle, respectively. For example, when data is transferred in 16
bit units and when both the source address and destination address are an odd address ((2) in Figure
11.1.1), two source read bus cycles and two destination write bus cycles are required.
Rev.0.60 2004.02.01 page 80 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
11. DMAC
M16C/28 Group
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
CPU clock
Address
bus
Dummy
cycle
Destination
CPU use
Source
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
Destination
CPU use
Source
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
CPU clock
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
CPU use
Destination
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source + 1
Source
CPU use
Destination
(3) When the source read cycle under condition (1) has one wait state inserted
CPU clock
Dummy
cycle
Address
bus
Destination
Source
CPU use
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
Destination
CPU use
Source
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
CPU clock
Address
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
bus
RD signal
WR signal
Data
bus
Dummy
cycle
Destination
CPU use
CPU use
Source
Source + 1
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 11.1.1 Transfer Cycles for Source Read
Rev.0.60 2004.02.01 page 81 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
11. DMAC
M16C/28 Group
11.2. DMA Transfer Cycles
Any combination of even or odd transfer read and write adresses is possible. Table 11.2.1 shows the
number of DMA transfer cycles. Table 11.2.2 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 11.2.1 DMA Transfer Cycles
Transfer unit
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
Access address
Even
No. of read cycles
No. of write cycles
1
1
1
2
1
1
1
2
Odd
Even
Odd
Table 11.2.2 Coefficient j, k
Internal area
Internal ROM, RAM
No wait With wait
SFR
1 wait
2 wait
(Note)
(Note)
3
j
1
1
2
2
2
2
3
k
Note : Depends on the set value of PM20 bit in PM2 register
Rev.0.60 2004.02.01 page 82 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
11. DMAC
M16C/28 Group
11.3 DMA Enable
When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register
is “1” (forward) or the DARi register value when the DAD bit of DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However,
if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
11.4 DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the
DMS and DSEL3 to DSEL0 bits of DMiSL register (i = 0, 1) on either channel. Table 11.4.1 shows the
timing at which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is
set to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in
a program (it can only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 11.4.1 Timing at Which the DMAS Bit Changes State
DMAS bit of the DMiCON register
DMA factor
Timing at which the bit is set to “1” Timing at which the bit is set to “0”
When the DSR bit of DMiSL
register is set to “1”
• Immediately before a data transfer starts
• When set by writing “0” in a program
Software trigger
Peripheral function
When the interrupt control register
for the peripheral function that is
selected by the DSEL3 to DSEL0
and DMS bits of DMiSL register
has its IR bit set to “1”
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Preliminary specification
Specifications in this manual are tentative and subject to change.
11. DMAC
M16C/28 Group
11.5 Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
CPU clock), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case,
the DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following de-
scribes DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling
period. Figure 11.5.1 shows an example of DMA transfer effected by external factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request
are generated simultanelously. After one DMA0 transfer is completed, a bus arbitration is returned to the
CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is
completed, the bus arbitration is again returned to the CPU.
In addition, DMA requsts cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 11.5.1, occurs more than one time, the DAMS bit is set to "0" as soon
as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
An example where DMA requests for external causes are detected active at the same
CPU clock
DMA0
Obtainment
of the bus
right
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 11.5.1 DMA Transfer by External Factors
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12. Timers
Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as
either timer A (five) and timer B (three). The count source for each timer acts as a clock, to control such
timer operations as counting, reloading, etc. Figures 12.1 and 12.2 show block diagrams of timer A and
timer B configuration, respectively.
f
2
PCLK0 bit = 0
PCLK0 bit = 1
Clock prescaler
1/2
1/8
• Main clock
• PLL clock
• Ring oscillator
clock
f
1 or f2
f1
f
C32
1/32
X
CIN
Reset
f
8
Set the CPSR bit of CPSRF
register to “1” (= prescaler
reset)
f
32
1/4
f8 f32 fC32
f
1 or f2
• Timer mode
• One-shot timer mode
• Pulse Width Measuring (PWM) mode
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer A0
Noise
filter
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A1
Noise
filter
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A2
Noise
filter
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A3
Noise
filter
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A4
Noise
filter
• Event counter mode
Timer B2 overflow or underflow
Figure 12.1. Timer A Configuration
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
f2
PCLK0 bit = 0
PCLK0 bit = 1
Clock prescaler
1/2
1/8
• Main clock
• PLL clock
• Ring oscillator
clock
f1 or f2
f1
fC32
1/32
XCIN
Reset
f8
Set the CPSR bit of CPSRF
register to “1” (= prescaler
reset)
f32
1/4
f1 or f2 f8 f32 fC32
Timer B2 overflow or underflow ( to Timer A count source)
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B0 interrupt
Noise
filter
Timer B0
TB0IN
TB1IN
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B1 interrupt
Timer B2 interrupt
Noise
filter
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB2IN
Timer B2
• Event counter mode
Figure 12.2. Timer B Configuration
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
12.1 Timer A
Figure 12.1.1 shows a block diagram of the timer A. Figures 12.1.2 to 12.1.4 show registers related to the
timer A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of
other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count
“000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f1 or f2
Low-order
8 bits
High-order
8 bits
f8
• Timer
(gate function)
f32
Reload register
f
C32
Clock selection
• Event counter
Counter
Polarity
selection
Up-count/down-count
TAiIN
(i = 0 to 4)
Always counts down except
in event counter mode
TABSR register
Clock selection
TAi
Addresses
TAj
TAk
(Note)
TB2 overflow
(Note)
TAj overflow
Timer A0 038716 - 038616
Timer A1 038916 - 038816
Timer A2 038B16 - 038A16
Timer A3 038D16 - 038C16
Timer A4 038F16 - 038E16
Timer A4 Timer A1
Timer A0 Timer A2
Timer A1 Timer A3
Timer A2 Timer A4
Timer A3 Timer A0
To external
trigger circuit
Down count
(j = i – 1. Note, however, that j = 4 when i = 0)
UDF register
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Note: Overflow or underflow
Figure 12.1.1. Timer A Block Diagram
Timer Ai mode register (i=0 to 4)
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Bit symbol
TMOD0
Bit name
Operation mode select bit
Function
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
TMOD1
RW
RW
MR0
MR1
MR2
MR3
TCK0
TCK1
Function varies with each
operation mode
RW
RW
RW
RW
RW
Count source select bit
Function varies with each
operation mode
Figure 12.1.2. TA0MR to TA4MR Registers
Rev.0.60 2004.02.01 page 87 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
Timer Ai register (i= 0 to 4) (Note 1)
Symbol
Address
After reset
(b15)
b7
(b8)
b0 b7
TA0
TA1
TA2
TA3
TA4
038716, 038616
038916, 038816
038B16, 038A16
038D16, 038C16
038F16, 038E16
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b0
Function
RW
RW
Mode
Timer
mode
Setting range
Divide the count source by n + 1 where n =
set value
000016 to FFFF16
Event
counter
mode
Divide the count source by FFFF16 – n + 1
000016 to FFFF16
RW
WO
where n = set value when counting up or
(Note 5)
by n + 1 when counting down
One-shot
Divide the count source by n where n = set 000016 to FFFF16
timer mode value and cause the timer to stop
(Notes 2, 4)
Modify the pulse width as follows:
PWM period: (216 – 1) / fj
High level PWM pulse width: n / fj
where n = set value, fj = count source
frequency
Pulse width
modulation
mode
000016 to FFFE16
(Note 3, 4)
WO
WO
(16-bit PWM)
Pulse width
modulation
mode
0016 to FE16
Modify the pulse width as follows:
PWM period: (28 – 1) x (m + 1)/ fj
High level PWM pulse width: (m + 1)n / fj
where n = high-order address set value,
m = low-order address set value, fj =
count source frequency
(High-order address)
0016 to FF16
(Low-order address)
(8-bit PWM)
(Note 3, 4)
Note 1: The register must be accessed in 16 bit units.
Note 2: If the TAi register is set to ‘000016,’ the counter does not work and timer Ai interrupt
requests are not generated either. Furthermore, if “pulse output” is selected, no pulses are
output from the TAiOUT pin.
Note 3: If the TAi register is set to ‘000016,’ the pulse width modulator does not work, the output
level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated
either. The same applies when the 8 high-order bits of the timer TAi register are set to ‘001
6’ while operating as an 8-bit pulse width modulator.
Note 4: Use the MOV instruction to write to the TAi register.
Note 5: The timer counts pulses from an external device or overflows or underflows in other timers.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
After reset
0016
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
0 : Stops counting
RW
RW
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
1 : Starts counting
RW
RW
RW
RW
RW
RW
RW
Up/down flag (Note 1)
Symbol
UDF
Address
038416
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0UD
TA1UD
TA2UD
TA3UD
TA4UD
Bit name
Function
RW
RW
Timer A0 up/down flag
0 : Down count
1 : Up count
RW
RW
RW
RW
Timer A1 up/down flag
Timer A2 up/down flag
Enabled by setting the TAiMR
register’s MR2 bit to “0”
(= switching source in UDF
register) during event counter
mode.
Timer A3 up/down flag
Timer A4 up/down flag
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
Timer A2 two-phase pulse
signal processing select bit
TA2P
TA3P
TA4P
WO
WO
WO
Timer A3 two-phase pulse
signal processing select bit
(Notes 2, 3)
Timer A4 two-phase pulse
signal processing select bit
Note 1: Use MOV instruction to write to this register.
Note 2: Make sure the port direction bits for the TA2IN to TA4I
“0” (input mode).
N
and TA2OUT to TA4OUT pins are set to
Note 3: When not using the two-phase pulse signal processing function, set the corresponding bit to “0”.
Figure 12.1.3. TA0 to TA4 Registers, TABSR Register, and UDF Register
Rev.0.60 2004.02.01 page 88 of N
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
One-shot start flag
Symbol
ONSF
Address
038216
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Bit symbol
Bit name
Function
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
The timer starts counting by setting
this bit to “1” while the TMOD1 to
TMOD0 bits of TAiMR register (i =
2’ (= one-shot timer
mode) and the MR2 bit of TAiMR
RW
RW
0 to 4) = ‘10
register = “0” (=TAiOS bit enabled). RW
When read, its content is “0”.
RW
0 : Z-phase input disabled
RW
TAZIE
Z-phase input enable bit
1 : Z-phase input enabled
b7 b6
TA0TGL
Timer A0 event/trigger
select bit
RW
(Note 1)
0 0 : Input on TA0IN is selected
(Note 2)
(Note 2)
(Note 2)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
TA0TGH
RW
Note 1: Make sure the PD7_1 bit of PD7 register is set to “0” (= input mode).
Note 2: Overflow or underflow
Trigger select register
Symbol
TRGSR
Address
038316
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA1TGL
Bit name
Function
RW
RW
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 is selected
1 0 : TA0 is selected
1 1 : TA2 is selected
TA1TGH
TA2TGL
RW
RW
b3 b2
Timer A2 event/trigger
select bit
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 is selected
1 0 : TA1 is selected
1 1 : TA3 is selected
TA2TGH
TA3TGL
TA3TGH
RW
RW
RW
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 is selected
1 0 : TA2 is selected
1 1 : TA4 is selected
b7 b6
Timer A4 event/trigger
select bit
TA4TGL
TA4TGH
RW
RW
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 is selected
1 0 : TA3 is selected
1 1 : TA0 is selected
Note : Make sure the port direction bits for the TA1IN to TA4IN pins are set to “0” (= input mode).
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
After reset
0XXXXXXX
2
RW
RW
Bit symbol
Bit name
Nothing is assigned.
When write, set to “0”. When read, their contents are
Function
(b6-b0)
CPSR
indeterminate.
Setting this bit to “1” initializes the
prescaler for the timekeeping clock. (
Clock prescaler reset flag
When read, its content is “0”.)
Figure 12.1.4. ONSF Register, TRGSR Register, and CPSRF Register
Rev.0.60 2004.02.01 page 89 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
12.1.1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 12.1.1.1). Figure 1.2.1.1.1
shows TAiMR register in timer mode.
Table 12.1.1.1. Specifications in Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
•
When the timer underflows, it reloads the reload register contents and continues counting
Divide ratio
1/(n+1) n: set value of TAi register (i= 0 to 4) 000016 to FFFF16
Count start condition
Count stop condition
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
I/O port or gate input
I/O port or pulse output
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Gate function
Select function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When not counting, the pin outputs a low.
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
0
0 0
Bit symbol
Bit name
Function
RW
RW
RW
b1 b0
Operation mode
select bit
TMOD0
TMOD1
MR0
0 0 : Timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output
RW
(TAiOUT pin is a pulse output pin)
b4 b3
Gate function select bit
MR1
MR2
0 0 : Gate function not available
}
RW
RW
0 1 :
(TAiIN pin functions as I/O port)
1 0 : Counts while input on the TAiIN pin
is low (Note 1)
1 1 : Counts while input on the TAiIN pin
is high (Note 1)
RW
RW
MR3
Must be set to “0” in timer mode
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
or f2
0 1 : f
1 0 : f32
1 1 : fC32
TCK1
RW
Note 1: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 12.1.1.1. Timer Ai Mode Register in Timer Mode
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
12.1.2. Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 12.1.2.1 lists specifica-
tions in event counter mode (when not processing two-phase pulse signal). Table 12.1.2.2 lists specifica-
tions in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4).
Figure 12.1.2.1 shows TAiMR register in event counter mode (when not processing two-phase pulse
signal). Figure 12.1.2.2 shows TA2MR to TA4MR registers in event counter mode (when processing two-
phase pulse signal with the timers A2, A3 and A4).
Table 12.1.2.1. Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item
Specification
Count source
• External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected
in program)
• Timer B2 overflows or underflows,
timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,
timer Ak (k=i+1, except k=0 if i=4) overflows or underflows
• Up-count or down-count can be selected by external signal or program
• When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Count operation
Divided ratio
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Count start condition
Count stop condition
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
I/O port or count source input
I/O port, pulse output, or up/down-count select input
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Free-run count function
Select function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
• Pulse output function
Whenever the timer underflows or underflows, the output polarity of TAiOUT
pin is inverted . When not counting, the pin outputs a low.
Rev.0.60 2004.02.01 page 91 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
Timer Ai mode register (i=0 to 4)
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
0
0 1
Bit symbol
Bit name
Function
RW
b1 b0
TMOD0
TMOD1
MR0
RW
RW
Operation mode select bit
0 1 : Event counter mode (Note 1)
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output
Pulse output function
select bit
RW
RW
(TAiOUT pin functions as pulse output pin)
MR1
MR2
Count polarity
select bit (Note 2)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : UDF register
1 : Input signal to TAiOUT pin (Note 3)
RW
RW
RW
MR3
Must be set to “0” in event counter mode
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK1
Can be “0” or “1” when not using two-phase pulse signal
processing
RW
Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘00 ’ (TAiIN pin input).
2
Note 3: Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port
direction bit for TAiOUT pin must be set to “0” (= input mode).
Figure 12.1.2.1. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
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M16C/28 Group
12.1 Timer A
Table 12.1.2.2. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4)
Item
Count source
Count operation
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 4)
• Up-count or down-count can be selected by two-phase pulse signal
• When the timer overflows or underflows, it reloads the reload register con-
tents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divide ratio
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Count start condition
Count stop condition
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Two-phase pulse input
Two-phase pulse input
Count value can be read by reading timer A2, A3 or A4 register
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
(Transferred to counter when reloaded next)
Select function (Note)
• Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN pin
when input signals on TAjOUT pin is “H”.
TAjOUT
TAjIN
(j=2,3)
Up-
count
Up-
count
Up-
count count
Down- Down- Down-
count count
• Multiply-by-4 processing operation (timer A3 and timer A4)
If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the
input signal on TAkOUT pin is “H”, the timer counts up rising and falling
edges on TAkOUT and TAkIN pins. If the phase relationship is such that
TAkIN pin goes “L” when the input signal on TAkOUT pin is “H”, the timer
counts down rising and falling edges on TAkOUT and TAkIN pins.
TAkOUT
Count down all edges
Count up all edges
TAkIN
(k=3,4)
Count up all edges
Count down all edges
• Counter initialization by Z-phase input (timer A3)
The timer count value is initialized to 0 by Z-phase input.
Notes:
1. Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to
multiply-by-4 processing operation.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
Timer Ai mode register (i=2 to 4)
(When using two-phase pulse signal processing)
Symbol
TA2MR to TA4MR
Address
039816 to 039A16
After reset
0016
b6 b5 b4 b3 b2 b1 b0
0
1 0 0 0 1
RW
Bit name
Operation mode select bit
Function
0 1 : Event counter mode
b1 b0
TMOD0
RW
RW
TMOD1
MR0
To use two-phase pulse signal processing, set this bit to “0”.
RW
RW
RW
RW
RW
MR1
MR2
To use two-phase pulse signal processing, set this bit to “0”.
To use two-phase pulse signal processing, set this bit to “1”.
MR3
To use two-phase pulse signal processing, set this bit to “0”.
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK0
Two-phase pulse signal
processing operation
select bit (Note 1)(Note 2)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
RW
Note 1: TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
Note 2: If two-phase pulse signal processing is desired, following register settings are required:
• Set the UDF register’s TAiP bit to “1” (two-phase pulse signal processing function enabled).
• Set the TRGSR register’s TAiTGH and TAiTGL bits to ‘002’ (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode).
Figure 12.1.2.2. TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase
pulse signal processing with timer A2, A3 or A4)
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal process-
_______
ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Counter initialization by Z-phase input is enabled by writing “000016” to the TA3 register and setting
the TAZIE bit in ONSF register to “1” (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-
sen to be the rising or falling edge by using the POL bit of INT2IC register. The Z-phase pulse width
_______
applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.1.2.1.1
shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
(Note)
INT2
(Z phase)
Input equal to or greater than one clock cycle
of count source
m
m+1
1
2
3
4
5
Timer A3
Note: This timing diagram is for the case where the POL bit of INT2IC register = “1” (= rising edge).
Figure 12.1.2.1.1. Two-phase Pulse (A phase and B phase) and the Z Phase
Rev.0.60 2004.02.01 page 95 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
12.1.3. One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.1.3.1.) When the
trigger occurs, the timer starts up and continues operating for a given period. Figure 12.1.3.1 shows the
TAiMR register in one-shot timer mode.
Table 12.1.3.1. Specifications in One-shot Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
•
When the counter reaches 000016, it stops counting after reloading a new value
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
n : set value of TAi register 000016 to FFFF16
Divide ratio
1/n
However, the counter does not work if the divide-by-n value is set to 000016.
TAiS bit of TABSR register = “1” (start counting) and one of the following
triggers occurs.
Count start condition
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• The TAiOS bit of ONSF register is set to “1” (= timer starts)
• When the counter is reloaded after reaching “000016”
• TAiS bit is set to “0” (= stop counting)
Count stop condition
Interrupt request generation timing When the counter reaches “000016”
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
I/O port or trigger input
I/O port or pulse output
An indeterminate value is read by reading TAi register
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Pulse output function
Select function
The timer outputs a low when not counting and a high when counting.
Rev.0.60 2004.02.01 page 96 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
39616 to 039A16
After reset
0016
0
1 0
Bit symbol
Bit name
RW
RW
RW
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
1 0 : One-shot timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output
RW
(TAiOUT pin functions as a pulse output pin)
MR1
MR2
0 : Falling edge of input signal to TAiIN pin (Note 2)
1 : Rising edge of input signal to TAiIN pin (Note 2)
External trigger select
bit (Note 1)
RW
RW
Trigger select bit
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
MR3
RW
RW
Must be set to “0” in one-shot timer mode
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
or f2
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
RW
Note 1: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘00
2’ (TAiIN pin input).
Note 2: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 12.1.3.1. TAiMR Register in One-shot Timer Mode
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
12.1.4. Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.1.4.1). The counter
functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.1.4.1 shows
TAiMR register in pulse width modulation mode. Figures 12.1.4.2 and 12.1.4.3 show examples of how a
16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates.
Table 12.1.4.1. Specifications in Pulse Width Modulation Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count (operating as an 8-bit or a 16-bit pulse width modulator)
The timer reloads a new value at a rising edge of PWM pulse and continues counting
•
• The timer is not affected by a trigger that occurs during counting
16-bit PWM
• High level width
• Cycle time (2 -1) / fj fixed
n / fj
n : set value of TAi register (i=o to 4)
fj: count source frequency (f1, f2, f8, f32, fC32)
16
8-bit PWM
•
•
High level width n x (m+1) / fj n : set value of TAi register high-order address
Cycle time (2 -1) x (m+1) / fj m : set value of TAi register low-order address
8
Count start condition
• TAiS bit of TABSR register is set to “1” (= start counting)
• The TAiS bit = 1 and external trigger input from the TAiIN pin
• The TAiS bit = 1 and one of the following external triggers occurs
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
TAiS bit is set to “0” (= stop counting)
Count stop condition
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function
TAiOUT pin function
Read from timer
I/O port or trigger input
Pulse output
An indeterminate value is read by reading TAi register
Write to timer
•
When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Rev.0.60 2004.02.01 page 98 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
Timer Ai mode register (i= 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
039616 to 039A16
After reset
0016
1 1
1
RW
RW
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 1 : PWM mode
RW
RW
MR0
MR1
Must be set to “1” in PWM mode
External trigger select
bit (Note 1)
0: Falling edge of input signal to TAiIN pin(Note 2)
1: Rising edge of input signal to TAiIN pin(Note 2)
RW
RW
MR2
MR3
Trigger select bit
0 : Write “1” to TAiS bit in the TASF register
1 : Selected by TAiTGH to TAiTGL bits
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
16/8-bit PWM mode
select bit
RW
RW
RW
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
1 0 : f32
1
8
or f2
1 1 : fC32
Note 1: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘00
Note 2: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
2’ (TAiIN pin input).
Figure 12.1.4.1. TAiMR Register in Pulse Width Modulation Mode
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.1 Timer A
1 / fi
X
(216 – 1)
Count source
“H”
“L”
Input signal to
TAiIN pin
Trigger is not generated by this signal
1 / fj
X
n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
IR bit of TAiIC
register
f
j
: Frequency of count source
(f , f , f , f32, fC32
i = 0 to 4
Note 1: n = 000016 to FFFE16
Note 2: This timing diagram is for the case where the TAi register is ‘000316,’ the TAiTGH and TAiTGL bits of
ONSF or TRGSR register = ‘00 ’ (TAiIN pin input), the MR1 bit of TAiMR register = 1 (rising edge), and
1
2
8
)
Set to “0” upon accepting an interrupt request or by writing in program
.
2
the MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 12.1.4.2. Example of 16-bit Pulse Width Modulator Operation
1 / fj
X (m + 1) X (28 – 1)
Count source (Note1)
“H”
“L”
Input signal to
TAiIN pin
1 / fj X (m + 1)
“H”
“L”
Underflow signal of
8-bit prescaler (Note2)
1 / fj X (m + 1) X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
IR bit of TAiIC
register
f
j
: Frequency of count source
(f , f , f , f32, fC32
i = 0 to 4
Set to “0” upon accepting an interrupt request or by writing in program
1
2
8
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FE16
Note 4: This timing diagram is for the case where the TAi register is ‘020216,’ the TAiTGH and TAiTGL bits of ONSF or
TRGSR register = ‘00 ’ (TAiIN pin input), the MR1 bit of TAiMR register = 0 (falling edge), and the MR2 bit of
.
2
TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 12.1.4.3. Example of 8-bit Pulse Width Modulator Operation
Rev.0.60 2004.02.01 page 100 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer B
M16C/28 Group
12.2 Timer B
Figure 12.2.1 shows a block diagram of the timer B. Figures 12.2.2 and 12.2.3 show registers related to the
timer B.
Timer B supports the following four modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 2)
to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
• A-D trigger mode: The timer counts only once before it reaches the minimum count "000016"
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
Reload register
• Timer
f1 or f2
• Pulse period measuremnet,
pulse width measurement
f
f
8
Clock selection
32
fC32
Counter
• Event counter
Polarity switching,
edge pulse
TABSR register
TBiIN
(i = 0 to 2)
Counter reset circuit
TBi
Can be selected in only
event counter mode
Address
TBj
Timer B0 039116
Timer B1 039316
Timer B2 039516
-
-
-
039016 Timer B2
039216 Timer B0
039416 Timer B1
TBj overflow (Note)
(j = i – 1, except j = 2 if i = 0)
Note: Overflow or underflow.
Figure 12.2.1. Timer B Block Diagram
Timer Bi mode register (i=0 to 2)
Symbol
Address
After reset
b7 b6 b5 b4 b3 b2 b1 b0
TB0MR to TB2MR 039B16 to 039D16 00XX0000
2
Bit symbol
TMOD0
Function
Bit
RW
RW
b1 b0
name
Operation mode select bit
0 0 : Timer mode or A-D trigger mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
TMOD1
RW
MR0
MR1
MR2
RW
RW
Function varies with each operation
mode
RW
(Note 1)
(Note 2)
RO
MR3
TCK0
TCK1
RW
RW
Count source select bit
Function varies with each operation
mode
Note 1: Timer B0.
Note 2: Timer B1, Timer B2.
Figure 12.2.2. TB0MR to TB2MR Registers
Rev.0.60 2004.02.01 page 101 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer B
M16C/28 Group
Timer Bi register (i=0 to 2)(Note 1)
Symbol
TB0
TB1
Address
After reset
(b15)
b7
(b8)
b0 b7
039116, 039016 Indeterminate
039316, 039216 Indeterminate
039516, 039416 Indeterminate
b0
TB2
Function
Setting range
Mode
RW
Timer mode
Divide the count source by n + 1
where n = set value
000016 to FFFF16
RW
RW
Event counter
mode
Divide the count source by n + 1
where n = set value (Note 2)
000016 to FFFF16
Pulse period
modulation mode,
Measures a pulse period or width
RO
Pulse width
modulation mode
A-D trigger
mode (Note 3)
Divide the count source by n + 1 where
n = set value and cause the timer stop
000016 to FFFF16
RW
Note 1: The register must be accessed in 16 bit units.
Note 2: The timer counts pulses from an external device or overflows or underflows of other timers.
Note 3: When this mode is used combining delayed trigger mode 0, set the larger value than the
value of the timer B0 register to the timer B1 register.
Count start flag
Symbol
TABSR
Address
038016
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0S
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Clock prescaler reset flag
Symbol
CPSRF
Address
038116
After reset
0XXXXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
Bit name
Function
RW
RW
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
(b6-b0)
CPSR
Clock prescaler reset flag
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, the value of this bit is “0”.)
Figure 12.2.3. TB0 to TB2 Registers, TABSR Register, CPSRF Register
Rev.0.60 2004.02.01 page 102 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer B
M16C/28 Group
12.2.1 Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 12.2.1.1). Figure 12.2.1.1
shows TBiMR register in timer mode.
Table 12.2.1.1 Specifications in Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1) n: set value of TBi register (i= 0 to 2)
000016 to FFFF16
(Note)
Count start condition
Count stop condition
Set TBiS bit
to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Read from timer
Write to timer
I/O port
Count value can be read by reading TBi register
•
When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Note : The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7.
Timer Bi mode register (i= 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB0MR to TB2MR
Address
039B16 to 039D16
After reset
00XX00002
0
0
Bit symbol
Bit name
Function
0 0 : Timer mode or A-D trigger mode
RW
RW
RW
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
RW
RW
Has no effect in timer mode
Can be set to “0” or “1”
MR1
TB0MR register
Must be set to “0” in timer mode
MR2
RW
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3
When write in timer mode, set to “0”. When read in timer mode, its
content is indeterminate.
RO
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
1
8
or f2
RW
RW
0 1 : f
1 0 : f32
1 1 : fC32
Figure 12.2.1.1 TBiMR Register in Timer Mode
Rev.0.60 2004.02.01 page 103 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer B
M16C/28 Group
12.2.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 12.2.2.1) . Figure 12.2.2.1 shows TBiMR register in event counter mode.
Table 12.2.2.1 Specifications in Event Counter Mode
Item
Specification
• External signals input to TBiIN pin (i=0 to 2) (effective edge can be selected
in program)
Count source
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0)
• Down-count
Count operation
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1)
n: set value of TBi register
000016 to FFFF16
1
Count start condition
Count stop condition
Set TBiS bit to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Read from timer
Write to timer
Count source input
Count value can be read by reading TBi register
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Notes:
1. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
TB0MR to TB2MR 039B16 to 039D16
00XX00002
0
1
RW
RW
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
0 1 : Event counter mode
RW
b3 b2
Count polarity select
bit (Note 1)
0 0 : Counts external signal's
falling edges
RW
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set
MR1
MR2
RW
RW
TB0MR register
Must be set to “0” in timer mode
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate.
MR3
RO
Has no effect in event counter mode.
Can be set to “0” or “1”.
TCK0
TCK1
RW
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0)
Event clock select
RW
Note 1: Effective when the TCK1 bit = “0” (input from TBiIN pin). If the TCK1 bit = “1” (TBj overflow or underflow), these
bits can be set to “0” or “1”.
Note 2: The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Figure 12.2.2.1 TBiMR Register in Event Counter Mode
Rev.0.60 2004.02.01 page 104 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer B
M16C/28 Group
12.2.3 Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 12.2.3.1). Figure 12.2.3.1 shows TBiMR register in pulse period and pulse
width measurement mode. Figure 12.2.3.2 shows the operation timing when measuring a pulse period.
Figure 12.2.3.3 shows the operation timing when measuring a pulse width.
Table 12.2.3.1 Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of mea-
surement pulse. The counter value is set to “000016” to continue counting.
3
Count start condition
Count stop condition
Set TBiS (i=0 to 2) bit to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
1
Interrupt request generation timing • When an effective edge of measurement pulse is input
• Timer overflow. When an overflow occurs, MR3 bit of TBiMR register is set
to “1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no overflow) by
writing to TBiMR register at the next count timing or later after MR3 bit was
set to “1”. At this time, make sure TBiS bit is set to “1” (start counting).
Measurement pulse input
TBiIN pin function
Read from timer
Write to timer
Notes:
Contents of the reload register (measurement result) can be read by reading TBi register2
Value written to TBi register is written to neither reload register nor counter
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.
3. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB0MR to TB2MR
Address
039B16 to 039D16
After reset
00XX00002
1
0
Bit symbol
TMOD0
Bit name
Function
RW
RW
RW
b1 b0
Operation mode
select bit
1 0 : Pulse period / pulse width
measurement mode
TMOD1
MR0
b3 b2
Measurement mode
select bit
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
RW
MR1
MR2
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Must not be set.
RW
RW
TB0MR register
Must be set to “0” in pulse period and pulse width measurement mode
TB1MR, TB2MR registers
Nothing is assigned. When write, set to “0”. When read, its content turns out to be
indeterminate.
Timer Bi overflow
flag ( Note)
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
MR3
RO
TCK0
Count source
select bit
RW
0 0 : f
0 1 : f
1
8
or f2
1 0 : f32
1 1 : fC32
TCK1
RW
Note: This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to “0” (no overflow) by writing
to the TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit cannot be set to
“1” in a program. The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7.
Figure 12.2.3.1 TBiMR Register in Pulse Period and Pulse Width Measurement Mode
Rev.0.60 2004.02.01 page 105 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer B
M16C/28 Group
Count source
“H”
“L”
Measurement pulse
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
TBiS bit
“1”
“0”
TBiIC register's
IR bit
Set to “0” upon accepting an interrupt request or by writing in
program
“1”
“0”
TBiMR register's
MR3 bit
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7.
i = 0 to 2
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “00
from falling edge to falling edge of the measurement pulse).
2” (measure the interval
Figure 12.2.3.2 Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
“L”
Transfer
(measured value)
Transfer
(measured value)
Transfer
(indeterminate
value)
Transfer
(measured
value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
TBiS bit
“1”
“0”
TBiIC register's
IR bit
Set to “0” upon accepting an interrupt request or by
writing in program
“1”
“0”
TBiMR register's
MR3 bit
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7.
i = 0 to 2
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “10
2” (measure the interval
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
Figure 12.2.3.3 Operation timing when measuring a pulse width
Rev.0.60 2004.02.01 page 106 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer B
M16C/28 Group
12.2.4 A-D Trigger Mode
A-D trigger mode is used as conversion start trigger for A-D converter in simultaneous sample sweep
mode of A-D conversion or delayed trigger mode 0. This mode is used as conversion start trigger of A-D
converter. A-D trigger mode is used in timer B0 and timer B1. In this mode, the timer is activated only by
one trigger. A-D trigger mode is available only for timer B0 and time B1. Figure 12.2.4.1 shows the TBiMR
register in A-D trigger mode and figure 12.2.4.2 shows the TB2SC register.
Table 12.2.4.1 Specifications in A-D Trigger Mode
Item
Specification
Count Source
f1, f2, f8, f32, and fC32
Count Operation
• Down count
• When the timer underflows, reload register contents are reloaded before
stopping counting
• When a trigger is generated during the count operation, the count is not
affected
Divide Ratio
1/(n+1) n: Setting value of TBi register (i=0,1)
000016-FFFF16
Count Start Condition
When the TBiS (i=0,1) bit in the TABSR register is "1"(count started),
TBiEN(i=0,1) in TB2SC register is "1" and the following trigger is generated.
(Selection based on TB2SEL, TBiTRIG (i=0,1) bits of TB2SC)
• Timer B2 overflow or underflow
• Underflow of Timer B2 interrupt generation frequency counter setting
• After the count value is 000016 and reload register contents are reloaded
• Set the TBiS bit to "0"(count stopped)
Count Stop Condition
Interrupt Request
Timer underflows (Note 1)
Generation Timing
TBiIN Pin Function
Read From Timer
I/O port
Count value can be read by reading TBi register
• When writing in the TBi register during count stopped.
Value is written to both reload register and counter
• When writing in the TBi register during count.
Value is written to only reload register (Transfered to counter when reloaded next)
Write To Timer (Note 2)
Note 1: A-D conversion is started by the timer underflow.
For details refer to Section 14. A-D Converter.
Note 2: When using in delayed trigger mode 0, set the larger value than the value of the timer B0 register
to the timer B1 register.
Rev.0.60 2004.02.01 page 107 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.2 Timer B
M16C/28 Group
Timer Bi mode register (i= 0 to 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB0MR to TB1MR
Address
039B16 to 039C16
After reset
00XX00002
0
0
Bit symbol
Bit name
Function
0 0 : Timer mode or A-D trigger mode
RW
RW
RW
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
RW
RW
Invalid in A-D trigger mode
Either "0" or "1" is enabled
MR1
TB0MR register
Set to “0” in A-D trigger mode
MR2
RW
TB1MR register
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3
When write in A-D trigger mode, set to “0”. When read in A-D
trigger mode, its content is indeterminate.
RO
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
1
8
or f2
RW
RW
0 1 : f
1 0 : f32
1 1 : fC32
Figure 12.2.4.1 TBiMR Register in Delayed Trigger Mode
(Note 1)
Timer B2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2SC
Address
039E16
After reset
X0000000
2
RW
Bit symbol
PWCOM
Bit name
Function
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 Reload Timing
RW
(Note 2)
Switch Bit
Three-Phase Output Port 0 : Three-phase output forcible cutoff
IVPCR1
SD Control Bit 1
(Note 3, 4, 7)
by SD pin input (high impedance)
disabled
RW
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
Timer B0 Operation Mode 0 : Other than A-D trigger mode
Select Bit 1 : A-D trigger mode
TB0EN
TB1EN
RW
RW
RW
(Note 5)
Timer B1 Operation Mode 0 : Other than A-D trigger mode
Select Bit
1 : A-D trigger mode
(Note 5)
(Note 6)
TB2SEL Trigger Select Bit
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
Reserved bits
(b6-b5)
Must set to "0"
RW
Nothing is assigned. When write, set to 0 .
When read, its content is 0 .
(b7)
Note 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
Note 2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set
this bit to "0" (timer B2 underflow).
Note 3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5
bit to "0" (= input mode).
Note 4. Related pins are U(P8
0), U(P8
1), V(P72), V(P7
3), W(P7
4), W(P7
5). After forcible cutoff, input "H" to the P8
5/NMI/SD pin.
Set the IVPCR1 bit to "0", and this forcible cutoff will be reset. If L is input to the P8
5/NMI/SD pin, a three-phase motor
control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is "0", the target pins changes to
programmable I/O port. When the IVPCR1 bit is "1", the target pins changes to high-impedance state regardless of
which functions of those pins are used.
Note 5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1" (A-D trigger mode).
Note 6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the INV02
bit to "1" (three-phase motor control timer function).
Note 7. Refer to "17.6 Digital Debounce function" for the SD input
Figure 12.2.4.2 TB2SC Register
Rev.0.60 2004.02.01 page 108 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.3 Three-phase Motor Control Timer Function
M16C/28 Group
12.3 Three-phase Motor Control Timer Function
Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.3.1 lists the
specifications of the three-phase motor control timer function. Figure 12.3.1 shows the block diagram for
three-phase motor control timer function. Also, the related registers are shown on Figure 12.3.2 to Figure
12.3.8.
Table 12.3.1. Three-phase Motor Control Timer Function Specifications
Item
Specification
___
___
___
Three-phase waveform output pin
Forced cutoff input (Note 1)
Used Timers
Six pins (U, U, V, V, W, W)
_____
Input “L” to SD pin
Timer A4, A1, A2 (used in the one-shot timer mode)
___
Timer A4: U- and U-phase waveform control
___
Timer A1: V- and V-phase waveform control
___
Timer A2: W- and W-phase waveform control
Timer B2 (used in the timer mode)
Carrier wave cycle control
Dead timer timer (3 eight-bit timer and shared reload register)
Dead time control
Output waveform
Triangular wave modulation, Sawtooth wave modification
Enable to output “H” or “L” for one cycle
Enable to set positive-phase level and negative-phase
level respectively
Carrier wave cycle
Triangular wave modulation: count source x (m+1) x 2
Sawtooth wave modulation: count source x (m+1)
m: Setting value of TB2 register, 0 to 65535
Count source: f1, f2, f8, f32, fC32
Three-phase PWM output width
Triangular wave modulation: count source x n x 2
Sawtooth wave modulation: count source x n
n: Setting value of TA4, TA1 and TA2 register (of TA4,
TA41, TA1, TA11, TA2 and TA21 registers when setting
the INV11 bit to “1”), 1 to 65535
Count source: f1, f2, f8, f32, fC32
Dead time
Count source x p, or no dead time
active disable function
p: Setting value of DTT register, 1 to 255
Count source: f1, f2, f1 divided by 2, f2 divided by 2
Eable to select “H” or “L”
Active level
Positive and negative-phase concurrent
Positive and negative-phases concurrent active disable
function
Positive and negative-phases concurrent active detect func-
tion
Interrupt frequency
For Timer B2 interrupt, select a carrier wave cycle-to-cycle
basis through 15 times carrier wave cycle-to-cycle basis
_____
Note 1: When three phase motor control function is enabled (INV02=1) P85 becomes SD. Do not use P85 for
_____
_____
GPIO. If__t_h__e SD fueature is not needed then P85/SD must always be driven high.
__
When _S_ D is driven low, INV03 (three phase output control bit) is cleared, pins U(P80), U(P81),
___
V(P72), V(P73), W(P74), W(P75) pins go back to GPIO mode and are controlled by their corresponding
_____
Port Direction and Data registers. In addition if bit IVPRC1 is set to 1 when SD is driven low pin P80,
P81, P72, P73, P74, P75 tri-state regardless of when function (3 phase, GPIO, or UART) is assigned to
them.
Related pins
P72/CLK2/TA1OUT/V/RXD1
_________ _________ ___
P73/CTS2/RTS2/TA1IN/V/TXD1
P74/TA2OUT/W
____
P75/TA2IN/W
P80/TA4OUT/U
___
P81/TA4IN/U
Rev.0.60 2004.02.01 page 109 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.3 Three-phase Motor Control Timer Function
Figure 12.3.1. Three-phase Motor Control Timer Functions Block Diagram
Rev.0.60 2004.02.01 page 110 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.3 Three-phase Motor Control Timer Function
M16C/28 Group
Three-phase PWM control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
Address
034816
After reset
0016
Bit symbol
INV00
Bit name
Description
RW
RW
Effective interrupt output
polarity select bit
0: ICTB2 counter incremented by 1 at
odd-numbered occurrences of a timer
B2 underflow
1: ICTB2 counter incremented by 1 at
even-numbered occurrences of a timer
B2 underflow
(Note 3)
Effective interrupt output
specification bit
0: ICTB2 counter incremented by 1 at a
timer B2 underflow
1: Selected by INV00 bit
INV01
RW
RW
(Note 2, Note 3)
Mode select bit
(Note 4) 0: Three-phase motor control timer
function unused
INV02
INV03
1: Three-phase motor control timer
function
Output control bit (Note 6) 0: Three-phase motor control timer output
disabled
(Note 5)
1: Three-phase motor control timer output
(Note 10)
RW
enabled
Positive and negative
phases concurrent output
disable bit
0: Simultaneous active output enabled
1: Simultaneous active output disabled
INV04
RW
RW
RW
Positive and negative
phases concurrent output
detect flag
0: Not detected yet
1: Already detected
(Note 7)
INV05
INV06
INV07
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
Modulation mode select
(Note 9)
bit
(Note 8)
Setting this bit to “1” generates a transfer
trigger. If the INV06 bit is “1”, a trigger for
the dead time timer is also generated.
The value of this bit when read is “0”.
Software trigger select bit
RW
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable). Note also that this register can
only be rewritten when timers A1, A2, A4 and B2 are idle.
Note 2: If this bit needs to be set to “1”, set any value in the ICTB2 register before writing to it.
Note 3: Effective when the INV11 bit is “1” (three-phase mode 1). If INV11 is “0” (three-phase mode 0), the ICTB2 counter is
incremented by “1” each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are set.
Note 4: Setting the INV02 bit to “1” activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter.
Note 5: When INV03="1"(three-phase motor control timer output enabled) P80, P81, P72, P73, P74, and P75 functionas U, U,
V, V, W, W
Note 6: The INV03 bit is set to “0” in the following cases:
• When reset
• When positive and negative go active (INV05="1") simultaneously while INV04 bit is “1”
• When set to “0” in a program
• When input on the SD pin changes state from “H” to “L” (The INV03 bit cannot be set to “1” when SD input is
“L”.)
INV03 is set to “0” when the SD pin changes from “H” to “L” regardless of the value of the INVCR1 bit.
INV03 is set to "0" when both INV04 bit and INV05 bit are "1".
Note 7: Can only be set by writing “0” in a program, and cannot be set to “1”.
Note 8: The effects of the INV06 bit are described in the table below.
Item
INV06=0
INV06=1
Mode
Sawtooth wave modulation mode
Transferred every transfer trigger
Triangular wave modulation mode
Transferred only once synchronously
with the transfer trigger after writing to
the IDB0 to IDB1 registers
Timing at which transferred from IDB0 to
IDB1 registers to three-phase output shift
register
Timing at which dead time timer trigger is
generated when INV16 bit is “0”
Synchronous with the falling edge of
timer A1, A2, or A4 one-shot pulse
Synchronous with the transfer
trigger and the falling edge of timer
A1, A2, or A4 one-shot pulse
Has no effect
INV13 bit
Effective when INV11 is “1” and INV06
is “0”
Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when INV10 is “1”
Note 9: If the INV06 bit is “1”, set the INV11 bit to “0” (three-phase mode 0) and set the PWCON bit to “0” (timer B2
reloaded by a timer B2 underflow).
Note 10: Individual pins can be disabled using PFCR register.
Figure 12.3.2. INVC0 Register
Rev.0.60 2004.02.01 page 111 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.3 Three-phase Motor Control Timer Function
Three-phase PWM control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC1
Address
034916
After reset
0
0016
Bit symbol
INV10
Bit name
Description
0: Timer B2 underflow
1: Timer B2 underflow and write to the
TB2 register
RW
RW
Timer A1, A2, A4 start
trigger signal select bit
Timer A1-1, A2-1, A4-1
control bit
0: Three-phase mode 0
1: Three-phase mode 1
(Note 3)
INV11
INV12
RW
RW
(Note 2)
Dead time timer count
source select bit
0 : f
1 : f
1
1
or f
2
divided by 2 or f
2
divided by 2
Carrier wave detect flag
0: Timer A output at even-numbered occ-
urrences (TA11, TA21, TA41 register
value counted)
(Note 4)
INV13
RO
1: Timer A output at odd-numbered occ-
urrences (TA1, TA2, TA4 register
value counted)
0 : Output waveform “L” active
1 : Output waveform “H” active
Output polarity control bit
Dead time invalid bit
INV14
INV15
RW
RW
0: Dead time timer enabled
1: Dead time timer disabled
Dead time timer trigger
select bit
0: Falling edge of timer A4, A1 or A2
one-shot pulse
1: Rising edge of three-phase output shift
register (U, V or W phase) output
INV16
RW
RW
(Note 5)
Reserved bit
This bit should be set to “0”
(b7)
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable). Note also that this
register can only be rewritten when timers A1, A2, A4 and B2 are idle.
Note 2: The effects of the INV11 bit are described in the table below.
Item
INV11=0
Three-phase mode 0
INV11=1
Mode
Three-phase mode 1
TA11, TA21, TA41 registers
INV00 bit, INV01 bit
Used
Effect
Not used
Has no effect. ICTB2 counted every time
timer B2 underflows regardless of
whether the INV00 to INV01 bits are set.
INV13 bit
Effective when INV11 bit is “1” and
INV06 bit is “0”
Has no effect
Note 3: If the INV06 bit is “1” (sawtooth wave modulation mode), set this bit to “0” (three-phase mode 0). Also, if the
INV11 bit is “0”, set the PWCON bit to “0” (timer B2 reloaded by a timer B2 underflow).
Note 4: The INV13 bit is effective only when the INV06 bit is “0” (triangular wave modulation mode) and the INV11 bit
is “1” (three-phase mode 1).
Note 5: If all of the following conditions hold true, set the INV16 bit to “1” (dead time timer triggered by the rising edge
of three-phase output shift register output)
• The INV15 bit is “0” (dead time timer enabled)
• When the INV03 bit is set to “1” (three-phase motor control timer output enabled), the Dij bit and DiBj bit (i:U,
V, or W, j: 0 to 1) have always different values (the positive-phase and negative-phase always output
different levels during the period other than dead time).
Conversely, if either one of the above conditions holds false, set the INV16 bit to “0” (dead time timer triggered
Figure 12.3.3. INVC1 Register
Rev.0.60 2004.02.01 page 112 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.3 Three-phase Motor Control Timer Function
M16C/28 Group
Three-phase output buffer register i (i=0, 1) (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IDB0
IDB1
Address
034A16
034B16
After reset
0016
0016
Bit name
Bit Symbol
Function
RW
RW
RW
DUi
DUBi
DVi
U phase output buffer i
U phase output buffer i
V phase output buffer i
Write the output level
0: Active level
1: Inactive level
When read, these bits show the
three-phase output shift register
value.
RW
DVBi
DWi
V phase output buffer i
W phase output buffer i
W phase output buffer i
RW
RW
RW
DWBi
Nothing is assigned. When write, set to “0”. When read, its
content is “0”.
(b7-b6)
Note: The IDB0 and IDB1 register values are transferred to the three-phase shift register by a transfer trigger. The
value written to the IDB0 register after a transfer trigger represents the output signal of each phase, and the
next value written to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents
the output signal of each phase.
Dead time timer (Note 1, Note 2)
b7
b0
Symbol
DTT
Address
034C16
After reset
??16
Setting range
1 to 255
RW
WO
Function
Assuming the set value = n, upon a start trigger the
timer starts counting the count source selected by
the INV12 bit and stops after counting it n times. The
positive or negative phase whichever is going from
an inactive to an active level changes at the same
time the dead time timer stops.
Note 1: Use MOV instruction to write to this register.
Note 2: Effective when the INV15 bit is “0” (dead time timer enable). If the INV15 bit is “1”, the dead time timer is
disabled and has no effect.
Timer B2 interrupt occurrences frequency set counter
b7
b3
b0
Symbol
ICTB2
Address
034D16
After reset
X?16
RW
Function
Setting range
1 to 15
If the INV01 bit is ì0î (ICTB2 counter counted every
time timer B2 underflows), assuming the set value
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow.
If the INV01 bit is ì1î (ICTB2 counter count timing
selected by the INV00 bit), assuming the set value
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow that meets the
WO
condition selected by the INV00 bit.
(Note)
Nothing is assigned. When write, set to "0". When read, its content is
indeterminate.
Note : Use MOV instruction to write to this register.
If the INV01 bit = ì1î, make sure the TB2S bit also = ì0î (timer B2 count stopped) when writing to this register.
If the INV01 bit = ì0î, although this register can be written even when the TB2S bit = ì1î (timer B2 count start),
do not write synchronously with a timer B2 underflow.
Figure 12.3.4. IDB0 Register, IDB1Register, DTT Register, and ICCTB2 Register
Rev.0.60 2004.02.01 page 113 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.3 Three-phase Motor Control Timer Function
Timer Ai, Ai-1 register (i=1, 2, 4) (Note 1, Note 2, Note 3, Note 4, Note 5)
Symbol
Address
After reset
TA1
TA2
TA4
038916-038816
038B16-038A16
038F16-038E16
????16
????16
????16
????16
????16
????16
(b15)
b7
(b8)
b0 b7
b0
TA11 (Note6,7) 034316-034216
TA21 (Note6,7) 034516-034416
TA41 (Note6,7) 034716-034616
Function
Setting range
RW
WO
000016 to FFFF16
Assuming the set value = n, upon a start trigger the timer
starts counting the count source and stops after counting
it n times. The positive and negative phases change at
the same time timer A, A2 or A4 stops.
Note 1: The register must be accessed in 16 bit units.
Note 2: When the timer Ai register is set to "000016", the counter does not operate and a timer Ai interrupt does
not occur.
Note 3: Use MOV instruction to write to these registers.
Note 4: If the INV15 bit is "0" (dead time timer enable), the positive or negative phase whichever is going from an
inactive to an active level changes at the same time the dead time timer stops.
Note 5: If the INV11 bit is "0" (three-phase mode 0), the TAi register value is transferred to the reload register by
a timer Ai (i = 1, 2 or 4) start trigger.
If the INV11 bit is "1" (three-phase mode 1), the TAi1 register value is transferred to the reload register
by a timer Ai start trigger first and then the TAi register value is transferred to the reload register by the
next timer Ai start trigger. Thereafter, the TAi1 register and TAi register values are transferred to the
reload register alternately.
Note 6: Do not write to TAi1 registers synchronously with a timer B2 underflow I.n three-phase mode 1, do not set
TAi1 register while the timer B underflows.
.
Note 7: Write to the TAi1 register as follows:
(1) Write a value to the TAi1 register
(2) Wait for one cycle of timer Ai count source.
(3) Write the same value to the TAi1 register again.
Figure 12.3.5. TA1, TA2, TA4, TA11, TA21 and TA41 Registers
Rev.0.60 2004.02.01 page 114 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.3 Three-phase Motor Control Timer Function
M16C/28 Group
(Note 1)
Timer B2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2SC
Address
039E16
After reset
X0000000
2
RW
RW
Bit symbol
PWCOM
Bit name
Function
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 Reload Timing
(Note 2)
Switch Bit
Three-Phase Output Port 0 : Three-phase output forcible cutoff
IVPCR1
SD Control Bit 1
(Note 3, 4, 7)
by SD pin input (high impedance)
disabled
RW
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
Timer B0 Operation Mode 0 : Other than A-D trigger mode
Select Bit 1 : A-D trigger mode
TB0EN
TB1EN
RW
RW
RW
(Note 5)
Timer B1 Operation Mode 0 : Other than A-D trigger mode
Select Bit
1 : A-D trigger mode
(Note 5)
(Note 6)
TB2SEL Trigger Select Bit
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
Reserved bits
(b6-b5)
Must set to "0"
RW
Nothing is assigned. When write, set to 0 .
When read, its content is 0 .
(b7)
Note 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
Note 2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set
this bit to "0" (timer B2 underflow).
Note 3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5
bit to "0" (= input mode).
Note 4. Related pins are U(P8
0), U(P81), V(P72), V(P73), W(P74), W(P75). After forcible cutoff, input "H" to the P85/NMI/SD pin.
Set the IVPCR1 bit to "0", and this forcible cutoff will be reset. If L is input to the P85/NMI/SD pin, a three-phase motor
control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is "0", the target pins changes to
programmable I/O port. When the IVPCR1 bit is "1", the target pins changes to high-impedance state regardless of
which functions of those pins are used.
Note 5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1" (A-D trigger mode).
Note 6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the INV02
bit to "1" (three-phase motor control timer function).
Note 7. Refer to "17.6 Digital Debounce function" for the SD input
The effect of P8
5/NMI/SD pin input is below.
1.Case of INV03 = "1"(Three-phase motor control timer output enabled)
P8
5
/NMT/SD pin inputs
IVPCR1 bit
status of U/V/W pins
Remarks
(Note 3)
"1"
H
Three-phase PWM output
High impedance
(Three-phase output
forcrible cutoff enable)
Three-phase output
forcrible cutoff
L(Note 1)
H
"0"
Three-phase PWM output
Input/output port(Note 2)
(Three-phase output
forcrible cutoff disable)
L(Note 1)
Note 1: When "L" is input to the P8
Note 2: The value of the port register and the port direction register becomes effective.
Note 3: When SD function isn’t used, set to "0"(Input) in PD8 and pullup to "H" in P8
5/NMI/SD pin, INV03 bit changes in "0" at the same time.
5
5/NMI/SD pin from outside.
2.Case of INV03 = "0"(Three-phase motor control timer output disabled)
status of U/V/W pins
Remarks
IVPCR1 bit
P85/NMT/SD pin inputs
peripheral input/output
or input/output port
"1"
H
L
(Three-phase output
forcrible cutoff enable)
Three-phase output
forcrible cutoff(Note 1)
High impedance
peripheral input/output
or input/output port
peripheral input/output
or input/output port
"0"
H
L
(Three-phase output
forcrible cutoff disable)
Note 1: The three-phase output forcrible cutoff function becomes effective if the INPCR1 bit is "1" (three-phase
output forcrible cutoff function enable) even when INV03 bit is "0"(three-phase motor control timer output
disalbe)
Figure 12.3.6. TB2SC Registers
Rev.0.60 2004.02.01 page 115 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.3 Three-phase Motor Control Timer Function
Timer B2 register (Note )
Symbol
TB2
Address
039516-039416
After reset
Indeterminate
(b15)
(b8)
b0
b7
b0 b7
Function
Setting range
RW
RW
000016 to FFFF16
Divide the count source by n + 1 where n = set value.
Timer A1, A2 and A4 are started at every occurrence of
underflow.
Note : The register must be accessed in 16 bit units.
Trigger select register
b7 b6 b5 b4 b3 b2 b1
b0
Symbol
TRGSR
Address
038316
After reset
0016
Bit symbol
TA1TGL
Bit name
Function
To use the V-phase output control
RW
RW
Timer A1 event/trigger
select bit
circuit, set these bits to “012”(TB2
underflow).
TA1TGH
TA2TGL
RW
Timer A2 event/trigger
select bit
To use the W-phase output control
circuit, set these bits to “012”(TB2
RW
RW
RW
RW
underflow).
TA2TGH
TA3TGL
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (Note 1)
0 1 : TB2 overflow is selected (Note 2)
1 0 : TA2 overflow is selected (Note 2)
1 1 : TA4 overflow is selected (Note 2)
TA3TGH
TA4TGL
TA4TGH
To use the U-phase output control
circuit, set these bits to “012”(TB2
underflow).
Timer A4 event/trigger
select bit
RW
RW
Note 1: Set the corresponding port direction bit to “0” (input mode).
Note 2: Overflow or underflow.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
After reset
0016
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
RW
RW
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
RW
RW
RW
RW
RW
RW
RW
Figure 12.3.7. TB2 Register, TRGSR Register, and TABSR Register
Rev.0.60 2004.02.01 page 116 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
12.3 Three-phase Motor Control Timer Function
M16C/28 Group
Timer Ai mode register
Symbol
TA1MR
TA2MR
TA4MR
Address
039716
039816
039A16
After reset
b7 b6 b5 b4 b3 b2 b1 b0
0016
0016
0016
0
1
0
0
1
Bit symbol
Bit name
Function
RW
RW
RW
TMOD0
TMOD1
MR0
Must set to “10
2
” (one-shot timer mode) for
the three-phase motor control timer function
Operation mode
select bit
Must set to “0” for the three-phase motor
control timer function
Pulse output function
select bit
MR1
MR2
Has no effect for the three-phase motor
control timer function
External trigger select
bit
RW
RW
Trigger select bit
Must set to “1” (selected by event/trigger
select register) for the three-phase motor
control timer function
MR3
Must set to “0” for the three-phase motor control timer function
RW
RW
b7 b6
0 0 : f
TCK0
Count source select bit
1
8
or f2
0 1 : f
1 0 : f32
1 1 : fC32
TCK1
RW
Timer B2 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2MR
Address
039D16
After reset
00XX0000
0
0
0
2
Bit symbol
Bit name
RW
RW
RW
Function
TMOD0
TMOD1
MR0
Set to “00
2
” (timer mode) for the three-
phase motor control timer function
Operation mode select bit
RW
RW
Has no effect for the three-phase motor control timer function.
When write, set to “0”. When read, its content is indeterminate.
MR1
Must set to “0” for the three-phase motor control timer function
MR2
MR3
RW
RO
When write in three-phase motor control timer function, write “0”.
When read, its content is indeterminate.
b7 b6
Count source select bit
TCK0
TCK1
RW
RW
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
or f2
Figure 12.3.8. TA1MR, TA2MR, TA4MR, and TB2MR Registers
Rev.0.60 2004.02.01 page 117 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.3 Three-phase Motor Control Timer Function
The three-phase motor control timer function is enabled by setting the INV02 bit of INVC0 register to “1”.
When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used
__
___
___
to control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated
dead-time timer. Figure 12.3.9 shows the example of triangular modulation waveform, and Figure 12.3.10
shows the example of sawtooth modulation waveform.
Carrier wave
Signal wave
TB2S bit of the
TABSR register
Timer B2
Start trigger signal
for timer A4*
p
p
n
n
m
m
Timer A4
one-shot pulse*
Rewriting IDB0, IDB1 registers
U phase
output signal *
Transfer to three-phase
output shift register
U phase
output signal *
U phase
INV14 = 0
(“L” active)
U phase
U phase
Dead time
INV14 = 1
(“H” active)
Dead time
U phase
INV13
(INV11=1(three-phase
mode 1))
* Internal signals. See the block diagram of the three-phase motor control timer function.
Shown here is a typical waveform for the case where INVC0 = 00XX11XX
An example for changing PWM outputs is shown below.
2 (X = set as suitable for the system) and INVC1 = 010XXXX02.
(1)When INV11=1(three-phase mode 1)
(2)When INV11=0(three-phase mode 0)
· INV01=0, ICTB2=216(timer B2 interrupt is generated at every 2’th
occurrence of a timer B2 underflow), or INV01=1, INV00=1,
ICTB2=116(timer B2 interrupt is generated at even-numbered
occurrences of a timer B2 underflow).
· Initial timer value: TA41=m, TA4=m. The TA4 and TA41 registers
are modified every time a timer B2 interrupt occurs. First time,
TA41= n, TA4 = n. Second time, TA41 = p, TA4 = p.
· Initial values of IDB0 and IDB1 registers: DU0 = 1, DUB0 = 0,
DU1 = 0, DUB1 = 1.The register values are changed to DU0 = 1,
DUB0 = 0, DU1= 1 and DUB1 = 0 the third time a timer B2
interrupt occurs.
· INV01=0, ICTB2=116(timer B2 interrupt is generated at every
occurrence of a timer B2 underflow)
· Initial timer value: TA4 = m. The TA4 register is modified each time
a timer B2 interrupt occurs. First time, TA4 = m. Second time, TA4 = n.
Third time, TA4 = n. Fourth time, TA4 = p. Fifth time, TA4 = p.
· Initial values of IDB0 and IDB1 registers: DU0=1, DUB0=0, DU1=0,
DUB1=1.The register values are changed to DU0 = 1, DUB0 = 0, DU1=
1 and DUB1 = 0 the sixth time a timer B2 interrupt occurs.
The value written to the TA4 register and TA41 register are inverted at odd-numbered timer A outputs.
Figure 12.3.9. Triangular Wave Modulation Operation
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Preliminary specification
Specifications in this manual are tentative and subject to change.
12.3 Three-phase Motor Control Timer Function
M16C/28 Group
Carrier wave: sawtooth waveform
Carrier wave
Signal wave
Timer B2
Start trigger signal
for timer A4*
Timer A4
one-shot pulse*
Rewriting IDB0, IDB1 registers
Transfer to three-phase
output shift register
U phase
output signal *
U phase
output signal *
U phase
U phase
INV14 = 0
(“L” active)
Dead time
Dead time
U phase
U phase
INV14 = 1
(“H” active)
* Internal signals. See the block diagram of the three-phase motor control timer function.
Shown here is a typical waveform for the case where INVC0= 01XX110X2 (X = set as suitable for the
system) and INVC1 = 010XXX00 . An example for changing PWM outputs is shown below.
2
• Initial values of IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1. The register values are
changed to DU0=1, DUB0=0, DU1=1, DUB1=1 a timer B2 interrupt occurs.
Figure 12.3.10. Sawtooth Wave Modulation Operation
Rev.0.60 2004.02.01 page 119 of N
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
12.3 Three-phase Motor Control Timer Function
12.3.1 Position-data-retain Function
This function is used to retain the position data synchronously with the three-phase waveform
output.There are three position-data input pins for U, V, and W phases.
A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected
by the retain-trigger polarity select bit(bit 3 of the position-data-retain function control register, at address
034E16). This bit selects the retain trigger to be the falling edge of each positive phase, or the rising edge
of each positive phase.
12.3.1.1 Operation of the Position-data-retain Function
Figure 12.3.1.1.1 shows a usage example of the position-data-retain function (U phase) when the
retain trigger is selected as the falling edge of the positive signal.
(1) At the falling edge of the U-phase waveform ouput, the state at pin IDU is transferred to the U-
phase position data retain bit ( bit2 at address 034E16 ).
(2) Until the next falling edge of the Uphase waveform output,the above value is retained.
1
2
Carrier wave
U-phase waveform output
U-phase waveform output
Pin IDU
Transferred
Transferred
Transferred
Transferred
U-phase position data retain bit
(bit 2 at address 034E16
)
Note: The retain trigger is the falling edge of the positive signal.
Figure 12.3.1.1.1 Usage Example of Position-data-retain Function ( U phase )
Rev.0.60 2004.02.01 page 120 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
12.3 Three-phase Motor Control Timer Function
M16C/28 Group
12.3.1.2 Position-data-retain Function Control Register
Figure 12.3.1.2.1 shows the structure of the position-data-retain function contol register.
Position-data-retain function control register (Note)
b7
b3 b2 b1 b0
Symbol
PDRF
Address
034E16
When reset
XXXX 0000
2
Bit
Bit name
Function
RW
RO
Input level at pin IDW is read out.
0: "L" level
W-phase position
data retain bit
PDRW
1: "H" level
Input level at pin IDV is read out.
0: "L" level
1: "H" level
V-phase position
data retain bit
PDRV
PDRU
PDRT
(b7-b4)
RO
RO
RW
Input level at pin IDU is read out.
0: "L" level
1: "H" level
U-phase position
data retain bit
Retain-trigger
polarity select bit
0: Rising edge of positive phase
1: Falling edge of positive phase
Nothing is assigned. When write, set to ì0î. When read,
contents are indeterminate.
Note: This register is valid only in the three-phase mode.
Figure 12.3.1.2.1. Structure of Position-data-retain Function Control Register
12.3.1.2.1 W-phase Position Data Retain Bit (PDRW)
This bit is used to retain the input level at pin IDW.
12.3.1.2.2 V-phase Position Data Retain Bit (PDRV)
This bit is used to retain the input level at pin IDV.
12.3.1.2.3 U-phase Position Data Retain Bit (PDRU)
This bit is used to retain the input level at pin IDU.
12.3.1.2.4 Retain-trigger Polarity Select Bit (PDRT)
This bit is used to select the trigger polarity to retain the position data.
When this bit = "0", the rising edge of each positive phase selected.
When this bit = "1", the falling edge of each pocitive phase selected.
Rev.0.60 2004.02.01 page 121 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
13. Timer S (Input Capture/Output Compare)
The Timer S (Input Capture/Output Compare : here after, Timer S is referred to as "IC/OC".) is a multi-
functional I/O port for time measurement and waveform generation. Each channel of the IC/OC module
provides the capability for time measurement, by input capture, and also provides the capability for wave-
form generation, by output comparison.
The IC/OC consists of one 16-bit base timer for free-running operation, as well as eight 16-bit registers for
time measurement and waveform generation.
Table 13.1 lists functions and channels of the IC/OC.
Table 13.1. IC/OC Functions and Channels
Function
Time measurement (Note 1)
Digital filter
8 channels
8 channels
2 channels
2 channels
8 channels
Available
Trigger input prescaler
Trigger input gate
Waveform generation (Note 1)
Single-phase waveform output
Phase-delayed waveform output
Set/Reset waveform output
Available
Available
Notes 1 : The time measurement function shares pins with the waveform generation function.
The time measurement function or waveform generation function can be selected for each channel.
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
Figure 13.1 shows the block diagram of the IC/OC.
PCLK0=0
1/2
Main clock,
PLL clock,
Ring oscillator
clock
f1 or f2
PCLK0=1
Request by matching G1BTRR and base timer
Request by matching G1PO0 register and base timer
Base timer reset
Request from INT1 pin
BTS
BCK1 to BCK0
11
(n+1)
f
1
or f
2
f
BT1
Divider register
Base timer over flow request
Base timer
Two-phase
10
(G1DV)
pulse input
Base timer interrupt request
Base timer reset
register (G1BTRR)
Base timer reset request
00
10:fBT1
G1TM0, G1PO0
Digital
filter
11: f
1
or f
2
Edge
select
OUTC1
OUTC1
OUTC1
OUTC1
OUTC1
0
1
2
3
4
INPC1
0
(Note 1)
register
DF1 to DF0
00
PWM
output
CTS1 to CTS0
10:fBT1
11: f or f
G1TM1, G1PO1
register
Digital
filter
Edge
select
1
2
INPC1
INPC1
INPC1
1
DF1 to DF0
00
CTS1 to CTS0
10:fBT1
11: f or f
G1TM2, G1PO2
register
Digital
filter
1
2
Edge
select
2
3
DF1 to DF0
00
PWM
output
CTS1 to CTS0
10:fBT1
11: f1 or f2
G1TM3, G1PO3
register
Digital
filter
Edge
select
DF1 to DF0
00
CTS1 to CTS0
10:fBT1
11: f1 or f2
G1TM4, G1PO4
register
Digital
filter
Edge
select
INPC1
4
DF1 to DF0
00
CTS1 to CTS0
PWM
output
10:fBT1
11: f or f
1
2
G1TM5, G1PO5
register
Digital
filter
Edge
select
INPC1
5
OUTC1
5
DF1 to DF0
00
CTS1 to CTS0
0
0
10:fBT1
11: f or f
1
2
G1TM6, G1PO6
register
Digital
filter
Gate
function
Prescaler
function
1
1
Edge
select
1
OUTC1
6
7
INPC1
6
DF1 to DF0
00
GT
0
PR
0
PWM
output
CTS1 to CTS0
10:fBT1
11: f or f
1
2
G1TM7, G1PO7
register
Gate
function
1
Prescaler
function
Digital
filter
Edge
select
Digital
debounce
OUTC1
INPC1
7
DF1 to DF0
GT
PR
CTS1 to CTS0
Ch0 to ch7
interrupt request signal
BCK1 to BCK0 : Bits in the G1BCR0 register
BTS: Bits in the G1BCR1 register
CTS1 to CTS0, DF1 to DF0, GT, PR : Bits in the G1TMCRj register (j= 0 to 7)
PCLK0 : Bits in the PCLKR register
Figures 13.1. IC/OC Block Diagram
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
Figures 13.2 to 13.11 show registers associated with the IC/OC base timer, the time measurement function,
and the waveform generation function.
Base timer register(Note 1)
b15
(b7)
b8
(b0) b7
b0
Symbol
G1BT
Address
When reset
????16
032116 - 032016
Setting range
Function
RW
When the base timer is operating:
When read, value of the counter can be read.
When write, the counter starts counting from the
value written. When the base timer is reset, this
register is set to "000016". (Note 2)
000016 to FFFF16 RW
When the base timer is reset:
This register is set to "000016" but a value read
is indeterminate. No value is written. (Note 2)
Note 1: The value which is written in this register is reflected synchronizing with the base timer count source fBT1
Note 2: This base timer stops only when the BCK1 to BCK0 bits in the G1BCR0 register are set to "00 " (count
source clock stop). This base timer operates when the BCK1 to BCK0 bits are set to other than "00 ".
.
2
2
When the BTS bit in the G1BCR1 register is set to "0", the base timer continues to be held in reset, and
remains in a no counting state with a value of "000016". When the BTS bit in the G1BCR1 register is
set to "1", this state is cleared and the timer starts counting.
Base timer control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
032216
When reset
0000 0000
G1BCR0
2
0 0 0
Bit
Bit name
Function
RW
RW
symbol
b1b0
BCK0
0 0
0 1
1 0
1 1
: Clock stop
: Avoid this setting
: Two-phase input (Note 1)
: f or f (Note 2)
Count source
select bit
BCK1
RST4
RW
RW
1
2
0: Base timer not reset by matching
G1BTRR
1: Base timer reset by matching
G1BTRR
Base timer reset
cause select bit 4
Reserved bit
Should be set to 0"
RW
RW
(b5-b3)
CH7INSEL
IT
Channel 7 Input
select bit
0: P27/OUTC17/INPC1
7 pin
/IDU pin
1: P1
7
/INT5/INPC1
7
Base timer
overflow select bit 1: Bit 14 overflow
0: Bit 15 overflow
RW
Note 1: This setting can be used when the UD1 to UD0 bits in the G1BCR1 register are set to "10
phase signal processing mode). Avoid setting the BCK1 to BCK0 bits to "10
Note 2: When the PCLK0 bit in the PCLKR register is set to "0", the Count source is f
is set to "1", the Count source is f
2
" (two-
2
" in other modes.
. And when this bit
2
1.
Figure 13.2. G1BT and G1BCR0 Registers
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
Divider register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
G1DV
Address
032A16
When reset
0016
Function
Divide ratio of f1, f2 or two pulse input by (n+1)
Setting range
0016 to FF16
RW
RW
for fBT1
.
n: this register detemines
Figure 13.3. G1DV Register
Rev.0.60 2004.02.01 page 125 of N
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
Base timer control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
032316
When reset
G1BCR1
0000 00002
0
0
0
Bit
Bit name
Function
RW
RW
symbol
(b0)
Reserved bit
Should be set to "0".
0: The base timer is not reset by
matching the G1PO0 register
1: The base timer is reset by matching
the G1PO0 register (Note 1)
Base timer reset
cause select bit 1
RST1
RST2
RW
RW
0: The base timer is not reset when an
input to the INT1 pin is "L" level
1: The base timer is reset when an input
to the INT1 pin is "L" level
Base timer reset
cause select bit 2
Reserved bit
Should set to "0".
RW
RW
RW
RW
(b3)
BTS
Base timer
start bit
0: Base timer is reset
1: Base timer starts counting
b6b5
0 0 : Counter increment mode
0 1 : Counter increment/decrement mode
1 0 : Two-phase pulse signal processing
mode
UD0
UD1
Counter increment/
decrement control bit
1 1 : Avoid this setting
Reserved bit
Should set to "0".
RW
(b7)
Note 1: The base timer is reset after two clock cycles of fBT1 when it matches the G1PO0 register. (See
Figure 13.8 about the G1PO0 register.) When setting the RST1 bit to "1", values of the G1POj
register (j=1 to7) to use for the waveform generation function should be set to smaller value than
values of the G1PO0 register.
Figure 13.4. G1BCR1 Register
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
Base timer reset register(Note 1)
b15
(b7)
b8
(b0) b7
b0
Symbol
G1BTRR
Address
032916 - 032816
When reset
????16
Function
Setting range
000016 to FFFF16
RW
RW
When enabled by the RST4 reset cause bit
(bit 2 of G1BCR0), the G1BTRR will reset the
Base Timer, G1BT, when G1BT matches
G1BTRR
Note 1: The value which is written in this register is reflected synchronizing with the base timer count source fBT1
.
Figure 13.5. G1BTRR Register
Rev.0.60 2004.02.01 page 127 of N
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
Time measurement control register j (j=0 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
G1TMCR0 to G1TMCR3
G1TMCR4 to G1TMCR7
031816, 031916, 031A16, 031B16
031C16, 031D16, 031E16, 031F16
0000 0000
2
0000 0000
2
Bit
Bit name
Function
RW
RW
symbol
b1 b0
CTS0
CTS1
0
0
1
1
0 : No time measurement
Time measurement
trigger select bit
1 : Rising edge
0 : Falling edge
1 : Both edges
RW
RW
RW
RW
RW
RW
RW
b3 b2
DF0
DF1
GT
0
0
1
1
0 : No digital filter
1 : Avoid this setting
0 : fBT1
Digital filter function
select bit
1 : f1 or f2 (Note 1)
Gate function
select bit (Note 2)
0 : Gate function not used
1 : Gate function used
0 : Not cleared
1 : The gate is cleared when the base
timer matches the G1POk register
Gate function clear
select bit (Notes 2, 3, 4)
GOC
GSC
PR
When setting the GSC bit to "1", the
gate is cleared.
Gate function clear
bit (Notes 2, 3)
Prescaler function
select bit (Note 2)
0 : Not used
1 : Used
Notes :
1. When the PCLK0 bit in the PCLKR register is set to "0", the Count source is f
set to "1", the Count source is f
2. And when this bit is
1.
2. This bit is in the G1TMCR6 and G1TMCR7 registers.
All bits 4 to 7 in the G1TMCR0 to G1TMCR5 registers should be set to "0".
3. These bits are available when setting the GT bit to "1".
3. The GOC bit is set to "0" after the gate function is cleared. See Figure 13.8 about the G1POk register
(k=4 when j=6 and k=5 when j=7).
Time measurement prescale register j (j=6,7)(Note 1)
b7
b0
Symbol
Address
When reset
0000 00002
G1TPR6 to G1TPR7 032416, 032516
Function
Setting range
0016 to FF16
RW
RW
As the setting value is n, time is measured when-
ever a trigger input is counted by n+1 (Note 2)
Note 1: The value which is written in this register is reflected synchronizing with the base timer count
source fBT1
Note 2: The first prescaler, after the PR bit in the G1TMCRj register changes "0" (prescaler function
unused) to "1" (prescaler function used), may be divided by n, not by n+1. Subsequent prescalers
.
Figure 13.6. G1TMCR0 to G1TMCR7 Registers, and G1TPR6 to G1TPR7 Registers
Rev.0.60 2004.02.01 page 128 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
Time measurement register j (j=0 to 7)
b8
b15
(b7)
(b0)b7
b0
Symbol
Address
When reset
G1TM0 to G1TM2
G1TM3 to G1TM5
G1TM6 to G1TM7
030116 - 030016, 030316 - 030216, 030516 - 030416
030716 - 030616, 030916 - 030816, 030B16 - 030A16
030D16 - 030C16, 030F16 - 030E16
????16
????16
????16
Function
Setting range
RW
RO
Value of the base timer is stored every time
measurement.
Waveform generation control register j (j=0 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
G1POCR0 to G1POCR3
G1POCR4 to G1POCR7
031016, 031116, 031216, 031316
031416, 031516, 031616, 031716
0X00 XX00
2
0X00 XX00
2
Bit
Bit name
Function
RW
RW
RW
symbol
b1b0
00: Single waveform output mode
01: SR waveform output mode
(Note 1)
10: Phase-delayed waveform
output mode
11: Avoid this setting
MOD0
Operation mode
select bit
MOD1
Nothing is assigned. When write, should set to "0".
When read, its content is indeterminate.
(b3-b2)
IVL
Output initial value
select bit
0: Outputs "L" as an initial value
1: Outputs "H" as an initial value
RW
RW
0: Reloads the G1POj register when
the CPU writes to a counter
1: Reloads the G1POj register when
the base timer is reset
GiPOj register value
reload timing select bit
RLD
Nothing is assigned. When write, should set to "0".
When read, its content is indeterminate.
(b6)
INV
Inverse output function 0: Output is not inversed
RW
select bit (Note 2)
1: Output is inversed
Notes :
1. This setting is enabled only on even channels. In SR waveform output mode, the values written to the
corresponding odd channel (next channel after an even channel) are ignored. An even channel
outputs waveform. An odd channel outputs no waveform.
2. The inverse output function is performed as a final step on a process of waveform generation. When
setting the INV bit to "1" (output inverse), "H" is output with setting the IVL bit to "0" (output "L" as an
initial value) and "L" with setting the IVL bit to "1" (output "H" as an initial value).
Figure 13.7. G1TM0 to G1TM7 Registers, and G1POCR0 to G1POCR7 Registers
Rev.0.60 2004.02.01 page 129 of N
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
Waveform generation register j (j=0 to 7)
b8
b15
(b7)
Symbol
Address
When reset
(b0)b7
b0
G1PO0 to G1PO2 030116-030016, 030316-030216, 030516-030416
G1PO3 to G1PO5 030716-030616, 030916-030816, 030B16-030A16
G1PO6 to G1PO7 030D16-030C16, 030F16-030E16
????16
????16
????16
Function
Setting range
RW
RW
When the RLD bit in the G1POCRj register
should be set to "0"
Value is reloaded into the G1POj register to
include it in output waveform, etc.
When the RLD bit should be set to "1"
Value is reloaded when the base timer is reset.
Value written can be read between writing the
value and reloaded.
000016 to FFFF16
Figure 13.8. G1PO0 to G1PO7 Registers
Rev.0.60 2004.02.01 page 130 of N
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
Function select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
G1FS
Address
032716
When reset
0000 0000
2
Bit
Bit name
Function
RW
RW
symbol
Channel 0 time measure-
ment/waveform generation
function select bit
0 : Select the waveform generation
function
1 : Select the time measurement
function
FSC0
Channel 1 time measure-
ment/waveform generation
function select bit
FSC1
FSC2
FSC3
FSC4
RW
RW
RW
RW
Channel 2 time measure-
ment/waveform generation
function select bit
Channel 3 time measure-
ment/waveform generation
function select bit
Channel 4 time measure-
ment/waveform generation
function select bit
Channel 5 time measure-
ment/waveform generation
function select bit
FSC5
FSC6
FSC7
RW
RW
RW
Channel 6 time measure-
ment/waveform generation
function select bit
Channel 7 time measure-
ment/waveform generation
function select bit
Function enable register(Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
032616
When reset
G1FE
0000 0000
2
Bit
symbol
Bit name
Function
RW
IFE0
IFE1
IFE2
RW
RW
RW
RW
RW
RW
RW
RW
Channel 0 function enable bit
Channel 1 function enable bit
Channel 2 function enable bit
0 : Channel functions disabled
1 : Channel functions enabled
IFE3 Channel 3 function enable bit
IFE4
IFE5
IFE6
IFE7
Channel 4 function enable bit
Channel 5 function enable bit
Channel 6 function enable bit
Channel 7 function enable bit
Note 1: The value which is written in this register is reflected synchronizing with the base timer count source fBT1
.
Figure 13.9. G1FS and G1FE Registers
Rev.0.60 2004.02.01 page 131 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
Interrupt request register (Notes 1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
G1IR
Address
033016
When reset
???? ????
2
Bit
Bit name
Function
RW
RW
RW
symbol
0 : No Request
1 : Interrupt Requested
G1IR0
Interrupt Request, Ch0
Interrupt Request, Ch1
G1IR1
G1IR2
G1IR3
G1IR4
G1IR5
G1IR6
G1IR7
Interrupt Request, Ch2
Interrupt Request, Ch3
Interrupt Request, Ch4
Interrupt Request, Ch5
Interrupt Request, Ch6
Interrupt Request, Ch7
RW
RW
RW
RW
RW
RW
Notes:
1. Interrupt Request for Base Timer is latched by the soft interrupt 7 ICR at address 0047h.
2. Each G1IRi (i = 0 to 7) is ANDed with its corresponding G1IEx (x = 0 to 1) to generate soft interrupt 5
or soft interrupt 6.
Figure 13.10. G1IR Register
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13. Timer S (Input Capture / Output Compare)
Interrupt enable register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
033116
When reset
G1IE0
0000 0000
2
Bit
Bit name
Function
RW
RW
RW
symbol
0 : IC/OC interrupt 0 request disable
1 : IC/OC interrupt 0 request enable
G1IE00 Interrupt Enable 0, CH0
G1IE01 Interrupt Enable 0, CH1
G1IE02 Interrupt Enable 0, CH2
G1IE03 Interrupt Enable 0, CH3
G1IE04 Interrupt Enable 0, CH4
G1IE05 Interrupt Enable 0, CH5
G1IE06 Interrupt Enable 0, CH6
G1IE07 Interrupt Enable 0, CH7
RW
RW
RW
RW
RW
RW
Interrupt enable register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
G1IE1
Address
033216
When reset
0000 0000
2
Bit
symbol
Bit name
Function
RW
RW
RW
0 : IC/OC interrupt 1 request disable
1 : IC/OC interrupt 1 request enable
G1IE10 Interrupt Enable 1, CH0
G1IE11 Interrupt Enable 1, CH1
G1IE12 Interrupt Enable 1, CH2
G1IE13 Interrupt Enable 1, CH3
G1IE14 Interrupt Enable 1, CH4
G1IE15 Interrupt Enable 1, CH5
G1IE16 Interrupt Enable 1, CH6
G1IE17 Interrupt Enable 1, CH7
RW
RW
RW
RW
RW
RW
Figure 13.11. G1IE0 and G1IE1 Registers
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13. Timer S (Input Capture / Output Compare)
13.1 Base Timer
The base timer counts an internally generated count source with free-running.
Table 13.1.1 lists specifications of the base timer. Table 13.1.2 shows registers associated with the base
timer. Figure 13.1.1 shows a block diagram of the base timer. Figure 13.1.2 shows an example of the base
timer in counter increment mode. Figure 13.1.3 shows an example of the base timer in counter increment/
decrement mode. Figure 13.1.4 shows an example of two-phase pulse signal processing mode.
Table 13.1.1. Base Timer Specifications
Item
Specification
Count source(fBT1)
f
1
or f
2
divided by (n+1) , two pulse input divided by (n+1)
n: The DIV7 to DIV0 bits in the G1DV register determines. n=0 to 255
In f1 and two pulse input when n=0, a count source is not divided
Counting operation
Count start condition
The base timer increments the counter
The base timer increments/decrements the counter (see the selectable function)
Two-phase pulse processing (see the selectable function)
• The base timer starts counting when the BTS bit in the G1BCR1 register is set
to "1"
Count stop condition
The BTS bit in the G1BCR1 register is set to "0" (base timer reset)
Base timer reset condition
(1) Value of the base timer matches value of the G1BTRR register
(2) Value of the base timer matches value of G1PO0 register.
(3) Apply a low-level signal ("L") to external interrupt pin,INT1 pin
Value for base timer reset
Interrupt request
"000016"
The base timer interrupt request is asserten:
(1) At bit 14 or bit 15 is overflow of the base timer
(2) Base timer value matches the base timer reset register, and the base
timer reset is enable (See Figure 13.1.1.)
Read from timer
Write to timer
• While the base timer is running,the G1BT register indicates a counter value
• When the base timer is reset, a counter value is indeterminate
When a value is written while the base timer is running, the value written is
counted first. No value can be written while the base timer is reset.
Selectable function
• Counter increment/decrement mode
The base timer starts counting in increment mode until reaching the
maximum count value. Then the base timer starts in decrement mode until
reaching next 000016. (See Figure 13.1.3.)
• Two-phase pulse processing mode.
Two-phase pulses from P8
0
and P8
1
pins are counted (See Figure 13.1.4.)
P80
P81
The timer increments
a counter on all edges
The timer decrements
a counter on all edges
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M16C/28 Group
13. Timer S (Input Capture / Output Compare)
fBT1
BCK1 to BCK0
11
10
f
1
or f2
(n+1) divider
Base timer
b14 b15
Two-phase pulse input
(Note 1)
Overflow signal
0
Base timer
overflow request
BTS bit in G1BCR1 register
1
RST4
RST1
RST2
IT
Matched with G1BTRR
Matched with G1PO0 register
Input "L" to INT1 pin
Base timer reset
Notes :
1. Divider is reset when setting BTS bit to "0".
IT, RST4, BCK1 to BCK0 : Bits in the G1BCR0 register
RST2 to RST1: Bits in the G1BCR1 register
Figure 13.1.1. Base Timer Block Diagram
Table 13.1.2. Base Timer Associated Register Settings (Time Measurement Function, Waveform
Generation Function, Communication Function)
Register
Bit
Function
G1BCR0
BCK1 to BCK0
Select a count source
RST4
IT
RST2 to RST1
Select base timer reset timing
Select the base timer overflow
Select base timer reset timing
G1BCR1
BTS
UD1 to UD0
Used when starting the base timer
Select how to count
G1BT
G1DV
-
-
Base timer value to read or to write
Divide ratio of a count source
When setting the RST1 bit to "1" (base timer reset when base timer matches G1PO0), the following registers require to be setup.
G1POCR0
MOD1 to MOD0
Set to "002" (single-phase waveform output mode)
G1PO0
G1FS
G1FE
-
Set reset cycle
Set to "0" (waveform generation function)
Set to "1" (channel operation start)
FSC0
IFE0
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13. Timer S (Input Capture / Output Compare)
FFFF16
C00016
State of a counter
800016
400016
000016
IT=1 in the G1BCR0 register
(Base timer interrupt generated
by the bit 14 overflow)
"1"
"0"
b14 overflow signal
Base Timer interrupts
IT=0 in the G1BCR0 register
(Base timer interrupt generated
by the bit 15 overflow)
"1"
"0"
b15 overflow signal
Base Timer interrupt
The above applies to the following conditions.
The RST4 bit in the G1BCR0 register is set to "0" (the base timer is not reset by
matching the G1BTRR register)
The RST1 bit in the G1BCR1 register is set to "0" (the base timer is not reset by
matching the G1PO0 register)
The UD1 to UD0 bits in the G1BCR1 register are set to "002" (counter increment mode)
Figure 13.1.2. Counter Increment Mode
FFFF16
C00016
800016
State of a counter
400016
000016
IT=1 in the G1BCR0 register
(Base timer interrupt generated
by the bit 14 overflow)
"1"
"0"
b14 overflow signal
Base Timer interrupts
IT=0 in the G1BCR0 register
(Base timer interrupt generated
by the bit 15 overflow)
"1"
"0"
b15 overflow signal
Base Timer interrupt
Figure 13.1.3. Counter Increment/Decrement Mode
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M16C/28 Group
13. Timer S (Input Capture / Output Compare)
(1) When the base timer is reset while the base timer increments the counter
P80
(A-phase)
Input waveform
min 1 µs
P81
(B-phase)
min 1 µs
f
BT1
When selects no
division (n+1) divisor
(
)
(Note 1)
INT1 (Z-phase)
Value of counter
Base timer starts counting
m
m+1
0
1
2
Set to "0" in this timing
Set to "1" in this timing
(2) When the base timer is reset while the base timer decrements the counter
P80
(A-phase)
Input waveform
min 1 µs
P81
(B-phase)
min 1 µs
f
BT1
When no selects no
division (n+1) divisor
(
)
(Note 1)
INT1 (Z-phase)
Base timer starts counting
Value of counter
m
m-1
0
FFFF16 FFFE16
Set to "0" in this timing
Set to "FFFF16" in this timing
Note 1: More or equal to 1.5 fBT1 clock cycle are required.
Figure 13.1.4. Base Timer Operation in Two-phase Pulse Signal Processing Mode
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13. Timer S (Input Capture / Output Compare)
13.1.1 Base Timer Reset Register
The Base Timer Reset Register(G1BTRR) provides the capability to reset the Base Timer(BT) when
the base timer count value matches the value stored in the G1BTRR. The G1BTRR is enabled by the
RST4 reset cause select bit,G1BCR0(2). This function is identical in operation to the G1PO0 base
timer reset that is enabled by RST1.The Base Timer Reset feature is included to allow all eight chan-
nels to be used for waveform generation while providing a base timer reset on match function.
It is possible to simultaneously enable both RST1 and RST4, G1PO0 and G1BTRR base timer resets,
although operation of both base timer reset on match functions may cause unexpected behavior. It is
recommended that only one of RST1 or RST4 be enabled.
RST4
Base Timer
000016 000116
m-2
m-1
m
m+1
Base Timer Reset Register
Base Timer Interrupt
m
Figure 13.1.1.1. Base Timer Reset operation by Base Timer Reset Register
RST1
Base Timer
G1PO0
000016 000116
m-2
m-1
m
m+1
m
G1IR0
Figure 13.1.1.2. Base Timer Reset operation by G1PO0 register
RST2
Base Timer
000016 000116
m-2
m-1
m
m+1
P83/INT1
Note1:_I_N__T__1__ Base Timer reset does not generate a Base Timer interrupt,_I_N__T__1__ may generate an interrupt if enabled.
_______
Figure 13.1.1.3. Base Timer Reset operation by INT1
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M16C/28 Group
13. Timer S (Input Capture / Output Compare)
13.2 Interrupt Operation
The IC/OC interrupt contains several request causes. Figure 13.2.1 shows the IC/OC interrupt block dia-
gram and Table 13.2.1 shows the IC/OC interrupt assignation.
When either the base timer reset request or base timer overflow request is generated, the IR bit (bit 3 in the
BTIC register) corresponding to the IC/OC base timer interrupt is set to "1" (with an interrupt request). Also
when an interrupt request of each eight channels (channel i) is generated, the bit i in the G1IR register is set
to "1" (with an interrupt request). At this time, if the bit i in the G1IE0 register is "1" (IC/OC interrupt 0 request
enabled), the IR bit (bit 3 in the ICOC0IC register) corresponding to the IC/OC interrupt 0 is set to "1" (with
an interrupt request). And if the bit i in the G1IE1 register is "1" (IC/OC interrupt 1 request enabled), the IR
bit (bit 3 in the ICOC1IC register) corresponding to the IC/OC interrupt 1 is set to "1"(with an interrupt
request).
Additionally, because each bit in the G1IR register is not automatically set to "0" even if the interrupt is
acknowledged, set to "0" using a program. If these bits are left "1", all IC/OC channel interrupt causes,
which are generated after setting the IR bit to "1", will be disabled.
Interrupt Select Logic
DMA Requests (channel 0 to 7)
Channel 0 to 7 Interrupt requests
All register are read / write
G1IE0
ENABLE
G1IE1
ENABLE
G1IR
REQUEST
IC/OC interrupt 1 request
IC/OC interrupt 0 request
Base timer reset request
Base timer overflow request
IC/OC base timer interrupt request
Base Timer Interrupt / DMA Request
Figure 13.2.1. IC/OC Interrupt and DMA request generation
Table 13.2.1. Interrupt Assignment
Interrupt
Interrupt control register
BTIC(004716)
IC/OC base timer interrupt
IC/OC interrupt 0
IC/OC interrupt 1
ICOC0IC(004516)
ICOC0IC(004616)
13.3 DMA Support
Each of the interrupt sources - the eight IC/OC channel interrupts and the one Base Timer interrupt - are
capable of generating a DMA request.
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M16C/28 Group
13. Timer S (Input Capture / Output Compare)
13.4 Time Measurement Function
Synchronizing with an external trigger input, the value of the base timer is stored into the G1TMj register
(j=0 to 7). Table 13.4.1 shows specifications of the time measurement function. Table 13.4.2 shows regis-
ter settings associated with the time measurement function. Figures 13.4.1 and 13.4.2 display operational
timing of the time measurement function. Figure 13.4.3 shows operational timing of the prescaler function
and the gate function.
Table 13.4.1. Time Measurement Function Specifications
Item
Specification
Measurement channel
Selecting trigger input polarity
Measurement start condition
Channels 0 to 7
Rising edge, falling edge, both edges of the INPC1j pin(Note 1)
The IFEj bit in the G1FE register should be set to "1" (channels j function
enabled) when the FSCj bit (j=0 to 7) in the G1FS register is set to "1" (time
measurement function selected).
Measurement stop condition
Time measurement timing
The IFEj bit should be set to "0" (channel j function disabled)
•No prescaler
:every input is a trigger
•Prescaler (for channel 6 and channel 7)
:
every [G1TPRk (k=6,7) +1]th input is a trigger
Interrupt request generation timing The G1IRi bit (i=0 to 7) in the interrupt request register (See Figure 13.10) is
set to "1" at time measurement timing
INPC1j pin function(Note 1)
Selectable function
Trigger input pin
• Digital filter function
The digital filter samples a trigger input level every f1, f2 or fBT1 to pass
pulses matching a trigger input level three times
• Prescaler function (for channel 6 and channel 7)
Trigger inputs are counted to perform time measurement whenever value
of the G1TPRk(k=6,7) register + 1 trigger is input
• Gate function (for channel 6 and channel 7)
When a trigger input is inhibited with setting the GOC bit in the G1TMCRk
(k=6,7) register to "1" (gate cleared by matching the G1POp register (p=4
when k=6, p=5 when k=7)) after time measurement by first trigger input, a
trigger input is enabled to receive again by matching the base timer with the
G1POp register
• Digital Debounce function (for channel7)
See section 13.6.2 and 17.6 for details
Note1: The INPC10 to INPC17 pins
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13. Timer S (Input Capture / Output Compare)
Table 13.4.2. Register Settings Associated with the Time Measurement Function
Register
Bit
Function
G1TMCRj
CTS1 to CTS0
DF1 to DF0
Select time measurement trigger
Select the digital filter function
Select the gate function
GT, GOC, GSC
PR
-
Select the prescaler function
Setting value of prescaler
G1TPRk
G1FS
FSCj
IFEj
Set to "1" (time measurement function)
Set to "1" (channel j function enabled)
G1FE
j = 0 to 7 k = 6, 7
Bit configuration and function vary depending on which channel is used.
Registers associated with the time measurement function should be set after setting registers associated with the base time.
INPC1j pin input
FFFF16
n
Base timer
p
m
000016
p
n
m
G1TMj register
G1IRj bit
When setting to "0", write "0" by program
j=0 to 7
G1IRj bit : Bits in the G1IR register
The above applies to the following condition.
The CTS1 to CTS0 bits in the G1TMCRj registers are set to "012" (time measurement
is trigger on the rising edge). The PR bit is set to "0" (no prescaler used) and the GT bit
is set to"0" (no gate function used).
Bits RTS4, RTS2, and RTS1 of the G1BCR0 and G1BCR1 registers are set to "0" (no
base timer reset). The UD1 to UD0 bits are set to "002" (counter increment mode).
When the base timer matches the G1PO0 register and is set to "000016" (setting the RST1
bit to "1", and the RST4 and RST2 bits to "0"), the base timer is set to "000016" after it
reaches a setting value of the G1PO0 register+2.
Figure 13.4.1. Time Measurement Function (1)
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13. Timer S (Input Capture / Output Compare)
(a) When selecting the rising edge for timer measurement trigger
(The CTS1 to CTS0 bits in the G1TMCR register (j=0 to 7)=012)
fBT1
Base timer
n
n-2 n-1
n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14
(Note 2)
INPC1j pin input or
trigger signal after
passing the digital
filter
G1IRj bit (Note 1)
When setting to "0", write "0"
Delayed by 1 clock
by program
G1TMj register
Notes :
n
n +5
n+8
1. Bits in the G1IR register.
2. For an input pulse to the INPC1j pin, more or equal to 1.5 fBT1 cloc.k periods are required.
(b) When selecting both edges for timer measurement trigger
(The CTS1 to CTS0 bits=112)
f
BT1
n-2 n-1
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14
Base timer
INPC1j pin input or
trigger signal after
passing the digital
filter
G1IRj bit (Note 1)
When setting to "0",
write "0" by program
G1TMj register (Note 2)
Notes :
n
n+2
n+5
n+8
n+12
1. Bits in the G1IR register.
2. No interrupt is generated when the microcomputer receives input w. hen the G1IRj bit is in "H".
Value of the base timer is stored into the G1TMj register.
(c) Trigger signal when using digital filter
(The DF1 to DF0 bits in the G1TMCR register =102 or 112)
f
1
or f
2
or fBT1 (Note 1)
INPC1j pin
Maximum 3.5 clock cycles
of f or f or fBT1 (Note 1)
1
2
Signals, which do not match 3
Trigger signal after
passing the digital
times, are stripped off
filter
The trigger signal is delayed
by the digital filter
Note 1: fBT1 when the DF1 to DF0 bits are set to "102", and f1 or f2 when set to "112".
Figure 13.4.2. Time Measurement Function (2)
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13. Timer S (Input Capture / Output Compare)
(a) When using the prescaler function
(When the G1TPRj register (j=6, 7) =0216, PR bit in the G1TMCRj register (j=6, 7) =1)
f
BT1
Base timer
n-2 n-1
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 +12 n+13 n+14
INPC1j pin input or
trigger signal after
passing the digital
filter
Internal time
measurement trigger
2
2
1
0
Prescaler (Note 1)
G1IRj bit (Note 2)
When setting to "0", write "0" by program
n+1
G1TMj register
Notes :
n+13
1. This applies to the second period that the G1TPRj register decrements after setting the PR bit in the G1TMCRj
register to "1" (prescaler used).
2. Bits in the G1IR register.
(b) When using the gate function
(Gate function is cleared by matching the G1POk register and base timer,
the GT bit in the G1TMCRj register=1, the GOC bit=1)
f
BT1
FFFF16
000016
Value of the G1POk register
Base timer
IFEj bit in G1FE
register
INPC1j pin input or
trigger signal after
passing the digital
filter
This trigger input is disabled
due to gate function.
Internal time
measurement trigger
G1POk register
match signal
Gate control signal
Gate
When setting to "0", write "0" by program
Gate cleared
Gate
G1IRj bit (Note 1)
G1TMj register
Note 1: Bits in the G1IR register.
.
Figure 13.4.3. Prescaler Function and Gate Function
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13. Timer S (Input Capture / Output Compare)
13.5 Waveform Generation Function
Waveforms are generated when value of the base timer matches G1POj register (j=0 to 7).
The waveform generation function has the following three modes :
• Single-phase waveform output mode
• Phase-delayed waveform output mode
• Set/Reset waveform output (SR waveform output) mode
Table 13.5.1 lists registers associated with the waveform generation function.
Table 13.5.1. Registers Related to the Waveform Generation Function Settings
Register
Bit
Function
G1POCRj
MOD1 to MOD0
Select output waveform mode
Select default value
Select G1POj register value reload timing
Select inverse output
Select timing to output waveform inverted
Set to "0" (waveform generation function)
Set to "1" (enables function on channel j)
IVL
RLD
INV
-
FSCj
IFEj
G1POj
G1FS
G1FE
j = 0 to 7
Bit configuration and function vary depending on which channel is used.
Registers associated with the waveform generation function should be set after setting registers associated with the base time.
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13. Timer S (Input Capture / Output Compare)
13.5.1 Single-Phase Waveform Output Mode
Output level of the OUTC1j pin is inverted when value of the base timer matches that of the G1POj
register (j=0 to 7). The inverted output level is returned to a default output level when the base timer
reaches "000016". Table 13.5.1.1 lists specifications of single-phase waveform mode. Figure 13.5.1.1
lists an example of single-phase waveform mode operation.
Table 13.5.1.1. Single-phase Waveform Output Mode Specifications
Item
Specification
Output waveform
• Free-running operation
(the RST1, RST2, and RST4 bits of the G1BCR1 and G1BCR0 registers are set
to "0" (no reset))
65536
Cycle
:
fBT1
m
fBT1
Default output level :
65536-m
fBT1
Inverse level
:
• The base timer is reset when its value matches that of either register
(a) G1PO0 (enabled by setting bit RST1 to "1", and bits RST4 and RST2 to "0"), or
(b) G1BTRR (enabled by setting bit RST4 to "1", and bits RST2 and RST1 to "0")
n+2
Cycle
:
fBT1
m
fBT1
Default output level :
n+2-m
fBT1
Inverse level
:
m : setting value of the G1POj register (j=0 to 7), 000116 to FFFD16
n : setting value of the G1PO0 register or the G1BTRR register, 000116 to FFFD16
The IFEj bit in the G1FE register should be set to "1" (channel j function enabled)
Waveform output start condition
Waveform output stop condition
Interrupt request
The IFEj bit should be set to "0" (channel j function disabled)
The G1IRj bit in the interrupt request register is set to "1" when value of the
base timer matches one of the G1POj registers. (See Figure 13.10.)
Pulse output
OUTC1j pin(Note 1)
Selectable function
• Default value set function : Output level is set when waveform output starts
• Inverse output function : Waveform level is inverted to output waveform from
the OUTC1j pin
Note 1: The OUTC10 to OUTC17 pins .
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M16C/28 Group
13. Timer S (Input Capture / Output Compare)
(1) Free-running operation
(Bits RST4, RST2, and RST1 of the G1BCR0 and G1BCR1 registers are set to "0")
FFFF16
Base timer
m
000016
m
65536-m
f
BT1
fBT1
Inverse
65536
Inverse
OUTC1j pin
G1IRj bit
Return to initial output level
f
BT1
When setting to "0",
write "0" by program
j=0 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
The above applies to the following conditions.
The IVL bit in the G1POCRj register is set to "0" (output "L" as an initial value) and the INV bit
is set to "0" (no output inverted).
Bits RST4, RST2, and RST1 of the G1BCR0 and G1BCR1 registers are set to "0" (no base
timer reset), and the UD1 to UD0 bits are set to "002" (counter increment mode).
(2) The base timer is reset when its value matches that of either register
(a) G1PO0 (enabled by setting bit RST1 to "1", and bits RST4 and RST2 to "0"), or
(b) G1BTRR (enabled by setting bit RST4 to "1", and bits RST2 and RST1 to "0")
FFFF16
n+2
Base timer
m
000016
m
n+2-m
f
BT1
f
BT1
OUTC1j pin
G1IRj bit
Inverse
Inverse
n+2
Inverse
Return to initial
When setting
to "0", write "0"
by program
output level
f
BT1
j=1 to 7
m : Setting value of the G1POk register
n: Setting value of either G1PO0 register or G1BTRR register
G1IRj bit : Bits in the G1IR register
The above applies to the following conditions.
The IVL bit in the G1POCRj register is set to "0" (output "L" as an initial value) and the INV
bit be set to "0" (no output inverted).
The UD1 to UD0 bits are set to "002" (counter increment mode).
Figure 13.5.1.1. Single-phase Waveform Output Mode
Rev.0.60 2004.02.01 page 146 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
13.5.2 Phase-Delayed Waveform Output Mode
Output level of the OUTC1j pin is inverted whenever the value of the base timer matches that of the
G1POj register value ( j=0 to 7). Table 13.5.2.1 lists specifications of phase-delayed waveform mode.
Figure 13.5.2.1 lists an example of phase-delayed waveform mode operation.
Table 13.5.2.1. Phase-delayed Waveform Output Mode Specifications
Item
Specification
Output waveform
• Free-running operation
(the RST1, RST2, and RST4 bits of the G1BCR1 and G1BCR0 registers are set
to "0" (no reset))
65536 x 2
Cycle
:
fBT1
65536
fBT1
"H" and "L" width
:
• Setting bit RST1 to "1", and bits RST4 and RST2 to "0" enables the base
timer to be reset when its value matches the G1PO0 register. Likewise,
setting bit RST4 to "1",and bits RST2 and RST1 to "0" enables the base timer
to be reset when its value matches the G1BTRR register.
2(n+2)
Cycle
:
fBT1
n+2
fBT1
"H" and "L" width
:
n : setting value of either G1PO0 register or G1BTRR register, 000116
to FFFD16
Waveform output start condition(Note 1) The IFEj bit in the G1FE register should be set to "1" (channel j function enabled)
Waveform output stop condition
Interrupt request
The IFEj bit should be set to "0" (channel j function disabled)
The G1IRj bit in the interrupt request register is set to "1" when value of the
base timer matches one of the G1POj registers. (See Figure 13.10.)
Pulse output
OUTC1j pin(Note 2)
Selectable function
• Default value set function : Output level is set when waveform output starts
• Inverse output function : Waveform level is inverted to output waveform from
the OUTC1j pin
Note 1 : The FSCj bit in the G1FS register should be set to "0" (waveform generation function selected) in the channels
shared by the time measurement function and waveform generation function.
Note 2 : The OUTC10 to OUTC17 pins.
Rev.0.60 2004.02.01 page 147 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
(1) Free-running operation
(Bits RST4, RST2, and RST1 of the G1BCR0 and G1BCR1 registers are set to "0")
FFFF16
Base timer
m
000016
65536
65536
f
BT1
f
BT1
Inverse
65536X2
Inverse
OUTC1j pin
G1IRj bit
f
BT1
When setting to "0",
write "0" by program
j=0 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
The above applies to the following conditions.
The IVL bit in the G1POCRj register is set to "0" (output "L" as an initial value). The INV bit
is set to "0" (no output inverted).
Bits RST4, RST2, and RST1 of the G1BCR0 and G1BCR1 registers are set to "0" (no base timer reset). The UD1 to UD0
bits are set to "002" (counter increment mode).
(2) Base timer is reset when its value matches that of either register (a) G1PO0
(enabled by setting bit RST1 to "1", and bits RST4 and RST2 to "0"), or (b) G1BTRR
(enabled by setting bit RST4 to "1", and bits RST2 and RST1 to "0")
FFFF16
n+2
Base timer
m
000016
n+2
n+2
m
f
BT1
fBT1
f
BT1
Inverse
OUTC1j pin
G1IRj bit
Inverse
Inverse
2(n+2)
When setting
to "0", write "0"
by program
f
BT1
j=1 to 7
m : Setting value of the G1POj register
G1IRj bit : Bits in the G1IR register
n: Setting value of either register G1PO0 or G1BTRR
The above applies to the following conditions.
The IVL bit in the G1POCRj register is set to "0" (output "L" as an initial value).
The INV bit is set to "0" (no output inverted).
The UD1 to UD0 bits are set to "002" (counter increment mode).
Figure 13.5.2.1. Phase-delayed Waveform Output Mode
Rev.0.60 2004.02.01 page 148 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode
Output level of the OUTC1j pin is inverted when the base timer value matches that of the G1POj register
value (j=0, 2, 4, 6). It is returned to default output level when the base timer value matches that of the
G1POk register (k=j+1). Table 13.5.3.1 lists specifications of SR waveform mode. Figure 13.5.3.1 lists an
example of the SR waveform mode operation.
Table 13.5.3.1. SR Waveform Output Mode Specifications
Item
Specification
Output waveform
• Free-running operation
(the RST1, RTS2, and RST4 bits of the G1BCR1 and G1BCR0 registers are set
to "0" (no reset))
65536
Cycle
:
fBT1
m-n
fBT1
Inverse level(Note 1)
:
• Setting bit RST1 to "1", and bits RST4 and RST2 to "0" enables the base
timer to be reset when its value matches the G1PO0 register(Note 2).
Likewise, setting bit RST4 to "1", and bits RST2 and RST1 to "0" enables the
base timer to be reset when its value matches the G1BTRR register.
p+2
Cycle
:
fBT1
m-n
fBT1
Inverse level(Note 1)
:
m : setting value of the G1POj register (j=0, 2, 4, 6 )
n : setting value of the G1POk register (k=j+1)
p : setting value of either G1PO0 register or G1BTRR register
all m, n, p: 000116 to FFFD16
Waveform output start condition(Note 3) The IFEj bit in the G1FE register should be set to "1" (channel j function enabled)
Waveform output stop condition
Interrupt request
The IFEj bit should be set to "0" (channel j function disabled)
The G1IRj bit in the interrupt request register is set to "1" when value of the
base timer matches one of the G1POj registers.
The G1IRk bit in the interrupt request register is set to "1 " when value of the
base timer matches one of the G1POk registers (See Figure 13.10.)
Pulse output
OUTC1j pin(Note 3)
Selectable function
• Default value set function : Output level is set when waveform output starts
• Inverse output function : Waveform level is inverted to output waveform from the
OUTC1j pin
Note 1 : The waveform generation register of odd channel should have greater value than the one of even channel has.
Note 2 : When the G1PO0 register resets the base timer, the SR waveform generation function with channels 0 and 1
cannot be used.
Note 3 : The OUTC10, OUTC12, OUTC14, OUTC16 pins.
Rev.0.60 2004.02.01 page 149 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
(1) Free-running operation
(The RST1 bit is set to "1", and both RST4 and RST2 bits are set to "0")
FFFF16
n
Base timer
m
000016
n-m
65536-n+m
f
BT1
f
BT1
Return to initial
output level
OUTC1j pin
Inverse
Inverse
65536
f
BT1
When setting to "0",
write "0" by program
G1IRj bit
G1IRk bit
inverse
j=0, 2, 4, 6 k=j+1
m : Setting value of the G1POk register
G1IRj, G1IRk bits: Bits in the G1IR register
n: Setting value of the G1POj register
The above applies to the following conditions.
The IVL bit in the G1POCRj register is set to "0" (output "L" as an initial value). The INV bit is set to "0" (no output
inverted).
Bits RST4, RST2, and RST1 of the G1BCR0 and G1BCR1 registers are set to "0" (no base timer reset). The UD1 to
UD0 bits are set to "002" (counter increment mode).
(2) Base timer is reset when its value matches that of either register (a) G1PO0
(enabled by setting bit RST1 to "1", and bits RST4 and RST2 to "0"), or (b) G1BTRR
(enabled by setting bit RST4 to "1", and bits RST2 and RST1 to "0")
FFFF16
p+2
n
Base timer
m
000016
n-m
p+2-n+m
f
BT1
fBT1
Return to initial output level
OUTC1j pin
p+2
f
BT1
When setting to "0",
write "0" by program
G1IRj bit
G1IRk bit
When setting to "0",
write "0" by program
j=2, 4, 6 k=j+1
m : Setting value of the G1POk register
n: Setting value of the G1POj register
p: Setting value of either register G1PO0 or G1BTRR
G1IRj, G1IRk bits: Bits in the G1IR register
The above applies to the following conditions.
The IVL bit in the G1POCRj register is set to "0" (output "L" as an initial value). The INV bit is set to "0" (no output
inverted).
The UD1 to UD0 bits are set to "002" (counter increment mode).
Figure 13.5.3.1. Set/Reset Waveform Output Mode
Rev.0.60 2004.02.01 page 150 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
13.6 I/O Port Function Select
The M16C/28 will automatically configure the port package pins to be IC/OC inputs or outputs based on
the values in the Function Enable (G1FE) and Function Select (G1FS) registers. When using PWM S-R
mode, two channels are enabled and selected as output, but only one output, the output corresponding to
the even numbered channel, is generated.
The port package pin corresponding to the odd numbered channel is available for use as General Pur-
pose Input / Output.
Table 13.6.1. Pin setting for Time Measurement and Waveform Generation Functions
Pin
IFE FSC MOD1 MOD0 Port Direction
Port Data
P27/INPC17/
OUTC17
0
1
1
1
1
X
1
0
0
0
X
X
0
0
1
X
X
0
1
0
Determined by PD27
Determined by PD27, Input to INPC17 is always active P27 or INPC17
Single-phase Waveform Output
Determined by PD27, S-R PWM mode
Phase-delayed Waveform Output
P27
OUTC17
P27
OUTC17
P26/INPC16/
OUTC16
0
X
X
X
Determined by PD26
P26
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
X
1
0
0
0
X
1
0
0
0
X
1
0
0
0
X
1
0
0
0
X
1
0
0
0
X
1
0
0
0
X
0
0
1
X
X
0
0
1
X
X
0
0
1
X
X
0
0
1
X
X
0
0
1
X
X
0
0
1
X
X
0
0
1
X
0
1
0
X
X
0
1
0
X
X
0
1
0
X
X
0
1
0
X
X
0
1
0
X
X
0
1
0
X
X
0
1
0
Determined by PD26, Input to INPC16 is always active P26 or INPC16
Single-phase Waveform Output
SR Waveform Output
Phase-delayed Waveform Output
Determined by PD25
Determined by PD25, Input to INPC15 is always active P25 or INPC15
Single-phase Waveform Output
Determined by PD25, S-R PWM mode
Phase-delayed Waveform Output
Determined by PD24
Determined by PD24, Input to INPC14 is always active P24 or INPC14
Single-phase Waveform Output
SR Waveform Output
Phase-delayed Waveform Output
Determined by PD23
Determined by PD23, Input to INPC13 is always active P23 or INPC13
Single-phase Waveform Output
Determined by PD23, S-R PWM mode
Phase-delayed Waveform Output
Determined by PD22
Determined by PD22, Input to INPC12 is always active P22 or INPC12
Single-phase Waveform Output
SR Waveform Output
Phase-delayed Waveform Output
Determined by PD21
Determined by PD21, Input to INPC11 is always active P21 or INPC11
OUTC16
OUTC16
OUTC16
P25
P25/INPC15/
OUTC15
OUTC15
P25
OUTC15
P24
P24/INPC14/
OUTC14
OUTC14
OUTC14
OUTC14
P23
P23/INPC13/
OUTC13
OUTC13
P23
OUTC13
P22
P22/INPC12/
OUTC12
OUTC12
OUTC12
OUTC12
P21
P21/INPC11/
OUTC11
Single-phase Waveform Output
Determined by PD21, S-R PWM mode
Phase-delayed Waveform Output
Determined by PD20
Determined by PD20, Input to INPC10 is always active P20 or INPC10
Single-phase Waveform Output
SR Waveform Output
OUTC11
P21
OUTC11
P20
P20/INPC10/
OUTC10
OUTC10
OUTC10
OUTC10
Phase-delayed Waveform Output
IFE: IFEj (j=0 to 7) bits in the G1FE register.
FSC: FSCj (j=0 to 7) bits in the G1FS register.
MOD2 to MOD1: Bits in the G1POCRj (j=0 to 7) register.
Rev.0.60 2004.02.01 page 151 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
13. Timer S (Input Capture / Output Compare)
13.6.1 INPC17 Alternate Input Pin Selection
The input capture pin for IC/OC channel 7 can be assigned to one of two package pins.
Control bit, G1BCR0(6) CH7INSEL, Channel 7 input select, selects IC/OC INPC17 to come from P27/
________
OUTC17/INPC17 or P17/INT5/INPC17/IDU.
________
13.6.2 Digital Debounce Function for Pin P17/INT5/INPC17
________
________
The INT5/INPC17 input from the P17/INT5/INPC17/IDU pin has an effective digital debounce function for
a noise rejection. Refer to "17.6 Digital Debounce function" for this detail.
Rev.0.60 2004.02.01 page 152 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
14. Serial I/O
Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4.
SI/O4 is not in 64 pin version.
14.1. UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each
other.
Figure 14.1.1 shows the block diagram of UARTi. Figures 14.1.2 and 14.1.3 shows the block diagram of
the UARTi transmit/receive.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
2
•
•
•
•
Special mode 1 (I C mode) : UART2
Special mode 2 : UART2
Special mode 3 (Bus collision detection function, IE mode) : UART2
Special mode 4 (SIM mode) : UART2
Figures 14.1.4 to 14.1.9 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
Rev.0.60 2004.02.01 page 153 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
PCLK1=0
PCLK1=1
f
2SIO
1SIO
1/2
1/8
f
1SIO or f2SIO
f
Main clock or ring oscillator clock
f
8SIO
32SIO
f
1/4
(UART0)
RxD0
TxD0
UART reception
Clock source selection
CLK1 to CLK0
Receive
clock
1/16
Reception
control circuit
Clock synchronous
type
00
01
10
External
2
Transmit/
receive
unit
U0BRG
register
f
1SIO or
f
f
2SIO
8SIO
32SIO
Internal
2
CKDIR=0
CKDIR=1
UART transmission
2
Transmit
clock
f
1/16
1/2
1 / (n0+1)
Transmission control
circuit
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
Clock synchronous type
CKPOL
CKDIR=1
(when internal clock is selected)
CLK
polarity
reversing
circuit
CLK0
CTS/RTS disabled
CTS/RTS selected
CRS=1
RTS
0
CTS0 / RTS
0
CRS=0
V
CC
CTS/RTS disabled
RCSP=0
RCSP=1
CRD=1
CTS
0
CRD=0
CTS0 from UART1
(UART1)
RxD1
TxD1
UART reception
Clock source selection
CLK1 to CLK0
Receive
clock
1/16
Reception
control circuit
Clock synchronous
type
Transmit/
receive
unit
00
01
10
2
U1BRG
register
f
1SIO or
f
f
2SIO
8SIO
32SIO
Internal
2
CKDIR=0
2
UART transmission
Transmit
clock
f
1/16
1/2
1 / (n1+1)
Transmission
control circuit
Clock synchronous
type
External
CKDIR=1
Clock synchronous type
(when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CKPOL
CKDIR=1
CLK
polarity
reversing
circuit
CLKMD0=0
CLKMD0=1
CLK
1
Clock output
pin select
CLKMD1=1
CTS/RTS selected
CRS=1
CTS/RTS disabled
CTS
CTS
1
0
/ RTS
1
/
RTS1
/ CLKS
1
CLKMD1=0
CRS=0
V
CC
CTS/RTS disabled
CTS1
CTS
RCSP=0
RCSP=1
CRD=1
CRD=0
0
from UART0
(UART2)
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD
2
TxD2
UART reception
Clock source selection
CLK1 to CLK0
00
Receive
clock
1/16
Reception
control circuit
Clock synchronous
type
2
Transmit/
receive
unit
U2BRG
register
f
1SIO or
f
f
2SIO
8SIO
32SIO
01
2
Internal
CKDIR=0
CKDIR=1
UART transmission
10
2
Transmit
clock
f
1/16
1/2
1 / (n2+1)
Transmission
control circuit
Clock synchronous
type
External
Clock synchronous type
(when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CKDIR=1
CKPOL
CLK
polarity
reversing
circuit
CLK2
CTS/RTS disabled
CTS/RTS
selected
CRS=1
CRS=0
RTS
2
CTS2 / RTS
2
V
CC
CTS/RTS disabled
CRD=1
CTS
2
CRD=0
i = 0 to 2
: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: UiMR register’s bits
n
i
CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register’s bits
CLKMD0, CLKMD1, RCSP: UCON register’s bits
Figure 14.1.1. Block diagram of UARTi (i = 0 to 2)
Rev.0.60 2004.02.01 page 154 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
Clock
synchronous type
PAR
disabled
UART (7 bits)
UART (8 bits)
1SP
Clock
UARTi receive register
synchronous
type
UART (7 bits)
STPS=0
PRYE=0
PRYE=1
SP
SP
PAR
RxDi
STPS=1
UART
2SP
UART (9 bits)
enabled
Clock
synchronous type
UART (8 bits)
UART (9 bits)
UARTi receive
buffer register
0
0
0
0
0
0
0
D8
D
7
D
6
D5
D
4
D3
D
2
D1
D0
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
UARTi transmit
buffer register
D7
D6
D5
D4
D
3
D
2
D1
D0
D8
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UART (9 bits)
PAR
enabled
UART
STPS=1
STPS=0
2SP
PRYE=1
PAR
SP
SP
TxDi
PRYE=0
Clock
synchronous
type
UART (7 bits)
UARTi transmit register
UART (7 bits)
UART (8 bits)
1SP
PAR
disabled
SP: Stop bit
PAR: Parity bit
0
Clock synchronous
type
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : UiMR register’s bit
Figure 14.1.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
Rev.0.60 2004.02.01 page 155 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
No reverse
IOPOL=0
RxD data
reverse circuit
RxD2
IOPOL=1
Reverse
Clock
synchronous type
UART
PAR
disabled
1SP
(7 bits)
UART
(8 bits)
Clock
synchronous
type
UARTi receive register
UART(7 bits)
STPS=0
STPS=1
PRYE=0
PRYE=1
PAR
SP
SP
Clock
synchronous type
PAR
enabled
2SP
UART
UART
(9 bits)
UART
(8 bits)
UART
(9 bits)
UART2 receive
buffer register
0
0
0
0
0
0
0
D
8
D
7
D6
D
5
D
4
D3
D
2
D
1
D0
Address 037E16
Address 037F16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
UART2 transmit
buffer register
D
7
D6
D5
D
4
D
3
D
2
D
1
D0
D
8
Address 037A16
Address 037B16
UART
(8 bits)
UART
(9 bits)
UART
(9 bits)
Clock
synchronous type
PAR
enabled
STPS=1
STPS=0
UART
PRYE=1
PRYE=0
2SP
SP
SP
PAR
Clock
synchronous
type
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UARTi transmit register
PAR
disabled
1SP
0
Clock
synchronous type
Error signal output
disable
No reverse
U2ERE
=0
IOPOL
=0
TxD data
reverse circuit
Error signal
output circuit
TxD2
IOPOL
=1
U2ERE
=1
Reverse
Error signal output
enable
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : U2MR register’s bit
U2ERE : U2C1 register’s bit
Figure 14.1.3. Block diagram of UART2 transmit/receive unit
Rev.0.60 2004.02.01 page 156 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
UARTi transmit buffer register (i=0 to 2)(Note)
Symbol
U0TB
U1TB
U2TB
Address
After reset
(b15)
b7
(b8)
03A316-03A216
03AB16-03AA16
037B16-037A16
Indeterminate
Indeterminate
Indeterminate
b0 b7
b0
Function
RW
WO
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register (i=0 to 2)
(b8)
b0 b7
(b15)
b7
Symbol
U0RB
U1RB
U2RB
Address
After reset
b0
03A716-03A616
03AF16-03AE16
037F16-037E16
Indeterminate
Indeterminate
Indeterminate
Bit
Function
Bit name
RW
symbol
(b7-b0)
(b8)
Receive data (D
7
to D
0)
RO
RO
Receive data (D
8
)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
(b10-b9)
ABT
0 : Not detected
1 : Detected
Arbitration lost detecting
flag (Note 2)
RW
RO
0 : No overrun error
1 : Overrun error found
Overrun error flag (Note 1)
OER
FER
PER
SUM
Framing error flag (Note 1) 0 : No framing error
1 : Framing error found
RO
RO
Parity error flag (Note 1)
0 : No parity error
1 : Parity error found
Error sum flag (Note 1)
0 : No error
1 : Error found
RO
Note 1: When the UiMR register’s SMD2 to SMD0 bits = “0002” (serial I/O disabled) or the UiC1 register’s RE bit = “0” (reception disabled), all of the SUM,
PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER bits = “0” (no error).
Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.
Note 2: The ABT bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.)
UARTi baud rate generation register (i=0 to 2)(Notes 1, 2)
Symbol
U0BRG
U1BRG
U2BRG
Address
03A116
03A916
037916
After reset
b7
b0
Indeterminate
Indeterminate
Indeterminate
Function
Setting range
0016 to FF16
RW
WO
Assuming that set value = n, UiBRG divides the count source
by n + 1
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
Figure 14.1.4. Serial I/O-related registers (1)
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
UARTi transmit/receive mode register (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0MR, U1MR
Address
03A016, 03A816
After reset
0016
Bit
symbol
Function
Bit name
RW
RW
b2 b1 b0
SMD0
Serial I/O mode select bit
(Note 2)
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
SMD1
SMD2
RW
RW
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
RW
RW
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Odd/even parity select bit
Effective when PRYE = 1
0 : Odd parity
RW
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
(b7)
Parity enable bit
Reserve bit
RW
RW
Write to "0"
Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
After reset
0016
Bit
symbol
Function
Bit name
RW
RW
RW
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
(Note 2)
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I2C mode
(Note 3)
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
RW
RW
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
CKDIR
STPS
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Odd/even parity select bit
RW
RW
PRY
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
Parity enable bit
PRYE
RW
RW
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
IOPOL
Note 1: Set the corresponding port direction bit for each CLK2 pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxD2 pin to “0” (input mode).
Note 3: Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).
Figure 14.1.5. Serial I/O-related registers (2)
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
UARTi transmit/receive control register 0 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
U0C0 to U2C0 03A416, 03AC16, 037C16 00001000
2
Bit
symbol
RW
Bit name
Function
b1 b0
CLK0
BRG count source
select bit
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Must not be set
RW
RW
CLK1
CRS
Effective when CRD = 0
0 : CTS function is selected (Note 1)
1 : RTS function is selected
CTS/RTS function
select bit
(Note 3)
RW
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
TXEPT Transmit register empty
flag
RO
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60, P64 and P73 can be used as I/O ports)
CRD
CTS/RTS disable bit
Data output select bit
RW
RW
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N-channel open-drain output
NCH
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
CKPOL CLK polarity select bit
RW
RW
UFORM Transfer format select bit
(Note 2)
0 : LSB first
1 : MSB first
Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
Note 2: Effective for clock synchronous serial I/O mode, UART mode transfer data 8 bits long and special mode 2.
Note 3: CTS
1
/RTS
1
can be used when the UCON register’s CLKMD1 bit = “0” (only CLK
not separated).
1 output) and the UCON register’s RCSP bit =
“0” (CTS
0/RTS
0
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
After reset
X0000000
2
Bit
Function
0 : Transmit buffer empty (Tl = 1)
Bit
RW
RW
symbol
name
U0IRS UART0 transmit
interrupt cause select bit 1 : Transmission completed (TXEPT = 1)
U1IRS UART1 transmit
0 : Transmit buffer empty (Tl = 1)
RW
interrupt cause select bit 1 : Transmission completed (TXEPT = 1)
U0RRM UART0 continuous
0 : Continuous receive mode disabled
RW
RW
RW
receive mode enable bit 1 : Continuous receive mode enable
U1RRM UART1 continuous
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
receive mode enable bit
CLKMD0 UART1 CLK/CLKS
select bit 0
Effective when CLKMD1 = “1”
0 : Clock output from CLK1
1 : Clock output from CLKS1
CLKMD1 UART1 CLK/CLKS
select bit 1 (Note)
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
RW
RW
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS0 supplied from the P64 pin)
RCSP
(b7)
Separate UART0
CTS/RTS bit
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = “0” (internal clock)
Figure 14.1.6. Serial I/O-related registers (3)
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Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
UARTi transmit/receive control register 1 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
U0C1, U1C1
03A516,03AD16 00000010
2
Bit
symbol
Function
Bit name
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
RO
RW
RO
TI
Transmit buffer
empty flag
0 : Data present in UiTB register
1 : No data present in UiTB register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in UiRB register
1 : Data present in UiRB register
Nothing is assigned.
When write, set “0”. When read, these contents are “0”.
(b7-b4)
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C1
Address
037D16
After reset
00000010
2
Bit
Function
Bit name
symbol
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
RO
Transmit buffer
empty flag
0 : Data present in U2TB register
1 : No data present in U2TB register
TI
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RO
0 : No data present in U2RB register
1 : Data present in U2RB register
RI
Receive complete flag
U2IRS UART2 transmit interrupt 0 : Transmit buffer empty (TI = 1)
RW
RW
cause select bit
1 : Transmit is completed (TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
RW
RW
U2ERE Error signal output
enable bit
0 : Output disabled
1 : Output enabled
Figure 14.1.7. Serial I/O-related registers (4)
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U2SMR
Address
037716
After reset
X0000000
2
Bit
symbol
Function
Bit
name
RW
IICM
ABC
I2C mode select bit
0 : Other than I2C mode
1 : I2C mode
RW
RW
Arbitration lost detecting 0 : Update per bit
flag control bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
RW
(Note1)
BBS
Bus busy flag
Set to “0”
Reserved bit
RW
RW
(b3)
Bus collision detect
0 : Rising edge of transfer clock
sampling clock select bit 1 : Underflow signal of timer A0
ABSCS
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
ACSE
RW
RW
0 : Not synchronized to R
XDi
Transmit start condition
select bit
SSS
(b7)
1 : Synchronized to R Di (Note 2)
X
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).
Note 2: When a transfer begins, the SSS bit is set to “0” (Not synchronized to RXDi).
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
037616
After reset
X0000000
2
Bit
symbol
Bit name
Function
RW
2
I C mode select bit 2
Refer to “Table 141.3.4. I2C Mode Functions”
IICM2
CSC
RW
RW
RW
RW
Clock-synchronous bit
SCL wait output bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
SWC
ALS
SDA output stop bit
UART initialization bit
SCL wait output bit 2
SDA output disable bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
STAC
SWC2
RW
RW
RW
0: Transfer clock
1: “L” output
0: Enabled
1: Disabled (high impedance)
SDHI
(b7)
Nothing is assigned. When write, set “0”. When read, its content is
indeterminate.
Figure 14.1.8. Serial I/O-related registers (5)
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Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
UART2 special mode register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
037516
After reset
000X0X0X
2
Bit
symbol
Bit name
Function
RW
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b0)
CKPH
Clock phase set bit
0 : Without clock delay
1 : With clock delay
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b2)
NODC Clock output select bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
RW
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b4)
DL0
b7 b6 b5
SDA digital delay
0 0 0 : Without delay
setup bit
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
(Note 1, Note 2)
DL1
DL2
RW
RW
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode. In other than I2C
mode, set these bits to “000 ” (no delay).
2
Note 2 : The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
UART2 special mode register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR4
Address
037416
After reset
0016
Bit
symbol
Bit name
Start condition
Function
RW
RW
0 : Clear
1 : Start
STAREQ
generate bit (Note)
Restart condition
generate bit (Note)
0 : Clear
1 : Start
RSTAREQ
RW
RW
RW
RW
RW
RW
RW
Stop condition
generate bit (Note)
0 : Clear
1 : Start
STPREQ
STSPSEL
SCL,SDA output
select bit
0 : Start and stop conditions not output
1 : Start and stop conditions output
ACK data bit
0 : ACK
1 : NACK
ACKD
ACK data output
enable bit
0 : Serial I/O data output
1 : ACK data output
ACKC
SCLHI
SWC9
0 : Disabled
1 : Enabled
SCL output stop
enable bit
SCL wait bit 3
0 : SCL “L” hold disabled
1 : SCL “L” hold enabled
Note: Set to “0” when each condition is generated.
Figure 14.1.9. Serial I/O-related registers (6)
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
14.1.1. Clock Synchronous serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1.1.1
lists the specifications of the clock synchronous serial I/O mode. Table 14.1.1.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
Table 14.1.1.1. Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
• CKDIR bit = “1” (external clock) : Input from CLKi pin
0016 to FF16
_______
_______
Transmission, reception control
Transmission start condition
• Selectable from CTS function, _R__T__S__ function or C___T__S__/RTS function disable
• Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______
_______
_ If CTS function is selected, input on the CTSi pin = “L”
• Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register= 1 (reception enabled)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register= 0 (data present in the UiTB register)
• For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 3) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
Reception start condition
Interrupt request
generation timing
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
Select function
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic (UART2)
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
• Separate _C__T__S__/R___T__S__ pins (UART0)
_________
CTS0 and _R__T__S___0_ are input/output from separate pins
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 3: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Rev.0.60 2004.02.01 page 163 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
Table 14.1.1. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
Bit
Function
Set transmission data
UiTB(Note3) 0 to 7
UiRB(Note3) 0 to 7
OER
Reception data can be read
Overrun error flag
UiBRG
0 to 7
Set a transfer rate
UiMR(Note3) SMD2 to SMD0
CKDIR
Set to “0012”
Select the internal clock or external clock
IOPOL(i=2)(Note 4) Set to “0”
UiC0
CLK1 to CLK0
CRS
Select the count source for the UiBRG register
_______ _______
Select CTS or RTS to use
TXEPT
Transmit register empty flag
_______
_______
CRD
Enable or disable the CTS or RTS function
Select TxDi pin output mode
NCH
CKPOL
UFORM
TE
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to “1” to enable transmission/reception
Transmit buffer empty flag
UiC1
TI
RE
Set this bit to “1” to enable reception
Reception complete flag
RI
U2IRS (Note 1)
U2RRM (Note 1)
U2LCH(Note 3)
U2ERE(Note 3)
0 to 7
Select the source of UART2 transmit interrupt
Set this bit to “1” to use UART2 continuous receive mode
Set this bit to “1” to use UART2 inverted data logic
Set to “0”
UiSMR
Set to “0”
UiSMR2
UiSMR3
0 to 7
Set to “0”
0 to 2
Set to “0”
NODC
Select clock output mode
4 to 7
Set to “0”
UiSMR4
UCON
0 to 7
Set to “0”
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
Select the source of UART0/UART1 transmit interrupt
Set this bit to “1” to use continuous receive mode
Select the transfer clock output pin when CLKMD1 = 1
Set this bit to “1” to output UART1 transfer clock from two pins
Set this bit to “1” to accept as input the UART0 C___T__S___0_ signal from the P64 pin
Set to “0”
7
Note 1: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
Note 3: Set the U0C1 and U1C1 register bit 6 and bit 7 to "0".
Note 4: Set the U0MR and U1MR register bit 7 to "0".
i=0 to 2
Rev.0.60 2004.02.01 page 164 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
Table 14.1.1.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
14.3 shows pin functions for the case where the multiple transfer clock output pin select function is dese-
lected. Table 14.1.1.4 lists the P64 pin functions during clock synchronous serial I/O mode.
Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi
pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)
Table 14.1.1.3. Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name
Function
Method of selection
TxDi (i = 0 to 2)
Serial data output
(Outputs dummy data when performing reception only)
(P6
3, P6
7, P70)
Serial data input
RxDi
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input/output port when performing transmission only)
(P6 , P6
2
6
, P7
1
)
)
CLKi
(P6 , P6
Transfer clock output
Transfer clock input
UiMR register’s CKDIR bit=0
1
5, P7
2
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
CTSi/RTSi
(P6 , P6 , P73)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
CTS input
0
4
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
RTS output
I/O port
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
UiC0 register’s CRD bit=1
Table 14.1.1.4. P64 Pin Functions
Pin function
Bit set value
U1C0 register
UCON register
PD6 register
PD6_4
Input: 0, Output: 1
CLKMD0
CLKMD1
0
RCSP
CRS
CRD
P64
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
CTS
1
1
RTS
0
CTS
0(Note1)
CLKS
1
1(Note 2)
1
Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS
U0C0 register’s CRS bit to “1” (RTS selected).
0/RTS0 enabled) and the
0
Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the U1C0 register’s CLKPOL bit = 0
• Low if the U1C0 register’s CLKPOL bit = 1
Rev.0.60 2004.02.01 page 165 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
(1) Example of transmit timing
Tc
Transfer clock
“1”
“0”
UiC1 register
TE bit
Write data to the UiTB register
“1”
“0”
“H”
UiC1 register
TI bit
Transferred from UiTB register to UARTi transmit register
CTSi
CLKi
T
CLK
“L”
Stopped pulsing because CTSi = “H”
Stopped pulsing because the TE bit = “0”
TxDi
D0
D
1
D2
D3
D4
D5
D6
D7
D0
D
1
D2
D3
D4
D5
D
6
D7
D
0
D1
D2
D
3
D
4
D
5
D6
D7
“1”
“0”
UiC0 register
TXEPT bit
“1”
“0”
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO
)
n: value set to UiBRG register
i: 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register CKDIR bit = 0 (internal clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
(2) Example of receive timing
“1”
UiC1 register
RE bit
“0”
“1”
UiC1 register
TE bit
“0”
“1”
“0”
“H”
Write dummy data to UiTB register
UiC1 register
TI bit
Transferred from UiTB register to UARTi transmit register
Even if the reception is completed, the RTS
does not change. The RTS becomes “L”
when the RI bit changes to “0” from “1”.
RTSi
CLKi
RxDi
“L”
1 / fEXT
Receive data is taken in
D
0
D1
D
2
D3
D
4
D5
D6
D
0
D
1
D
2
D4
D5
D
7
D3
Transferred from UARTi receive register
to UiRB register
Read out from UiRB register
“1”
“0”
UiC1 register
RI bit
“1”
“0”
SiRIC register
IR bit
Cleared to “0” when interrupt request is
accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register CKDIR bit = 1 (external clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transfer clock)
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
• UiC0 register TE bit = 1 (transmit enabled)
• UiC0 register RE bit = 1 (Receive enabled)
• Write dummy data to the UiTB register
Figure 14.1.1.1. Typical transmit/receive timings in clock synchronous serial I/O mode
Rev.0.60 2004.02.01 page 166 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
14.1.1.1 CLK Polarity Select Function
Use the UiC0 register (i = 0 to 2)’s CKPOL bit to select the transfer clock polarity. Figure 14.1.1.1.1
shows the polarity of the transfer clock.
(1) When the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLK
i
(Note 2)
D0
D
1
D
2
D
3
3
D
4
D
5
5
D
6
6
D
7
7
TXDi
D
0
D
1
D
2
D
D4
D
D
D
RXDi
(2) When the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
(Note 3)
CLK
i
D
0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
0
D
1
D
2
D
3
D
D
5
D
6
D7
RXDi
Note 1: This applies to the case where the UiC0 register’s UFORM bit = 0
(LSB first) and UiC1 register's UiLCH bit = 0 (no reverse).
Note 2: When not transferring, the CLKi pin outputs a high signal.
Note 3: When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 14.1.1.1.1. Polarity of transfer clock
14.1.1.2 LSB First/MSB First Select Function
Use the UiC0 register (i = 0 to 2)’s UFORM bit to select the transfer format. Figure 14.1.1.2.1 shows
the transfer format.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLK
i
D0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
1
D
2
D
3
D
D
5
D
6
D7
D0
RXDi
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLK
i
D
7
7
D
6
D
5
D
4
D
3
3
D
2
D
1
D0
TXDi
D
6
D
5
D
4
D
D
2
D
1
D0
D
RXDi
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UiC1 register’s
UiLCH bit = 0 (no reverse).
i = 0 to 2
Figure 14.1.1.2.1 Transfer format
Rev.0.60 2004.02.01 page 167 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
14.1.1.3 Continuous receive mode
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “0”
(data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do
not write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON
register bit 2 and bit 3, respectively, and the U2RRM bit is the U2C1 register bit 5.
14.1.1.4 Serial data logic switch function (UART2)
When the U2C1 register’s U2LCH bit = 1 (reverse), the data written to the U2TB register has its logic
reversed before being transmitted. Similarly, the received data has its logic reversed when read from
the U2RB register. Figure 14.1.1.4.1 shows serial data logic.
(1) When the U2C1 register's U2LCH bit = 0 (no reverse)
“H”
Transfer clock
“L”
“H”
2
TxD
(no reverse)
D0
D1
D2
D3
D4
D5
D6
D7
“L”
(2) When the U2C1 register's U2LCH bit = 1 (reverse)
“H”
Transfer clock
“L”
“H”
TxD
2
D0
D1
D2
D3
D4
D5
D6
D7
(reverse)
“L”
Note: This applies to the case where the U2C0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
Figure 14.1.1.4.1. Serial data logic switch timing
14.1.1.5 Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 14.1.1.5.1.)
The multiple pins function is valid only when the internal clock is selected for UART1.
Microcomputer
T
X
D1
(P67)
CLKS
1
1
(P6
4
)
)
CLK
(P65
IN
IN
CLK
CLK
Transfer enabled
when the UCON
register's
Transfer enabled
when the UCON
register's
CLKMD0 bit = 0
CLKMD0 bit = 1
Note: This applies to the case where the U1MRregister's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1 (
transfer clock output from multiple pins).
Figure 14.1.1.5.1 Transfer Clock Output From Multiple Pins
Rev.0.60 2004.02.01 page 168 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
_______ _______
14.1.1.6 CTS/RTS separate function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
IC
Microcomputer
TXD0 (P63)
IN
R
X
D0
(P62)
OUT
CLK
0
(P61
)
CLK
CTS
RTS
RTS
CTS
0
(P6
0)
0
(P64)
Figure 14.1.1.6.1. CTS/RTS separate function usage
Rev.0.60 2004.02.01 page 169 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
14.1.2. Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 14.1.2.1 lists the specifications of the UART mode.
Table 14.1.2.1. UART Mode Specifications
Item
Specification
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
Transfer data format
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
Transfer clock
• UiMR(i=0 to 2) register’s CKDIR bit = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
0016 to FF16
fEXT: Input from CLKi pin. n :Setting value of UiBRG register
0016 to FF16
_______
_______
Transmission, reception control • Selectable from CTS function, _R__T__S__ function or _C__T__S__/RTS function disable
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______
_______
_ If CTS function is selected, input on the CTSi pin = “L”
• Before reception can start, the following requirements must be met
_ The RE bit of UiC1 register= 1 (reception enabled)
_ Start bit detection
Reception start condition
• For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
Interrupt request
generation timing
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
• Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch (UART2)
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch (UART2)
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
• Separate _C__T__S__/R___T__S__ pins (UART0)
_________
CTS0 and _R__T__S___0_ are input/output from separate pins
Note 1: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Rev.0.60 2004.02.01 page 170 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
Table 14.1.2.2. Registers to Be Used and Settings in UART Mode
Register
UiTB
Bit
0 to 8
0 to 8
Function
Set transmission data (Note 1)
Reception data can be read (Note 1)
UiRB
OER,FER,PER,SUM Error flag
UiBRG
UiMR
0 to 7
Set a transfer rate
SMD2 to SMD0
Set these bits to ‘1002’ when transfer data is 7 bits long
Set these bits to ‘1012’ when transfer data is 8 bits long
Set these bits to ‘1102’ when transfer data is 9 bits long
Select the internal clock or external clock
CKDIR
STPS
Select the stop bit
PRY, PRYE
Select whether parity is included and whether odd or even
IOPOL(i=2)(Note 4) Select the TxD/RxD input/output polarity
UiC0
CLK0, CLK1
CRS
Select the count source for the UiBRG register
_______ _______
Select CTS or RTS to use
TXEPT
CRD
Transmit register empty flag
_______
_______
Enable or disable the CTS or RTS function
Select TxDi pin output mode
Set to “0”
NCH
CKPOL
UFORM
LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
bit to “0” when transfer data is 7 or 9 bits long.
UiC1
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS (Note 2)
U2RRM (Note 2)
UiLCH (Note 3)
UiERE (Note 3)
0 to 7
Select the source of UART2 transmit interrupt
Set to “0”
Set this bit to “1” to use UART2 inverted data logic
Set to “0”
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Set this bit to “1” to accept as input the UART0 C___T__S___0_ signal from the P64 pin
Set to “0”
7
Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long;
bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are included in the UCON register.
Note 3: Set the U0C1 and U1C1 registers bit 6 to bit 7 to “0”.
Note 4: Set the U0MR and U1MR registers bit 7 to “0”.
i=0 to 2
Rev.0.60 2004.02.01 page 171 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
Table 14.1.2.3 lists the functions of the input/output pins during UART mode. Table 14.1.2.4 lists the P64
pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected
to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this
pin is in a high-impedance state.)
Table 14.1.2.3. I/O Pin Functions in UART mode
Pin name
Function
Method of selection
TxDi (i = 0 to 2)
Serial data output
(Outputs "H" when performing reception only)
(P6
3, P6
7, P70)
Serial data input
RxDi
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input/output port when performing transmission only)
(P6 , P6
2
6
, P7
1
)
)
CLKi
(P6 , P6
Input/output port
UiMR register’s CKDIR bit=0
1
5, P7
2
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
Transfer clock input
CTSi/RTSi
(P6 , P6 , P73)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
CTS input
0
4
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
RTS output
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
Input/output port
UiC0 register’s CRD bit=1
Table 14.1.2.4. P64 Pin Functions in UART mode
Pin function
Bit set value
U1C0 register
UCON register
PD6 register
PD6_4
CLKMD1
RCSP
CRS
CRD
P64
1
0
0
0
0
0
0
1
0
0
0
0
Input: 0, Output: 1
0
CTS1
0
1
0
RTS1
CTS0 (Note)
0
Note: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0
enabled) and the U0C0 register’s CRS bit to “1” (RTS0 selected).
Rev.0.60 2004.02.01 page 172 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
Tc
Transfer clock
UiC1 register
“1”
TE bit
“0”
Write data to the UiTB register
UiC1 register
“1”
“0”
TI bit
Transferred from UiTB register to UARTi transmit register
“H”
“L”
CTSi
TxDi
Stopped pulsing
because the TE bit
= “0”
Start
bit
Parity Stop
bit bit
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D
7
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
D6
SP
UiC0 register
TXEPT bit
“1”
“0”
“1”
“0”
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register PRYE bit = 1 (parity enabled)
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO
EXT : frequency of UiBRG count source (external clock)
)
f
• UiMR register STPS bit = 0 (1 stop bit)
n : value set to UiBRG
i: 0 to 2
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiIRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
UiC1 register
Write data to the UiTB register
TE bit
“0”
“1”
UiC1 register
TI bit
“0”
Transferred from UiTB register to UARTi
transmit register
Start
bit
Stop Stop
bit bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
D8
ST
D0
D1
D2
D3
D4
D5
D7
D8
SPSP
D6
SP SP
D6
“1”
“0”
UiC0 register
TXEPT bit
“1”
“0”
SiTIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO
EXT : frequency of UiBRG count source (external clock)
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register PRYE bit = 0 (parity disabled)
)
f
• UiMR register STPS bit = 1 (2 stop bits)
n : value set to UiBRG
i: 0 to 2
• UiC0 register CRD bit = 1 (CTS/RTS disabled)
• UiIRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Figure 14.1.2.1. Typical transmit timing in UART mode (UART0, UART1)
Rev.0.60 2004.02.01 page 173 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
“1”
“0”
UiC1 register
RE bit
Stop bit
Start bit
Sampled “L”
D
1
D7
RxDi
D0
Receive data taken in
Transfer clock
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Transferred from UARTi receive
register to UiRB register
UiC1 register
RI bit
“0”
“H”
“L”
RTSi
“1”
“0”
SiRIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 14.1.2.2. Receive Operation
14.1.2.1. LSB First/MSB First Select Function
As shown in Figure 14.1.2.1.1, use the UiC0 register’s UFORM bit to select the transfer format. This
function is valid when transfer data is 8 bits long.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLK
i
ST
ST
D0
D
1
D
2
D
3
D
4
4
D
5
D
6
D
7
7
P
P
SP
SP
TXDi
D0
D
1
D
2
D
3
D
D
5
D6
D
RXDi
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLK
i
T
X
D
i
D
6
D
5
D
4
D
3
D
2
D
1
D0
ST
ST
P
P
SP
SP
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D0
RXDi
D
7
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiC1 register’s UiLCH
bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and
UiMR register's PRYE bit = 1 (parity enabled).
Figure 14.1.2.1.1. Transfer Format
Rev.0.60 2004.02.01 page 174 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1 UARTi (i=0 to 2)
14.1.2.2. Serial Data Logic Switching Function (UART2)
The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the U2RB register. Figure 14.1.2.2.1 shows serial
data logic.
(1) When the U2C1 register's U2LCH bit = 0 (no reverse)
“H”
Transfer clock
“L”
“H”
TxD
2
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(no reverse)
“L”
(2) When the U2C1 register's U2LCH bit = 1 (reverse)
“H”
Transfer clock
“L”
“H”
TxD
2
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(reverse)
“L”
Note: This applies to the case where the U2C0 register’s CKPOL bit = 0
(transmit data output at the falling edge of the transfer clock), the
U2C0 register's UFORM bit = 0 (LSB first), the U2MR register's
STPS bit = 0 (1 stop bit) and U2MR register's PRYE bit = 1 (parity
enabled).
ST : Start bit
P : Parity bit
SP : Stop bit
Figure 14.1.2.2.1. Serial Data Logic Switching
14.1.2.3. TxD and RxD I/O Polarity Inverse Function (UART2)
This function inverses the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all
input/output data (including the start, stop and parity bits) are inversed. Figure 14.1.2.3.1 shows the
TXD pin output and RXD pin input polarity inverse.
(1) When the U2MR register's IOPOL bit = 0 (no reverse)
“H”
Transfer clock
“L”
“H”
2
(no reverse) “L”
TxD
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
“H”
RxD
2
“L”
(no reverse)
(2) When the U2MR register's IOPOL bit = 1 (reverse)
“H”
Transfer clock
“L”
“H”
TxD
2
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(reverse) “L”
“H”
RxD
2
“L”
(reverse)
ST : Start bit
P : Parity bit
SP : Stop bit
Note: This applies to the case where the U2C0 register's UFORM bit = 0
(LSB first), the U2MR register's STPS bit = 0 (1 stop bit) and the
U2MR register's PRYE bit = 1 (parity enabled).
Figure 14.1.2.3.1. TXD and RXD I/O Polarity Inverse
Rev.0.60 2004.02.01 page 175 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1 UARTi (i=0 to 2)
M16C/28 Group
_______ _______
14.1.2.4. CTS/RTS Separate Function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
IC
Microcomputer
T
X
D0
(P6
3)
IN
R
X
D0
(P6
2)
OUT
CTS
RTS
RTS
0
(P6
(P6
0)
CTS
0
4)
_______ _______
Figure 1.19.6. CTS/RTS Separate Function
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Specifications in this manual are tentative and subject to change.
2
14.1.3 Special Mode 1 (I C Bus mode) (UART2)
M16C/28 Group
2
14.1.3 Special Mode 1 (I C Bus mode)(UART2)
2
2
II C mode is provided for use as a simplified I C interface compatible mode. Table 14.1.3.1 lists the
2
2
specifications of the I C mode. Table 14.1.3.2 and 14.1.3.3 list the registers used in the I C mode and the
2
register values set. Table 14.1.3.4 lists the I C mode fuctions. Figure 14.1.3.1 shows the block diagram
2
for I C mode. Figure 14.1.3.2 shows SCL2 timing.
2
As shown in Table 14.1.3.2, the microcomputer is placed in I C mode by setting the SMD2 to SMD0 bits
to ‘0102’ and the IICM bit to “1”. Because SDA2 transmit output has a delay circuit attached, SDA output
does not change state until SCL2 goes low and remains stably low.
2
Table 14.1.3.1. I C Bus Mode Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• During master
U2MR register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register 0016 to FF16
• During slave
CKDIR bit = “1” (external clock) : Input from SCL pin
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of U2C1 register= 1 (transmission enabled)
_ The TI bit of U2C1 register = 0 (data present in U2TB register)
Reception start condition
• Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of U2C1 register= 1 (reception enabled)
_ The TE bit of U2C1 register= 1 (transmission enabled)
_ The TI bit of U2C1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Interrupt request
generation timing
Error detection
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 8th bit of the next data
• Arbitration lost
Select function
Timing at which the U2RB register’s ABT bit is updated can be selected
• SDA digital delay
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the
high state.
Note 2: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC
register does not change
.
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Specifications in this manual are tentative and subject to change.
2
14.1.3 Special Mode 1 (I C Bus mode) (UART2)
M16C/28 Group
Start and stop condition generation block
SDA2
DMA0, DMA1 request
(UART1: DMA0 only)
STSPSEL=1
SDASTSP
SCLSTSP
Delay
circuit
STSPSEL=0
ACKC=0
IICM2=1
Transmission
register
UART2 transmit,
NACK interrupt
request
ACKC=1
ACKD bit
IICM=1 and
IICM2=0
UART2
SDHI
ALS
DMA0
(UART0, UART2)
D
Q
T
Arbitration
Noise
Filter
IICM2=1
UART2 receive,
ACK interrupt request,
DMA1 request
Reception register
UART2
IICM=1 and
IICM2=0
Start condition
detection
S
R
Bus
busy
Q
Stop condition
detection
NACK
D
Q
T
Falling edge
detection
SCL2
D
Q
ACK
T
R
Port register
(Note)
IICM=0
I/O port
STSPSEL=0
9th bit
Q
Internal clock
Start/stop condition detection
interrupt request
SWC2
External
clock
CLK
control
UART2
IICM=1
STSPSEL=1
Noise
Filter
UART2
9th bit falling edge
SWC
R
S
This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 0102 and the UiSMR register's IICM bit = 1.
IICM : UiSMR register bit
IICM2, SWC, ALS, SWC2, SDHI : UiSMR2 register bit
STSPSEL, ACKD, ACKC : UiSMR4 register bit
Note: If the IICM bit = 1, the pin can be read even when the PD7_1 bit = 1 (output mode).
2
Figure 14.1.3.1. I C Bus Mode Block Diagram
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Specifications in this manual are tentative and subject to change.
2
14.1.3 Special Mode 1 (I C Bus mode) (UART2)
M16C/28 Group
Table 14.1.3.2. Registers to Be Used and Settings in I2C Bus Mode (1) (Continued)
Register
Bit
Function
Master
Set transmission data
Slave
Set transmission data
U2TB
0 to 7
(Note 1)
U2RB
(Note 1)
0 to 7
8
ABT
OER
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to ‘0102’
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
U2BRG 0 to 7
U2MR SMD2 to SMD0
Set to ‘0102’
(Note 1) CKDIR
IOPOL
Set to “0”
Set to “0”
Set to “1”
Set to “0”
U2C0
CLK1, CLK0
Select the count source for the U2BRG
register
Invalid
CRS
TXEPT
CRD
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
NCH
Set to “1”
Set to “1”
CKPOL
UFORM
TE
Set to “0”
Set to “1”
Set to “0”
Set to “1”
U2C1
Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission
TI
RE
RI
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
U2IRS
U2RRM,
U2LCH, U2ERE
Set to “0”
Set to “0”
U2SMR IICM
ABC
Set to “1”
Set to “1”
Select the timing at which arbitration-lost Invalid
is detected
BBS
3 to 7
U2SMR2 IICM2
CSC
Bus busy flag
Set to “0”
Refer to Table "I C Mode Functions”
Set this bit to “1” to enable clock
synchronization
Bus busy flag
Set to “0”
Refer to Table " I C Mode Functions”
Set to “0”
2
2
SWC
Set this bit to “1” to have SCL2 output
fixed to “L” at the falling edge of the 9th
bit of clock
Set this bit to “1” to have SCL2 output
fixed to “L” at the falling edge of the 9th
bit of clock
ALS
Set this bit to “1” to have SDA2 output
stopped when arbitration-lost is detected
Set to “0”
Set to “0”
STAC
SWC2
Set this bit to “1” to initialize UART2 at
start condition detection
Set this bit to “1” to have SCL2 output
forcibly pulled low
Set this bit to “1” to have SCL2 output
forcibly pulled low
SDHI
7
Set this bit to “1” to disable SDA2 output Set this bit to “1” to disable SDA2 output
Set to “0”
Set to “0”
Set to “0”
U2SMR3 0, 2, 4 and NODC Set to “0”
2
2
CKPH
Refer to Table "I C Mode Functions”
Refer to Table "I C Mode Functions”
DL2 to DL0
Set the amount of SDA2 digital delay
Set the amount of SDA2 digital delay
Note 1: Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C Bus
mode.
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Specifications in this manual are tentative and subject to change.
2
14.1.3 Special Mode 1 (I C Bus mode) (UART2)
M16C/28 Group
Table 14.1.3.3. Registers to Be Used and Settings in I2C Bus Mode (2) (Continued)
Register
Bit
Function
Master
Set this bit to “1” to generate start
condition
Set this bit to “1” to generate restart
condition
Slave
U2SMR4 STAREQ
RSTAREQ
Set to “0”
Set to “0”
Set to “0”
STPREQ
Set this bit to “1” to generate stop
condition
STSPSEL
ACKD
Set this bit to “1” to output each condition Set to “0”
Select ACK or NACK
Select ACK or NACK
ACKC
SCLHI
Set this bit to “1” to output ACK data
Set this bit to “1” to have SCL2 output
stopped when stop condition is detected
Set to “0”
Set this bit to “1” to output ACK data
Set to “0”
SWC9
Set this bit to “1” to set the SCL2 to “L”
hold at the falling edge of the 9th bit of
clock
2
Note 1: Not all register bits are described above. Set those bits to “0” when writing to the registers in I C Bus
mode.
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Specifications in this manual are tentative and subject to change.
2
14.1.3 Special Mode 1 (I C Bus mode) (UART2)
M16C/28 Group
2
Table 14.1.3.4. I C Bus Mode Functions
Clock synchronous serial I/O
mode (SMD2 to SMD0 = 001
IICM = 0)
I2C mode (SMD2 to SMD0 = 010
2, IICM = 1)
Function
2,
IICM2 = 0
IICM2 = 1
(NACK/ACK interrupt)
(UART transmit/ receive interrupt)
CKPH = 1
CKPH = 0
CKPH = 1
CKPH = 0
(Clock delay)
(No clock delay) (Clock delay) (No clock delay)
Factor of interrupt number
10 (Note 1) (Refer to Fig.
14.1.3.2.)
Start condition detection or stop condition detection
(Refer to Fig 14.1.3.4.)
Factor of interrupt number
15 (Note 1) (Refer to Fig.
14.1.3.2.)
No acknowledgment
detection (NACK)
Rising edge of SCL2 9th bit
UART2 transmission
Transmission started or
completed (selected by U2IRS)
UART2 transmission UART2 transmission
Rising edge of
SCL 9th bit
UART2 transmission
Falling edge of SCL
next to the 9th bit
2
2
Factor of interrupt number UART2 reception
16 (Note 1) (Refer to Fig. When 8th bit received
Acknowledgment detection
(ACK)
Falling edge of SCL
2
9th bit
14.1.3.2.)
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Rising edge of SCL
2
9th bit
Timing for transferring data
from the UART reception
shift register to the U2RB
register
Falling and rising
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Falling edge of
SCL2 9th bit
Rising edge of SCL
2
9th bit
edges of SCL2 9th
bit
UART2 transmission
output delay
Delayed
Not delayed
TxD2 output
SDA
SCL
2
input/output
input/output
Functions of P7
0
pin
pin
pin
2
Functions of P7
Functions of P7
1
2
RxD2 input
(Cannot be used in I2C mode)
CLK2 input or output selected
Noise filter width
200ns
15ns
Read RxD2 and SCL
levels
2
pin Possible when the
corresponding port direction bit
= 0
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I2C mode (Note 2)
CKPOL = 0 (H)
CKPOL = 1 (L)
Initial value of TxD2 and
SDA outputs
2
Initial and end values of
SCL
H
L
H
L
2
UART2 reception
DMA1 factor (Refer to Fig.
14.1.3.2.)
Acknowledgment detection
(ACK)
UART2 reception
Falling edge of SCL
2
9th bit
Store received data
1st to 8th bits are stored in
U2RB register bit 0 to bit 7
1st to 8th bits are stored in
U2RB register bit 7 to bit 0
1st to 7th bits are stored in U2RB register
bit 6 to bit 0, with 8th bit stored in U2RB
register bit 8
1st to 8th bits are
stored in U2RB
register bit 7 to bit 0
(Note 3)
Read received data
Read U2RB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 (Note 4)
U2RB register status is read
directly as is
Note 1: If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to 1 (interrupt requested). (Refer to Notes on interrupts in Precautions.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore,
.
always be sure to clear the IR bit to 0 (interrupt not requested) after changing those bits.
.
SMD2—SMD0 bits in the U2MR register, IICM bit in the U2SMR register,
IICM2 bit in the U2SMR2 register, CKPH bit in the U2SMR3 register
Note 2: Set the initial value of SDA2 output while the U2MR register s SMD2 to SMD0 bits = 0002 (serial I/O disabled).
Note 3: Second data transfer to U2RB register (Rising edge of SCL2 9th bit)
Note 4. First data transfer to U2RB register (Falling edge of SCL2 9th bit)
Rev.0.60 2004.02.01 page 181 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
2
14.1.3 Special Mode 1 (I C Bus mode) (UART2)
M16C/28 Group
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to U2RB register
b15
b9
b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
•••
U2RB register
(2) IICM2= 0, CKPH= 1 (clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to U2RB register
b15
b9
b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
•••
U2RB register
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transmit interrupt
Transfer to U2RB register
b15
b9
b8 b7
D0
b0
D7 D6 D5 D4 D3 D2 D1
•••
U2RB register
(4) IICM2= 1, CKPH= 1
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D1
D0
D8
(ACK, NACK)
Receive interrupt
(DMA1 request)
Transmit interrupt
Transfer to U2RB register Transfer to U2RB register
b15
b9
b8 b7
D0
b0
b15
b9
b8 b7
b0
D7 D6 D5 D4 D3 D2 D1
D8 D7 D6 D5 D4 D3 D2 D1 D0
•••
•••
U2RB register
U2RB register
This diagram applies to the case where the following condition is met.
• U2MR register CKDIR bit = 0 (Slave selected)
Figure 14.1.3.2. Transfer to U2RB Register and Interrupt Timing
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Preliminary specification
Specifications in this manual are tentative and subject to change.
2
14.1.3 Special Mode 1 (I C Bus mode) (UART2)
M16C/28 Group
14.1.3.1 Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDA2 pin changes state from high
to low while the SCL2 pin is in the high state. A stop condition-detected interrupt request is generated
when the SDA2 pin changes state from low to high while the SCL2 pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the U2SMR register’s BBS bit to determine which interrupt source is requesting the inter-
rupt.
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
Duration for
setting up
Duration for
holding
SCL2
SDA2
(Start condition)
SDA2
(Stop condition)
Note: When the PCLKR register's PCLK1 bit = "1", this is the cycle number of
f1SIO; when PCLK1 bit = "0", this is the cycle number of f2SIO.
Figure 14.1.3.1.1. Detection of Start and Stop Condition
14.1.3.2 Output of Start and Stop Condition
A start condition is generated by setting the U2SMR4 register’s STAREQ bit to “1” (start).
A restart condition is generated by setting the U2SMR4 register’s RSTAREQ bit to “1” (start).
A stop condition is generated by setting the U2SMR4 register’s STPREQ bit to “1” (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the U2SMR4 register to “1” (output).
Make sure that no interrupts or DMA transfers will occur between (1) and (2).
The function of the STSPSEL bit is shown in Table 14.1.3.2.1 and Figure 14.1.3.2.1.
Rev.0.60 2004.02.01 page 183 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
2
14.1.3 Special Mode 1 (I C Bus mode) (UART2)
M16C/28 Group
Table 14.1.3.2.1. STSPSEL Bit Functions
Function
STSPSEL = 0
Output of transfer clock and
data
STSPSEL = 1
Output of SCL2 and SDA2 pins
Output of a start/stop condition
according to the STAREQ,
Output of start/stop condition is RSTAREQ and STPREQ bit
accomplished by a program
using ports (not automatically
generated in hardware)
Start/stop condition interrupt
request generation timing
Start/stop condition detection
Finish generating start/stop condi-
tion
(1) When slave
CKDIR="1" (external clock)
STPSEL bit (= "0")
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCL2
SDA2
Start condition
detection interrupt
Stop condition
detection interrupt
(2) When master
CKDIR="0" (internal clock), CKPH="1" (clock delayed)
STPSEL bit
Set to “1” in
a program
Set to “0” in
a program
Set to “1” in
a program
Set to “0” in
a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCL2
SDA2
Set STAREQ=
"1" (start)
Set STPREQ=
"1" (start)
Stop condition
detection interrupt
Start condition
detection interrupt
Figure 14.1.3.2.1. STSPSEL Bit Functions
14.1.3.3 Arbitration
Unmatching of the transmit data and SDA2 pin input data is checked synchronously with the rising
edge of SCL2. Use the U2SMR register’s ABC bit to select the timing at which the U2RB register’s
ABT bit is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time
unmatching is detected during check, and is cleared to “0” when not detected. In cases when the ABC
bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to “1” (unmatching
detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise,
clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte, before transferring
the next byte.
Setting the U2SMR2 register’s ALS bit to “1” (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDA2 pin is placed in the high-impedance state at the same time the ABT bit
is set to “1” (unmatching detected).
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Specifications in this manual are tentative and subject to change.
2
14.1.3 Special Mode 1 (I C Bus mode) (UART2)
M16C/28 Group
14.1.3.4 Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 14.1.3.2.1.
The U2SMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCL2)
and an external clock supplied to the SCL2 pin. In cases when the CSC bit is set to “1” (clock synchro-
nization enabled), if a falling edge on the SCL2 pin is detected while the internal SCL2 is high, the
internal SCL2 goes low, at which time the U2BRG register value is reloaded with and starts counting in
the low-level interval. If the internal SCL2 changes state from low to high while the SCL2 pin is low,
counting stops, and when the SCL2 pin goes high, counting restarts.
In this way, the UART2 transfer clock is comprised of the logical product of the internal SCL2 and SCL2
pin signal. The transfer clock works from a half period before the falling edge of the internal SCL2 1st
th
bit to the rising edge of the 9 bit. To use this function, select an internal clock for the transfer clock.
The U2SMR2 register’s SWC bit allows to select whether the SCL2 pin should be fixed to or freed from
low-level output at the falling edge of the 9th clock pulse.
If the U2SMR4 register’s SCLHI bit is set to “1” (enabled), SCL2 output is turned off (placed in the high-
impedance state) when a stop condition is detected.
Setting the U2SMR2 register’s SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level
signal from the SCL2 pin even while sending or receiving data. Clearing the SWC2 bit to “0” (transfer
clock) allows the transfer clock to be output from or supplied to the SCL2 pin, instead of outputting a
low-level signal.
If the U2SMR4 register’s SWC9 bit is set to “1” (SCL hold low enabled) when the U2SMR3 register’s
CKPH bit = 1, the SCL2 pin is fixed to low-level output at the falling edge of the clock pulse next to the
ninth. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCL2 pin from low-level output.
14.1.3.5 SDA Output
The data written to the U2TB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7.
The ninth bit (D8) is ACK or NACK.
2
The initial value of SDA2 transmit output can only be set when IICM = 1 (I C Bus mode) and the U2MR
register’s SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).
The U2SMR3 register’s DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 U2BRG count
source clock cycles to SDA2 output.
Setting the U2SMR2 register’s SDHI bit = 1 (SDA output disabled) forcibly places the SDA2 pin in the
high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UART2
transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).
14.1.3.6 SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the U2RB register
bit 7 to bit 0. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the U2RB register
bit 6 to bit 0 and the 8th bit (D0) is stored in the U2RB register bit 8. Even when the IICM2 bit = 1,
providing the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the
U2RB register after the rising edge of the corresponding clock pulse of 9th bit.
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Specifications in this manual are tentative and subject to change.
2
14.1.3 Special Mode 1 (I C Bus mode) (UART2)
M16C/28 Group
14.1.3.7 ACK and NACK
If the STSPSEL bit in the U2SMR4 register is set to “0” (start and stop conditions not generated) and
the ACKC bit in the U2SMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the
U2SMR4 register is output from the SDA2 pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDA2 pin remains high at the rising
edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDA2 pin is low
at the rising edge of the 9th bit of transmit clock pulse.
If ACK2 is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
14.1.3.8 Initialization of Transmission/Reception
If a start condition is detected while the STAC bit = 1 (UART2 initialization enabled), the serial I/O
operates as described below.
- The transmit shift register is initialized, and the content of the U2TB register is transferred to the
transmit shift register. In this way, the serial I/O starts sending data synchronously with the next
clock pulse applied. However, the UART2 output value does not change state and remains the
same as when a start condition was detected until the first bit of data is output synchronously with
the input clock.
- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the
next clock pulse applied.
- The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCL2 pin is pulled low at the
falling edge of the ninth clock pulse.
Note that when UART2 transmission/reception is started using this function, the TI does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.
Rev.0.60 2004.02.01 page 186 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1.4 Special Mode 2 (UART2)
M16C/28 Group
14.1.4 Special Mode 2 (UART2)
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 14.1.4.1 lists the specifications of Special Mode 2. Table 14.1.4.2 lists the registers
used in Special Mode 2 and the register values set. Figure 14.1.4.1 shows communication control ex-
ample for Special Mode 2.
Table 14.1.4.1. Special Mode 2 Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• Master mode
U2MR register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register 0016 to FF16
• Slave mode
CKDIR bit = “1” (external clock selected) : Input from CLK2 pin
Controlled by input/output ports
Transmit/receive control
Transmission start condition • Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of U2C1 register= 1 (transmission enabled)
_ The TI bit of U2C1 register = 0 (data present in U2TB register)
Reception start condition
• Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of U2C1 register= 1 (reception enabled)
_ The TE bit of U2C1 register= 1 (transmission enabled)
_ The TI bit of U2C1 register= 0 (data present in the U2TB register)
• For transmission, one of the following conditions can be selected
_ The U2IRS bit of U2C1 register = 0 (transmit buffer empty): when transferring data
from the U2TB register to the UART2 transmit register (at start of transmission)
_ The U2IRS bit =1 (transfer completed): when the serial I/O finished sending data
from the UART2 transmit register
Interrupt request
generation timing
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Error detection
Select function
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the 7th bit of the next data
• Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
Note 1: When an external clock is selected, the conditions must be met while if the U2C0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the U2C0 register’s CKPOL bit = “1” (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low
state.
Note 2: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC register does
not change.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1.4 Special Mode 2 (UART2)
M16C/28 Group
P1
P1
3
2
P9
P72(CLK
P71(RxD
P70(TxD
3
P72(CLK
2
)
2
)
P71(RxD
2
)
2
)
P70(TxD
2
)
2
)
Microcomputer
(Master)
Microcomputer
(Slave)
P93
P72(CLK
2
)
)
P71(RxD
2
P70(TxD )
2
Microcomputer
(Slave)
Figure 14.1.4.1. Serial Bus Communication Control Example (UART2)
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Specifications in this manual are tentative and subject to change.
14.1.4 Special Mode 2 (UART2)
M16C/28 Group
Table 14.1.4.2. Registers to Be Used and Settings in Special Mode 2
Register
Bit
Function
Set transmission data
Reception data can be read
Overrun error flag
Set a transfer rate
Set to ‘0012’
U2TB(Note) 0 to 7
U2RB(Note) 0 to 7
OER
U2BRG
0 to 7
U2MR(Note) SMD2 to SMD0
CKDIR
IOPOL
Set this bit to “0” for master mode or “1” for slave mode
Set to “0”
U2C0
U2C1
CLK1, CLK0
CRS
TXEPT
CRD
Select the count source for the U2BRG register
Invalid because CRD = 1
Transmit register empty flag
Set to “1”
NCH
Select TxD2 pin output format
Clock phases can be set in combination with the U2SMR3 register's CKPH bit
Select the LSB first or MSB first
Set this bit to “1” to enable transmission
Transmit buffer empty flag
CKPOL
UFORM
TE
TI
RE
RI
Set this bit to “1” to enable reception
Reception complete flag
U2IRS
U2RRM,
U2LCH, U2ERE
0 to 7
Select UART2 transmit interrupt cause
Set to “0”
U2SMR
Set to “0”
U2SMR2
U2SMR3
0 to 7
Set to “0”
CKPH
NODC
0, 2, 4 to 7
0 to 7
Clock phases can be set in combination with the U2C0 register's CKPOL bit
Set to “0”
Set to “0”
Set to “0”
U2SMR4
Note : Not all register bits are described above. Set those bits to “0” when writing to the registers in Special
Mode 2.
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Specifications in this manual are tentative and subject to change.
14.1.4 Special Mode 2 (UART2)
M16C/28 Group
14.1.4.1 Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the U2SMR3
register’s CKPH bit and the U2C0 register’s CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and slave to communi-
cate.
14.1.4.1.1 Master (Internal Clock)
Figure 14.1.4.1.1.1 shows the transmission and reception timing in master (internal clock).
14.1.4.1.2 Slave (External Clock)
Figure 14.1.4.1.2.1 shows the transmission and reception timing (CKPH=0) in slave (external clock)
while Figure 14.1.4.1.2.2 shows the transmission and reception timing (CKPH=1) in slave (external
clock).
"H"
Clock output
"L"
(CKPOL=0, CKPH=0)
"H"
"L"
Clock output
(CKPOL=1, CKPH=0)
Clock output
(CKPOL=0, CKPH=1)
"H"
"L"
"H"
"L"
Clock output
(CKPOL=1, CKPH=1)
"H"
"L"
Data output timing
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Figure 14.1.4.1.1.1. Transmission and Reception Timing in Master Mode (Internal Clock)
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Specifications in this manual are tentative and subject to change.
14.1.4 Special Mode 2 (UART2)
M16C/28 Group
"H"
Slave control input
"L"
"H"
"L"
Clock input
(CKPOL=0, CKPH=0)
"H"
"L"
Clock input
(CKPOL=1, CKPH=0)
"H"
"L"
Data output timing
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Indeterminate
Figure 14.1.4.1.2.1. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)
"H"
Slave control input
"L"
"H "
Clock input
"L"
(CKPOL=0, CKPH=1)
"H "
"L "
Clock input
(CKPOL=1, CKPH=1)
"H "
"L"
Data output timing
Data input timing
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D 7
.
Figure 14.1.4.1.2.2. Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
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Specifications in this manual are tentative and subject to change.
14.1.5 Special Mode 3 (IE Bus Mode) (UART2)
M16C/28 Group
14.1.5 Special Mode 3 (IE Bus mode)(UART2)
In this mode, one bit of IE Bus is approximated with one byte of UART mode waveform.
Table 14.1.5.1 lists the registers used in IE Bus mode and the register values set. Figure 14.1.5.1 shows
the functions of bus collision detect function related bits.
If the TxD2 pin output level and RxD2 pin input level do not match, a UART2 bus collision detect interrupt
request is generated.
Use the IFSR2A register’s IFSR26 and IFSR27 bits to enable the UART0/UART1 bus collision detect
function.
Table 14.1.5.1. Registers to Be Used and Settings in IE Bus Mode
Register
U2TB
Bit
Function
Set transmission data
Reception data can be read
OER,FER,PER,SUM Error flag
0 to 8
U2RB(Note) 0 to 8
U2BRG
U2MR
0 to 7
Set a transfer rate
SMD2 to SMD0
CKDIR
STPS
Set to ‘1102’
Select the internal clock or external clock
Set to “0”
PRY
Invalid because PRYE=0
Set to “0”
PRYE
IOPOL
CLK1, CLK0
CRS
Select the TxD/RxD input/output polarity
Select the count source for the U2BRG register
Invalid because CRD=1
Transmit register empty flag
Set to “1”
U2C0
TXEPT
CRD
NCH
Select TxD2 pin output mode
Set to “0”
CKPOL
UFORM
TE
Set to “0”
U2C1
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
0 to 3, 7
ABSCS
ACSE
SSS
U2SMR
Set to “0”
Select the sampling timing at which to detect a bus collision
Set this bit to “1” to use the auto clear function of transmit enable bit
Select the transmit start condition
U2SMR2
U2SMR3
U2SMR4
0 to 7
Set to “0”
Set to “0”
Set to “0”
0 to 7
0 to 7
Note : Not all register bits are described above. Set those bits to “0” when writing to the registers in IE Bus
mode.
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Specifications in this manual are tentative and subject to change.
14.1.5 Special Mode 3 (IE Bus Mode) (UART2)
M16C/28 Group
(1) U2SMR register ABSCS bit (bus collision detect sampling clock select)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxD2
RxD2
Input to TAjIN
Timer Aj
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: timer A0 when UART2
(2) U2SMR register ACSE bit (auto clear of transmit enable bit)
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxD2
RxD2
U2BCNIC register
IR bit (Note)
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to 0
(transmission disabled) when
the U2BCNIC register s IR bit = 1
(unmatching detected).
U2C1 register
TE bit
Note: BCNIC register when UART2.
(3) U2SMR register SSS bit (Transmit start condition select)
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
TxD2
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxD2
CLK2
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
(Note 2)
TxD2
RxD2
Note 1: The falling edge of RxD2 when IOPOL=0; the rising edge of RxD2 when IOPOL = 1.
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where IOPOL=1 (reversed).
Figure 14.1.5.1. Bus Collision Detect Function-Related Bits
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14.1.6 Special Mode 4 (SIM Mode) (UART2)
M16C/28 Group
14.1.6 Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected.
Tables 14.1.6.1 lists the specifications of SIM mode. Table 14.1.6.2 lists the registers used in the SIM
mode and the register values set.
Table 14.1.6.1. SIM Mode Specifications
Item
Specification
Transfer data format
• Direct format
• Inverse format
Transfer clock
• U2MR register’s CKDIR bit = “0” (internal clock) : fi/ 16(n+1)
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
0016 to FF16
0016 to FF16
fEXT: Input from CLK2 pin. n: Setting value of U2BRG register
Transmission start condition • Before transmission can start, the following requirements must be met
_ The TE bit of U2C1 register= 1 (transmission enabled)
_ The TI bit of U2C1 register = 0 (data present in U2TB register)
Reception start condition
• Before reception can start, the following requirements must be met
_ The RE bit of U2C1 register= 1 (reception enabled)
_ Start bit detection
• For transmission
Interrupt request
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit =1)
• For reception
generation timing
(Note 2)
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Error detection
• Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Note 1: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC
register does not change.
Note 2: A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmis-
sion complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM
mode, be sure to clear the IR bit to “0” (no interrupt request) after setting these bits.
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1.6 Special Mode 4 (SIM Mode) (UART2)
Table 14.1.6.2. Registers to Be Used and Settings in SIM Mode
Register
Bit
Function
Set transmission data
Reception data can be read
U2TB(Note) 0 to 7
U2RB(Note) 0 to 7
OER,FER,PER,SUM Error flag
U2BRG
U2MR
0 to 7
Set a transfer rate
Set to ‘1012’
Select the internal clock or external clock
Set to “0”
SMD2 to SMD0
CKDIR
STPS
PRY
Set this bit to “1” for direct format or “0” for inverse format
PRYE
Set to “1”
Set to “0”
IOPOL
U2C0
CLK1, CLK0
CRS
Select the count source for the U2BRG register
Invalid because CRD=1
TXEPT
CRD
Transmit register empty flag
Set to “1”
NCH
Set to “0”
CKPOL
UFORM
TE
Set to “0”
Set this bit to “0” for direct format or “1” for inverse format
U2C1
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS
U2RRM
U2LCH
U2ERE
Set to “1”
Set to “0”
Set this bit to “0” for direct format or “1” for inverse format
Set to “1”
Set to “0”
Set to “0”
Set to “0”
Set to “0”
U2SMR(Note) 0 to 3
U2SMR2
U2SMR3
U2SMR4
0 to 7
0 to 7
0 to 7
Note: Not all register bits are described above. Set those bits to “0” when writing to the registers in SIM mode.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1.6 Special Mode 4 (SIM Mode) (UART2)
M16C/28 Group
(1) Transmission
Tc
Transfer clock
“1”
“0”
“1”
U2C1 register
TE bit
Write data to U2TB register
U2C1 register
TI bit
“0”
Transferred from U2TB register to UART2 transmit register
Parity Stop
Start
bit
bit
bit
TxD
2
ST
D
0
0
D
1
1
D
2
2
D
3
3
D
4
4
D
5
5
D
7
P
SP
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
D
6
6
D6
SP
Parity error signal sent
back from receiver
An “L” level returns due to the
occurrence of a parity error.
RxD2
pin level
(Note)
ST
D
D
D
D
D
D
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
D
D6
SP
The level is detected by the
interrupt routine.
“1”
“0”
U2C0 register
TXEPT bit
The level is
detected by the
interrupt routine.
The IR bit is set to “1” at the
falling edge of transfer clock
“1”
“0”
S2TIC register
IR bit
The above timing diagram applies to the case where data is
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO
EXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
)
f
Note : Because TxD
2
and RxD
2
are connected, this is composite waveform consisting of the TxD
2
output and the parity error signal
sent back from receiver.
(1) Reception
Tc
Transfer clock
“1”
“0”
U2C1 register
RE bit
Stop
bit
Parity
bit
Start
bit
Transmitter's
transmit waveform
SP
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
SP
ST
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
D
6
D6
TxD2
An “L” level is output from TxD
the occurrence of a parity error
2 due to
RxD2
pin level
(Note)
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
D0
D1
D2
D3
D4
D5
D7
P
D6
D6
SP
“1”
“0”
U2C0 register
RI bit
Read the U2RB register
Read the U2RB register
“1”
“0”
S2RIC register
IR bit
The above timing diagram applies to the case where data is
transferred in the direct format.
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO
)
f
EXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Note : Because TxD
2 and RxD2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the
parity error signal received.
Figure 14.1.6.1. Transmit and Receive Timing in SIM Mode
Rev.0.60 2004.02.01 page 196 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
14.1.6 Special Mode 4 (SIM Mode) (UART2)
Figure 14.1.6.2 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.
Microcomputer
SIM card
TxD
2
2
RxD
Figure 14.1.6.2. SIM Interface Connection
14.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2C1 register’s U2ERE bit to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 14.1.6.1.1. If the R2RB register is read
while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output
is returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.
“H”
Transfer
“L”
clock
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RxD
2
“L”
“H”
“L”
(Note)
TxD
2
“1”
“0”
U2C1 register
RI bit
This timing diagram applies to the case where the direct format is
implemented.
ST : Start bit
P : Even Parity
SP : Stop bit
Note: The output of microcomputer is in the high-impedance state
(pulled up externally).
Figure 14.1.6.1.1. Parity Error Signal Output Timing
Rev.0.60 2004.02.01 page 197 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.1.6 Special Mode 4 (SIM Mode) (UART2)
M16C/28 Group
14.1.6.2 Format
• Direct Format
Set the U2MR register's PRY bit to “1”, U2C0 register's UFORM bit to “0” and U2C1 register's U2LCH
bit to “0”.
• Inverse Format
Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”.
Figure 14.1.6.2.1 shows the SIM interface format.
(1) Direct format
“H”
Transfer
“L”
clcck
“H”
TxD
2
D0
D1
D2
D3
D4
D5
D6
D7
P
“L”
P : Even parity
(2) Inverse format
“H”
Transfer
“L”
clcck
“H”
TxD
2
D7
D6
D5
D4
D3
D2
D1
D0
P
“L”
P : Odd parity
Figure 14.1.6.2.1. SIM Interface Format
Rev.0.60 2004.02.01 page 198 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.2 SI/O 3 and SI/O 4
M16C/28 Group
14.2 SI/O3 and SI/O4
SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os.
Figure 14.2.1 shows the block diagram of SI/O3 and SI/O4, and Figure 14.2.2 shows the SI/O3 and SI/O4-
related registers.
Table 14.2.1 shows the specifications of SI/O3 and SI/O4.
Clock source select
f
2SIO
PCLK1=0
SMi1 to SMi0
00
1/2
Data bus
2
Main clock,
PLL clock,
or ring oscillator clock
f
1SIO
01
2
2
f
8SIO
32SIO
PCLK1=1
1/4
1/8
10
f
Synchronous
circuit
1/(n+1)
1/2
SiBRG register
SMi3
SMi4
SMi6
CLK
SMi6
polarity
reversing
circuit
SI/Oi
interrupt request
SI/O counter i
CLK
i
SMi2
SMi3
SMi5 LSB
MSB
SOUTi
SiTRR register
S
INi
8
Note: i = 3, 4.
n = A value set in the SiBRG register.
Figure 14.2.1. SI/O3 and SI/O4 Block Diagram
Rev.0.60 2004.02.01 page 199 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.2 SI/O 3 and SI/O 4
M16c/28 Group
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3C
S4C
Address
036216
036616
After reset
0100000
0100000
2
2
Bit
symbol
Description
Bit name
RW
RW
RW
RW
RW
b1 b0
SMi0 Internal synchronous
clock select bit
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Must not be set.
SMi1
SMi2
SMi3
SMi4
S
OUTi output disable bit
(Note 4)
0 : SOUTi output
1 : SOUTi output disable(high impedance)
0 : Input/output port
1 : SOUTi output, CLKi function
S I/Oi port select bit
0 : Transmit data is output at falling edge of
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input at
falling edge
CLK polarity select bit
RW
SMi5 Transfer direction select
bit
0 : LSB first
1 : MSB first
RW
RW
(Note 2)
(Note 3)
SMi6
Synchronous clock
select bit
0 : External clock
1 : Internal clock
SMi7
S
OUTi initial value
Effective when SMi3 = 0
0 : “L” output
RW
set bit
1 : “H” output
Note 1: Make sure register S4C is written to by the next instruction after setting the PRCR register's PRC2 bit to “1"
(write enable).
Note 2: Set the SMi3 bit to “1” (SOUTi output, CLKi function).
Note 3: Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
Note 4: Effective when SMi3 bit = 1.
SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)
Symbol
S3BRG
S4BRG
Address
036316
036716
After reset
??16
b7
b0
??16
Setting range
0016 to FF16
Description
RW
WO
Assuming that set value = n, BRGi divides the count
source by n + 1
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)
Symbol
S3TRR
S4TRR
Address
036016
036416
After reset
??16
b7
b0
??16
RW
RW
Description
Transmission/reception starts by writing transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: To receive data, set the corresponding port direction bit for SINi to “0” (input mode).
Figure 14.2.2. S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers
Rev.0.60 2004.02.01 page 200 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.2 SI/O 3 and SI/O 4
M16C/28 Group
Table 14.2.1. SI/O3 and SI/O4 Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• SiC (i=3, 4) register’s SMi6 bit = “1” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n=Setting value of SiBRG register
• SMi6 bit = “0” (external clock) : Input from CLKi pin (Note 1)
0016 to FF16.
Transmission/reception
start condition
• Before transmission/reception can start, the following requirements must be met
Write transmit data to the SiTRR register (Notes 2, 3)
• When SiC register's SMi4 bit = 0
Interrupt request
generation timing
The rising edge of the last transfer clock pulse (Note 4)
• When SMi4 = 1
The falling edge of the last transfer clock pulse (Note 4)
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
CLKi pin fucntion
SOUTi pin function
SINi pin function
Select function
• LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Function for setting an SOUTi initial value set function
When the SiC register's SMi6 bit = 0 (external clock), the SOUTi pin output level while
not tranmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
Note 1: To set the SiC register’s SMi6 bit to “0” (external clock), follow the procedure described below.
• If the SiC register’s SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is
high. The same applies when rewriting the SiC register’s SMi7 bit.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same
applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the
transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock automatically
stops.
Note 2: Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. There-
fore, do not write the next transmit data to the SiTRR register during transmission.
Note 3: When the SiC register’s SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period
after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with the
data hold time thereby reduced.
Note 4: When the SiC register’s SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit
= 0, or stops in the low state if the SMi4 bit = 1.
Rev.0.60 2004.02.01 page 201 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.2 SI/O 3 and SI/O 4
M16c/28 Group
14.2.1 SI/Oi Operation Timing
Figure 14.2.1.1 shows the SI/Oi operation timing
1.5 cycle (max)
(Note 3)
"H"
"L"
SI/Oi internal clock
CLKi output
"H"
"L"
"H"
"L"
Signal written to the
SiTRR register
(Note 2)
S
OUTi output
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
"H"
"L"
S
INi input
"1"
"0"
SiIC register
IR bit
i= 3, 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the
rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
Note 3: If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
Figure 14.2.1.1. SI/Oi Operation Timing
14.2.2 CLK Polarity Selection
The SiC register's SMi4 bit allows selection of the polarity of the transfer clock. Figure 14.2.2.1 shows
the polarity of the transfer clock.
(1) When SiC register's SMi4 bit = “0”
(Note 2)
CLK
i
D0
D
1
D
2
D
3
3
D
4
D
5
5
D
6
6
D
7
7
S
INi
D0
D
1
D
2
D
D4
D
D
D
S
OUTi
(2) When SiC register's SMi4 bit = “1”
(Note 3)
CLK
i
D
0
D1
D
2
D
3
D
4
D
5
D
6
D7
SINi
D
0
D1
D
2
D
3
D
4
D
5
D
6
D7
S
OUTi
i=3 and 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
pin if not transferring data.
Note 3: When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
pin if not transferring data.
Figure 14.2.2.1. Polarity of Transfer Clock
Rev.0.60 2004.02.01 page 202 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
14.2 SI/O 3 and SI/O 4
M16C/28 Group
14.2.3 Functions for Setting an SOUTi Initial Value
If the SiC register’s SMi6 bit = 0 (external clock), the SOUTi pin output can be fixed high or low when not
transferring. Figure 14.2.3.1 shows the timing chart for setting an SOUTi initial value and how to set it.
(Example) When “H” selected for SOUTi initial value (Note 1)
Setting of the initial value of SOUT
output and starting of transmission/
reception
i
Signal written to
SiTRR register
SMi7 bit
SMi3 bit
Set the SMi3 bit to “0”
(SOUTi pin functions as an I/O port)
Set the SMi7 bit to “1”
(SOUTi initial value = “H”)
D0
D0
S
OUTi (internal)
Set the SMi3 bit to “1”
(SOUTi pin functions as SOUTi output)
Port output
S
OUTi pin output
“H” level is output
Initial value = “H” (Note 3)
from the SOUTi pin
(i = 3, 4)
Setting the SOUT
initial value to “H”
i
Port selection switching
(I/O port OUTi)
Write to the SiTRR register
S
(Note 2)
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi5=0 (LSB first) and SMi6=0 (external clock)
Note 2: SOUTi can only be initialized when input on the CLKi pin is in the high state if the SiC
register’s SMi4 bit = 0 (transmit data output at the falling edge of the transfer clock) or
in the low state if the SMi4 bit = 1 (transmit data output at the rising edge of the
transfer clock).
Serial transmit/reception starts
Note 3: If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUT output disabled),
this output goes to the high-impedance state.
Figure 14.2.3.1. SOUTi’s Initial Value Setting
Rev.0.60 2004.02.01 page 203 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15. A-D Converter
The microcomputer contains one A-D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107 (AN0 to
____________
AN7), P00 to P07 (AN00 to AN07), and P10 to P13, P93, P95 to P97 (AN20 to AN27). Similarly, ADTRG input
shares the pin with P15. Therefore, when using these inputs, make sure the corresponding port direction
bits are set to “0” (= input mode). Note that P10 to P13, P93, P95 to P97 (AN20 to AN27) are available only in
the 80-pin package.
When not using the A-D converter, set the VCUT bit to “0” (= VREF unconnected), so that no current will flow
from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A-D conversion result is stored in the ADi register bits for ANi, AN0i, and AN2i pins (i = 0 to 7).
Table 15.1 shows the A-D converter performance. Figure 15.1 shows the A-D converter block diagram
and Figures 15.2 to 15.4 show the A-D converter associated with registers.
Table 15.1 A-D Converter Performance
Item
Performance
A-D Conversion Method
Successive approximation (capacitive coupling amplifier)
Analog Input Voltage (Note 1) 0V to AVCC (VCC)
Operating Clock fAD (Note 2)
fAD/divided-by-2 or fAD/divided-by-3 or fAD/divided-by-4 or fAD/divided-by-6
or fAD/divided-by-12 or fAD
8-bit or 10-bit (selectable)
Resolution
Integral Nonlinearity Error When AVCC = VREF = 5V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
- AN0 to AN7 input : ±3LSB
- AN00 to AN07 input and AN20 to AN27 input : ±7LSB
When AVCC = VREF = 3.3V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution
- AN0 to AN7 input : ±5LSB
- AN00 to AN07 input and AN20 to AN27 input : ±7LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat
sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1
Operating Modes
Analog Input Pins
8 pins (AN0 to AN7) + 8 pins (AN00 to AN07) + 8 pins (AN20 to AN27)
8 pins (AN0 to AN7) + 4 pins (AN00 to AN03) + 1 pin (AN24)
• Without sample and hold function
(80pin-ver.)
(64pin-ver.)
Conversion Speed Per Pin
8-bit resolution: 49 fAD cycles
• With sample and hold function
8-bit resolution: 28 fAD cycles
,
10-bit resolution: 59 fAD cycles
,
10-bit resolution: 33 fAD cycles
Note 1: Not dependent on use of sample and hold function.
Note 2: Set the fAD frequency to 10 MHz or less.
Without sample-and-hold function, set the fAD frequency to 250kHZ or more.
With the sample and hold function, set the fAD frequency to 1MHZ or more.
Rev.0.60 2004.02.01 page 204 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D conversion rate
selection
CKS1=1
CKS1=0
CKS2=0
øAD
CKS0=1
CKS0=0
1/2
1/2
f
AD
1/3
CKS2=1
V
REF
VCUT=0
VCUT=1
Resistor ladder
AVSS
Successive conversion register
ADCON1 register
(address 03D716
)
ADCON0 register
(address 03D616
)
Addresses
(03C116 to 03C016
)
A-D register 0(16)
(03C316 to 03C216
)
)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
(03C516 to 03C416
Decoder
for A-D register
(03C716 to 03C616
(03C916 to 03C816
(03CB16 to 03CA16
(03CD16 to 03CC16
(03CF16 to 03CE16
)
)
A-D register 4(16)
A-D register 5(16)
A-D register 6(16)
)
)
)
A-D register 7(16)
Data bus high-order
V
ref
ADCON2 register
(address 03D416
Data bus low-order
)
Comparator 0
Decoder
for channel
selection
V
IN
CH2 to CH0
Port P10 group
AN
AN
=000
2
ADGSEL1 to ADGSEL0=00
2
0
=001
=010
2
2
1
AN
AN
AN
AN
AN
AN
2
3
Port P0 group
=011
=100
2
2
CH2 to CH0
=000
2
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
4
=101
=110
2
2
=001
=010
2
2
5
ADGSEL1 to ADGSEL0=10
2
6
=111
2
=011
=100
2
2
7
SSE = 1
=101
=110
2
2
CH2 to CH0=001
2
=111
2
ADGSEL1 to ADGSEL0=11
2
Port P1/Port P9
CH2 to CH0
group
(Note)
=000
2
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
=001
=010
2
2
=011
=100
2
2
ADGSEL1 to ADGSEL0=00
ADGSEL1 to ADGSEL0=10
2
2
=101
=110
2
2
=111
2
VIN1
Comparator 1
ADGSEL1 to ADGSEL0=11
2
Note: Port P1/Port P9 group is available for only 80-pin package.
Figure 15.1 A-D Converter Block Diagram
Rev.0.60 2004.02.01 page 205 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D control register 0 (Note)
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Bit name
Function
RW
RW
CH0
Analog Input Pin Select
Bit
Function varies with each operation mode
CH1
RW
RW
RW
CH2
MD0
b4 b3
A-D Operation Mode
Select Bit 0
0 0 : One-shot mode or Delayed trigger mode 0,1
0 1 : Repeat mode
1 0 : Single sweep mode or
Simultaneous sample sweep mode
1 1 : Repeat sweep mode 0 or Repeat sweep
mode 1
MD1
RW
RW
Trigger Select Bit
0 : Software trigger
1 : Hardware trigger
TRG
A-D Conversion Start Flag
0 : A-D conversion disabled
1 : A-D conversion started
ADST
RW
RW
Frequency Select Bit 0
See Table 15.2 A-D Conversion
Frequency Select
CKS0
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
Bit symbol
Bit name
Function
RW
RW
A-D Sweep Pin Select Bit
Function varies with each operation mode
SCAN0
SCAN1
RW
RW
0 : Other than repeat sweep mode 1
1 : Repeat sweep mode 1
A-D Operation Mode
Select Bit 1
MD2
8/10-Bit Mode Select Bit
Frequency Select Bit 1
0 : 8-bit mode
1 : 10-bit mode
BITS
RW
RW
RW
See Table 15.2 A-D Conversion
Frequency Select
CKS1
VREF Connect Bit
(Note 2)
0 : VREF not connected
1 : VREF connected
VCUT
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before
startingA-D conversion.
A-D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
Bit symbol
SMP
Bit name
Function
RW
0 : Without sample and hold
1 : With sample and hold
A-D Conversion Method
Select Bit
RW
b2 b1
A-D Input Group Select Bit
ADGSEL0
ADGSEL1
0 0 : Select port P10 group (ANi)
RW
RW
RW
RW
0 1 : Do not set
1 0 : Select port P0 group (AN0i)
1 1 : Select port P1/P9 group (AN2i)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
See Table 15.2 A-D Conversion
Frequency Select
CKS2
Trigger Select Bit
Function varies with each operation
mode
RW
TRG1
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Figure 15.2 ADCON0 to ADCON2 Registers
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D trigger control register (Note 1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADTRGCON
Address
03D216
After reset
0016
Bit symbol
Bit name
Function
RW
RW
0 : Other than simultaneous sample sweep
mode or delayed trigger mode 0,1
1 : Simultaneous sample sweep mode or
delayed trigger mode 0,1
A-D Operation Mode
Select Bit 2
SSE
0 : Other than delayed trigger mode 0,1
1 : Delayed trigger mode 0,1
A-D Operation Mode
Select Bit 3
RW
DTE
Function varies with each operation mode
AN0 Trigger Select Bit
AN1 Trigger Select Bit
RW
RW
HPTRG0
HPTRG1
Function varies with each operation mode
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
Note 1: If the ADTRGCON register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: Set “0016” in this register in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat
sweep mode 1.
Figure 15.3 ADTRGCON Register
Table 15.2 A-D Conversion Frequency Select
CKS2 CKS1 CKS0
ØAD
0
0
0
Divided-by-4 of fAD
Divided-by-2 of fAD
0
0
0
1
1
0
fAD
0
1
1
0
1
0
Divided-by-12 of fAD
Divided-by-6 of fAD
1
1
1
0
1
1
1
0
1
Divided-by-3 of fAD
Note: Set the ØAD frequency to 10 MHz or less. The selected ØAD frequency is determined by a combination of
the CKS0 bit in the ADCON0 register, CKS1 bit in the ADCON1 register and the CKS2 bit in the ADCON2
register.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D conversion status register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADSTAT0
Address
03D316
After reset
0016
Bit symbol
ADERR0
Bit name
Function
RW
RW
AN1 Trigger Status Flag
0 : Without AN1 trigger during
AN0 conversion
1 : With AN1 trigger during
AN0 conversion
Conversion Termination
Flag
ADERR1
0 : Conversion not terminated
1 : Conversion terminated by
Timer B0 underflow
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b2)
0 : Sweep not in progress
1 : Sweep in progress
Delayed Trigger Sweep
Status Flag
ADTCSF
RO
0 : AN0 conversion not in progress
1 : AN0 conversion in progress
AN0 Conversion Status
Flag
ADSTT0
ADSTT1
RO
RO
RW
RW
AN1 Conversion Status
Flag
0 : AN1 conversion not in progress
1 : AN1 conversion in progress
AN0 Conversion
Completion Status Flag
0 : AN0 conversion not completed
1 : AN0 conversion completed
ADSTRT0
ADSTRT1
AN1 Conversion
Completion Status Flag
0 : AN1 conversion not completed
1 : AN1 conversion completed
Note 1: ADSTAT0 register is valid only when the DTE bit in the ADTRGCON register is set to “1”.
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Address
After reset
A-D Register i (i=0 to 7)
03C116 to 03C016 Indeterminate
03C316 to 03C216 Indeterminate
03C516 to 03C416 Indeterminate
03C716 to 03C616 Indeterminate
03C916 to 03C816 Indeterminate
03CB16 to 03CA16 Indeterminate
03CD16 to 03CC16 Indeterminate
03CF16 to 03CE16 Indeterminate
(b15)
b7
(b8)
b0 b7
b0
Function
RW
When the BITS bit in the ADCON1
register is “1” (10-bit mode)
When the BITS bit in the ADCON1
register is “0” (8-bit mode)
Eight low-order bits of
A-D conversion result
A-D conversion result
RO
RO
Two high-order bits of
A-D conversion result
When read, its content is
indeterminate
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Figure 15.4 ADSTAT0 Register and AD0 to AD7 Registers
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
(Note 1)
Timer B2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2SC
Address
039E16
After reset
X0000000
2
RW
RW
Bit symbol
PWCOM
Bit name
Function
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 Reload Timing
(Note 2)
Switch Bit
Three-Phase Output Port 0 : Three-phase output forcible cutoff
IVPCR1
SD Control Bit 1
(Note 3, 4, 7)
by SD pin input (high impedance)
disabled
RW
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
Timer B0 Operation Mode 0 : Other than A-D trigger mode
Select Bit 1 : A-D trigger mode
TB0EN
TB1EN
RW
RW
RW
(Note 5)
Timer B1 Operation Mode 0 : Other than A-D trigger mode
Select Bit
1 : A-D trigger mode
(Note 5)
(Note 6)
TB2SEL Trigger Select Bit
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
Reserved bits
(b6-b5)
Must set to "0"
RW
Nothing is assigned. When write, set to 0 .
When read, its content is 0 .
(b7)
Note 1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
Note 2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set
this bit to "0" (timer B2 underflow).
Note 3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5
bit to "0" (= input mode).
Note 4. Related pins are U(P8
0), U(P81), V(P72), V(P73), W(P74), W(P75). After forcible cutoff, input "H" to the P85/NMI/SD pin.
Set the IVPCR1 bit to "0", and this forcible cutoff will be reset. If L is input to the P85/NMI/SD pin, a three-phase motor
control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is "0", the target pins changes to
programmable I/O port. When the IVPCR1 bit is "1", the target pins changes to high-impedance state regardless of
which functions of those pins are used.
Note 5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1" (A-D trigger mode).
Note 6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the INV02
bit to "1" (three-phase motor control timer function).
Note 7. Refer to "17.6 Digital Debounce function" for the SD input
Figure 15.5 TB2SC Register
Rev.0.60 2004.02.01 page 209 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15.1 Operation Modes
15.1.1 One-Shot Mode
In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table
15.1.1.1 shows the one-shot mode specifications. Figure 15.1.1.1 shows the operation example in one-
shot mode. Figure 15.1.1.2 shows the ADCON0 to ADCON2 registers in one-shot mode.
Table 15.1.1.1 One-shot Mode Specifications
Item
Specification
Function
The CH2 to CH0 bits in the ADCON0 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
a selected pin is once converted to a digital code
A-D Conversion Start
Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A-D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the
ADST bit to “1” (A-D conversion started)
A-D Conversion Stop
Condition
• A-D conversion completed (If a software trigger is selected, the ADST bit is
set to “0” (A-D conversion halted)).
• Set the ADST bit to “0”
Interrupt Request Generation Timing A-D conversion completed
Analog Input Pin
Select one pin from AN0 to AN7, AN00 to AN07, AN20 to AN27
Readout of A-D Conversion Result Readout one of the AD0 to AD7 registers that corresponds to the selected pin
•Example when selecting AN2 to an analog input pin (Ch2 to CH0="0102")
A-D conversion started
A-D pin input voltage
sampling
AN
0
1
2
3
4
5
6
7
A-D pin conversion
AN
AN
AN
AN
AN
AN
AN
A-D interrupt request generated
Figure 15.1.1.1 Operation Example in One-Shot Mode
Rev.0.60 2004.02.01 page 210 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
0
0
Bit symbol
Bit name
Function
RW
RW
b2 b1 b0
Analog Input Pin
Select Bit (Note 2, 3)
0 0 0 : Select AN
0
1
2
3
4
5
6
7
CH0
0 0 1 : Select AN
0 1 0 : Select AN
0 1 1 : Select AN
1 0 0 : Select AN
1 0 1 : Select AN
1 1 0 : Select AN
1 1 1 : Select AN
CH1
RW
RW
CH2
b4 b3
MD0
MD1
RW
RW
A-D Operation Mode
Select Bit 0 (Note 3)
0 0 : One-shot mode or delayed trigger mode
0,1
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Trigger Select Bit
TRG
RW
RW
RW
A-D Conversion Start
Flag
0 : A-D conversion disabled
1 : A-D conversion started
ADST
See Table 15.2 A-D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to
ADGSEL 0 bits in the ADCON2 register to select the desired pin.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using an another instruction.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
SCAN0
Bit name
Function
RW
RW
A-D Sweep Pin
Select Bit
Invalid in one-shot mode
SCAN1
MD2
RW
A-D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
RW
RW
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
REF Connect Bit (Note 2)
RW
RW
VCUT
1 : VREF connected
V
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A-D conversion.
A-D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A-D Conversion Method
Select Bit
b2 b1
ADGSEL0
ADGSEL1
A-D Input Group Select
Bit
RW
RW
RW
RW
0 0 : Select port P10 group (AN
0 1 : Do not set
1 0 : Select port P0 group (AN0i
i)
)
1 1 : Select port P1/P9 group (AN2i
)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
See Table 15.2 A-D Conversion
Frequency Select
CKS2
Trigger Select Bit 1
Set to "0" in one-shot mode
TRG1
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Figure 15.1.1.2 ADCON0 to ADCON2 Registers in One-Shot Mode
Rev.0.60 2004.02.01 page 211 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15.1.2 Repeat mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table
15.1.2.1 shows the repeat mode specifications. Figure 15.1.2.1 shows the operation example in repeat
mode. Figure 15.1.2.2 shows the ADCON0 to ADCON2 registers in repeat mode.
Table 15.1.2.1 Repeat Mode Specifications
Item
Specification
Function
The CH2 to CH0 bits in the ADCON0 register and the ADGSEL1 to ADGSEL0
bits in the ADCON2 register select pins. Analog voltage applied to a selected
pin is repeatedly converted to a digital code
A-D Conversion Start
Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A-D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A-D conversion started)
A-D Conversion Stop Condition Set the ADST bit to “0” (A-D conversion halted)
Interrupt Request Generation Timing None generated
Analog Input Pin
Select one pin from AN0 to AN7, AN00 to AN07 and AN20 to AN27
Readout of A-D Conversion Result Readout one of the AD0 to AD7 registers that corresponds to the selected pin
•Example when selecting AN
2
to an analog input pin (Ch2 to CH0="010
2")
A-D pin input voltage
sampling
A-D pin conversion
A-D conversion started
AN
0
1
2
3
4
5
6
7
AN
AN
AN
AN
AN
AN
AN
Figure 15.1.2.1 Operation Example in Repeat Mode
Rev.0.60 2004.02.01 page 212 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
0
1
Bit symbol
Bit name
Function
RW
RW
b2 b1 b0
Analog Input Pin
Select Bit (Note 2, 3)
0 0 0 : Select AN
0
1
2
3
4
5
6
7
CH0
0 0 1 : Select AN
0 1 0 : Select AN
0 1 1 : Select AN
1 0 0 : Select AN
1 0 1 : Select AN
1 1 0 : Select AN
1 1 1 : Select AN
CH1
RW
RW
CH2
b4 b3
MD0
MD1
RW
RW
A-D Operation Mode
Select Bit 0 (Note 3)
0 1 : Repeat mode
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Trigger Select Bit
TRG
RW
RW
RW
A-D Conversion Start
Flag
0 : A-D conversion disabled
1 : A-D conversion started
ADST
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register to select the desired pin.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using an another instruction.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
SCAN0
Bit name
Function
RW
RW
A-D Sweep Pin
Select Bit
Invalid in repeat mode
SCAN1
MD2
RW
A-D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
RW
RW
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
RW
RW
VCUT
VREF connect bit (Note 2) 1 : VREF connected
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A-D conversion.
A-D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A-D Conversion Method
Select Bit
b2 b1
ADGSEL0
ADGSEL1
A-D Input Group Select
Bit
RW
RW
RW
RW
0 0 : Select port P10 group (AN
0 1 : Do not set
1 0 : Select port P0 group (AN0i
i)
)
1 1 : Select port P1/P9 group (AN2i
)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
See Table 15.2 A-D Conversion
Frequency Select
CKS2
Trigger Select Bit 1
Set to "0" in repeat mode
TRG1
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Figure 15.1.2.2 ADCON0 to ADCON2 Registers in Repeat Mode
Rev.0.60 2004.02.01 page 213 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15.1.3 Single Sweep Mode
In single sweep mode, analog voltage is applied to the selected pins are converted one-by-one to a digital
code. Table 15.1.3.1 shows the single sweep mode specifications. Figure 15.1.3.1 shows the operation
example in single sweep mode. Figure 15.1.3.2 shows the ADCON0 to ADCON2 registers in single
sweep mode.
Table 15.1.3.1 Single Sweep Mode Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the selected pins is converted one-by-one to a digital code
A-D Conversion Start Condition • When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A-D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A-D conversion started)
A-D Conversion Stop Condition • A-D conversion completed(When selecting a software trigger, the ADST bit
is set to “0” (A-D conversion halted)).
• Set the ADST bit to “0”
Interrupt Request Generation Timing A-D conversion completed
Analog Input Pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),
)
AN0 to AN7 (8 pins) (Note 1
Readout of A-D Conversion Result Readout one of the AD0 to AD7 registers that corresponds to the selected pin
Note 1. AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7. However, all input pins
need to belong to the same group.
•Example when selecting AN0 to AN3 to A-D sweep pins (SCAN1 to SCAN0="012")
A-D pin input voltage
sampling
A-D pin conversion
A-D conversion started
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
A-D interrupt request generated
Figure 15.1.3.1 Operation Example in Single Sweep Mode
Rev.0.60 2004.02.01 page 214 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
1
0
2
Bit symbol
Bit name
Function
RW
RW
Analog Input Pin
Select Bit
Invalid in single sweep mode
CH0
CH1
RW
RW
CH2
b4 b3
MD0
MD1
RW
RW
A-D Operation Mode
Select Bit 0
1 0 : Single sweep mode or simultaneous
sample sweep mode
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Trigger Select Bit
TRG
RW
RW
RW
A-D Conversion Start
Flag
0 : A-D conversion disabled
1 : A-D conversion started
ADST
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
SCAN0
Bit name
Function
RW
RW
When selecting single sweep mode
A-D Sweep Pin
Select Bit (Note 2)
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
MD2
RW
A-D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
RW
RW
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
REF Connect Bit (Note 3)
RW
RW
VCUT
1 : VREF connected
V
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the
ADCON2 register to select the desired pin.
Note 3: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A-D conversion.
A-D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A-D Conversion Method
Select Bit
b2 b1
ADGSEL0
ADGSEL1
A-D Input Group
Select Bit
RW
RW
RW
RW
0 0 : Select port P10 group (AN
0 1 : Do not set
1 0 : Select port P0 group (AN0i
i)
)
1 1 : Select port P1/P9 group (AN2i
)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
Refer to Table 15.2 A-D Conversion
CKS2
Frequency Select
Trigger Select Bit 1
Set to "0" in single sweep mode
TRG1
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Figure 15.1.3.2 ADCON0 Register to ADCON2 Registers in Single Sweep Mode
Rev.0.60 2004.02.01 page 215 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15.1.4 Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltage is applied to the selected pins are repeatedly converted to a
digital code. Table 15.1.4.1 shows the repeat sweep mode 0 specifications. Figure 15.1.4.1 shows the
operation example in repeat sweep mode 0. Figure 15.1.4.2 shows the ADCON0 to ADCON2 registers in
repeat sweep mode 0.
Table 15.1.4.1 Repeat Sweep Mode 0 Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the selected pins is repeatedly converted to a digital code
A-D Conversion Start Condition • When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A-D conversion started)
• When the TRG bit in the ADCON0 register is “1” (Hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A-D conversion started)
A-D Conversion Stop Condition Set the ADST bit to “0” (A-D conversion halted)
Interrupt Request Generation Timing None generated
Analog Input Pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),
AN0 to AN7 (8 pins) (Note 1)
Readout of A-D Conversion Result Readout one of the AD0 to AD7 registers that corresponds to the selected pin
Note 1. AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7. However, all input pins
need to belong to the same group.
•Example when selecting AN0 to AN3 to A-D sweep pins (SCAN1 to SCAN0="012")
A-D pin input voltage
sampling
A-D conversion started
A-D pin conversion
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
Figure 15.1.4.1 Operation Example in Repeat Sweep Mode 0
Rev.0.60 2004.02.01 page 216 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
RW
RW
Analog Input Pin
Select Bit
Invalid in repeat sweep mode 0
CH0
CH1
CH2
RW
RW
b4 b3
RW
RW
A-D Operation Mode
Select Bit 0
MD0
MD1
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Trigger Select Bit
TR
G
RW
A-D Conversion Start
Flag
0 : A-D conversion disabled
1 : A-D conversion started
ADST
RW
RW
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
0
Bit symbol
Bit name
A-D Sweep Pin
Function
RW
RW
When selecting repeat sweep mode 0
SCAN0
b1 b0
Select Bit (Note 2)
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
MD2
RW
A-D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
RW
RW
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
REF Connect Bit (Note 3)
RW
RW
VCUT
1 : VREF connected
V
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN
the ADCON2 register to select the desired pin.
0 to AN7 . Use the ADGSEL1 to ADGSET0 bits in
Note 3: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A-D conversion.
A-D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A-D Conversion Method
Select Bit
b2 b1
ADGSEL0
ADGSEL1
A-D Input Group
Select Bit
RW
RW
RW
RW
0 0 : Select port P10 group (AN
0 1 : Do not set
1 0 : Select port P0 group (AN0i
i)
)
1 1 : Select port P1/P9 group (AN2i
)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
Refer to Table 15.2 A-D Conversion
CKS2
Frequency Select
Trigger Select Bit 1
Set to "0" in repeat sweep mode 0
TRG1
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Figure 15.1.4.2 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 0
Rev.0.60 2004.02.01 page 217 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15.1.5 Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltage is applied to the all selected pins are converted to a digital code,
with mainly used in the selected pins. Table 15.1.5.1 shows the repeat sweep mode 1 specifications.
Figure 15.1.5.1 shows the operation example in repeat sweep mode 1. Figure 15.1.5.2
ADCON0 to ADCON2 registers in repeat sweep mode 1.
shows the
Table 15.1.5.1 Repeat Sweep Mode 1 Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register mainly select pins. Analog voltage
applied to the all selected pins is repeatedly converted to a digital code
Example : When selecting AN0
Analog voltage is converted to a digital code in the following order
AN0
AN1
AN0
AN2
AN0
AN3, and so on.
A-D Conversion Start Condition • When the TRG bit in the ADCON0 register is “0” (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A-D conversion started)
• When the TRG bit in the ADCON0 register is “1” (hardware trigger)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A-D conversion started)
A-D Conversion Stop Condition Set the ADST bit to “0” (A-D conversion halted)
Interrupt Request Generation Timing None generated
Analog Input Pins Mainly Select from AN0 (1 pins), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to
Used in A-D Conversions AN3 (4 pins) (Note 1)
Readout of A-D Conversion Result Readout one of the AD0 to AD7 registers that corresponds to the selected pin
Note1. AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7. However, all input pins
need to belong to the same group.
•Example when selecting AN0 to A-D sweep pins (SCAN1 to SCAN0="002")
A-D pin input voltage
sampling
A-D pin conversion
A-D conversion started
AN
0
1
2
3
4
5
6
7
AN
AN
AN
AN
AN
AN
AN
Figure 15.1.5.1 Operation Example in Repeat Sweep Mode 1
Rev.0.60 2004.02.01 page 218 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
RW
RW
Analog Input Pin
Select Bit
Invalid in repeat sweep mode 1
CH0
CH1
CH2
RW
RW
b4 b3
RW
RW
A-D Operation Mode
Select Bit 0
MD0
MD1
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Trigger Select Bit
TRG
ADST
CKS0
RW
A-D Conversion Start
Flag
0 : A-D conversion disabled
1 : A-D conversion started
RW
RW
Refer to Table 15.2 A-D Conversion
Frequency Select
Frequency Select Bit 0
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
1
1
Bit symbol
Bit name
Function
RW
RW
When selecting repeat sweep mode 1
b1 b0
A-D Sweep Pin
Select Bit (Note2)
SCAN0
0 0 : AN0 (1 pin)
0 1 : AN0 to AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
SCAN1
MD2
RW
A-D Operation Mode
Select Bit 1
1 : Repeat sweep mode 1
RW
RW
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
RW
RW
VREF Connect Bit (Note 3)
VCUT
1 : VREF connected
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7 .
Use the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin.
Note 3: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before
starting A-D conversion.
A-D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
0
Bit symbol
SMP
Bit name
Function
RW
RW
0 : Without sample and hold
1 : With sample and hold
A-D Conversion Method
Select Bit
b2 b1
ADGSEL0
ADGSEL1
A-D Input Group
Select Bit
RW
RW
RW
RW
0 0 : Select port P10 group (ANi)
0 1 : Do not set
1 0 : Select port P0 group (AN0i)
1 1 : Select port P1/P9 group (AN2i)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS2
Trigger Select Bit 1
Set to "0" in repeat sweep mode 1
TRG1
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Figure 15.1.5.2 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 1
Rev.0.60 2004.02.01 page 219 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15.1.6 Simultaneous Sample Sweep Mode
In simultaneous sample sweep mode, analog voltage is applied to the selected pins are converted one-
by-one to a digital code. At this time, the input voltage of AN0 and AN1 are sampled simultaneously using
two circuits of sample and hold circuit. Table 15.1.6.1 shows the simultaneous sample sweep mode
specifications. Figure 15.1.6.1 shows the operation example in simultaneous sample sweep mode. Fig-
ure 15.1.6.2 shows ADCON0 to ADCON2 registers and Figure 15.1.6.3 shows ADTRGCON registers in
simultaneous sample sweep mode. Table 15.1.6.2 shows the trigger select bit setting in simultaneous
sample sweep mode. In simultaneous sample sweep mode, Timer B0 underflow can be selected as a
trigger by combining software trigger, ADTRG trigger, Timer B2 underflow, Timer B2 interrupt generation
frequency setting counter underflow or A-D trigger mode of Timer B.
Table 15.1.6.1 Simultaneous Sample Sweep Mode Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the selected pins is converted one-by-one to a digital code. At this time, the
input voltage of AN0 and AN1 are sampled simultaneously.
When the TRG bit in the ADCON0 register is "0" (software trigger)
Set the ADST bit in the ADCON0 register to “1” (A-D conversion started)
When the TRG bit in the ADCON0 register is "1" (hardware trigger)
The trigger is selected by TRG1 and HPTRG0 bits (See Table 15.1.6.2)
The ADTRG pin input changes state from “H” to “L” after setting the ADST bit
to “1” (A-D conversion started)
A-D Conversion Start Condition
Timer B0, B2 or Timer B2 interrupt generation frequency setting counter
underflow after setting the ADST bit to “1” (A-D conversion started)
A-D conversion completed (If selecting software trigger, the ADST bit is auto-
matically set to "0" ).
A-D Conversion Stop Condition
Set the ADST bit to "0" (A-D conversion halted)
Interrupt Generation Timing A-D conversion completed
Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins),AN0 to AN5 (6 pins), or
AN0 to AN7 (8 pins) (Note 1)
Readout of A-D conversion result Readout one of the AN0 to AN7 registers that corresponds to the selected pin
Note 1. AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN07. However, all input pins
need to belong to the same group.
•Example when selecting AN0 to AN3 to A-D pins for sweep (SCAN1 to SCAN0="012")
A-D pin input voltage
sampling
A-D pin conversion
A-D conversion started
AN
0
1
2
3
4
5
6
7
AN
AN
AN
AN
AN
AN
AN
A-D interrupt request generated
Figure 15.1.6.1 Operation Example in Simultaneous Sample Sweep Mode
Rev.0.60 2004.02.01 page 220 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX
1
0
2
Bit symbol
Bit name
Function
RW
RW
Analog Input Pin
Select Bit
Invalid in simultaneous sample sweep mode
CH0
CH1
CH2
RW
RW
b4 b3
RW
RW
A-D Operation Mode
Select Bit 0
MD0
MD1
1 0 : Single sweep mode or simultaneous
sample sweep mode
Refer to Table 15.1.6.2 Trigger Select Bit
Setting in Simultaneous Sample Sweep
Mode
Trigger Select Bit
TRG
ADST
CKS0
RW
A-D Conversion Start Fag 0 : A-D conversion disabled
1 : A-D conversion started
RW
RW
Refer to Table 15.2 A-D Conversion
Frequency Select
Frequency Select Bit 0
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
0
0
1
0
Bit symbol
Bit name
A-D Sweep Pin
Function
RW
RW
When selecting simultaneous sample sweep
mode
SCAN0
Select Bit
(Note2)
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
MD2
RW
A-D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
REF Connect Bit (Note 3)
Reserved Bit
VCUT
1 : VREF connected
V
RW
RW
Set to "0"
(b7-b6)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN
bits in the ADCON2 register to select the desired pin.
0 to AN7. Use the ADGSEL1 to ADGSET0
Note 3: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A-D conversion.
A-D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
1
Bit symbol
SMP
Bit name
Function
RW
RW
Set to “1” in simultaneous sample
A-D Conversion Method
Select Bit
sweep mode
b2 b1
ADGSEL0
ADGSEL1
A-D Input Group
Select Bit
RW
RW
RW
RW
0 0 : Select port P10 group (AN
0 1 : Do not set
1 0 : Select port P0 group (AN0i
i)
)
1 1 : Select port P1/P9 group (AN2i
)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
Refer to Table 15.2 A-D Conversion
CKS2
Frequency Select
Refer to Table 15.1.6.2 Trigger Select Bit
Setting in Simultaneous Sample Sweep
Mode
Trigger select bit 1
TRG1
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Figure 15.1.6.2 ADCON0 to ADCON2 Registers for Simultaneous Sample Sweep Mode
Rev.0.60 2004.02.01 page 221 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D trigger control register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADTRGCON
Address
03D216
After reset
0
0
1
0016
Bit symbol
SSE
Bit name
Function
RW
RW
1 : Simultaneous sample sweep mode
or delayed trigger mode 0, 1
A-D Operation Mode
Select Bit 2
A-D Operation Mode
Select Bit 3
0 : Any mode other than delayed trigger
mode 0,1
DTE
RW
RW
RW
Refer to Table 15.1.6.2 Trigger Select
Bit Setting in Simultaneous Sample
Sweep Mode
AN0 Trigger Select Bit
HPTRG0
Set to "0" in simultaneous sample
sweep mode
AN1 Trigger Select Bit
HPTRG1
(b7-b4)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Note 1: If ADTRGCON register is rewritten during A-D conversion, the conversion result will be indeterminate.
Figure 15.1.6.3 ADTRGCON Register in Simultaneous Sample Sweep Mode
TRIGGER
Software trigger
TRG
TRG1 HPTRG0
-
-
-
0
1
1
Timer B0 underflow (Note 1)
1
0
ADTRG
0
Timer B2 or Timer B2 interrupt generation frequency
setting counter underflow (Note 2)
1
0
1
Note 1. A count can be started for Timer B2, Timer B2 interrupt generation frequency
setting counter underflow or the INT5 pin falling edge as count start
conditions of Timer B0.
Note 2. Select Timer B2 or Timer B2 interrupt generation frequency setting counter
using the TB2SEL bit in the TB2SC register.
Table 15.1.6.2 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode
Rev.0.60 2004.02.01 page 222 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15.1.7 Delayed Trigger Mode 0
In delayed trigger mode 0, analog voltage applied to the selected pins are converted one-by-one to a
digital code. The delayed trigger mode 0 used in combination with A-D trigger mode of Timer B. The
Timer B0 underflow starts a single sweep conversion. After completing the AN0 pin conversion, the AN1
pin is not sampled and converted until the Timer B1 underflow is generated. When the Timer B1 under-
flow is generated, the single sweep conversion is restarted after the AN1 pin. Table 15.1.7.1 shows the
delayed trigger mode 0 specifications. Figure 15.1.7.1 shows the operation example in delayed trigger
mode 0. Figure 15.1.7.2 to Figure 15.1.7.3 show each flag operation in the ADSTAT0 register that corre-
sponds to the operation example. Figure 15.1.7.4 shows the ADCON0 to ADCON2 registers in delayed
trigger mode 0. Figure 15.1.7.5 shows the ADTRGCON register in delayed trigger mode 0 and Table
15.1.7.2 shows the trigger select bit setting in delayed trigger mode 0.
Table 15.1.7.1 Delayed Trigger Mode 0 Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits in
the ADCON2 register select pins. Analog voltage applied to the input voltage of the
selected pins are converted one-by-one to the digital code. At this time, Timer B0 under
flow generation starts AN0 pin conversion. Timer B1 underflow generation starts con-
version after the AN1 pin. (Note 1)
A-D Conversion Start
AN0 pin conversion start condition
•After Timer B0 underflow is generated if Timer B0 underflow is generated again
before Timer B1 underflow is generated , the conversion is not affected
•When Timer B0 underflow is generated during A-D conversion of pins after the AN1
pin, conversion is halted and the sweep is restarted from the AN0 pin
again
AN1 pin conversion start condition
•When Timer B1 underflow is generated during A-D conversion of the AN0 pin, the
input voltage of the AN1 pin is sampled. The AN1 conversion and the rest of the
sweep start when AN0 conversion is completed.
A-D Conversion Stop
Condition
•When single sweep conversion from the AN0 pin is completed
•Set the ADST bit to "0" (A-D conversion halted)(Note 2)
A-D conversion completed
Interrupt Request
Generation Timing
Analog Input Pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and
AN0 to AN7 (8 pins)(Note 3)
Readout of A-D Conversion Result Readout one of the AN0 to AN7 registers that corresponds to the selected pins
Note 1. Set the larger value than the value of the timer B0 register to the timer B1 register.
Note 2. Do not write “1” (A-D conversion started) to the ADST bit in delayed trigger mode 0. When write “1”,
unexpected interrupts may be generated.
Note 3. AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7. However, all input pins need to
belong to the same group.
Rev.0.60 2004.02.01 page 223 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
•Example when selecting AN0 to AN3 to A-D sweep pins (SCAN1 to SCAN0="012")
•Example 1: When Timer B1 underflow is generated during AN0 pin conversion
A-D pin input
voltage sampling
Timer B0 underflow
Timer B1 underflow
A-D pin conversion
AN
AN
AN
AN
0
1
2
3
•Example 2: When Timer B1 underflow is generated after AN0 pin conversion
Timer B0 underflow
Timer B1 underflow
AN
AN
AN
AN
0
1
2
3
•Example 3: When Timer B0 underflow is generated during A-D conversion of any pins except AN0 pin
Timer B0 underflow
Timer B0 underflow
(Abort othrt pins conversion)
Timer B1 underflow
Timer B1 under flow
AN
AN
AN
AN
0
1
2
3
•Example 4: When Timer B0 underflow is generated again before Timer B1 underflow is generated
after Timer B0 underflow generation
Timrt B0 underflow
Timer B0 underflow
(An interrupt does not affect A-D conversion)
Timer B1 underflow
AN
AN
AN
AN
0
1
2
3
Figure 15.1.7.1 Operation Example in Delayed Trigger Mode 0
Rev.0.60 2004.02.01 page 224 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
•Example when selecting AN
0
to AN
3
to A-D sweep pins (SCAN1 to SCAN0="01
2")
•Example 1: When Timer B1 underflow is generated during AN0 pin conversion
A-D pin input
voltage sampling
Timer B0 underflow
Timer B1 underflow
A-D pin conversion
AN
AN
AN
AN
0
1
2
3
"1"
"0"
ADST flag
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to “0" by program
"1"
"0"
IR bit in the ADIC "1"
register
"0"
Set to "0" by an interrupt request acknowledgement or a program
•Example 2: When Timer B1 underflow is generated after AN0 pin conversion
Timer B0 underflow
Timer B1 underflow
AN
AN
AN
AN
0
1
2
3
"1"
"0"
ADST flag
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
IR bit in the ADIC
register
"1"
"0"
Set to "0" by an interrupt request acknowledgement or a program
ADST flag: Bit 6 in the ADCON0 register
n
fl
n
n
h
Figure 15.1.7.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation
Example in Delayed Trigger Mode 0 (1)
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
•Example 3: When Timer B0 underflow is generated during A-D pin conversion of any pins except AN
0
pin
A-D pin input
Timer B0 underflow
Timer B0 underflow
(Abort othrt pins conversion )
voltage sampling
Timer B1 underflow
Timer B1 underflow
A-D pin conversion
AN
AN
AN
AN
0
1
2
3
"1"
"0"
ADST flag
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
IR bit in the ADIC"1"
register
"0"
Set to "0" by interrupt request acknowledgement or a program
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
•Example 4: After Timer B0 underflow is generated and when Timer B0 underflow is generated again
before Timer B1 underflow is genetaed
Timrt B0 underflow
Timer B0 underflow
(An interrupt does not affect A-D conversion)
A-D pin input
Timer B1 underflow
voltage sampling
A-D pin conversion
AN
AN
AN
AN
0
1
2
3
"1"
"0"
ADST flag
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
"1"
"0"
IR bit in the ADIC
register
Set to "0" by interrupt request acknowledgement or a program
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
Figure 15.1.7.3 Each Flag Operation in ADSTAT0 Register Associated with the Operation
Example in Delayed Trigger Mode 0 (2)
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
0
0 1 1 1
Bit symbol
Bit name
Function
RW
RW
b2 b1 b0
Analog Input Pin
Select Bit
CH0
1 1 1 : Set to "111b" in delayed trigger
mode 0
CH1
RW
RW
CH2
b4 b3
MD0
MD1
RW
RW
A-D Operation Mode
Select Bit 0
0 0 : One-shot mode or delayed trigger mode
0,1
Refer to Table 15.1.7.2 Trigger Select Bit
Setting in Delayed Trigger Mode 0
Trigger Select Bit
TRG
RW
RW
RW
A-D Conversion Start
Flag (Note 2)
0 : A-D conversion disabled
1 : A-D conversion started
ADST
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: Do not write “1” in delayed trigger mode 0. When write, set to "0".
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
0
0
1
0
Bit symbol
Bit name
Function
When selecting delayed trigger sweep mode 0
RW
RW
A-D Sweep Pin
Select Bit (Note2)
SCAN0
b1 b0
0 0: AN
0 1: AN
1 0: AN
1 1: AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
MD2
RW
A-D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
REF Connect Bit (Note 3)
Reserved Bit
VCUT
1 : VREF connected
V
RW
RW
Set to "0"
(b7-b6)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN
bits in the ADCON2 register to select the desired pin.
0 to AN7. Use the ADGSEL1 to ADGSEL0
Note 3: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A-D conversion.
A-D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
1
Bit symbol
SMP
Bit name
Function
RW
RW
A-D Conversion Method
Select Bit (Note 2)
1 : With sample and hold
b2 b1
ADGSEL0
ADGSEL1
A-D Input Group
Select Bit
RW
RW
RW
RW
0 0 : Select port P10 group (AN
0 1 : Do not set
1 0 : Select port P0 group (AN0i
i)
)
1 1 : Select port P1/P9 group (AN2i
)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
Refer to Table 15.2 A-D Conversion
CKS2
Frequency Select
Refer to Table 15.1.7.2 Trigger Select Bit
Setting in Delayed Trigger Mode 0
Trigger Select Bit 1
TRG1
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: Set to “1” in delayed trigger mode 0.
Figure 15.1.7.4 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 0
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D trigger control register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADTRGCON
Address
03D216
After reset
1
0
1
0016
Bit symbol
SSE
Bit name
Function
RW
RW
Simultaneous sample sweep mode or
delayed trigger mode 0,1
A-D Operation Mode
Select Bit 2
A-D Operation Mode
Select Bit 3
Delayed trigger mode 0, 1
DTE
RW
RW
RW
Refer to Table 15.1.7.2 Trigger Select
Bit Setting in Delayed Trigger Mode 0
AN0 Trigger Select Bit
HPTRG0
HPTRG1
AN1 Trigger Select Bit
Refer to Table 15.1.7.2 Trigger Select
Bit Setting in Delayed Trigger Mode 0
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
Note 1: If ADTRGCON reigster is rewritten during A-D conversion, the conversion result will be indeterminate.
Figure 15.1.7.5 ADTRGCON Register in Delayed Trigger Mode 0
Table 15.1.7.2 Trigger Select Bit Setting in Delayed Trigger Mode 0
Trigger
HPTRG1
1
TRG
0
TRG1
0
HPTRG0
1
Timer B0, B1 underflow
Rev.0.60 2004.02.01 page 228 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15.1.8 Delayed Trigger Mode 1
In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a
digital code. When the input of the ADTRG pin (falling edge) changes state from “H” to “L”, a single sweep
conversion is started. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted
until the second ADTRG pin falling edge is generated. When the second ADTRG falling edge is generated,
The single sweep conversion of the pins after the AN1 pin is restarted. Table 15.1.8.1 shows the delayed
trigger mode 1 specifications. Figure 15.1.8.1 shows the operation example of delayed trigger mode 1.
Figure 15.1.8.2 to Figure 15.1.8.3 show each flag operation in the ADSTAT0 register that corresponds to
the operation example. Figure 15.1.8.4 shows the ADCON0 to ADCON2 registers in delayed trigger
mode 1. Figure 15.1.8.5 shows the ADTRGCON register in delayed trigger mode 1 and Table 15.1.8.2
shows the trigger select bit setting in delayed trigger mode 1.
Table 15.1.8.1 Delayed Trigger Mode 1 Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits
in the ADCON2 register select pins. Analog voltages applied to the selected pins are
converted one-by-one to a digital code. At this time, the ADTRG pin
falling edge starts AN0 pin conversion and the second ADTRG pin falling edge starts
conversion of the pins after AN1 pin
A-D Conversion Start
Condition
AN0 pin conversion start condition
The ADTRG pin input changes state from “H” to “L” (falling edge)(Note 1)
AN1 pin conversion start condition (Note 2)
The ADTRG pin input changes state from “H” to “L” (falling edge)
•When the second ADTRG pin falling edge is generated during A-D conversion of
the AN0 pin, input voltage of AN1 pin is sampled or after at the time of ADTRG
falling edge. The conversion of AN1 and the rest of the sweep starts when AN0
conversion is completed.
•When the ADTRG pin falling edge is generated again during single sweep conver
sion of pins after the AN1 pin, the conversion is not affected
A-D Conversion Stop
Condition
•A-D conversion completed
•Set the ADST bit to "0" (A-D conversion halted)(Note 3)
Interrupt Request
Generation Timing
Analog Input Pin
Single sweep conversion completed
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and
AN0 to AN7 (8 pins)(Note 4)
Readout of A-D Conversion Result Readout one of the AN0 to AN7 registers that corresponds to the selected pins
___________
Note 1. When a third ADTRG pin falling edge is generated again during A-D conversion, its trigger is ignored.
___________
Note 2. The ADTRG pin falling edge is detected synchronized with the operation clock φAD. Therefore, when the
___________
___________
ADTRG pin falling edge is generated in shorter periods than φAD, the second ADTRG pin falling edge may not
___________
be detected. Do not generate the ADTRG pin falling edge in shorter periods than φAD.
Note 3. Do not write “1” (A-D conversion started) to the ADST bit in delayed trigger mode 1. When write “1”,unexpected
interrupts may be generated.
Note 4. AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7. However, all input pins need to
belong to the same group.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
•Example when selecting AN0 to AN3 to A-D sweep pins (SCAN1 to SCAN0="012")
•Example 1: When ADTRG pin falling edge is generated during AN0 pin conversion
A-D pin input
voltage sampling
A-D pin conversion
ADTRG pin input
AN
0
1
2
3
AN
AN
AN
•Example 2: When ADTRG pin falling edge is generated again after AN0 pin conversion
ADTRG pin input
AN
0
1
2
3
AN
AN
AN
•Example 3: When ADTRG pin falling edge is generated more than two times after AN0 pin conversion
ADTRG pin input
(valid after single sweep conversion)
AN
0
1
2
3
(invalid)
AN
AN
AN
Figure 15.1.8.1 Operation Example in Delayed Trigger Mode1
Rev.0.60 2004.02.01 page 230 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
•Example when selecting AN0 to AN3 to A-D sweep pins (SCAN1 to SCAN0="012")
•Example 1: When ADTRG pin falling edge is generated during AN0 pin conversion
A-D pin input
voltage sampling
A-D pin conversion
ADTRG pin input
AN
0
1
2
3
AN
AN
AN
"1"
"0"
ADST flag
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
IR bit in the ADIC"1"
register
"0"
Set to "0" by interrupt request acknowledgement or a program
•Example 2: When ADTRG pin falling edge is generated again after AN0 pin conversion
ADTRG pin input
AN
0
1
2
3
AN
AN
AN
"1"
"0"
ADST flag
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
IR bit in the ADIC
register
"1"
"0"
Set to "0" by interrupt request acknowledgment or a program
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
Figure 15.1.8.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example
in Delayed Trigger Mode 1 (1)
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
•Example 3: When ADTRG input falling edge is generated more than two times after AN0 pin conversion
A-D pin input
voltage sampling
A-D pin conversion
ADTRG pin input
(valid after single sweep conversion)
AN0
AN1
AN2
AN3
(invalid)
"1"
"0"
ADST flag
Do not set to "1" by program
"1"
"0"
ADERR0 flag
ADERR1 flag
ADTCSF flag
ADSTT0 flag
ADSTT1 flag
ADSTRT0 flag
ADSTRT1 flag
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
Set to "0" by program
"1"
"0"
IR bit in the ADIC
register
"1"
"0"
Set to "0" when interrupt request acknowledgement or a program
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
Figure 15.1.8.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example
in Delayed Trigger Mode 1 (2)
Rev.0.60 2004.02.01 page 232 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
0
0 1 1 1
Bit symbol
Bit name
Function
RW
RW
b2 b1 b0
Analog Input Pin
Select Bit
CH0
1 1 1 : Set to "111b" in delayed trigger
mode 1
CH1
RW
RW
CH2
b4 b3
MD0
MD1
RW
RW
A-D Operation Mode
Select Bit 0
0 0 : One-shot mode or delayed trigger mode
0,1
Trigger Select Bit
Refer to Table 15.1.8.2 Trigger Select Bit
Setting in Delayed Trigger Mode 1
TR
G
ADST
RW
RW
RW
A-D Conversion Start
0 : A-D conversion disabled
1 : A-D conversion started
Flag
(Note 2)
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS0
Frequency Select Bit 0
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: Do not write “1” in delayed trigger mode 1. When write, set to "0".
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
After reset
0016
0
0
1
0
Bit symbol
Bit name
A-D Sweep Pin
Function
When selecting delayed trigger mode 1
RW
RW
SCAN0
b1 b0
Select Bit
(Note 2)
0 0: AN
0 1: AN
1 0: AN
1 1: AN
0
0
0
0
to AN
to AN
to AN
to AN
1
3
5
7
(2 pins)
(4 pins)
(6 pins)
(8 pins)
SCAN1
MD2
RW
A-D Operation Mode
Select Bit 1
0 : Any mode other than repeat sweep
mode 1
RW
RW
RW
8/10-Bit Mode Select Bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Refer to Table 15.2 A-D Conversion
Frequency Select
CKS1
Frequency Select Bit 1
REF Connect Bit (Note 3)
Reserved Bit
VCUT
1 : VREF connected
V
RW
RW
Set to "0"
(b7-b6)
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSET0
bits in the ADCON2 register to select the desired pin.
Note 3: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting
A-D conversion.
A-D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
After reset
0016
0
1
Bit symbol
SMP
Bit name
Function
RW
RW
A-D Conversion Method
Select Bit (Note 2)
1 : With sample and hold
b2 b1
ADGSEL0
ADGSEL1
A-D Input Group
Select Bit
RW
RW
RW
RW
0 0 : Select port P10 group (AN
0 1 : Do not set
1 0 : Select port P0 group (AN0i
i)
)
1 1 : Select port P1/P9 group (AN2i
)
Reserved Bit
Set to “0”
(b3)
Frequency Select Bit 2
Refer to Table 15.2 A-D Conversion
CKS2
Frequency Select
Trigger Select Bit 1
Refer to Table 15.1.8.2 Trigger Select Bit
Setting in Delayed Trigger Mode 1
TRG1
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: Set to “1” in delayed trigger mode 1.
Figure 15.1.8.4 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 1
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
A-D trigger control register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADTRGCON
Address
03D2h
After reset
00h
1
0
1
Bit symbol
SSE
Bit name
Function
RW
Simultaneous sample sweep mode or
delayed trigger mode 0,1
A-D Operation Mode
Select Bit 2
RW
A-D Operation Mode
Select Bit 3
Delayed trigger mode 0, 1
DTE
RW
RW
RW
Refer to Table 15.1.8.2 Trigger Select
Bit Setting in Delayed Trigger Mode 1
AN0 Trigger Select Bit
HPTRG0
HPTRG1
Refer to Table 15.1.8.2 Trigger Select
Bit Setting in Delayed Trigger Mode 1
AN1 Trigger Select Bit
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b4)
Note 1: If ADTRGCON is rewritten during A-D conversion, the conversion result will be indeterminate.
Figure 15.1.8.5 ADTRGCON Register in Delayed Trigger Mode 1
Table 15.1.8.2 Trigger Select Bit Setting in Delayed Trigger Mode 1
Trigger
HPTRG1
0
TRG
0
TRG1
1
HPTRG0
0
ADTRG
Rev.0.60 2004.02.01 page 234 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15.2 Resolution Select Function
The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to “1” (10-bit
precision), the A-D conversion result is stored into bits 0 to 9 in the ADi register (i=0 to 7). When the BITS
bit is set to “0” (8-bit precision), the A-D conversion result is stored into bits 0 to 7 in the ADi register.
15.3 Sample and Hold
When the SMP bit in the ADCON 2 register is set to “1” (with the sample and hold function), A-D conver-
sion rate per pin increases to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. The
sample and hold function is available in one-shot mode, repeat mode, single sweep mode, repeat sweep
mode 0 and repeat sweep mode 1. In these modes, start A-D conversion after selecting whether the
sample and hold circuit is to be used or not.
15.4 Current Consumption Reducing Function
When the A-D converter is not used, the VCUT bit in the ADCON1 register isolates the resistor ladder of
the A-D converter from the reference voltage input pin (VREF). Power consumption is reduced by shutting
off any current flow into the resistor ladder from the VREF pin.
When using the A-D converter, set the VCUT bit to “1” (VREF connected) before setting the ADST bit in
the ADCON0 register to “1” (A-D conversion started). Do not set the ADST bit and VCUT bit to “1” simul-
taneously, nor set the VCUT bit to “0” (VREF unconnected) during A-D conversion.
15.5 Analog Input Pin and External Sensor Equivalent Circuit Example
Figure 15.5.1 shows an example of the analog input pin and external sensor equivalent circuit.
Microcomputer
Sensor equivalent
circuit
R0
R (7.8kΩ)
VIN
3
AD
Sampling time :
f
C (1.5pF)
VC
Figure 15.5.1 Analog Input Pin and External Sensor Equivalent Circuit
Rev.0.60 2004.02.01 page 235 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
15. A-D Converter
15.6 Precautions of Using A-D Converter
(1) Set the bit in the port direction register, which corresponds to the pin being used as the analog input,
to “0” (input mode) Set the bit in the port direction register, which corresponds to pin ADTRG, to “0”
(input mode) if the external trigger is used.
(2) When using a key input interrupt, do not use pins AN4 to AN7 as analog input pins (key input interrupt
request is generated when the A-D input voltage is “L”).
(3) Insert capacitors between pins AVCC, VREF, analog input pin (ANi (i=0 to 7), AN0i and AN2i) and AVSS
to prevent latch-ups and malfunctions due to noise, and to minimize conversion errors. The same
applies to pins VCC and VSS. Figure 15.6.1 shows the procedure of each pin.
(4) Incorrect values are stored in the ADi register (i=0 to 7) if the CPU reads the ADi register while the ADi
register is storing results from a completed A-D conversion. This occurs when a divided main clock or
a sub clock is selected as the CPU clock.
• In one-shot mode or single sweep mode, simultaneous sample sweep mode and delayed trigger
mode 0, 1 , read the corresponding ADi register after verifying that the A-D conversion has been
completed. (The completion of the A-D conversion can be determined by the IR bit in the ADIC
register).
• In repeat mode, repeat sweep mode 0 and repeat sweep mode 1, use an undivided main clock as
the CPU clock.
(5) Conversion results of the A-D converter are indeterminate, if the ADST bit in the ADCON0 register is
set to “0” (A-D conversion halted) and the conversion is forcibly terminated, by program during A-D
conversion. ADi registers not operating A-D conversion may also be indeterminate. If the ADST bit is
changed to “0” by program, during the A-D conversion, do not use any values obtained from the ADi
registers.
Microcomputer
AVCC
V
REF
C2
C1
C3
AVSS
V
CC
C4
AN
i
V
SS
AN
i
: AN
i(i=0 to 7), AN0i (i=0 to 7 for 80-pin version, and i=0 to 3 for 64-pin version)
AN2i (i=0 to 7 for 80-pin version, i=4 for 64-pin version)
NOTES
1. C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF (reference)
2. Use thick and shortest possible wiring to connect capacitors.
Figure 15.6.1 VCC, VSS, AVCC, AVSS, VREF and ANi Connections
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
16. Multi-master I2C bus Interface
2
2
The multi-master I C bus interface is a serial communication circuit based on Philips I C bus data transfer
format. 2 independent channels, with both arbitration lost detection and synchronous functions, are built in
2
for the multi-master serial communication. Figure 16.1 shows a block diagram of the multi-master I C bus
2
interface and Table 16.1 lists the multi-master I C bus interface functions.
2
2
2
2
The multi-master I C bus interface consists of the I C0 address register, the I C0 data shift register, the I C0
2
2
2
2
clock control register, the I C0 control register 1, I C0 control register 2, the I C0 status register, the I C0
start/stop condition control register and other control circuits.
2
Figure 16.2 to 16.8 show the registers associated with the multi-master I C bus.
2
Table 16.1 Multi-master I C bus interface functions
Item
Function
2
Based on Philips I C bus standard:
7-bit addressing format
Format
High-speed clock mode
Standard clock mode
2
Based on Philips I C bus standard:
Master transmit
Communication mode
SCL clock frequency
Master receive
Slave transmit
Slave receive
16.1kHz to 400kHz (at VIIC (Note 1)= 4MHz)
2
Note 1. VIIC=I C system clock
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
Figure 16.1 Block diagram of multi-master I C bus interface
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Preliminary specification
Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
I
Symbol
S0D0
Address
02E216
After reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
Bit Symbol
Bit Name
Reserved bit
Function
Set to “0”
Comparing with received
address data
RW
SAD0
Slave address
RW
RW
RW
SAD1
SAD2
SAD3
SAD4
RW
RW
SAD5
SAD6
RW
2
2
Figure 16.2 I C0 address register, I C0 address register 2
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
I C0 data shift register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S00
Address
02E016
When reset
XX16
RW
Function
Transmit/receive data are stored.
In the master transmit mode, the start condition/stop condition are triggered
by writing data to the register (refer to Section 16.9 START Condition
Generation Method and Section16.11 STOP Condition Generation
RW
(Note 1)
Method). The transmit/receive are started synchronized with SCL
.
Note 1: The write is only enabled when the bus interface enable bit (ES0 bit) is "1".
Because the register is used both for storing transmit/receive data, Write the
transmit data after the receive data is read out when transmitting.
2
I C0 clock control register
b6 b5 b4 b3 b2 b1 b0
Symbol
S20
Address
02E416
After reset
0016
RW
RW
Bit Symbol
Bit Name
CL frequency control bits
Function
S
See table 16.3 Set values
of I C0 clock control
register and SCL
frequency
CCR0
CCR1
CCR2
CCR3
CCR4
2
RW
RW
RW
RW
0: Standard clock mode
1: High-speed clock mode
FAST
MODE
S
CL mode specification bit
RW
RW
0: ACK is returned
1: ACK is not returned
ACK BIT
ACK
ACK bit
0: No ACK clock
1: With ACK clock
ACK clock bit
RW
2
2
Figure 16.3 I C0 data shift register, I C0 clock control register
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
I C0 control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S1D0
Address
02E316
After reset
0016
Bit Symbol
BC0
Bit Name
Bit counter
Function
RW
RW
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
: 8
: 7
: 6
: 5
: 4
: 3
: 2
: 1
(Number of transmit/receive
bits)
(Note 1)
BC1
BC2
RW
I2C bus interface
enable bit
0: Disabled
1: Enabled
ES0
ALS
RW
RW
0: Addressing format
1: Free data format
Data format select bit
Reserved bit
(b5)
Set to "0"
RW
I2C bus interface
reset bit
0: Reset release (auto)
1: Reset
IHR
RW
RW
0: I2C bus input
1: SMBUS input
I2C bus interface pin
input level select bit
TISS
Note 1: In the following status, the bit counter is cleared automatically
•Start condition/stop condition are detected
•Immediately after the completion of 1-byte data transmit
•Immediately after the completion of 1-byte data receive
2
Figure 16.4 I C0 control register 0
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
I C0 status register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S10
Address
02E816
After reset
0001000X
2
Bit Symbol
Bit Name
Last receive bit
Function
RW
LRB
0: Last bit = 0
1: Last bit = 1
RO
(Note 1)
0: No general call detected
1: General call detected
ADR0
AAS
AL
General call detecting flag
Slave address comparison flag
Arbitration lost detection flag
RO
(Note 1)
0: No address matched
1: Address matched
RO
(Note 1)
0: Not detected
1: Detected
RO
(Note 2)
I2C bus interface interrupt
request bit
0: Interrupt request issued
1: No interrupt request issued
PIN
BB
RO
(Note 2)
0: Bus free
1: Bus busy
Bus busy flag
RO
(Note 1)
Communication mode
specification bits
b7 b6
TRX
MST
RO
0
0
1
1
0: Slave receive mode
1: Slave transmit mode
0: Master receive mode
1: Master transmit mode
(Note 3)
RO
(Note 3)
Note 1: This bit is read only if it is used for the status check.
To write to this bit, refer to Sections 16.9 START Condition Generation Method and
16.11 STOP Condition Generation Method.
Note 2: This bit is read only, When write, set to “0”.
Note 3: To write to these bits, refer to Sections 16.9 START Condition Generation Method and
16.11 STOP Condition Generation Method.
2
Figure 16.5 I C0 status register
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
I C0 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3D0
Address
02E616
When reset
00110000
2
Bit Symbol
Bit Name
Function
RW
RW
0: Disable the I2C bus interface
interrupt of STOP condition
detection
SIM
The interrupt enable bit for
STOP condition detection
1: Enable the I2C bus interface
interrupt of STOP condition
detection
WIT
The interrupt enable bit for 0: Disable the I2C bus interface
data receive completion
interrupt of data receive
completion
1: Enable the I2C bus interface
interrupt of data receive
completion
RW
When setting NACK
(ACK bit = 0), write "0"
S
bit
DAi/Port function switch
0: SDA I/O pin (enable ES0 = 1)
1: Port output pin (enable ES0 = 1)
PED
PEC
RW
RW
S
bit
CLi/Port function switch
0: SCL I/O pin (enable ES0 = 1)
1: Port output pin (enable ES0 = 1)
The logic value monitor
bit of SDA output
0: SDA output logic value = 0
1: SDA output logic value = 1
SDAM
SCLM
ICK0
RO
RO
RW
The logic value monitor
bit of SCL output
0: SCL output logic value = 0
1: SCL output logic value = 1
b7 b6
0 0 : VIIC
0 1 : VIIC =1/4f
1 0 :
1 1 :
I2C system clock
selection bits,
if ICK4 to ICK2 bits in the
S4D0 register is "0002"
=1/2 f
1
1
1
✼f✼1=f(XIN)
=1/8f
IIC
Reserved
V
RW
ICK1
2
Figure 16.6 I C0 control register 1
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
I C0 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S4D0
Address
02E716
When reset
0016
Bit Symbol
Bit Name
Function
0 : Disabled
RW
RW
Time out detection function
enable bit
TOE
1 : Enabled
0 : Not detected
1 : Detected
TOF
RO
Time out detection flag
TOSEL
Time out detection time
select bit
0 : Long time
1 : Short time
RW
b5 b4 b3
I2C system clock select
bits
RW
RW
ICK2
ICK3
0
0
0
V
IIC set by ICK1 and ICK0
bits in S3D0 register
0
0
0
1
0
1
1
0
1
0
1
0
V
V
V
V
IIC = 1/2.5 f1
IIC = 1/3 f1
IIC = 1/5 f1
IIC = 1/6 f1
RW
RW
ICK4
(b6)
Reserved bit
Set to "0"
0 : No I2C bus interface interrupt
request
STOP condition detection
interrupt request bit
SCPIN
RW
1 : I2C bus interface interrupt
request
2
Figure 16.7 I C0 control register 2
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
I
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S2D0
Address
02E516
When reset
00011010
2
Bit Symbol
Bit Name
Function
RW
RW
START/STOP condition setting Setting for detection condition
bits(Note 1)
SSC0
of START/STOP condition.
See Table 16.2
SSC1
SSC2
SSC3
SSC4
Recommended setting value
(SSC4 - SSC0) start/stop
condition at each oscillation
frequency.
RW
RW
RW
RW
0: Active in falling edge
1: Active in rising edge
S
CL/SDA interrupt pin polarity
RW
RW
RW
SIP
SIS
select bit
S
bit
CL/SDA interrupt pin select
0: SDA enabled
1: SCL enabled
0: Setup/hold time short mode
1: Setup/hold time long mode
STSP
SEL
START/STOP condition
generation select bit
Note 1: Disable the setting of "00000
2" and odd values.
2
Figure 16.8 I C0 start/stop condition control register
Table 16.2 Recommended setting value (SSC4 - SSC0) start/stop condition at each oscillation frequency
2
Oscillation
I C Bus system I2C Bus system SSC4-SSC0
SCL release
time(cycle)
6.2 µs (31)
6.75 µs(27)
6.25 µs(25)
5.0 µs (5)
6.5 µs (13)
5.5 µs (11)
5.0 µs (5)
Setup time
(cycle)
Hold time
(cycle)
f1 (MHz)
clock select
1 / 2f1
clock(MHz)
10
8
5
4
XXX11110
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
3.2 µs (16) 3.0 µs (15)
3.5 µs (14) 3.25 µs(13)
3.25 µs (13) 3.0 µs (12)
1 / 2f1
8
4
1 / 8f1
1 / 2f1
1
2
3.0 µs (3)
3.5 µs (7)
3.0 µs (6)
3.0 µs (3)
2.0 µs (2)
3.0 µs (6)
2.5 µs (5)
2.0 µs (2)
2
1 / 2f1
1
Note: Do not set odd values or “000002” to START/STOP condition setting bits(SSC4 to SSC0)
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
16.1 I C0 Data Shift Register (S00 register)
2
The I C0 data shift register (address 02E016) is the 8-bit shift register to store the receive data and the
write transmit data. When the transmit data is written into this register, it is transferred to the outside from
bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register is
shifted by one bit to the left. When the data is received, it is input to this register from the bit 0 in synchro-
nization with the SCL clock, and each time the one-bit data is input, the data of this register is shifted by one
2
bit to the left. Figure 16.9 shows the timing which stores the receive data to this register. The I C0 data shift
2
register is in a write enable status only when the I C bus interface enable bit (ES0 bit : bit 3 of address
2
2
02E316) of the I C0 control register 0 is “1”. The bit counter is reset by a write instruction to the I C0 data
2
shift register. When both the ES0 bit and the MST bit in the I C0 status register (address 02E816) are “1”,
2
2
the SCL is output by a write instruction to the I C0 data shift register. Reading data from the I C0 data shift
register is always enabled regardless of the ES0 bit value.
S
CL
DA
S
tdfil
t
dfil : Noise elimination circuit delay time
1 to 2 VIIC cycle
Internal SCL
Internal SDA
Shift clock
t
dsf : Shift clock delay time
1 VIIC cycle
tdfil
tdsft
Storing data at shift clock rising edge.
2
Figure 16.9 The timing of receiving data stored to I C0 data shift register
2
16.2 I C0 Address Register (S0D0 register)
This register consists of 7 bits of SAD6 to SAD0. At the addressing format which detects the slave
address automatically, the contents of SAD6 to SAD0 are compared with the address data to be
received.
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Specifications in this manual are tentative and subject to change.
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
16.3 I C0 Clock Control Register (S20 register)
2
The I C0 clock control register (address 02E416) is used to set theACK control, SCL mode and the SCL
frequency.
16.3.1 Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
2
These bits control the SCL frequency. See Table 16.3 Set values of I C0 clock control register and
SCL frequency.
16.3.2 Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies SCL mode. When this bit is set to “0”, Standard clock mode is selected. When the bit is
2
set to “1” , high-speed clock mode is selected. When connecting to the bus with high-speed mode I C bus
2
standard (maximum 400 kbits/s), set 4 MHz or more to the I C system clock(VIIC).
16.3.3 Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock(Note 1) is generated. When this bit is set to “0”, ACK return
mode is selected and the SDA goes to “L” at the ACK clock generation. When the bit is set to “1”, ACK non-
return mode is selected. The SDA is held in the “H” status at the ACK clock generation. However,
when the address data is received at the ACK BIT=0 and the slave address matches with the address data,
the SDA is automatically set to “L” (ACK is returned). If the slave address does not match with the address
data, the SDA is automatically set to “H” (ACK is not returned).
Note 1. ACK clock: Clock for acknowledgment
16.3.4 Bit 7: ACK clock bit (ACK)
This bit specifies mode of acknowledgment for responses to transfer data. When this bit is set to “0”, no
ACK clock mode is selected. In this case, the ACK clock is not generated after the data transmit. When
the bit is set to “1”, ACK clock mode is selected and the master generates an ACK clock at the completion
of each 1-byte data transfer. The device for transmitting the address data and the control data releases the
SDA at the ACK clock generation (set the SDA to “H”) and receives the ACK bit generated by the data receive
device.
2
Note . Do not rewrite the data into the I C0 clock control register other than the ACK bit (ACKBIT) during
2
the transfer. If data is written during the transfer, the I C Bus clock circuit is reset and the data can
not be transferred normally.
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
Table 16.3 Set values of I C0 clock control register and SCL frequency
Setting value of CCR4 to CCR0
SCL frequency (at VIIC=4MHz, unit : kHz) (Note 1)
CCR4 CCR3 CCR2 CCR1 CCR0
Standard clock mode
Setting disabled
Setting disabled
Setting disabled
- (Note 2)
High-speed clock mode
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Setting disabled
Setting disabled
Setting disabled
333
- (Note 2)
250
100
400 (Note 3)
166
83.3
500 / CCR value
(Note 3)
1000 / CCR value
(Note 3)
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
17.2
34.5
16.6
33.3
16.1
32.3
Note 1: The duty of the SCL clock output is 50 %. The duty becomes 35 to 45 % only when high-speed
clock mode is selected and the CCR value = 5 (400 kHz, at VIIC = 4 MHz). “H” duration of
2
the clock fluctuates from –4 to +2 I C system clock cycles in standard clock mode, and fluctu-
2
ates from –2 to +2 I C system clock cycles in high-speed clock mode. In the case of negative
fluctuation, the frequency does not increase because the “L” is extended instead of “H” reduc
tion. These are the values when the SCL clock synchronization by the synchronous function is
not performed. The CCR value is the decimal notation value of the SCL frequency control bits
CCR4 to CCR0.
Note 2: Each value of the SCL frequency exceeds the limit at VIIC = 4 MHz or more. When using
2
these setting values, use VIIC = 4 MHz or less. Refer to Figure 16.6 I C system clock
2
select bits (bit 6 and 7 of I C control register 1) on VIIC.
Note 3: The data formula of SCL frequency is described below:
VIIC/(8 × CCR value) Standard clock mode
VIIC/(4 × CCR value) High-speed clock mode (CCR value ≠ 5)
VIIC/(2 × CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as the CCR value regardless of the VIIC frequency.
Set 100 kHz (max.) in standard clock mode and 400 kHz (max.) in high-speed clock
mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0.
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
16.4 I C0 Control Register 0 (S1D0 register)
2
The I C0 control register 0 (address 02E316) controls the data communication format.
16.4.1 Bits 0 to 2: Bit counter (BC0–BC2)
2
These bits decide the number of bits for the next 1-byte data to be transmitted. The I C Bus interface
interrupt request signal is generated immediately after the number of count specified with these bits (the
ACK clock is added to the number of count when the ACK clock is selected by the ACK bit (bit 7 of address
02E416)) have been transferred, and the BC0 to BC2 are returned to “0002”.
Also when a START condition is detected, these bits become “0002” and the address data is always
transmitted and received in 8 bits.
2
16.4.2 Bit 3: I C interface enable bit (ES0)
2
This bit enables to use the multi-master I C bus interface. When this bit is set to “0”, the interface is
disabled and the SDA and the SCL become high-impedance. When the bit is set to “1”, the interface is
enabled.
When the ES0 bit is set to “0”, the following is performed.
2
1)Set MST = 1, TRX = 0, PIN = 1, BB = 0, AL = 0, AAS = 0, and ADR0 = 0, of the I C0 status
register (Address : 02E816)
2
2)Writing the data into the I C0 data shift register (Address : 02E016) is disabled.
2
3)The TOF bit in the I C0 control register (Address : 02E716) is cleared to “0”
2
4)The I C system clock (VIIC) is stopped and the internal counter, flags are initialized.
16.4.3 Bit 4: Data format select bit (ALS)
This bit decides if the recognition of the slave address is processed or not. When this bit is set to “0”, the
addressing format is selected and the address data is recognized. The transfer will be processed only
when a comparison is matched between the slave address and the address data or a general call is
2
received (Refer to Figure 16.5 I C0 status register: the item of bit 1, general call detection flag). When
this bit is set to “1”, the free data format is selected and the slave address is not recognized.
2
16.4.4 Bit 6: I C bus interface reset bit (IHR)
2
The bit is used to reset the I C bus interface circuit when the abnormal communication occurs.
2
When the ES0 bit is “1” (I C bus interface is enabled), writing “1” to the IHR bit resets H/W.
Flags are processed as follows:
2
1)Set MST = 0, TRX = 0, PIN = 1, BB = 0, AL = 0, AAS = 0, and ADR0 = 0, of I C0 status
register (Address : 02E816)
2
2)The TOF bit of the I C0 control register 2 (Address : 02E716) is cleared to “0”
3)The internal counter, flags are initialized.
After writing“1” to the IHR bit, the circuit reset processing is finished in Max. 2.5 VIIC cycles and the IHR
bit is automatically cleared to “0”. Figure 16.10 shows the reset timing.
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
16.4.5 Bit 7: I C bus interface pin input level select bit (TISS)
2
This bit selects the input level of the SCL and SDA pins of the multi-master I C bus interface. When this bit is
set to “1”, the P20 and P21 become the SMBus input level.
The signal of writing "1" to IHR bit
IHR bit
2
The reset signal to I C-BUS interface circuit
2.5 VIIC cycles
2
Figure 16.10 The timing of reset to the I C bus interface circuit
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Specifications in this manual are tentative and subject to change.
2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
16.5 I C0 Status Register (S10 register)
2
2
The I C0 status register (address 02E816) controls the I C bus interface status. Use the lower-6 bit as read
only if it is used for a status check.
16.5.1 Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for an ACK receive confirmation. If
the ACK is returned when the ACK clock is generated, the LRB bit is set to “0”. If the ACK is not returned,
this bit is set to “1”. Except in ACK mode, the last bit value of the received data is input. The bit is “0”
2
by executing a write instruction to the I C0 data shift register (address 02E016).
16.5.2 Bit 1: General call detection flag (ADR0)
When the ALS bit is “0”, this bit is set to “1” when a general call(Note 1),whose address data is all “0”, is
received in slave mode. By a general call of the master device, every slave device receives control data
after the general call. The ADR0 bit is set to “0” by detecting the STOP condition, START condition and
when the ES0 is “0”, or reset.
Note 1. General call: The master transmits the general call address “0016” to all slaves.
16.5.3 Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of the address data when the ALS bit in the S1D0 register is “0”.
In slave receive mode, this bit is set to “1” in one of the following conditions:
• 7 bit of the address data matches the slave address stored in the S0D0 register.
• A general call is received.
The AAS flag is set to “0” in one of the following conditions:
• When the ES0 bit is set to “1”, excute to write an instruction to the S00 register
• When the ES0 bit is set to “0”.
• Excute to reset by the IHR bit in the S1D0 register.
16.5.4 Bit 3: Arbitration lost detection flag (AL)(Note 1)
When devices other than the microcomputer set the SDA to “L” in master transmit mode, the arbitration is
judged to be lost and the AL bit is set to “1”. At the same time, the TRX bit is set to “0”. Immediately after the
bute transmist, whose arbitration is lost, is completed, the MST bit is set to “0”. The arbitration lost can be
detected only in master transmit mode. When the arbitration is lost during the slave address transmit, the
TRX bit is set to “0” and the receive mode is set. Consequently, it is possible to detect the match between
its own slave address and address data transmitted by another master devices. The bit becomes “0” if
2
writing to the I C0 data shift register (address 02E016) when the ES0 bit is “1”.
The bit also becomes “0” when the ES0 bit is set to “0” or when reset.
Note 1. Arbitration lost: The status is that communication as a master is disabled.
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
16.5.5 Bit 4: I C bus interface interrupt request bit (PIN)
2
This bit generates an I C bus interface interrupt request signal. After each byte data is transmitted, the
2
PIN bit is changed from “1” to “0”. At the same time, an I C bus interface interrupt request signal is
generated to the CPU. The PIN bit is set to “0” synchronized with the falling edge of the last internal
transmit clock (the ACK clock in ACK clock enable mode, the 8th clock in ACK clock disable mode) and an
interrupt request signal is generated synchronized with the falling edge of the PIN bit. When the PIN bit is
“0”, SCL is kept in the “0” state and the clock generation is disabled. In ACK clock enable mode, and when
the WIT bit in the S3D0 register is set to “1”, synchronized with the falling edge of the last bit clock and the
2
ACK clock, the PIN bit becomes to “0” and the I C bus interface interrupt request is generated (Refer to
Section 16.6.2 Bit1: Interrupt enable bit at the completion of data receive (WIT). Figure 16.11 shows
2
the timing of the I C bus interface interrupt request generation.
The PIN bit is set to “1” in one of the following conditions:
•Executing a write instruction to the S00 register (address 02E016).
•Executing a write instruction to the S20 register (Address : 02E416)
(only when the WIT is “1” and the internal WAIT flag is “1”)
•When the ES0 bit is “0”
•At reset
The PIN bit is set to “0” in one of the following conditions:
•Immediately after the completion of the 1-byte data transmit (including arbitration lost is detected)
•Immediately after the completion of the 1-byte data receive
•In slave receive mode, with the ALS = 0 and immediately after the completion of the slave address
match or the general call address receive
•In slave receive mode, with the ALS = 1 and immediately after the completion of the address data
receive
16.5.6 Bit 5: Bus busy flag (BB)
This bit indicates the operating conditions of the bus system. When this bit is set to “0”, the bus system is
not used and a START condition can be generated. The BB flag is set/reset by the SCL and the SDA pins
input the signal regardless of master or slave mode. This flag is set to “1” by detecting the start condition,
and is set to “0” by detecting the stop condition. The condition of these detections is followed by the start/
stop condition setting bits (SSC4–SSC0) of the S2D0 register (address 02E516). When the ES0 bit of the
S1D0 register (address 02E316) is “0” or reset, the BB flag is set to “0”. For the writing function to the
BB flag, refer to Section 16.9 START Condition Generation Method and 16.11 STOP Condi-
tion Generation Method as described later.
S
CL
PIN flag
2
I CIRQ
Figure 16.11 Interrupt request signal generation timing
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Specifications in this manual are tentative and subject to change.
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
16.5.7 Bit 6: Communication mode select bit (transfer direction select bit: TRX)
This bit decides a transfer direction for the data communication. When this bit is “0”, receive mode is
selected and the data from a transmit device is received. When the bit is “1”, transmit mode is selected
and the address data and the control data are output onto the SDA synchronized with the clock gener-
ated on the SCL. This bit can be set/reset by software or hardware. This bit is set to “1” by hardware in the
following condition:
•In slave mode with the ALS = 0, if the AAS flag is set to “1” after the address data receive and the
___
received R/W bit is “1”.
This bit is set to “0” by hardware in one of the following conditions:
•When an arbitration lost is detected.
•When a STOP condition is detected.
•When a START condition is detected.
•When a start condition is disabled by the START condition duplicate protect function (1)
.
•When a start condition is detected with MST = 0.
•When ACK non-return is detected with MST = 0.
•ES0 = 0.
•At reset
16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST)
This bit is used for the master/slave select bit for the data communication. When this bit is “0”, the slave is
specified, so that a START condition and a STOP condition are generated by the master are received. The
data communication is performed synchronized with the clock generated by the master. When this bit is
“1”, the master is specified and a START condition and a STOP condition are generated.
Additionally, the clocks required for the data communication are generated on the SCL.
This bit is set to “0” by hardware in one of the following conditions.
•Immediately after the completion of 1-byte data transfer,which lost the arbitration, when arbitration lost is
detected.
•When a STOP condition is detected.
•When a START condition is detected.
•Writing a start condition is disabled by the start condition duplicate protect function(Note 1).
•At reset
Note 1. START condition duplicate protect function
The MST, TRX, and BB bits are set to “1” at the same time after confirming that the BB flag is “0”
in the procedure of a START condition generation. However, when a START condition generation
by other master devices and the BB flag is set to “1” immediately after the contents of the BB flag
are confirmed, the START condition duplicate protect function makes the writing to the MST and
TRX bits invalid. The duplicate protect function becomes valid from the rising of the BB flag to
receive completion of the slave address. Refer to Section 16.9 START Condition Generation
Method for details.
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Specifications in this manual are tentative and subject to change.
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
16.6 I C0 control register 1 (S3D0 register)
2
2
I C0 control register 1 (address 02E616) controls I C bus interface circuit.
16.6.1 Bit 0 : Interrupt enable bit by STOP condition (SIM )
2
2
This bit enables the I C bus interface to request an I C bus interface interrupt by detecting a STOP
2
condition. If the bit set to “1”, an interrupt request from the I C bus interface is generated by detecting a
STOP condition ( There is no change for the PIN flag)
16.6.2 Bit 1: Interrupt enable bit at the completion of data receive (WIT)
When with ACK mode (ACK bit = 1) is specified, by the interrupt enable (WIT bit = 1) at the completion of
2
data receive, the I C bus interface interrupt request is generated and the PIN bit becomes “0” synchro-
nized with the falling edge of the last data bit clock. The SCL becomes “L” and the ACK clock generation
is suppressed.
2
Table 16.4 and Figure 16.12 show the I C Bus interrupt request timing and the communication restart
method. After the communication restart, synchronized with the falling edge of ACK clock, the PIN bit
2
becomes “0” again and the I C bus interface interrupt request is generated.
Table16.4 Timing of interrupt generation in data receive
2
I C Bus interrupt generation timing
1) Synchronized with the falling edge of the
last data bit clock
Communication restart method
2
The execution of writing to ACK bit of I C0 clock control
register. Follow this by a register write to set PIN bit = 1.
2
(Do not write to the I C0 data shift register.
The ACK clock operation can be incorrect.)
2
2) Synchronized with the falling edge of the
ACK clock
The execution of writing to the I C0 data shift register
The state of the internal WAIT flag can be read out by reading the WIT bit. The internal WAIT flag is set after
2
2
writing to the I C0 data shift register, and it is reset after writing to the I C0 clock control register. Conse-
2
quently, the I C bus interface interrupt request generated by the timing 1) or 2) can be determined. (See
Figure 16.12 The timing of the interrupt generation at the competion of data receive.) In the cases of
2
transmit and the address data receive immediately after the START condition, the I C bus interface interrupt
request is only generated at the falling edge of the ACK clock regardless of the value of the WIT bit and the
WAIT flag remains the reset state. Write “0” to the WIT bit when in NACK is specified. (ACK bit = 0)
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
In receive mode, ACK bit = 1 WIT bit = 0
ACK
clock
7 clock
8 clock
1 clock
1 bit
S
CL
7 bit
8 bit
ACK bit
S
DA
ACKBIT
PIN flag
Internal WAIT flag
2
I C bus interface
interrupt request signal
2
The writing signal of I C0
data shift register
In receive mode, ACK bit = 1 WIT bit = 1
ACK
clock
7 clock
8 clock
SCL
7 bit
8 bit
1 bit
S
DA
ACKBIT
PIN flag
Internal WAIT flag
2
1)
I C bus interface
2)
interrupt request signal
2
The writing signal of I C0
data shift register
2
The writing signal of I C0
clock control register
2
Note: Do not write to the I C0 clock control register except the bit
ACKBIT.
Figure 16.12 The timing of the interrupt generation at the completion of the data receive
16.6.3 Bits 2,3 : Port function select bits PED, PEC
2
When the ES0 bit of the I C0 control register 0 is set to “1”, P21 and P20 functions as SCL and SDA pins
respectively. However, if the PED is set to “1”, the SDA functions as the output port so as to the SCL if the
2
PEC is set to “1”. In this case, if “0” or “1” is written to the port register, the data can be output onto the I C
bus regardless of the internal SCL/SDA output signals. The functions of SCL/SDA are returned back by
setting the PED to “1” again.
2
If the ports are set in input mode, the values on the I C bus can be known by reading the port register
regardless of the values of the PED and PEC.Table 16.5 shows the port specification.
Table 16.5 Port specifications
P20 port
direction register
Pin name
P20
ES0 bit
PED bit
Function
Port I/O function
0
1
1
-
0/1
0
1
-
-
SDA I/O function
SDA input function, port output function
P21 port
direction register
P21
ES0 bit
PEC bit
Function
0
1
-
0/1
-
Port I/O function
SCL I/O function
0
1
1
-
SCL input function, port output function
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
16.6.4 Bits 4,5 : SDA/SCL logic output value monitor bits SDAM/SCLM
2
These bits enableto monitor the logic value of the SDA and SCL output signals from the I C bus interface
circuit. The SDAM bit monitors the SDA output logic value. The SCLM bit monitors the SCL output logic value.
The bits are read-only. When write, set to “0”.
2
16.6.5 Bits 6,7 : I C system clock select bits ICK0, ICK1
These bits and ICK4 to ICK2 bits in the S4D0 register select the system clock (VIIC) of the I C bus interface
2
2
circuit. These bits enable to select the I C bus system clock VIIC among divisions by 2, 2.5, 3, 4, 5, 6 or 8
of the main clock f(XIN).
2
Table 16.6 I C system clock select bits
2
I3CK4[S4D0] ICK3[S4D0]
ICK2[S4D0]
ICK1[S3D0]
ICK0[S3D0]
I C system clock
VIIC = 1/2 f(XIN)
VIIC = 1/4 f(XIN)
VIIC = 1/8 f(XIN)
VIIC = 1/2.5 f(XIN)
VIIC = 1/3 f(XIN)
VIIC = 1/5 f(XIN)
VIIC = 1/6 f(XIN)
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
0
X
X
X
X
X
X
X
X
( Do not set the combination which is not indicated here)
16.6.6 The address receive in STOP mode/WAIT mode
2
The I C bus interface circuit enables to receive the address data in WAIT mode when setting the CM02 bit
in the CM0 register to "0" (do not stop the peripheral function clock in wait mode) and entering WAIT mode.
2
However, the I C bus interface circuit is not operated in STOP mode or in low power consumption mode,
2
because the I C bus system clock VIIC is not supplied.
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
16.7 I C0 control register 2 (S3D0 register)
2
2
I C0 control register 2 (address: 02E716) controls the abnormal communication detection. In the I C bus
communication, the data transfer is controlled by the SCL clock signal. The devices are stoped in the commu-
nication state if the SCL clock is stopped during the transfer. To avoid that, if the SCL clock is stopped in “H”
2
state for a period of time, the I C bus interface circuit has the function to detect the time out and generate an
2
I C bus interface interrupt request. Please see Figure 16.13 The timing of time out detection.
S
CL clock stop (“H”)
1 clock
2 clock
3 clock
SCL
1 bit
2 bit
3 bit
SDA
BB flag
Internal counter start signal
Internal counter stop, reset signal
Internal counter overflow signal
The time of timeout detection
I2C-BUS interface interrupt
request signal
Figure 16.13 The timing of time out detection
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
16.7.1 Bit0: Time out detection function enable bit (TOE)
2
The bit enables a time out detection function. When setting this bit to “1”, the I C bus interface interrupt
request signal is generated if the SCL clock is stopped in “H” state for a period of time during the bus busy
(BB flag =1).
The time out detection period is measured by the internal counter and selected from long time mode or
short time mode by the time out detection period select bit (TOSEL). When time out is detected, set the
ES0 bit to “0” and then process initialization.
16.7.2 Bit1: Time out detection flag (TOF )
The bit is the flag showing the time out detection status. If the internal counter which measures the time out
2
period overflows, the time out detection flag (TOF) becomes to “1”, and at the same time the I C bus
interface interrupt request signal is generated.
16.7.3 Bit2: time out detection period select bit (TOSEL)
The bit selects time out detection period from long time and short time mode. If the TOSEL = 0, the long
time mode and TOSEL = 1, the short time mode is selected respectively. The long time is counted by 16-
2
bit counters and the short time is counted by 14-bit counters based on the I C system clock (VIIC). Table
16.7 shows examples of the time out detection period.
Table 16.7 Examples of time out detection period
(Unit: ms)
VIIC(MHz)
Long time mode
Short time mode
4
2
1
16.4
32.8
65.6
4.1
8.2
16.4
2
16.7.4 Bits 3,4,5: I C system clock select bits (ICK2-4)
ICK4 to 2 bits, ICK1 and ICK0 bits of the S3D0 register select the system clock (VIIC) of the I C bus
2
2
interface circuit.Table 16.6 shows the I C system clock setting for the setting values.
16.7.5 Bit7: STOP condition detection interrupt request bit (SCPIN)
2
The bit monitors the stop condition detection interrupt. The bit becomes to “1” when the I C bus interface
interrupt is generated by detecting of the STOP condition. Writing “0” clears the bit and “1” can not be
written.
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
16.8 I C0 START/STOP condition control registers (S2D0 register)
2
The I C0 START/STOP condition control register(address 02E516) controls the detection of the START/
STOP condition.
16.8.1 Bit0-Bit4: START/STOP condition setting bits (SSC0-SSC4)
2
Because the release time, the set up time and the hold time of the SCL are measured on the base of the I C
bus system clock(VIIC). The detecting condition changes depending on the oscillation frequency (XIN) and
2
the I C bus system clock select bits. It is necessary to set the appropriate value of START/STOP condition
setting bits (SSC4-SSC0) and set the release time, the set up time and the hold time by the system clock
frequency. Refer to Table 16.10 Start/Stop condition detect conditions. Do not set odd numbers or
“000002” to START/STOP condition setting bits. Table 16.2 shows the recommended setting value to START/
STOP condition setting bits (SSC4-SSC0) at each oscillation frequency under standard clock mode. The
detection of the START/STOP condition starts immediately after setting the ES0 bit to "1".
16.8.2 Bit5: SCL/SDA interrupt pin polarity select bit (SIP)
The SCL/SDA interrupt can be generated by detecting the rising edge or the falling edge of the SCL pin or
the SDA pin. The SCL/SDA interrupt pin polarity select bit selects the polarity of the SCL pin or the SDA pin for
interrupt.
16.8.3 Bit6 : SCL/SDA interrupt pin select bit (SIS)
The SCL/SDA interrupt pin select bit selects either the SCL pin or the SDA pin as the SCL/SDA interrupt enable
pin.
NOTES:
The SCL/SDA interrupt request may be set when the setting of the SCL/SDA interrupt pin polarity se lect
2
bit, SCL/SDA interrupt pin select bit and I C bus interface enable bit ES0 are changed. When using the
SCL/SDA interrupt, write “0” to the SCL/SDA interrupt request bit after setting the above bits, and enable
the SCL/SDA interrupt.
16.8.4 Bit7: START/STOP condition generation select bit (STSPSEL)
The bit selects the length of the set up and the hold time when the START/STOP condition is generated. The
2
length of the set up and hold time is based on the I C system clock cycles. Refer to Table 16.8 Start/Stop
2
generation timing table. Set the bit to “1” if the I C bus system clock frequency is over 4MHz.
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
16.9 START Condition Generation Method
When the ES0 bit of the I C0 control register is “1” and the BB flag of the I C0 status register is “0”, writing
2
2
2
“1” to the MST, TRX, and BB bits and “0” to the PIN and low-order bits of the I C0 status register (S10
register) simultaneously enters the standby status to generate the start condition. The start condition is
2
generated after writing the slave address data to the I C0 data shift register. After that, the bit counter
becomes “0002” and 1-byte SCL are output. The start condition generation timing is different in standard
clock mode and high-speed clock mode. Refer to Figure 16.16 Start condition generation timing dia-
gram, and Table 16.8 Start/Stop generation timing table.
Interrupt disable
No
BB=0?
Yes
Start condition standby status setting
S10=E016
Start condition trigger generation
S00=Data
*Data=Slave address data
Interrupt enable
Figure 16.14 Start condition generation flow chart
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
16.10 START condition duplicate protect function
It is necessary to verify that the bus is not in use via the BB flag before the start condition is generated.
However,when the BB flag is set to “1” because a start condition is generated by another master devices
immediately after the BB flag is verified, the start condition is suspended by the start condition duplicate
protect function. When the function starts, it works as follows:
•The start condition standby setting is disabled.
If the start condition standby has been set, release it and resets the MST and TRX bits.
2
•Writing to the I C0 data shift register is disabled. (The start condition trigger generation is disabled)
•When the start condition generation is interrupted, sets the AL flag.
The start condition duplicate protect function is valid from the SDA falling edge of the start condition to the
slave receive completion. Figure16.15 shows the duration of the start condition duplicate protect function.
ACK clock
1 clock
2 clock
2 bit
3 clock
3 bit
8 clock
8 bit
S
CL
DA
1 bit
ACK bit
S
BB flag
The duration of start condition duplicate protect
Figure 16.15 The duration of the start condition duplicate protect function
16.11 STOP Condition Generation Method
When the ES0 bit in the I C0 control register is “1”, writing “1” to the MST and the TRX bits in the I C0
2
2
2
status register, and “0” to the BB, PIN and low-order 4 bits in the I C0 status register simultaneously enters
the standby status to generate the stop condition. The stop condition is generated after writing the dummy
2
data to the I C0 data shift register. The stop condition generation timing is different in standard clock mode
and high-speed clock mode. Refer to Figure 16.17 STOP condition generation timing diagram, and
2
2
Table 16.8 Start/Stop generation timing table. Do not write data to the I C0 status register and the I C0
data shift register, before the BB flag becomes “0” after executing the instruction to generate the stop
condition. Otherwise, the stop condition waveform may not be operated normally.
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
2
I C0 data shift register
write signal
Setup
time
Hold
time
S
S
CL
DA
Figure 16.16 Start condition generation timing diagram
2
I C0 data shift register
write signal
Hold
time
SCL
Setup
time
SDA
Figure 16.17 Stop condition generation timing diagram
Table 16.8 Start/Stop generation timing table
Item
Start/Stop condition generation
Standard clock mode
High-speed clock mode
select bit
“0”
Setup
time
hold
time
5.0µs (20 cycles)
13.0µs (52 cycles)
5.0µs (20 cycles)
13.0µs (52 cycles)
2.5µs (10 cycles)
6.5µs (26 cycles)
2.5µs (10 cycles)
6.5µs (26 cycles)
“1”
“0”
“1”
Note 1. Actual time at the time of VIIC = 4MHz, The contents in () denote cycle numbers.
As mentioned above, Writing “1” to MST and TRX bits.
Writing “1” or “0” to the BB bit, writing “0” to the PIN and low-order 4 bits, simultaneously set up the START
or STOP condition standby. It releases the SDA in the START condition standby, sets the SDA to “L” in the
STOP condition standby. The signal writing to data shift register triggers the generation of START/STOP
conditions. In the case of setting the MST, and the TRX to “1” without generating a START/STOP condi-
tion. Write “1” to the low-order 4 bits simultaneously. Table16.9 shows the function of writing to the status
register.
Table 16.9 The function of writing to status register
The value of the data writing to status register
MST TRX BB PIN AL AAS AS0 LRB
Function
1
1
1
1
1
0
-
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
Setting up the START condition stand by in master transmit mode
Setting up the STOP condition stand by in master transmit mode
2
0/1 0/1
Setting up each communication mode (refer to Chapter 16.5 I C status register)
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
16.12 START/STOP Condition Detect Operation
Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. The START/
STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected
only when the input signal of the SCL and SDA pins satisfied with three conditions: the SCL release time, the
setup time, and the hold time (see Table.16.10 Start/Stop condition detect conditions). The BB flag is
set to “1” by detecting the start condition and is set to “0” by detecting the stop condition. The BB flag set
and reset timing are different in standard clock mode and high-speed clock mode. See Table.16.10 Start/
Stop condition detect conditions.
S
CL release time
SCL
Setup
time
Hold
time
SDA
BB flag
set time
BB flag
Figure 16.18 Start condition detection timing diagram
S
CL release time
S
CL
Setup
time
Hold
time
S
DA
BB flag
reset time
BB flag
Figure 16.19 Stop condition detection timing diagram
Table 16.10 Start/Stop detection timing table
Standard clock mode
High-speed clock mode
4 cycles (1.0µs)
SCL release time
Setup time
SSC value + 1 cycle (6.25µs)
SSC value + 1 cycle < 4.0µs (3.25µs)
2 cycles (0.5µs)
2
Hold time
SSC value cycle < 4.0µs (3.0µs)
2 cycles (0.5µs)
2
BB flag set/reset
time
SSC value - 1 +2 cycles (3.375µs)
3.5 cycles (0.875µs)
2
2
Note 1. Unit : Cycle numbers of I C system clock VIIC
The SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0.
2
Do not set “0” or odd numbers to the SSC value. The values in () are examples when the I C0
start/stop condition control register is set to “1816” at VIIC = 4 MHz.
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2
16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
16.13 Address Data Communication
16.13.1 Example of Master Transmit
An example of master transmit in standard clock mode, at the SCL frequency of 100 kHz and in ACK return
mode is shown below.
2
1)Set the slave address in the upper 7-bit of I C0 address registers (S0D0).
2
2)Set ACK return mode and the SCL = 100 kHz by setting “0016” in the I C0 control register 1(S3D0),
2
2
“0002” in the ICK4 to ICK2 bits of the I C0 control register 2(S4D0) and “8516” in the I C0 clock control
register (S20) respectively. (f1=8MHz)
2
3)Set “0016” in the I C0 status register (S10) so that transmit/receive mode is initialized.
2
4)Set a communication enable status by setting “0816” in the I C0 control register 0 (S1D0).
2
5)Confirm the bus free condition by the BB flag of the I C0 status register (S10).
2
6)Set “E016” in the I C0 status register (S10) to set the start condition standby.
2
7 )Set the destination address data for transmit in high-order 7 bit in the I C0 data shift register (S00) and
set “0” in the least significant bit. And then a start condition is generated. At this time, SCL for 1 byte
and an ACK clock are automatically generated.
2
8)Set transmit data in the I C0 data shift register (S00). At this time, an SCL and an ACK clock
are automaticall generated.
9)When transmitting more than 1-byte control data, repeat step 7).
2
10)Set “C016” in the I C0 status register (S10) to set a stop condition if ACK is not returned from the slave
receive side or the transmit end.
2
11)A stop condition is generated when writing the dummy data to the I C0 data shift register (S00).
Figure 16.20 (1) shows the master transmit format.
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
16.13.2 Example of Slave Receive
An example of the slave receive in high-speed clock mode, at the SCL frequency of 400 kHz, in ACK return
mode and using the addressing format is shown below.
2
1)Set a slave address in the high-order 7 bits in the I C0 address register (S0D0).
2
2)Set ACK clock mode and SCL = 400 kHz by setting “0016” in the I C0 control register 1 (S3D0), “0002”
2
2
in the ICK4 to ICK2 bits in the I C0 control register 2 (S4D0) and “A516” in the I C0 clock control register
(S20) respectively. (f1=8MHz)
2
3)Set “0016” in the I C0 status register (S10) so that transmit/receive mode is initialized.
2
4)Set a communication enable status by setting “0816” in the I C0 control register 0 (S1D0).
5)When a start condition is received, an address comparison is performed.
6)•When all transmitted addresses are “0” (general call):
2
2
ADR0 in the I C0 status register (S10) is set to “1” and an I C bus interface interrupt request signal
is generated.
•When the transmitted addresses match with the address set in 2):
2
2
ASS in the I C0 status register (S10) is set to “1” and an I C bus interface interrupt request signal
occurs.
2
2
•In the cases other than the above ADR0 and AAS of the I C0 status register are set to “0” and no I C
bus interface interrupt request signal occurs.
2
7)Set dummy data in the I C0 data shift register (S00).
2
8)After receiving 1-byte data, an ACK is automatically returned and an I C bus interface interrupt request
signal is generated.
2
9)After receiving 1-byte data, an I C bus interface interrupt request signal is generated, set the ACKBIT
to “1” or “0” by reading the contents in the data shift register (S00). and the ACK bit is returned or not
returned.
10)When receiving more than 1-byte control data, repeat step 7) 8) or 7) 9).
11)When a STOP condition is detected, the communication ends.
Refer to Figure 16.20 Address data communication format, (2).
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
(1) A master transmit device transmits data to a receive device
Data
Data
S
Slave address
bits
R/W
A
A
A/A
P
P
“0”
1 - 8 bits
1 - 8 bits
7
(2) A master receive device receives data from a transmit device
S
R/W
A
Data
A
Data
A
Slave address
bits
“1”
1 - 8 bits
1 - 8 bits
7
S
:
START condition
P : STOP condition
A : ACK bit
R/W : Read/Write bit
Figure 16.20 Address data communication format
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
16.14 Usage precautions
2
(1) Access to the registers of I C bus interface circuit
2
The precaution of read/write to the control registers of I C bus interface circuit is as follows.
2
•I C0 data shift register (S00 : 02E016)
Do not write the register during the data transfer. The transfer bit counter is reset and the data may not be
transfered normally.
2
•I C0 control register 0 (S1D0 : address 02E316).
After the start condition detection or the 1-byte transfer completion, the bit counter (bits BC2 to
BC0) is reset by Hardware. Do not read/write the register at this time, because the data may be
undetermined.
Figure 16.22 and Figure 16.23 show the bit counter reset timing by Hardware.
2
•I C0 clock control register (S20 : address 02E416)
2
Do not write to this register except the ACKBIT during the transfer. The I C clock generator is reset
and the data may not be transfered normally.
2
•I C0 control register 1 (S3D0 : address 02E616)
2
2
Write I C system clock select bits when I C bus interface enable bit (ES0)is disabled. When the data
receive completion interrupt enable bit (WIT) reads out, the internal WAIT flag is read.Do not use the
bit managing instrustion (read-modify-write instruction) to access the register.
2
•I C0 status register (S10 : address 02E816)
Do not use the bit managing instruction (read-modify-write instruction) to access the register be
cause all bits of this register are changed by H/W. Do not read/write during the timing when the MST
and the TRX bits for the communication mode setting are changed. The data may be undetermined.
Figure16.21 to Figure 16.23 show the timing when the MST and the TRX bits are changed by H/W.
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
SCL
SDA
BB flag
Bit reset signal
Related bits
1.5VIIC cycle
MST
TRX
Figure 16.21 The bit reset timing (The STOP condition detection)
SCL
SDA
BB flag
Bit reset signal
Related bits
BC0 - BC2
TRX(slave mode)
Figure 16.22 The bit reset timing (The START condition detection)
S
CL
PIN bit
BC0 - BC2
The bits referring
to reset
MST(When in arbitration lost)
TRX(When in NACK receive in slave
transmit mode)
Bit reset signal
Bit set signal
2VIIC cycle
The bits referring
to set
TRX(ALS=0 meanwhile the slave
receive R/W bit = 1
1VIIC cycle
Figure 16.23 Bit set/reset timing ( at the completion of data transfer)
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16. MULTI-MASTER I C bus INTERFACE
M16C/28 Group
(2) Generation of RESTART condition
2
After 1-byte data transfer and a restart condition is generated, write“E016” to I C0 status register, set the
2
start condition standby and the SDA pin will be released. Writing to the I C0 data shift register gener-
ates the start condition trigger after waiting in software until the SDA becomes “H”. Figure 16.24 shows
the restart condition generation timing.
ACK
clock
8 clock
SCL
S
DA
Insert software wait
S1I writing signal
( START condition setting standby)
S0I writing signal
(START condition trigger generation)
Figure 16.24 The time of generation of RESTART condition
(3) Iimitation of CPU clock
2
The registers of I C bus interface circuit can not be read from or written to if the CPU clock is selected
to the sub clock (XCIN, XCOUT) by the system clock select bit (system clock control register 0, address
0006h, CM07 bit). Select the main clock (XIN, XOUT) or the ring oscillator clock in read/write.
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M16C/28 Group
17. Programmable I/O Ports
17. Programmable I/O Ports
The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 71 lines P0,
P1,P2, P3, P6, P7, P8, P9, P10 (except P94) for the 80-pin version, or 55 lines P00 to P03, P15 to P17, P2,
P30 to P33, P6, P7, P8, P90 to P93, P10 for the 64-pin version. Each port can be set for input or output every
line by using a direction register, and can also be chosen to be or not be pulled high in sets of 4 lines.
Figures 17.1 to 17.5 show the I/O ports. Figure 17.6 shows the I/O pins.
Each pin functions as an I/O port, a peripheral function input/output.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin
is used as a peripheral function input, set the direction bit for that pin to “0” (input mode). Any pin used as an
output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set.
17.1 Port Pi Direction Register (PDi Register, i = 0 to 3, 6 to 10)
Figure 17.1.1 shows the direction registers.
This register selects whether the I/O port is to be used for input or output. The bits in this register corre-
spond one for one to each port.
17.2 Port Pi Register (Pi Register, i = 0 to 3, 6 to 10)
Figure 17.2.1 shows the Pi registers.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the output data and a circuit to read the pin status. For ports
set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register. The data written to the port latch is output
from the pin. The bits in the Pi register correspond one for one to each port.
17.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Regis-
ters)
Figure 17.3.1 shows the PUR0 to PUR2 registers.
The PUR0 to PUR2 register bits can be used to select whether or not to pull the corresponding port high
in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit
is set for input mode.
17.4 Port Control Register
Figure 17.4.1 shows the port control register.
When the P1 register is read after setting the PCR register’s PCR0 bit to “1”, the corresponding port latch
can be read no matter how the PD1 register is set.
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M16C/28 Group
17. Programmable I/O Ports
17.5 Pin Assignment Control register (PACR)
Figure 17.5.1 shows the PACR. After reset set PACR2 to PACR0 bit in the PACR register before you
input and output to each pin. When the PACR register isn’t set up, the input and output function of some
of the pins doesn’t work.
PACR2 to PACR0 : control the number of pins enabled for use.
At reset these bits equal “0002” .
When using the 80 pin version of the M16C/28 set these bits to “0112”.
When using the 64 pin version of the M16C/28 set these bits to “0102”.
U1MAP : controls the assignment of UART1 pins.
If U1MAP = “0” (default at reset) the UART1 functions are assigned to P64/CTS1/RTS1, P65/CLK1,
P66/RxD1, and P67/TxD1.
If U1MAP = “1” the UART1 functions are assigned to P70/CTS1/RTS1, P71/CLK1, P72/RxD1, and
P73/TxD1.
PACR is write protected by PRC2 bit of PRCR (protect register). PRC2 bit of PRCR must be set immedi-
ately before the write to PACR.
17.6 Digital Debounce function
Two digital debounce function circuits are provided. Level is determined when level is held, after applying
either a falling edge or rising edge to the pin, longer than the programmed filter width time. This enables
noise reduction.
________
_______ _____
This function is assigned to INT5/INPC17 and NMI/SD. Digital filter width is set in the NDDR register and
the P17DDR register respectively.Figure 17.6.1 shows the NDDR register and the P17DDR register.
Additionally, a digital debounce function is disabled to the port P17 input and the port P85 input.
Filter width :
f8 × 1 / (n+1)
n: count value set in the NDDR register and P17DDR register
The NDDR register and the P17DDR register decrement count value with f8 as the count source. The
NDDR register and the P17DDR register indicate count time. Count value is reloaded if a falling edge or
a rising edge is applied to the pin.
The NDDR register and the P17DDR register can be set 0016 to FF16 when using the digital debounce
function. Setting to FF16 disables the digital filter. See Figure 17.6.2 for details.
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M16C/28 Group
17. Programmable I/O Ports
Pull-up selection
Direction register
P0
P3
0
0
to P0
to P3
7
, P93
(inside dotted-line
included)
Port latch
Data bus
(Note 1)
(inside dotted-line not included)
7
Analog input
Pull-up selection
Direction register
P1
P1
0
to P1
3
(inside dotted-line included)
Port P1 control register
Port latch
Data bus
(inside dotted-line not included)
(Note 1)
4
Analog input
Pull-up selection
Direction register
(inside dotted-line not included)
5 to P16
P1
P1
Port P1 control register
Data bus
(inside dotted-line included)
Port latch
(Note 1)
7
Input to respective peripheral functions
Digital
INPC17/INT5
Debounce
Pull-up selection
P2
P6
2
4
to P2
, P6 , P7
(inside dotted-line included)
7
, P3
0
, P6
0
, P6
1
,
Direction
register
5
3
, P7
5
, P8
1
"1"
Output
Port latch
Data bus
(Note 1)
P32, P7
4, P7
6, P80
(inside dotted-line not included)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 17.1. I/O Ports (1)
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M16C/28 Group
17. Programmable I/O Ports
Pull-up selection
Direction
register
P2
0, P2
1
, P71, P72
"1"
Output
Port latch
Data bus
(Note 1)
Switching
between
CMOS and
Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P8
2
to P8
4
Port latch
Data bus
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction register
P31, P77, P90 to P92
Port latch
Data bus
(Note 1)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 17.2. I/O Ports (2)
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M16C/28 Group
17. Programmable I/O Ports
Pull-up selection
Direction register
P6
2, P6
6
Port latch
Data bus
(Note 1)
Switching
between
CMOS and Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P63, P67
“1”
Output
Port latch
Data bus
(Note 1)
Switching between CMOS and Nch
Pull-up selection
NMI Enable
P85
Direction register
Port latch
Data bus
(Note 1)
Digital Debounce
NMI Interrupt Input
NMI Enable
SD
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 17.3. I/O Ports (3)
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M16C/28 Group
17. Programmable I/O Ports
Pull-up selection
P100 to P103
(inside dotted-line
not included)
Direction register
P97, P104 to P107
(inside dotted-line
included)
Data bus
Port latch
(Note 1)
Analog input
Input to respective peripheral functions
Pull-up selection
Direction register
P95, P96
“1”
Output
Data bus
Port latch
(Note 1)
Analog input
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 17.4. I/O Ports (4)
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M16C/28 Group
17. Programmable I/O Ports
Pull-up selection
Direction register
P8
7
Data bus
Port latch
(Note)
fc
Rf
Pull-up selection
Rd
Direction register
P8
6
Data bus
Port latch
(Note)
Note:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 17.5. I/O Ports (5)
CNVSS
CNVSS signal input
(Note 1)
RESET
Note 1:
RESET signal input
(Note 1)
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 17.6. I/O Pins
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M16C/28 Group
17. Programmable I/O Ports
Port Pi direction register (i=0 to 3, 6 to 8, and 10) (Note)
Symbol
PD0 to PD3
PD6 to PD8
PD10
Address
After reset
0016
03E216, 03E316, 03E616, 03E716
03EE16, 03EF16, 03F216
03F616
b7 b6 b5 b4 b3 b2 b1 b0
0016
0016
Bit symbol
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
PDi_0
PDi_1
PDi_2
PDi_3
Port Pi
0
direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
Port Pi
1
2
3
direction bit
Port Pi
Port Pi
direction bit
direction bit
(Functions as an output port)
(i = 0 to 3, 6 to 8, and 10)
PDi_4
PDi_5
PDi_6
PDi_7
Port Pi
Port Pi
Port Pi
Port Pi
4
5
6
7
direction bit
direction bit
direction bit
direction bit
Note: Ports must be enabled using the PACR
In 80 pin version set PACR2, PACR1, PACR0 to "011
In 64 pin version set PACR2, PACR1, PACR0 to "010
2
2
"
"
Port P9 direction register (Note 1,2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD9
Address
03F316
After reset
00000000
2
RW
RW
RW
Bit symbol
PD9_0
Bit name
Function
Port P9
0
direction bit
direction bit
direction bit
direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
PD9_1
PD9_2
PD9_3
Port P9
Port P9
Port P9
1
2
3
RW
RW
(Functions as an output port)
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
(b4)
PD9_5
PD9_6
PD9_7
Port P9
Port P9
Port P9
5
6
7
direction bit
direction bit
direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
RW
RW
RW
(Functions as an output port)
Note 1: Make sure the PD9 register is written to by the next instruction after setting the PRCR
register's PRC2 bit to "1"(write enabled).
Note 2: Ports must be enabled using the PACR
In 80 pin version set PACR2, PACR1, PACR0 to "011
In 64 pin version set PACR2, PACR1, PACR0 to "010
2
2
"
"
Figure 17.1.1. PD0, PD1, PD2, PD3, PD6, PD7, PD8, PD9, and PD10 Registers
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M16C/28 Group
17. Programmable I/O Ports
Port Pi register (i=0 to 3, 6 to 8 and 10) (Note)
Symbol
P0 to P3
P6 to P8
P10
Address
After reset
03E016, 03E116, 03E416, 03E516
03EC16, 03ED16, 03F016
03F416
Indeterminate
Indeterminate
Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Pi_0
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
1
2
3
4
bit
bit
bit
bit
bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Pi_7
Port Pi
Port Pi
Port Pi
5
6
7
bit
bit
bit
0 : “L” level
1 : “H” level (Note 1)
(i = 0 to 3, 6 to 8 and 10)
Note: Ports must be enabled using the PACR
In 80 pin version set PACR2, PACR1, PACR0 to "011
In 64 pin version set PACR2, PACR1, PACR0 to "010
2
2
"
"
(Note1)
Port P9 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P9
Address
03F116
After reset
Indeterminate
RW
RW
RW
Bit symbol
P9_0
Bit name
Function
Port P9
0
bit
bit
bit
bit
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
P9_1
Port P9
Port P9
Port P9
1
2
3
P9_2
RW
RW
-
P9_3
(b4)
Nothing is assigned (Note 2)
P9_5
Port P9
Port P9
Port P9
5
6
7
bit
bit
bit
RW
RW
RW
this register (except for P8
0 : “L” level
5)
P9_6
1 : “H” level
P9_7
Note1: Ports must be enabled using the PACR
In 80 pin version set PACR2, PACR1, PACR0 to "011
In 64 pin version set PACR2, PACR1, PACR0 to "010
2
2
"
"
Note2: Nothing is assigned. In an attempt to write t o this bit, write "0".
The value if read turns out to be "0".
Figure 17.2.1. P0, P1, P2, P3, P6, P7, P8, P9, and P10 Registers
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M16C/28 Group
17. Programmable I/O Ports
Pull-up control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
After reset
0016
Bit symbol
PU00
Bit name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
P0
0
to P0
3
pull-up
0 : Not pulled high
1 : Pulled high (Note)
PU01
PU02
PU03
PU04
PU05
PU06
PU07
P0
P1
P1
P2
P2
P3
P3
4
0
4
0
4
0
4
to P0
to P1
to P1
to P2
to P2
to P3
to P3
7
3
7
3
7
3
7
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
Note : The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
After reset(Note 5)
000000002
Bit symbol
(b3-b0)
Bit name
Function
RW
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
PU14
PU15
P6
P6
0
4
to P6
to P6
3
7
pull-up
pull-up
0 : Not pulled high
1 : Pulled high (Note)
RW
RW
RW
RW
PU16
PU17
P70
4
to P7
3
7
pull-up
pull-up
P7
to P7
Note : The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FE16
After reset
0016
Bit symbol
PU20
Bit name
Function
RW
RW
RW
RW
P8
0
4
to P8
3
pull-up
pull-up
pull-up
pull-up
0 : Not pulled high
1 : Pulled high (Note)
PU21
PU22
PU23
PU24
P8
to P8
7
P9
P9
P10
P10
0
to P9
to P9
to P10
to P10
3
5
7
RW
RW
RW
0
3
pull-up
PU25
4
7 pull-up
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
(b7-b6)
Note : The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Figure 17.3.1. PUR0 to PUR2 Registers
Rev.0.60 2004.02.01 page 279 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
17. Programmable I/O Ports
Port control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbpl
PCR
Address
03FF16
After reset
0016
Bit symbol
PCR0
Bit name
Function
RW
Port P1 control bit
Operation performed when the P1
register is read
0: When the port is set for input,
the input levels of P10 to P17
pins are read. When set for
output, the port latch is read.
1: The port latch is read
RW
regardless of whether the port
is set for input or output.
Nothing is assigned. In an attempt to write to these bits,
write “0”. The value, if read, turns out to be “0”.
(b7-b1)
Figure 17.4.1. PCR Register
Pin assignment control register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbpl
PACR
Address
025D16
After reset
000000002
Bit symbol
Bit name
Pin enabling bit
Function
RW
RW
RW
RW
PACR0
PACR1
PACR2
010 : 64 pin
011 : 80 pin
All other values are reserved. Do
not use.
Reserved bits
Nothing is assigned. In an attempt
to write to these bits, write “0”.
The value, if read, turns out to
be “0”.
(b6-b3)
U1MAP
UART1 pins assigned to
UART1 pin remapping bit
RW
0 : P6
7
3
to P6
to P7
4
1 : P7
0
Note : Set bit 2 of protect register (address 000A16) to "1" before writing to PACR.
Figure 17.5.1. PACR Register
Rev.0.60 2004.02.01 page 280 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
17. Programmable I/O Ports
NMI digital debounce register (Note)
b7
b0
Symbol
NDDR
Address
033E16
After reset
FF16
Function
RW
RW
Setting range
0016~FF16
Assuming that set value =n,
for n = 0 to FEh, NMI / SD pulse whose width is greater than
(V1/8) / ( n + 1) will be input.
For n = FFh, the digital debounce filter is disabled.
All signals are input
Note : Set bit 2 of protect register (Address 000A16) to "1" before writing to NDDR.
P1
7
digital debounce register
b7
b0
Symbol
P17DDR
Address
033F16
After reset
FF16
Setting range
0016~FF16
Function
RW
RW
Assuming that set value =n,
for n = 0 to FEh, INPC17 / INT5 pulse whose width is greater
than (V1/8) / ( n + 1) will be input.
For n = FFh, the digital debounce filter is disabled.
All signals are input
Figure 17.6.1. NDDR and P17DDR Registers
Rev.0.60 2004.02.01 page 281 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
17. Programmable I/O Ports
Digital Debounce Filter
Clock
f
8
Port In
Signal Out
P8
5 / P17
To NMI and SD / INT5 and INPC17
Data Bus
Reload Value
(write)
Count Value
(read)
Data Bus
f
8
Reload Value
Port In
FF
03
Signal Out
Count Value
03
02
01
00
FF
02
01
03
FF
3
1
2
4
5
Reload Value
(continued)
03
FF
Port In
(continued)
Signal Out
(continued)
01
FF
Count Value
(continued)
03
02
00
FF
03
02
FF
6
8
7
9
1. (Condition after reset). Reload = FF, Port In = signal Out continuosly.
2. Reload = 03. At edge of Port In != Signal Out, Counter gets Reload Value and
stats counting down.
3. Port In = Signal Out, counting stops.
4. At edge of Port In != Signal Out, Counter gets Reload Value and starts counting.
5. Counter underflows, stops, and Port In is driven to Signal Out.
6. At edge of Port In != Signal Out, counter gets Reload Value and starts counting.
7. Counter underflows, stops, and Port In is driven to Signal Out.
8. At edge of Port In != Signal Out, counter gets Reload Value and starts counting.
9. FF is written to Reload Value. Counter is stopped and loaded with FF.
Port In = Signal Out continuously.
Figure 17.6.2. Functioning of Digital Debounce Filter
Rev.0.60 2004.02.01 page 282 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
17. Programmable I/O Ports
Table 17.1. Unassigned Pin Handling in Single-chip Mode
Pin name
Connection
After setting for input mode, connect every pin to VSS via a resistor(pull-down);
or after setting for output mode, leave these pins open. (Note 1, Note 2, Note 4)
Ports P0 to P3,
P6 to P10
XOUT (Note 3)
Open
Connect via resistor to VCC (pull-up)
Connect to VCC
Xin
AVCC
AVSS, VREF
Connect to VSS
Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input
mode until it is switched to output mode in a program after reset. For this reason, the voltage level
on the pin becomes indeterminate, causing the power supply current to increase while the port
remains in input mode.
Futhermore, by considering a possibility that the contents of the direction registers could be
changed by noise or noise-induced runaway, it is recommended that the contents of the
directionregisters be periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer
pins (within 2 cm).
Note 3: With external clock or VCC input to XIN pin.
Note 4: When using the 80pin version, set PACR2, PACR1, PACR0 to "011
2
".
".
When using the 64pin version, set PACR2, PACR1, PACR0 to "010
2
Microcomputer
Port P0 to P3, P6 to P10
(Note)
(Input mode)
·
·
·
·
·
·
(Input mode)
(Output mode)
Open
XIN
X
OUT
Open
V
CC
AVCC
AVSS
V
REF
V
SS
In single-chip mode
Note : when using the 64pin version, set PACR2, PACR1, PACR0 to "010 ".
2
Figure 17.7. Unassigned Pins Handling
Rev.0.60 2004.02.01 page 283 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
18. Electrical Characteristics
18.1. Normal version
Table 18.1. Absolute Maximum Ratings
Symbol
Parameter
Condition
Rated value
-0.3 to 6.5
Unit
V
V
CC
Supply voltage
VCC=AVCC
AVCC
Analog supply voltage
VCC=AVCC
-0.3 to 6.5
V
Input
voltage
P0
P3
P8
0
0
0
to P0
to P3
to P8
7
7
7
, P1
, P6
, P9
0
0
0
to P1
to P6
to P9
7, P2
7, P7
3, P9
0
0
5
to P2
to P7
to P9
7,
7,
7
,
V
I
V
V
-0.3 to VCC+0.3
-0.3 to VCC+0.3
P10
0 to P107,
XIN, VREF, RESET, CNVSS
Output
voltage
P0
P3
P8
0
0
0
to P0
to P3
to P8
7, P1
7, P6
7, P9
0
0
0
to P1
to P6
to P9
7, P2
7, P7
3, P9
0
0
5
to P2
to P7
to P9
7,
7,
7
,
V
P
O
d
P100 to P107,
XOUT
Power dissipation
Topr=25
mW
C
C
300
T
T
opr
stg
Operating ambient temperature
Storage temperature
-20 to 85 / -40 to 85
-65 to 150
C
Rev.0.60 2004.02.01 page 284 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
Table 18.2. Recommended Operating Conditions (Note 1)
Standard
Typ.
Symbol
Parameter
Unit
Min.
2.7
Max.
5.5
V
CC
Supply voltage
V
AVcc
Vss
Analog supply voltage
Supply voltage
VCC
V
V
0
0
AVss
Analog supply voltage
V
HIGH input
voltage
P0
P7
0
0
to P0
to P7
7
, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0
to P6
7,
V
IH
IL
V
0.7VCC
0
VCC
7, P8
to P8
7
3
7, P10
0
to P10
7
,
XIN, RESET, CNVSS
LOW input
voltage
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
V
V
0.3VCC
7, P8
to P8
7
3
7, P10
0
to P10
7
7
,
XIN, RESET, CNVSS
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
HIGH peak output
current
IOH (peak)
-10.0
-5.0
mA
mA
7, P8
to P8
7
3
7, P10
0
to P10
HIGH average
output current
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
IOH (avg)
IOL (peak)
IOL (avg)
7, P8
to P8
7
3
7, P10
0
to P10
7
7
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
LOW peak output
current
10.0
mA
mA
7, P8
to P8
7
3
7, P10
0
to P10
LOW average
output current
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
5.0
20
7, P8
to P8
7
3
7, P10
0
to P10
7
V
CC=3.0 to 5.5V
CC=2.7 to 3.0V
MHz
MHz
kHz
0
0
Main clock input oscillation frequency
(Note 4)
f (XIN
)
V
33 X VCC-80
50
f (XCIN
)
Sub-clock oscillation frequency
Ring oscillation frequency 1
32.768
1
2
MHz
MHz
MHz
f
f
f
1
(ROC)
(ROC)
(ROC)
2
3
Ring oscillation frequency 2
Ring oscillation frequency 3
16
f (PLL)
PLL clock oscillation frequency (Note 4)
V
V
CC=3.0 to 5.5V
CC=2.7 to 3.0V
20
MHz
10
MHz
MHz
ms
33 X VCC-80
20
10
0
f (BCLK)
CPU operation clock
V
V
CC=5.0V
CC=3.0V
T
SU(PLL)
PLL frequency synthesizer stabilization wait time
20
50
ms
Note 1: Referenced to VCC = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.
Note 2: The mean output current is the mean value within 100ms.
Note 3: The total IOL(peak) for all ports must be 80mA max. The total IOH(peak) for all ports must be -80mA max.
Note 4: Relationship between main clock oscillation frequency, PLL clock oscillation frequency and supply voltage.
PLL clock oscillation frequency
33.3 x VCC-80MH
Main clock input oscillation frequency
33.3 x VCC-80MH
Z
20.0
Z
20.0
10.0
10.0
0.0
0.0
2.7
3.0
5.5
2.7
3.0
5.5
V
CC[V] (main clock: no division)
VCC[V] (PLL clock oscillation)
Rev.0.60 2004.02.01 page 285 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
Table 18.3. A-D Conversion Characteristics (Note 1)
Standard
Min. Typ. Max.
10
Symbol
Parameter
Resolution
Measuring condition
Unit
–
VREF =VCC
Bits
LSB
Integral non-
linearity
error
AN
AN00 to AN07, AN20 to AN27 input
AN to AN input
AN00 to AN07, AN20 to AN27 input
0 to AN7 input
±3
±7
±5
V
REF =VCC=5V
LSB
LSB
LSB
LSB
10 bit
8 bit
INL
0
7
V
V
V
REF =VCC=3.3V
±7
±2
REF =VCC=3.3V AN
0
to AN
7
input
AN
0
to AN
7
input
±3
LSB
LSB
Absolute
accuracy
REF =VCC=5V
AN00 to AN07, AN20 to AN27 input
AN to AN input
AN00 to AN07, AN20 to AN27 input
to AN input
±7
±5
10 bit
8 bit
–
0
7
LSB
LSB
LSB
LSB
V
REF =VCC=3.3V
±7
±2
±1
±3
±3
V
REF =VCC=3.3V AN
0
7
Differential non-linearity error
DNL
–
–
Offset error
LSB
LSB
kΩ
Gain error
Ladder resistance
10
40
RLADDER
V
V
REF =VCC
Conversion time(10bit),
Sample & hold function available
3.3
µs
t
CONV
REF =VCC=5V, øAD=10MHz
Conversion time(8bit),
Sample & hold function available
2.8
0.3
µs
V
REF =VCC=5V, øAD=10MHz
t
t
CONV
SAMP
Sampling time
µs
V
V
V
REF
IA
Reference voltage
Analog input voltage
2.0
0
V
CC
V
V
REF
Note 1: Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise
specified.
Note 2: AD operation clock frequency (ØAD frequency) must be 10 MHz or less. And divide the fAD if VCC is less than 4.2V,
and make ØAD frequency equal to or lower than fAD/2.
Note 3: A case without sample & hold function turn ØAD frequency into 250 kHz or more in addition to a limit of Note 2.
A case with sample & hold function turn ØAD frequency into 1MHz or more in addition to a limit of Note 2.
Rev.0.60 2004.02.01 page 286 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
Table 18.4. Flash Memory Version Electrical Characteristics (Note 1)
Standard
Parameter
Symbol
Unit
Min.
Typ.
(Note 2)
Max
Erase/Write cycle (Note 3)
100(Note 4)
cycle
µs
–
600
9
Word program time (Vcc=5.0V, Topr=25°C)
75
0.2
0.4
0.7
1.2
–
–
s
Block erase time
2Kbyte block
8Kbyte block
16Kbyte block
32Kbyte block
s
s
s
9
9
9
20
ms
Time delay from Suspend Request until Erase Suspend
Data retention time (Note 5)
td(SR-ES)
year
20
–
Table 18.5. Flash Memory Version Electrical Characteristics (Note 6) 10000 E/W cycle products (Option)
[blockA and block B(Note 7)]
Standard
Parameter
Symbol
Unit
Min.
Typ.
(Note 2)
Max
10000(Note 4,10)
cycle
µs
Erase/Write cycle (Note 3, 8, 9)
–
Word program time (Vcc=5.0V, Topr=25°C)
Block erase time(Vcc=5.0V, Topr=25°C)
(2Kbyte block)
100
0.3
–
–
9
s
20
ms
Time delay from Suspend Request until Erase Suspend
td(SR-ES)
Note 1: When not otherwise specified, Vcc = 2.7 to5.5V; Topr = 0 to 60 °C.
Note 2: VCC = 5V; TOPR = 25 °C.
Note 3: Definition of E/W cycle: Each block may be written to a variable number of times - up to a maximum of the total
number of distinct word addresses - for every block erase. Performing multiple writes to the same address before
an erase operation is prohibited.
Note 4: Maximum number of E/W cycles for which opration is guaranteed.
Note 5: Topr = 55°C.
Note 6: When not otherwise specified, Vcc = 2.7 to 5.5V; Topr = -20 to 85°C / -40 to 85°C (Option).
Note 7: Table18.5 applies for Block A or B E/W cycles > 1000. Otherwise, use Table 18.4.
Note 8: To reduce the number of E/W cycles, a block erase should ideally be performed after writing as many different
word addresses (only one time each) as possible. It is important to track the total number of block erases.
Note 9: Should erase error occur during block erase, attempt to execute clear status register command, then clock erase
command at least three times until erase error disappears.
Note 10: When Block A or B E/W cycles exceed 100 (Option), select one wait state per block access. When FMR17 is set
to "1", one wait state is inserted per access to Block A or B - regardless of the value of PM17. Wait state insertion
during access to all other blocks, as well as to internal RAM, is controlled by PM17 - regardless of the setting of
Erase suspend
request
(interrupt request)
FMR46
td(SR-ES)
Rev.0.60 2004.02.01 page 287 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
Table 18.6. Low Voltage Detection Circuit Electrical Characteristics (Note 1, Note 3
)
Standard
Typ.
Symbol
Parameter
Measuring condition
Unit
Max.
T.B.D
T.B.D
T.B.D
Min.
T.B.D
Voltage down detection voltage (Note 1)
Reset level detection voltage (Notes 1)
Low voltage reset retention voltage (Note 2)
Low voltage reset release voltage
Vdet4
Vdet3
T.B.D
T.B.D
T.B.D
V
V
T.B.D
T.B.D
T.B.D
VCC=0.8 to 5.5V
V
V
Vdet3s
Vdet3r
T.B.D
T.B.D
Note 1: Vdet4 > Vdet3
Note 2: Vdet3s is the min voltage at which "hardware reset 2" is maintained.
Note 3: The low voltage detection circuit is designed to use when VCC is set to 5V.
Table 18.7. Power Supply Circuit Timing Characteristics
Standard
Typ.
Symbol
Parameter
Measuring condition
Unit
Min.
T.B.D
Max.
2
Time for internal power supply stabilization during powering-on
Time for internal ring oscillator stabilization during powering-on
STOP release time (Note 2)
ms
ms
ms
µs
td(P-R)
td(ROC)
td(R-S)
td(W-S)
T.B.D
T.B.D
2
VCC=2.7 to 5.5V
150
50
Low power dissipation mode wait mode release time (Note 2)
Time for internal power supply stabilization when main clock oscillation starts
Hardware reset 2 release wait time
td(M-L)
td(S-R)
td(E-A)
µs
VCC=Vdet3r to 5.5V
VCC=2.7 to 5.5V
6 (Note 1)
20
20
ms
µs
Low voltage detection circuit operation start time (Note 3)
Note 1: When VCC = 5V
Note 2: This is the time between interrupt for (STOP/WAIT) mode release and resumption of CPU clock operation.
Note 3: After enabling low voltage detection, this time is required before proper detection can occur.
Vdet3r
V
CC
CPU clock
td(S-R)
Interrupt for
stop mode
release
CPU clock
td(R-S)
Rev.0.60 2004.02.01 page 288 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Table 18.8. Electrical Characteristics (Note 1
)
Standard
Typ.
Symbol
Measuring condition
Parameter
Unit
Min.
CC-2.0
CC-0.3
Max.
P0
P7
0
0
to P0
to P7
7
, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0
to P67,
HIGH output
voltage
V
OH
OH
I
OH=-5mA
V
V
V
CC
V
V
7, P8
to P8
7
3
7, P10
0
to P10
7
7
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
HIGH output
voltage
V
V
CC
I
I
I
OH=-200µA
OH=-1mA
7, P8
to P8
7
3
7, P10
0
to P10
HIGHPOWER
VCC-2.0
CC-2.0
V
CC
CC
HIGH output voltage
HIGH output voltage
XOUT
V
V
LOWPOWER
OH=-0.5mA
V
V
V
OH
With no load applied
With no load applied
2.5
1.6
HIGHPOWER
LOWPOWER
XCOUT
P0
P7
0
0
to P0
to P7
7
, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0 to P67
,
LOW output
voltage
I
I
OL=5mA
2.0
V
V
V
OL
OL
7, P8
to P8
7
3
7, P10
0
to P10
to P6
to P10
7
7
LOW output P0
voltage P7
0
0
to P0
to P7
7, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
7
,
OL=200µA
0.45
V
7, P8
to P8
7
3
7, P10
0
I
I
OL=1mA
2.0
2.0
HIGHPOWER
LOWPOWER
X
OUT
VOL
LOW output voltage
LOW output voltage
V
V
OL=0.5mA
With no load applied
With no load applied
0
0
HIGHPOWER
LOWPOWER
XCOUT
TA0IN to TA4IN, TB0IN to TB2IN
INT to INT , NMI,
ADTRG, CTS to CTS
CLK to CLK ,TA2OUT to TA4OUT
KI to KI , RxD to RxD , SIN3, SIN4
RESET
,
Hysteresis
0
5
V
T+-
T+-
V
T-
T-
0.2
0.2
1.0
V
0
2, SCL, SDA,
0
2
,
0
3
0
2
V
V
Hysteresis
2.5
5.0
V
P0
P7
0
0
to P0
to P7
7
, P1
, P8
0
0
to P1
to P8
7
, P2
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0
to P6
0 to P107,
7,
HIGH input
current
I
IH
V
I
=5V
=0V
7
7, P9
3
7, P10
µA
XIN, RESET, CNVss
P0
P7
0
0
to P0
to P7
7
, P1
, P8
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
LOW input
current
VI
I
IL
7
7
3
7, P10
0
to P107,
-5.0
170
µA
XIN, RESET, CNVss
Pull-up
resistance
P0
P7
0
0
to P0
to P7
7
, P1
, P8
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
RPULLUP
VI=0V
30
50
kΩ
7
7
3
7, P10
0
to P10
7
R
fXIN
Feedback resistance
Feedback resistance
X
IN
1.5
15
MΩ
MΩ
RfXCIN
X
CIN
VRAM
RAM retention voltage
At stop mode
2.0
V
Note 1: Referenced to VCC=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified.
Rev.0.60 2004.02.01 page 289 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Table 18.9. Electrical Characteristics (2) (Note 1
)
Standard
Typ.
Symbol
Parameter
Measuring condition
Unit
mA
Min.
Max.
19
f(XIN)=20MHz,
No division
Flash memory
The output pins are open and
other pins are VSS
16
No division, Ring oscillation
f(BCLK)=10MHz,
1
mA
mA
Flash memory
Program
T.B.D
T.B.D
V
CC=5.0V
f(BCLK)=10MHz,
CC=5.0V
Flash memory
Erase
mA
µA
V
f(BCLK)=32kHz,
Low power dissipation mode,
RAM(Note 3)
Flash memory
25
Power supply current
(VCC=3.0 to 5.5V)
I
CC
f(BCLK)=32kHz
µA
Low power dissipation mode,
Flash memory(Note 3)
500
T.B.D
12
Ring oscillation,
Wait mode
µA
µA
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity High
Flash memory
f(BCLK)=32kHz,
Wait mode(Note 2),
Oscillation capacity Low
µA
µA
T.B.D
0.8
Stop mode,
3
Topr=25°C
T.B.D
T.B.D
µA
µA
µA
Idet4
Idet3
Idet2
Voltage down detection dissipation current (Note 4)
Reset area detection dissipation current (Note 4)
RAM retention limit detection dissipation current (Note 4)
T.B.D
T.B.D
T.B.D
T.B.D
Note 1: Referenced to VCC=3.0 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(XIN)=20MHz unless otherwise specified.
Note 2: With one timer operated using fC32
.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit of VCR2 register
Idet3: VC26 bit of VCR2 register
Idet2: VC25 bit of VCR2 register
Rev.0.60 2004.02.01 page 290 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Timing Requirements
o
o
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.10. External Clock Input (XIN input)
Standard
Symbol
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
Unit
Min.
50
Max.
t
c
ns
ns
ns
ns
ns
t
w(H
)
20
t
w(L)
20
t
r
9
9
t
f
External clock fall time
Rev.0.60 2004.02.01 page 291 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Timing Requirements
o
o
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.11. Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
40
Table 18.12. Timer A Input (Gating Input in Timer Mode)
Standard
Min. Max.
400
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.13. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.14. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.15. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN
)
t
h(TIN-UP)
400
Table 18.16. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
t
c(TA)
ns
ns
ns
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
t
su(TAIN-TAOUT
su(TAOUT-TAIN
)
)
t
Rev.0.60 2004.02.01 page 292 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Timing Requirements
o
o
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.17. Timer B Input (Counter Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
t
c(TB)
100
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
t
t
200
80
t
w(TBH)
tw(TBL)
80
Table 18.18. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.19. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.20. A-D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
t
c(AD)
w(ADL)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
Table 18.21. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
80
0
30
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 18.22. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
Rev.0.60 2004.02.01 page 293 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Timing Requirements
o
o
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
2
Table 18.23. Multi-master I C-Bus Line
Standard clock mode
High-speed clock mode
Symbol
Parameter
Unit
Min.
4.7
Max.
Min.
1.3
Max.
tBUF
µs
µs
µs
ns
µs
µs
Bus free time
tHD;STA
tLOW
The hold time in start condition
4.0
4.7
0.6
1.3
The hold time in SCL clock "0" status
SCL, SDA signals' rising time
Data hold time
tR
1000
300
300
0.9
20+0.1Cb
0
tHD;DAT
tHIGH
0
The hold time in SCL clock "1" status
4.0
0.6
tF
20+0.1Cb
100
ns
ns
µs
µs
SCL, SDA signals' falling time
Data setup time
300
t
SU;DAT
SU;STA
SU;STO
250
4.7
4.0
t
The setup time in restart condition
Stop condition setup time
0.6
t
0.6
Rev.0.60 2004.02.01 page 294 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
t
c(TA)
t
w(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
t
w(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
t
h(TIN–UP)
t
su(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
t
c(TA)
TAiIN input
t
su(TAIN-TAOUT)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
t
su(TAOUT-TAIN)
tc(TB)
t
w(TBH)
TBiIN input
t
w(TBL)
t
c(AD)
tw(ADL)
ADTRG input
Figure 18.1. Timing Diagram (1)
Rev.0.60 2004.02.01 page 295 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
t
h(C–D)
t
w(INL)
INTi input
tw(INH)
Figure 18.2. Timing Diagram (2)
VCC = 5V
SDA
t
HD:STA
tsu:STO
t
BUF
t
LOW
t
R
t
F
p
Sr
p
S
SCL
t
HD:STA
t
HD:DTA
t
HIGH
tsu:DAT
tsu:STA
Figure 18.3. Timing Diagram (3)
Rev.0.60 2004.02.01 page 296 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Table 18.24. Electrical Characteristics (Note 1)
Standard
Typ.
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
HIGH output
voltage
P0
P7
0
0
to P0
to P7
7
, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0
to P6
7,
V
V
OH
OH
V
V
CC
I
OH
=
-
1mA
V
CC
-
0.5
7, P8
to P8
7
3
7, P10
0
to P10
7
V
V
CC
CC
HIGHPOWER
V
V
CC-
0.5
0.5
I
I
OH=
-
-
0.1mA
50µA
V
X
OUT
HIGH output voltage
HIGH output voltage
LOWPOWER
OH=
CC-
With no load applied
With no load applied
2.5
1.6
HIGHPOWER
LOWPOWER
X
COUT
V
V
LOW output
voltage
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
V
V
OL
OL
I
OL=1mA
0.5
7, P8
to P8
7
3
7, P10
0
to P10
7
I
I
OL=0.1mA
OL=50µA
0.5
0.5
HIGHPOWER
LOWPOWER
X
OUT
LOW output voltage
LOW output voltage
V
V
With no load applied
With no load applied
0
0
HIGHPOWER
LOWPOWER
X
COUT
Hysteresis
TA0IN to TA4IN, TB0IN to TB2IN
INT to INT , NMI,
ADTRG, CTS to CTS
CLK to CLK , TA2OUT to TA4OUT
KI to KI , RxD
,
0
5
V
V
T+-
T+-
V
V
T-
T-
0
2, SCL, SDA,
0.2
0.2
0.8
V
0
2
,
0
3
0
to RxD
2
, SIN3,SIN4
Hysteresis
0.7
1.8
4.0
V
RESET
HIGH input
current
P0
P7
0
0
to P0
to P7
7
, P1
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0
to P6
7,
I
IH
V
I=3V
7, P8
7
3
7, P10
0
to P10
7
µA
X
IN, RESET, CNVss
LOW input
current
P0
P7
0
0
to P0
to P7
7
, P1
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0
to P6
7
,
I
IL
7, P8
to P8
7
3
7, P10
0
to P10
7
7
V
V
I
=0V
=0V
µA
-
4.0
X
IN, RESET, CNVss
R
PULLUP
Pull-up
resistance
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
I
50
100
500
kΩ
7, P8
7
3
7, P10
0
to P10
R
fXIN
Feedback resistance
Feedback resistance
RAM retention voltage
X
IN
CIN
3.0
25
MΩ
MΩ
V
RfXCIN
X
V
RAM
At stop mode
2.0
Note 1 : Referenced to VCC=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.
Rev.0.60 2004.02.01 page 297 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Table 18.25. Electrical Characteristics (2) (Note 1)
Standard
Typ.
Symbol
Parameter
Measuring condition
Unit
mA
Min.
Max.
T.B.D
f(BCLK)=10MHz,
No division
Flash memory
The output pins are open and
other pins are VSS
8
Flash memory
Program
f(BCLK)=10MHz,
Vcc=3.0V
T.B.D
T.B.D
mA
mA
Flash memory
Erase
f(BCLK)=10MHz,
Vcc=3.0V
f(BCLK)=32kHz,
Flash memory
µA
µA
Power supply current
(VCC=2.7 to 3.6V)
Low power dissipation mode,
RAM(Note 3)
T.B.D
T.B.D
I
CC
f(BCLK)=32kHz,
Low power dissipation mode,
Flash memory(Note 3)
Ring oscillation,
Wait mode
µA
µA
T.B.D
T.B.D
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity High
Flash memory
f(BCLK)=32kHz,
µA
µA
T.B.D
0.7
Wait mode (Note 2),
Oscillation capacity Low
Stop mode,
T.B.D
T
opr=25°C
Idet4
Idet3
Idet2
T.B.D
T.B.D
T.B.D
T.B.D
µA
µA
µA
Voltage down detection dissipation current (Note 4)
Reset level detection dissipation current (Note 4)
RAM retention limit detection dissipation current (Note 4)
T.B.D
T.B.D
Note 1: Referenced to VCC=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.
Note 2: With one timer operated using fC32
.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit of VCR2 register
Idet3: VC26 bit of VCR2 register
Idet2: VC25 bit of VCR2 register
Rev.0.60 2004.02.01 page 298 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Timing Requirements
o
o
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.26. External Clock Input (XIN input)
Standard
Symbol
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
Unit
Min.
100
40
Max.
t
c
ns
ns
ns
ns
ns
t
w(H)
t
w(L)
40
t
r
18
18
t
f
External clock fall time
Rev.0.60 2004.02.01 page 299 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Timing Requirements
o
o
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.27. Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
60
Table 18.28. Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
600
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
300
300
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.29. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.30. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.31. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN)
t
h(TIN-UP)
600
Table 18.32. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
t
c(TA)
µs
ns
ns
2
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
t
t
su(TAIN-TAOUT
)
)
500
500
su(TAOUT-TAIN
Rev.0.60 2004.02.01 page 300 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Timing Requirements
o
o
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 18.33. Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
60
60
t
t
300
120
120
t
w(TBH)
t
w(TBL)
Table 18.34. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.35. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.36. A-D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
t
c(AD)
w(ADL)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
Table 18.37. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
160
0
50
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 18.38. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
Rev.0.60 2004.02.01 page 301 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Timing Requirements
o
o
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
2
Table 18.39. Multi-master I C-Bus Line
Standard clock mode
High-speed clock mode
Symbol
Parameter
Unit
Min.
4.7
Max.
Min.
1.3
Max.
tBUF
µs
µs
µs
ns
µs
µs
Bus free time
tHD;STA
tLOW
The hold time in start condition
4.0
4.7
0.6
1.3
The hold time in SCL clock "0" status
SCL, SDA signals' rising time
Data hold time
tR
1000
300
300
0.9
20+0.1Cb
0
tHD;DAT
tHIGH
0
The hold time in SCL clock "1" status
4.0
0.6
tF
20+0.1Cb
100
ns
ns
µs
µs
SCL, SDA signals' falling time
Data setup time
300
t
SU;DAT
SU;STA
SU;STO
250
4.7
4.0
t
The setup time in restart condition
Stop condition setup time
0.6
t
0.6
Rev.0.60 2004.02.01 page 302 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
t
c(TA)
t
w(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
t
w(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
t
h(TIN–UP)
t
su(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
t
c(TA)
TAiIN input
t
su(TAIN-TAOUT)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
t
su(TAOUT-TAIN)
t
c(TB)
t
w(TBH)
TBiIN input
t
w(TBL)
t
c(AD)
t
w(ADL)
ADTRG input
Figure 18.4. Timing Diagram (1)
Rev.0.60 2004.02.01 page 303 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (Normal-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
th(C–D)
tw(INL)
INTi input
t
w(INH)
Figure 18.5. Timing Diagram (2)
VCC = 3V
SDA
t
HD:STA
tsu:STO
t
BUF
t
LOW
t
R
t
F
p
Sr
p
S
SCL
t
HD:STA
t
HD:DTA
t
HIGH
tsu:DAT
tsu:STA
Figure 18.6. Timing Diagram (3)
Rev.0.60 2004.02.01 page 304 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
18.2. T version
Table 18.40. Absolute Maximum Ratings
Symbol Parameter
Condition
Rated value
-0.3 to 6.5
Unit
V
VCC
Supply voltage
VCC=AVCC
AVCC
Analog supply voltage
VCC=AVCC
-0.3 to 6.5
V
Input
voltage
P0
P3
P8
0
0
0
to P0
to P3
to P8
7
7
7
, P1
, P6
, P9
0
0
0
to P1
to P6
to P9
7, P2
7, P7
3, P9
0
0
5
to P2
to P7
to P9
7,
7,
7,
V
I
V
V
-0.3 to VCC+0.3
-0.3 to VCC+0.3
P10
0 to P107,
XIN, VREF, RESET, CNVSS
Output
voltage
P0
P3
P8
0
0
0
to P0
to P3
to P8
7, P1
7, P6
7, P9
0
0
0
to P1
to P6
to P9
7, P2
7, P7
3, P9
0
0
5
to P2
to P7
to P9
7,
7,
7,
V
O
d
P100 to P107,
XOUT
P
Power dissipation
Topr=25
mW
C
C
300
T
T
opr
stg
Operating ambient temperature
Storage temperature
-40 to 85
-65 to 150
C
Rev.0.60 2004.02.01 page 305 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
Table 18.41. Recommended Operating Conditions (Note 1)
Standard
Typ.
Symbol
Parameter
Unit
Min.
3.0
Max.
5.5
V
CC
Supply voltage
V
AVcc
Vss
Analog supply voltage
Supply voltage
VCC
V
V
0
0
AVss
Analog supply voltage
V
HIGH input
voltage
P0
P7
0
0
to P0
to P7
7
, P1
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0
to P6
7,
V
IH
IL
V
0.7VCC
VCC
7, P8
7
3
7, P10
0
to P10
7
,
X
IN, RESET, CNVSS
LOW input
voltage
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
V
0
V
0.3VCC
7, P8
7
3
7, P10
0
to P10
7
7
,
X
IN, RESET, CNVSS
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
HIGH peak output
current
IOH (peak)
-10.0
-5.0
mA
mA
7, P8
7
3
7, P10
0
to P10
HIGH average
output current
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
IOH (avg)
7, P8
7
3
7, P10
0
to P10
7
7
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
LOW peak output
current
IOL (peak)
IOL (avg)
10.0
5.0
mA
mA
7, P8
7
3
7, P10
0
to P10
LOW average
output current
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
7, P8
7
3
7, P10
0
to P10
7
20
50
MHz
kHz
0
Main clock input oscillation frequency
Sub-clock oscillation frequency
(Note 3)
f (XIN
f (XCIN
)
)
32.768
1
2
MHz
MHz
MHz
f
f
f
1
(ROC)
(ROC)
(ROC)
Ring oscillation frequency 1
2
3
Ring oscillation frequency 2
Ring oscillation frequency 3
16
f (PLL)
PLL clock oscillation frequency (Note 3)
20
20
MHz
MHz
ms
10
0
f (BCLK)
CPU operation clock
V
V
CC=5.0V
CC=3.0V
T
SU(PLL)
PLL frequency synthesizer stabilization wait time
20
50
ms
Note 1: Referenced to VCC = 3.0 to 5.5V at Topr = -40 to 85 °C unless otherwise specified.
Note 2: The mean output current is the mean value within 100ms.
Note 3: Relationship between main clock oscillation frequency, PLL clock oscillation frequency and supply voltage.
Note 4: The total IOL(peak) for all ports must be 80mA max. The total IOH(peak) for all ports must be -80mA max.
PLL clock oscillation frequency
Main clock input oscillation frequency
20MHZ
20.0
20MHZ
20.0
10.0
0.0
10.0
0.0
2.7
3.0
5.5
3.0
5.5
VCC[V] (main clock: no division)
VCC[V] (PLL clock oscillation)
Rev.0.60 2004.02.01 page 306 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
Table 18.42. A-D Conversion Characteristics (Note 1)
Standard
Min. Typ. Max.
10
Symbol
Parameter
Resolution
Measuring condition
Unit
–
VREF =VCC
Bits
LSB
Integral non-
linearity
error
AN
AN00 to AN07, AN20 to AN27 input
AN to AN input
AN00 to AN07, AN20 to AN27 input
0 to AN7 input
±3
±7
±5
V
REF =VCC=5V
LSB
LSB
LSB
LSB
10 bit
8 bit
INL
0
7
V
V
V
REF =VCC=3.3V
±7
±2
REF =VCC=3.3V AN
0
to AN
7
input
AN
0
to AN
7
input
±3
LSB
LSB
Absolute
accuracy
REF =VCC=5V
AN00 to AN07, AN20 to AN27 input
AN to AN input
AN00 to AN07, AN20 to AN27 input
to AN input
±7
±5
10 bit
8 bit
–
0
7
LSB
LSB
LSB
LSB
V
REF =VCC=3.3V
±7
±2
±1
±3
±3
V
REF =VCC=3.3V AN
0
7
Differential non-linearity error
DNL
–
–
Offset error
LSB
LSB
kΩ
Gain error
Ladder resistance
10
40
RLADDER
V
V
REF =VCC
Conversion time(10bit),
Sample & hold function available
3.3
µs
t
CONV
REF =VCC=5V, øAD=10MHz
Conversion time(8bit),
Sample & hold function available
2.8
0.3
µs
V
REF =VCC=5V, øAD=10MHz
t
t
CONV
SAMP
Sampling time
µs
V
V
REF
IA
Reference voltage
Analog input voltage
2.0
0
V
CC
V
V
V
REF
Note 1: Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -40 to 85 °C unless otherwise specified.
Note 2: AD operation clock frequency (ØAD frequency) must be 10 MHz or less. And divide the fAD if VCC is less than 4.2V,
and make ØAD frequency equal to or lower than fAD/2.
Note 3: A case without sample & hold function turn ØAD frequency into 250 kHz or more in addition to a limit of Note 3.
A case with sample & hold function turn ØAD frequency into 1MHz or more in addition to a limit of Note 3.
Rev.0.60 2004.02.01 page 307 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
Table 18.43. Flash Memory Version Electrical Characteristics (Note 1) for 100 E/W cycle products
Standard
Parameter
Symbol
Unit
Min.
Typ.
(Note 2)
Max
Erase/Write cycle (Note 3)
100(Note 4)
cycle
µs
–
600
9
Word program time (Vcc=5.0V, Topr=25°C)
75
0.2
0.4
0.7
1.2
–
–
s
Block erase time
2Kbyte block
8Kbyte block
16Kbyte block
32Kbyte block
s
s
s
9
9
9
20
ms
Time delay from Suspend Request until Erase Suspend
Data retention time (Note 5)
td(SR-ES)
year
20
–
Table 18.44. Flash Memory Version Electrical Characteristics (Note 6) for 10000 E/W cycle products (Option)
[Block A and Block B (Note 7)]
Standard
Parameter
Symbol
Unit
Min.
Typ.
(Note 2)
Max
10000(Note 4,10)
cycle
µs
Erase/Write cycle (Note 3, 8, 9)
–
Word program time (Vcc=5.0V, Topr=25°C)
Block erase time(Vcc=5.0V, Topr=25°C)
(2Kbyte block)
100
0.3
–
–
9
s
20
ms
Time delay from Suspend Request until Erase Suspend
td(SR-ES)
Note 1: When not otherwise specified, Vcc = 2.7 to5.5V; Topr = 0 to 60 °C.
Note 2: VCC = 5V; TOPR = 25 °C.
Note 3: Definition of E/W cycle: Each block may be written to a variable number of times - up to a maximum of the total
number of distinct word addresses - for every block erase. Performing multiple writes to the same address before
an erase operation is prohibited.
Note 4: Maximum number of E/W cycles for which opration is guaranteed.
Note 5: Topr = 55°C.
Note 6: When not otherwise specified, Vcc = 2.7 to 5.5V; Topr = -40 to 85°C.
Note 7: Table18.44 applies for Block A or B E/W cycles > 1000. Otherwise, use Table 18.43.
Note 8: To reduce the number of E/W cycles, a block erase should ideally be performed after writing as many different
word addresses (only one time each) as possible. It is important to track the total number of block erases.
Note 9: Should erase error occur during block erase, attempt to execute clear status register command, then clock erase
command at least three times until erase error disappears.
Note 10: When Block A or B E/W cycles exceed 100 (Option), select one wait state per block access. When
FMR17 is set to "1", one wait state is inserted per access to Block A or B - regardless of the value of PM17. Wait
state insertion during access to all other blocks, as well as to internal RAM, is controlled by PM17 - regardless of
Erase suspend
request
(interrupt request)
FMR46
td(SR-ES)
Rev.0.60 2004.02.01 page 308 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
Table 18.45. Low Voltage Detection Circuit Electrical Characteristics (Note 1, Note 3
)
Standard
Typ.
Symbol
Parameter
Measuring condition
Unit
Max.
T.B.D
T.B.D
T.B.D
Min.
T.B.D
Voltage down detection voltage (Note 1)
Reset level detection voltage (Notes 1)
Low voltage reset retention voltage (Note 2)
Low voltage reset release voltage
Vdet4
Vdet3
T.B.D
T.B.D
T.B.D
V
V
T.B.D
T.B.D
T.B.D
V
CC=0.8 to 5.5V
V
V
Vdet3s
Vdet3r
T.B.D
T.B.D
Note 1: Vdet4 > Vdet3
Note 2: Vdet3s is the min voltage at which "hardware reset 2" is maintained. Below this voltage.
Note 3: The low voltage detection circuit is designed to use when VCC is set to 5V.
Table 18.46. Power Supply Circuit Timing Characteristics
Standard
Typ.
Symbol
Parameter
Measuring condition
Unit
Min.
T.B.D
Max.
2
Time for internal power supply stabilization during powering-on
Time for internal ring oscillator stabilization during powering-on
STOP release time (Note 2)
ms
ms
ms
µs
td(P-R)
td(ROC)
td(R-S)
td(W-S)
T.B.D
T.B.D
2
V
CC=3.0 to 5.5V
150
50
Low power dissipation mode wait mode release time (Note 2)
Time for internal power supply stabilization when main clock oscillation starts
Hardware reset 2 release wait time
td(M-L)
td(S-R)
td(E-A)
µs
VCC=Vdet3r to 5.5V
6 (Note 1)
20
20
ms
µs
V
CC=3.0 to 5.5V
Low voltage detection circuit operation start time (Note 3)
Note 1: When VCC = 5V
Note 2: This is the time between interrupt for (STOP/WAIT) mode release and resumption of CPU clock operation.
Note 3: After enabling low voltage detection, this time is required before proper detection can occur.
Vdet3r
VCC
CPU clock
td(S-R)
Interrupt for
stop mode
release
CPU clock
td(R-S)
Rev.0.60 2004.02.01 page 309 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Table 18.47. Electrical Characteristics (Note 1
)
Standard
Typ.
Symbol
Parameter
Measuring condition
Unit
Min.
Max.
HIGH output P0
voltage P7
0
0
to P0
to P7
7
7
, P1
, P8
0
0
to P1
to P8
7
7
, P2
, P9
0
0
to P2
to P9
7
3
, P3
, P9
0
5
to P3
to P9
7
7
, P6
, P10
0
to P6
7,
V
OH
OH
I
OH=-5mA
V
CC-2.0
CC-0.3
V
CC
CC
V
V
0
to P10
7
7
HIGH output P0
voltage P7
0
0
to P0
to P7
7
7
, P1
, P8
0
0
to P1
to P8
7
7
, P2
, P9
0
0
to P2
to P9
7
3
, P3
, P9
0
5
to P3
to P9
7
7
, P6
, P10
0
to P6
7
,
V
V
V
IOH=-200µA
0
to P10
HIGHPOWER
I
OH=-1mA
V
V
CC-2.0
CC-2.0
V
V
CC
CC
X
X
OUT
V
V
HIGH output voltage
HIGH output voltage
LOWPOWER
IOH=-0.5mA
V
OH
With no load applied
With no load applied
2.5
1.6
HIGHPOWER
LOWPOWER
COUT
LOW output P0
0
to P0
to P7
7
7
, P1
, P8
0
0
to P1
to P8
7
7
, P2
, P9
0
0
to P2
to P9
7
3
, P3
, P9
0
5
to P3
to P9
7
7
, P6
, P10
0 to P67
,
2.0
V
V
V
OL
OL
IOL=5mA
voltage
P7
0
0
to P10
to P6
to P10
7
LOW output
voltage
P0
P7
0
0
to P0
to P7
7
7
, P1
, P8
0
0
to P1
to P8
7
7
, P2
, P9
0
0
to P2
to P9
7
3
, P3
, P9
0
5
to P3
to P9
7
7
, P6
, P10
0
7
,
I
OL=200µA
OL=1mA
OL=0.5mA
0.45
V
0
7
I
2.0
2.0
HIGHPOWER
LOWPOWER
LOW output voltage
LOW output voltage
V
OL
X
OUT
V
V
I
With no load applied
With no load applied
0
0
HIGHPOWER
LOWPOWER
X
COUT
TA0IN to TA4IN, TB0IN to TB2IN
INT to INT , NMI,
ADTRG, CTS to CTS
CLK to CLK ,TA2OUT to TA4OUT
KI to KI , RxD to RxD , SIN3, SIN4
RESET
,
Hysteresis
0
5
V
T+-
V
T-
T-
1.0
V
0.2
0.2
0
2, SCL, SDA,
0
2
,
0
3
0
2
V
T+-
V
Hysteresis
2.5
5.0
V
P0
P7
0
0
to P0
to P7
7
7
, P1
, P8
0
0
to P1
to P8
7
7
, P2
, P9
0
0
to P2
to P9
7
3
, P3
, P9
0
5
to P3
to P9
7
7
, P6
, P10
0
to P6
7,
HIGH input
current
I
IH
0
to P107,
V
V
I
I
=5V
=0V
µA
X
IN, RESET, CNVss
P0
P7
0
0
to P0
to P7
7
7
, P1
, P8
0
0
to P1
to P8
7
7
, P2
, P9
0
0
to P2
to P9
7
3
, P3
, P9
0
5
to P3
to P9
7
7
, P6
, P10
0 to P67,
LOW input
current
I
IL
0
to P107,
-5.0
170
µA
X
IN, RESET, CNVss
Pull-up
resistance
P0
P7
0
0
to P0
to P7
7
7
, P1
, P8
0
0
to P1
to P8
7
7
, P2
, P9
0
0
to P2
to P9
7
3
, P3
, P9
0
5
to P3
to P9
7
7
, P6
, P10
0
to P67,
R
PULLUP
VI=0V
30
50
1.5
15
k
M
M
V
0
to P107
R
fXIN
Feedback resistance
Feedback resistance
RAM retention voltage
X
IN
CIN
R
fXCIN
X
V
RAM
2.0
At stop mode
Note 1: Referenced to VCC=4.2 to 5.5V, VSS=0V at Topr = -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified.
Rev.0.60 2004.02.01 page 310 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Table 18.48. Electrical Characteristics (2) (Note 1
)
Standard
Typ.
Symbol
Parameter
Measuring condition
Unit
mA
Min.
Max.
19
f(XIN)=20MHz,
No division
Flash memory
The output pins are open and
other pins are VSS
16
No division, Ring oscillation
f(BCLK)=10MHz,
1
mA
mA
Flash memory
Program
T.B.D
T.B.D
V
CC1=5.0V
f(BCLK)=10MHz,
CC1=5.0V
Flash memory
Erase
mA
µA
V
f(BCLK)=32kHz,
Low power dissipation mode,
RAM(Note 3)
Flash memory
25
Power supply current
(VCC=3.0 to 5.5V)
I
CC
f(BCLK)=32kHz
µA
Low power dissipation mode,
Flash memory(Note 3)
500
T.B.D
12
Ring oscillation,
Wait mode
µA
µA
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity High
Flash memory
f(BCLK)=32kHz,
Wait mode(Note 2),
Oscillation capacity Low
µA
µA
T.B.D
0.8
Stop mode,
3
Topr=25°C
T.B.D
T.B.D
µA
µA
µA
Idet4
Idet3
Idet2
Voltage down detection dissipation current (Note 4)
Reset area detection dissipation current (Note 4)
RAM retention limit detection dissipation current (Note 4)
T.B.D
T.B.D
T.B.D
T.B.D
Note 1: Referenced to VCC=3.0 to 5.5V, VSS=0V at Topr = -40 to 85 °C, f(XIN)=20MHz unless otherwise specified.
Note 2: With one timer operated using fC32
.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit of VCR2 register
Idet3: VC26 bit of VCR2 register
Idet2: VC25 bit of VCR2 register
Rev.0.60 2004.02.01 page 311 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Timing Requirements
o
(VCC = 5V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.49. External Clock Input (XIN input)
Standard
Min. Max.
50
20
20
Symbol
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
Unit
t
c
ns
ns
ns
ns
ns
t
w(H
)
t
w(L)
t
r
9
9
t
f
External clock fall time
Rev.0.60 2004.02.01 page 312 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Timing Requirements
o
(VCC = 5V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.50. Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
40
Table 18.51. Timer A Input (Gating Input in Timer Mode)
Standard
Min. Max.
400
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.52. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.53. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.54. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN
)
t
h(TIN-UP)
400
Table 18.55. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
t
c(TA)
ns
ns
ns
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
t
su(TAIN-TAOUT
su(TAOUT-TAIN
)
)
t
Rev.0.60 2004.02.01 page 313 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Timing Requirements
o
(VCC = 5V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.56. Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
t
t
200
80
t
w(TBH)
t
w(TBL)
80
Table 18.57. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.58. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.59. A-D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 18.60. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
80
0
30
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 18.61. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
Rev.0.60 2004.02.01 page 314 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
Timing Requirements
o
(VCC = 5V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
2
Table 18.62. Multi-master I C-Bus Line
Standard clock mode
High-speed clock mode
Symbol
Parameter
Unit
Min.
4.7
Max.
Min.
1.3
Max.
tBUF
µs
µs
µs
ns
µs
µs
Bus free time
tHD;STA
tLOW
The hold time in start condition
4.0
4.7
0.6
1.3
The hold time in SCL clock "0" status
SCL, SDA signals' rising time
Data hold time
tR
1000
300
300
0.9
20+0.1Cb
0
tHD;DAT
tHIGH
0
The hold time in SCL clock "1" status
4.0
0.6
tF
20+0.1Cb
100
ns
ns
µs
µs
SCL, SDA signals' falling time
Data setup time
300
t
SU;DAT
SU;STA
SU;STO
250
4.7
4.0
t
The setup time in restart condition
Stop condition setup time
0.6
t
0.6
Rev.0.60 2004.02.01 page 315 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
t
c(TA)
t
w(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
t
w(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
th(TIN–UP)
t
su(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
t
c(TA)
TAiIN input
t
su(TAIN-TAOUT)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
t
su(TAOUT-TAIN)
t
c(TB)
t
w(TBH)
TBiIN input
tw(TBL)
t
c(AD)
t
w(ADL)
ADTRG input
Figure 18.7. Timing Diagram (1)
Rev.0.60 2004.02.01 page 316 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
RxDi
tsu(D–C)
td(C–Q)
t
h(C–D)
tw(INL)
INTi input
t
w(INH)
Figure 18.8. Timing Diagram (2)
VCC = 5V
SDA
t
HD:STA
tsu:STO
t
BUF
t
LOW
t
R
t
F
p
Sr
p
S
SCL
t
HD:STA
t
HD:DTA
t
HIGH
tsu:DAT
tsu:STA
Figure 18.9. Timing Diagram (3)
Rev.0.60 2004.02.01 page 317 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Table 18.63. Electrical Characteristics (Note)
Standard
Typ.
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
HIGH output
voltage
P0
P7
0
0
to P0
to P7
7
, P1
, P8
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0
to P6
7,
V
V
OH
OH
V
V
CC
I
OH
=
-
1mA
V
CC
-
0.5
7
to P8
7
3
7, P10
0
to P10
7
V
V
CC
CC
HIGHPOWER
LOWPOWER
V
V
CC-
0.5
0.5
I
I
OH=
-
-
0.1mA
50µA
V
X
OUT
HIGH output voltage
HIGH output voltage
OH=
CC-
With no load applied
With no load applied
2.5
1.6
HIGHPOWER
LOWPOWER
X
COUT
V
V
LOW output
voltage
P0
P7
0
0
to P0
to P7
7
, P1
, P8
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
V
V
OL
OL
I
OL=1mA
0.5
7
to P8
7
3
7, P10
0
to P10
7
I
I
OL=0.1mA
OL=50µA
0.5
0.5
HIGHPOWER
LOWPOWER
X
OUT
LOW output voltage
LOW output voltage
V
V
With no load applied
With no load applied
0
0
HIGHPOWER
LOWPOWER
X
COUT
Hysteresis
TA0IN to TA4IN, TB0IN to TB2IN
INT to INT , NMI,
ADTRG, CTS to CTS
CLK to CLK , TA2OUT to TA4OUT
KI to KI , RxD
,
0
5
V
V
T+-
T+-
V
V
T-
T-
0
2, SCL, SDA,
0.2
0.2
0.8
V
0
2
,
0
3
0
to RxD
2
, SIN3,SIN4
Hysteresis
0.7
1.8
4.0
V
RESET
HIGH input
current
P0
P7
0
0
to P0
to P7
7
, P1
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0
to P6
7,
I
IH
V
I=3V
7, P8
7
3
7, P10
0
to P10
7
µA
X
IN, RESET, CNVss
LOW input
current
P0
P7
0
0
to P0
to P7
7
, P1
, P8
0
0
to P1
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7
, P6
0
to P6
7
,
I
IL
7
to P8
7
3
7, P10
0
to P10
7
7
V
V
I
=0V
=0V
µA
-
4.0
X
IN, RESET, CNVss
R
PULLUP
Pull-up
resistance
P0
P7
0
0
to P0
to P7
7, P1
0
0
to P1
to P8
7
, P2
, P9
0
0
to P2
to P9
7
, P3
, P9
0
5
to P3
to P9
7, P6
0
to P6
7,
I
50
100
500
kΩ
7, P8
7
3
7, P10
0
to P10
R
fXIN
Feedback resistance
Feedback resistance
RAM retention voltage
X
IN
CIN
3.0
25
MΩ
MΩ
V
RfXCIN
X
V
RAM
At stop mode
2.0
Note 1 : Referenced to VCC=3.0 to 3.3V, VSS=0V at Topr = -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified.
Rev.0.60 2004.02.01 page 318 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Table 18.64. Electrical Characteristics (2) (Note 1)
Standard
Typ.
Symbol
Parameter
Measuring condition
Unit
mA
Min.
Max.
T.B.D
f(BCLK)=10MHz,
No division
Flash memory
The output pins are open and
other pins are VSS
8
Flash memory
Program
f(BCLK)=10MHz,
Vcc=3.0V
T.B.D
T.B.D
mA
mA
Flash memory
Erase
f(BCLK)=10MHz,
Vcc=3.0V
f(BCLK)=32kHz,
Flash memory
µA
µA
Power supply current
(VCC=2.7 to 3.6V)
Low power dissipation mode,
RAM(Note 3)
T.B.D
T.B.D
I
CC
f(BCLK)=32kHz,
Low power dissipation mode,
Flash memory(Note 3)
Ring oscillation,
Wait mode
µA
µA
T.B.D
T.B.D
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity High
Flash memory
f(BCLK)=32kHz,
µA
µA
T.B.D
0.7
Wait mode (Note 2),
Oscillation capacity Low
Stop mode,
T.B.D
T
opr=25°C
Idet4
Idet3
Idet2
T.B.D
T.B.D
T.B.D
T.B.D
µA
µA
µA
Voltage down detection dissipation current (Note 4)
Reset level detection dissipation current (Note 4)
RAM retention limit detection dissipation current (Note 4)
T.B.D
T.B.D
Note 1: Referenced to VCC=3.0 to 3.3V, VSS=0V at Topr = -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified.
Note 2: With one timer operated using fC32
.
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit of VCR2 register
Idet3: VC26 bit of VCR2 register
Idet2: VC25 bit of VCR2 register
Rev.0.60 2004.02.01 page 319 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
Timing Requirements
o
(VCC = 3V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.65. External Clock Input (XIN input)
Standard
Symbol
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
Unit
Min.
100
40
Max.
t
c
ns
ns
ns
ns
ns
t
w(H)
t
w(L)
40
t
r
18
18
t
f
External clock fall time
Rev.0.60 2004.02.01 page 320 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Timing Requirements
o
(VCC = 3V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.66. Timer A Input (Counter Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
150
60
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
60
Table 18.67. Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
600
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
300
300
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.68. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.69. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 18.70. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN)
t
h(TIN-UP)
600
Table 18.71. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
t
c(TA)
µs
ns
ns
2
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
t
t
su(TAIN-TAOUT
)
)
500
500
su(TAOUT-TAIN
Rev.0.60 2004.02.01 page 321 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Timing Requirements
o
(VCC = 3V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
Table 18.72. Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
60
60
t
t
300
120
120
t
w(TBH)
t
w(TBL)
Table 18.73. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.74. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 18.75. A-D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 18.76. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
160
0
50
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 18.77. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
Rev.0.60 2004.02.01 page 322 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
Timing Requirements
o
(VCC = 3V, VSS = 0V, at Topr = – 40 to 85 C unless otherwise specified)
2
Table 18.78. Multi-master I C-Bus Line
Standard clock mode
High-speed clock mode
Symbol
Parameter
Unit
Min.
4.7
Max.
Min.
1.3
Max.
tBUF
µs
µs
µs
ns
µs
µs
Bus free time
tHD;STA
tLOW
The hold time in start condition
4.0
4.7
0.6
1.3
The hold time in SCL clock "0" status
SCL, SDA signals' rising time
Data hold time
tR
1000
300
300
0.9
20+0.1Cb
0
tHD;DAT
tHIGH
0
The hold time in SCL clock "1" status
4.0
0.6
tF
20+0.1Cb
100
ns
ns
µs
µs
SCL, SDA signals' falling time
Data setup time
300
t
SU;DAT
SU;STA
SU;STO
250
4.7
4.0
t
The setup time in restart condition
Stop condition setup time
0.6
t
0.6
Rev.0.60 2004.02.01 page 323 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
t
c(TA)
t
w(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
t
w(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
t
h(TIN–UP)
t
su(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
t
c(TA)
TAiIN input
t
su(TAIN-TAOUT)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
t
su(TAOUT-TAIN)
t
c(TB)
t
w(TBH)
TBiIN input
t
w(TBL)
t
c(AD)
t
w(ADL)
ADTRG input
Figure 18.10. Timing Diagram (1)
Rev.0.60 2004.02.01 page 324 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
18. Electrical Characteristics (T-version)
These standards are not final and focused only normal-version.
Should be used as a reference.
VCC = 3V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
t
h(C–Q)
TxDi
RxDi
tsu(D–C)
td(C–Q)
t
h(C–D)
t
w(INL)
INTi input
tw(INH)
Figure 18.11. Timing Diagram (2)
VCC = 3V
SDA
t
HD:STA
tsu:STO
t
BUF
t
LOW
t
R
t
F
p
Sr
p
S
SCL
t
HD:STA
t
HD:DTA
t
HIGH
tsu:DAT
tsu:STA
Figure 18.12. Timing Diagram (3)
Rev.0.60 2004.02.01 page 325 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
19. Flash Memory Version
19.1 Flash Memory Performance
The flash memory version is functionally the same as the mask ROM version except that it internally con-
tains flash memory.
In the flash memory version, the flash memory can perform in three mode : CPU rewrite mode, standard
serial I/O mode and parallel I/O mode.
Table 19.1 shows the flash memory version specifications. (Refer to “Table 1.2.1 Performance Outline of
M16C/28 Group (80-pin device)” for the items not listed in Table 19.1.” or “Table 1.2.2 Performance Outline
of M16C/28 Group (64-pin device)”).
Table 19.1. Flash Memory Version Specifications
Item
Specification
Flash memory operating mode
3 modes (CPU rewrite, standard serial I/O, parallel I/O)
Erase block
See Figure 19.2.1 to19.2.3 Flash Memory Block Diagram
In units of word
Program method
Block erase
Erase method
Program, erase control method
Program and erase controlled by software command
All user blocks are write protected by bit FMR16.
In addition, the block 0 and block 1 are write protected by bit FMR02.
Protect method
Number of commands
5 commands
Block 0 to 4 (program area)
100 times 1,000 times (Option)
100 times 10,000 times (Option)
Program/Erase
Endurance(Note1)
Block A and B (data are) (Note2)
10 years
Data Retention
Parallel I/O and standard serial I/O modes are supported.
ROM code protection
Note 1: Program and erase endurance definition
Program and erase endurance are the erase endurance of each block. If the program and erase endurance are
n times (n=100,1,000,10,000), each block can be erased n times. For example, if a 2-Kbyte block A is erased
after writing 1 word data 1024 times, each to different addresses, this is counted as one program and erasure.
However, data cannot be written to the same address more than once without erasing the block. (Rewrite
disabled)
Note 2: To use the limited number of erasure efficiently, write to unused address within the block instead of rewrite.
Erase block only after all possible address are used. For example, an 8-word program can be written 128 times
before erase is necessary. Maintaining an equal number of erasure between Block A and B will also improve
efficiency. We recommend keeping track of the number of times erasure is used.
Rev.0.60 2004.02.01 page 326 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
Parallel I/O mode
Table 19.2. Flash Memory Rewrite Modes Overview
Flash memory
rewrite mode
Function
CPU rewrite mode
Standard serial I/O mode
The user ROM area is rewrit-
ten when the CPU executes
software command.
EW0 mode:
Rewrite in area other than
flash memory
The user ROM area is rewrit- The user ROM areas are re-
ten using a dedicated serial written using a dedicated
programmer.
parallel programmer.
Standard serial I/O mode 1:
Clock synchronous serial
I/O
Standard serial I/O mode 2:
UART
EW1 mode:
Rewrite in flash memory
Areas which User ROM area
can be rewritten
User ROM area
Boot mode
User ROM area
Operation
mode
Single chip mode
Parallel I/O mode
ROM
None
Serial programmer
Parallel programmer
programmer
Rev.0.60 2004.02.01 page 327 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
19.2 Memory Map
The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 19.2.1 to
19.2.3 show the flash memory block diagram. The user ROM area has space to store the microcomputer
operation program in single-chip mode and a separate 2-Kbyte space as the block A and B.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite,
standard serial input/output, and parallel input/output modes. However, if block 0 and 1 are rewritten in
CPU rewrite mode, setting the FMR02 bit in the FMR0 register to “1” (block 0, 1 rewrite enabled) and the
FMR16 bit in the FMR1 register to “1”(blocks 0 to 4 rewrite enabled) enable rewriting. Also, if blocks 2 to 4
are rewritten in CPU rewrite mode, setting the FMR16 bit in the FMR1 register to “1” (blocks 0 to 4 rewrite
enabled) enables writing. Setting the PM10 bit in the PM1 register to “1”(data area access enabled) for
block A and B enables to use.
00F00016
Block B :2K bytes (Note 2)
00F7FF16
00F80016
Block A :2K bytes (Note 2)
00FFFF16
0F400016
Note 1: To specify a block, use the maximum even address in the block.
Note 2: Blocks A and B are enabled for use when the PM10 bit in the
PM1 register is set to "1".
Block 3 : 16K bytes (Note 5)
Note 3: Blocks 0 and 1 are enabled for programs and erasure when the
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
Note 4: The Boot ROM area is reserved. Do not access.
Note 5: Blocks 2 and 3 are enabled for programs and erasure when the
FMR16 bit in the FMR1 register is set to "1". (CPU rewrite mode
only)
0F7FFF16
0F800016
Block 2 : 16K bytes (Note 5)
Block 1 : 8K bytes (Note 3)
0FBFFF16
0FC00016
0FDFFF16
0FE00016
0FF00016
4K bytes (Note 4)
0FFFFF16
Block 0 : 8K bytes (Note 3)
User ROM area
0FFFFF16
Boot ROM area
Figure 19.2.1. Flash Memory Block Diagram (ROM capacity 48K byte)
Rev.0.60 2004.02.01 page 328 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
The M16C/28 (flash memory version) contains the flash memory that can be rewritten with a single voltage.
For this flash memory, three flash memory modes area available in which to read, program, and erase:
parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a program-
mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit
(CPU). Each mode is detailed in the follwing sections.
The flash memory is divided into several blocks as shown in Figures 19.2.1 to 19.2.3, so that memory can
be erased one block at time.
In addition to the user ROM area to store a microcomputer operation control program, the flash memory
has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial
I/O mode. This boot ROM area has a standard serial I/O mode control program stored in it when shipped
from the factory, which can be rewritten with a rewrite control program, to suit the user's application system.
When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut
off. It is reconnected automatically when CPU operation is restored.
00F00016
Block B :2K bytes (Note 2)
00F7FF16
00F80016
Block A :2K bytes (Note 2)
00FFFF16
0F000016
Note 1: To specify a block, use the maximum even address in the block.
Block 3 : 32K bytes (Note 5)
Note 2: Blocks A and B are enabled for use when the PM10 bit in the
PM1 register is set to "1".
Note 3: Blocks 0 and 1 are enabled for programs and erasure when the
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
Note 4: The Boot ROM area is reserved. Do not access.
Note 5: Blocks 2 and 3 are enabled for programs and erasure when the
FMR16 bit in the FMR1 register is set to "1". (CPU rewrite mode
only)
0F7FFF16
0F800016
Block 2 : 16K bytes (Note 5)
0FBFFF16
0FC00016
Block 1 : 8K bytes (Note 3)
0FDFFF16
0FE00016
0FF00016
4K bytes (Note 4)
0FFFFF16
Block 0 : 8K bytes (Note 3)
User ROM area
0FFFFF16
Boot ROM area
Figure 19.2.2. Flash Memory Block Diagram (ROM capacity 64K byte)
Rev.0.60 2004.02.01 page 329 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
00F00016
Block B :2K bytes (Note 2)
Block A :2K bytes (Note 2)
00F7FF16
00F80016
00FFFF16
0E800016
Block 4 : 32K bytes (Note 5)
0EFFFF16
0F000016
Block 3 : 32K bytes (Note 5)
Note 1: To specify a block, use the maximum even address in the block.
Note 2: Blocks A and B are enabled for use when the PM10 bit in the
PM1 register is set to "1".
Note 3: Blocks 0 and 1 are enabled for programs and erasure when the
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
Note 4: The Boot ROM area is reserved. Do not access.
Note 5: Blocks 2 to 4 are enabled for programs and erasure when the
FMR16 bit in the FMR1 register is set to "1". (CPU rewrite mode
only)
0F7FFF16
0F800016
Block 2 : 16K bytes (Note 5)
0FBFFF16
0FC00016
Block 1 : 8K bytes (Note 3)
0FDFFF16
0FE00016
0FF00016
Block 0 : 8K bytes (Note 3)
User ROM area
4K bytes (Note 4)
0FFFFF16
0FFFFF16
Boot ROM area
Figure 19.2.3. Flash Memory Block Diagram (ROM capacity 96K byte)
Rev.0.60 2004.02.01 page 330 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
19.3 Functions To Prevent Flash Memory from Rewriting
The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code
check function for standard input/output mode to prevent the flash memory from reading or rewriting.
19.3.1 ROM Code Protect Function
The ROM code protect function prevents the flash memory from reading and rewriting in parallel input/
output mode. Figure 19.3.1.1 shows the ROMCP register. The ROMCP register is located in the user
ROM area. The ROMCP1 bit consists of two bits. The ROM code protect function is enabled and reading
and rewriting flash memory is disabled when setting either or both of two ROMCP1 bits to “0” other than
the ROMCR bit is ‘002’. However, when setting the ROMCR bit to ‘002’, the flash memory can be read or
rewritten. Once the ROM code protect function is enabled, the ROMCR bits can not be changed in paral-
lel input/output mode. Therefore, use the standard serial input/output or other modes to rewrite the flash
memory.
19.3.2 ID Code Check Function
Use the ID code check function in standard serial input/output mode. Unless the flash memory is blank,
the ID codes sent from the programmer and the seven bytes ID codes written in the flash memory are
compared to see if they match. If the ID codes do not match, the commands sent from the programmer
are not acknowledged. The ID code consists of 8-bit data, starting with the first byte, into addresses,
0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. The flash memory
has a program with the ID code set in these addresses.
Rev.0.60 2004.02.01 page 331 of N
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M16C/28 Group
19. Flash Memory Version
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ROMCP
Address
0FFFFF16
Factory Setting
FF16 (Note 4)
1
1
1
1
RW
Bit symbol
Bit name
Function
Set this bit to “1”
RW
RW
Reserved bit
Set this bit to “1”
Set this bit to “1”
Reserved bit
Reserved bit
RW
RW
Set this bit to “1”
Reserved bit
b5 b4
ROM code protect reset
bit (Note 2, Note 4)
ROMCR
RW
RW
RW
00: Disables protect
01:
Enables ROMCP1 bit
10:
11:
}
b7 b6
00:
01:
10:
ROM code protect level
1 set bit
(Note 1, Note 3, Note 4)
ROMCP1
Enables protect
}
RW
11: Disables protect
Note 1: When the ROMCR bits are set to other than ‘00
2’ and the ROMCP1 bits are set to other than
‘11 ’ (ROM code protect enabled), the flash memory is disabled against reading and rewriting in
2
parallel input/output mode.
Note 2: When the ROMCR bits are set to ‘002’, the ROM code protect level 1 is reset. Because the
ROMCR bits can not be modified in parallel input/output mode, modify in standard serial input/
output mode.
Note 3: The ROMCP1 bits are valid when the ROMCR bits are ‘012’, ‘102’ or ‘112’.
Note 4: This bit can not be set to “1” once it is set to “0”. The ROMCP register is set to ‘FF16’ when a
block, including the ROMCP register, is erased.
Figure 19.3.1.1. ROMCP Register
Address
Undefined instruction vector
Overflow vector
ID1
ID2
0FFFDF16 to 0FFFDC16
0FFFE316 to 0FFFE016
0FFFE716 to 0FFFE416
0FFFEB16 to 0FFFE816
0FFFEF16 to 0FFFEC16
0FFFF316 to 0FFFF016
0FFFF716 to 0FFFF416
0FFFFB16 to 0FFFF816
0FFFFF16 to 0FFFFC16
BRK instruction vector
Address match vector
ID3
ID4
Single step vector
Watchdog timer vector
DBC vector
ID5
ID6
ID7
NMI vector
Reset vector
ROMCP
4 bytes
Figure 19.3.2.1. Address for ID Code Stored
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
19.4 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. In
CPU rewrite mode, only the user ROM area shown in Figure 19.2.1 to 19.2.3 can be rewritten and the boot
ROM area cannot be rewritten. Verify the Program and the Block Erase commands are executed only on
blocks in the user ROM area. Therefore, the user ROM area can be rewritten directly while the microcom-
puter is mounted on-board without using a ROM programmer, etc.
For interrupts requested during an erasing operation in CPU rewrite mode, the M16C/28 flash module
offers an erase-suspend function which the erasing operation to be suspended, and access made available
to the flash. Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU rewrite mode.
Table 19.4.1 shows the differences between erase-write 0 (EW0) and erase-write 1 (EW1) modes. 1 wait is
required for the CPU erase-write control.
Table 19.4.1. EW0 Mode and EW1 Mode
Item
EW0 mode
Single chip mode
User ROM area
EW1 mode(Note 2)
Single chip mode
User ROM area
Operation mode
Areas in which a
rewrite control
program can be located
Areas where
rewrite control
program can be
executed
The rewrite control program must be The rewrite control program can be
transferred to any other than the flash excuted in the user ROM area
memory (e.g., RAM) before being
executed
Areas which can be
rewritten
User ROM area
User ROM area
However, this excludes blocks with the
rewrite control program
Software command
Restrictions
None
• Program, block erase command
Cannot be executed in a block having
the rewite control program
• Read Status Register command
Cannot be executed
Mode after programming Read Status Register mode
or erasing
Read Array mode
CPU state during auto-
write and auto-erase
Operating
Hold state (I/O ports retain the state
before the command is excuted
(Note 1)
Flash memory status
detection(Note 2)
• Read the FMR0 register's FMR00, Read the FMR0 register's FMR00,
FMR06, and FMR07 bits in the
FMR0 register by program
• Execute the read status register
command to read the SR7, SR5,
and SR4 bits.
FMR06, and FMR07 bits in a program
Condition for transferring
Set the FMR40 and FMR41 bits in
The FMR40 bit in the FMR4 register is
to erase-suspend(Note 3) the FMR4 register to "1" by program. set to "1" and the interruput request of
Note 1: Do not generate a DMA transfer.
Note 2: Block 1 and Block 0 are enabled for rewrite by setting FMR02 bit in the FMR0 register to "1" and
setting FMR16 bit in the FMR1 register to "1". Block 2 to Block 4 are enabled for rewrite by
setting FMR16 bit in the FMR1 register to "1".
Note 3: The time, until entering erase suspend and reading flash is enabled, is maximum td(SR-ES) after
satisfying the conditions
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M16C/28 Group
19. Flash Memory Version
19.4.1 EW0 Mode
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU
rewrite mode enabled) and is ready to acknowledge the software commands. EW0 mode is selected by
setting the FMR11 bit in the FMR1 register to “0”. When setting the FMR01 bit to “1”, set to “1” after first
writing “0”. The software commands control programming and erasing. The FMR0 register or the status
register indicates whether a programming or erasing operations is completed. When entering the erase-
suspend during the auto-erasing, set the FMR40 bit to “1” (erase-suspend enabled) and the FMR41 bit to
“1” (suspend request). And wait for td(SR-ES). After verifying the FMR46 bit is set to “1” (auto-erase
stop), access to the user ROM area. When setting the FMR41 bit to “0” (erase restart), auto-erasing is
restarted.
19.4.2 EW1 Mode
EW1 mode is selected by setting the FMR11 bit to “1” after the FMR01 bit is set to “1”. (set to “1” after first
writing “0”). The FMR0 register indicates whether or not a programming or an erasing operation is com-
pleted. Do not execute the software commands of read status register in EW1 mode. When enabling an
erase suspend function, set the FMR40 bit to “1” (erase suspend enabled) and execute block erase
commands. Also, preliminarily set an interrupt to enter the erase-suspend to an interrupt enabled status.
After td(SR-ES) from an interrupt request and entering erase suspend, an interrupt can be acknowl-
edged. When an interrupt request is generated, the FMR41 bit is automatically set to “1” (suspend re-
quest) and an auto-erasing is halted. If an auto-erasing is not completed (the FMR00 bit is “0”) after an
interrupt process completed, set the FMR41 bit to “0” (erase restart) and execute block erase commands
again.
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M16C/28 Group
19. Flash Memory Version
19.5 Register Description
Figure 19.5.1 shows the flash memory control register 0 and flash memory control register 1. Figure 19.5.2
shows the flash memory control register 4.
19.5.1 Flash memory control register 0 (FMR0):
•FMR 00 Bit
This bit indicates the operation status of the flash memory. The bit is “0” during programming, erasing,
or erase-suspend mode; otherwise, the bit is “1”.
•FMR01 Bit
The microcomputer enables to acknowledge commands by setting the FMR01 bit to “1” (CPU rewrite
mode). To set this bit to “1”, it is necessary to set to “0” after first setting to “1”. To set this bit to “0” by
only writing “0”.
•FMR02 Bit
The combined setting of the FMR02 bit and the FMR16 bit enable to program and erase in the user
ROM area. See Table 19.5.2.1 for setting details. To set this bit to “1”, it is necessary to set to “0” after
first setting to “1”. To set this bit to “0” by only writing “0”. This bit is enabled only when the FMR01 bit
is “1” (CPU rewrite mode enable).
•FMSTP Bit
This bit resets the flash memory control circuits and minimizes power consumption in the flash
memory. Access to the flash memory is disabled when the FMSTP bit is set to “1”. Set the FMSTP bit
by a program in a space other than the flash memory.
Set the FMSTP bit to “1” if one of the following occurs:
•A flash memory access error occurs during erasing or programming in EW0 mode (FMR00 bit does
not switch back to “1” (ready)).
•Low-power consumption mode or ring oscillator low-power consumption mode is entered. Figure
19.5.1.3 shows a flow chart illustrating how to start and stop the flash memory before and after enter-
ing low power mode. Follow the procedure on this flow chart.
•FMR06 Bit
This is a read-only bit indicating an auto-program operation status. This bit is set to “1” when a pro-
gram error occurs; otherwise, it is set to “0”. For details, refer to the description of the full status check.
•FMR07 Bit
This is a read-only bit indicating an auto-erase operation status. The bit is set to “1” when an erase
error occurs; otherwise, it is set to “0”. For details, refer to the description of the full status check.
Figure 19.5.1.1 shows a EW0 mode set/reset flowchart, figure 19.5.1.2 shows a EW1 mode set/reset
flowchart.
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19. Flash Memory Version
19.5.2 Flash memory control register 1 (FMR1):
•FMR11 Bit
EW1 mode is entered by setting the FMR11 bit to “1” (EW1 mode). This bit is enabled only when the
FMR01 bit is “1”.
•FMR16 Bit
The combined setting of the FMR02 bit and the FMR16 bit enables to program and erase in the user
ROM area. To set this bit to “1”, it is necessary to set to “0” after first setting to “1”. To set this bit to “0”
by only writing “0”. This bit is enabled only when the FMR01 bit is “1”.
•FMR17 Bit
FMR17 bit is “1” (with wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the
access to block A and block B. Regardless of the content of the FMR17 bit, access to other block and
the internal RAM becomes the PM17 bit setting.
Set this bit to “1” (with wait state) when rewriting more than 100 times (Option).
Table 19.5.2.1. Protection using FMR16 and FMR02
FMR16
FMR02 Block A, Block B
Block 0, Block 1 other user block
0
0
1
1
0
1
0
1
write allowed
write allowed
write allowed
write allowed
write protected
write protected
write protected
write allowed
write protected
write protected
write allowed
write allowed
19.5.3 Flash memory control register 4 (FMR4):
•FMR40 Bit
The erase-suspend function is enabled by setting the FMR40 bit is set to “1” (enabled).
•FMR41 Bit
When setting the FMR41 bit to “1” in a program during auto-erasing in EW0 mode the flash module
enters erase suspend mode. In EW1 mode, the FMR41 bit is automatically set to “1” (suspend re-
quest) when an interrupt request of an enabled interrupt is generated, the FMR41 bit is automatically
set to “1” (suspend request) and when an auto-erasing operation is restarted, set the FMR41 bit to “0”
(erase restart).
•FMR46 Bit
The FMR46 bit is set to “0” during auto-erasing execution and set to “1” during erase-suspend mode.
Do not access to flash memory while this bit is “0”.
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19. Flash Memory Version
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR0
Address
01B716
After reset
XX000001
2
0
0
Bit symbol
Bit name
Function
RW
RO
0: Busy (during writing or erasing)
1: Ready
RY/BY status flag
FMR00
FMR01
0: Disables CPU rewrite mode
CPU rewrite mode select bit
(Note1)
(Disables software command)
1: Enables CPU rewrite mode
(Enables software commands)
RW
RW
Block 0, 1 rewrite enable bit
(Note 2)
Set write protection for user ROM area
(see Table 19.5.2.1)
FMR02
FMSTP
0: Starts flash memory operation
1: Stops flash memory operation
(Enters low-power consumption state
and flash memory reset)
Flash memory stop bit
(Note 3, 5)
RW
RW
Reserved bit
Set to “0”
(b5-b4)
FMR06
0: Terminated normally
1: Terminated in error
Program status flag
RO
RO
(Note 4)
(Note 4)
0: Terminated normally
1: Terminated in error
FMR07
Erase status flag
Note 1: When setting this bit to “1”, set to “1” immdediately after setting it first to “0”. Do not generate an
interrupt or a DMA transfer between setting the bit to “0” and setting it to “1”. Set this bit while the
P85/NMI/SD pin is “H” when selecting the NMI function. Set by program in a space other than the
flash memory in EW0 mode. Set this bit to read alley mode and “0”
Note 2: Set this bit to “1” immediately after setting it first to “0” while the FMR01 bit is set to “1”. Do not
generate an interrupt or a DMA transfer between setting this bit to “0” and setting it to “1”.
Note 3: Set this bit by a program in a space other than the flash memory.
Note 4: This bit is set to “0” by executing the clear status command.
Note 5: This bit is enabled when the FMR01 bit is set to “1” (CPU rewrite mode). This bit can be set to
“1” when the FMR01 bit is set to “1”. However, the flash memory does not enter low-power
consumption status and it is not initialized.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR1
Address
01B516
After reset
000XXX0X
2
0
Bit symbol
Bit name
Function
RW
RO
Reserved bit
When read, its content is indeterminate
(b0)
FMR11 EW1 mode select bit (Note1)
0: EW0 mode
1: EW1 mode
RW
RO
When read, its content is indeterminate
Reserved bit
(b3-b2)
Nothing is assigned. When write, set to “0”.
When read, its contect is indeterminate.
(b4)
Reserved bit
RW
RW
Set to “0”
(b5)
Set write protection for user ROM area
(see Table 19.5.2.1)
0: Disable
Block 0 to 3 rewrite enable
bit (Note2)
FMR16
1: Enable
Block A, B access wait bit (
Note 3)
FMR17
0: PM17 enabled
1: With wait state (1 wait)
RW
Note 1: Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA
transfer between setting the bit to “0” and setting it to “1”. Set this bit while the P8 /NMI/SD pin is “H”
5
when the NMI function is selected. If the FMR01 bit is set to “0”, the FMR01 bit and FMR11 bit are
both set to “0”
Note 2: Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA
transfer after setting to “0”.
Note 3: When rewriting more than 100 times, set this bit to “1” (with wait state). When the FMR17 bit is “1”
(with wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the access to the
block A and B.
Figure 19.5.1. Flash memory control register 0,1
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19. Flash Memory Version
Flash memory control register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR4
Address
01B316
After reset
01000000
2
0
0
0
0 0
Bit name
Function
Bit symbol
FMR40
RW
RW
0: Disabled
1: Enabled
Erase suspend function
enable bit (Note 1)
FMR41
Erase suspend
request bit (Note 2)
0: Erase restart
1: Suspend request
RW
Reserved bit
Erase status
Set to “0”
RO
RO
(b5-b2)
FMR46
0: During auto-erase operation
1: Auto-erase stop
(erase suspend mode)
Reserved bit
Set to “0”
RW
(b7)
Note 1: When setting this bit to “1”, set to “1” immediately after setting it first to “0”. Do not generate an
interrupt or a DMA transfer between setting the bit to “0” and setting it to “1”. Set by a program in a
space other than the flash memory in EW0 mode.
Note 2: This bit is valid only when the erase-suspend enable bit (FMR40) is “1”. Writing is enabled only
between executing an erase command and completing erase (this bit is set to “1” other than the
above duration). This bit can be set to “0” or “1” by a program in EW0 mode. In EW1 mode, this bit
is automatically set to “1” when the FMR40 bit is “1” and a maskable interrupt is generated during
erasing. Do not write to “1” by a program (writing “0” is enabled).
Figure 19.5.2. Flash memory control register 4
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19. Flash Memory Version
EW0 mode operation procedure
Rewrite control program
Set the FMR01 bit to “1” after writing “0” (
CPU rewrite mode enabled) (Note 2)
Single-chip mode
Set CM0, CM1, and PM1 registers (Note 1)
Execute software commands
Transfer a rewrite control program to internal RAM
area
Execute the Read Array command (Note 3)
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Jump to the rewrite control program transfered to an
internal RAM area (in the following steps, use the
rewrite control program internal RAM area)
Jump to a specified address in the flash memory
Note 1: Select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and CM17 to 16 bits in the
CM1 register. Also, set the PM17 bit in the PM1 register to “1” (with wait state).
Note 2: Set the FMR01 bit to “1” immediately after setting it to “0”. Do not generate an interrupt or a DMA transfer
between setting the bit to “0” and setting it to “1”. Set the FMR01 bit in a space other than the internal flash
memory. Also, set only when the P85/NMI/SD pin is “H” at the time of the NMI function selected.
Note 3: Disables the CPU rewrite mode after executing the read array command.
Figure 19.5.1.1. Setting and Resetting of EW0 Mode
EW1 mode operation procedure
Program in ROM
Single-chip mode (Note 1)
Set CM0, CM1, and PM1 registers (Note 2)
Set the FMR01 bit to “1” (CPU rewrite mode
enabled) after writing “0”
Set the FMR11 bit to “1” (EW1 mode) after writing
“0” (Note 3)
Execute software commands
Set the FMR01 bit to “0”
(CPU rewrite mode disabled)
Note 1: In EW1 mode, do not set boot mode.
Note 2: Select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and CM17 to 16
bits. in the CM1 register. Also, set the PM17 bit in the PM1 register to “1” (with wait state).
Note 3: Set the FMR01 bits to “1” immediately after setting it to “0”. Do not generate an interrupt or a DMA
transfer between setting the bit to “0” and setting the bit to “1”. Set the FMR01 bit in a space other
than the internal flash memory. Set only when the P8
function selected.
5/NMI/SD pin is “H” at the time of the NMI
Figure 19.5.1.2. Setting and Resetting of EW1 Mode
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19. Flash Memory Version
Low power consumption
mode program
Transfer a low power internal consumption mode
Set the FMR01 bit to “1” after setting “0” (
CPU rewrite mode enabled) (Note 2)
program to RAM area
Set the FMSTP bit to “1” (flash memory stopped.
Low power consumption state)(Note 1)
Jump to the low power consumption mode
program transferred to internal RAM area.
(In the following steps, use the low-power
consumption mode program or internal RAM area)
Switch the clock source of CPU clock.
Turn main clock off. (Note 2)
Process of low power consumption mode or
ring oscillator low power consumption mode
Start main clock
wait until oscillation stabilizes
oscillation
switch the clock source of the CPU clock (Note 2)
Set the FMSTP bit to “0” (flash memory operation)
Set the FMR01 bit to “0”
(CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes (10 µs)
(Note 3)
Jump to a desired address in the flash memory
Note 1: Set the FMRSTP bit to “1” after setting the FMR01 bit to “1”(CPU rewrite mode).
Note 2: Wait until the clock stabilizes to switch the clock source of the CPU clock to the main clock or the sub clock.
Note 3: Add a 10 µs wait time by a program. Do not access the flash memory during this wait time.
Figure 19.5.1.3. Processing Before and After Low Power Dissipation Mode
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19. Flash Memory Version
19.6 Precautions in CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
19.6.1 Operation Speed
When CPU clock source is the main clock, before entering CPU rewrite mode (EW0 or EW1 mode),
select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16
bits in the CM1 register. Also, when selecting f3(ROC) of a ring oscillator as a CPU clock source,
before entering CPU rewrite mode (EW0 or EW1 mode), the ROCR3 to ROCR2 bits in the ROCR
register set the CPU clock division rate to “divide-by-4” or “divide-by-8”.
On both cases, set the PM17 bit in the PM1 register to “1” (with wait state).
19.6.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because the CPU tries to read data in the
flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK in-
struction
19.6.3 Interrupts
EW0 Mode
• To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the
RAM area.
_______
• The NMI and watchdog timer interrupts can be used since the FMR0 and FMR1 registers are
forcibly reset when either interrupt is generated. However, the jump addresses for each interrupt
service routines to the fixed vector table are set and interrupt programs are required. Flash
memory rewrite operation is halted when the NMI or watchdog timer interrupt is generated. Set the
FMR01 bit to “1” and execute the rewrite and erase program again after exiting the interrupt rou-
tine.
• The address match interrupt can not be used since the CPU tries to read data in the flash memory.
EW1 Mode
• Do not acknowledge any interrupts with vectors in the relocatable vector table or the address
match interrupt during the auto-program or erase-suspend function.
19.6.4 How to Access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “1” after first setting the bit to “0”. Do not generate
an interrupt or a DMA transfer between the instruction to set the bit to “0” and the instruction to set it to
“1”. Set the bit while an “H” signal is applied to the NMI pin.
19.6.5 Writing in the User ROM Space
19.6.5.1 EW0 Mode
• If the supply voltage drops while rewriting the block where the rewrite control program is stored,
the flash memory can not be rewritten, because the rewrite control program is not correctly rewrit-
ten. If this error occurs, rewrite the user ROM area in standard serial I/O mode or parallel I/O
mode.
19.6.5.2 EW1 Mode
• Do not rewrite the block where the rewrite control program is stored.
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19. Flash Memory Version
19.6.6 DMA Transfer
In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0”.
(the auto-programming or auto-erasing duration ).
19.6.7 Writing Command and Data
Write the command code and data to even addresses in the user ROM area.
19.6.8 Wait Mode
When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the
WAIT instruction.
19.6.9 Stop Mode
When entering stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable the DMA transfer before setting
the CM10 bit to “1” (stop mode).
• Execute the instruction to set the CM10 bit to “1” (stop mode) and the JMP.B instruction.
Program example
BSET
0, CM1
L1
; Stop mode
JMP.B
L1:
Program after exiting stop mode
19.6.10 Low Power Consumption Mode and Ring Oscillator-Low Power Consumption Mode
If the CM05 bit is set to “1” (main clock stopped), do not execute the following commands.
• Program
• Block erase
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19. Flash Memory Version
19.7 Software Commands
Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing
a command code, 8 high-order bits (D15–D8) are ignored.
Table 19.7.1. Software Commands
First bus cycle
Address
Second bus cycle
Address
Command
Read array
Data
(D15 to D
Data
(D15 to D
Mode
Mode
Read
0
)
0)
Write
Write
Write
Write
Write
X
X
xxFF16
xx7016
xx5016
xx4016
xx2016
X
SRD
Read status register
Clear status register
Program
X
WA
BA
WD
WA
X
Write
Write
Block erase
xxD016
SRD: Status register data (D7 to D0)
WA : Write address (However,even address)
WD : Write data (16 bits)
BA : Highest-order block address (However,even address)
X : Any even address in the user ROM area
xx : 8 high-order bits of command code (ignored)
19.7.1 Read Array Command (FF16)
This command reads the flash memory.
By writing command code ‘xxFF16’ in the first bus cycle, read array mode is entered. Content of a
specified address can be read in 16-bit unit after the next bus cycle. The microcomputer remains in
read array mode until an another command is written. Therefore, contents of multiple addresses can
be read consecutively.
19.7.2 Read Status Register Command (7016)
This command reads the status register.
By writing command code ‘xx7016’ in the first bus cycle, the status register can be read in the second
bus cycle (Refer to “Status Register”). Read an even address in the user ROM area. Do not execute
this command in EW1 mode.
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19. Flash Memory Version
19.7.3 Clear Status Register Command (5016)
This command clears the status register to “0”.
By writing ‘xx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4
to SR5 bits in the status register are set to “0”.
19.7.4 Program Command (4016)
The program command writes 2-byte data to the flash memory. By writing ‘xx4016’ in the first bus cycle
and data to the write address specified in the second bus cycle, the auto-programming/erasing (data
prorgramming and verify) start. Set the address value specified in the first bus cycle to same and even
address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register
indicates whether an auto-programming operation has been completed. The FMR00 bit is set to “0”
during the auto-programming and “1” when the auto-programming operation is completed. After the
auto-programming operation is completed, the FMR06 bit in the FMR0 register indicates whether or
not the auto-programming operation has been completed as expected. (Refer to “Full Status Check”).
Also, each block disables writing (Refer to “Table 19.5.2.1”). Do not write additions to the address
which is already programmed. When commands other than a program command are executed imme-
diately after a program command, set the same address as the write address specified in the second
bus cycle of the program command, to the specified address value in the first bus cycle of the following
command. In EW1 mode, do not execute this command on the blocks where the rewrite control pro-
gram is allocated. In EW0 mode, the microcomputer enters read status register mode as soon as the
auto-programming operation starts and the status register can be read. The SR7 bit in the status
register is set to “0” as soon as the auto-programming operation starts. This bit is set to “1” when the
auto-programming operation is completed. The microcomputer remains in read status register mode
until the read array command is written. After completion of the auto-programming operation, the
status register indicates whether or not the auto-programming operation has been completed as ex-
pected.
Start
Write command code ‘xx4016’ to
the write address (Note 1)
Write data to the write address
(Note 1)
NO
FMR00=1?
YES
Full status check
(Note 2)
Program
completed
Note 1: Write the command code and data at even address.
Note 2: Refer to "Figure 19.8.4.1. Full Status Check and
Handling Procedure for Each Error"
Figure 19.7.4.1. Flow Chart of Program Command
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M16C/28 Group
19. Flash Memory Version
19.7.5 Block Erase
By writing ‘xx2016’ in the first bus cycle and ‘xxD016’ in the second bus cycle to the highest-order (even
addresse of a block) and the auto-programming/erasing (erase and erase verify) start. The FMR00 bit
in the FMR0 register indicates whether the auto-programming operation has been completed. The
FMR00 bit is set to “0” during the auto-erasing operation and “1” when the auto-erasing operation is
completed. When using the erase-suspend function in EW0 mode, the FMR46 bit in the FMR4 register
indicates whether a flash memory has entered erase-suspend mode. The FMR46 bit is set to “0”
during auto-erasing operation and “1” when the auto-erasing operation is completed (entering erase-
suspend). After the completion of an auto-erasing operation, the FMR07 bit in the FMR0 register
indicates whether or not the auto erasing-operation has been completed as expected. (Refer to “Full
Status Check”). Also, each block disables erasing. (Refer to “Table 19.5.2.1”). Figure 19.7.5.1 shows
a flow chart of the block erase command programming when not using the erase-suspend function.
Figure 19.7.5.2 shows a flow chart of the block erase command programming when using an erase-
suspend function. In EW1 mode, do not execute this command on the block where the rewrite control
program is allocated. In EW0 mode, the microcomputer enters read status register mode as soon as
the auto-erasing operation starts and the status register can be read. The SR7 bit in the status register
is set to “0” as soon as the auto-erasing operation starts. This bit is set to “1” when the auto-erasing
operation is completed. The microcomputer remains in read status register mode until the read array
command is written. Also, execute the clear status register command and the block erase command
at least 3 times until the erase error is not generated when an erase error is not generated.
Start
Write command code ‘xx2016’ (
Note 1)
Write ‘xxD016’ to the highest-order
block address (Note 1)
NO
FMR00=1?
YES
Full status check
(Note 2,3)
Block erase completed
Note 1: Write the command code and data at even address.
Note 2: Refer to "Figure 19.8.4.1. Full Status Check and Handling Porcedure
for Each Error".
Note 3: Execute the clear status register command and block erase
command at least 3 times until an erase error is not generated when
an erase error is generated.
Figure 19.7.5.1. Flow Chart of Block Erase Command (when not using erase suspend function)
Rev.0.60 2004.02.01 page 345 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
(EW0 mode)
Interrupt service routine
(Note 3)
Start
FMR40=1
FMR41=1
Write the command code ‘xx2016
’
(Note 1)
NO
FMR46=1?
Write ‘xxD016’ to the highest-order
block address (Note 1)
YES
Access Flash Memory
NO
FMR00=1?
FMR41=0
Return
YES
Full status check
(Note 2,4)
(Interrupt service routine end)
Block erase completed
(EW1 mode)
Interrupt service routine
(Note 3)
Start
FMR40=1
Access Flash Memory
Write the command code ‘xx2016
’
Return
(Interrupt service routine end)
(Note 1)
Write ‘xxD016’ to the highest-order
block address (Note 1)
FMR41=0
NO
FMR00=1?
YES
Full status check
(Note 2,4)
Block erase completed
Note 1: Write the command code and data to even address.
Note 2: Execute the clear status register command and block erase
command at least 3 times until an erase error is not generated when
an erase error is generated.
Note 3: In EW0 mode, allocate an interrupt vector table of an interrupt, to be
used, to a RAM area
Note 4: Refer to "Figure 19.8.4.1. Full Status Check and Handling Porcedure
for Each Error".
Figure 19.7.5.2. Block Erase Command (at use erase suspend)
Rev.0.60 2004.02.01 page 346 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
19.8 Status Register
The status register indicates the operating status of the flash memory and whether an erasing or a pro-
gramming operates normally and an error ends. The FMR00, FMR06, and FMR07 bits in the FMR0
register indicate the status of the status register.
Table 19.8.1 shows the status register.
In EW0 mode, the status register can be read in the following cases:
(1) When a given even address in the user ROM area is read after writing the read status register
command
(2) When a given even address in the user ROM area is read after executing the program or block
erase command but before executing the read a rray command.
19.8.1 Sequence Status (SR7 and FMR00 Bits )
The sequence status indicates the operating status of the flash memory. This bit is set to “0” (busy)
during an auto-programming and auto-erasing and “1” (ready) as soon as these operations are com-
pleted. This bit indicates “0” (busy) in erase-suspend mode.
19.8.2 Erase Status (SR5 and FMR07 Bits)
Refer to “Full Status Check.”
19.8.3 Program Status (SR4 and FMR06 Bits)
Refer to “Full Status Check.”
Table 19.8.1. Status Register
Bits in the
FMR0
register
Value
after
reset
Bits in the
SRD register
Contents
Status name
"0"
Busy
-
"1"
Ready
-
SR7 (D
SR6 (D
SR5 (D
SR4 (D
SR3 (D
SR2 (D
SR1 (D
SR0 (D
7)
6)
5)
4)
3)
2)
1)
0)
Sequence status
Reserved
FMR00
1
Erase status
Program status
Reserved
Completed normally
Completed normally
FMR07
FMR06
0
0
Terminated by error
Terminated by error
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
• D7 to D0: Indicates the data bus which is read out when executing the read status register command.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the clear status register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is 1, the program, and block erase command are not
acknowledged.
Rev.0.60 2004.02.01 page 347 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
19.8.4 Full Status Check
When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur-
rence of each specific error. Therefore, execution results can be verified by checking these status bits
(full status check). Table 19.8.4.1 shows errors and the status of FMR0 register. Figure 19.8.4.1
shows a flow chart of the full status check and handling procedure for each error.
Table 19.8.4.1. Errors and FMR0 Register Status
FMR00 register
(SRD register)
status
FMR06
Error
Error occurrence condition
FMR07
(SR5)
1
(SR4)
1
Command
• When any commands are not written correctly
sequence error • A value other than ‘xxD016’ or ‘xxFF16’ is written in the second
bus cycle of the block erase command (Note 1)
• When the block erase command is executed on protected blocks
• When the program command is executed on protected blocks
1
0
0
1
Erase error
• When the block erase command is executed on unprotected
blocks but the blocks are not automatically erased correctly
Program error • When the program command is executed on unprotected blocks
but the blocks are not automatically programmed correctly.
Note 1: The flash memory enters read array mode by writing command code ‘xxFF16’ in the second bus
cycle of these commands. The command code written in the first bus cycle becomes invalid.
Rev.0.60 2004.02.01 page 348 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
Full status check
FMR06 =1
and
FMR07=1?
YES
NO
(1) Execute the clear status register command and set
Command
sequence error
the status flag to “0” whether the command is
entered.
(2) Reexecute the command after checking that it is
entered correctly or the program command or the
block erase command is not executed for the
blocks which are protected.
NO
(1) Execute the clear status register command and set
the erase status flag to “0”.
(2) Reexecute the block erase command.
(3) Execute (1) and (2) at least 3 times until an erase
error is not generated.
FMR07=
0?
Erase error
YES
Note 1: If the error still occurs, the block can not be
used.
[During programming]
NO
(1) Execute the clear status register command and set
the program status flag to “0”.
(2) Reexecute the Program command.
Program error
FMR06=
0?
Note 2: If the error still occurs, the block can not be
used.
YES
Full status check completed
Note 4: If the FMR06 or FMR07 bits is “1”, any of the Program or Block Erase command can not
be aknowledged. Execute the clear status register command before executing those
commands.
Figure 19.8.4.1. Full Status Check and Handling Procedure for Each Error
Rev.0.60 2004.02.01 page 349 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
19.9 Standard Serial I/O Mode
In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is
mounted on-board by using a serial programmer which is applicable for the M16C/28 group. For more
information about serial programmers, contact the manufacturer of your serial programmer. For details on
how to use the serial programmer, refer to the user’s manual included with your serial programmer.
Table 19.9.1 shows pin functions (flash memory standard serial input/output mode). Figures 19.9.1 and
19.9.2 show pin connections for standard serial input/output mode.
19.9.1 ID Code Check Function
This function determines whether the ID codes sent from the serial programmer and those written in the
flash memory match. (Refer to "19.3 Functions To Prevent Flash Memory from Rewriting".)
Rev.0.60 2004.02.01 page 350 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
Table 19.9.1. Pin Functions (Flash Memory Standard Serial I/O Mode)
Pin
VCC,VSS
Name
Power input
Description
I/O
Apply the voltage guaranteed for Program and Erase to Vcc pin and 0
V to Vss pin.
CNVSS
RESET
CNVSS
I
I
Connect to Vcc pin.
Reset input
Reset input pin. While RESET pin is "L" level, wait for td(ROC).
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN pin
and open XOUT pin.
XIN
Clock input
I
XOUT
Clock output
O
AVCC, AVSS
Analog power supply input
Connect AVss to Vss and AVcc to Vcc, respectively.
VREF
Reference voltage input
Input port P0
I
I
Enter the reference voltage for AD conversion.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P60 to P63
P64
Input port P1
I
Input port P2
I
Input port P3
I
Input port P6
I
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitor signal output pin for boot program
operation check
BUSY output
O
Standard serial I/O mode 1: Serial clock input pin
Standard serial I/O mode 2: Input "L".
P65
SCLK input
I
P66
RxD input
I
O
I
Serial data input pin
P67
TxD output
Input port P7
Serial data output pin
(Note 1)
P70 to P77
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
P80 to P84,
P87
Input port P8
I
P85
P86
RP input
CE input
I
I
I
Connect this pin to Vss while RESET pin is “L”. (Note 2)
Connect this pin to Vcc while RESET pin is “L”. (Note 2)
Input "H" or "L" level signal or open.
P90 to P93,
P95 to P97
Input port P9
Input port P10
P100 to P107
I
Input "H" or "L" level signal or open.
Note 1: When using standard serial input/output mode 1, to input “H” to the TxD pin is necessary while the
___________
RESET pin is “L”. Therefore, connect this pin to VCC via a resistor. Adjust the pull-up resistor value
on a system not to affect a data transfer after reset, because this pin changes to a data-output pin
_____
_____
Note 2: Set either the RP pin or the CE pin.
Rev.0.60 2004.02.01 page 351 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
BUSY
SCLK
RxD
M16C/28 Group
(Flash memory version)
56
TxD
57
58
59
60
61
62
63
64
Mode setup method
Signal
CNVss
Reset
Value
Vcc
Vss to Vcc
Connect
oscillator
circuit
Package: 64P6Q-A
Note: In serial I/O Mode, it is necessary to connect the CE pin to "H" or the RP pin to "L" while the RESET pin is "L".
Figure 19.9.1. Pin Connections for Serial I/O Mode (1)
Rev.0.60 2004.02.01 page 352 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
61
62
63
64
65
66
67
68
69
M16C/28 Group
(Flash memory version)
70
BUSY
SCLK
RxD
71
72
73
74
75
76
77
78
79
80
TxD
Mode setup method
Signal
CNVss
Reset
Value
Vcc
Vss to Vcc
Connect
oscillator
circuit
Package: 80P6Q-A
Note: In serial I/O Mode, it is necessary to connect the CE pin to "H" or the RP pin to "L" while the RESET is "L"
Figure 19.9.2. Pin Connections for Serial I/O Mode (2)
Rev.0.60 2004.02.01 page 353 of N
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
19.9.2 Example of Circuit Application in Standard Serial I/O Mode
Figure 19.9.2.1 shows an example of a circuit application in standard serial I/O mode 1 and Figure
19.9.2.2 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's
manual for a serial writer to handle pins controlled by the serial writer.
Microcomputer
(Note 1)
SCLK
SCLK input
P86(CE)
TXD
TxD output
BUSY
RxD
BUSY output
RxD input
CNVss
Reset input
RESET
User reset
singnal
P85(RP)
(Note 1)
(1) Controlling pins and external circuits vary with the serial programmer. For more
information, refer to the user's manual included with the serial programmer.
(2) In this example, a selector controls the input voltage applied to CNVss to switch
between single-chip mode and standard serial I/O mode.
(3) In standard serial input/output mode 1, if the user reset signal becomes “L” while
the microcomputer is communicating with the serial programmer, break the
connection between the user reset signal and the RESET pin using a jumper
switch.
Note 1. Set either the P86(CE) pin or the P85(RP) pin.
Figure 19.9.2.1. Circuit Application in Standard Serial I/O Mode 1
Rev.0.60 2004.02.01 page 354 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
Microcomputer
(Note 1)
6(CE)
SCLK
TxD
P8
TxD output
BUSY
RxD
Monitor output
RxD input
CNVss
P85(RP)
(Note 1)
(1) In this example, a selector controls the input voltage applied to CNVss to switch
between single-chip mode and standard serial I/O mode.
Note 1. Set either the P86(CE) pin or the P85(RP) pin.
Figure 19.9.2.2. Circuit Application in Standard Serial I/o Mode 2
Rev.0.60 2004.02.01 page 355 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
19. Flash Memory Version
19.10 Parallel I/O Mode
In parallel input/output mode, the user ROM can be rewritten using a parallel programmer which is appli-
cable for the M16C/28 group. For more information about the parallel programmer, contact your parallel
programmer manufacturer. For details on how to use the parallel programmer, refer to the user’s manual of
the parallel programmer.
19.10.1 ROM Code Protect Function
The ROM code protect function prevents the flash memory from being read or rewritten. (Refer to the
description of the functions to inhibit rewriting flash memory version.)
Rev.0.60 2004.02.01 page 356 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
20. Package
20. Package
Recommended
64P6Q-A
Plastic 64pin 10✼10mm body LQFP
EIAJ Package Code
LQFP64-P-1010-0.50
JEDEC Code
–
Weight(g)
–
Lead Material
Cu Alloy
MD
HD
D
64
49
I
2
Recommended Mount Pad
Dimension in Millimeters
1
48
Symbol
Min
–
0
Nom
–
0.1
Max
1.7
0.2
–
A
A
A
1
2
–
1.4
b
0.13
0.105
9.9
9.9
–
0.18
0.125
10.0
10.0
0.5
0.28
0.175
10.1
10.1
–
16
33
c
D
E
e
17
32
A
H
H
L
D
11.8
11.8
0.3
–
12.0
12.0
0.5
12.2
12.2
0.7
–
F
E
e
L1
1.0
L1
Lp
A3
x
0.45
–
–
–
0°
–
1.0
–
0.6
0.25
–
–
–
0.225
–
10.4
10.4
0.75
–
0.08
0.1
10°
–
–
–
–
y
y
L
b
b2
x
M
Lp
I
2
Detail F
M
M
D
E
–
Recommended
80P6Q-A
Plastic 80pin 12✼12mm body LQFP
EIAJ Package Code
LQFP80-P-1212-0.5
JEDEC Code
Weight(g)
0.47
Lead Material
Cu Alloy
M
D
–
HD
D
80
61
l
2
1
60
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A
A
1
0
0.1
2
–
1.4
b
0.13
0.105
11.9
11.9
–
0.18
0.125
12.0
12.0
0.5
0.28
0.175
12.1
12.1
–
c
D
E
e
20
41
21
40
H
H
L
D
13.8
13.8
0.3
–
0.45
–
–
–
0°
–
14.0
14.0
0.5
1.0
0.6
0.25
–
–
14.2
14.2
0.7
–
0.75
–
0.08
0.1
10°
–
A
E
L
1
F
L1
e
Lp
A3
x
y
–
b
y
x
M
L
b2
0.225
–
12.4
12.4
I
2
0.9
–
–
–
–
–
Lp
Detail F
M
M
D
E
Rev.0.60 2004.02.01 page 357 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
Register Index
Register Index
G1IE0 133
A
G1IE1 133
AD0 to AD7 208
ADCON0 206
ADCON1 206
ADCON2 206
ADIC 60
G1IR 132
G1PO0 to G1PO7 130
G1POCR0 to G1POCR7 129
G1TM0 to G1TM7 129
G1TMCR0 to G1TMCR7 128
G1TPR6 128
ADSTAT0 208
ADTRGCON 207
AIER 72
G1TPR7 128
I
B
I2CIC 60
BCNIC 60
BTIC 60
ICOC0IC 60
ICOC1IC 60
ICTB2 113
IDB0 113
C
CM0 33
IDB1 113
CM1 34
IFSR 61, 69
IFSR2A 61
INT0IC to INT5IC 60
INVC0 111
INVC1 112
CM2 35
CPSRF 89,102
D
D4INT 26
DAR0 79
K
DAR1 79
KUPIC 60
DM0CON 78
DM0IC 60
DM0SL 78
DM1CON 78
DM1IC 60
DM1SL 78
DTT 113
M
N
NDDR 282
O
ONSF 89
F
P
FMR0 351
FMR1 351
FMR4 352
P0 to P3,P6 to P10 279
P17DDR 282
PACR 281
G
PCLKR 36
G1BCR0 124
G1BCR1 126
G1BT 124
PCR 281
PD0 to PD3,PD6 to PD10 278
PDRF 121
G1BTRR 127
G1DV 125
G1FE 131
PLC0 37
PM0 30
PM1 30
G1FS 131
PM2 36
Rev.0.60 2004.02.01 page 358 of N
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Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
Register Index
PRCR 53
TA21 114
PUR0 to PUR2 280
TA2IC 60
TA2MR 87,117
TA3 88
R
RMAD0 72
RMAD1 72
ROCR 34
TA3IC 60
TA3MR 87
TA4 88,114
TA41 114
S
TA4IC 60
S00 241
TA4MR 87,117
TABSR 88,102,116
TB0 102
S0D0 240
S0TIC 60
S0RIC 60
S10 243
TB0IC 60
TB0MR 101
TB1 102
S1D0 242
S1TIC 60
S1RIC 60
S20 241
TB1IC 60
TB1MR 101
TB2 102,116
TB2IC 60
S2D0 246
S2TIC 60
S2RIC 60
S3BRG 200
S3C 200
TB2MR 101,117
TB2SC 108,115
TCR0 79
TCR1 79
S3D0 244
S3IC 60
TRGSR 89,116
U
S3TRR 200
S4BRG 200
S4C 200
U0BRG 157
U0C0 159
U0C1 160
U0MR 158
U0RB 157
U0TB 157
U1BRG 157
U1C0 159
U1C1 160
U1MR 158
U1RB 157
U1TB 157
U2BRG 157
U2C0 159
U2C1 160
U2MR 158
U2RB 157
U2SMR 161
S4D0 245
S4IC 60
S4TRR 200
SAR0 79
SAR1 79
SCLDAIC 60
T
TA0 88
TA0IC 60
TA0MR 87
TA1 88,114
TA11 114
TA1IC 60
TA1MR 87,117
TA2 88,114
Rev.0.60 2004.02.01 page 359 of N
REJ09B0047-0060Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
Register Index
U2SMR2 161
U2SMR3 162
U2SMR4 162
U2TB 157
UCON 159
UDF 88
V
VCR1 26
VCR2 26
W
WDC 25,74
WDTS 74
Rev.0.60 2004.02.01 page 360 of N
REJ09B0047-0060Z
RENESAS 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER
HARDWARE MANUAL
M16C/28 Group Rev.0.60
Editioned by
Committee of editing of RENESAS Semiconductor Hardware Manual
This book, or parts thereof, may not be reproduced in any form without permission
of Renesas Technology Corporation.
Copyright © 2003. Renesas Technology Corporation, All rights reserved.
M16C/28 Group
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
REJ09B0170-0060Z
M16C/28 Group
Usage Notes Reference Book
16
M16C FAMILY / M16C/Tiny SERIES
For the most current Usage Notes Reference Book, please visit our website.
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 0.60
Revision date: February. 01. 2004
www.renesas.com
Keep safety first in your circuit designs!
•
Renesas Technology Corporation puts the maximum effort into making semiconductor prod-
ucts better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
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he products contained therein.
Preface
The “Usage Notes Reference Book” is a
compilation of usage notes from the
Hardware Manual as well as technical
news related to this product.
Table of Contents
1. Usage Precaution.............................................................. 1
1.1 Precautions for SFR ................................................................................. 1
1.1.1 Precaution for 80 pin version.................................................................................. 1
1.1.2 Precaution for 64 pin version.................................................................................. 1
1.2 Precautions for PLL Frequency Synthesizer ......................................... 2
1.3 Precautions for Power Control .................................................................3
1.4 Precautions for Protect ............................................................................ 4
1.5 Precautions for Interrupts .........................................................................5
1.5.1 Reading address 0000016 .........................................................................................................................................................
5
1.5.2 Setting the SP ........................................................................................................... 5
1.5.3 The _N__M___I_ Interrupt ..................................................................................................... 5
1.5.4 Changing the Interrupt Generate Factor ................................................................ 6
1.5.5 _I_N__T__ Interrupt.............................................................................................................. 6
1.5.6 Rewrite the Interrupt Control Register ................................................................... 7
1.5.7 Watchdog Timer Interrupt ....................................................................................... 8
1.6 Precautions for DMAC ...............................................................................9
1.6.1 Write to DMAE Bit in DMiCON Register ................................................................. 9
1.7 Precautions for Timers ............................................................................10
1.7.1 Timer A .................................................................................................................... 10
1.7.1.1 Timer A (Timer Mode) .................................................................................................. 10
1.7.1.2 Timer A (Event Counter Mode).....................................................................................11
1.7.1.3 Timer A (One-shot Timer Mode).................................................................................. 12
1.7.1.4 Timer A (Pulse Width Modulation Mode) ................................................................... 13
1.7.2 Timer B .................................................................................................................... 14
1.7.2.1 Timer B (Timer Mode) .................................................................................................. 14
1.7.2.2 Timer B (Event Counter Mode) ................................................................................... 15
1.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) ....................................... 16
1.7.3 Timer S .................................................................................................................... 17
1.7.3.1 Rewrite the G1IR register ............................................................................................ 17
A-1
1.8 Precautions for Serial I/O (Clock-synchronous Serial I/O) ..................18
1.8.1 Transmission/reception ......................................................................................... 18
1.8.2 Transmission ..........................................................................................................19
1.8.3 Reception ................................................................................................................ 20
1.9 Precautions for Serial I/O (UART Mode) ................................................21
1.9.1 Special Mode 2 ...................................................................................................... 21
1.9.2 Special Mode 4 (SIM Mode) .................................................................................. 21
1.10 Precautions for A-D Converter .............................................................22
1.11 Precautions for Programmable I/O Ports.............................................24
1.12 Electric Characteristic Differences Between Mask ROM
and Flash Memory Version Microcomputers ..............25
1.13 Precautions for Flash Memory Version ...............................................26
1.13.1 Precautions for Functions to Inhibit Rewriting Flash Memory Rewrite .......... 26
1.13.2 Precautions for Stop mode ................................................................................. 26
1.13.3 Precautions for Wait mode.................................................................................. 26
1.13.4 Precautions for Low power dissipation mode,
ring oscillator low power dissipation mode ......................... 26
1.13.5 Writing command and data ................................................................................. 26
1.13.6 Precautions for Program Command .................................................................. 26
1.13.7 Operation speed ................................................................................................... 27
1.13.8 Instructions inhibited against use ...................................................................... 27
1.13.9 Interrupts .............................................................................................................. 27
1.13.10 How to access .................................................................................................... 27
1.13.11 Writing in the user ROM area ............................................................................ 28
1.13.12 DMA transfer....................................................................................................... 28
1.13.13 Regarding Programming/Erasure Times and Execution Time ...................... 28
A-2
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Usage Precaution
1.1 Precautions for SFR
1.1.1 Precaution for 80 pin version
Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR
register to "0112".
1.1.2 Precaution for 64 pin version
Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR
register to "0102".
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1.2 Precautions for PLL Frequency Synthesizer
Make the supply voltage stable to use the PLL frequency synthesizer.
For ripple with the supply voltage 5V, keep below 10kHz as frequency, below 0.5V (peak to peak) as
voltage fluctuation band and below 1V/mS as voltage fluctuation rate.
For ripple with the supply voltage 3V, keep below 10kHz as frequency, below 0.3V (peak to peak) as
voltage fluctuation band and below 0.6V/mS as voltage fluctuation rate.
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1.3 Precautions for Power Control
1. When exiting stop mode by hardware reset, the device will startup using the ring oscillator.
2. Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of
CM1 register to “1”. When shifting to wait mode or stop mode, an instruction queue reads ahead to the
next instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit to “1” (all
clocks stopped). The next instruction may be executed before entering wait mode or stop mode, de-
pending on a combination of instruction and an execution timing.
3. Wait until the td(M-L) elapses or main clock oscillation stabilization time, whichever is longer, before
switching the clock source for CPU clock to the main clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the
sub clock.
4. Suggestions to reduce power consumption
(a) Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A
current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When
entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
(b) A-D converter
When A-D conversion is not performed, set the VCUT bit of ADiCON1 register to “0” (no VREF connec-
tion). When A-D conversion is performed, start the A-D conversion at least 1 µs or longer after setting
the VCUT bit to “1” (VREF connection).
(c) Stopping peripheral functions
Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode.
However, because the peripheral function clock (fC32) generated from the sub-clock does not stop,
this measure is not conducive to reducing the power consumption of the chip. If low speed mode or
low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not peripheral
function clock stopped when in wait mode), before changing wait mode.
(d) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
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1.4 Precautions for Protect
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction.
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1.5 Precautions for Interrupts
1.5.1 Reading address 0000016
Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU
reads interrupt information (interrupt number and interrupt request priority level) from the address
0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or an
unexpected interrupt request is generated.
1.5.2 Setting the SP
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to ‘000016’
after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the pro-
gram may go out of control.
_______
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first
_______
and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
1.5.3 The _N__M___I_ Interrupt
_______
_______
1. The NMI interrupt is invalid after reset. The NMI interrupt becomes effective by setting to “1” the PM24
bit of the PM2 register. Once enabled, it stays enabled until a reset is applid.
_______
2. The input level of the NMI pin can be read by accessing the P8 register’s P8_5 bit. Note that the P8_5
_______
bit can only be read when determining the pin level in NMI interrupt routine.
_______
_______
3. When selecting NMI function, stop mode cannot be entered into while input on the NMI pin is low. This
_______
is because while input on the NMI pin is low the CM1 register’s CM10 bit is fixed to “0”.
_______
_______
4. When selecting NMI function, do not go to wait mode while input on the NMI pin is low. This is because
_______
when input on the NMI pin goes low, the CPU stops but CPU clock remains active; therefore, the current
consumption in the chip does not drop. In this case, normal condition is restored by an interrupt gener-
ated thereafter.
_______
_______
5. When selecting NMI function, the low and high level durations of the input signal to the NMI pin must
each be 2 CPU clock cycles + 300 ns or more.
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1.5.4 Changing the Interrupt Generate Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor
for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt not
requested).
“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity
or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any
peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to
clear the IR bit for that interrupt to “0” (interrupt not requested) after making such changes. Refer to the
description of each peripheral function for details about the interrupts from peripheral functions.
Figure 1.5.1 shows the procedure for changing the interrupt generate factor.
Changing the interrupt source
Disable interrupts (Note 2, Note 3)
Change the interrupt generate factor (including a mode change of peripheral function)
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (Note 3)
Enable interrupts (Note 2, Note 3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed
Note 1: The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
Note 2: Use the I flag for the INTi interrupt (i = 0 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an interrupt
request before changing the interrupt generate factor. In this case, if the maskable interrupts
can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding
ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed.
Note 3: Refer to Section 1.1.6, “Rewrite the Interrupt Control Register” for details about the
instructions to use and the notes to be taken for instruction execution.
Figure 1.5.1. Procedure for Changing the Interrupt Generate Factor
1.5.5 _I_N__T__ Interrupt
1. Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal
input to pins INT0 through INT5 regardless of the CPU operation clock.
2. If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0
(interrupt not requested) after changing any of those register bits.
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1.5.6 Rewrite the Interrupt Control Register
(1) The interrupt control register for any interrupt should be modified in places where no requests for that
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
instruction to be used.
Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown below
to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not re-
quested). Therefore, be sure to use the MOV instruction to clear the IR bit.
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as
you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue
buffer.
Example 1:Using the NOP instruction to keep the program waiting until
the interrupt control register is modified
INT_SWITCH1:
FCLR
AND.B
NOP
I
; Disable interrupts.
#00h, 0055h ; Set the TA0IC register to “0016”.
;
NOP
FSET
I
; Enable interrupts.
Example 2:Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B
MOV.W
FSET
#00h, 0055h ; Set the TA0IC register to “0016”.
MEM, R0
I
; Dummy read.
; Enable interrupts.
Example 3:Using the POPC instruction to changing the I flag
INT_SWITCH3:
PUSHC
FCLR
FLG
I
; Disable interrupts.
AND.B
POPC
#00h, 0055h ; Set the TA0IC register to “0016”.
FLG ; Enable interrupts.
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1.5.7 Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
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1.6 Precautions for DMAC
1.6.1 Write to DMAE Bit in DMiCON Register
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.
(*1)
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously
.
(*2)
Step 2: Make sure that the DMAi is in an initial state
in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
Notes:
*1. The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set to
“0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should be
written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit
immediately before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to
the DMAS bit in order to maintain a DMA request which is generated during execution.
*2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a
value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state.
(If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is “1”.) If
the read value is a value in the middle of transfer, the DMAi is not in an initial state.
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1.7 Precautions for Timers
1.7.1 Timer A
1.7.1.1 Timer A (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count
starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the counter is read at the same time it is reloaded, the value “FFFF16” is read.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not
counting, the set value is read.
_____
3. If a low-level signal is applied to the SD pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_____
output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.
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1.7.1.2 Timer A (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count
starts).
Always make sure the TAiMR register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register are modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, “FFFF16” can be read in underflow, while reloading, and “000016” in overflow.
When setting TAi register to a value during a counter stop, the setting value can be read before a
counter starts counting. Also, if the counter is read before it starts counting after a value is set in the
TAi register while not counting, the set value is read.
_____
3. If a low-level signal is applied to the SD pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_____
output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.
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1.7.1.3 Timer A (One-shot Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after
reset or not.
2. When setting TAiS bit to “0” (count stop), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit of TAiIC register is set to “1” (interrupt request).
3. Output in one-shot timer mode synchronizes with a count source internally generated. When an
external trigger has been selected, one-cycle delay of a count source as maximum occurs between
a trigger input to TAiIN pin and output in one-shot timer mode.
4. The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operation mode from timer mode to one-shot timer mode.
• Change an operation mode from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have
been made.
5. When a trigger occurs, while counting, a counter reloads the reload register to continue counting
after generating a re-trigger and counting down once. To generate a trigger while counting, gener-
ate a second trigger between occurring the previous trigger and operating longer than one cycle of
a timer count source.
_____
6. If a low-level signal is applied to the SD pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_____
output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.
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1.7.1.4 Timer A (Pulse Width Modulation Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after
reset or not.
2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the PWM mode after reset.
• Change an operation mode from timer mode to PWM mode.
• Change an operation mode from event counter mode to PWM mode.
To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above
listed changes have been made.
3. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.
_____
4. If a low-level signal is applied to the SD pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_____
output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a
high-impedance state.
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1.7.2 Timer B
1.7.2.1 Timer B (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to
“1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
2. A value of a counter, while counting, can be read in TBi register at any time. “FFFF16” is read while
reloading. Setting value is read between setting values in TBi register at count stop and starting a
counter.
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1.7.2.2 Timer B (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to
“1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
2. The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this
register is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the
TBi register is read after setting a value in it while not counting but before the counter starts count-
ing, the read value is the one that has been set in the register.
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1.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)
1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2)
register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register
while the TBiS bit = “1” (count starts), be sure to write the same value as previously written to the
TM0D0, TM0D1, MR0, MR1, TCK0 and TCK1 bits and a 0 to the MR2 bit.
2. The IR bit of TBiIC register (i=0 to 2) goes to “1” (interrupt request), when an effective edge of a
measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be deter-
mined by use of the MR3 bit of TBiMR register within the interrupt routine.
3. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
input and a timer overflow occur at the same time, use another timer to count the number of times
timer B has overflowed.
4. To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and
counting the next count source after setting the MR3 bit to “1” (overflow).
5. Use the IR bit of TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.
6. When a count is started and the first effective edge is input, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
7. A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and timer
Bi interrupt request may be generated between a count start and an effective edge input.
8. For pulse width measurement, pulse widths are successively measured. Use program to check
whether the measurement result is an “H” level width or an “L” level width.
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M16C/28 Group
1.7.3 Timer S
1.7.3.1 Rewrite the G1IR register
When write "0" (without interrupt request) to each bit in the G1IR register, use the following
instructions.
Usable instructions: AND, BCLR
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M16C/28 Group
1.8 Precautions for Serial I/O (Clock-synchronous Serial I/O)
1.8.1 Transmission/reception
_______
________
1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes
to “L” when the data-receivable status becomes ready, which informs the transmission side that the
________
reception has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if
________
________
the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmission and
_______
reception data with consistent timing. With the internal clock, the RTS function has no effect.
_____
2. If a low-level signal is applied to the SD pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_____
output forcible cutoff by input on SD pin enabled), the RTS2 and CLK2 pins go to a high-impedance
state.
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M16C/28 Group
1.8.2 Transmission
When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit =
“0” (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer
clock), the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at
the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is
in the low state.
• The TE bit of UiC1 register= “1” (transmission enabled)
• The TI bit of UiC1 register = “0” (data present in UiTB register)
_______
_______
• If CTS function is selected, input on the CTSi pin = “L”
Rev.0.60 2004.02.01 page 19 of N
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Specifications in this manual are tentative and subject to change.
M16C/28 Group
1.8.3 Reception
1. In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix set-
tings for transmission even when using the device only for reception. Dummy data is output to the
outside from the TxDi pin when receiving data.
2. When an internal clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 (transmission enabled)
and write dummy data to the UiTB register, and the shift clock will thereby be generated. When an
external clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 and write dummy data to the
UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi input pin.
3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive
register while the UiC1 register (i = 0 to 2)’s RE bit = “1” (data present in the UiRB register), an overrun
error occurs and the UiRB register OER bit is set to “1” (overrun error occurred). In this case, because
the content of the UiRB register is indeterminate, a corrective measure must be taken by programs on
the transmit and receive sides so that the valid data before the overrun error occurred will be retransmit-
ted. Note that when an overrun error occurred, the SiRIC register IR bit does not change state.
4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time
reception is made.
5. When an external clock is selected, the conditions must be met while if the CKPOL bit = “0”, the
external clock is in the high state; if the CKPOL bit = “1”, the external clock is in the low state.
• The RE bit of UiC1 register= “1” (reception enabled)
• The TE bit of UiC1 register= “1” (transmission enabled)
• The TI bit of UiC1 register= “0” (data present in the UiTB register)
Rev.0.60 2004.02.01 page 20 of N
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M16C/28 Group
1.9 Precautions for Serial I/O (UART Mode)
1.9.1 Special Mode 2
_____
If a low-level signal is applied to the SD pin when the TB2SC register IVPCR1 bit = 1 (three-phase output
_____
forcible cutoff by input on SD pin enabled), the RTS2 and CLK2 pins go to a high-impedance state.
1.9.2 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission
complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be
sure to clear the IR bit to “0” (no interrupt request) after setting these bits.
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1.10 Precautions for A-D Converter
1. Set ADCON0 (except bit 6), ADCON1, ADCON2 and ADTRGCON registers when A-D conversion is
stopped (before a trigger occurs).
2. When the VCUT bit of ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref con-
nected), start A-D conversion after passing 1 µs or longer.
3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi, AN0i, AN2i(i=0 to 7)) each and the
AVSS pin. Similarly, insert a capacitor between the VCC1 pin and the VSS pin. Figure 1.10.1 is an ex-
ample connection of each pin.
4. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit for
___________
the ADTRG pin is set to “0” (input mode).
5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A-D input voltage goes low.)
6. The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency
to 250kHZ or more. With the sample and hold function, limit the φAD frequency to 1MHZ or more.
7. When changing an A-D operation mode, select analog input pin again in the CH2 to CH0 bits of
ADCON0 register and the SCAN1 to SCAN0 bits of ADCON1 register.
Microcomputer
AVCC
V
REF
C2
C1
C3
AVSS
V
CC
C4
AN
i
V
SS
AN
i
: AN
i(i=0 to 7), AN0i (i=0 to 7 for 80-pin version, and i=0 to 3 for 64-pin version)
AN2i (i=0 to 7 for 80-pin version, i=4 for 64-pin version)
NOTES
1. C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF (reference)
2. Use thick and shortest possible wiring to connect capacitors.
Figure 1.10.1. Use of capacitors to reduce noise
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8. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A-D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
• When operating in one-shot, single-sweep mode, simultaneous sample sweep mode, delayed
trigger mode 0 or delayed trigger mode 1
Check to see that A-D conversion is completed before reading the target ADi register. (Check the
ADIC register’s IR bit to see if A-D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
9. If A-D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit to
“0” (A-D conversion halted), the conversion result of the A-D converter is indeterminate. The contents of
ADi registers irrelevant to A-D conversion may also become indeterminate. If while A-D conversion is
underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.
10. When setting the ADST bit in the ADCON register to "0" and terminating forcefully by a program in
single sweep conversion mode, A-D delayed trigger mode 0 and A-D delayed trigger mode 1 during
A-D converting operation, the A-D interrupt request may be generated. If this causes a problemm, set
the ADST bit to "0" after an interrupt is disabled.
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1.11 Precautions for Programmable I/O Ports
_____
1. If a low-level signal is applied to the SD pin when the TB2SC register IVPCR1 bit = “1” (three-phase
_____
output forcible cutoff by input on SD pin enabled), the P72 to P75, P80 and P81 pins go to a high-
impedance state.
2. Setting the SM32 bit in the S3C register to “1” causes the P32 pin to go to a high-impedance state.
Similarly, setting the SM42 bit in the S4C register to “1” causes the P96 pin to go to a high-impedance
state.
3. When the INV03 bit of the INVC0 register is "1"(three-phase motor control timer output enabled), it
_____
_______ _____
becomes the following by the SD function when "L" is input to the P85 /NMI/SD pin.
_____
•When the TB2SC register IVPCR1 bit = “1” (three-phase output forcible cutoff by input on SD pin
__
__
___
enabled), the U/ U/ V/ V/ W/ W pins go to a high-impedance state.
•When the TB2SC register IVPCR1 bit = “0” (three-phase output forcible cutoff by input on SD pin
_____
__
__
___
disabled), the U/ U/ V/ V/ W/ W pins go to a normal port.
_____
_______ _____
When the SD function isn't used, set to "0" (Input) in PD85 and pullup to "H" in the P85 /NMI/SD pin from
outside.
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M16C/28 Group
1.12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin, noise
tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern,
etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests con-
ducted in the flush memory version.
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M16C/28 Group
1.13 Precautions for Flash Memory Version
1.13.1 Precautions for Functions to Inhibit Rewriting Flash Memory Rewrite
ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716,
and 0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be read or written
in standard serial I/O mode.
The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H)
of fixed vectors.
1.13.2 Precautions for Stop mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program
BSET
0, CM1
L1
; Stop mode
JMP.B
L1:
Program after returning from stop mode
1.13.3 Precautions for Wait mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode diabled) before executing the
WAIT instruction.
1.13.4 Precautions for Low power dissipation mode, ring oscillator low power dissipation mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
1.13.5 Writing command and data
Write the command code and data at even addresses.
1.13.6 Precautions for Program Command
Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in the
first bus cycle is the same even address as the write address specified in the second bus cycle.
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M16C/28 Group
1.13.7 Operation speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for CPU clock using the
CM0 register’s CM06 bit and CM1 register’s CM17–6 bits. Also, set the PM1 register’s PM17 bit to 1 (with
wait state).
1.13.8 Instructions inhibited against use
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
1.13.9 Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
_______
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 regis-
ter are initialized when one of those interrupts occurs. The jump addresses for those interrupt
service routines should be set in the fixed vector table.
_______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is refer-
enced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
_______
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table.
_______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.
1.13.10 How to access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary to
ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only when
_______
NMI pin is “H” level.
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M16C/28 Group
1.13.11 Writing in the user ROM area
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse-
quently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
1.13.12 DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).
1.13.13 Regarding Programming/Erasure Times and Execution Time
As the number of programming/erasure times increases, so does the execution time for software com-
mands (Program, Block Erase, Erase All Unlock Blocks, and Lock Bit Program). Especially when the
number of programming/erasure times exceeds 1,000, the software command execution time is notice-
ably extended. Therefore, the software command wait time that is set must be greater than the maximum
rated value of electrical characteristics.
_______
The software commands are aborted by hardware reset 1, hardware reset 2, NMI interrupt, and watchdog
timer interrupt. If a software command is aborted by such reset or interrupt, the block that was in process
must be erased before reexecuting the aborted command.
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RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
USAGE NOTES REFERENCE BOOK
M16C/28 Group Rev.0.60
Editioned by
Committee of editing of RENESAS Semiconductor Usage Notes Reference
Book
This book, or parts thereof, may not be reproduced in any form without permission
of Renesas Technology Corporation.
Copyright © 2003. Renesas Technology Corporation, All rights reserved.
M16C/28 Group
Usage Notes Reference Book
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
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