M30302FAPGP_技术文档

M16C/30P Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

REJ03B0088-0122

Rev.1.22

Mar 30, 2007

1. Overview

The M16C/30P Group of single-chip microcomputers is built using the high-performance silicon gate CMOS process

using a M16C/60 Series CPU core and is packaged in a 100-pin plastic molded QFP.

These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction

efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. In addition, these

microcomputers contain a multiplier and DMAC which combined with fast instruction processing capability, make it

suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/

logic operations.

1.1

Applications

Audio, cameras, TV, home appliance, office/communications/portable/industrial equipment, etc.

Rev.1.22 Mar 30, 2007 Page 1 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

1.2

Performance Outline

Table 1.1 lists Performance Outline of M16C/30P Group.

Table 1.1

Performance Outline of M16C/30P Group

Item

Performance

CPU

Number of Basic Instructions 91 instructions

Minimum Instruction

Execution Time

62.5ns(f(XIN)=16MHz, VCC1=VCC2=3.0 to 5.5V, no wait)

100ns(f(XIN)=10MHz, VCC1=VCC2=2.7 to 5.5V, no wait)

Single-chip, memory expansion and microprocessor

mode

Operation Mode

Memory Space

Memory Capacity

Port

1 Mbyte

See Table 1.2 Product List

Input/Output : 87 pins, Input : 1 pin

Timer A : 16 bits x 3 channels,

Timer B : 16 bits x 3 channels

1 channels

Peripheral

Function

Multifunction Timer

Serial Interface

2

(1)

(2)

Clock synchronous, UART, I CBus , IEBus

2 channels

2

(1)

Clock synchronous, UART, I CBus

A/D Converter

DMAC

10-bit A/D converter: 1 circuit, 18 channels

2 channels

CRC Calculation Circuit

Watchdog Timer

Interrupt

CCITT-CRC

15 bits x 1 channel (with prescaler)

Internal: 20 sources, External: 7 sources, Software: 4

sources, Priority level: 7 levels

Clock Generating Circuit

2 circuits

Main clock generation circuit (*),

Subclock generation circuit (*),

(*)Equipped with a built-in feedback resistor.

Electric

Characteristics

Supply Voltage

VCC1=VCC2=3.0 to 5.5 V (f(XIN)=16MHz)

VCC1=VCC2=2.7 to 5.5 V (f(XIN)=10MHz, no wait)

10 mA (VCC1=VCC2=5V, f(XIN)=16MHz)

8 mA (VCC1=VCC2=3V, f(XIN)=10MHz)

1.8 μA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)

0.7 μA(VCC1=VCC2=3V, stop mode)

Power Consumption

One time flash Program Supply Voltage

version

3.3±0.3 V or 5.0±0.5 V

Flash memory Program/Erase Supply

3.3±0.3 V or 5.0±0.5 V

100 times (all area)

version

Voltage

Program and Erase

Endurance

Operating Ambient Temperature

Package

-20 to 85°C, -40 to 85°C

100-pin plastic mold QFP, LQFP

NOTES:

2

1. I C bus is a registered trademark of Koninklijke Philips Electronics N. V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

3. Use the M16C/30P on VCC1 = VCC2.

Rev.1.22 Mar 30, 2007 Page 2 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

1.3

Block Diagram

Figure 1.1 is a M16C/30P Group Block Diagram.

8

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

Internal peripheral functions

Timer (16-bit)

System clock

generation circuit

A/D converter

(10 bits X 18 channels)

XIN-XOUT

XCIN-XCOUT

Output (timer A): 3

Input (timer B): 3

UART or

clock synchronous serial I/O

(3 channels)

CRC arithmetic circuit (CCITT )

(Polynomial : X¹⁶+X¹²+X⁵+1)

M16C/60 series16-bit CPU core

Memory

ROM ⁽¹⁾

SB

R0H

R1H

R0L

R1L

Watchdog timer

(15 bits)

USP

ISP

R2

R3

RAM ⁽²⁾

INTB

PC

FLG

DMAC

(2 channels)

A0

A1

FB

Multiplier

NOTES :

1. ROM size depends on microcomputer type.

2. RAM size depends on microcomputer type.

Figure 1.1

M16C/30P Group Block Diagram

Rev.1.22 Mar 30, 2007 Page 3 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

1.4

Product List

Table 1.2 lists the M16C/30P group products and Figure 1.2 shows the Part No., Memory Size, and Package. Table

1.4 lists Product Code of MASK ROM version for M16C/30P. Figure 1.3 shows the Marking Diagram of Mask

ROM Version for M16C/30P (Top View). Table 1.5 lists Product Code of One Time Flash version, Flash Memory

version, and ROM-less version for M16C/30P. Figure 1.4 shows the Marking Diagram of One Time Flash version,

Flash Memory version, and ROM-less Version for M16C/30P (Top View). Please specify the marking for

M16C30P (MASK ROM version) when placing an order for ROM.

Table 1.2

Product List (1)

Part No. ROM Capacity

96 Kbytes

As of March 2007

RAM Capacity

5 Kbytes

package code ⁽¹⁾

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

Remarks

M30302MAP-XXXFP

M30302MAP-XXXGP

M30302MCP-XXXFP

M30302MCP-XXXGP

M30302MDP-XXXFP

M30302MDP-XXXGP

M30302MEP-XXXFP

M30302MEP-XXXGP

M30302GAPFP

Mask ROM version

128 Kbytes

160 Kbytes

192 Kbytes

96 Kbytes

6 Kbytes

5 Kbytes

One Time Flash

version

(blank product)

M30302GAPGP

(D)

M30302GCPFP

128 Kbytes

160 Kbytes

M30302GCPGP

M30302GDPFP

6 Kbytes

12 Kbytes

6 Kbytes

12 Kbytes

5 Kbytes

M30302GDPGP

(D)

M30304GDPFP

M30304GDPGP

M30302GEPFP

192 Kbytes

M30302GEPGP

(D)

M30304GEPFP

M30304GEPGP

M30302GGPFP

(D) 256 Kbytes

M30302GGPGP

(D)

M30302GAP-XXXFP

M30302GAPvGP

96 Kbytes

One Time Flash

version

(factory programmed

product)

(D)

M30302GCP-XXXFP

M30302GCP-XXXGP

M30302GDP-XXXFP

M30302GDP-XXXGP

M30304GDP-XXXFP

M30304GDP-XXXGP

M30302GEP-XXXFP

M30302GEP-XXXGP

M30304GEP-XXXFP

M30304GEP-XXXGP

M30302GGP-XXXFP

M30302GGP-XXXGP

128 Kbytes

(D)

160 Kbytes

6 Kbytes

12 Kbytes

6 Kbytes

12 Kbytes

(D)

192 Kbytes

(D)

(D) 256 Kbytes

(D)

(D): Under development

(P): Under planning

NOTES:

1. Previous package codes are as follows.

PRQP0100JB-A : 100P6S-A,

PLQP0100KB-A : 100P6Q-A

2. Block A (4-Kbytes space) is available in flash memory version.

Rev.1.22 Mar 30, 2007 Page 4 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

Table 1.3

Product List (2)

Part No. ROM Capacity

As of March 2007

RAM Capacity

5 Kbytes

package code ⁽¹⁾

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

PRQP0100JB-A

PLQP0100KB-A

Remarks

Flash memory

version⁽²⁾

M30302FAPFP

M30302FAPGP

M30302FCPFP

M30302FCPGP

M30302FEPFP

M30302FEPGP

M30302SPFP

M30302SPGP

96 K + 4 Kbytes

128 K + 4 Kbytes

192 K + 4 Kbytes

-

6 Kbytes

ROM-less version

(D): Under development

(P): Under planning

NOTES:

1. Previous package codes are as follows.

PRQP0100JB-A : 100P6S-A,

PLQP0100KB-A : 100P6Q-A

2. Block A (4-Kbytes space) is available in flash memory version.

Part No.

M 3 0 3 0 2 M E P - X X X H P

Package type:

FP : Package PRQP0100JB-A (100P6S-A)

GP : Package PLQP0100KB-A (100P6Q-A)

ROM No.

M16C/30P Group

ROM capacity:

A :

96 Kbytes

C : 128 Kbytes

D : 160 Kbytes

E : 192 Kbytes

G : 256 Kbytes

Memory type:

M : Mask ROM version

G : One Time Flash version

F : Flash Memory version

S : ROM-less version

Shows RAM capacity, pin count, etc

(The value itself has no specific meaning)

M16C/30 Series

M16C Family

Figure 1.2

Part No., Memory Size, and Package

Rev.1.22 Mar 30, 2007 Page 5 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

Table 1.4

Product Code of MASK ROM version for M16C/30P

Product Code

Package

Lead-free

Operating Ambient Temperature

-20°C to 85°C

U1

U4

-40°C to 85°C

PRQP0100JB-A (100P6S-A)

1. Standard Renesas Mark

M 1 6 C

M3 0 3 0 2 M D P - X X X F P

U 1 X X X X X X X

Part No. (See Figure 1.2 Part No., Memory Size, and Package)

Chip version, product code and date code

A

: Shows chip version.

Henceforth, whenever it changes a version,

it continues with A, B, and C.

: Shows Product code. (See table 1.3 Product Code)

U1

XXXXXXX : Seven digits

2. Customer’s Parts Number + Renesas catalog name

Part No. (See Figure 1.2 Part No., Memory Size, and Package)

Chip version and product code

M3 0 3 0 2 M D P - X X X F P

U 1

M1 6 C X X X X X X X

A

: Shows chip version.

Henceforth, whenever it changes a version,

it continues with A, B, and C.

U1

: Shows Product code. (See table 1.3 Product Code)

Date code seven digits

PLQP0100KB-A (100P6Q-A)

1. Standard Renesas Mark

M 1 6 C

M 3 0 3 0 2 MD P

- X X X GP

Part No. (See Figure 1.2 Part No., Memory Size, and Package)

A

U 1 X X X X X X X

Chip version, product code and date code

A

: Shows chip version.

Henceforth, whenever it changes a version,

it continues with A, B, and C.

U1

: Shows Product code. (See table 1.3 Product Code)

XXXXXXX : Seven digits

2. Customer’s Parts Number + Renesas catalog name

Part No. (See Figure 1.2 Part No., Memory Size, and Package)

Chip version and product code

M 3 0 3 0 2 MD P

U 1 - X X X G P

M 1 6 C X X X X X X X

A

: Shows chip version.

Henceforth, whenever it changes a version,

it continues with A, B, and C.

U1

: Shows Product code. (See table 1.3 Product Code)

Date code seven digits

NOTES:

1. Refer to the mark specification form for details of the Mask ROM version marking.

Figure 1.3

Marking Diagram of Mask ROM Version for M16C/30P (Top View)

Rev.1.22 Mar 30, 2007 Page 6 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

Table 1.5

Product Code of One Time Flash version, Flash Memory version, and ROM-less

version for M16C/30P

Internal ROM

Program

and Erase

Endurance

Operating

Ambient

Temperature

Product

Code

Package

Temperature

Range

0°C to 60°C

One Time Flash

version

U3

U5

U3

U5

U3

U5

Lead-

free

0

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

0°C to 60°C

Flash Memory

version

Lead-

free

100

−

ROM-less version

Lead-

free

NOTES:The one time flash version can be written once only.

PRQP0100JB-A (100P6S-A)

M 1 6 C

Part No. (See Figure 1.2 Part No., Memory Size, and Package)

M 3 0 3 0 2 S P F P

U 3

X X X X X X X

Chip version and product code

A

: Shows chip version.

Henceforth, whenever it changes a version,

it continues with A, B, and C.

U3

: Shows Product code. (See table 1.3 Product Code)

Date code seven digits

PLQP0100KB-A (100P6Q-A)

M 1 6 C

Part No. (See Figure 1.2 Part No., Memory Size, and Package)

M 3 0 3 0 2 S P G P

A

U 3

Chip version and product code

A

: Shows chip version.

X X X X X X X

Henceforth, whenever it changes a version,

it continues with A, B, and C.

U3

: Shows Product code. (See table 1.3 Product Code)

Date code seven digits

The product without marking of chip version of One Time Flash version, Flash

Memory version, and the ROMless version corresponds to the chip version “A”.

Figure 1.4

Marking Diagram of One Time Flash version, Flash Memory version, and ROM-less

Version for M16C/30P (Top View)

Rev.1.22 Mar 30, 2007 Page 7 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

1.5

Pin Configuration

Figures 1.5 to 1.6 show the pin configurations (top view).

PIN CONFIGURATION (top view)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

P4_4/CS0

P4_5/CS1

P4_6/CS2

P4_7/CS3

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

P5_4/HLDA

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3

P10_2/AN2

P10_1/AN1

AVSS

P10_0/AN0

VREF

AVCC

P9_7/ADTRG

P5_5/HOLD

P5_6/ALE

M16C/30P Group

P5_7/RDY/CLKOUT

P6_0/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

P6_6/RXD1/SCL1

36

35

34

33

32

31

P6_7/TXD1/SDA1

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

2. Use the M16C/30P on VCC1=VCC2.

Package : PRQP0100JB-A (100P6S-A)

Figure 1.5

Pin Configuration (Top View)

Rev.1.22 Mar 30, 2007 Page 8 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

PIN CONFIGURATION (top view)

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P1_2/D10

P1_1/D9

P1_0/D8

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P4_2/A18

P4_3/A19

P4_4/CS0

P4_5/CS1

P4_6/CS2

P4_7/CS3

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3

P10_2/AN2

P10_1/AN1

AVSS

P10_0/AN0

VREF

AVCC

P9_7/ADTRG

P9_6/ANEX1

P9_5/ANEX0

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

P5_4/HLDA

P5_5/HOLD

P5_6/ALE

P5_7/CLKOUT

P6_0/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

P6_6/RXD1/SCL1

M16C/30P Group

P6_7/TXD1/SDA1

P7_0/TXD2/SDA2/TA0OUT⁽¹⁾

P7_1/RXD2/SCL2/TA0IN⁽¹⁾

P7_2/CLK2/TA1OUT

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

2. Use the M16C/30P on VCC1=VCC2.

Package : PLQP0100KB-A (100P6Q-A)

Figure 1.6

Pin Configuration (Top View)

Rev.1.22 Mar 30, 2007 Page 9 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

Table 1.6

Pin Characteristics (1)

Pin No.

Control

Bus Control

Port

Interrupt Pin

Timer Pin

UART Pin

Analog Pin

FP GP

1

2

99

100

1

P9_6

P9_5

P9_4

P9_3

P9_2

P9_1

P9_0

ANEX1

ANEX0

3

4

2

5

3

TB2IN

6

4

TB1IN

TB0IN

7

5

8

6

BYTE

9

7

CNVSS

XCIN

10

11

12

13

14

15

16

17

8

P8_7

P8_6

9

XCOUT

10

RESET

11 XOUT

12 VSS

13 XIN

14 VCC1

15

P8_5

P8_4

P8_3

NMI

18

19

16

17

INT2

INT1

INT0

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

P8_2

P8_1

P8_0

P7_7

P7_6

P7_5

P7_4

TA2IN

TA2OUT

P7_3

P7_2

P7_1

P7_0

P6_7

P6_6

P6_5

TA1IN

CTS2/RTS2

TA1OUT

TA0IN

CLK2

RXD2/SCL2

TXD2/SDA2

TXD1/SDA1

RXD1/SCL1

CLK1

TA0OUT

P6_4

P6_3

P6_2

P6_1

CTS1/RTS1/CTS0/CLKS1

TXD0/SDA0

RXD0/SCL0

CLK0

P6_0

P5_7

P5_6

P5_5

P5_4

P5_3

P5_2

P5_1

P5_0

P4_7

P4_6

P4_5

P4_4

CTS0/RTS0

39

40

41

42

43

44

45

46

47

48

49

50

37

38

39

40

41

42

43

44

45

46

47

48

RDY/CLKOUT

ALE

HOLD

HLDA

BCLK

RD

WRH/BHE

WRL/WR

CS3

CS2

CS1

CS0

Rev.1.22 Mar 30, 2007 Page 10 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

Table 1.7

Pin Characteristics (2)

Pin No.

Control Pin Port

Interrupt Pin

Timer Pin

UART Pin

Analog Pin Bus Control Pin

FP GP

51

52

49

50

51

52

P4_3

P4_2

P4_1

P4_0

P3_7

P3_6

P3_5

P3_4

P3_3

P3_2

P3_1

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

53

54

55

56

57

58

59

60 VCC2

61

P3_0

A8

62 VSS

63

P2_7

P2_6

P2_5

P2_4

P2_3

P2_2

P2_1

P2_0

A7

A6

A5

A4

A3

A2

A1

A0

64

65

66

67

68

69

70

71

P1_7

P1_6

D15

D14

74

72

INT4

INT3

75

76

77

78

73

74

75

76

P1_5

P1_4

P1_3

P1_2

D13

D12

D11

D10

79

77

P1_1

D9

D8

80

81

82

83

84

85

86

87

88

89

78

79

80

81

82

83

84

85

86

87

P1_0

P0_7

P0_6

P0_5

P0_4

P0_3

P0_2

P0_1

P0_0

AN0_7

D7

D6

D5

D4

D3

D2

D1

D0

AN0_6

AN0_5

AN0_4

AN0_3

AN0_2

AN0_1

AN0_0

P10_7 KI3

P10_6 KI2

P10_5 KI1

AN7

AN6

AN5

90

91

88

89

92

93

94

95

96

97

98

90

P10_4 KI0

P10_3

AN4

AN3

AN2

AN1

91

92

P10_2

93

P10_1

94 AVSS

95

P10_0

P9_7

AN0

96 VREF

99

97 AVCC

100 98

ADTRG

Rev.1.22 Mar 30, 2007 Page 11 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

1.6

Pin Description

Table 1.8

Pin Description (1)

Pin Name

Signal Name

I/O Type

I

Description

Power supply input VCC1, VCC2

VSS

Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS

pin. The VCC apply condition is that VCC1 = VCC2.

Analog power

supply input

AVCC

AVSS

I

Applies the power supply for the A/D converter. Connect the AVCC

pin to VCC1. Connect the AVSS pin to VSS.

Reset input

The microcomputer is in a reset state when applying “L” to the this

pin.

RESET

CNVSS

Switches processor mode. Connect this pin to VSS to when after

a reset to start up in single-chip mode. Connect this pin to VCC1 to

start up in microprocessor mode.

External data bus

width select input

BYTE

I

Switches the data bus in external memory space. The data bus is

16 bits long when the this pin is held "L" and 8 bits long when the

this pin is held "H". Set it to either one. Connect this pin to VSS

when an single-chip mode.

Bus control pins

D0 to D7

I/O

Inputs and outputs data (D0 to D7) when these pins are set as the

separate bus.

D8 to D15

Inputs and outputs data (D8 to D15) when external 16-bit data bus

is set as the separate bus.

A0 to A19

O

Output address bits (A0 to A19).

CS0 to CS3

Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to

specify an external space.

WRL/WR

WRH/BHE

RD

O

Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or

BHE and WR can be switched by program.

• WRL, WRH and RD are selected

The WRL signal becomes "L" by writing data to an even address in

an external memory space.

The WRH signal becomes "L" by writing data to an odd address in

an external memory space.

The RD pin signal becomes "L" by reading data in an external

memory space.

• WR, BHE and RD are selected

The WR signal becomes "L" by writing data in an external memory space.

The RD signal becomes "L" by reading data in an external memory space.

The BHE signal becomes "L" by accessing an odd address.

Select WR, BHE and RD for an external 8-bit data bus.

ALE

O

I

ALE is a signal to latch the address.

HOLD

While the HOLD pin is held "L", the microcomputer is placed in a

hold state.

HLDA

RDY

O

I

In a hold state, HLDA outputs a "L" signal.

While applying a "L" signal to the RDY pin, the microcomputer is

placed in a wait state.

I : Input O : Output I/O : Input and output

Rev.1.22 Mar 30, 2007 Page 12 of 53

REJ03B0088-0122

M16C/30P Group

1.Overview

Table 1.9

Pin Description (2)

Pin Name I/O Type

XIN

Signal Name

Description

Main clock

input

I

I/O pins for the main clock generation circuit. Connect a ceramic

resonator or crystal oscillator between XIN and XOUT. To use the

external clock, input the clock from XIN and leave XOUT open.

Main clock

output

XOUT

XCIN

O

I

Sub clock

input

I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator

between XCIN and XCOUT. To use the external clock, input the clock

from XCIN and leave XCOUT open.

Sub clock

output

XCOUT

O

Clock output

CLKOUT

O

I

The clock of the same cycle as fC, f8, or f32 is outputted.

Input pins for the INT interrupt.

INT interrupt

input

INT0 to INT4

I

NMI interrupt NMI

Input pin for the NMI interrupt.

input

Key input

interrupt input

I

Input pins for the key input interrupt.

KI0 to KI3

Timer A

TA0OUT to

TA2OUT

I/O

These are timer A0 to timer A2 I/O pins. (however, the output of

TA0OUT for the N-channel open drain output.)

TA0IN to TA2IN

TB0IN to TB2IN

I

These are timer A0 to timer A2 input pins.

These are timer B0 to timer B2 input pins.

These are send control input pins.

Timer B

Serial

interface

CTS0 to CTS2

O

These are receive control output pins.

RTS0 to RTS2

CLK0 to CLK2

RXD0 to RXD2

TXD0 to TXD2

I/O

I

These are transfer clock I/O pins.

These are serial data input pins.

O

These are serial data output pins. (however, TXD2 for the N-channel

open drain output.)

CLKS1

O

This is output pin for transfer clock output from multiple pins function.

I²C mode

SDA0 to SDA2

I/O

These are serial data I/O pins. (however, SDA2 for the N-channel

open drain output.)

SCL0 to SCL2

VREF

I/O

These are transfer clock I/O pins. (however, SCL2 for the N-channel

open drain output.)

Reference

voltage input

I

Applies the reference voltage for the A/D converter.

Analog input pins for the A/D converter.

This is an A/D trigger input pin.

A/D converter AN0 to AN7,

AN0_0 to AN0_7

I

ADTRG

ANEX0

I/O

This is the extended analog input pin for the A/D converter, and is the

output in external op-amp connection mode.

ANEX1

I

This is the extended analog input pin for the A/D converter.

I/O port

P0_0 to P0_7,

P1_0 to P1_7,

P2_0 to P2_7,

P3_0 to P3_7,

P4_0 to P4_7,

P5_0 to P5_7,

P6_0 to P6_7,

P7_0 to P7_7,

P9_0 to P9_7,

P10_0 to P10_7

I/O

8-bit I/O ports in CMOS, having a direction register to select an input

or output.

Each pin is set as an input port or output port. An input port can be set

for a pull-up or for no pull-up in 4-bit unit by program. (however, P7_0

and P7_1 for the N-channel open drain output.)

P8_0 to P8_4,

P8_6, P8_7

I/O

I

I/O ports having equivalent functions to P0.

Input port

P8_5

Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit

in the P8 register.

I : Input O : Output I/O : Input and output

Rev.1.22 Mar 30, 2007 Page 13 of 53

REJ03B0088-0122

M16C/30P Group

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a

register bank. There are two register banks.

b31

b15

b8b7

b0

R2

R3

R0H

R1H

R0L

R1L

Data Registers ⁽¹⁾

R2

R3

A0

A1

FB

Address Registers ⁽¹⁾

Frame Base Registers ⁽¹⁾

b19

b15

b0

Interrupt Table Register

Program Counter

INTBH

INTBL

b19

b0

PC

b15

USP

ISP

SB

User Stack Pointer

Interrupt Stack Pointer

Static Base Register

b15

b0

FLG

O B

Flag Register

b15

b8 b7

IPL

U

I

S

Z

D C

Carry Flag

Debug Flag

Zero Flag

Sign Flag

Register Bank Select Flag

Overflow Flag

Interrupt Enable Flag

Stack Pointer Select Flag

Reserved Area

Processor Interrupt Priority Level

Reserved Area

NOTES:

1. These registers comprise a register bank. There are two register banks.

Figure 2.1

Central Processing Unit Register

2.1

Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are

the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data

register (R2R0). R3R1 is the same as R2R0.

Rev.1.22 Mar 30, 2007 Page 14 of 53

REJ03B0088-0122

M16C/30P Group

2. Central Processing Unit (CPU)

2.2

Address Registers (A0 and A1)

The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative

addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

2.3

Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4

Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5

Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7

Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8

Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1

Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2

Debug Flag (D Flag)

The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3

Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4

Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

2.8.5

Register Bank Select Flag (B Flag)

Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.

2.8.6

Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7

Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag

is cleared to “0” when the interrupt request is accepted.

Rev.1.22 Mar 30, 2007 Page 15 of 53

REJ03B0088-0122

M16C/30P Group

2. Central Processing Unit (CPU)

2.8.8

Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.

The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software

interrupt Nos. 0 to 31 is executed.

2.8.9

Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0

to level 7.

If a requested interrupt has priority greater than IPL, the interrupt is enabled.

2.8.10 Reserved Area

When write to this bit, write “0”. When read, its content is indeterminate.

Rev.1.22 Mar 30, 2007 Page 16 of 53

REJ03B0088-0122

M16C/30P Group

3.Memory

3. Memory

Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1 Mbyte from address 00000h to

FFFFFh.

The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte

internal ROM is allocated to the addresses from F0000h to FFFFFh.

The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start

address of each interrupt routine here.

The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 5-Kbyte

internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the internal RAM also

stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses

from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no

functions allocated is reserved for future use and cannot be used by users.

The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS

or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.

00000h

SFR

00400h

Internal RAM

XXXXXh

Reserved area ⁽¹⁾

FFE00h

0F000h

Internal ROM

(data area) ^{(3, 4)}

0FFFFh

Special page

vector table

10000h

External area

27000h

28000h

Reserved area

External area

FFFDCh

Undefined instruction

Overflow

BRK instruction

(5)

Internal RAM

Internal ROM

Size

Address XXXXXh

017FFh

Size

Address YYYYYh

E8000h

Address match

D0000h

5 Kbytes

6 Kbytes

12 Kbytes

96 Kbytes

128 Kbytes

160 Kbytes

Reserved area ^{(2, 4)}

Single step

Watchdog timer

01BFFh

E0000h

YYYYYh

033FFh

D8000h

DBC

NMI

Reset

Internal ROM

192 Kbytes

256 Kbytes

D0000h

(program area) ⁽⁵⁾

C0000h⁽⁶⁾

FFFFFh

NOTES:

1. During memory expansion and microprocessor modes, can be used.

2. In memory expansion mode, can be used.

3. As for the flash memory version, 4-Kbyte space (block A) exists.

4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1” .

5. When using the masked ROM version, write nothing to internal ROM area.

6. When the PM13 bit is set to "0", the address of Internal ROM becomes D0000h, and when

the PM13 bit is set to "1", the address becomes C0000h.

Figure 3.1

Memory Map

Rev.1.22 Mar 30, 2007 Page 17 of 53

REJ03B0088-0122

M16C/30P Group

4. Special Function Register (SFR)

SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.5 list the SFR

information.

(1)

Table 4.1

SFR Information (1)

Address

0000h

Register

Symbol

After Reset

0001h

0002h

0003h

0004h

(2)

00000000b(CNVSS pin is “L”)

00000011b(CNVSS pin is “H”)

Processor Mode Register 0

PM0

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

Processor Mode Register 1

PM1

CM0

CM1

CSR

AIER

PRCR

00XXX0X0b

01001000b

00100000b

00000001b

XXXXXX00b

XX000000b

System Clock Control Register 0

System Clock Control Register 1

Chip Select Control Register

Address Match Interrupt Enable Register

Protect Register

Watchdog Timer Start Register

Watchdog Timer Control Register

Address Match Interrupt Register 0

WDTS

WDC

RMAD0

XXh

00XXXXXXb

00h

X0h

Address Match Interrupt Register 1

RMAD1

00h

X0h

DMA0 Source Pointer

DMA0 Destination Pointer

DMA0 Transfer Counter

DMA0 Control Register

DMA1 Source Pointer

DMA1 Destination Pointer

DMA1 Transfer Counter

DMA1 Control Register

SAR0

XXh

DAR0

XXh

TCR0

XXh

DM0CON

SAR1

00000X00b

XXh

DAR1

XXh

TCR1

XXh

DM1CON

00000X00b

NOTES:

1. The blank areas are reserved and cannot be accessed by users.

2. The PM00 and PM01 bits do not change at software reset.

X : Nothing is mapped to this bit

Rev.1.22 Mar 30, 2007 Page 18 of 53

REJ03B0088-0122

M16C/30P Group

4. Special Function Register (SFR)

(1)

Table 4.2

SFR Information (2)

Address

0040h

Register

Symbol

After Reset

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

to

INT3 Interrupt Control Register

INT3IC

XX00X000b

UART1 BUS Collision Detection Interrupt Control Register

UART0 BUS Collision Detection Interrupt Control Register

U1BCNIC

U0BCNIC

XXXXX000b

INT4 Interrupt Control Register

UART2 Bus Collision Detection Interrupt Control Register

DMA0 Interrupt Control Register

DMA1 Interrupt Control Register

Key Input Interrupt Control Register

A/D Conversion Interrupt Control Register

UART2 Transmit Interrupt Control Register

UART2 Receive Interrupt Control Register

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

UART1 Transmit Interrupt Control Register

UART1 Receive Interrupt Control Register

Timer A0 Interrupt Control Register

INT4IC

BCNIC

DM0IC

DM1IC

KUPIC

ADIC

S2TIC

S2RIC

S0TIC

S0RIC

S1TIC

S1RIC

TA0IC

TA1IC

TA2IC

XX00X000b

XXXXX000b

Timer A1 Interrupt Control Register

Timer A2 Interrupt Control Register

Timer B0 Interrupt Control Register

Timer B1 Interrupt Control Register

Timer B2 Interrupt Control Register

INT0 Interrupt Control Register

INT1 Interrupt Control Register

INT2 Interrupt Control Register

TB0IC

TB1IC

TB2IC

INT0IC

INT1IC

INT2IC

XXXXX000b

XX00X000b

01AFh

01B0h

01B1h

01B2h

01B3h

01B4h

01B5h

01B6h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

01C0h

to

(2)

Flash Memory Control Register 1

FMR1

FMR0

0X00XX0Xb

00000001b

(3)

Flash Memory Control Register 0

024Fh

0250h

0251h

0252h

0253h

0254h

0255h

0256h

0257h

0258h

0259h

025Ah

025Bh

025Ch

025Dh

025Eh

025Fh

0260h

to

Peripheral Clock Select Register

PCLKR

00000011b

033Fh

NOTES:

1. The blank areas are reserved and cannot be accessed by users.

2. This register is included in the flash memory version.

3. This register is included in the flash memory version and one time flash version.

X : Nothing is mapped to this bit

Rev.1.22 Mar 30, 2007 Page 19 of 53

REJ03B0088-0122

M16C/30P Group

4. Special Function Register (SFR)

(1)

Table 4.3

SFR Information (3)

Address

0340h

0341h

0342h

0343h

0344h

0345h

0346h

0347h

0348h

0349h

034Ah

034Bh

034Ch

034Dh

034Eh

034Fh

0350h

0351h

0352h

0353h

0354h

0355h

0356h

0357h

0358h

0359h

035Ah

035Bh

035Ch

035Dh

Register

Symbol

After Reset

035Eh

035Fh

0360h

0361h

0362h

0363h

0364h

0365h

0366h

0367h

0368h

0369h

036Ah

036Bh

036Ch

036Dh

036Eh

036Fh

0370h

0371h

0372h

0373h

0374h

0375h

0376h

0377h

0378h

0379h

037Ah

037Bh

037Ch

037Dh

037Eh

037Fh

Interrupt Factor Select Register 2

Interrupt Factor Select Register

IFSR2A

IFSR

00XXXXXXb

00h

UART0 Special Mode Register 4

UART0 Special Mode Register 3

UART0 Special Mode Register 2

UART0 Special Mode Register

UART1 Special Mode Register 4

UART1 Special Mode Register 3

UART1 Special Mode Register 2

UART1 Special Mode Register

UART2 Special Mode Register 4

UART2 Special Mode Register 3

UART2 Special Mode Register 2

UART2 Special Mode Register

U0SMR4

U0SMR3

U0SMR2

U0SMR

U1SMR4

U1SMR3

U1SMR2

U1SMR

U2SMR4

U2SMR3

U2SMR2

U2SMR

U2MR

00h

000X0X0Xb

X0000000b

00h

000X0X0Xb

X0000000b

00h

000X0X0Xb

X0000000b

00h

XXh

00001000b

00000010b

XXh

UART2 Transmit/Receive Mode Register

UART2 Bit Rate Generator

UART2 Transmit Buffer Register

U2BRG

U2TB

UART2 Transmit/Receive Control Register 0

UART2 Transmit/Receive Control Register 1

UART2 Receive Buffer Register

U2C0

U2C1

U2RB

XXh

NOTES:

1. The blank areas are reserved and cannot be accessed by users.

X : Nothing is mapped to this bit

Rev.1.22 Mar 30, 2007 Page 20 of 53

REJ03B0088-0122

M16C/30P Group

4. Special Function Register (SFR)

(1)

Table 4.4

SFR Information (4)

Address

Register

Symbol

TABSR

After Reset

000XX000b

0380h

0381h

0382h

0383h

0384h

0385h

0386h

0387h

0388h

0389h

038Ah

038Bh

038Ch

038Dh

038Eh

038Fh

0390h

0391h

0392h

0393h

0394h

0395h

0396h

0397h

0398h

0399h

039Ah

039Bh

039Ch

039Dh

039Eh

039Fh

03A0h

03A1h

03A2h

03A3h

03A4h

03A5h

03A6h

03A7h

03A8h

03A9h

03AAh

03ABh

03ACh

03ADh

03AEh

03AFh

03B0h

03B1h

03B2h

03B3h

03B4h

03B5h

03B6h

03B7h

03B8h

03B9h

03BAh

03BBh

03BCh

03BDh

03BEh

03BFh

Count Start Flag

Clock Prescaler Reset Fag

One-Shot Start Flag

Trigger Select Register

Up-Down Flag

CPSRF

ONSF

TRGSR

UDF

0XXXXXXXb

00XXX000b

XXXX0000b

(2)

XX0XX000b

Timer A0 Register

Timer A1 Register

Timer A2 Register

TA0

TA1

TA2

XXh

Timer B0 Register

Timer B1 Register

Timer B2 Register

TB0

TB1

TB2

XXh

00h

Timer A0 Mode Register

Timer A1 Mode Register

Timer A2 Mode Register

TA0MR

TA1MR

TA2MR

Timer B0 Mode Register

Timer B1 Mode Register

Timer B2 Mode Register

TB0MR

TB1MR

TB2MR

00XX0000b

UART0 Transmit/Receive Mode Register

UART0 Bit Rate Generator

UART0 Transmit Buffer Register

U0MR

U0BRG

U0TB

00h

XXh

00001000b

00000010b

XXh

00h

XXh

00001000b

00000010b

XXh

X0000000b

UART0 Transmit/Receive Control Register 0

UART0 Transmit/Receive Control Register 1

UART0 Receive Buffer Register

U0C0

U0C1

U0RB

UART1 Transmit/Receive Mode Register

UART1 Bit Rate Generator

UART1 Transmit Buffer Register

U1MR

U1BRG

U1TB

UART1 Transmit/Receive Control Register 0

UART1 Transmit/Receive Control Register 1

UART1 Receive Buffer Register

U1C0

U1C1

U1RB

UART Transmit/Receive Control Register 2

UCON

DMA0 Request Factor Select Register

DMA1 Request Factor Select Register

CRC Data Register

DM0SL

DM1SL

CRCD

00h

XXh

CRC Input Register

CRCIN

NOTES:

1. The blank areas are reserved and cannot be accessed by users.

2. Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate.

X : Nothing is mapped to this bit

Rev.1.22 Mar 30, 2007 Page 21 of 53

REJ03B0088-0122

M16C/30P Group

4. Special Function Register (SFR)

(1)

Table 4.5

SFR Information (5)

Address

Register

Symbol

After Reset

03C0h

03C1h

03C2h

03C3h

03C4h

03C5h

03C6h

03C7h

03C8h

03C9h

03CAh

03CBh

03CCh

03CDh

03CEh

03CFh

03D0h

03D1h

03D2h

03D3h

03D4h

03D5h

03D6h

03D7h

03D8h

03D9h

03DAh

03DBh

03DCh

03DDh

03DEh

03DFh

03E0h

03E1h

03E2h

03E3h

03E4h

03E5h

03E6h

03E7h

03E8h

03E9h

03EAh

03EBh

03ECh

03EDh

03EEh

03EFh

03F0h

03F1h

03F2h

03F3h

03F4h

03F5h

03F6h

03F7h

03F8h

03F9h

03FAh

03FBh

03FCh

03FDh

A/D Register 0

A/D Register 1

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

XXh

A/D Register 2

A/D Register 3

A/D Register 4

A/D Register 5

A/D Register 6

A/D Register 7

A/D Control Register 2

ADCON2

XXX000X0b

A/D Control Register 0

A/D Control Register 1

ADCON0

ADCON1

000X0XXXb

00000XXXb

Port P0 Register

Port P1 Register

Port P0 Direction Register

Port P1 Direction Register

Port P2 Register

P0

P1

PD0

PD1

P2

XXh

00h

XXh

00h

Port P3 Register

P3

Port P2 Direction Register

Port P3 Direction Register

Port P4 Register

PD2

PD3

P4

00h

XXh

00h

Port P5 Register

P5

Port P4 Direction Register

Port P5 Direction Register

Port P6 Register

PD4

PD5

P6

00h

XXh

00h

Port P7 Register

P7

Port P6 Direction Register

Port P7 Direction Register

Port P8 Register

PD6

PD7

P8

00h

XXh

00X00000b

00h

Port P9 Register

P9

Port P8 Direction Register

Port P9 Direction Register

Port P10 Register

PD8

PD9

P10

XXh

Port P10 Direction Register

PD10

00h

Pull-Up Control Register 0

Pull-Up Control Register 1

PUR0

PUR1

00h

(2)

00000000b

00000010b

00h

(2)

03FEh

03FFh

Pull-Up Control Register 2

Port Control Register

PUR2

PCR

00h

NOTES:

1. The blank areas are reserved and cannot be accessed by users.

2. At hardware reset, the register is as follows:

• “00000000b” where “L” is inputted to the CNVSS pin

• “00000010b” where “H” is inputted to the CNVSS pin

At software reset, the register is as follows:

• “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode).

• “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or “11b” (microprocessor mode).

X : Nothing is mapped to this bit

Rev.1.22 Mar 30, 2007 Page 22 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

Table 5.1

Absolute Maximum Ratings

Symbol

VCC

Parameter

Supply Voltage(VCC1=VCC2)

Analog Supply Voltage

Condition

Rated Value

−0.3 to 6.5

Unit

V

VCC1=VCC2=AVCC

AVCC

VI

−0.3 to 6.5

V

Input Voltage

−0.3 to VCC+0.3

V

RESET, CNVSS, BYTE,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

VREF, XIN

P7_0, P7_1

−0.3 to 6.5

V

VO

Output

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

XOUT

−0.3 to VCC+0.3

Voltage

P7_0, P7_1

−0.3 to 6.5

300

V

Pd

Power Dissipation

−40°C<Topr≤85°C

mW

°C

Topr

Operating

Ambient

When the Microcomputer is Operating

−20 to 85 / −40 to 85

Temperature

One Time Flash Program Erase

Flash Program Erase

0 to 60

Tstg

Storage Temperature

−65 to 150

°C

Rev.1.22 Mar 30, 2007 Page 23 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

(1)

Table 5.2

Recommended Operating Conditions

Standard

Unit

Symbol

Parameter

Min.

2.7

Typ.

5.0

VCC

0

Max.

5.5

VCC

AVCC

VSS

Supply Voltage (VCC1=VCC2)

Analog Supply Voltage

Supply Voltage

V

AVSS

VIH

Analog Supply Voltage

0

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7

HIGH Input

Voltage

0.8VCC

VCC

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(during single-chip mode)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(data input during memory expansion and microprocessor mode)

0.5VCC

0.8VCC

VCC

V

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7, XIN, RESET, CNVSS, BYTE

P7_0, P7_1

0.8VCC

6.5

V

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7

VIL

LOW Input

Voltage

0

0.2VCC

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(during single-chip mode)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

0

0.16VCC

V

(data input during memory expansion and microprocessor mode)

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,

XIN, RESET, CNVSS, BYTE

0.2VCC

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

IOH(peak)

IOH(avg)

IOL(peak)

IOL(avg)

f(XIN)

HIGH Peak

Output Current

−10.0

mA

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

HIGH Average

Output Current

−5.0

10.0

5.0

mA

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

LOW Peak

Output Current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

LOW Average

Output Current

mA

VCC=3.0V to 5.5V

VCC=2.7V to 3.0V

Main Clock Input

Oscillation

Frequency ⁽⁴⁾

0

16

MHz

20×VCC1−44 MHz

f(XCIN)

f(BCLK)

Sub-Clock Oscillation Frequency

CPU Operation Clock

32.768

50

16

kHz

0

MHz

NOTES:

1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.

2. The Average Output Current is the mean value within 100ms.

3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9 and P10 must be 80mA max. The total IOL(peak) for ports P3, P4, P5,

P6, P7 and P8_0 to P8_4 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must be −40mA max. The total

IOH(peak) for ports P3, P4 and P5 must be −40mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be −40mA

max.

The total IOH(peak) for ports P8_6, P8_7 and P9 must be −40mA max. Set Average Output Current to 1/2 of peak.

4. Relationship between main clock oscillation frequency, and supply voltage.

Main clock input oscillation frequency

20 x VCC1-44MHz

16.0

10.0

0.0

2.7

3.0

5.5

VCC1[V] (main clock: no division)

Rev.1.22 Mar 30, 2007 Page 24 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

(1)

Table 5.3

A/D Conversion Characteristics

Standard

Unit

Symbol

Parameter

Measuring Condition

Min.

Typ.

Max.

10

−

Resolution

VREF=VCC

Bits

INL

Integral Non-Linearity

Error

10bit

VREF= AN0 to AN7 input,

±5

LSB

VCC=

5V

AN0_0 to AN0_7 input,

ANEX0, ANEX1 input

VREF= AN0 to AN7 input,

±7

LSB

VCC=

3.3V

AN0_0 to AN0_7 input,

ANEX0, ANEX1 input

8bit

VREF=VCC=5V, 3.3V

±2

±5

LSB

−

Absolute Accuracy

10bit

VREF= AN0 to AN7 input,

VCC=

5V

AN0_0 to AN0_7 input,

ANEX0, ANEX1 input

VREF= AN0 to AN7 input,

AN0_0 to AN0_7 input,

=3.3V ANEX0, ANEX1 input

±7

±2

LSB

VCC

8bit

VREF=VCC=5V, 3.3V

LSB

kΩ

−

Tolerance Level Impedance

Differential Non-Linearity Error

Offset Error

3

DNL

±2

±5

40

LSB

kΩ

−

Gain Error

RLADDER

tCONV

Ladder Resistance

VREF=VCC

10

10-bit Conversion Time, Sample & Hold

Function Available

VREF=VCC=5V, φAD=10MHz

3.3

μs

tCONV

8-bit Conversion Time, Sample & Hold

Function Available

VREF=VCC=5V, φAD=10MHz

2.8

μs

tSAMP

VREF

VIA

Sampling Time

0.3

3.0

0

μs

V

Reference Voltage

Analog Input Voltage

VCC

VREF

V

NOTES:

1. Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.

2. φAD frequency must be 10 MHz or less.

3. When sample & hold function is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 2.

4. When sample & hold function is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 2.

Rev.1.22 Mar 30, 2007 Page 25 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

Table 5.4

Flash Memory Version Electrical Characteristics ⁽¹⁾

Standard

Symbol

Parameter

Unit

Min.

Typ.

Max.

−

Program and Erase Endurance ⁽²⁾

Word Program Time (VCC1=5.0V)

Lock Bit Program Time

100⁽³⁾

cycle

μs

s

−

25

200

4

−

Block Erase Time

(VCC1=5.0V)

4-Kbyte block

8-Kbyte block

32-Kbyte block

64-Kbyte block

0.3

0.5

0.8

−

4

s

−

4

s

−

4

s

tPS

−

Flash Memory Circuit Stabilization Wait Time

Data Hold Time ⁽⁴⁾

15

μs

year

10

NOTES:

1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (U3, U5) unless otherwise specified.

2. Program and Erase Endurance refers to the number of times a block erase can be performed.

If the program and erase endurance is 100, each block can be erased 100 times.

For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as

one program and erase endurance. Data cannot be written to the same address more than once without erasing the block.

(Rewrite prohibited)

3. Maximum number of E/W cycles for which operation is guaranteed.

4. Topr = -40 to 85 °C (U3) / -20 to 85 °C (U5).

Table 5.5

Flash Memory Version Program / Erase Voltage and Read Operation Voltage

Characteristics

Flash Program, Erase Voltage

Flash Read Operation Voltage

VCC1 = 3.3 ± 0.3 V or 5.0 ± 0.5 (Topr = 0°C to 60°C ) VCC1=2.7 to 5.5 V (Topr = -40°C to 85°C (U3)

-20°C to 85°C (U5))

Rev.1.22 Mar 30, 2007 Page 26 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

Table 5.6

One Time Flash Version Electrical Characteristics ⁽¹⁾

Standard

Symbol

Parameter

Unit

Min.

10

Typ.

Max.

1

−

Program Endurance

cycle

μs

−

Word Program Time (VCC1=5.0V)

One Time Flash Memory Circuit Stabilization Wait Time

Data Hold Time ⁽⁴⁾

50

500

15

tPS

−

μs

year

NOTES:

1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (U3, U5) unless otherwise specified.

2. Topr = -40 to 85 °C (U3) / -20 to 85 °C (U5).

Table 5.7

One Time Flash Version Program Voltage and Read Operation Voltage Characteristics

Flash Program Voltage

VCC1 = 3.3 ± 0.3 V or 5.0 ± 0.5 (Topr = 0°C to 60°C )

Flash Read Operation Voltage

VCC1=2.7 to 5.5 V (Topr = -40°C to 85°C (U3)

-20°C to 85°C (U5))

Rev.1.22 Mar 30, 2007 Page 27 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

Table 5.8

Power Supply Circuit Timing Characteristics

Standard

Unit

Symbol

Parameter

Measuring Condition

Min.

Typ.

Max.

2

td(P-R)

Time for Internal Power Supply Stabilization

During Powering-On

VCC=2.7V to 5.5V

ms

td(R-S)

td(W-S)

STOP Release Time

1500

μs

Low Power Dissipation Mode Wait Mode

Release Time

Recommended

operation voltage

td(P-R)

Time for Internal Power

VCC

Supply Stabilization During

Powering-On

td(P-R)

CPU clock

Interrupt for

td(R-S)

(a) Stop mode release

or

STOP Release Time

(b)Wait mode release

td(W-S)

Low Power Dissipation

Mode Wait Mode Release

Time

CPU clock

(a)

(b)

td(R-S)

td(W-S)

Figure 5.1

Power Supply Circuit Timing Diagram

Rev.1.22 Mar 30, 2007 Page 28 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

(1)

Table 5.9

Electrical Characteristics(1)

Standard

Unit

Symbol

Parameter

Measuring Condition

Min.

Typ. Max.

HIGH

Output

Voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7

IOH=−5mA

VOH

VCC−2.0

VCC

V

HIGH

Output

Voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7

IOH=−200μA

VCC−0.3

VCC

HIGH Output Voltage XOUT

HIGHPOWER

LOWPOWER

IOH=−1mA

VCC−2.0

VCC

V

IOH=−0.5mA

HIGH Output Voltage XCOUT HIGHPOWER

LOWPOWER

With no load applied

IOL=5mA

2.5

1.6

LOW

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

VOL

Output

Voltage

2.0

V

LOW

Output

Voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

IOL=200μA

0.45

LOW Output Voltage XOUT

HIGHPOWER

LOWPOWER

IOL=1mA

2.0

V

IOL=0.5mA

2.0

LOW Output Voltage XCOUT HIGHPOWER

LOWPOWER

With no load applied

0

Hysteresis TA0IN to TA2IN, TB0IN to TB2IN,

INT0 to INT4, NMI, ADTRG, CTS0 to CTS2,

CLK0 to CLK2, TA0OUT to TA2OUT, KI0 to KI3,

RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2

VT+-VT-

0.2

1.0

2.5

V

Hysteresis

RESET

VT+-VT-

IIH

HIGH Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

VI=5V

VI=0V

Current

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

5.0

μA

XIN, RESET, CNVSS, BYTE

LOW Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

IIL

Current

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

−5.0

μA

kΩ

XIN, RESET, CNVSS, BYTE

Pull-Up

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

RPULLUP

Resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7

30

50

170

Feedback Resistance XIN

Feedback Resistance XCIN

RAM Retention Voltage

RfXIN

1.5

15

MΩ

V

RfXCIN

VRAM

At stop mode

2.0

NOTES:

1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr

= −20 to 85°C / −40 to 85°C, f(XIN) =16MHz unless otherwise specified.

Rev.1.22 Mar 30, 2007 Page 29 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

(1)

Table 5.10

Electrical Characteristics (2)

Standard

Unit

Symbol

Parameter

Measuring Condition

Min.

Typ. Max.

f(XIN)=16MHz

No division

ICC

Power Supply Current

In single-chip

(VCC1=VCC2=4.0V to 5.5V) mode, the output

pins are open and

Mask ROM

10

15

18

mA

f(XIN)=16MHz,

No division

One Time

Flash

other pins are VSS

f(XIN)=16MHz,

No division

Flash

Memory

12

15

25

18

mA

f(XIN)=10MHz,

VCC1=5.0V

One Time

Flash

f(XIN)=10MHz,

VCC1=5.0V

Flash Memory

Program

f(XIN)=10MHz,

VCC1=5.0V

Flash Memory

Erase

f(XCIN)=32kHz

Mask ROM

Low power dissipation

25

μA

(3)

mode, ROM

f(XCIN)=32kHz

One Time

Flash

Low power dissipation

(3)

mode, RAM

f(XCIN)=32kHz

Low power dissipation

mode, Flash Memory

350

25

(3)

f(XCIN)=32kHz

Flash Memory

Low power dissipation

(3)

mode, RAM

f(XCIN)=32kHz

Low power dissipation

mode, Flash Memory

420

7.5

(3)

f(XCIN)=32kHz

(2)

Mask ROM

One Time Flash

Flash Memory

Wait mode

,

Oscillation capability High

f(XCIN)=32kHz

(2)

Wait mode

,

2.0

0.8

μA

Oscillation capability Low

Stop mode

Topr =25°C

3.0

NOTES:

1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=16MHz unless otherwise

specified.

2. With one timer operated using fC32.

3. This indicates the memory in which the program to be executed exists.

Rev.1.22 Mar 30, 2007 Page 30 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

Timing Requirements

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

(1)

Table 5.11

External Clock Input (XIN input)

Standard

Symbol

Parameter

Unit

Min.

62.5

25

Max.

tc

External Clock Input Cycle Time

External Clock Input HIGH Pulse Width

External Clock Input LOW Pulse Width

External Clock Rise Time

ns

tw(H)

tw(L)

tr

25

15

tf

External Clock Fall Time

NOTES:

1. The condition is VCC1=VCC2=3.0 to 5.0V.

Table 5.12

Memory Expansion Mode and Microprocessor Mode

Standard

Symbol

Parameter

Unit

Min.

Max.

tac1(RD-DB)

tac2(RD-DB)

tsu(DB-RD)

Data Input Access Time (for setting with no wait)

Data Input Access Time (for setting with wait)

Data Input Setup Time

(NOTE 1)

(NOTE 2)

ns

40

30

40

0

tsu(RDY-BCLK)

RDY Input Setup Time

tsu(HOLD-BCLK) HOLD Input Setup Time

th(RD-DB)

Data Input Hold Time

RDY Input Hold Time

th(BCLK-RDY)

0

th(BCLK-HOLD) HOLD Input Hold Time

0

NOTES:

1. Calculated according to the BCLK frequency as follows:

9

0.5x10

----------------------- – 45[ns]

f(BCLK)

2. Calculated according to the BCLK frequency as follows:

9

(n – 0.5)x10

f(BCLK)

------------------------------------ – 45[ns]

n is ”2” for 1-wait setting.

Rev.1.22 Mar 30, 2007 Page 31 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

Timing Requirements

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

Table 5.13

Timer A Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

100

40

Max.

tc(TA)

TAiIN Input Cycle Time

ns

tw(TAH)

tw(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

40

Table 5.14

Timer A Input (Gating Input in Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

tc(TA)

TAiIN Input Cycle Time

ns

tw(TAH)

tw(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

Table 5.15

Timer A Input (External Trigger Input in One-shot Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

200

100

tc(TA)

TAiIN Input Cycle Time

ns

tw(TAH)

tw(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

Table 5.16

Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Standard

Symbol

Parameter

Unit

Min.

100

Max.

tw(TAH)

tw(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

ns

Table 5.17

Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

2000

1000

400

Max.

tc(UP)

TAiOUT Input Cycle Time

TAiOUT Input HIGH Pulse Width

TAiOUT Input LOW Pulse Width

TAiOUT Input Setup Time

TAiOUT Input Hold Time

ns

tw(UPH)

tw(UPL)

tsu(UP-TIN)

th(TIN-UP)

400

Table 5.18

Timer A Input (Two-phase Pulse Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

800

200

Max.

tc(TA)

TAiIN Input Cycle Time

ns

tsu(TAIN-TAOUT) TAiOUT Input Setup Time

tsu(TAOUT-TAIN) TAiIN Input Setup Time

Rev.1.22 Mar 30, 2007 Page 32 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

Timing Requirements

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

Table 5.19

Timer B Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

100

40

Max.

tc(TB)

TBiIN Input Cycle Time (counted on one edge)

ns

tw(TBH)

tw(TBL)

tc(TB)

TBiIN Input HIGH Pulse Width (counted on one edge)

TBiIN Input LOW Pulse Width (counted on one edge)

TBiIN Input Cycle Time (counted on both edges)

TBiIN Input HIGH Pulse Width (counted on both edges)

TBiIN Input LOW Pulse Width (counted on both edges)

40

200

80

tw(TBH)

tw(TBL)

80

Table 5.20

Timer B Input (Pulse Period Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

tc(TB)

TBiIN Input Cycle Time

ns

tw(TBH)

tw(TBL)

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

Table 5.21

Timer B Input (Pulse Width Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

tc(TB)

TBiIN Input Cycle Time

ns

tw(TBH)

tw(TBL)

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

Table 5.22

A/D Trigger Input

Standard

Symbol

Parameter

Unit

Min.

tc(AD)

1000

ns

ADTRG Input Cycle Time

tw(ADL)

125

ADTRG input LOW Pulse Width

Table 5.23

Serial Interface

Standard

Symbol

Parameter

Unit

Min.

200

100

Max.

80

tc(CK)

CLKi Input Cycle Time

CLKi Input HIGH Pulse Width

CLKi Input LOW Pulse Width

TXDi Output Delay Time

TXDi Hold Time

ns

tw(CKH)

tw(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

0

RXDi Input Setup Time

RXDi Input Hold Time

70

90

Table 5.24

External Interrupt INTi Input

Standard

Symbol

Parameter

Unit

Min.

250

Max.

tw(INH)

tw(INL)

ns

INTi Input HIGH Pulse Width

INTi Input LOW Pulse Width

250

Rev.1.22 Mar 30, 2007 Page 33 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

Switching Characteristics

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

Table 5.25

Memory Expansion and Microprocessor Modes (for setting with no wait)

Standard

Symbol

Parameter

Unit

Min.

Max.

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

Address Output Delay Time

25

ns

Address Output Hold Time (in relation to BCLK)

Address Output Hold Time (in relation to RD)

Address Output Hold Time (in relation to WR)

Chip Select Output Delay Time

−3

0

th(WR-AD)

(NOTE 2)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

25

15

25

40

Chip Select Output Hold Time (in relation to BCLK)

ALE Signal Output Delay Time

−3

−4

0

ALE Signal Output Hold Time

See

Figure 5.2

RD Signal Output Delay Time

RD Signal Output Hold Time

WR Signal Output Delay Time

WR Signal Output Hold Time

0

Data Output Delay Time (in relation to BCLK)

Data Output Hold Time (in relation to BCLK) ⁽³⁾

Data Output Delay Time (in relation to WR)

Data Output Hold Time (in relation to WR) ⁽³⁾

HLDA Output Delay Time

4

(NOTE 1)

(NOTE 2)

th(WR-DB)

td(BCLK-HLDA)

40

NOTES:

1. Calculated according to the BCLK frequency as follows:

9

0.5x10

----------------------- – 40[ns]

f(BCLK) is 12.5MHz or less.

f(BCLK)

2. Calculated according to the BCLK frequency as follows:

9

0.5x10

----------------------- – 10[ns]

f(BCLK)

3. This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

R

C

Hold time of data bus is expressed in

t = −CR X ln (1−VOL / VCC1)

by a circuit of the right figure.

For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold time

of output ”L” level is

DBi

t = −30pF X 1k Ω X In(1−0.2VCC1 / VCC1)

= 6.7ns.

P0

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

30pF

Figure 5.2

Ports P0 to P10 Measurement Circuit

Rev.1.22 Mar 30, 2007 Page 34 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

Switching Characteristics

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

Table 5.26

Memory Expansion and Microprocessor Modes (for 1 wait setting and external area

access)

Standard

Symbol

Parameter

Unit

Min.

Max.

25

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

Address Output Delay Time

ns

Address Output Hold Time (in relation to BCLK)

Address Output Hold Time (in relation to RD)

Address Output Hold Time (in relation to WR)

Chip Select Output Delay Time

−3

0

th(WR-AD)

(NOTE 2)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

25

15

25

40

Chip Select Output Hold Time (in relation to BCLK)

ALE Signal Output Delay Time

−3

−4

0

ALE Signal Output Hold Time

See

Figure 5.2

RD Signal Output Delay Time

RD Signal Output Hold Time

WR Signal Output Delay Time

WR Signal Output Hold Time

0

Data Output Delay Time (in relation to BCLK)

Data Output Hold Time (in relation to BCLK) ⁽³⁾

Data Output Delay Time (in relation to WR)

Data Output Hold Time (in relation to WR)⁽³⁾

HLDA Output Delay Time

4

(NOTE 1)

(NOTE 2)

th(WR-DB)

td(BCLK-HLDA)

40

NOTES:

1. Calculated according to the BCLK frequency as follows:

9

(n – 0.5)x10

f(BCLK)

------------------------------------ – 4 0 [n s ]

n is “1” for 1-wait setting, f(BCLK) is 12.5MHz or less.

2. Calculated according to the BCLK frequency as follows:

9

0.5x10

----------------------- – 10[ns]

f(BCLK)

3. This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

R

Hold time of data bus is expressed in

t = −CR X ln (1−VOL / VCC1)

by a circuit of the right figure.

DBi

For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold time

of output ”L” level is

C

t = −30pF X 1kΩ X In(1−0.2VCC1 / VCC1)

= 6.7ns.

Rev.1.22 Mar 30, 2007 Page 35 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

XIN input

tf

tw(H)

tw(L)

tr

tc

tc(TA)

tw(TAH)

TAiIN input

tw(TAL)

tc(UP)

tw(UPH)

TAiOUT input

tw(UPL)

TAiOUT input

(Up/down input)

During event counter mode

TAiIN input

th(TIN-UP) tsu(UP-TIN)

(When count on falling

edge is selected)

TAiIN input

(When count on rising

edge is selected)

Two-phase pulse input in

event counter mode

tc(TA)

TAiIN input

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

TAiOUT input

tsu(TAOUT-TAIN)

tc(TB)

tw(TBH)

TBiIN input

tw(TBL)

tc(AD)

tw(ADL)

ADTRG input

Figure 5.3

Timing Diagram (1)

Rev.1.22 Mar 30, 2007 Page 36 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

tc(CK)

tw(CKH)

CLKi

tw(CKL)

th(C-Q)

TXDi

RXDi

tsu(D-C)

td(C-Q)

th(C-D)

tw(INL)

INTi input

tw(INH)

Figure 5.4

Timing Diagram (2)

Rev.1.22 Mar 30, 2007 Page 37 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

Memory Expansion Mode, Microprocessor Mode

(Effective for setting with wait)

BCLK

RD

(Separate bus)

WR, WRL, WRH

(Separate bus)

RDY input

tsu(RDY−BCLK)

th(BCLK−RDY)

(Common to setting with wait and setting without wait)

BCLK

th(BCLK−HOLD)

tsu(HOLD−BCLK)

HOLD input

HLDA input

td(BCLK−HLDA)

P0, P1, P2,

P3, P4,

Hi−Z

P5_0 to P5_2

(1)

NOTES:

1. These pins are set to high-impedance regardless of the input level of the BYTE pin,

PM06 bit in PM0 register.

· Measuring conditions :

· VCC1=VCC2=5V

· Input timing voltage : Determined with VIL=1.0V, VIH=4.0V

· Output timing voltage : Determined with VOL=2.5V, VOH=2.5V

Figure 5.5

Timing Diagram (3)

Rev.1.22 Mar 30, 2007 Page 38 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

Memory Expansion Mode, Microprocessor Mode

(For setting with no wait)

Read timing

BCLK

td(BCLK-CS)

25ns.max

th(BCLK-CS)

−3ns.min

CSi

tcyc

td(BCLK-AD)

25ns.max

th(BCLK-AD)

−3ns.min

ADi

BHE

td(BCLK-ALE)

25ns.max

th(BCLK-ALE)

-4ns.min

th(RD-AD)

0ns.min

ALE

RD

td(BCLK-RD)

25ns.max

th(BCLK-RD)

0ns.min

tac1(RD-DB)

(0.5 × tcyc-45)ns.max

Hi-Z

DBi

tsu(DB-RD)

40ns.min

th(RD-DB)

0ns.min

Write timing

BCLK

td(BCLK-CS)

25ns.max

th(BCLK-CS)

−3ns.min

CSi

tcyc

td(BCLK-AD)

25ns.max

th(BCLK-AD)

−3ns.min

ADi

BHE

td(BCLK-ALE)

25ns.max

th(BCLK-ALE)

-4ns.min

th(WR-AD)

(0.5 × tcyc-10)ns.min

ALE

td(BCLK-WR)

th(BCLK-WR)

0ns.min

25ns.max

WR, WRL,

WRH

td(BCLK-DB)

40ns.max

th(BCLK-DB)

4ns.min

Hi-Z

DBi

td(DB-WR)

th(WR-DB)

(0.5 × tcyc-40)ns.min (0.5 × tcyc-10)ns.min

1

tcyc=

f(BCLK)

Measuring conditions

· VCC1=VCC2=5V

· Input timing voltage : VIL=0.8V, VIH=2.0V

· Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 5.6

Timing Diagram (4)

Rev.1.22 Mar 30, 2007 Page 39 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=5V

Memory Expansion Mode, Microprocessor Mode

(for 1-wait setting and external area access)

Read timing

BCLK

td(BCLK-CS)

25ns.max

th(BCLK-CS)

−3ns.min

CSi

tcyc

td(BCLK-AD)

25ns.max

th(BCLK-AD)

−3ns.min

ADi

BHE

th(RD-AD)

0ns.min

th(BCLK-ALE)

-4ns.min

td(BCLK-ALE)

25ns.max

ALE

RD

td(BCLK-RD)

25ns.max

th(BCLK-RD)

0ns.min

tac2(RD-DB)

(1.5 × tcyc-45)ns.max

Hi-Z

DBi

th(RD-DB)

0ns.min

tsu(DB-RD)

40ns.min

Write timing

BCLK

td(BCLK-CS)

25ns.max

th(BCLK-CS)

−3ns.min

CSi

tcyc

td(BCLK-AD)

25ns.max

th(BCLK-AD)

−3ns.min

ADi

BHE

td(BCLK-ALE)

25ns.max

th(BCLK-ALE)

-4ns.min

th(WR-AD)

(0.5 × tcyc-10)ns.min

ALE

td(BCLK-WR)

25ns.max

th(BCLK-WR)

0ns.min

WR, WRL,

WRH

td(BCLK-DB)

40ns.max

th(BCLK-DB)

4ns.min

Hi-Z

DBi

td(DB-WR)

(0.5 × tcyc-40)ns.min

th(WR-DB)

(0.5 × tcyc-10)ns.min

1

tcyc=

f(BCLK)

Measuring conditions

· VCC1=VCC2=5V

· Input timing voltage : VIL=0.8V, VIH=2.0V

· Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 5.7

Timing Diagram (5)

Rev.1.22 Mar 30, 2007 Page 40 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

(1)

Table 5.27

Electrical Characteristics (1)

Standard

Unit

Symbol

Parameter

Measuring Condition

IOH=−1mA

Min.

Typ. Max.

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

VOH

HIGH

Output

Voltage

VCC−0.5

VCC

V

HIGHPOWER

HIGH Output Voltage XOUT

IOH=−0.1mA

VCC−0.5

VCC

V

LOWPOWER

HIGHPOWER

LOWPOWER

IOH=−50μA

VCC

HIGH Output Voltage XCOUT

With no load applied

IOL=1mA

2.5

1.6

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

VOL

LOW

Output

Voltage

0.5

V

HIGHPOWER

LOWPOWER

HIGHPOWER

LOWPOWER

LOW Output Voltage XOUT

IOL=0.1mA

0.5

V

IOL=50μA

0.5

LOW Output Voltage XCOUT

With no load applied

0

TA0IN to TA2IN,

VT+-VT-

Hysteresis

TB0IN to TB2IN, INT0 to INT4, NMI,

0.2

0.8

V

ADTRG, CTS0 to CTS2, RXD0 to RXD2,

CLK0 to CLK2, TA0OUT to TA2OUT,

KI0 to KI3, SCL0 to SCL2, SDA0 to SDA2

VT+-VT-

IIH

(0.7)

1.8

4.0

V

RESET

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

HIGH Input

Current

VI=3V

VI=0V

μA

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

IIL

LOW Input

Current

−4.0

μA

kΩ

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

RPULLUP Pull-Up

Resistance

50

100

500

RfXIN

Feedback Resistance

3.0

25

MΩ

V

XIN

RfXCIN

VRAM

Feedback Resistance

RAM Retention Voltage

XCIN

At stop mode

2.0

NOTES:

1. Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz no wait unless

otherwise specified.

Rev.1.22 Mar 30, 2007 Page 41 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

(1)

Table 5.28

Electrical Characteristics (2)

Standard

Unit

Symbol

Parameter

Measuring Condition

Min.

Typ. Max.

ICC

Power Supply Current

In single-chip

(VCC1=VCC2=2.7V to 3.6V) mode, the output

pins are open and

Mask ROM

f(XIN)=10MHz

No division

8

11

13

mA

One Time

Flash

f(XIN)=10MHz,

No division

other pins are VSS

Flash

Memory

f(XIN)=10MHz,

No division

8

Flash Memory f(XIN)=10MHz,

Program

12

22

VCC1=3.0V

One Time

Flash Program VCC1=3.0V

f(XIN)=10MHz,

Flash Memory f(XIN)=10MHz,

Erase

VCC1=3.0V

Mask ROM

f(XCIN)=32kHz

Low power dissipation

mode, ROM ⁽³⁾

25

μA

One Time

Flash

f(XCIN)=32kHz

Low power dissipation

mode, RAM ⁽³⁾

f(XCIN)=32kHz

Low power dissipation

mode, Flash Memory ⁽³⁾

350

25

Flash Memory f(XCIN)=32kHz

Low power dissipation

mode, RAM ⁽³⁾

f(XCIN)=32kHz

Low power dissipation

mode, Flash Memory ⁽³⁾

420

6.0

Mask ROM

f(XCIN)=32kHz

One Time Flash Wait mode ⁽²⁾

,

Flash Memory Oscillation capability High

f(XCIN)=32kHz

Wait mode ⁽²⁾

Oscillation capability Low

,

1.8

0.7

μA

Stop mode

Topr =25°C

3.0

NOTES:

1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz unless otherwise

specified.

2. With one timer operated using fC32.

3. This indicates the memory in which the program to be executed exists.

Rev.1.22 Mar 30, 2007 Page 42 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

Timing Requirements

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

Table 5.29

External Clock Input (XIN input)

Standard

Symbol

Parameter

Unit

Min.

Max.

tc

External Clock Input Cycle Time

External Clock Input HIGH Pulse Width

External Clock Input LOW Pulse Width

External Clock Rise Time

(NOTE 2)

(NOTE 3)

ns

tw(H)

tw(L)

tr

(NOTE 4)

tf

External Clock Fall Time

NOTES:

1. The condition is VCC1=VCC2=2.7 to 3.0V.

2. Calculated according to the VCC1 voltage as follows:

10^–6

--------------------------------------- [ns]

20 × VCC1 – 44

3. Calculated according to the VCC1 voltage as follows:

10^–6

---------------------------------------

× 0.4 [ns]

20 × VCC1 – 44

4. Calculated according to the VCC1 voltage as follows:

–10 × VCC1 + 45 [ns]

Table 5.30

Memory Expansion Mode and Microprocessor Mode

Standard

Symbol

Parameter

Unit

Min.

Max.

tac1(RD-DB)

tac2(RD-DB)

tsu(DB-RD)

Data Input Access Time (for setting with no wait)

Data Input Access Time (for setting with wait)

Data Input Setup Time

(NOTE 1)

(NOTE 2)

ns

50

40

50

0

tsu(RDY-BCLK)

RDY Input Setup Time

tsu(HOLD-BCLK) HOLD Input Setup Time

th(RD-DB)

Data Input Hold Time

RDY Input Hold Time

th(BCLK-RDY)

0

th(BCLK-HOLD) HOLD Input Hold Time

0

NOTES:

1. Calculated according to the BCLK frequency as follows:

9

0.5x10

----------------------- – 60[ns]

f(BCLK)

2. Calculated according to the BCLK frequency as follows:

9

(n – 0.5)x10

f(BCLK)

------------------------------------ – 6 0 [n s ]

n is ”2” for 1-wait setting.

Rev.1.22 Mar 30, 2007 Page 43 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

Timing Requirements

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

Table 5.31

Timer A Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

150

60

Max.

tc(TA)

TAiIN Input Cycle Time

ns

tw(TAH)

tw(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

60

Table 5.32

Timer A Input (Gating Input in Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

tc(TA)

TAiIN Input Cycle Time

ns

tw(TAH)

tw(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

Table 5.33

Timer A Input (External Trigger Input in One-shot Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

300

150

tc(TA)

TAiIN Input Cycle Time

ns

tw(TAH)

tw(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

Table 5.34

Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Standard

Symbol

Parameter

Unit

Min.

150

Max.

tw(TAH)

tw(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

ns

Table 5.35

Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

3000

1500

600

Max.

tc(UP)

TAiOUT Input Cycle Time

TAiOUT Input HIGH Pulse Width

TAiOUT Input LOW Pulse Width

TAiOUT Input Setup Time

TAiOUT Input Hold Time

ns

tw(UPH)

tw(UPL)

tsu(UP-TIN)

th(TIN-UP)

600

Table 5.36

Timer A Input (Two-phase Pulse Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

2

Max.

tc(TA)

TAiIN Input Cycle Time

μs

ns

tsu(TAIN-TAOUT) TAiOUT Input Setup Time

tsu(TAOUT-TAIN) TAiIN Input Setup Time

500

Rev.1.22 Mar 30, 2007 Page 44 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

Timing Requirements

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

Table 5.37

Timer B Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

150

60

Max.

tc(TB)

TBiIN Input Cycle Time (counted on one edge)

ns

tw(TBH)

tw(TBL)

tc(TB)

TBiIN Input HIGH Pulse Width (counted on one edge)

TBiIN Input LOW Pulse Width (counted on one edge)

TBiIN Input Cycle Time (counted on both edges)

TBiIN Input HIGH Pulse Width (counted on both edges)

TBiIN Input LOW Pulse Width (counted on both edges)

60

300

120

tw(TBH)

tw(TBL)

Table 5.38

Timer B Input (Pulse Period Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

Max.

tc(TB)

TBiIN Input Cycle Time

ns

tw(TBH)

tw(TBL)

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

Table 5.39

Timer B Input (Pulse Width Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

tc(TB)

TBiIN Input Cycle Time

ns

tw(TBH)

tw(TBL)

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

Table 5.40

A/D Trigger Input

Standard

Symbol

Parameter

Unit

Min.

tc(AD)

1500

ns

ADTRG Input Cycle Time

tw(ADL)

200

ADTRG Input LOW Pulse Width

Table 5.41

Serial Interface

Standard

Symbol

Parameter

Unit

Min.

300

150

Max.

160

tc(CK)

CLKi Input Cycle Time

CLKi Input HIGH Pulse Width

CLKi Input LOW Pulse Width

TXDi Output Delay Time

TXDi Hold Time

ns

tw(CKH)

tw(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

0

RXDi Input Setup Time

RXDi Input Hold Time

100

90

Table 5.42

External Interrupt INTi Input

Standard

Symbol

Parameter

Unit

Min.

380

Max.

tw(INH)

tw(INL)

ns

INTi Input HIGH Pulse Width

INTi Input LOW Pulse Width

380

Rev.1.22 Mar 30, 2007 Page 45 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

Switching Characteristics

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

Table 5.43

Memory Expansion and Microprocessor Modes (for setting with no wait)

Standard

Symbol

Parameter

Unit

Min.

Max.

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

Address Output Delay Time

30

ns

Address Output Hold Time (in relation to BCLK)

Address Output Hold Time (in relation to RD)

Address Output Hold Time (in relation to WR)

Chip Select Output Delay Time

0

th(WR-AD)

(NOTE 2)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

30

25

30

40

Chip Select Output Hold Time (in relation to BCLK)

ALE Signal Output Delay Time

0

−4

0

ALE Signal Output Hold Time

See

Figure 5.8

RD Signal Output Delay Time

RD Signal Output Hold Time

WR Signal Output Delay Time

WR Signal Output Hold Time

0

Data Output Delay Time (in relation to BCLK)

Data Output Hold Time (in relation to BCLK) ⁽³⁾

Data Output Delay Time (in relation to WR)

Data Output Hold Time (in relation to WR) ⁽³⁾

HLDA Output Delay Time

4

(NOTE 1)

(NOTE 2)

th(WR-DB)

td(BCLK-HLDA)

40

NOTES:

1. Calculated according to the BCLK frequency as follows:

9

0.5x10

----------------------- – 40[ns]

f(BCLK) is 12.5MHz or less.

f(BCLK)

2. Calculated according to the BCLK frequency as follows:

9

0.5x10

----------------------- – 10[ns]

f(BCLK)

3. This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

R

C

Hold time of data bus is expressed in

t = −CR X ln (1−VOL / VCC1)

by a circuit of the right figure.

For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold time

of output ”L” level is

DBi

t = −30pF X 1k Ω X In(1−0.2VCC1 / VCC1)

= 6.7ns.

P0

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

30pF

Figure 5.8

Ports P0 to P10 Measurement Circuit

Rev.1.22 Mar 30, 2007 Page 46 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

Switching Characteristics

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

Table 5.44

Memory Expansion and Microprocessor Modes (for 1 wait setting and external area

access)

Standard

Symbol

Parameter

Unit

Min.

Max.

30

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

Address Output Delay Time

ns

Address Output Hold Time (in relation to BCLK)

Address Output Hold Time (in relation to RD)

Address Output Hold Time (in relation to WR)

Chip Select Output Delay Time

0

th(WR-AD)

(NOTE 2)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

30

25

30

40

Chip Select Output Hold Time (in relation to BCLK)

ALE Signal Output Delay Time

0

-4

0

ALE Signal Output Hold Time

See

Figure 5.8

RD Signal Output Delay Time

RD Signal Output Hold Time

WR Signal Output Delay Time

WR Signal Output Hold Time

0

Data Output Delay Time (in relation to BCLK)

Data Output Hold Time (in relation to BCLK) ⁽³⁾

Data Output Delay Time (in relation to WR)

Data Output Hold Time (in relation to WR)⁽³⁾

HLDA Output Delay Time

4

(NOTE 1)

(NOTE 2)

th(WR-DB)

td(BCLK-HLDA)

40

NOTES:

1. Calculated according to the BCLK frequency as follows:

9

(n – 0.5)x10

f(BCLK)

------------------------------------ – 4 0 [n s ]

n is “1” for 1-wait setting, f(BCLK) is 12.5MHz or less.

2. Calculated according to the BCLK frequency as follows:

9

0.5x10

----------------------- – 10[ns]

f(BCLK)

3. This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

R

C

Hold time of data bus is expressed in

t = −CR X ln (1−VOL / VCC1)

by a circuit of the right figure.

For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold time

of output ”L” level is

DBi

t = −30pF X 1kΩ X In(1−0.2VCC1 / VCC1)

= 6.7ns.

Rev.1.22 Mar 30, 2007 Page 47 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

XIN input

tf

tw(H)

tw(L)

tr

tc

tc(TA)

tw(TAH)

TAiIN input

tw(TAL)

tc(UP)

tw(UPH)

TAiOUT input

tw(UPL)

TAiOUT input

(Up/down input)

During Event Counter Mode

TAiIN input

(When count on falling

edge is selected)

th(TIN-UP) tsu(UP-TIN)

TAiIN input

(When count on rising

edge is selected)

Two-Phase Pulse Input in

Event Counter Mode

tc(TA)

TAiIN input

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

TAiOUT input

tsu(TAOUT-TAIN)

tc(TB)

tw(TBH)

TBiIN input

tw(TBL)

tc(AD)

tw(ADL)

ADTRG input

Figure 5.9

Timing Diagram (1)

Rev.1.22 Mar 30, 2007 Page 48 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

tc(CK)

tw(CKH)

CLKi

tw(CKL)

th(C-Q)

TXDi

RXDi

tsu(D-C)

td(C-Q)

th(C-D)

tw(INL)

INTi input

tw(INH)

Figure 5.10

Timing Diagram (2)

Rev.1.22 Mar 30, 2007 Page 49 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

Memory Expansion Mode, Microprocessor Mode

(Effective for setting with wait)

BCLK

RD

(Separate bus)

WR, WRL, WRH

(Separate bus)

RDY input

tsu(RDY−BCLK)

th(BCLK−RDY)

(Common to setting with wait and setting without wait)

BCLK

th(BCLK−HOLD)

tsu(HOLD−BCLK)

HOLD input

HLDA output

td(BCLK−HLDA)

P0, P1, P2,

P3, P4,

Hi−Z

P5_0 to P5_2 ⁽¹⁾

NOTES:

1. These pins are set to high-impedance regardless of the input level of the BYTE pin,

PM06 bit in PM0 register.

Measuring conditions :

· VCC1=VCC2=3V

· Input timing voltage : Determined with VIL=0.6V, VIH=2.4V

· Output timing voltage : Determined with VOL=1.5V, VOH=1.5V

Figure 5.11

Timing Diagram (3)

Rev.1.22 Mar 30, 2007 Page 50 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

Memory Expansion Mode, Microprocessor Mode

(for setting with no wait)

Read timing

BCLK

td(BCLK-CS)

th(BCLK-CS)

0ns.min

30ns.max

CSi

tcyc

td(BCLK-AD)

30ns.max

th(BCLK-AD)

0ns.min

ADi

BHE

td(BCLK-ALE)

30ns.max

th(BCLK-ALE)

-4ns.min

th(RD-AD)

0ns.min

ALE

RD

td(BCLK-RD)

30ns.max

th(BCLK-RD)

0ns.min

tac1(RD-DB)

(0.5 × tcyc-60)ns.max

Hi-Z

DBi

tsu(DB-RD)

50ns.min

th(RD-DB)

0ns.min

Write timing

BCLK

td(BCLK-CS)

30ns.max

th(BCLK-CS)

0ns.min

CSi

tcyc

td(BCLK-AD)

30ns.max

th(BCLK-AD)

0ns.min

ADi

BHE

td(BCLK-ALE)

30ns.max

th(BCLK-ALE)

-4ns.min

th(WR-AD)

(0.5 × tcyc-10)ns.min

ALE

td(BCLK-WR)

th(BCLK-WR)

0ns.min

30ns.max

WR, WRL,

WRH

td(BCLK-DB)

40ns.max

th(BCLK-DB)

4ns.min

Hi-Z

DBi

th(WR-DB)

(0.5 × tcyc-10)ns.min

td(DB-WR)

(0.5 × tcyc-40)ns.min

1

tcyc=

f(BCLK)

Measuring conditions

· VCC1=VCC2=3V

· Input timing voltage : VIL=0.6V, VIH=2.4V

· Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 5.12

Timing Diagram (4)

Rev.1.22 Mar 30, 2007 Page 51 of 53

REJ03B0088-0122

M16C/30P Group

5. Electrical Characteristics

VCC1=VCC2=3V

Memory Expansion Mode, Microprocessor Mode

(for 1-wait setting and external area access)

Read timing

BCLK

td(BCLK−CS)

th(BCLK−CS)

30ns.max

0ns.min

CSi

tcyc

td(BCLK−AD)

30ns.max

th(BCLK−AD)

0ns.min

ADi

BHE

th(RD−AD)

th(BCLK−ALE)

−4ns.min

td(BCLK−ALE)

0ns.min

30ns.max

ALE

RD

td(BCLK−RD)

30ns.max

th(BCLK−RD)

0ns.min

tac2(RD−DB)

(1.5 × tcyc−60)ns.max

Hi−Z

DBi

th(RD−DB)

0ns.min

tsu(DB−RD)

50ns.min

Write timing

BCLK

td(BCLK−CS)

30ns.max

th(BCLK−CS)

0ns.min

CSi

tcyc

td(BCLK−AD)

30ns.max

th(BCLK−AD)

0ns.min

ADi

BHE

td(BCLK−ALE)

30ns.max

th(BCLK−ALE)

−4ns.min

th(WR−AD)

(0.5 × tcyc−10)ns.min

ALE

td(BCLK−WR)

th(BCLK−WR)

30ns.max

0ns.min

WR,WRL,

WRH

td(BCLK−DB)

th(BCLK−DB)

40ns.max

4ns.min

Hi−Z

DBi

td(DB−WR)

(0.5 × tcyc−40)ns.min

th(WR−DB)

(0.5 × tcyc−10)ns.min

1

tcyc=

f(BCLK)

Measuring conditions

· VCC1=VCC2=3V

· Input timing voltage : VIL=0.6V, VIH=2.4V

· Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 5.13

Timing Diagram (5)

Rev.1.22 Mar 30, 2007 Page 52 of 53

REJ03B0088-0122

M16C/30P Group

Appendix 1. Package Dimensions

Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section

of the Renesas Technology website.

JEITA Package Code

P-QFP100-14x20-0.65

RENESAS Code

PRQP0100JB-A

Previous Code

100P6S-A

MASS[Typ.]

1.6g

H_D

D

*1

80

51

81

50

NOTE)

1.

DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

2.

Dimension in Millimeters

Reference

Symbol

Min

19.8

13.8

Nom

20.0

14.0

2.8

Max

20.2

14.2

D

E

100

31

A₂

H_D

H_E

A

22.5

16.5

22.8

16.8

23.1

17.1

3.05

0.2

1

30

Z_D

Index mark

F

A₁

b_p

c

0

0.1

0.3

0.25

0.13

0.4

0.15

0.2

L

0°

10°

*3

e

b_p

y

e

y

0.5

0.65

0.8

Detail F

0.10

Z_D

Z_E

L

0.575

0.825

0.6

0.4

0.8

JEITA Package Code

RENESAS Code

PLQP0100KB-A

Previous Code

100P6Q-A / FP-100U / FP-100UV

MASS[Typ.]

0.6g

P-LQFP100-14x14-0.50

H_D

D

*1

51

75

NOTE)

1.

DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

76

50

2.

b_p

b₁

Dimension in Millimeters

Reference

Symbol

Min

13.9

Nom

14.0

1.4

Max

14.1

D

E

Terminal cross section

A₂

H_D

H_E

A

15.8

16.0

16.2

1.7

100

26

A₁

b_p

b₁

c

0.05

0.15

0.1

0.20

0.15

0.25

1

25

Index mark

Z_D

F

0.18

0.09

0.145

0.125

0.20

c₁

0

°

8°

e

x

0.5

y

*3

0.08

L

b_p

e

x

y

L₁

Z_D

Z_E

L

1.0

0.5

1.0

Detail F

0.35

0.65

L₁

Rev.1.22 Mar 30, 2007 Page 53 of 53

REJ03B0088-0122

REVISION HISTORY

M16C/30P Group Datasheet

Description

Summary

Rev.

Date

Page

0.70

0.80

Aug 26, 2004

Mar 18, 2005

−

First Edition issued

development support tools -> development tools

BCLK -> CPU clock

Table 1.1 Performance Outline of M16C/30P Group

Serial interface is revised.

2

4

8

Figure 1.2 Type., Memory Size, and Package is partly revised.

Table 1.4 Pin Detection (2) is partly revised.

20

Note 2 Table 5.3 A/D Conversion Characteristics is partly revised.

Symbol of Table 5.4 Power Supply Circuit Timing Characteristics is partly

revised.

21

22

28

2

Table 5.5 Electrical Characteristics is revised.

Table 5.19 Electrical Characteristics is revised.

Table 1.1 Performance Outline of M16C/30P Group is partly revised.

Table 1.2 Product List is partly revised.

1.00

Sep 01, 2005

4

Figure 1.2 Type No., Memory Size, and Package is partly revised.

Figure 1.3 Pin Configuration is partly revised.

5

6

Figure 1.4 Pin Configuration is partly revised.

7-8 Tables 1.3 to 1.4 Pin Characteristics are added.

9

Table 1.5 Pin Description is revised.

14

15

19

21

22

25

3. Memory is partly revised.

Table 4.1 SFR Information is partly revised.

Table 4.5 SFR Information is partly revised

Table 5.2 Recommended Operating Conditions is partly revised.

Table 5.3 A/D Conversion Characteristics is partly revised.

Note 1 is added in Table 5.6 External Clock Input (XIN input)

Table 5.7 Memory Expansion Mode and Microprocessor Mode is added.

28

29

Table 5.20 Memory Expansion Mode and Microprocessor Modes (for

setting with no wait) is added.

Figure 5.2 Ports P0 to P10 Measurement Circuit is added.

Table 5.21 Memory Expansion Mode and Microprocessor Modes (for 1- to

3-wait setting and external area access) is added.

32

33

34

36

Figure 5.5 Timing Diagram (3) is added.

Figure 5.6 Timing Diagram (4) is added.

Figure 5.7 Timing Diagram (5) is added.

Note 1 to 4 are added in Table 5.23 External Clock Input (XIN input)

Table 5.24 Memory Expansion Mode and Microprocessor Mode is added.

39

Table 5.37 Memory Expansion Mode and Microprocessor Modes (for

setting with no wait) is added.

Figure 5.8 Ports P0 to P10 Measurement Circuit is added.

40

43

Table 5.38 Memory Expansion Mode and Microprocessor Modes (for 1- to

3-wait setting and external area access) is added.

Figure 5.11 Timing Diagram (3) is added.

C - 1

REVISION HISTORY

M16C/30P Group Datasheet

Description

Summary

Rev.

1.10

Date

Page

44

45

2

Figure 5.12 Timing Diagram (4) is added.

Figure 5.13 Timing Diagram (5) is added.

Oct 01, 2005

Table 1.1 Performance Outline of M16C/30P Group is partly revised.

Table 1.2 Product List is partly revised.

4

Figure 1.2 Type No., Memory Size, and Package is partly revised.

5

Table 1.3 Product Code of Mask ROM version Version for M16C/30P is

added.

Figure 1.3 Marking Diagram of Mask ROM Version for M16C/30P is

added.

6

Figure 1.4 Marking Diagram of ROM -less Version for M16C/30P is added.

Table 1.4 Product Code of ROM-less version for M16C/30P is added.

Figure 3.1 Memory Map is partly added.

16

23

4

Table 5.2 information is revised.

1.11

May 31, 2006

1.4 Product List information is revised.

Table 1.2 Product List is partly revised.

5

7

Figure 1.2 Type No., Memory Size, and Package is partly added.

Table 1.4 Product Code of Flash Memory version and ROM-less version

for M16C/30P is partly revised.

Figure 1.4 Marking Diagram of Flash Memory version and ROM-less

Version for M16C/30P (Top View) is partly added.

17

3. Memory information is revised.

Figure 3.1 Memory Map is partly revised.

18

19

23

26

Table 4.1 SFR Information(1) is partly revised.

Table 4.2 SFR Information(2) is partly added.

Table 5.1 Absolute Maximum Ratings information is revised.

Table 5.4 Flash Memory Version Electrical Characteristics is added.

Table 5.5 Flash Memory Version Program / Erase Voltage and Read

Operation Voltage Characteristics is added.

28

29

33

Table 5.7 Electrical Characteristics(1) is partly deleted.

Table 5.8 Electrical Characteristics (2) is partly revised.

Table 5.23 Memory Expansion and Microprocessor Modes

NOTES 3 is partly revised.

34

Table 5.24 Memory Expansion and Microprocessor Modes

NOTES 3 is partly revised.

40

41

45

Table 5.25 Electrical Characteristics (1) is partly deleted.

Table 5.26 Electrical Characteristics (2) is partly revised.

Table 5.41 Memory Expansion and Microprocessor Modes

NOTES 3 is partly revised.

46

Table 5.42 Memory Expansion and Microprocessor Modes

NOTES 3 is partly revised.

C - 2

REVISION HISTORY

M16C/30P Group Datasheet

Description

Summary

Rev.

1.20

Date

Page

Oct 17, 2006

1

2

4

5

7

Note is partly deleted.

Table 1.1 Performance Outline of M16C/30P Group is partly added.

Table 1.2 Product List is partly revised.

Figure 1.2 Type No., Memory Size, and Package is added.

Table 1.4 Product Code of One Time Flash version, Flash Memory ver-

sion, and ROM-less version for M16C/30P is partly added.

Figure 3.1 Memory Map is partly added.

17

19

23

27

Table 4.2 SFR Information (2) is partly added.

Table 5.1 Absolute Maximum Ratings is partly added.

Table 5.6 One Time Flash Version Electrical Characteristics and

Table 5.7 One Time Flash Version Program Voltage and Read Operation

Voltage Characteristics is added.

30

42

7

Table 5.10 Electrical Characteristics (2) is partly added.

Table 5.28 Electrical Characteristics (2) is partly added.

1.21

1.22

Nov 02 2006

Mar 30, 2007

Table 1.4 Product Code of One Time Flash version, Flash Memory

version, and ROM-less version for M16C/30P is partly revised.

4

5

Table 1.2 Product List (1) is partly revised.

Table 1.3 Product List (2) is partly revised.

Table 4.2 SFR Information (2) is partly revised.

19

C - 3

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Notes:

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes

warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property

rights or any other rights of Renesas or any third party with respect to the information in this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,

but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass

destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws

and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this

document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,

please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be

disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a

result of errors or omissions in the information included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability

of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular

application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications

or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality

and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or

undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall

have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems

(2) surgical implantations

(3) healthcare intervention (e.g., excision, administration of medication, etc.)

(4) any other purposes that pose a direct threat to human life

Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing

applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all

damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,

movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages

arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain

rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage

caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and

malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software

alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as

swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.

Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have

any other inquiries.

RENESAS SALES OFFICES

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A

Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

Renesas Technology Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.

Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

Renesas Technology (Shanghai) Co., Ltd.

Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120

Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898

Renesas Technology Hong Kong Ltd.

7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2730-6071

Renesas Technology Taiwan Co., Ltd.

10th Floor, No.99, Fushing North Road, Taipei, Taiwan

Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999

Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

Renesas Technology Korea Co., Ltd.

Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea

Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145

Renesas Technology Malaysia Sdn. Bhd

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: <603> 7955-9390, Fax: <603> 7955-9510

Colophon .7.0


型号：	M30302FAPGP
厂家：	RENESAS TECHNOLOGY CORP
描述：	SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 单芯片16位CMOS微机微控制器和处理器外围集成电路计算机时钟
文件：	总57页 (文件大小：653K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M30302FAPGP [RENESAS]

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