M30302MCP-XXX [RENESAS]
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER; 单芯片16位CMOS微机
| 型号： | M30302MCP-XXX |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 文件： | 总36页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
M16C/30P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0088-0080
Rev.0.80
Mar 18, 2005
1. Overview
The M16C/30P Group of single-chip microcomputers are built using the high-performance silicon gate CMOS process
using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this
microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it
suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/
logic operations.
1.1
Applications
Audio, cameras, TV, home appliance, office/communications/portable/industrial equipment, etc.
Specifications written in this manual are believed to be accurate,
but are not guaranteed to be entirely free of error. Specifications in
this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
Rev.0.80 Mar 18, 2005 Page 1 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
1.Overview
1.2
Performance Outline
Table 1.1 lists Performance Outline of M16C/30P Group.
Table 1.1
Performance Outline of M16C/30P Group
Item
Performance
CPU
Number of Basic Instructions 91 instructions
Minimum Instruction
Execution Time
62.5ns(f(XIN)=16MHz, VCC1=VCC2=4.2 to 5.5V, no wait)
100ns(f(XIN)=10MHz, VCC1=VCC2=2.7 to 5.5V, no wait)
Single-chip
Operation Mode
Memory Space
Memory Capacity
Port
1 Mbyte
See Table 1.2 Product List
Input/Output : 87 pins, Input : 1 pin
Timer A : 16 bits x 3 channels,
Timer B : 16 bits x 3 channels
3 channels
Peripheral
Function
Multifunction Timer
Serial Interface
Clock synchronous, UART,
2
(1)
I C bus
1 channels
(2)
IEBus
A/D Converter
DMAC
10-bit A/D converter: 1 circuit, 18 channels
2 channels
CRC Calculation Circuit
Watchdog Timer
Interrupt
CCITT-CRC
15 bits x 1 channel (with prescaler)
Internal: 20 sources, External: 7 sources, Software: 4
sources, Priority level: 7 levels
Clock Generating Circuit
2 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
(*)Equipped with a built-in feedback resistor.
Electric
Characteristics
Supply Voltage
VCC1=VCC2=3.0 to 5.5 V (f(XIN)=16MHz)
VCC1=VCC2=2.7 to 5.5 V (f(XIN)=10MHz, no wait)
10 mA (VCC1=VCC2=5V, f(XIN)=16MHz)
8 mA (VCC1=VCC2=3V, f(XIN)=10MHz)
1.8 µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7 µA(VCC1=VCC2=3V, stop mode)
-20 to 85°C, -40 to 85°C
Power Consumption
Operating Ambient Temperature
Package
100-pin plastic mold QFP, LQFP
NOTES:
2
1. I C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. Use the M16C/30P on VCC1 = VCC2.
Rev.0.80 Mar 18, 2005 Page 2 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
1.Overview
1.3
Block Diagram
Figure 1.1 is a M16C/30P Group Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
Timer (16-bit)
System clock
generation circuit
A/D converter
(10 bits X 18 channels)
XIN-XOUT
XCIN-XCOUT
Output (timer A): 3
Input (timer B): 3
UART or
clock synchronous serial I/O
(3 channels)
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
M16C/60 series16-bit CPU core
Memory
ROM (1)
SB
R0H
R1H
R0L
R1L
Watchdog timer
(15 bits)
USP
ISP
R2
R3
RAM (2)
INTB
PC
FLG
DMAC
(2 channels)
A0
A1
FB
Multiplier
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
Figure 1.1
M16C/30P Group Block Diagram
Rev.0.80 Mar 18, 2005 Page 3 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
1.Overview
1.4
Product List
Table 1.2 lists the M16C/30P group products and Figure 1.2 shows the Type No., Memory Size, and Package.
Table 1.2
Product List
Type No.
As of Mar 2005
ROM Capacity RAM Capacity Package Type
Remarks
M30302MAP-XXXFP
M30302MAP-XXXGP
M30302MCP-XXXFP
(D) 96 Kbytes
(D)
5 Kbytes
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
MASK ROM version
(D) 128 Kbytes
M30302MCP-XXXGP (D)
M30302MEP-XXXFP
M30302MEP-XXXGP
(D) 192 Kbytes
(D)
6 Kbytes
(D): Under development
(P): Under planning
Type No. M 3 0 3 0 2 M E P - X X X F P
Package type:
FP : Package 100P6S-A
GP : Package 100P6Q-A
ROM No.
M16C/30P Group
ROM capacity:
A : 96 Kbytes
C : 128 Kbytes
E : 192 Kbytes
Memory type:
M : Mask ROM version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/30 Series
M16C Family
Figure 1.2
Type No., Memory Size, and Package
Rev.0.80 Mar 18, 2005 Page 4 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
1.Overview
1.5
Pin Configuration
Figures 1.3 to 1.4 show the pin configurations (top view).
PIN CONFIGURATION (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P4_4
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0_7/AN0_7
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1
P0_0/AN0_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P5_4
P5_5
P5_6
M16C/30P Group
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P10_0/AN0
VREF
AVCC
P9_7/ADTRG
P6_7/TXD1/SDA1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/30P on VCC1=VCC2.
Package : 100P6S-A
Figure 1.3
Pin Configuration (Top View)
Rev.0.80 Mar 18, 2005 Page 5 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
1.Overview
PIN CONFIGURATION (top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P1_2
P1_1
P1_0
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P0_7/AN0_7
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1
P0_0/AN0_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P5_6
M16C/30P Group
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P10_0/AN0
VREF
AVCC
P6_7/TXD1/SDA1
P9_7/ADTRG
P9_6/ANEX1
P9_5/ANEX0
P7_0/TXD2/SDA2/TA0OUT(1)
P7_1/RXD2/SCL2/TA0IN(1)
P7_2/CLK2/TA1OUT
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/30P on VCC1=VCC2.
Package : 100P6Q-A
Figure 1.4
Pin Configuration (Top View)
Rev.0.80 Mar 18, 2005 Page 6 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
1.Overview
1.6
Pin Description
Table 1.3
Pin Description (1)
Signal Name
Pin Name
I/O Type
I
Description
Power supply input VCC1, VCC2
VSS
Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC1 = VCC2.
Analog power
supply input
AVCC
AVSS
I
I
Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
Reset input
The microcomputer is in a reset state when applying “L” to the this
pin.
RESET
CNVSS
CNVSS
BYTE
I
I
Connect this pin to VSS.
External data bus
width select input
Main clock input
Main clock output
XIN
I
I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT. To use the
external clock, input the clock from XIN and leave XOUT open.
XOUT
O
Sub clock input
Sub clock output
XCIN
I
I/O pins for a sub clock oscillation circuit. Connect a crystal
oscillator between XCIN and XCOUT. To use the external clock,
input the clock from XCIN and leave XCOUT open.
XCOUT
O
Clock output
CLKOUT
INT0 to INT4
NMI
O
I
The clock of the same cycle as fC, f8, or f32 is outputted.
Input pins for the INT interrupt.
INT interrupt input
NMI interrupt input
I
I
Input pin for the NMI interrupt.
Key input interrupt
input
Input pins for the key input interrupt.
KI0 to KI3
Timer A
TA0OUT to
TA2OUT
I/O
These are timer A0 to timer A2 I/O pins. (except the output of
TA0OUT for the N-channel open drain output.)
TA0IN to TA2IN
TB0IN to TB2IN
I
I
I
These are timer A0 to timer A2 input pins.
These are timer B0 to timer B2 input pins.
These are send control input pins.
Timer B
Serial interface
CTS0 to CTS2
O
These are receive control output pins.
RTS0 to RTS2
CLK0 to CLK2
RXD0 to RXD2
TXD0 to TXD2
I/O
I
These are transfer clock I/O pins.
These are serial data input pins.
O
These are serial data output pins. (except TXD2 for the N-channel
open drain output.)
CLKS1
O
This is output pin for transfer clock output from multiple pins
function.
I2C mode
SDA0 to SDA2
SCL0 to SCL2
I/O
I/O
These are serial data I/O pins. (except SDA2 for the N-channel
open drain output.)
These are transfer clock I/O pins. (except SCL2 for the N-channel
open drain output.)
I : Input O : Output I/O : Input and output
Rev.0.80 Mar 18, 2005 Page 7 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
1.Overview
Table 1.4
Pin Description (2)
Signal Name
Pin Name
VREF
I/O Type
I
Description
Reference
Applies the reference voltage for the A/D converter.
voltage input
A/D converter AN0 to AN7,
AN0_0 to AN0_7
I
Analog input pins for the A/D converter.
This is an A/D trigger input pin.
I
ADTRG
ANEX0
I/O
This is the extended analog input pin for the A/D converter, and is the
output in external op-amp connection mode.
ANEX1
I
This is the extended analog input pin for the A/D converter.
I/O port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
P6_0 to P6_7,
P7_0 to P7_7,
P9_0 to P9_7,
P10_0 to P10_7
I/O
8-bit I/O ports in CMOS, having a direction register to select an input
or output.
Each pin is set as an input port or output port. An input port can be set
for a pull-up or for no pull-up in 4-bit unit by program. (except P7_0 and
P7_1 for the N-channel open drain output.)
P8_0 to P8_4,
P8_6, P8_7
I/O
I
I/O ports having equivalent functions to P0.
Input port
P8_5
Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit
in the P8 register.
I : Input O : Output I/O : Input and output
Rev.0.80 Mar 18, 2005 Page 8 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
b31
b15
b8b7
b0
R2
R3
R0H
R1H
R0L
R1L
Data Registers (1)
R2
R3
A0
A1
FB
Address Registers (1)
Frame Base Registers (1)
b19
b15
b0
Interrupt Table Register
Program Counter
INTBH
INTBL
b19
b0
b0
PC
b15
USP
ISP
SB
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
b15
b0
b0
FLG
O B
Flag Register
b15
b8 b7
IPL
U
I
S
Z
D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTES:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
Central Processing Unit Register
2.1
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
Rev.0.80 Mar 18, 2005 Page 9 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
2. Central Processing Unit (CPU)
2.2
Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative
addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7
Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8
Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1
Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3
Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4
Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6
Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7
Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.
Rev.0.80 Mar 18, 2005 Page 10 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
2. Central Processing Unit (CPU)
2.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0
to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write “0”. When read, its content is indeterminate.
Rev.0.80 Mar 18, 2005 Page 11 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
3.Memory
3. Memory
Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1M bytes from address 00000h to
FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte
internal ROM is allocated to the addresses from F0000h to FFFFFh.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start
address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte
internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also
stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses
from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no
functions allocated is reserved for future use and cannot be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS
or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
00000h
SFR
00400h
Internal RAM
FFE00h
XXXXXh
Special page
vector table
FFFDCh
Undefined instruction
Reserved area
Internal ROM
Overflow
BRK instruction
Address match
Single step
Internal RAM
Internal ROM
Watchdog timer
Address XXXXXh
Address YYYYYh
Size
Size
YYYYYh
FFFFFh
DBC
NMI
Reset
5 kbytes
96 kbytes
128 kbytes
192 kbytes
017FFh
E8000h
E0000h
D0000h
6 kbytes
01BFFh
FFFFFh
Figure 3.1
Memory Map
Rev.0.80 Mar 18, 2005 Page 12 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
4. Special Function Register (SFR)
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.5 list the SFR
information.
(1)
Table 4.1
SFR Information(1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Register
Symbol
After Reset
(2)
Processor Mode Register 0
Processor Mode Register 1
PM0
PM1
CM0
CM1
00h
00XXX0XXb
01001000b
00100000b
System Clock Control Register 0
System Clock Control Register 1
Address Match Interrupt Enable Register
Protect Register
AIER
PRCR
XXXXXX00b
XX000000b
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
WDTS
WDC
XXh
00XXXXXXb
00h
RMAD0
00h
X0h
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
DMA0 Source Pointer
DMA0 Destination Pointer
DMA0 Transfer Counter
DMA0 Control Register
DMA1 Source Pointer
DMA1 Destination Pointer
DMA1 Transfer Counter
DMA1 Control Register
SAR0
XXh
XXh
XXh
DAR0
XXh
XXh
XXh
TCR0
XXh
XXh
DM0CON
SAR1
00000X00b
XXh
XXh
XXh
DAR1
XXh
XXh
XXh
TCR1
XXh
XXh
DM1CON
00000X00b
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. The PM00 and PM01 bits do not change at software reset.
X : Nothing is mapped to this bit
Rev.0.80 Mar 18, 2005 Page 13 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
4. Special Function Register (SFR)
(1)
Table 4.2
SFR Information(2)
Address
0040h
Register
Symbol
After Reset
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
to
INT3 Interrupt Control Register
INT3IC
XX00X000b
UART1 BUS Collision Detection Interrupt Control Register
UART0 BUS Collision Detection Interrupt Control Register
U1BCNIC
U0BCNIC
XXXXX000b
XXXXX000b
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
DMA1 Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
Timer B0 Interrupt Control Register
Timer B1 Interrupt Control Register
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
INT2 Interrupt Control Register
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XX00X000b
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
to
Peripheral Clock Select Register
PCLKR
00000011b
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.0.80 Mar 18, 2005 Page 14 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
4. Special Function Register (SFR)
(1)
Table 4.3
SFR Information(3)
Address
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
Register
Symbol
After Reset
035Eh
035Fh
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
Interrupt Factor Select Register 2
Interrupt Factor Select Register
IFSR2A
IFSR
00XXXXXXb
00h
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
U2BRG
U2TB
UART2 Transmit Buffer Register
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
XXh
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.0.80 Mar 18, 2005 Page 15 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
4. Special Function Register (SFR)
(1)
Table 4.4
SFR Information(4)
Address
Register
Symbol
TABSR
After Reset
000XX000b
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
Count Start Flag
Clock Prescaler Reset Fag
One-Shot Start Flag
Trigger Select Register
Up-Down Flag
CPSRF
ONSF
TRGSR
UDF
0XXXXXXXb
00XXX000b
XXXX0000b
(2)
XX0XX000b
Timer A0 Register
Timer A1 Register
Timer A2 Register
TA0
TA1
TA2
XXh
XXh
XXh
XXh
XXh
XXh
Timer B0 Register
Timer B1 Register
Timer B2 Register
TB0
TB1
TB2
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
TA0MR
TA1MR
TA2MR
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
TB0MR
TB1MR
TB2MR
00XX0000b
00XX0000b
00XX0000b
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Generator
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
X0000000b
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Generator
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
UART Transmit/Receive Control Register 2
UCON
DMA0 Request Factor Select Register
DMA1 Request Factor Select Register
CRC Data Register
DM0SL
DM1SL
CRCD
00h
00h
XXh
XXh
XXh
CRC Input Register
CRCIN
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate.
X : Nothing is mapped to this bit
Rev.0.80 Mar 18, 2005 Page 16 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
4. Special Function Register (SFR)
(1)
Table 4.5
SFR Information(5)
Address
Register
Symbol
After Reset
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
A/D Register 0
A/D Register 1
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
A/D Control Register 2
ADCON2
XXX000X0b
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
000X0XXXb
00000XXXb
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
P0
P1
PD0
PD1
P2
XXh
XXh
00h
00h
XXh
XXh
00h
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
00h
XXh
XXh
00h
Port P5 Register
P5
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
PD4
PD5
P6
00h
XXh
XXh
00h
Port P7 Register
P7
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
PD6
PD7
P8
00h
XXh
XXh
00X00000b
00h
Port P9 Register
P9
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
PD8
PD9
P10
XXh
Port P10 Direction Register
PD10
00h
Pull-Up Control Register 0
Pull-Up Control Register 1
Pull-Up Control Register 2
Port Control Register
PUR0
PUR1
PUR2
PCR
00h
00h
00h
00h
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.0.80 Mar 18, 2005 Page 17 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
VCC
Parameter
Supply Voltage(VCC1=VCC2)
Analog Supply Voltage
Condition
Rated Value
−0.3 to 6.5
Unit
V
VCC1=VCC2=AVCC
VCC1=VCC2=AVCC
AVCC
VI
−0.3 to 6.5
V
Input Voltage
−0.3 to VCC+0.3
V
RESET, CNVSS, BYTE,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
VREF, XIN
P7_0, P7_1
−0.3 to 6.5
V
V
VO
Output
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
XOUT
−0.3 to VCC+0.3
Voltage
P7_0, P7_1
−0.3 to 6.5
300
V
Pd
Power Dissipation
−40°C<Topr≤85°C
mW
°C
Topr
Operating
Ambient
When the Microcomputer is Operating
−20 to 85 / −40 to 85
Temperature
Tstg
Storage Temperature
−65 to 150
°C
Rev.0.80 Mar 18, 2005 Page 18 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
(1)
Table 5.2
Recommended Operating Conditions
Standard
Unit
Symbol
Parameter
Min.
2.7
Typ.
5.0
VCC
0
Max.
5.5
VCC
AVCC
VSS
Supply Voltage (VCC1=VCC2)
Analog Supply Voltage
Supply Voltage
V
V
V
V
V
AVSS
VIH
Analog Supply Voltage
0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
HIGH Input
Voltage
0.8VCC
VCC
XIN, RESET, CNVSS, BYTE
P7_0, P7_1
0.8VCC
0
6.5
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
VIL
LOW Input
Voltage
0.2VCC
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
f(XIN)
HIGH Peak
Output Current
−10.0
−5.0
10.0
5.0
mA
mA
mA
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
HIGH Average
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
LOW Peak
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
LOW Average
Output Current
VCC=4.2V to 5.5V
VCC=2.7V to 4.2V
Main Clock Input
Oscillation
Frequency (4)
0
0
16
MHz
MHz
4×VCC
−0.8
f(XCIN)
f(BCLK)
Sub-Clock Oscillation Frequency
CPU Operation Clock
32.768
50
16
kHz
0
MHz
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. The Average Output Current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9 and P10 must be 80mA max. The total IOL(peak) for ports P3, P4, P5,
P6, P7 and P8_0 to P8_4 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must be −20mA max. The total
IOH(peak) for ports P3, P4 and P5 must be −40mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be −40mA
max.
The total IOH(peak) for ports P8_6, P8_7 and P9 must be −40mA max. Set Average Output Current to 1/2 of peak.
4. Relationship between main clock oscillation frequency, and supply voltage.
Main clock input oscillation frequency
16.0
4×VCC–0.8MHZ
10.0
0.0
2.7
4.2
5.5
Supply voltage [V]
(main clock: no division)
Rev.0.80 Mar 18, 2005 Page 19 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
(1)
Table 5.3
A/D Conversion Characteristics
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ.
Max.
10
−
Resolution
VREF=VCC
Bits
INL
Integral Non-Linearity
Error
10bit
VREF= AN0 to AN7 input,
±5
LSB
VCC=
5V
AN0_0 to AN0_7 input,
ANEX0, ANEX1 input
VREF= AN0 to AN7 input,
±7
LSB
VCC=
3.3V
AN0_0 to AN0_7 input,
ANEX0, ANEX1 input
8bit
VREF=VCC=3.3V
±2
±5
LSB
LSB
−
Absolute Accuracy
10bit
VREF= AN0 to AN7 input,
VCC=
5V
AN0_0 to AN0_7 input,
ANEX0, ANEX1 input
VREF= AN0 to AN7 input,
AN0_0 to AN0_7 input,
=3.3V ANEX0, ANEX1 input
±7
±2
LSB
VCC
8bit
VREF=VCC=3.3V
LSB
kΩ
−
Tolerance Level Impedance
Differential Non-Linearity Error
Offset Error
3
DNL
±2
±5
±5
40
LSB
LSB
LSB
kΩ
−
−
Gain Error
RLADDER
tCONV
Ladder Resistance
VREF=VCC
10
10-bit Conversion Time, Sample & Hold
Function Available
VREF=VCC=5V, φAD=10MHz
3.3
µs
tCONV
8-bit Conversion Time, Sample & Hold
Function Available
VREF=VCC=5V, φAD=10MHz
2.8
µs
tSAMP
VREF
VIA
Sampling Time
0.3
3.0
0
µs
V
Reference Voltage
Analog Input Voltage
VCC
VREF
V
NOTES:
1. Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. φAD frequency must be 10 MHz or less.
3. When sample & hold function is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 2.
When sample & hold function is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 2.
Rev.0.80 Mar 18, 2005 Page 20 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
Table 5.4
Power Supply Circuit Timing Characteristics
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ.
Max.
2
td(P-R)
Time for Internal Power Supply Stabilization
During Powering-On
VCC=2.7V to 5.5V
ms
td(R-S)
td(W-S)
STOP Release Time
1500
1500
µs
µs
Low Power Dissipation Mode Wait Mode
Release Time
Recommended
operation voltage
td(P-R)
Time for Internal Power
VCC
Supply Stabilization During
Powering-On
td(P-R)
CPU clock
Interrupt for
td(R-S)
(a) Stop mode release
or
STOP Release Time
(b)Wait mode release
td(W-S)
Low Power Dissipation
Mode Wait Mode Release
Time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
Figure 5.1
Power Supply Circuit Timing Diagram
Rev.0.80 Mar 18, 2005 Page 21 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
(1)
Table 5.5
Electrical Characteristics
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ. Max.
HIGH
Output
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH=−5mA
VOH
VOH
VOH
VCC−2.0
VCC
V
V
HIGH
Output
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7
IOH=−200µA
VCC−0.3
VCC
HIGH Output Voltage XOUT
HIGHPOWER
LOWPOWER
IOH=−1mA
VCC−2.0
VCC−2.0
VCC
VCC
V
V
IOH=−0.5mA
HIGH Output Voltage XCOUT HIGHPOWER
LOWPOWER
With no load applied
With no load applied
IOL=5mA
2.5
1.6
LOW
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
VOL
VOL
VOL
Output
Voltage
2.0
V
V
LOW
Output
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
IOL=200µA
0.45
LOW Output Voltage XOUT
HIGHPOWER
LOWPOWER
IOL=1mA
2.0
V
V
IOL=0.5mA
2.0
LOW Output Voltage XCOUT HIGHPOWER
LOWPOWER
With no load applied
With no load applied
0
0
Hysteresis TA0IN to TA2IN, TB0IN to TB2IN,
INT0 to INT4, NMI, ADTRG, CTS0 to CTS2,
CLK0 to CLK2, TA0OUT to TA2OUT, KI0 to KI3,
RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2
VT+-VT-
VT+-VT-
0.2
1.0
V
Hysteresis
RESET
0.2
0.2
2.5
0.8
V
V
Hysteresis XIN
VT+-VT-
IIH
HIGH Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
VI=5V
VI=0V
VI=0V
Current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
5.0
µA
XIN, RESET, CNVSS, BYTE
LOW Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
IIL
Current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
−5.0
µA
kΩ
XIN, RESET, CNVSS, BYTE
Pull-Up
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
RPULLUP
Resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,
P8_7, P9_0 to P9_7, P10_0 to P10_7
30
50
170
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
RfXIN
RfXCIN
VRAM
ICC
1.5
15
MΩ
MΩ
V
At stop mode
2.0
Power Supply Current
(VCC1=VCC2=4.2V to 5.5V)
Mask f(XIN)=16MHz
ROM No division
In single-chip mode, the
output pins are open and
other pins are VSS
10
25
mA
f(XCIN)=32kHz
Low power dissipation mode,
ROM (3)
µA
f(XCIN)=32kHz
Wait mode (2)
Oscillation capacity High
,
7.5
µA
f(XCIN)=32kHz
Wait mode (2)
Oscillation capacity Low
,
2.0
0.8
µA
µA
Stop mode
Topr =25°C
3.0
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=16MHz unless otherwise
specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
Rev.0.80 Mar 18, 2005 Page 22 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.6
External Clock Input (XIN input)
Standard
Symbol
Parameter
Unit
Min.
62.5
25
Max.
tc
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
25
15
15
tf
External Clock Fall Time
Rev.0.80 Mar 18, 2005 Page 23 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.7
Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
Max.
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
40
Table 5.8
Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.9
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.10
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
ns
ns
Table 5.11
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
tc(UP)
TAiOUT Input Cycle Time
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
ns
ns
ns
ns
ns
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
400
Table 5.12
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tsu(TAIN-TAOUT) TAiOUT Input Setup Time
tsu(TAOUT-TAIN) TAiIN Input Setup Time
Rev.0.80 Mar 18, 2005 Page 24 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.13
Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 5.14
Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
Max.
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.15
Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.16
A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
tc(AD)
1000
ns
ns
ADTRG Input Cycle Time
tw(ADL)
125
ADTRG input LOW Pulse Width
Table 5.17
Serial Interface
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
80
tc(CK)
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
0
RXDi Input Setup Time
RXDi Input Hold Time
70
90
Table 5.18
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
Max.
tw(INH)
tw(INL)
ns
ns
INTi Input HIGH Pulse Width
INTi Input LOW Pulse Width
250
Rev.0.80 Mar 18, 2005 Page 25 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
XIN input
tf
tw(H)
tw(L)
tr
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
th(TIN-UP) tsu(UP-TIN)
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 5.2
Timing Diagram (1)
Rev.0.80 Mar 18, 2005 Page 26 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
RXDi
tsu(D-C)
td(C-Q)
th(C-D)
tw(INL)
INTi input
tw(INH)
Figure 5.3
Timing Diagram (2)
Rev.0.80 Mar 18, 2005 Page 27 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
(1)
Table 5.19
Electrical Characteristics
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ. Max.
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
VOH
VOH
HIGH
Output
Voltage
IOH=−1mA
VCC−0.5
VCC
V
HIGHPOWER
HIGH Output Voltage XOUT
IOH=−0.1mA
VCC−0.5
VCC−0.5
VCC
V
V
LOWPOWER
HIGHPOWER
LOWPOWER
IOH=−50µA
VCC
HIGH Output Voltage XCOUT
With no load applied
With no load applied
IOL=1mA
2.5
1.6
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
VOL
VOL
LOW
Output
Voltage
0.5
V
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
LOW Output Voltage XOUT
IOL=0.1mA
0.5
V
V
IOL=50µA
0.5
LOW Output Voltage XCOUT
With no load applied
With no load applied
0
0
TA0IN to TA2IN,
VT+-VT-
Hysteresis
TB0IN to TB2IN, INT0 to INT4, NMI,
0.2
0.8
V
ADTRG, CTS0 to CTS2, RXD0 to RXD2,
CLK0 to CLK2, TA0OUT to TA2OUT,
KI0 to KI3, SCL0 to SCL2, SDA0 to SDA2
VT+-VT-
Hysteresis
Hysteresis
0.2
0.2
(0.7)
1.8
0.8
V
V
RESET
XIN
VT+-VT-
IIH
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
HIGH Input
Current
VI=3V
VI=0V
VI=0V
4.0
µA
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
IIL
LOW Input
Current
−4.0
µA
kΩ
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
RPULLUP Pull-Up
Resistance
50
100
500
RfXIN
Feedback Resistance
3.0
25
MΩ
MΩ
V
XIN
RfXCIN
Feedback Resistance
RAM Retention Voltage
XCIN
VRAM
ICC
At stop mode
2.0
Power Supply Current
(VCC1=VCC2=2.7V to 3.6V)
In single-chip
mode, the output ROM No division
Mask f(XIN)=10MHz, no wait
8
mA
pins are open and
other pins are VSS
f(XCIN)=32kHz,
Low power dissipation mode,
ROM (3)
25
µA
f(XCIN)=32kHz,
Wait mode (2)
,
7.0
µA
Oscillation capacity High
f(XCIN)=32kHz,
Wait mode (2)
,
1.8
0.7
µA
µA
Oscillation capacity Low
Stop mode,
Topr =25°C
3.0
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz no wait unless
otherwise specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
Rev.0.80 Mar 18, 2005 Page 28 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.20
External Clock Input (XIN input)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
tc
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
40
18
18
tf
External Clock Fall Time
Rev.0.80 Mar 18, 2005 Page 29 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.21
Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
Max.
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
60
Table 5.22
Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.23
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
300
150
150
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.24
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
ns
ns
Table 5.25
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
tc(UP)
TAiOUT Input Cycle Time
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
ns
ns
ns
ns
ns
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
600
Table 5.26
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2
Max.
tc(TA)
TAiIN Input Cycle Time
µs
ns
ns
tsu(TAIN-TAOUT) TAiOUT Input Setup Time
tsu(TAOUT-TAIN) TAiIN Input Setup Time
500
500
Rev.0.80 Mar 18, 2005 Page 30 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.27
Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
60
300
120
120
tw(TBH)
tw(TBL)
Table 5.28
Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
Max.
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.29
Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.30
A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
tc(AD)
1500
ns
ns
ADTRG Input Cycle Time
tw(ADL)
200
ADTRG Input LOW Pulse Width
Table 5.31
Serial Interface
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
160
tc(CK)
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
0
RXDi Input Setup Time
RXDi Input Hold Time
100
90
Table 5.32
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
Max.
tw(INH)
tw(INL)
ns
ns
INTi Input HIGH Pulse Width
INTi Input LOW Pulse Width
380
Rev.0.80 Mar 18, 2005 Page 31 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
XIN input
tf
tw(H)
tw(L)
tr
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During Event Counter Mode
TAiIN input
(When count on falling
edge is selected)
th(TIN-UP) tsu(UP-TIN)
TAiIN input
(When count on rising
edge is selected)
Two-Phase Pulse Input in
Event Counter Mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 5.4
Timing Diagram (1)
Rev.0.80 Mar 18, 2005 Page 32 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
5. Electrical Characteristics
VCC1=VCC2=3V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
RXDi
tsu(D-C)
td(C-Q)
th(C-D)
tw(INL)
INTi input
tw(INH)
Figure 5.5
Timing Diagram (2)
Rev.0.80 Mar 18, 2005 Page 33 of 34
REJ03B0088-0080
Preliminary specification
Specifications in this manual are tentative and subject to change.
Under development
M16C/30P Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Recommended
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
QFP100-P-1420-0.65
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
MD
HD
D
100
81
1
80
I2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.25
0.13
13.8
19.8
–
16.5
22.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.4
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.13
0.1
10°
–
A
A1
A2
b
c
D
0.1
2.8
0.3
0.15
14.0
20.0
0.65
16.8
22.8
0.6
1.4
–
30
51
E
e
31
50
HD
HE
L
L1
x
A
L1
y
–
–
F
b2
I2
MD
ME
0.35
–
14.6
20.6
e
b
L
x
M
–
–
–
Detail F
y
–
Recommended
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
EIAJ Package Code
JEDEC Code
–
Weight(g)
0.63
Lead Material
Cu Alloy
MD
LQFP100-P-1414-0.50
HD
D
100
76
l2
Recommended Mount Pad
1
75
Dimension in Millimeters
Symbol
Min
–
0
Nom
–
0.1
Max
1.7
0.2
–
0.28
0.175
14.1
14.1
–
A
A1
A2
b
c
D
–
1.4
0.13
0.105
13.9
13.9
–
0.18
0.125
14.0
14.0
0.5
E
e
25
51
HD
HE
L
L1
Lp
A3
x
15.8
15.8
0.3
–
0.45
–
–
–
0°
–
16.0
16.0
0.5
1.0
0.6
0.25
–
–
16.2
16.2
0.7
–
0.75
–
0.08
0.1
10°
–
26
50
A
L1
F
e
y
–
b
x
y
L
M
b2
I2
MD
ME
0.225
–
14.4
14.4
0.9
–
–
–
–
–
Lp
Detail F
Rev.0.80 Mar 18, 2005 Page 34 of 34
REJ03B0088-0080
REVISION HISTORY
M16C/30P Group Datasheet
Description
Summary
Rev.
Date
Page
0.70
0.80
Aug 26, 2004
Mar 18, 2005
−
−
−
First Edition issued
development support tools -> development tools
BCLK -> CPU clock
Table 1.1 Performance Outline of M16C/30P Group
Serial interface is revised.
2
4
8
Figure 1.2 Type., Memory Size, and Package is partly revised.
Table 1.4 Pin Detection (2) is partly revised.
20
Note 2 Table 5.3 A/D Conversion Characteristics is partly revised.
Symbol of Table 5.4 Power Supply Circuit Timing Characteristics is partly
revised.
21
22
28
Table 5.5 Electrical Characteristics is revised.
Table 5.19 Electrical Characteristics is revised.
C - 1
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