M30623S8 [RENESAS]
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER; 单芯片16位CMOS微机
| 型号： | M30623S8 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 文件： | 总231页 (文件大小：3278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Description
The M16C/62 (80-pin version) group of single-chip microcomputers are built using the high-performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin plastic molded
QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of
instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high
speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communi-
cations, industrial equipment, and other high-speed processing applications.
The M16C/62 (80-pin version) group includes a wide range of products with different internal memory types
and sizes and various package types.
Features
• Memory capacity..................................ROM (See Figure 1.1.4. ROM Expansion)
RAM 3K to 20K bytes
• Shortest instruction execution time ......62.5ns (f(XIN)=16MHZ, VCC=5V)
100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait) : Mask ROM, flash memory 5V version
142.9ns (f(XIN)=7MH
• Supply voltage .....................................4.2 to 5.5V (f(XIN)=16MHZ, without software wait) : Mask ROM, flash memory 5V version
4.5 to 5.5V (f(XIN)=16MH , without software wait) : One-time PROM version
Z, VCC=3V, with software one-wait) : One-time PROM version
Z
2.7 to 5.5V (f(XIN)=10MHZ with software one-wait) : Mask ROM, flash memory 5V version
2.7 to 5.5V (f(XIN)=7MHZ with software one-wait) : One-time PROM version
• Low power consumption ......................25.5mW ( f(XIN)=10MHZ, with software one-wait, VCC = 3V)
• Interrupts..............................................25 internal and 5 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer......................5 output timers + 6 input timers (3 for timer function only)
• Serial I/O..............................................5 channels (2 for UART or clock synchronous, 1 for UART, 2 for clock synchronous)
• DMAC ..................................................2 channels (trigger: 24 sources)
• A-D converter.......................................10 bits X 8 channels (Expandable up to 10 channels)
• D-A converter.......................................8 bits X 2 channels
• CRC calculation circuit.........................1 circuit
• Watchdog timer....................................1 line
• Programmable I/O ...............................70 lines
_______
• Input port..............................................1 line (P85 shared with NMI pin)
• Clock generating circuit .......................2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Note: Memory expansion mode and microprocessor mode are not supported.
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
About the M16C/62 (80-pin version) group ..... 7
Central Processing Unit (CPU) ..................... 11
Reset............................................................. 14
Processor Mode ............................................ 21
Clock Generating Circuit ............................... 26
Protection ...................................................... 35
Interrupts ....................................................... 36
Watchdog Timer............................................ 56
DMAC ........................................................... 58
Timer ............................................................. 68
Serial I/O ....................................................... 86
A-D Converter ............................................. 126
D-A Converter ............................................. 136
CRC Calculation Circuit .............................. 138
Programmable I/O Ports ............................. 140
Electric Characteristics ............................... 154
Flash memory version................................. 192
1
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Pin Configuration
Figures 1.1.1 show the pin configurations (top view).
PIN CONFIGURATION (top view)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
61
62
P43
P0
P0
P0
P0
P0
6
5
4
3
2
P5
0
1
63
64
65
66
67
68
P5
37
36
35
34
33
P5
P5
P5
P5
P5
P5
2
3
4
5
6
7
P0
P0
1
0
P10
P10
P10
7
6
5
/AN
/AN
/AN
7
6
5
/KI3
/KI2
/KI1
69
70
71
32
31
30
29
/CLKOUT
M16C/62 Group (80-pin version)
P6
0
/CTS
0/RTS
0
1
P104/AN4/KI0
P6
P6
1
/CLK
0
0
P10
P10
P10
3
2
1
/AN
/AN
/AN
3
2
1
72
73
74
75
76
77
78
79
80
2
/RxD
28
27
26
25
24
P6
P6
3
/TX
D
0
4
/CTS
1/RTS
/CTS0/CLKS1
AVSS
P6
P6
5
/CLK
1
1
P10
0
/AN
0
6
/RxD
VREF
P6
7
/TX
D
1
AVcc
23
22
21
P7
P7
0
1
/TxD
/RxD
2
/SDA/TA0OUT
/SCL/TA0IN/TB5IN
P9
7
/ADTRG/SIN
4
2
P9 /ANEX1/SOUT
6
4
P76/TA3OUT
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
Package: 80P6S-A
Figure 1.1.1. Pin configuration (top view)
2
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Block Diagram
Figure 1.1.2 is a block diagram of the M16C/62 (80-pin version) group.
Block diagram of the M16C/62 (80-pin version) group
8
8
8
4
8
8
I/O ports
Port P0
Port P2
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
Timer
System clock generator
A-D converter
(10 bits
X
8 channels
XIN-XOUT
Expandable up to 10 channels)
X
CIN-XCOUT
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
Clock synchronous SI/O
UART/clock synchronous SI/O
(8 bits X 3 channels)(Note 3)
(8 bits
X
2 channels)
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
M16C/60 series16-bit CPU core
Memory
Registers
ROM
(Note 1)
Program counter
R0H
R0H
R1H
R2
R3
A0
A1
FB
R0L
R0L
R1L
PC
Watchdog timer
(15 bits)
RAM
(Note 2)
Vector table
INTB
DMAC
(2 channels)
Stack pointer
ISP
USP
D-A converter
(8 bits X 2 channels)
Multiplier
Flag register
FLG
SB
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Note 3: One of three channels is used for UART and IIC mode only.
Figure 1.1.2. Block diagram of M16C/62 (80-pin version) group
3
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Performance Outline
Table 1.1.1 is a performance outline of M16C/62 (80-pin version) group.
Table 1.1.1. Performance outline of M16C/62 (80-pin version) group
Item
Number of basic instructions
Shortest instruction execution time
Performance
91 instructions
62.5ns(f(XIN)=16MHZ, VCC=5V)
100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait)
: Mask ROM, flash memory 5V version
142.9ns (f(XIN)=7MHZ, VCC=3V, with software one-wait)
: One-time PROM version
Memory
capacity
I/O port
ROM
(See the figure 1.1.3. ROM Expansion)
3K to 20K bytes
RAM
P0 to P10 (except P85)
P85
8 bits x 10, 7 bits x 1
Input port
1 bit x 1
Multifunction TA0, TA3, TA4
timer
16 bits x 3 (timer mode, internal/external event count,
one-shot timer mode and pulse width measurement mode)
16 bits x 5 (timer mode, internal/external event count
and pulse period/pulse width measurement mode)
16 bits x 2 (timer mode, internal event count and
TB0, TB2, TB3, TB4, TB5
TA1, TA2
a trigger through one-shot timer mode occurs.
)
TB1
16 bits x 1 (timer mode and internal event count
)
Serial I/O
UART0, UART1, UART2
SI/O3, SI/O4
(UART or clock synchronous) x 2, UART x 1(UART2)
(Clock synchronous) x 2 (SI/O3 is output only)
10 bits x (8 + 2) channels
A-D converter
D-A converter
DMAC
8 bits x 2
2 channels (trigger: 24 sources)
CRC-CCITT
CRC calculation circuit
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
25 internal and 5 external sources, 4 software sources, 7 levels
2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
4.2 to 5.5V (f(XIN)=16MHZ, without software wait)
: Mask ROM, flash memory 5V version
4.5 to 5.5V (f(XIN)=16MHZ, without software wait)
: One-time PROM version
Clock generating circuit
Supply voltage
2.7 to 5.5V (f(XIN)=10MHZ with software one-wait)
: Mask ROM, flash memory 5V version
2.7 to 5.5V (f(XIN)=7MHZ with software one-wait)
: One-time PROM version
Power consumption
25.5mW (f(XIN) = 10MHZ, VCC=3V with software one-wait)
5V
I/O
I/O withstand voltage
characteristics Output current
Device configuration
Package
5mA
CMOS high performance silicon gate
100-pin plastic mold QFP
Note : M16C/62 (80-pin version) group does not support memory expansion or microprocessor mode.
4
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Mitsubishi plans to release the following products in the M16C/62 (80-pin version) group:
(1) Support for mask ROM version, one-time PROM version and flash memory version
(2) ROM capacity
(3) Package
80P6S-A
: Plastic molded QFP (mask ROM, one-time PROM, and flash memory versions)
ROM Size
(Byte)
External
ROM
M30625FGGP
M30625FGLGP
256K
128K
96K
M30625MG-XXXGP
M30623MC-XXXGP
M30621MC-XXXGP
M30621ECGP
M30621MA-XXXGP
M30623MA-XXXGP
80K
64K
32K
M30623M8-XXXGP
M30621M8-XXXGP
M30623M4-XXXGP
Mask ROM version
One-time PROM version
Flash memory version
External ROM version
Figure 1.1.3. ROM expansion
The M16C/62 (80-pin version) group products currently supported are listed in Table 1.1.2.
Table 1.1.2. M16C/62 (80-pin version) group
As of December 1999
Type No
ROM capacity
32 Kbytes
Remarks
RAM capacity
3 Kbytes
Package type
80P6S-A
M30623M4-XXXGP
M30623M8-XXXGP
M30623MA-XXXGP
M30623MC-XXXGP
M30621M8-XXXGP
M30621MA-XXXGP
64 Kbytes
96 Kbytes
128 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
256 Kbytes
4 Kbytes
5 Kbytes
5 Kbytes
10 Kbytes
10 Kbytes
80P6S-A
80P6S-A
80P6S-A
80P6S-A
80P6S-A
mask ROM version
M30621MC-XXXGP
M30625MG-XXXGP
M30621ECGP
10 Kbytes
20 Kbytes
10 Kbytes
80P6S-A
80P6S-A
80P6S-A
128 Kbytes
256 Kbytes
256 Kbytes
One-time PROM version
M30625FGGP
M30625FGLGP
20 Kbytes
20 Kbytes
80P6S-A
80P6S-A
Flash memory 5V version
Flash memory 3V version
5
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Type No.
M 3 0 6 2 3 M 8 – X X X F P
Package type:
GP : Package 80P6S-A
ROM No.
Omitted for blank one-time PROM version,
EPROM version and flash memory version
ROM capacity:
4 : 32K bytes
8 : 64K bytes
A : 96K bytes
C : 128K bytes
G: 256K bytes
Memory type:
M : Mask ROM version
E : EPROM or one-time PROM version
S : External ROM version
F : Flash memory version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/62 Group
M16C Family
Figure 1.1.4. Type No., memory size, and package
6
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
About the M16C/62 (80-pin version) group
The M16C/62 (80-pin version) group is packaged in a 80-pin plastic mold package. The number of pins in
comparison with the 100-pin package products is decreased. So be careful about the following.
(a) The M16C/62 (80-pin version) group supports single chip mode alone. It supports neither memory
expansion mode nor microprocessor mode.
(b) The input/output ports given below are absent from the M16C/62 (80-pin version) group. To stabi-
lize the internal state, set to output mode the direction register of each input/output port. Failing in
setting to output mode involves an increase in current consumption.
<Pins absent from the 80-pin version>
P10 to P17, P44 to P47, P72 to P75, P91
(c) INT3 to INT5 allocated to P15 to P17 cannot be used. Keep the INT3 interrupt control register
disabled for interrupts. The INT4 interrupt control register and the INT5 interrupt control register
are shared with SI/O3 and SI/O4. When the user don’t use them as SI/O3 and SI/4, set them
disabled for interrupts.
(d) The output pins of timers A1 and A2 - TA1IN, TA1OUT, TA2IN and TA2OUT - allocated to P72 to P75
cannot be used. In connection with this, the gate function and pulse outputting function of timers A1
and A2 cannot be used. Use timer mode and internal event count, or use as trigger signal genera-
tion in one-shot timer mode.
______ ______
(e) The UART2 input/output pins - CLK2 and CTS/RTS - allocated to P72 and P73 cannot be used. In
connection with this, UART2 solely as UART of the internal clock can be used.
(f) The input pin TB1IN of timer B1 allocated to P91 cannot be used. With timer B1 under this state, use
only timer mode or the internal event count.
(g) The input pin SIN3 of serial I/O3 allocated to P91 cannot be used. In connection with this, use serial
I/O3 as a serial I/O exclusive to transmission.
(h) The output pins for three-phase motor control allocated to P72 to P75 cannot be used. So set to 0
(ordinary mode) the mode select bit (bit 2) of three-phase PWM control register 0.
7
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name
VCC, VSS
Signal name
I/O
Function
Power supply
input
Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
This pin switches between processor modes. Connect it to the
VSS pin.
CNVSS
RESET
CNVSS
I
I
Reset input
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the XIN pin and leave the
XOUT pin open.
XIN
Clock input
I
XOUT
Clock output
O
(BYTE)
External data
bus width
select input
I
This pin is connected to CNVss in microcomputer. Connect this pin to
VSS.
AVCC
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VCC.
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VSS.
VREF
I
Reference
voltage input
This pin is a reference voltage input for the A-D converter.
P00 to P07
I/O port P0
I/O
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When set for input, the user can specify in units of four
bits via software whether or not they are tied to a pull-up resistor.
P20 to P27
I/O port P2
I/O
This is an 8-bit I/O port equivalent to P0.
P30 to P37
P40 to P43
I/O port P3
I/O port P4
I/O
I/O
This is an 8-bit I/O port equivalent to P0.
This is an 4-bit I/O port equivalent to P0.
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by software.
P50 to P57
I/O port P5
I/O
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as UART0 and UART1 I/O pins as selected by software.
P60 to P67
I/O port P6
I/O port P7
I/O
I/O
This is an 4-bit I/O port equivalent to P0 (P70 and P71 are N channel
open-drain output). Pins in this port also function as timer A0–A3,
timer B5 or UART2 I/O pins as selected by software.
P70, P71,
P76, P77
P80 to P84,
P80 to P84, P86, and P87 are I/O ports with the same functions as P0.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts.
P86 and P87 can be set using software to function as the I/O pins for a
sub clock generation circuit. In this case, connect a quartz oscillator
between P86 (XCOUT pin) and P87 (XCIN pin).
P85 is an input-only port that also functions for NMI. The NMI interrupt
is generated when the input at this pin changes from “H” to “L”. The
NMI function cannot be cancelled using software. The pull-up cannot be
set for this pin.
I/O port P8
I/O port P85
I/O
I/O
P86,
P85
P87,
I
8
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name
Signal name
I/O port P9
I/O
I/O
Function
P9
P9
0
,
This is an 7-bit I/O port equivalent to P0. Pins in this port also function
as SI/O3, 4 I/O pins, Timer B0–B4 input pins, D-A converter output
pins, A-D converter extended input pins, or A-D trigger input pins as
selected by software.
2
to P9
7
P100
to P10
7
I/O port P10
I/O
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as A-D converter input pins. Furthermore, P10
input pins for the key input interrupt function.
4–P107 also function as
Note: Memory expansion mode and microprocessor mode are not be supported.
9
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M16C/62(80-pin version) group accommodates certain units in a single chip. These units include ROM
and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic
operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calcu-
lation circuit, A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.4.1 is a memory map of the M16C/62 group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30623MC-XXXFP, there
is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as the
_______
reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored
here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal
register (INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30623MC-XXXFP, 5K bytes of internal RAM is mapped to
the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.7.1 to 1.7.3 are location
of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be
used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area
For details, see Figures
1.7.1 to 1.7.3
FFE0016
0040016
Internal RAM area
Special page
vector table
XXXXX16
Address
XXXXX16
Address
YYYYY16
Type No.
FFFDC16
Reserved
area
Undefined instruction
Overflow
M30623M4
M30623M8
00FFF16
013FF16
017FF16
017FF16
02BFF16
02BFF16
02BFF16
053FF16
F800016
F000016
E800016
E000016
F000016
E000016
E800016
C000016
BRK instruction
Address match
Single step
M30623MA
M30623MC
M30621M8
Watchdog timer
YYYYY16
FFFFF16
M30621MC/EC
M30621MA
M30625MG/FG
DBC
NMI
Reset
Internal ROM area
FFFFF16
Note: Set PM13 to “1” in M30625MG/FG. Otherwise set PM13 to “0”.
Figure 1.4.1. Memory map
10
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
b15
b15
b15
b15
b15
b15
b15
b8 b7
b8 b7
b0
b0
b0
b0
b0
b0
b0
R0(Note)
R1(Note)
R2(Note)
R3(Note)
A0(Note)
A1(Note)
FB(Note)
L
L
H
H
b19
b19
b0
PC
Program counter
Data
registers
b0
b0
Interrupt table
register
INTB
H
L
b15
b15
b15
b15
User stack pointer
USP
ISP
SB
b0
b0
b0
Interrupt stack
pointer
Address
registers
Static base
register
FLG
Frame base
registers
Flag register
IPL
U
I O B S Z D C
Note: These registers consist of two register banks.
Figure 1.5.1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
11
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”
.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
12
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b15
b0
IPL
Flag register (FLG)
U
I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.5.2. Flag register (FLG)
13
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence.
5V
4.0V
V
CC
0V
5V
V
CC
RESET
RESET
0V
0.8V
Example when VCC = 5V
.
Figure 1.6.1. Example reset circuit
X
IN
More than 20 cycles are needed
Single chip
mode
RESET
BCLK 24cycles
BCLK
FFFFC16
Content of reset vector
Address
FFFFE16
Figure 1.6.2. Reset sequence
14
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
____________
Table 1.6.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.6.3 and 1.6.4
show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.6.1. Pin status when RESET pin level is “L”
Status
Pin name
CNVSS = VSS
P0, P2, P3, P4
P7 , P7 , P7 , P7
P8 , P8 , P9 , P9
0
to P4
3
, P5, P6,
to P8
, P10
Input port (floating)
0
1
6
7
, P8
0
4,
6
7
0
2
to P9
7
15
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(29)UART1 transmit interrupt control register
(30)UART1 receive interrupt control register
(1) Processor mode register 0 (Note1) (000416)···
0016
0 0
(005316)···
(005416)···
(005516)···
(005616)···
(005716)···
(005816)···
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(2) Processor mode register 1
(000516)··· 0
(000616)··· 0
(000716)··· 0
0
1
0
0
0
1
0
0
0
(31)
(32)
(33)
(34)
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
(3) System clock control register 0
(4) System clock control register 1
(5)
0
0
1 0
0 0
0
0
(6)
(000916)···
(000A16)···
0
0
0
0
Address match interrupt enable
register
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
Timer B3,4,5 count start flag
(005916)···
(005A16)···
(005B16)···
(005C16)···
(005D16)···
(005E16)···
(005F16)···
(034016)···
(034816)···
(034916)···
(034A16)···
(034B16)···
(035B16)···
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(7) Protect register
0
(8) Data bank register
0016
(000B16)···
(9)
Watchdog timer control register
(000F16)··· 0
0
0
?
? ?
?
0
?
0
(10)
Address match interrupt register 0 (001016)···
0016
0016
0
0
0
0
0
0
(001116)···
(001216)···
Address match interrupt register 1 (001416)···
(001516)···
0 0
(11)
0016
0016
0
0
0
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Timer B3 mode register
0016
(001616)···
0 0
0
0
0
0
0
0
0
0
0
0
0
0016
0016
(12)
(13)
(14)
(15)
(16)
(17)
DMA0 control register
(002C16)··· 0
(003C16)··· 0
(004416)···
(004516)···
(004616)···
(004716)···
(004816)···
(004916)···
(004A16)···
(004B16)···
(004C16)···
0
0
0
0
0
0
0
0
0 ?
0 ?
DMA1 control register
0016
INT3 interrupt control register
Timer B5 interrupt control register
Timer B4 interrupt control register
Timer B3 interrupt control register
?
?
?
0 0
0
0
0
0
0
0
?
?
?
0 0
0 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
Timer B4 mode register
Timer B5 mode register
Interrupt cause select register
SI/O3 control register
(035C16)···
(035D16)···
(035F16)···
(036216)···
(036616)···
(48)
(49)
(50)
(51)
(52)
? 0
(18)SI/O4 interrupt control register
0 0
?
0
0016
(19)
4016
4016
SI/O3 interrupt control register
0
0
? 0
? 0
? 0
? 0
? 0
? 0
0
0
0
0
0
0
0
0
0
0
0
0
Bus collision detection interrupt
(20)
SI/O4 control register
control register
(21)
UART2 special mode register 2 (Note2)
UART2 special mode register
(037616)···
(037716)···
(53)
(54)
DMA0 interrupt control register
0016
0016
0016
(22)
(23)
(24)
DMA1 interrupt control register
Key input interrupt control register (004D16)···
(55)
(56)
(037816)···
UART2 transmit/receive mode register
A-D conversion interrupt control
register
(004E16)···
(004F16)···
(005016)···
UART2 transmit/receive control register 0 (037C16)··· 0
(037D16)···
0
0
0
0
0
0
1 0
0 0
0
1
0
0
(25)
(26)
(27)
(28)
UART2 transmit interrupt control
register
? 0
? 0
0
0
0
0
0
0
0
0
(57)
UART2 transmit/receive control register 1
0
UART2 receive interrupt control
register
UART0 transmit interrupt control
register
?
?
0
0
(005116)···
(005216)···
UART0 receive interrupt control
register
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note1: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
Note2: This register is not exist in M30623EC.
Figure 1.6.3. Device's internal status after a reset is cleared
16
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(58)
Count start flag
(038016)···
(038116)···
0016
(84)A-D control register 1
(85)
(03D716)···
(03DC16)···
(03E216)···
(03E316)···
(03E616)···
(03E716)···
(03EA16)···
(03EB16)···
(03EE16)···
(03EF16)···
(03F216)··· 0
(03F316)···
(03F616)···
(03FC16)···
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
(59)
0
Clock prescaler reset flag
D-A control register
(60)One-shot start flag
(038216)··· 0
(038316)···
(038416)···
(039616)···
(039716)···
(039816)···
(039916)···
(039A16)···
(039B16)··· 0
0
0
0
0
0
0
(86) Port P0 direction register
(87) Port P1 direction register
(88) Port P2 direction register
(89) Port P3 direction register
(90) Port P4 direction register
(61)Trigger select flag
0016
0016
0016
0016
0016
0016
0016
0
(62)Up-down flag
(63)Timer A0 mode register
(64)Timer A1 mode register
(65)Timer A2 mode register
(66)Timer A3 mode register
(67)Timer A4 mode register
(68)Timer B0 mode register
(91)
(92)
(93)
Port P5 direction register
Port P6 direction register
Port P7 direction register
0
0
0
?
?
?
0
0
0
0
0
0
0
0
0
(94) Port P8 direction register
(95)
0
0 0 0 0 0
Timer B1 mode register
(69)
(039C16)···
0
0
0
Port P9 direction register
0016
0016
0016
0016
0016
0016
(70)Timer B2 mode register
(039D16)··· 0
(03A016)···
(96) Port P10 direction register
(97) Pull-up control register 0
(71)UART0 transmit/receive mode register
0016
(72)UART0 transmit/receive control register 0 (03A416)··· 0
(73)UART0 transmit/receive control register 1 (03A516)··· 0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
(98) Pull-up control register 1(Note1) (03FD16)···
(99)
Pull-up control register 2
Port control register
(03FE16)···
(03FF16)···
(74)UART1 transmit/receive mode register
(03A816)···
0016
(100)
(75)UART1 transmit/receive control register 0 (03AC16)··· 0
(76)UART1 transmit/receive control register 1 (03AD16)··· 0
0
0
0
?
0
0
0
?
0
0
0
0
?
0
1
0
0
0
0
0
0
0
?
0
0
1
0
0
0
0
(101) Data registers (R0/R1/R2/R3)
(102) Address registers (A0/A1)
(103) Frame base register (FB)
(104) Interrupt table register (INTB)
(105) User stack pointer (USP)
(106) Interrupt stack pointer (ISP)
000016
000016
000016
0000016
000016
000016
000016
000016
(77)UART transmit/receive control register 2
(78)Flash memory control register 1 (Note2)
(79)Flash memory control register 0 (Note2)
(03B016)···
(03B616)···
(03B716)···
(03B816)···
(03BA16)···
(03D416)···
?
? ?
0
1
(80)
DMA0 cause select register
0016
0016
0
(81)
Static base register (SB)
Flag register (FLG)
DMA1 cause select register
(107)
(108)
(82)
0
0
0
0
0
A-D control register 2
0
?
(83) A-D control register 0
(03D616)··· 0
0
0
?
?
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note1: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset.
Note2: This register is only exist in flash memory version.
Figure 1.6.4. Device's internal status after a reset is cleared
17
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
000016
000116
000216
000316
000416
004016
004116
004216
004316
004416
004516
004616
004716
004816
Processor mode register 0 (PM0)
INT3 interrupt control register (INT3IC)*
000516 Processor mode register 1(PM1)
000616
Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
SI/O4 interrupt control register (S4IC)
INT5 interrupt control register (INT5IC)*
SI/O3 interrupt control register (S3IC)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Reserved register
Address match interrupt enable register (AIER)
000716
000816
000916
000A16
Protect register (PRCR)
004916
000B16 Data bank register (DBR)
000C16
INT4 interrupt control register (INT4IC)*
Bus collision detection interrupt control register (BCNIC)
004A16
004B16
000D16
DMA0 interrupt control register (DM0IC)
000E16
Watchdog timer start register (WDTS)
004C16 DMA1 interrupt control register (DM1IC)
000F16 Watchdog timer control register (WDC)
Key input interrupt control register (KUPIC)
004D16
A-D conversion interrupt control register (ADIC)
001016
004E16
001116
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
Address match interrupt register 0 (RMAD0)
001216
001316
001416
Address match interrupt register 1 (RMAD1)
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
DMA0 source pointer (SAR0)
INT2 interrupt control register (INT2IC)
DMA0 destination pointer (DAR0)
DMA0 transfer counter (TCR0)
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
DMA0 control register (DM0CON)
DMA1 source pointer (SAR1)
003516 DMA1 destination pointer (DAR1)
003616
003716
003816
DMA1 transfer counter (TCR1)
003916
003A16
003B16
003C16
DMA1 control register (DM1CON)
003D16
003E16
003F16
Note 1: M16C/62 (80-pin version) group is not provided with the functions, in whole or in part, of the registers marked with an *. But the relevant
registers need to be dealt with as given on page 7.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.7.1. Location of peripheral unit control registers (1)
18
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
Count start flag (TABSR)
Timer B3, 4, 5 count start flag (TBSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
Timer A1-1 register (TA11)
Timer A2-1 register (TA21)
Timer A4-1 register (TA41)
Timer A0 (TA0)
Timer A1 (TA1)
Timer A2 (TA2)
Three-phase PWM control register 0(INVC0)
Three-phase PWM control register 1(INVC1)
Thrree-phase output buffer register 0(IDB0)
Thrree-phase output buffer register 1(IDB1)
Dead time timer(DTT)
Timer B2 interrupt occurrence frequency set counter(ICTB2)
Timer A3 (TA3)
Timer A4 (TA4)
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
Timer B3 register (TB3)
Timer B4 register (TB4)
Timer B5 register (TB5)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register (TB5MR)
035F16 Interrupt cause select register (IFSR)
036016
SI/O3 transmit/receive register (S3TRR)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
036116
SI/O3 control register (S3C)
SI/O3 bit rate generator (S3BRG)
SI/O4 transmit/receive register (S4TRR)
036216
UART0 transmit buffer register (U0TB)
036316
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
036416
036516
SI/O4 control register (S4C)
SI/O4 bit rate generator (S4BRG)
036616
UART0 receive buffer register (U0RB)
036716
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0)
03AD16 UART1 transmit/receive control register 1 (U1C1)
03AE16
UART1 receive buffer register (U1RB)
03AF16
03B016 UART transmit/receive control register 2 (UCON)
03B116
03B216
03B316
03B416
03B516
03B616
Flash memory control register 1 (FMR1) (Note2)
037616
UART2 special mode register 2(U2SMR2) (Note1)
UART2 special mode register (U2SMR)
UART2 transmit/receive mode register (U2MR)
UART2 bit rate generator (U2BRG)
03B716 Flash memory control register 0 (FMR0) (Note2)
03B816 DMA0 request cause select register (DM0SL)
03B916
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
03BA16
DMA1 request cause select register (DM1SL)
UART2 transmit buffer register (U2TB)
03BB16
03BC16
UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive control register 1 (U2C1)
CRC data register (CRCD)
03BD16
CRC input register (CRCIN)
03BE16
UART2 receive buffer register (U2RB)
03BF16
Note 1 : This register is not exist in M30623EC.
Note 2 : This register is only exist in flash memory version
Note 3 : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
.
Figure 1.7.2. Location of peripheral unit control registers (2)
19
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
A-D register 7 (AD7)
A-D control register 2 (ADCON2)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
D-A register 1 (DA1)
D-A control register (DACON)
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
*
*
Port P3 (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
*
*
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 (P6)
Port P7 (P7)
*
*
*
*
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 (P8)
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
Port P10 direction register (PD10)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
Port control register (PCR)
Note 1: M16C/62 (80-pin version) group is not provided with the functions, in whole or in part, of the registers
marked with an *. But the relevant registers need to be dealt with as given on page 7.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for
read or write.
Figure 1.7.3. Location of peripheral unit control registers (3)
20
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Processor Mode
Single-chip mode
M16C/62 (80-pin version) group support single-chip mode only.
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be ac-
cessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral
functions.
Figure 1.8.1 shows the processor mode register 0 and 1.
Figure 1.8.2 shows the memory map.
21
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Processor mode register 0 (Note)
Symbol
PM0
Address
000416
When reset
b7 b6 b5 b4 b3 b2 b1 b0
0016
0
0
0
0
0
R W
Bit symbol
PM00
Bit name
Function
b1 b0
Processor mode bit
0 0: Single-chip mode
0 1: Inhibited
1 0: Inhibited
PM01
1 1: Inhibited
Reserved bit
PM03
Must always be set to “0”
Software reset bit
The device is reset when this bit
is set to “1”. The value of this bit
is “0” when read.
Reserved bit
Must always be set to “0”
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
000516
When reset
00000XX0
2
0
0
0
0
R W
Bit symbol
Reserved bit
Bit name
Function
Must always be set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
0: The same internal reserved
area as that of M16C/60 and
M16C/61 group
PM13
Internal reserved area
expansion bit (Note 2)
1: Expands the internal RAM area
and internal ROM area to 23 K
bytes and to 256K bytes
respectively. (Note 2)
Reserved bit
PM17
Must always be set to “0”
0 : No wait state
1 : Wait state inserted
Wait bit
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to
this register.
Note 2: Be sure to set this bit to 0 except products whose RAM size and ROM size exceed
15K bytes and 192K bytes respectively.
In using M30625MG/FG, a product having a RAM of more than 15K bytes and a
ROM of more than 192K bytes, set this bit to 1 at the beginning of user program.
Specify D000016 or a subsequent address, which becomes an internal ROM area
if PM13 is set to 0 at the time reset is revoked, for the reset vector table of user
program.
Figure 1.8.1. Processor mode register 0 and 1
22
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Single-chip mode
0000016
SFR area
0040016
Internal
RAM area
XXXXX16
Address XXXXX16 Address YYYYY16
Type No.
M30623M4
Reserved
area
00FFF16
013FF16
017FF16
017FF16
02BFF16
02BFF16
02BFF16
053FF16
F800016
F000016
E800016
E000016
F000016
E000016
E800016
C000016
M30623M8
M30623MA
M30623MC
M30621M8
M30621MC/EC
M30621MA
M30625MG/FG
YYYYY16
Internal
ROM area
FFFFF16
Note: This memory map shows when PM13 is “0”.
However, this shows when PM13 is “1” in M30625MG/FG.
Set PM13 to “1” in M30625MG/FG.
Figure 1.8.2. Memory map
23
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software wait
Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note).
A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode
register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle
is executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. Set this bit
after referring to the recommended operating conditions (main clock input oscillation frequency) of the
electric characteristics.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits.
Table 1.8.1 shows the software wait and bus cycles. Figure 1.8.3 shows example bus timing when using
software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 1.8.1. Software waits and bus cycles
Bus cycle
2 BCLK cycles
Area
SFR
Wait bit
Invalid
0
1
1 BCLK cycle
2 BCLK cycles
Internal
ROM/RAM
24
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software wait
< No wait >
Bus cycle (Note)
BCLK
Write signal
Read signal
Output
Input
Data bus
Address bus
Chip select
Address
Address
< With wait >
Bus cycle (Note)
BCLK
Write signal
Read signal
Input
Output
Data bus
Address
Address bus
Address
Chip select
Note : These example timing charts indicate bus cycle length.
After this bus cycle sometimes come read and write cycles in succession.
Figure 1.8.3. Typical bus timings using software wait
25
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 1.9.1. Main clock and sub clock generating circuits
Main clock generating circuit
• CPU’s operating clock source
• Internal peripheral units’
operating clock source
Ceramic or crystal oscillator
XIN, XOUT
Sub clock generating circuit
• CPU’s operating clock source
• Timer A/B’s count clock
source
Use of clock
Usable oscillator
Crystal oscillator
XCIN, XCOUT
Pins to connect oscillator
Oscillation stop/restart function
Oscillator status immediately after reset
Other
Available
Available
Oscillating
Stopped
Externally derived clock can be input
Example of oscillator circuit
Figure 1.9.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.9.2 shows some examples of
sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.9.1 and 1.9.2 vary with each oscillator used. Use the
values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
IN
XOUT
X
IN
XOUT
Open
(Note)
R
d
Externally derived clock
Vcc
Vss
CIN
C
OUT
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 1.9.1. Examples of main clock
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
CIN
XCOUT
X
CIN
XCOUT
Open
(Note)
R
Cd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Figure 1.9.2. Examples of sub clock
26
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Control
Figure 1.9.3 shows the block diagram of the clock generating circuit.
X
CIN
X
COUT
fC32
1/32
f
1
CM04
f1SIO2
f
AD
f
C
f
f
8
SIO2
f
8
Sub clock
32SIO2
CM10 “1”
Write signal
f
32
S
R
Q
X
IN
X
OUT
b
c
CM07=0
a
d
Divider
RESET
Software reset
NMI
BCLK
f
C
Main clock
CM02
CM07=1
CM05
Interrupt request
level judgment
output
S Q
R
WAIT instruction
c
b
1/2
1/2
1/2
1/2
1/2
a
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
d
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
Details of divider
Figure 1.9.3. Clock generating circuit
27
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-
tained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can
be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expan-
sion and the microprocessor modes.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-
speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
28
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.9.4 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
When reset
4816
Bit symbol
CM00
Bit name
Function
R W
b1 b0
Clock output function
select bit
(Valid only in single-chip
mode)
0 0 : I/O port P5
0 1 : f
1 0 : f
1 1 : f32 output
7
C
output
output
8
CM01
CM02
CM03
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
Port X
C
select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM04
CM05
Main clock (XIN-XOUT
stop bit (Note 3, 4, 5)
)
0 : On
1 : Off
Main clock division select 0 : CM16 and CM17 valid
CM06
CM07
bit 0 (Note 7)
1 : Division by 8 mode
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shiffing to stop mode and at a reset.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and
operating with XIN, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns
pulled up to XOUT (“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: fC32 is not included.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
When reset
2016
0
0
0
0
Bit symbol
CM10
Bit name
Function
R W
All clock stop control bit
(Note4)
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Always set to “0”
Reserved bit
Reserved bit
Reserved bit
Always set to “0”
Always set to “0”
Always set to “0”
X
IN-XOUT drive capacity
0 : LOW
1 : HIGH
CM15
select bit (Note 2)
b7 b6
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
CM16
CM17
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is
fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-
impedance state.
Figure 1.9.4. Clock control registers 0 and 1
29
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2), SI/O3,4
functions provided an external clock is selected. Table 1.9.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
Table 1.9.2. Port status during stop mode
Pin
Single-chip mode
Retains status before stop mode
“H”
Port
CLKOUT
When fc selected
When f8, f32 selected
Retains status before stop mode
30
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Wait Mode
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. Table 1.9.3 shows the status of the ports in
wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table 1.9.3. Port status during wait mode
Pin
Single-chip mode
Retains status before wait mode
Does not stop
Port
CLKOUT
When fC selected
When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit
is “0”.
When the WAIT peripheral function clock stop bit is “1”, the sta-
tus immediately prior to entering wait mode is retained.
31
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Transition of BCLK
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.9.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
Table 1.9.4. Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM07
CM06
CM05
CM04
Invalid
Invalid
Invalid
Invalid
Invalid
1
Operating mode of BCLK
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
Division by 2 mode
0
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Invalid
1
Invalid
1
1
0
0
0
0
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Low-speed mode
1
Low power dissipation mode
32
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power control
Power control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal
clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the internal clock selected. Each peripheral function oper-
ates according to its assigned clock.
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC
clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 1.9.5 is the state transition diagram of the above modes.
33
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power control
Transition of stop mode, wait mode
Reset
All oscillators stopped
CPU operation stopped
WAIT
instruction
CM10 = “1”
Interrupt
Medium-speed mode
(divided-by-8 mode)
Stop mode
Wait mode
Interrupt
Interrupt
WAIT
instruction
All oscillators stopped
CPU operation stopped
High-speed/medium-
speed mode
CM10 = “1”
Stop mode
Wait mode
Interrupt
WAIT
instruction
All oscillators stopped
CPU operation stopped
CM10 = “1”
Interrupt
Low-speed/low power
dissipation mode
Stop mode
Wait mode
Interrupt
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
CM06 = “1”
BCLK : f(XIN)/8
CM07 = “0” CM06 = “1”
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM04 = “1”
(Notes 1, 3)
Main clock is oscillating
Sub clock is oscillating
CM04 = “0”
Medium-speed mode
(divided-by-2 mode)
High-speed mode
Main clock is oscillating
Sub clock is oscillating
BCLK : f(XIN
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-8 mode)
Low-speed mode
CM07 = “0”
(Note 1, 3)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
BCLK : f(XCIN
CM07 = “1”
)
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
CM07 = “1”
(Note 2)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
CM05 = “0”
CM05 = “1”
CM04 = “0”
CM04 = “1”
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
Medium-speed mode
(divided-by-2 mode)
High-speed mode
CM07 = “1” (Note 2)
CM05 = “1”
BCLK : f(XIN
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
BCLK : f(XCIN
CM07 = “1”
)
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
CM06 = “0”
(Notes 1,3)
BCLK : f(XIN)/4
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
Figure 1.9.5. State transition diagram of Power control mode
34
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.9.6 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (ad-
dress 03F316) , SI/O3 control register (address 036216) and SI/O4 control register (address 036616) can
only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs
can be allocated to port P9.
If, after “1” (write-enabled) has been written to the port P9 direction register and SI/Oi control register
(i=3,4) write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically
reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at
000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return
to “0” after a value has been written to an address. The program must therefore be written to return these
bits to “0”.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
When reset
XXXXX000
2
Bit symbol
PRC0
Bit name
Function
0 : Write-inhibited
R W
Enables writing to system clock
control registers 0 and 1 (addresses
1 : Write-enabled
000616 and 000716
)
Enables writing to processor mode
registers 0 and 1 (addresses 000416
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC2
and 000516
)
Enables writing to port P9 direction
register (address 03F316) and SI/Oi
control register (i=3,4) (addresses
0 : Write-inhibited
1 : Write-enabled
036216 and 036616) (Note
)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Figure 1.9.6. Protect register
35
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Overview of Interrupt
Type of Interrupts
Figure 1.10.1 lists the types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
Software
INT instruction
Interrupt
Reset
_______
NMI
________
DBC
Special
Watchdog timer
Single step
Hardware
Address matched
Peripheral I/O (Note)
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 1.10.1. Classification of interrupts
• Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
36
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing
the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts,
so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O
interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-
quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
37
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an “L” is input to the RESET pin.
_______
• NMI interrupt
_______
_______
An NMI interrupt occurs if an “L” is input to the NMI pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
• Key-input interrupt
___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B5 interrupt
These are interrupts that timer B generates.
________
________
• INT0 interrupt through INT2 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
38
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.10.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
MSB
LSB
Low address
Mid address
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
0 0 0 0
0 0 0 0
High address
0 0 0 0
Figure 1.10.2. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.10.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.10.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
Remarks
Undefined instruction
Overflow
Interrupt on UND instruction
Interrupt on INTO instruction
BRK instruction
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
FFFF416 to FFFF716
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
Single step (Note)
Watchdog timer
________
DBC (Note)
NMI
Do not use
_______
External interrupt by input to NMI pin
Reset
Note: Interrupts used for debugging purposes only.
39
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-
dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 1.10.2 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
Table 1.10.2. Interrupts assigned to the variable vector tables and addresses of vector tables
Vector table address
Software interrupt number
Software interrupt number 0
Interrupt source
BRK instruction
Remarks
Address (L) to address (H)
+0 to +3 (Note 1)
Cannot be masked I flag
Software interrupt number 4
Software interrupt number 5
+16 to +19 (Note 1)
+20 to +23 (Note 1)
INT3
Timer B5
Timer B4
Timer B3
Software interrupt number 6
Software interrupt number 7
Software interrupt number 8
Software interrupt number 9
Software interrupt number 10
Software interrupt number 11
+24 to +27 (Note 1)
+28 to +31 (Note 1)
+32 to +35 (Note 1)
+36 to +39 (Note 1)
+40 to +43 (Note 1)
+44 to +47 (Note 1)
SI/O4/INT5 (Note 3, 4)
SI/O3/INT4 (Note 3, 4)
Bus collision detection
DMA0
Software interrupt number 12
Software interrupt number 13
Software interrupt number 14
Software interrupt number 15
Software interrupt number 16
Software interrupt number 17
Software interrupt number 18
Software interrupt number 19
Software interrupt number 20
Software interrupt number 21
Software interrupt number 22
Software interrupt number 23
Software interrupt number 24
Software interrupt number 25
Software interrupt number 26
Software interrupt number 27
Software interrupt number 28
Software interrupt number 29
Software interrupt number 30
Software interrupt number 31
Software interrupt number 32
+48 to +51 (Note 1)
+52 to +55 (Note 1)
+56 to +59 (Note 1)
+60 to +63 (Note 1)
+64 to +67 (Note 1)
+68 to +71 (Note 1)
+72 to +75 (Note 1)
+76 to +79 (Note 1)
+80 to +83 (Note 1)
+84 to +87 (Note 1)
+88 to +91 (Note 1)
+92 to +95 (Note 1)
+96 to +99 (Note 1)
+100 to +103 (Note 1)
+104 to +107 (Note 1)
+108 to +111 (Note 1)
+112 to +115 (Note 1)
+116 to +119 (Note 1)
+120 to +123 (Note 1)
+124 to +127 (Note 1)
+128 to +131 (Note 1)
DMA1
Key input interrupt
A-D
UART2 transmit/NACK (Note 2)
UART2 receive/ACK (Note 2)
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
INT0
INT1
INT2
to
to
Cannot be masked I flag
Software interrupt
Software interrupt number 63
+252 to +255 (Note 1)
Note 1: Address relative to address in interrupt table register (INTB).
Note 2: When IIC mode is selected, NACK and ACK interrupts are selected.
Note 3: It is selected by interrupt request cause bit (bit 6, 7 in address 035F16 ).
Note 4: P1
5/INT3 to P17/INT5 do not connect to outside. INT3 to INT5 interrupt cannot
be used in M16C/62 (80-pin version) group.
40
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selec-
tion bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 1.10.3 shows the memory map of the interrupt control registers.
41
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt control register (Note 2)
Symbol
TBiIC(i=3 to 5)
BCNIC
DMiIC(i=0, 1)
KUPIC
ADIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
Address
004516 to 004716
004A16
004B16, 004C16
004D16
When reset
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
005A16 to 005C16
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Bit name
Function
R
W
Interrupt priority level
select bit
ILVL0
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL2
IR
0 : Interrupt not requested
1 : Interrupt requested
Interrupt request bit
(Note 1)
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Symbol
INTiIC(i=3)
SiIC/INTjIC (i=4, 3)
(j=5, 4)
INTiIC(i=0 to 2)
Address
When reset
004416 XX00X000
2
2
2
2
b7 b6 b5 b4 b3 b2 b1 b0
004816, 004916 XX00X000
004816, 004916 XX00X000
005D16 to 005F16 XX00X000
0
R
W
Bit symbol
ILVL0
Bit name
Function
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1
ILVL2
IR
Interrupt request bit
Polarity select bit
0: Interrupt not requested
1: Interrupt requested
(Note 1)
POL
0 : Selects falling edge
1 : Selects rising edge
Reserved bit
Always set to “0”
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: INT3 to INT5 interrupts cannot be used. However, must set INT3IC to "0016". INT4IC
and INT5IC are shared with S3IC and S4IC respectively. When not using as S3IC and
S4IC, must set INT3IC to "0016".
Note 3: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Figure 1.10.3. Interrupt control registers
42
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.10.3 shows the settings of interrupt priority levels and Table 1.10.4 shows the interrupt levels
enabled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 1.10.4. Interrupt levels enabled according
to the contents of the IPL
Table 1.10.3. Settings of interrupt priority
levels
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
IPL
Enabled interrupt priority levels
b2 b1 b0
IPL
2
IPL1
IPL0
Level 0 (interrupt disabled)
0
0
0
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0
0
0
1
1
0
Low
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
High
43
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP
NOP
FSET
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
I
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
; Enable interrupts.
FSET
I
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
I
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
44
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
dress 0000016. After this, the corresponding interrupt request bit becomes “0”.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.10.4 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction in
interrupt routine
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 1.10.4. Interrupt response time
45
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.10.5.
Table 1.10.5. Time required for executing the interrupt sequence
Interrupt vector address Stack pointer (SP) value
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address
0000
Address bus
Data bus
Indeterminate
Indeterminate
SP-2
SP-4
vec
vec+2
PC
Interrupt
information
SP-2
SP-4
vec
vec+2
contents contents contents contents
R
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 1.10.5. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.10.6 is set in the IPL.
Table 1.10.6. Relationship between interrupts without interrupt priority levels and IPL
Value set in the IPL
Interrupt sources without priority levels
_______
Watchdog timer, NMI
7
0
Reset
Other
Not changed
46
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 1.10.6 shows the state of the stack as it was before the acceptance of the
interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Stack area
Stack area
Address
MSB
Address
MSB
LSB
LSB
[SP]
New stack
pointer value
m – 4
m – 3
m – 2
m – 1
m
m – 4
m – 3
m – 2
m – 1
m
Program counter (PC
Program counter (PC
L
)
M
)
Flag register (FLG )
L
Flag register
(FLG
Program
counter (PC )
H
)
H
[SP]
Stack pointer
value before
interrupt occurs
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
m + 1
m + 1
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 1.10.6. State of stack before and after acceptance of interrupt request
47
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.10.7 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer
indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).
(1) Stack pointer (SP) contains even number
Sequence in which order
registers are saved
Address
Stack area
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
Program counter (PC )
L
(2) Saved simultaneously,
all 16 bits
Program counter (PC
Flag register (FLG
M
)
L
)
(1) Saved simultaneously,
all 16 bits
Flag register
(FLG
Program
counter (PC )
H
)
H
[SP]
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
Program counter (PC )
L
(3)
(4)
Program counter (PC
Flag register (FLG
M
)
Saved simultaneously,
all 8 bits
L
)
(1)
(2)
Program
counter (PC )
Flag register
(FLG
H
H
)
[SP]
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 1.10.7. Operation of saving registers
48
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-
tion before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.10.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset > _N__M___I_ > _D__B___C__ > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 1.10.8. Hardware interrupts priorities
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Figure 1.10.9 shows the circuit that judges the interrupt priority level.
49
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Priority level of each interrupt
INT1
Level 0 (initial value)
High
Timer B2
Timer B0
Timer A3
Timer A1
Timer B4
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer B3
Timer B5
UART1 reception
UART0 reception
UART2 reception/ACK
A-D conversion
DMA1
Priority of peripheral I/O interrupts
(if priority levels are same)
Bus collision detection
Serial I/O4
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission/NACK
Key input interrupt
DMA0
Low
Serial I/O3
Interrupt request level judgment output
To clock generating circuit (Fig.1.9.3)
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
Interrupt
request
accepted
Address match
Watchdog timer
DBC
NMI
Reset
Figure 1.10.9. Maskable interrupts priorities (peripheral I/O interrupts)
50
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
______
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INT Interrupt
______
INT Interrupt
________
_______
INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity
select bit.
As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge
by setting “1” in the INTi interrupt polarity switching bit of the interrupt request cause select register
(035F16). To select both edges, set the polarity switching bit of the corresponding interrupt control register
to ‘falling edge’ (“0”).
Figure 1.10.10 shows the Interrupt request cause select register.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
035F16
When reset
0016
R
W
Bit symbol
Bit name
Function
IFSR0
INT0 interrupt polarity
switching bit
0 : One edge
1 : Two edges
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
INT1 interrupt polarity
switching bit
0 : One edge
1 : Two edges
INT2 interrupt polarity
switching bit
0 : One edge
1 : Two edges
INT3 interrupt polarity
switching bit (Note 1)
0 : One edge
1 : Two edges
INT4 interrupt polarity
switching bit (Note 1)
0 : One edge
1 : Two edges
INT5 interrupt polarity
switching bit (Note 1)
0 : One edge
1 : Two edges
Interrupt request cause
select bit
0 : SIO3
1 : INT4
Interrupt request cause
select bit
0 : SIO4
1 : INT5
Note 1: INT3 to INT5 interrupts cannot be used in M16C/62 (80-pin version) group. Thus,
the setting value of these bits are invalid.
Note 2: INT3 to INT5 interrupts cannot be used in M16C/62 (80-pin version) group.
Figure 1.10.10. Interrupt request cause select register
51
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
NMI Interrupt
________
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
______
NMI Interrupt
______
______
______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.10.11 shows the block diagram of the key input interrupt. Note that if an
“L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as
an interrupt.
Port P10
4-P107 pull-up
select bit
Pull-up
Key input interrupt control register
(address 004D16
)
transistor
Port P10
register
7 direction
Port P10
7
direction register
P10
7
/KI
3
2
Port P10
register
6 direction
Pull-up
transistor
Key input interrupt
request
Interrupt control circuit
P10
6
/KI
Pull-up
transistor
Port P10
register
5
direction
direction
P105/KI1
Port P10
register
4
Pull-up
transistor
P104/KI0
Figure 1.10.11. Block diagram of key input interrupt
52
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC)
for an address match interrupt varies depending on the instruction being executed.
Figure 1.10.12 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXXXX00
2
Bit symbol
AIER0
Bit name
Function
R W
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Address match interrupt 1
enable bit
AIER1
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Address match interrupt register i (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
When reset
X0000016
X0000016
b0
Function
Values that can be set
R W
Address setting register for address match interrupt
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Figure 1.10.12. Address match interrupt-related registers
53
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
_______
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point
at the beginning of a program. Concerning the first instruction immediately after reset, generating any
_______
interrupts including the NMI interrupt is prohibited.
(3) The _N__M___I_ interrupt
_______
_______
•The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if
unused.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input.
_______
• Do not reset the CPU with the input to the NMI pin being in the “L” state.
_______
• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to
_______
the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned
down.
_______
• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to
_______
the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved.
In this instance, the CPU is returned to the normal state by a later interrupt.
_______
• Signals input to the NMI pin require an “L” level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 to
_______
INT2 regardless of the CPU operation clock.
________
_______
• When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to “1”.
After changing the polarity, set the interrupt request bit to “0”. Figure 1.10.13 shows the procedure for
______
changing the INT interrupt generate factor.
54
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
______
Figure 1.10.13. Switching condition of INT interrupt request
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP
NOP
FSET
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
I
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
; Enable interrupts.
FSET
I
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
I
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
55
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by
16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7
of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calcu-
lated as given below. The watchdog timer's period is, however, subject to an error due to the pre-scaler.
With XIN chosen for BCLK
pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768)
Watchdog timer period =
BCLK
With XCIN chosen for BCLK
pre-scaler dividing ratio (2) X watchdog timer count (32768)
Watchdog timer period =
BCLK
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
pre-scaler, then the watchdog timer's period becomes approximately 32.8 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 1.11.1 shows the block diagram of the watchdog timer. Figure 1.11.2 shows the watchdog timer-
related registers.
Prescaler
“CM07 = 0”
“WDC7 = 0”
1/16
“CM07 = 0”
“WDC7 = 1”
Watchdog timer
interrupt request
1/128
1/2
Watchdog timer
BCLK
“CM07 = 1”
Write to the watchdog timer
start register
Set to
“7FFF16
(address 000E16
)
”
RESET
Figure 1.11.1. Block diagram of watchdog timer
56
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
When reset
000XXXXX
0
0
2
Bit symbol
Bit name
Function
R W
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Must always be set to “0”
Reserved bit
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
R W
this register. The watchdog timer value is always initialized to “7FFF16
regardless of whatever value is written.
”
Figure 1.11.2. Watchdog timer control and start registers
57
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-
bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.12.1 shows the block diagram
of the DMAC. Table 1.12.1 shows the DMAC specifications. Figures 1.12.2 to 1.12.4 show the registers
used by the DMAC.
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016
DMA0 destination pointer DAR0 (20)
)
(addresses 002616 to 002416
)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016
DMA1 destination pointer DAR1 (20)
(addresses 002916, 002816
)
)
)
DMA0 transfer counter TCR0 (16)
(addresses 003616 to 003416
)
DMA1 forward address pointer (20) (Note)
DMA1 transfer counter reload register TCR1 (16)
(addresses 003916, 003816
DMA latch high-order bits DMA latch low-order bits
DMA1 transfer counter TCR1 (16)
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 1.12.1. Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
58
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
Table 1.12.1. DMAC specifications
Item
No. of channels
Transfer memory space
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
________
DMA request factors (Note)
Falling edge of INT0 or INT1, or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer and reception interrupt requests
UART1 transfer and reception interrupt requests
UART2 transfer and reception interrupt requests
Serial I/O3, 4 interrpt requests
A-D conversion interrupt requests
Software triggers
Channel priority
Transfer unit
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
• Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to
“0”, and the DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
DMA interrupt request generation timing When an underflow occurs in the transfer counter
Active
When the DMA enable bit is set to “1”, the DMAC is active.
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
Inactive
• When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active, the
value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer,and the value
of the transfer counter reload register is reloaded to the transfer counter.
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Forward address pointer and
reload timing for transfer
counter
Writing to register
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
59
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA0 request cause select register
Symbol
DM0SL
Address
03B816
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Function
Bit symbol
DSEL0
Bit name
R
W
b3 b2 b1 b0
DMA request cause
select bit
0 0 0 0 : Falling edge of INT0 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4 (DMS=0)
/two edges of INT0 pin (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)
Timer B3 (DMS=1)
1 0 0 0 : Timer B1 (DMS=0)
Timer B4 (DMS=1)
1 0 0 1 : Timer B2 (DMS=0)
Timer B5 (DMS=1)
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit
DSEL1
DSEL2
DSEL3
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMA request cause
expansion bit
0 : Normal
1 : Expanded cause
DMS
DSR
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Software DMA
request bit
Figure 1.12.2. DMAC register (1)
60
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA1 request cause select register
Symbol
DM1SL
Address
03BA16
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Function
Bit symbol
DSEL0
R
W
b3 b2 b1 b0
DMA request cause
select bit
0 0 0 0 : Falling edge of INT1 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3(DMS=0)
DSEL1
DSEL2
DSEL3
/serial I/O3 (DMS=1)
0 1 1 0 : Timer A4 (DMS=0)
/serial I/O4 (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)
/two edges of INT1 (DMS=1)
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 receive
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
0 : Normal
1 : Expanded cause
DMA request cause
expansion bit
DMS
DSR
Software DMA
request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMiCON(i=0,1)
Address
002C16, 003C16
When reset
00000X00
2
Bit symbol
DMBIT
Bit name
Function
R
W
Transfer unit bit select bit 0 : 16 bits
1 : 8 bits
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMASL
DMAS
DMAE
0 : DMA not requested
1 : DMA requested
DMA request bit (Note 1)
DMA enable bit
(Note 2)
0 : Disabled
1 : Enabled
Source address direction
select bit (Note 3)
0 : Fixed
1 : Forward
DSD
DAD
Destination address
direction select bit (Note 3)
0 : Fixed
1 : Forward
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
Figure 1.12.3. DMAC register (2)
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAi source pointer (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
R W
• Source pointer
Stores the source address
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi destination pointer (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
R W
• Destination pointer
Stores the destination address
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
R W
• Transfer counter
Set a value one less than the transfer count
000016 to FFFF16
Figure 1.12.4. DMAC register (3)
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.12.5 shows the example of the transfer cycles for a source read. For convenience, the destina-
tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown.
In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-
tive conditions to both the destination write cycle and the source read cycle. For example (2) in Figure
1.12.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the
source read cycle and the destination write cycle.
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(1) 8-bit transfers
16-bit transfers from even address and the source address is even.
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1 Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source + 1
Source
CPU use
Destination
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.12.5. Example of the transfer cycles for a source read
64
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.12.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.12.2. No. of DMAC transfer cycles
Single-chip mode
Transfer unit
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
Bus width
16-bit
Access address
Even
No. of read cycles
No. of write cycles
1
1
1
2
1
1
1
2
(BYTE= “L”)
16-bit
Odd
Even
(BYTE = “L”)
Odd
Coefficient j, k
Internal memory
Internal ROM/RAM Internal ROM/RAM
SFR area
2
No wait
1
With wait
2
65
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA enable bit
Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations
at the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the
forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given
above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA
enable bit.
DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of
DMA request factors for each channel.
DMA request factors include the following.
* Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
* External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMAi factor selection register.
The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state
(regardless of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before data
transfer starts.
In addition, it can be set to "0" by use of a program, but cannot be set to "1".
There can be instances in which a change in DMA request factor selection bit causes the DMA request bit
to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is
changed.
The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately
before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the
DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the
DMAC is active, read the DMA enable bit.
Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1"
due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control
register to turn to "1" due to several factors.
Turning the DMA request bit to "1" due to an internal factor is timed to be effected immediately before
the transfer starts.
(2) External factors
An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends
on which DMAC channel is used).
Selecting the INTi pins as external factors using the DMA request factor selection bit causes input
from these pins to become the DMA transfer request signals.
The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with
the signal's edge applicable to the function specified by the DMA request factor selection bit (synchro-
nizes with the trailing edge of the input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data
transfer starts similarly to the state in which an internal factor is selected.
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period
from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels
concurrently turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start
data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU
finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur.
Figure 1.12.6 An example of DMA transfer effected by external factors.
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
BCLK
DMA0
Obtainm
ent of the
bus right
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 1.12.6. An example of DMA transfer effected by external factors
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(six). All these timers function independently. Figures 1.13.1 and 1.13.2 show the block diagram of timers.
Clock prescaler
f
1
8
fC32
XIN
1/32
Reset
X
CIN
f
1/8
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
f
32
1/4
f1 f8 f32 fC32
• Timer mode
• One-shot mode
• PWM mode
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer A0
Noise
filter
TA0IN
• Event counter mode
• Timer mode
• One-shot mode
Timer A1
• Event counter mode
• Timer mode
• One-shot mode
Timer A2
Timer A3
Timer A4
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Noise
filter
TA3IN
TA4IN
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Noise
filter
• Event counter mode
Timer B2 overflow
Note 1: The TA0IN pin (P71) is shared with RxD2, SCL and the TB5IN pin, so be careful.
Note 2: Timer A1 and A2 have no pin to perform input/output. Thus I/O functions like as external event input, PWM output
and one-shot output cannot be used.
Figure 1.13.1. Timer A block diagram
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
Clock prescaler
f
f
1
8
fC32
XIN
1/32
Reset
X
CIN
1/8
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
f
32
1/4
f1 f8 f32 fC32
Timer A
• Timer mode
• Pulse width measuring mode
Timer B0 interrupt
Noise
filter
Timer B0
TB0IN
• Event counter mode
• Timer mode
Timer B1 interrupt
Timer B2 interrupt
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
TB2IN
Timer B2
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B3 interrupt
Noise
filter
TB3IN
TB4IN
Timer B3
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B4 interrupt
Timer B5 interrupt
Noise
filter
Timer B4
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
TB5IN
Timer B5
• Event counter mode
Note 1: The TB5IN pin (P71) is shared with RxD
2, SCL and the TA0IN pin, so be careful.
Note 2: TB1IN pin is not connect to outside. Thus, timer B1 can use neither in external event count mode or
pulse width measurement mode.
Figure 1.13.2. Timer B block diagram
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A
Figure 1.13.3 shows the block diagram of timer A. Figures 1.13.4 to 1.13.6 show the timer A-related registers.
Except in event counter mode, timers A0 through A4 all have the same function. However, in M16C/62 (80-
pin version) group, timer A1 and A2 are used for internal timer since timer A1 and A2 have no pin to perform
input/output. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f
1
Low-order
8 bits
High-order
8 bits
f8
• Timer
(gate function)
f
32
Reload register (16)
f
C32
• Event counter
Clock selection
Counter (16)
Polarity
selection
Up count/down count
TAiIN
Always down count except
in event counter mode
(i = 0 to 4)
Count start flag
(Address 038016
)
TAi
Addresses
TAj
TAk
Down count
Timer A0 038716 038616
Timer A1 038916 038816
Timer A2 038B16 038A16 Timer A1 Timer A3
Timer A3 038D16 038C16 Timer A2 Timer A4
Timer A4 038F16 038E16 Timer A3 Timer A0
Timer A4 Timer A1
Timer A0 Timer A2
TB2 overflow
External
trigger
Up/down flag
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
(Address 038416
)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Note 1: The TA0IN pin (P71) is shared with RxD2, SCL and the TB5IN pin, so be careful.
Note 2: TA1IN, TA1OUT, TA2IN and TA2OUT do not connect to outside. Do not set functions using these pins.
Figure 1.13.3. Block diagram of timer A
Timer Ai mode register
Symbol
Address
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
TAiMR(i=0 to 4) 039616 to 039A16
R W
Bit symbol
TMOD0
Bit name
Function
b1 b0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Figure 1.13.4. Timer A-related registers (1)
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer Ai register (Note)
Symbol
TA0
TA1
TA2
TA3
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
(b15)
(b8)
b0 b7
038716,038616
038916,038816
038B16,038A16
038D16,038C16
038F16,038E16
b7
b0
TA4
Values that can be set
000016 to FFFF16
Function
R W
• Timer mode
Counts an internal count source
• Event counter mode
Counts pulses from an external source or timer overflow
000016 to FFFF16
000016 to FFFF16
• One-shot timer mode
Counts a one shot width
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE16
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FE16
(Both high-order
and low-order
addresses)
Note: Read and write data in 16-bit units.
Count start flag
Symbol
TABSR
Address
038016
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
R W
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Up/down flag
Symbol
UDF
Address
038416
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
TA0UD
Bit name
Function
Timer A0 up/down flag
0 : Down count
1 : Up count
TA1UD
TA2UD
TA3UD
TA4UD
TA2P
Timer A1 up/down flag
Timer A2 up/down flag
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
Timer A3 up/down flag
Timer A4 up/down flag
(Note)
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
Timer A2 two-phase pulse
signal processing select bit
TA3P
TA4P
Timer A3 two-phase pulse
signal processing select bit
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Timer A4 two-phase pulse
signal processing select bit
Note: Since timer A2 have no pin to perform input/output, must set "0" in this bit.
Figure 1.13.5. Timer A-related registers (2)
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
One-shot start flag
Symbol
ONSF
Address
038216
When reset
b7 b6 b5 b4 b3 b2 b1 b0
00X00000
2
R W
Bit symbol
Bit name
Function
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
1 : Timer start
When read, the value is “0”
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
b7 b6
TA0TGL
TA0TGH
Timer A0 event/trigger
select bit
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
Trigger select register
Symbol
TRGSR
Address
038316
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA1TGL
Bit name
Function
R W
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (Note1,2)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
TA1TGH
TA2TGL
b3 b2
Timer A2 event/trigger
select bit
0 0 : Input on TA2IN is selected (Note1,2)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
TA2TGH
TA3TGL
TA3TGH
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (Note1)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
Timer A4 event/trigger
select bit
TA4TGL
TA4TGH
0 0 : Input on TA4IN is selected (Note1)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note 1: Set the corresponding port direction register to “0”.
Note 2: Since TA1IN and TA2IN are not connected to external pin, do not select these
functions.
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
2
Bit symbol
Bit name
Function
R W
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
0 : No effect
1 : Prescaler is reset
CPSR
Clock prescaler reset flag
(When read, the value is “0”)
Figure 1.13.6. Timer A-related registers (3)
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.13.1.) Figure 1.13.7
shows the timer Ai mode register in timer mode.
Table 1.13.1. Specifications of timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Down count
•
When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing When the timer underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or gate input
Programmable I/O port or pulse output
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
• Gate function
Select function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Note: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT).
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i=0 to 4) 039616 to 039A16
0
0 0
Bit symbol
Bit name
Function
R W
b1 b0
Operation mode
select bit
TMOD0
TMOD1
MR0
0 0 : Timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
b4 b3
(Note 4)
MR1
MR2
Gate function select bit
(Note 4)
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is
held “L” (Note 3)
1 1 : Timer counts only when TAiIN pin is
held “H” (Note 3)
MR3
0 (Must always be fixed to “0” in timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Note 4: Set these bits "0" in timer A1 and A2 mode registers.
Figure 1.13.7. Timer Ai mode register in timer mode
73
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 1.13.2 lists timer specifications when counting a single-phase external signal.
Figure 1.13.8 shows the timer Ai mode register in event counter mode.
Table 1.13.3 lists timer specifications when counting a two-phase external signal. Figure 1.13.9 shows
the timer Ai mode register in event counter mode.
Table 1.13.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
•
External signals input to TAiIN pin (effective edge can be selected by software)
• TB2 overflow, TAj overflow
Count operation
Divide ratio
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or count source input
Programmable I/O port, pulse output, or up/down count select input
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note 1: This does not apply when the free-run function is selected.
Note 2: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT).
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TAiMR(i = 0, 1)
Address
039616, 039716
When reset
0016
0
0 1
Bit symbol
Bit name
Function
R W
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
0 1 : Event counter mode (Note 1)
0 : Pulse is not output
Pulse output function
select bit
(Note 5)
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TAiOUT pin is a pulse output pin)
MR1
MR2
Count polarity
select bit (Note 3,5)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 4)
MR3
0 (Must always be fixed to “0” in event counter mode)
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
Invalid in event counter mode
Can be “0” or “1”
TCK1
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Note 5: Set these bits "0" in timer A1 and A2 mode registers.
Figure 1.13.8. Timer Ai mode register in event counter mode
74
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Table 1.13.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4)
Item
Count source
Count operation
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pin
• Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Divide ratio
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing Timer overflows or underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Two-phase pulse input
Two-phase pulse input
Count value can be read out by reading timer A2, A3, or A4 register
• When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
• Normal processing operation
Select function
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is “H”
TAiOUT
TAiIN
(i=2,3)
Up
count
Up
count
Up
Down
Down
count
Down
count
count count
• Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count down all edges
Count down all edges
Count up all edges
TAiIN
(i=3,4)
Count up all edges
Note 1: This does not apply when the free-run function is selected.
Note 2: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT).
75
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer Ai mode register
(When not using two-phase pulse signal processing)
Symbol
Address
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
TAiMR(i = 2 to 4) 039816 to 039A16
0
0 1
R W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode select bit
0 1 : Event counter mode
Pulse output function
0 : Pulse is not output
MR0
select bit
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
(Note 6)
Count polarity
select bit (Note 2,6)
0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
MR1
MR2
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 3)
Up/down switching
cause select bit
(Note 6)
0 : (Must always be “0” in event counter mode)
MR3
TCK0
0 : Reload type
1 : Free-run type
Count operation type
select bit
Two-phase pulse signal
processing operation
select bit (Note 4,5)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0”.
Note 4: This bit is valid for the timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0 ”or “1”.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Note 6: Set these bits "0" in timer A2 and A3 mode registers.
Timer Ai mode register
(When using two-phase pulse signal processing)
Symbol
Address
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
TAiMR(i = 2 to 4) 039816 to 039A16
0
1 0 0 0 1
Bit symbol
Bit name
Function
R W
b1 b0
TMOD0
TMOD1
Operation mode select bit
0 1 : Event counter mode
0 (Must always be “0” when using two-phase pulse signal
processing)
MR0
MR1
MR2
0 (Must always be “0” when using two-phase pulse signal
processing)
1 (Must always be “1” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
MR3
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK0
Two-phase pulse
processing operation
select bit (Note 1)(Note 2)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: This bit is valid for timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0” or “1”.
Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Note 3: Timer A2 cannot be used for two-phase pulse signal processing.
Figure 1.13.9. Timer Ai mode register in event counter mode
76
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.13.4.) When a trigger occurs, the timer starts up and
continues operating for a given period. Figure 1.13.10 shows the timer Ai mode register in one-shot timer mode.
Table1.13.4. Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio
1/n
n : Set value
Count start condition
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing The count reaches 000016
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Programmable I/O port or pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Note: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT).
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i = 0 to 4) 039616 to 039A16
0
1 0
Bit symbol
Bit name
R W
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
1 0 : One-shot timer mode
Pulse output function
0 : Pulse is not output
select bit
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
(Note 4)
MR1
MR2
0 : Falling edge of TAiIN pin's input signal (Note 3)
1 : Rising edge of TAiIN pin's input signal (Note 3)
External trigger select
bit (Note 2,4)
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
Trigger select bit
MR3
0 (Must always be “0” in one-shot timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0”.
Note 4: Set these bits "0" in timer A1 and A2 mode registers.
Figure 1.13.10. Timer Ai mode register in one-shot timer mode
77
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.13.5.) In this mode, the
counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Timer A1
and A2 have no output pin, so it doesn't work in this mode. Figure 1.13.11 shows the timer Ai mode
register in pulse width modulation mode. Figure 1.13.12 shows the example of how a 16-bit pulse width
modulator operates. Figure 1.13.13 shows the example of how an 8-bit pulse width modulator operates.
Table 1.13.5. Timer specifications in pulse width modulation mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
• High level width n / fi n : Set value
(2 -1) / fi fixed
•
16-bit PWM
16
(m+1) / fi
• Cycle time
•
•
8-bit PWM
High level width
Cycle time
n
(2
n : values set to timer Ai register’s high-order address
-1) (m+1) / fi m : values set to timer Ai register’s low-order address
8
Count start condition
• External trigger is input
• The timer overflows
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Note: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT).
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
1
1
1
TAiMR(i=0 to 4) 039616 to 039A16
R W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 1 : PWM mode
MR0
MR1
1 (Must always be “1” in PWM mode) (Note 3)
External trigger select
bit (Note 1,3)
0: Falling edge of TAiIN pin's input signal (Note 2)
1: Rising edge of TAiIN pin's input signal (Note 2)
MR2
MR3
0: Count start flag is valid
1: Selected by event/trigger select register
Trigger select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
16/8-bit PWM mode
select bit
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding port direction register to “0”.
Note 3: Set these bits "0" in timer A1 and A2 mode registers.
Figure 1.13.11. Timer Ai mode register in pulse width modulation mode
78
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Condition : Reload register = 000316, when external trigger
(rising edge of TAiIN pin input signal) is selected
1 / fi X
(216 – 1)
Count source
“H”
“L”
TAiIN pin
input signal
Trigger is not generated by this signal
1 / f
i
X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
Timer Ai interrupt
request bit
fi
: Frequency of count source
(f , f , f32, fC32
1
8
)
Cleared to “0” when interrupt request is accepted, or cleared by software
.
Note 1: n = 000016 to FFFE16
Note 2: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT).
Figure 1.13.12. Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi X (m + 1) X (28 – 1)
Count source (Note1)
“H”
TAiIN pin input signal
“L”
1 / fi X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2)
“L”
1 / fi X (m + 1) X n
“H”
PWM pulse output
from TAiOUT pin
“L”
“1”
Timer Ai interrupt
request bit
“0”
fi : Frequency of count source
Cleared to “0” when interrupt request is accepted, or cleaerd by software
(f1, f8, f32, fC32)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16.
Note 4: Timer A1 and A2 do not have I/O port (TAiIN and TAiOUT).
Figure 1.13.13. Example of how an 8-bit pulse width modulator operates
79
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer B
Figure 1.13.14 shows the block diagram of timer B. Figures 1.13.15 and 1.13.16 show the timer B-related
registers. However, timer B1 is used for internal timer since timer B1 does not have input port.
Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f
1
• Timer
Reload register (16)
• Pulse period/pulse width measurement
f
f
8
32
fC32
Counter (16)
• Event counter
Count start flag
Polarity switching
and edge pulse
TBiIN
(i = 0 to 5)
(address 038016
)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Address
TBj
TBj overflow
Timer B0 039116 039016 Timer B2
Timer B1 039316 039216 Timer B0
Timer B2 039516 039416 Timer B1
Timer B3 035116 035016 Timer B5
Timer B4 035316 035216 Timer B3
Timer B5 035516 035416 Timer B4
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Note: TB1IN does not connect to outside. Thus, do not select the function using this pin.
Figure 1.13.14. Block diagram of timer B
Timer Bi mode register
Symbol
Address
When reset
b7 b6 b5 b4 b3 b2 b1 b0
TBiMR(i = 0 to 5) 039B16 to 039D16
035B16 to 035D16
00XX0000
2
00XX0000
2
R
W
Bit symbol
Function
Bit name
b1 b0
TMOD0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
TMOD1
measurement mode
1 1 : Inhibited
(Note 3)
MR0
MR1
MR2
Function varies with each operation mode
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Note 3: Do not set this mode since timer B1 does not have input port.
Figure 1.13.15. Timer B-related registers (1)
80
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Address
When reset
Timer Bi register (Note)
039116, 039016 Indeterminate
039316, 039216 Indeterminate
039516, 039416 Indeterminate
035116, 035016 Indeterminate
035316, 035216 Indeterminate
035516, 035416 Indeterminate
(b15)
(b8)
b7
b0 b7
b0
Values that can be set
000016 to FFFF16
Function
R W
• Timer mode
Counts the timer's period
• Event counter mode
000016 to FFFF16
Counts external pulses input or a timer overflow
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note 1: Read and write data in 16-bit units.
Note 2: Timer B1 is provided with no input pin, so it does not work in this mode. The
overflow of the timer, however, can be counted in event counter mode.
Count start flag
Symbol
TABSR
Address
038016
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
TA0S
Bit name
Function
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Timer B3, 4, 5 count start flag
Symbol
TBSR
Address
034016
When reset
000XXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
R W
Bit symbol
Bit name
Function
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
TB3S
TB4S
TB5S
Timer B3 count start flag
Timer B4 count start flag
Timer B5 count start flag
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
Bit name
Function
R W
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
Clock prescaler reset flag
Figure 1.13.16. Timer B-related registers (2)
81
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.13.6.) Figure 1.13.17
shows the timer Bi mode register in timer mode.
Table 1.13.6. Timer specifications in timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Programmable I/O port
Count value is read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Note: Timer B1 works exclusively as an internal timer since timer B1 does not have input port (TB1IN).
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
TBiMR(i=0 to 5) 039B16 to 039D16
035B16 to 035D16
00XX0000
00XX0000
2
0
0
2
Bit
name
Function
Bit symbol
TMOD0
TMOD1
MR0
R
W
b1 b0
Operation mode select bit
0 0 : Timer mode
Invalid in timer mode
Can be “0” or “1”
MR1
MR2
0 (Fixed to “0” in timer mode ; i = 0, 3)
(Note 1)
(Note 2)
Nothing is assiigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write “0”. The value, if read, turns out
to be indeterminate.
MR3
Invalid in timer mode.
In an attempt to write to this bit, write “0”. The value, if read in
timer mode, turns out to be indeterminate.
b7 b6
Count source select bit
TCK0
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 1.13.17. Timer Bi mode register in timer mode
82
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.13.7.)
Figure 1.13.18 shows the timer Bi mode register in event counter mode.
Table 1.13.7. Timer specifications in event counter mode
Item
Specification
Count source
• External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Count source input
Count value can be read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Note: Timer B1 works exclusively as an internal timer since timer B1 does not have input port (TB1IN).
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
TBiMR(i=0 to 5) 039B16 to 039D16
035B16 to 035D16
00XX0000
2
0
1
00XX0000
2
R
W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
0 1 : Event counter mode
b3 b2
Count polarity select
bit (Note 1)
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
MR1
1 0 : Counts external signal's
falling and rising edges
1 1 : Inhibited
0 (Fixed to “0” in event counter mode; i = 0, 3)
MR2
MR3
(Note 2)
(Note 3)
Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write “0”. The value, if read, turns out
to be indeterminate.
Invalid in event counter mode.
In an attempt to write to this bit, write “0”. The value, if read in
event counter mode, turns out to be indeterminate.
TCK0
TCK1
Invalid in event counter mode. Can be “0” or “1”.
0 : Input from TBiIN pin (Note 4)
1 : TBj overflow
Event clock select
(j = i – 1; however, j = 2 when i = 0,
j = 5 when i = 3)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”. Since Timer B1 does
not have TB1IN pin, the setting value of this bit is invaid.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Note 4: Set the corresponding port direction register to “0”. Since Timer B1 does not
have TB1IN pin, do not use TB1IN pin as event clock.
Figure 1.13.18. Timer Bi mode register in event counter mode
83
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.13.8.)
However, this function cannot be used since timer B1 does not have input port. Figure 1.13.19 shows the
timer Bi mode register in pulse period/pulse width measurement mode. Figure 1.13.20 shows the opera-
tion timing when measuring a pulse period. Figure 1.13.21 shows the operation timing when measuring
a pulse width.
Table 1.13.8. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start flag is set (= 1)
Count start condition
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function
Read from timer
Measurement pulse input
When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
TBiMR(i=0 to 5) 039B16 to 039D16
035B16 to 035D16
00XX0000
2
1
0
00XX0000
2
R
W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 0 : Pulse period / pulse width
measurement mode
b3 b2
MR0
MR1
Measurement mode
select bit
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0, 3)
MR2
(Note 2)
(Note 3)
Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
Timer Bi overflow
flag ( Note 1)
0 : Timer did not overflow
1 : Timer has overflowed
MR3
TCK0
TCK1
b7 b6
Count source
select bit
0 0 : f
0 1 : f
1
8
1 0 : f32
1 1 : fC32
Note 1: The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Figure 1.13.19. Timer Bi mode register in pulse period/pulse width measurement mode
84
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
When measuring measurement pulse time interval from falling edge to falling edge
Count source
“H”
“L”
Measurement pulse
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.13.20. Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
“L”
Transfer
(measured value)
Transfer
(measured value)
Transfer
(indeterminate
value)
Transfer
(measured
value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.13.21. Operation timing when measuring a pulse width
85
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O
Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4.
UART0 to 2
UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate
independently of each other.
Figure 1.14.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.14.2 and 1.14.3 show
the block diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART.
UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is
used for the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It
also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD
pin are different in level. UART and IIC mode can be used in UART2.
Table 1.14.1 shows the comparison of functions of UART0 through UART2, and Figures 1.14.4 to 1.14.8
show the registers related to UARTi.
Note: SIM : Subscriber Identity Module
Table 1.14.1. Comparison of functions of UART0 through UART2
Function
UART0
UART1
UART2
Possible
CLK polarity selection
Possible
Possible
(Note 1) Possible (Note 1)
(Note 1) Possible (Note 1)
(Note 1) Possible (Note 1)
Possible (Note 1)
(Note 5)
(Note 2)
(Note 1)
LSB first / MSB first selection
Possible
Possible
Impossible
Continuous receive mode selection
Possible
Transfer clock output from multiple
pins selection
Impossible
Possible
Separate CTS/RTS pins
Serial data logic switch
Sleep mode selection
Impossible
Impossible (Note 5)
Impossible
Possible
Impossible
Possible
Impossible
Possible
(Note 4)
(Note 3) Possible (Note 3)
Impossible
TxD, RxD I/O polarity switch
TxD, RxD port output format
Parity error signal output
Bus collision detection
Impossible
(Note 5)
N-channel open-drain
CMOS output
Impossible
Impossible
CMOS output
Impossible
Impossible
output
(Note 6)
Possible
(Note 4)
Possible
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
Note 5: Since CLK2 and CTS2/RTS2 do not connect to outside, this function cannot be used.
Note 6: Connect this pin to Vcc via a pull-up resistor on the outside.
86
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
(UART0)
RxD0
TxD0
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate generator
f
f
f
1
Internal
(address 03A116
)
8
Transmit
clock
UART transmission
1/16
32
1 / (n0+1)
Transmission
control circuit
Clock synchronous type
External
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK0
CTS/RTS disabled
CTS/RTS selected
RTS
0
CTS0 / RTS0
Vcc
CTS/RTS disabled
CTS/RTS separated
CTS
0
CTS0 from UART1
(UART1)
RxD1
TxD1
UART reception
Receive
clock
1/16
Transmit/
receive
unit
Reception
control circuit
Clock source selection
Bit rate generator
(address 03A916
Clock synchronous type
f
1
)
Internal
f
8
UART transmission
1/16
Transmit
clock
1 / (n1+1)
f
32
Transmission
control circuit
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
1/2
External
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK1
CTS/RTS disabled
CTS/RTS separated
RTS
1
CTS
1
/ RTS
1
1
V
CC
/ CTS
0
/ CLKS
Clock output pin
select switch
CTS/RTS disabled
CTS
1
CTS
0
CTS0 to UART0
(UART2)
TxD
RxD polarity
reversing circuit
polarity
reversing
circuit
RxD
2
TxD2
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate generator
(address 037916
f
f
f
1
Internal
)
8
UART transmission
1/16
Transmit
clock
32
1 / (n2+1)
Transmission
control circuit
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
1/2
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
Note: CLK and CTS/RTS of UART2 do not connect to outside.
Clock synchronous serial I/O mode cannot be used in UART2.
Figure 1.14.1. Block diagram of UARTi (i = 0 to 2)
87
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Clock
synchronous type
UART (7 bits)
UART (8 bits)
Clock
UARTi receive register
synchronous
type
UART (7 bits)
PAR
disabled
1SP
2SP
SP
SP
PAR
RxDi
PAR
enabled
UART
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
UARTi receive
buffer register
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D
2
D1
D0
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
UARTi transmit
buffer register
D
7
D6
D5
D4
D
3
D2
D1
D0
D
8
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UART (9 bits)
PAR
enabled
UART
2SP
1SP
SP
SP
PAR
TxDi
Clock
synchronous
type
PAR
disabled
UART (7 bits)
UARTi transmit register
UART (7 bits)
UART (8 bits)
SP: Stop bit
PAR: Parity bit
“0”
Clock synchronous
type
Figure 1.14.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
88
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
No reverse
Reverse
RxD data
reverse circuit
RxD2
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
UART2 receive register
PAR
disabled
UART(7 bits)
1SP
SP
PAR
SP
2SP
Clock
synchronous type
PAR
enabled
UART
UART
(9 bits)
UART
(8 bits)
UART
(9 bits)
UART2 receive
buffer register
0
0
0
0
0
0
0
D8
D7
D6
D
5
D4
D3
D2
D1
D0
Address 037E16
Address 037F16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
UART2 transmit
buffer register
D7
D6
D5
D
4
D3
D2
D
1
D0
D
8
Address 037A16
Address 037B16
UART
(8 bits)
UART
(9 bits)
UART
(9 bits)
Clock
synchronous type
PAR
enabled
UART
2SP
SP
SP
PAR
1SP
Clock
synchronous
type
PAR
disabled
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART2 transmit register
“0”
Clock
synchronous type
Error signal output
disable
No reverse
TxD data
reverse circuit
Error signal
output circuit
TxD2
Reverse
Error signal output
enable
SP: Stop bit
PAR: Parity bit
Note: Clock synchronous serial I/O mode cannot be used in UART2.
Figure 1.14.3. Block diagram of UART2 transmit/receive unit
89
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit buffer register
Symbol
U0TB
U1TB
U2TB
Address
When reset
Indeterminate
Indeterminate
Indeterminate
(b15)
b7
(b8)
b0 b7
03A316, 03A216
03AB16, 03AA16
037B16, 037A16
b0
Function
R W
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turn out to be indeterminate.
UARTi receive buffer register
(b8)
b0 b7
(b15)
b7
Symbol
U0RB
U1RB
U2RB
Address
When reset
Indeterminate
Indeterminate
Indeterminate
b0
03A716, 03A616
03AF16, 03AE16
037F16, 037E16
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
Receive data
Receive data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turn out to be “0”.
Arbitration lost detecting
flag (Note 2)
0 : Not detected
1 : Detected
Invalid
ABT
Overrun error flag (Note 1)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
OER
FER
PER
SUM
Framing error flag (Note 1) Invalid
0 : No framing error
1 : Framing error found
Parity error flag (Note 1)
Error sum flag (Note 1)
Invalid
Invalid
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016
,
03A816 and 037816) are set to “000 ” or the receive enable bit is set to “0”.
2
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out.
Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is
assigned in bit 11 of U0RB and U1RB. These bits can neither be set or reset. When read, the value
of this bit is “0”.
UARTi bit rate generator
Symbol
U0BRG
U1BRG
U2BRG
Address
03A116
03A916
037916
When reset
Indeterminate
Indeterminate
Indeterminate
b7
b0
R W
Function
Values that can be set
0016 to FF16
Assuming that set value = n, BRGi divides the count source by
n + 1
Figure 1.14.4. Serial I/O-related registers (1)
90
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
R W
Bit name
(During UART mode)
b2 b1 b0
Must be fixed to 001
b2 b1 b0
SMD0
Serial I/O mode
select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
0 1 1 : Inhibited
1 1 1 : Inhibited
Internal/external
clock select bit
CKDIR
STPS
PRY
0 : Internal clock
1 : External clock (Note)
0 : Internal clock
1 : External clock (Note)
0 : One stop bit
1 : Two stop bits
Stop bit length
select bit
Invalid
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Odd/even parity
select bit
Parity enable bit
Sleep select bit
0 : Parity disabled
1 : Parity enabled
PRYE
SLEP
Invalid
0 : Sleep mode deselected
1 : Sleep mode selected
Must always be “0”
Note : Set the corresponding port direction register to “0”.
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
R W
Bit name
(During UART mode)
b2 b1 b0
SMD0
Clock synchronous serial
I/O mode can not be used
in UART2 (Note).
Serial I/O mode
select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
SMD1
SMD2
0 1 1 : Inhibited
1 1 1 : Inhibited
Internal/external
clock select bit
CKDIR
STPS
PRY
Must always be fixed to “0”
0 : One stop bit
1 : Two stop bits
Stop bit length
select bit
Odd/even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Parity enable bit
0 : Parity disabled
1 : Parity enabled
PRYE
0 : No reverse
1 : Reverse
TxD, RxD I/O
polarity reverse bit
IOPOL
Usually set to “0”
2
Note : Bit 2 to bit 0 are set to “010
2
” when I C mode is used.
Figure 1.14.5. Serial I/O-related registers (2)
91
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0(i=0,1)
Address
03A416, 03AC16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
R W
Bit name
(During UART mode)
b1 b0
b1 b0
CLK0
BRG count source
select bit
0 0 : f
0 1 : f
1
8
is selected
is selected
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : Inhibited
1 0 : f32 is selected
1 1 : Inhibited
CLK1
CRS
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CTS/RTS function
select bit
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0 : Data present in transmit
TXEPT Transmit register
empty flag
register (during transmission)
1 : No data present in transmit
register (transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
CRD
NCH
CTS/RTS disable
bit
programmable I/O port)
programmable I/O port)
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
Data output
select bit
0 : Transmit data is output at falling
edge of transfer clock and receive
data is input at rising edge
Must always be “0”
CKPOL CLK polarity
select bit
1 : Transmit data is output at rising
edge of transfer clock and receive
data is input at falling edge
0 : LSB first
1 : MSB first
Transfer format
select bit
UFORM
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C0
Address
037C16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
R W
Bit name
symbol
b1 b0
b1 b0
CLK0
CLK1
BRG count source
select bit
0 0 : f
0 1 : f
1 0 : f32 is selected
1 1 : Inhibited
1
8
is selected
is selected
0 0 : f
0 1 : f
1 0 : f32 is selected
1 1 : Inhibited
1
8
is selected
is selected
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CRS
CTS/RTS function
select bit
0 : Data present in transmit
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register
empty flag
register (during transmission)
1 : No data present in transmit
register (transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
CTS/RTS disable
bit
(P7
3
functions
(P7
3 functions programmable
programmable I/O port)
I/O port)
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
0 : Transmit data is output at falling
edge of transfer clock and receive
data is input at rising edge
Must always be “0”
CKPOL CLK polarity
select bit
1 : Transmit data is output at rising
edge of transfer clock and receive
data is input at falling edge
Transfer format
UFORM
0 : LSB first
1 : MSB first
0 : LSB first
1 : MSB first
select bit (Note 3)
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Note 4: The setting value of these bits are invalid since CLK2 and CTS2/RTS2 do not have external pin in
M16C/62 (80-pin version) group.
Note 5: UART2 clock synchronous serial I/O mode cannot be used in M16C/62 (80-pin version) group.
Figure 1.14.6. Serial I/O-related registers (3)
92
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1(i=0,1)
Address
03A516 03AD16
When reset
0216
,
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
R W
Bit name
(During UART mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C1
Address
037D16
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
Bit name
symbol
R W
TE
TI
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
U2IRS UART2 transmit interrupt 0 : Transmit buffer empty
0 : Transmit buffer empty
(TI = 1)
cause select bit
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
1 : Transmit is completed
(TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
U2ERE Error signal output
enable bit
Must be fixed to “0”
0 : Output disabled
1 : Output enabled
Note: UART2 clock synchronous serial I/O mode cannot be used in M16C/62 (80-pin version) group.
Figure 1.14.7. Serial I/O-related registers (4)
93
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
When reset
X0000000
2
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit
name
R W
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0IRS UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS UART1 transmit
interrupt cause select bit
U0RRM UART0 continuous
0 : Continuous receive
mode disabled
Invalid
receive mode enable bit
1 : Continuous receive
mode enable
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
CLKMD0 CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1 CLK/CLKS select
bit 1 (Note)
0 : Normal mode
Must always be “0”
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Separate CTS/RTS bit
RCSP
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
037716
When reset
0016
0
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit
name
R W
IIC mode selection bit
0 : Normal mode
1 : IIC mode
Must always be “0”
Must always be “0”
IICM
ABC
Arbitration lost detecting 0 : Update per bit
flag control bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected
BBS
Bus busy flag
Must always be “0”
Must always be “0”
(Note)
LSYN SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Bus collision detect
sampling
clock select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ABSCS
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
ACSE
Auto clear function
select bit of transmit
enable bit
Must always be “0”
0 : Ordinary
1 : Falling edge of RxD2
Must always be “0”
Always set to “0”
Transmit start condition
select bit
SSS
Reserved bit
Note 1: Nothing but "0" may be written.
Note 2: UART2 clock synchronous serial I/O mode cannot be used in M16C/62 (80-pin version) group.
Figure 1.14.8. Serial I/O-related registers (5)
94
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.14.2
and 1.14.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.14.9 shows the
UARTi transmit/receive mode register. Clock synchronous serial I/O mode cannot be used in UART2.
Table 1.14.2. Specifications of clock synchronous serial I/O mode (1)
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”)
: fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816 = “1”)
: Input from CLKi pin
_______
_______
_______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
_______
_______
_
When CTS function selected, CTS input level = “L”
Furthermore, if external clock is selected, the following requirements must also be met:
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “0”
: CLKi input level = “H”
•
_
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “1”
: CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_
Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “0”
: CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “1”
: CLKi input level = “L”
• When transmitting
Interrupt request
generation timing
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016) = “0”
: Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016) = “1”
: Interrupts requested when data transmission from UARTi transfer register
is completed
• When receiving
_
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 2)
Error detection
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
95
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
Table 1.14.4. Specifications of clock synchronous serial I/O mode (2)
Item
Specification
Select function
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) (Note)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
_______ _______
• Separate CTS/RTS pins (UART0) (Note)
_______
_______
UART0 CTS and RTS pins each can be assigned to separate pins
_______ _______
Note 1: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
selected simultaneously.
Note 2: Clock synchronous serial I/O mode cannot be used in UART2.
96
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
0
0 0 1
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note)
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
0 (Must always be “0” in clock synchronous serial I/O mode)
Note : Set the corresponding port direction register to “0”.
Figure 1.14.9. UARTi transmit/receive mode register in clock synchronous serial I/O mode
97
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
Table 1.14.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
_______
table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/
_______
RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is
selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-channel open-drain is selected, this
pin is in floating state.)
Table 1.14.4. Input/output pin functions in clock synchronous serial I/O mode
Pin name
TxDi
(P6 , P6
RxDi
(P6 , P6
Function
Method of selection
Serial data output
(Outputs dummy data when performing reception only)
3
7)
Serial data input
Port P6
2 and P66 direction register (bits 2 and 6 at address 03EE16)= “0”
(Can be used as an input port when performing transmission only)
2
6
)
)
CLKi
(P6 , P6
Transfer clock output Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “0”
1
5
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1”
Transfer clock input
Port P61 and P65 direction register (bits 1 and 5 at address 03EE16) = “0”
CTSi/RTSi
(P6 , P6
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) =“0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “0”
CTS input
0
4)
Port P60 and P64 direction register (bits 0 and 4 at address 03EE16) = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “1”
Programmable I/O
port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “1”
_______ _______
(when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected)
Note: Clock synchronous serial I/O mode cannot be used in UART2.
98
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
“0”
“1”
“0”
“H”
Data is set in UARTi transmit buffer register
bit (TE)
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
CTSi
CLKi
TCLK
“L”
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
TxDi
D0
D
1
D2
D3
D4
D5
D6
D7
D0
D
1
D2
D3
D4
D5
D
6
D7
D
0
D1
D2
D
3
D
4
D
5
D6
D7
Transmit
register empty
flag (TXEPT)
“1”
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = TCLK = 2(n + 1) / fi
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
fi: frequency of BRGi count source (f
n: value set to BRGi
1, f8, f32)
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
“1”
Transmit enable
bit (TE)
“0”
“1”
“0”
“H”
Dummy data is set in UARTi transmit buffer register
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
RTSi
CLKi
RxDi
“L”
1 / fEXT
Receive data is taken in
D
0
D1
D
2
D3
D
4
D5
D6
D0
D
1
D
2
D4
D5
D
7
D3
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
“1”
“0”
Receive complete
flag (Rl)
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
fEXT: frequency of external clock
Figure 1.14.10. Typical transmit/receive timings in clock synchronous serial I/O mode
99
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(a) Polarity select function
As shown in Figure 1.14.11, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16) allows
selection of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLK
i
Note 1: The CLK pin level when not
transferring data is “H”.
D0
D
1
D
2
D
3
3
D
4
D
5
5
D
6
6
D
7
7
TXDi
D
0
D
1
D
2
D
D4
D
D
D
RXDi
• When CLK polarity select bit = “1”
CLK
i
Note 2: The CLK pin level when not
transferring data is “L”.
D
0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
0
D
1
D
2
D
3
D
D
5
D
6
D7
RXDi
Figure 1.14.11. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.14.12, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16) =
“0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLK
i
D0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
LSB first
D
1
D
2
D
3
D
D
5
D
6
D7
D0
RXDi
• When transfer format select bit = “1”
CLK
i
D
7
7
D
6
D
5
D
4
D
3
3
D
2
D
1
D0
TXDi
MSB first
D
6
D
5
D
4
D
D
2
D
1
D0
D
RXDi
Note: This applies when the CLK polarity select bit = “0”.
Figure 1.14.12. Transfer format
100
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.14.3.)
The multiple pins function is valid only when the internal clock is selected for UART1. Note that when
_______ _______
this function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
T
X
D1
(P67)
CLKS
1
1
(P6
4
)
)
CLK
(P65
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 1.14.13. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is
set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register
is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to
the transmit buffer register back again.
_______ _______
(e) Separate CTS/RTS pins function (UART0)
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method
of setting and the input/output pin functions are both the same, so refer to select function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the
transfer clock output from the multiple pins function is selected.
101
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.14.5 and 1.14.6 list the specifications of the UART mode. Figure 1.14.15 shows
the UARTi transmit/receive mode register.
Table 1.14.5. Specifications of UART Mode (1)
Item
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
Transfer data format
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock
•
When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”)
: fi/16(n+1) (Note 1) fi = f1, f8, f32
•
:
When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”)
fEXT/16(n+1)(Note 1,2,4)
_______
_______
_______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid (Note 5)
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
-
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
_______ _______
- When CTS function selected, CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
- Start bit detection
Interrupt request
generation timing
• When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
Note 4: Since_C___L__K__2_ does not have external port, external clock cannot be selected as UART2 transfer clock.
________
_______ _______
Note 5: Since CTS
2
/RTS
2
does not have external port, select CTS/RTS function inhavit (bit 4 at 037C16 = “1”).
102
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Table 1.14.6. Specifications of UART Mode (2)
Item
Specification
_______ _______
Select function
• Separate CTS/RTS pins (UART0)
_______ _______
UART0 CTS and RTS pins each can be assigned to separate pins
• Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave micro-
computers
• Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
• TxD, RxD I/O polarity switch (UART2)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
103
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
CKDIR
STPS
PRY
Internal / external clock
select bit
0 : Internal clock
1 : External clock (Note)
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
SLEP
Parity enable bit
Sleep select bit
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Note : Set the corresponding port direction register to “0”.
UART2 transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
When reset
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
CKDIR
STPS
PRY
Internal / external clock
select bit
Must always be fixed to “0”.
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
0 : No reverse
1 : Reverse
Note: Usually set to “0”.
Figure 1.14.15. UARTi transmit/receive mode register in UART mode
104
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Table 1.14.7 lists the functions of the input/output pins during UART mode. This table shows the pin
_______ _______
functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the
UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-channel
open-drain is selected, this pin is in floating state.)
Table 1.14.7. Input/output pin functions in UART mode
Pin name
TxDi
(P6 , P6
RxDi
(P6 , P6
Function
Method of selection
Serial data
output
3
7
, P7
0
)
Serial data
input
Port P6
2, P6
6
and P7
1
direction register (bits 2 and 6 at address 03EE16,
bit 1 at address 03EF16)= “0”
(Can be used as an input port when performing transmission only)
2
6
, P7
)
1)
CLKi
(P6 , P6
Programmable
I/O port
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “0”
1
5
Transfer clock
input
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1”
Port P61 and P65 direction register (bits 1 and 5 at address 03EE16) = “0”
CTSi/RTSi
(P6 , P6
CTS input
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) =“0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “0”
0
4)
Port P60 and P64 direction register (bits 0 and 4 at address 03EE16) = “0”
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “1”
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “1”
Programmable
I/O port
________ _______
(when separate CTS/RTS pins function is not selected)
Note 1: Since CLK2(P72) does not have external port, use internal as UART2 transfer clock.
_______ _______
Note 2: Since CTS2/RTS2(P73) does not have external port, select CTS/RTS function inhavit (bit 4 at address
037C16 = “1”).
105
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
“0”
“1”
“0”
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag(TI)
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
“L”
CTSi
Stopped pulsing because transmit enable bit = “0”
Start
bit
Parity Stop
bit bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
D6
SP
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f
The above timing applies to the following settings :
• Parity is enabled.
1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
• One stop bit.
n : value set to BRGi
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
Note: CTS2 does not have external port so that this porrt function cannot be used.
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
Data is set in UARTi transmit buffer register
“0”
“1”
Transmit buffer
empty flag(TI)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop Stop
Start
bit
bit
bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
D8
ST
D0
D1
D2
D3
D4
D5
D7
D8
SPSP
D6
SP SP
D6
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f
1, f8, f32)
• Two stop bits.
fEXT : frequency of BRGi count source (external clock)
• CTS function is disabled.
n : value set to BRGi
• Transmit interrupt cause select bit = “0”.
Figure 1.14.16. Typical transmit timings in UART mode(UART0, UART1)
106
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
Data is set in UART2 transmit buffer register
“0”
“1”
Note
Transmit buffer
empty flag(TI)
“0”
Transferred from UART2 transmit buffer register to UARTi transmit register
Stop
Parity
bit
Start
bit
bit
TxD
2
ST
D0
D1
D2
D3
D4
D5
D7
P
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
SP
D6
SP
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
fi : frequency of BRG2 count source (f
n : value set to BRG2
1, f8, f32)
• Transmit interrupt cause select bit = “1”.
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Figure 1.14.17. Typical transmit timings in UART mode(UART2)
107
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
“1”
Receive enable bit
“0”
Stop bit
Start bit
D1
D7
RxDi
D0
Sampled “L”
Receive data taken in
Transfer clock
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Receive
complete flag
“0”
“H”
“L”
RTSi
Receive interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Note: RTS in UART2 is not connected to the outside.
Figure 1.14.18. Typical receive timing in UART mode
_______ _______
(a) Separate CTS/RTS pins function (UART0)
_______ _______
_______
Setting the CTS/RTS separate bit (bit 6 of address 03B016) to “1” inputs/outputs the CTS signal and
_______
_______
_______
_______ _______
RTS signal from different pins. Choose which to use, CTS or RTS, by use of the CTS/RTS function
select bit (bit 2 of address 03A416). This function is effective in UART0 only. With this function cho-
_______ _______
_______ _______
sen, the user cannot use the CTS/RTS function. Set "0" both to the CTS/RTS function select bit (bit
_______ _______
2 of address 03AC16) and to the CTS/RTS disable bit (bit 4 of address 03AC16).
Microcomputer
IC
TXD
0
(P6
3)
IN
R
X
D0
(P6
2)
OUT
RTS0 (P6
0
)
CTS
RTS
CTS0 (P6
4
)
Note : The user cannot use CTS and RTS at the same time.
_______ _______
Figure 1.14.19. The separate CTS/RTS pins function usage
(b) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
108
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(c) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 1.14.20 shows the ex-
ample of timing for switching serial data logic.
• When LSB first, parity enabled, one stop bit
“H”
Transfer clock
“L”
“H”
TxD
2
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(no reverse)
“L”
“H”
“L”
TxD
2
(reverse)
ST : Start bit
P : Even parity
SP : Stop bit
Figure 1.14.20. Timing for switching serial data logic
(d) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
(e) Bus collision detection function (UART2)
This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.14.21
shows the example of detection timing of a buss collision (in UART mode).
“H”
Transfer clock
“L”
“H”
TxD
2
2
ST
ST
SP
SP
“L”
“H”
“L”
RxD
Bus collision detection
interrupt request signal
“1”
“0”
Bus collision detection
interrupt request bit
“1”
“0”
ST : Start bit
SP : Stop bit
Figure 1.14.21. Detection timing of a bus collision (in UART mode)
109
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(3) Clock-asynchronous serial I/O mode (used for the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some
extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table
1.14.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface).
Table 1.14.8. Specifications of clock-asynchronous serial I/O mode (used for the SIM interface)
Item
Specification
Transfer data format
• Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”)
• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen
Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D16 = “0”).
Set transfer format to LSB (bit 7 of address 037C16 = “0”).
• With the inverse format chosen
Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D16 = “1”)
Set transfer format to MSB (bit 7 of address 037C16 = “1”)
• With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1)
(Note 1) : fi=f1, f8, f32
Transfer clock
_______
_______
Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)
Other settings • The sleep mode select function is not available for UART2
•
Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”)
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 037D16) = “1”
- Transmit buffer empty flag (bit 1 of address 037D16) = “0”
Reception start condition
• To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 037D16) = “1”
- Detection of a start bit
Interrupt request
generation timing
• When transmitting
When data transmission from the UART2 transfer register is completed
(bit 4 of address 037D16 = “1”)
• When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
Error detection
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TxD2 pin by use of the parity error
signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RxD2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
110
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
“0”
“1”
Note 2
Data is set in UART2 transmit buffer register
Transmit buffer
empty flag(TI)
“0”
Transferred from UART2 transmit buffer register to UART2 transmit register
Start
bit
Parity
bit
Stop
bit
TxD
2
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
P
D
6
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
D
6
SP
SP
SP
RxD
2
A “L” level returns from TxD
the occurrence of a parity error.
2 due to
Signal conductor level
(Note 1)
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
The level is
D
6
SP
ST
D0
D1
D2
D3
D4
D5
D7
D6
detected by the
interrupt routine.
The level is detected by the
interrupt routine.
“1”
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
fi : frequency of BRG2 count source (f
n : value set to BRG2
1, f8, f32)
• Transmit interrupt cause select bit = “1”.
Note 1: Equal in waveform because TxD2 and RxD2 are connected.
Note 2: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Tc
Transfer clock
“1”
Receive enable
bit (RE)
“0”
Parity
bit
Stop
bit
Start
bit
SP
RxD
2
ST
D
0
D
1
D
2
D
D
3
D
4
D
D
5
D
7
P
ST
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
P
D
6
SP
D6
TxD2
A “L” level returns from TxD
the occurrence of a parity error.
2 due to
Signal conductor level
(Note )
SP
ST
D
0
D
1
D2
3
D4
5
D7
P
D
0
D
1
D
2
D
3
D
4
D
5
D7
D6
SP
D6
“1”
Receive complete
flag (RI)
“0”
Read to receive buffer
Read to receive buffer
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
n : value set to BRG2
1, f8, f32)
• Transmit interrupt cause select bit = “0”.
Note: Equal in waveform because TxD2 and RxD2 are connected.
Figure 1.14.22. Typical transmit/receive timing in UART mode (used for the SIM interface)
111
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(a) Function for outputting a parity error signal
With the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you can output an “L”
level from the TxD2 pin when a parity error is detected. In step with this function, the generation timing
of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure
1.14.23 shows the output timing of the parity error signal.
• LSB first
“H”
Transfer
“L”
clock
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RxD2
TxD2
“L”
“H”
“L”
Hi-Z
“1”
“0”
Receive
complete flag
ST : Start bit
P : Even Parity
SP : Stop bit
Figure 1.14.23. Output timing of the parity error signal
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted
and output from TxD2.
Figure 1.14.24 shows the SIM interface format.
Transfer
clcck
TxD2
(direct)
D0
D7
D1
D6
D2
D5
D3
D4
D4
D3
D5
D2
D6
D1
D7
D0
P
P
TxD2
(inverse)
P : Even parity
Figure 1.14.24. SIM interface format
112
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Figure 1.14.25 shows the example of connecting the SIM interface. Connect TxD2 and RxD2 and apply
pull-up.
Microcomputer
SIM card
TxD
2
2
RxD
Figure 1.14.25. Connecting the SIM interface
113
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
UART2 Special Mode Register
The UART2 special mode register (address 037716) is used to control UART2 in various ways.
Figure 1.14.26 shows the UART2 special mode register.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
037716
When reset
0016
0
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
2
I C mode selection bit
0 : Normal mode
1 : I C mode
IICM
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
2
ABC
BBS
Arbitration lost detecting 0 : Update per bit
flag control bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected
Bus busy flag
(Note1)
LSYN
SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Bus collision detect
sampling clock select bit
0 : Rising edge of transfer
clock
Must always be “0”
ABSCS
1 : Underflow signal of timer A0
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
ACSE
SSS
Auto clear function
select bit of transmit
enable bit
Must always be “0”
Transmit start condition
select bit
0 : Ordinary
1 : Falling edge of RxD2
Must always be “0”
Always set to “0”
Reserved bit
Note 1: Nothing but “0” may be written.
Note 2: UART2 clock synchronous serial I/O mode cannot be used in M16C/62 (80-pin version) group.
Figure 1.14.26. UART2 special mode register
2
Table 1.14.8. Features in I C mode
2
Function
Normal mode
I C mode (Note 1)
Start condition detection or stop
condition detection
Bus collision detection
1
Factor of interrupt number 10 (Note 2)
2
3
4
5
6
7
Factor of interrupt number 15 (Note 2)
Factor of interrupt number 16 (Note 2)
UART2 transmission output delay
UART2 transmission
UART2 reception
Not delayed
No acknowledgment detection (NACK)
Acknowledgment detection (ACK)
Delayed
P7
0
1
at the time when UART2 is in use
at the time when UART2 is in use
at the time when UART2 is in use
TxD
2
(output)
(input)
SDA (input/output) (Note 3)
SCL (input/output)
P7
RxD
2
2
P72
CLK
P72
DMA1 factor at the time when 1 1 0 1 is assigned
to the DMA request factor selection bits
8
9
UART2 reception
15ns
Acknowledgment detection (ACK)
Noise filter width
50ns
Reading the terminal when 0 is
assigned to the direction register
Reading the terminal regardless of the
value of the direction register
10 Reading P7
1
H level (when 0 is assigned to
the CLK polarity select bit)
The value set in latch P7
selected
0 when the port is
11 Initial value of UART2 output
2
Note 1: Make the settings given below when I C mode is in use.
Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.
Note 2: Follow the steps given below to switch from a factor to another.
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
114
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
2
2
In the first place, the control bits related to the I C bus(simplified I C bus) interface are explained.
2
Bit 0 of the UART special mode register (037716) is used as the I C mode selection bit.
2
2
2
Setting “1” in the I C mode select bit (bit 0) goes the circuit to achieve the I C bus (simplified I C bus)
interface effective.
2
Table 1.14.9 shows the relation between the I C mode select bit and respective control workings.
Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.
2
P70
through P7
2
conforming to the simplified I C bus
P70/TxD2/SDA
To DMA0, DMA1
To DMA0
Timer
UART2 transmission/
NACK interrupt
request
Selector
IICM=1
I/O
IICM=0
IICM=1
Transmission
register
delay
UART2
IICM=0
UART2
D
Q
Arbitration
IICM=1
T
UART2 reception/ACK
interrupt request
DMA1 request
Noize
Filter
Timer
IICM=0
IICM=1
Reception register
UART2
IICM=0
Start condition detection
S
Q
R
Bus busy
Stop condition detection
L-synchronous
NACK
D
Q
Falling edge
detection
T
output enabling bit
D
Q
P71/RxD2/SCL
I/O
R
Q
ACK
T
Data bus
9th pulse
Bus collision/start, stop
condition detection
interrupt request
(Port P7
1
output data latch)
Internal clock
Selector
IICM=1
IICM=0
UART2
IICM=1
Bus collision
detection
CLK
IICM=1
Noize
Filter
External clock
Noize
Filter
UART2
Port reading
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7 of the direction register.
IICM=0
IICM=0
*
UART2
P72/CLK2
1
Selector
I/O
Timer
Note: P72/CLK2 is not connected to the outside.
2
Figure 1.14.27. Functional block diagram for I C mode
2
2
Figure 1.14.27 shows the functional block diagram for I C mode. Setting “1” in the I C mode selection bit
(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock input-
output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output,
so the SDA output changes after SCL fully goes to “L”. An attempt to read Port P71 (SCL) results in
getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA
transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision
detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop
condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection
interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt
refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL
terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the
start condition detection, and set to “0” by the stop condition detection.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal
level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment
detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already went
to “L” at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor
select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection.
Bit 1 of the UART2 special mode register (037716) is used as the arbitration loss detecting flag control bit.
Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal
data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the UART2 reception
buffer register (037F16), and “1” is set in this flag when nonconformity is detected. Use the arbitration lost
detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When
setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the arbitration lost
detecting flag is set to “1” at the falling edge of the 9th transmission clock.
If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after complet-
ing the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting
this bit to “1” goes the P71 data register to “0” in synchronization with the SCL terminal level going to “L”.
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
Some other functions added are explained here. Figure 1.14.28 shows their workings.
Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The
bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconfor-
mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If
this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at
the rising edge of the transfer clock.
Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable
bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus
collision detect interrupt request bit (nonconformity).
Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit
to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
0: Rising edges of the transfer clock
CLK
TxD/RxD
1: Timer A0 overflow
Timer A0
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
CLK
TxD/RxD
Bus collision
detect interrupt
request bit
Transmit
enable bit
3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)
0: In normal state
CLK
TxD
Enabling transmission
With "1: falling edge of RxD2" selected
CLK
TxD
RxD
Figure 1.14.28. Some other functions added
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
UART2 Special Mode Register 2
UART2 special mode register 2 (address 037616) is used to further control UART2 in I C mode, but is not
exsist in M30623EC. Figure 1.14.29 shows the UART2 special mode register 2.
2
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
037616
When reset
0016
Bit
symbol
Bit name
R W
Function
2
I C mode selection bit 2 Refer to Table 1.14.10
IICM2
CSC
Clock-synchronous bit
SCL wait output bit
0 : Disabled
1 : Enabled
SWC
0 : Disabled
1 : Enabled
ASL
SDA output stop bit
0 : Disabled
1 : Enabled
UART2 initialization bit
0 : Disabled
1 : Enabled
STAC
SWC2
SCL wait output bit 2
SDA output disable bit
0: UART2 clock
1: 0 output
0: Enabled
1: Disabled (high impedance)
SDHI
SHTC
Start/stop condition
control bit
Set this bit to “1” in I2C mode
(refer to Table 1.14.11)
Figure 1.14.29. UART2 special mode register 2
118
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
2
Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I C mode selection bit 2.
2
2
Table 1.14.10 shows the types of control to be changed by I C mode selection bit 2 when the I C mode
selection bit is set to "1". Table 1.14.11 shows the timing characteristics of detecting the start condition
and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to
2
"1" in I C mode.
2
Table 1.14.10. Functions changed by I C mode selection bit 2
IICM2 = 1
Function
IICM2 = 0
1
2
3
UART2 transmission (the rising edge
of the final bit of the clock)
Factor of interrupt number 15
No acknowledgment detection (NACK)
Factor of interrupt number 16
Acknowledgment detection (ACK)
UART2 reception (the falling edge
of the final bit of the clock)
DMA1 factor at the time when 1 1 0 1 Acknowledgment detection (ACK)
is assigned to the DMA request
factor selection bits
UART2 reception (the falling edge of
the final bit of the clock)
The rising edge of the final bit of the
Timing for transferring data from the
UART2 reception shift register to the
reception buffer.
4
5
The falling edge of the final bit of the
reception clock
reception clock
Timing for generating a UART2
reception/ACK interrupt request
The rising edge of the final bit of the
reception clock
The falling edge of the final bit of the
reception clock
Table 1.14.11. Timing characteristics of detecting the start condition and the stop condition
3 to 6 cycles < duration for setting-up (Note2)
3 to 6 cycles < duration for holding (Note2)
Note 1 : When the start/stop condition count bit is "1" .
Note 2 : "cycles" is in terms of the input oscillation frequency f(XIN) of the main clock.
Duration for
setting up
Duration for
holding
SCL
SDA
(Start condition)
SDA
(Stop condition)
119
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
P70/TXD2/SDA
Timer
I/0
To DMA0, DMA1
Selector
IICM=0
or
IICM2=1
UART2 transmission/
NACK interrupt
request
UART2
IICM=1
Transmission register
UART2
delay
IICM=1
and IICM2=0
IICM=0
SDHI
ALS
Arbitration
IICM=1
To DMA0
D
Q
T
Noize
Filter
IICM=0
or IICM2=1
UART2 reception/ACK interrupt request
DMA1 request
Reception register
UART2
IICM=0
IICM=1
and IICM2=0
Start condition detection
S
R
Bus
Q
busy
Stop condition detection
L-synchronous
NACK
D
Q
Falling edge
detection
T
T
output enabling bit
D
P71/RXD2/SCL
Q
I/0
R
ACK
Data register
9th pulse
Selector
Bus collision/start, stop condition detection
interrupt request
IICM=1
Internal clock
UART2
IICM=1
Bus collision
detection
UART2
SWC2
CLK
control
IICM=0
IICM=1
Noize
Filter
External clock
Noize
Filter
Falling of 9th pulse
SWC
IICM=0
R
S
Port reading
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7 of the direction register.
UART2
IICM=0
*
1
P72/CLK2
Selector
I/0
Timer
Note: P72/CLK2 is not connected to the outside.
2
Figure 1.14.30. Functional block diagram for I C mode
2
Functions available in I C mode are shown in Figure 1.14.30 — a functional block diagram.
Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting
this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state the
instant when the arbitration loss detection flag is set to "1".
Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit.
With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the
falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting
within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops
counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this
function, the UART2 transmission-reception clock becomes the logical product of the signal flowing
through the internal SCL and that flowing through the SCL pin. This function operates over the period
from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the
ninth bit. To use this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to
"1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to
"0" frees the output fixed to "L".
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit.
Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows.
(1) The transmission shift register is initialized, and the content of the transmission register is transferred
to the transmission shift register. This starts transmission by dealing with the clock entered next as the
first bit. The UART2 output value, however, doesn’t change until the first bit data is output after the
entrance of the clock, and remains unchanged from the value at the moment when the microcomputer
detected the start condition.
(2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the
clock entered next as the first bit.
(3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit of
the clock.
Starting to transmit/receive signals to/from UART2 using this function doesn’t change the value of the
transmission buffer empty flag. To use this function, choose the external clock for the transfer clock.
Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL pin wait output bit 2. Setting this
bit to "1" with the serial I/O specified allows the user to forcibly output an "L" from the SCL pin even if
UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2 clock
is input/output.
Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output disable bit. Setting this bit
to "1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit
at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detection
flag is turned on.
121
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3, 4
S I/O3, 4
S I/O3 and S I/O4 are exclusive clock-synchronous serial I/Os.
Figure 1.14.31 shows the S I/O3, 4 block diagram, and Figure 1.14.32 shows the S I/O3, 4 control register.
Table 1.14.12 shows the specifications of S I/O3, 4.
Data bus
f
1
8
SMi1
SMi0
f
f32
Synchronous
circuit
1/2
1/(ni+1)
SMi3
SMi6
Transfer rate register (8)
S I/O counter i (3)
SMi6
P90/CLK
3
S I/Oi
(P95/CLK
4)
interrupt request
SMi2
SMi3
SMi5 LSB
MSB
P92/
(P96/
SOUT3
SOUT4
)
P91/
S
IN4)
IN3
S I/Oi transmission/reception register (8)
8
(P97/S
Note 1: i = 3, 4.
ni = A value set in the S I/O transfer rate register i (036316, 036716).
Note 2: P9 /SIN3 is not connected to outside.
1
Figure 1.14.31. S I/O3, 4 block diagram
122
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3, 4
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SiC
Address
036216, 036616
When reset
4016
Bit
symbol
Description
Bit name
R W
b1 b0
SMi0 Internal synchronous
clock select bit
0 0 : Selecting f
1
8
0 1 : Selecting f
SMi1
1 0 : Selecting f32
1 1 : Not to be used
SMi2
SMi3
S
OUTi output disable bit
0 : SOUTi output
1 : SOUTi output disable(high impedance)
S I/Oi port select bit
(Note 2)
0 : Input-output port
1 : SOUTi output, CLK function
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
SMi5 Transfer direction select
bit
0 : LSB first
1 : MSB first
SMi6
Synchronous clock
select bit (Note 2)
0 : External clock
1 : Internal clock
SMi7
S
set bit
OUTi initial value
Effective when SMi3 = 0
0 : L output
1 : H output
Note 1: Set "1" in bit 2 of the protection register (000A16) in advance to write to the
S I/Oi control register (i = 3, 4).
Note 2: When using the port as an input/output port by setting the SI/Oi port
select bit (i = 3, 4) to "0", be sure to set the sync clock select bit to "1"
.
SI/Oi bit rate generator
Symbol
S3BRG
S4BRG
Address
036316
036716
When reset
Indeterminate
Indeterminate
b7
b0
Values that can be set
R W
Indeterminate
Assuming that set value = n, BRGi divides the count
source by n + 1
0016 to FF16
SI/Oi transmit/receive register
Symbol
S3TRR
S4TRR
Address
036016
036416
When reset
Indeterminate
Indeterminate
b7
b0
R W
Indeterminate
Transmission/reception starts by writing data to this register.
After transmission/reception finishes, reception data is input.
Note: SI/O3 is exclusive to transmission.
Figure 1.14.32. S I/O3, 4 related register
123
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3, 4
Table 1.14.12. Specifications of S I/O3, 4
Item
Specifications
Transfer data format • Transfer data length: 8 bits
Transfer clock
• With the internal clock selected (bit 6 of 036216, 036616 = “1”): f1/2(ni+1),
f8/2(ni+1), f32/2(ni+1) (Note 1)
•
With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi terminal (Note 2)
Conditions for
transmission/
reception start
• To start transmit/reception, the following requirements must be met:
- Select the synchronous clock (use bit 6 of 036216, 036616).
Select a frequency dividing ratio if the internal clock has been selected (use bits
0 and 1 of 036216, 036616).
- SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1.
- S I/Oi port select bit (bit 3 of 036216, 036616) = 1.
- Select the transfer direction (use bit 5 of 036216, 036616)
-Write transfer data to SI/Oi transmit/receive register (036016, 036416)
• To use S I/Oi interrupts, the following requirements must be met:
- Clear the SI/Oi interrupt request bit before writing transfer data to the SI/Oi
transmit/receive register (bit 3 of 004916, 004816) = 0.
Interrupt request • Rising edge of the last transfer clock. (Note 3)
generation timing
Select function
• LSB first or MSB first selection
Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be
selected.
• Function for setting an SOUTi initial value selection
When using an external clock for the transfer clock, the user can choose the
SOUTi pin output level during a non-transfer time. For details on how to set, see
Figure 1.14.33.
Precaution
• Unlike UART0–2, SI/Oi (i = 3, 4) is not divided for transfer register and buffer.
Therefore, do not write the next transfer data to the SI/Oi transmit/receive register
(addresses 036016, 036416) during a transfer. When the internal clock is selected
for the transfer clock, SOUTi holds the last data for a 1/2 transfer clock period after
it finished transferring and then goes to a high-impedance state. However, if the
transfer data is written to the SI/Oi transmit/receive register (addresses 036016,
036416) during this time, SOUTi is placed in the high-impedance state immediately
upon writing and the data hold time is thereby reduced.
Note 1: n is a value from 0016 through FF16 set in the S I/Oi transfer rate register (i = 3, 4).
Note 2: With the external clock selected:
• Before data can be written to the SI/Oi transmit/receive register (addresses 036016, 036416), the
CLKi pin input must be in the high state. Also, before rewriting the SI/Oi Control Register (addresses
036216, 036616)’s bit 7 (SOUTi initial value set bit), make sure the CLKi pin input is held high.
• The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it,
so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected,
automatically stops.
Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the “H” state.
Note 4: SI/O3 is provided with no connection to the external pin, so is used exclusively for transmission.
124
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3, 4
Functions for setting an SOUTi initial value
When using an external clock for the transfer clock, the SOUTi pin output level during a non-transfer
time can be set to the high or the low state. Figure 1.14.33 shows the timing chart for setting an SOUTi
initial value and how to set it.
(Example) With “H” selected for SOUTi:
S I/Oi port select bit SMi3 = 0
Signal written to the S I/Oi
transmission/reception
register
SOUTi initial value select bit
SMi7 = 1
(SOUTi: Internal
“H” level)
S
OUTi's initial value
set bit (SMi7)
S I/Oi port select bit
SMi3 = 0 1
(Port select: Normal port
S I/Oi port select bit
(SMi3)
S
OUTi)
D0
D0
S
OUTi terminal = “H” output
S
OUTi (internal)
Signal written to the S I/Oi register
=“L” “H” “L”
(Falling edge)
Port output
S
OUTi terminal output
(i = 3, 4)
Initial value = “H” (Note)
Setting the SOUT
initial value to H
i
Port selection
(normal port
S
OUTi terminal = Outputting
S
OUTi)
stored data in the S I/Oi transmission/
reception register
Note: The set value is output only when the external clock has been selected. When
initializing SOUTi, make sure the CLKi pin input is held “H” level.
If the internal clock has been selected or if SOUT output disable has been set,
this output goes to the high-impedance state.
Figure 1.14.33. Timing chart for setting SOUTi’s initial value and how to set it
S I/Oi operation timing
Figure 1.14.34 shows the S I/Oi operation timing
1.5 cycle (max)
"H"
SI/Oi internal clock
"L"
"H"
"L"
Transfer clock
(Note 1)
"H"
"L"
Signal written to the
S I/Oi register
Note2
Hiz
Hiz
S I/Oi output
S
OUT
i
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
(i= 3, 4)
"H"
"L"
S I/Oi input
SINi
(i= 3, 4)
"1"
"0"
SI/Oi interrupt request
(i= 3, 4)
bit
Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control register.
(i=3,4) (No frequency division, 8-division frequency, 32-division frequency.)
Note 2: With the internal clock selected for the transfer clock, the SOUTi pin becomes to the high-impedance state after the transfer finishes.
Note 3: Shown above is the case where the SOUTi (i = 3, 4) port select bit ="1".
Figure 1.14.34. S I/Oi operation timing chart
125
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling
amplifier. Pins P10 to P10 , P9 , and P9 also function as the analog signal input pins. The direction registers of
0
7
5
6
these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be
used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D
converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power
dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF
.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low
8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low
8 bits are stored in the even addresses.
Table 1.15.1 shows the performance of the A-D converter. Figure 1.15.1 shows the block diagram of the
A-D converter, and Figures 1.15.2 and 1.15.3 show the A-D converter-related registers.
Table 1.15.1. Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock φAD (Note 2) VCC = 5V
fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V
• Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
AN0 to AN7 input : ±3LSB
ANEX0 and ANEX1 input (including mode in which external
operation amp is connected) : ±7LSB
• Without sample and hold function (8-bit resolution)
±2LSB
VCC = 3V
Operating modes
Analog input pins
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
___________
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 AD cycles 10-bit resolution: 59
• With sample and hold function
8-bit resolution: 28 AD cycles, 10-bit resolution: 33 φAD cycles
φ
,
φAD cycles
φ
Note 1: Does not depend on use of sample and hold function.
Note 2: Divide the frequency if f(XIN) exceeds 10MHz, and make
φAD frequency equal to 10MHz.
Without sample and hold function, set the
With the sample and hold function, set the
φ
AD frequency to 250kHz min.
φ
AD frequency to 1MHz min.
126
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
CKS1=1
CKS1=0
CKS0=1
CKS0=0
φ
AD
f
AD
1/2
1/2
A-D conversion rate
selection
V
REF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register
A-D control register 1 (address 03D716
)
)
A-D control register 0 (address 03D616
Addresses
(03C116, 03C016
(03C316, 03C216
(03C516, 03C416
)
)
)
A-D register 0(16)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
V
ref
(03C716, 03C616
(03C916, 03C816
(03CB16, 03CA16
(03CD16, 03CC16
(03CF16, 03CE16
)
Decoder
)
A-D register 4(16)
)
A-D register 5(16)
A-D register 6(16)
Comparator
V
IN
)
)
A-D register 7(16)
Data bus high-order
Data bus low-order
CH2,CH1,CH0=000
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
OPA1,OPA0=0,0
OPA1, OPA0
0
0
1
1
0 : Normal operation
1 : ANEX0
0 : ANEX1
1 : External op-amp mode
OPA1,OPA0=1,1
OPA0=1
OPA1=1
ANEX0
ANEX1
OPA1,OPA0=0,1
Figure 1.15.1. Block diagram of A-D converter
127
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note 1)
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
Bit name
Function
0 is selected
b2 b1 b0
CH0
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
b4 b3
Analog input pin select bit
1
is selected
is selected
is selected
is selected
is selected
is selected
is selected
2
3
4
5
6
7
CH1
CH2
MD0
MD1
(Note 2)
(Note 2)
A-D operation mode
select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
ADST
CKS0
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
Bit symbol
Bit name
Function
R W
When single sweep and repeat sweep
A-D sweep pin select bit
mode 0 are selected
b1 b0
SCAN0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
When repeat sweep mode 1 is selected
b1 b0
SCAN1
MD2
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN
1
(2 pins)
to AN
2
3
(3 pins)
(4 pins)
to AN
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
0 : Vref not connected
1 : Vref connected
VCUT
OPA0
OPA1
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 1.15.2. A-D converter-related registers (1)
128
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 2 (Note)
Symbol
ADCON2
Address
03D416
When reset
0000XXX0
b7 b6 b5 b4 b3 b2 b1 b0
2
0
0 0
Bit symbol
SMP
Bit name
Function
R W
0 : Without sample and hold
1 : With sample and hold
A-D conversion method
select bit
Always set to “0”
Reserved bit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
ADi(i=0 to 7)
Address
When reset
A-D register i
(b15)
b7
03C016 to 03CF16 Indeterminate
(b8)
b0 b7
b0
Function
R W
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.
Figure 1.15.3. A-D converter-related registers (2)
129
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. Table 1.15.2 shows the specifications of one-shot mode. Figure 1.15.4 shows the A-D control regis-
ter in one-shot mode.
Table 1.15.2. One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
•
End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN7, as selected
Read A-D register corresponding to selected pin
Reading of result of A-D converter
A-D control register 0 (Note 1)
Symbol
ADCON0
Address
03D616
When reset
b7 b6 b5 b4 b3 b2 b1 b0
00000XXX
2
0
0
Bit symbol
Bit name
Function
R W
b2 b1 b0
Analog input pin select
bit
CH0
CH1
CH2
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
(Note 2)
(Note 2)
b4 b3
MD0
MD1
A-D operation mode
select bit 0
0 0 : One-shot mode
0 : Software trigger
1 : ADTRG trigger
Trigger select bit
TRG
ADST
CKS0
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0: fAD/4 is selected
1: fAD/2 is selected
Frequency select bit 0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
R W
Invalid in one-shot mode
SCAN0
SCAN1
select bit
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
MD2
BITS
CKS1
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Frequency select bit1
Vref connect bit
1 : Vref connected
VCUT
OPA0
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 1.15.4. A-D conversion register in one-shot mode
130
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
Table 1.15.3 shows the specifications of repeat mode. Figure 1.15.5 shows the A-D control register in
repeat mode.
Table 1.15.3. Repeat mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Writing “1” to A-D conversion start flag
Star condition
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
One of AN0 to AN7, as selected
Read A-D register corresponding to selected pin
Reading of result of A-D converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
0
1
Bit symbol
Bit name
Function
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
R W
b2 b1 b0
Analog input pin
select bit
CH0
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
CH1
CH2
(Note 2)
(Note 2)
b4 b3
MD0
MD1
A-D operation mode
select bit 0
0 1 : Repeat mode
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
Frequency select bit 0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
R W
Invalid in repeat mode
SCAN0
SCAN1
select bit
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
Frequency select bit 1
Vref connect bit
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 1.15.5. A-D conversion register in repeat mode
131
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(3) Single sweep mode
I
n single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 1.15.4 shows the specifications of single sweep mode. Figure 1.15.6 shows the A-D
control register in single sweep mode.
Table 1.15.4. Single sweep mode specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Writing “1” to A-D converter start flag
Start condition
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX
0
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in single sweep mode
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 0 : Single sweep mode
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
Function
R W
A-D sweep pin select bit When single sweep and repeat sweep mode 0
SCAN0
SCAN1
are selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
BITS
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Figure 1.15.6. A-D conversion register in single sweep mode
132
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 1.15.5 shows the specifications of repeat sweep mode 0. Figure 1.15.7 shows the
A-D control register in repeat sweep mode 0.
Table 1.15.5. Repeat sweep mode 0 specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in repeat sweep mode 0
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 0
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
SCAN0
Bit name
Function
R W
A-D sweep pin select bit When single sweep and repeat sweep mode 0
are selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
SCAN1
(6 pins)
(8 pins)
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
BITS
CKS1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Frequency select bit 1
Vref connect bit
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither “01” nor “10” can be selected with the external op-amp connection mode bit.
Figure 1.15.7. A-D conversion register in repeat sweep mode 0
133
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 1.15.6 shows the specifications of repeat sweep mode 1. Figure
1.15.8 shows the A-D control register in repeat sweep mode 1.
Table 1.15.6. Repeat sweep mode 1 specifications
Item
Specification
Function
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0
AN1
AN0
AN2
AN0
AN3, etc
Start condition
Stop condition
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Read A-D register corresponding to selected pin (at any time)
Reading of result of A-D converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in repeat sweep mode 1
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Frequency select bit 0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
1
Bit symbol
SCAN0
Bit name
Function
R W
A-D sweep pin select bit When repeat sweep mode 1 is selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN (2 pins)
1
SCAN1
to AN
to AN
2
3
(3 pins)
(4 pins)
A-D operation mode
select bit 1
1 : Repeat sweep mode 1
MD2
BITS
CKS1
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Figure 1.15.8. A-D conversion register in repeat sweep mode 1
134
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 f AD cycle is
achieved with 8-bit resolution and 33 f AD with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and
hold is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is
converted from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is
converted from analog to digital. The result of conversion is stored in A-D register 1.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 is
output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the
corresponding A-D register. The speed of A-D conversion depends on the response of the external op-
eration amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.15.9 is an example of how to
connect the pins in external operation amp mode.
Resistor ladder
Successive conversion register
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
Analog
input
AN7
ANEX0
ANEX1
Comparator
External op-amp
Figure 1.15.9. Example of external op-amp connection mode
135
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of
this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the
target port to output mode if D-A conversion is to be performed.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 1.16.1 lists the performance of the D-A converter. Figure 1.16.1 shows the block diagram of the D-A
converter. Figure 1.16.2 shows the D-A control register. Figure J1.16.3 shows the D-A converter equiva-
lent circuit.
Table 1.16.1. Performance of D-A converter
Item
Conversion method
Resolution
Performance
R-2R method
8 bits
Analog output pin
2 channels
Data bus low-order bits
D-A register0 (8)
(Address 03D816
)
D-A0 output enable bit
P9 /DA
3
0
R-2R resistor ladder
D-A register1 (8)
(Address 03DA16
D-A1 output enable bit
P9 /DA
)
4
1
R-2R resistor ladder
Figure 1.16.1. Block diagram of D-A converter
136
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DACON
Address
03DC16
When reset
0016
Bit symbol
DA0E
Bit name
Function
R W
0 : Output disabled
1 : Output enabled
D-A0 output enable bit
D-A1 output enable bit
0 : Output disabled
1 : Output enabled
DA1E
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
D-A register
b7
Symbol
DAi (i = 0,1)
Address
03D816 03DA16
When reset
Indeterminate
b0
,
Function
R W
Output value of D-A conversion
Figure 1.16.2. D-A control register
D-A0 output enable bit
“0”
R
R
R
R
R
R
R
2R
DA0
“1”
2R
MSB
2R
2R
2R
2R
2R
2R
2R
LSB
D-A0 register0
“0”
“1”
AVSS
REF
V
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16
.
Note 2: The same circuit as this is also used for D-A1.
Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016
so that no current flows in the resistors Rs and 2Rs.
Figure 1.16.3. D-A converter equivalent circuit
137
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom-
16
12
5
puter uses a generator polynomial of CRC_CCITT (X + X + X + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com-
pleted in two machine cycles.
Figure 1.17.1 shows the block diagram of the CRC circuit. Figure 1.17.2 shows the CRC-related registers.
Figure 1.17.3 shows the calculation example using the CRC calculation circuit
Data bus high-order bits
Data bus low-order bits
Eight low-order bits
Eight high-order bits
CRC data register (16)
(Addresses 03BD16, 03BC16)
CRC code generating circuit
x
16 + x12 + x5 + 1
CRC input register (8) (Address 03BE16)
Figure 1.17.1. Block diagram of CRC circuit
CRC data register
(b15)
b7
(b8)
b0 b7
Symbol
CRCD
Address
03BD16, 03BC16
When reset
Indeterminate
b0
Values that
can be set
Function
R W
CRC calculation result output register
000016 to FFFF16
CRC input register
b7
b0
Symbo
CRCIN
Address
03BE16
When reset
Indeterminate
Values that
can be set
Function
R W
Data input register
0016 to FF16
Figure 1.17.2. CRC-related registers
138
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC
b15
b0
b0
CRC data register CRCD
[03BD16, 03BC16
(1) Setting 000016
(2) Setting 0116
]
b7
CRC input register
2 cycles
CRCIN
[03BE16
]
After CRC calculation is complete
b15
b0
CRC data register
Stores CRC code
CRCD
[03BD16, 03BC16
118916
]
The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
16
12
5
16
(X + X + X + 1), becomes the remainder resulting from dividing (1000 0000) X by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
LSB
MSB
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001
1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
LSB
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
MSB
9
8
1
1
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
CRC input register
CRCIN
[03BE16
(3) Setting 2316
]
After CRC calculation is complete
b15
b0
CRC data register
Stores CRC code
CRCD
[03BD16, 03BC16
0A4116
]
Figure 1.17.3. Calculation example using the CRC calculation circuit
139
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Programmable I/O Ports
The M16C/62 (80-pin version) group has 70 programmable input/output ports given below (except P85).
• P00-P07
• P20–P27
• P30–P37
• P40–P43
• P50–P57
• P60–P67
• P70, P71, P76, P77
• P80–P84, P86, P87 (P85 is input port)
• P90, P92–P97
• P100–P107
Note: P1, P44 to P47, P72 to P75, P91 are not connected to external pins.
Figures 1.18.1 to 1.18.4 show the programmable I/O ports. Figure 1.18.5 shows the I/O pins.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), they function as outputs regardless of the contents of the direction registers. When pins are to be
used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.18.6 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
Note: There is no direction register bit for P85.
(2) Port registers
Figure 1.18.7 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.18.8 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
140
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P0
P3
P5
0
0
0
to P0
to P3
to P5
7, P2
7, P4
4, P5
0
0
6
to P2
to P4
7
7
,
,
Data bus
Port latch
(Note 1)
Pull-up selection
Direction register
P10 to P14
Port P1 control register
Data bus
Port latch
(Note 1)
Pull-up selection
Direction register
P15 to P17
Port P1 control register
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction register
P5
P7
P9
7
2
0
, P6
to P7
, P9
0
, P6
1
, P6
4, P65,
"1"
6
, P8
0, P81,
2
Output
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Note 2: P1, P4 to P4 , P7 to P7 , P9 are not connected to external pins, but are present within the
microcomputer.
4
7
2
5
1
Figure 1.18.1. Programmable I/O ports (1)
141
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P8
2
to P8
4
Data bus
Port latch
(Note1)
Input to respective peripheral functions
Pull-up selection
Direction register
P5
P8
5
1
, P6
, P9
2
1
, P6
, P9
6
7
, P77,
Data bus
Port latch
(Note1)
Input to respective peripheral functions
Pull-up selection
Direction register
P6
3
, P6
7
"1"
Output
Data bus
Port latch
(Note1)
P8
5
Data bus
(Note1)
NMI interrupt input
Direction register
P70, P71
"1"
Output
Port latch
(Note2)
Input to respective peripheral functions
Note 1:
Note 2:
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
symbolizes a parasitic diode.
Note 3: P1, P4
4 to P47, P72 to P75, P91 are not connected to external pins, but are present
within the microcomputer.
Figure 1.18.2. Programmable I/O ports (2)
142
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P10
(inside dotted-line not included)
P10 to P10
(inside dotted-line included)
0 to P103
4
7
Data bus
Port latch
(Note 1)
Analog input
Input to respective peripheral functions
Pull-up selection
D-A output enabled
Direction register
P93, P94
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Analog output
D-A output enabled
Pull-up selection
Direction register
"1"
P96
Output
Port latch
Data bus
(Note 1)
Analog input
Pull-up selection
Direction register
"1"
P95
Output
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Analog input
Note 1:
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Note 2: P1, P4 to P4 , P7 to P7 , P9 are not connected to external pins, but are
present within the microcomputer.
4
7
2
5
1
Figure 1.18.3. Programmable I/O ports (3)
143
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P8
7
Data bus
Port latch
(Note 1)
fc
Input to respective peripheral functions
Rf
Pull-up selection
Direction register
Rd
P8
6
"1"
Output
Data bus
Port latch
(Note 1)
Note 1:
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Note 2: P1, P4
4 to P47, P72 to P75, P91 are not connected to external pins, but are
present within the microcomputer.
Figure 1.18.4. Programmable I/O ports (4)
(Note2)
(Note1)
BYTE
BYTE signal input
(Note2)
(Note1)
CNVSS
CNVSS signal input
RESET
RESET signal input
(Note1)
Note 1:
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each pin.
Note 2: A parasitic diode on the VCC side is added to the mask ROM version.
Do not apply a voltage higher than Vcc to each pin.
Note 3: The BYTE and CNVss pins are connected on the inside.
Figure 1.18.5. I/O pins
144
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi direction register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PDi (i = 0 to 10, except 8)
Address
When reset
0016
03E216, 03E316, 03E616, 03E716, 03EA16
03EB16, 03EE16, 03EF16, 03F316, 03F616
Bit symbol
PDi_0
Bit name
direction register
Function
R W
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
0 : Input mode
(Functions as an input port)
1 : Output mode
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
1
direction register
direction register
direction register
direction register
direction register
direction register
2
(Functions as an output port)
3
(i = 0 to 10 except 8)
4
Port Pi
Port Pi
Port Pi
5
6
7
PDi_7
direction register
Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to
the port P9 direction register.
Note 2: P1, P44 to P47, P72 to P75, P91 are not connected to the outside, but
are present within the microcomputer, so set the direction registers to
output so that these pin are reserved for future use.
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address
03F216
When reset
00X00000
2
Bit symbol
PD8_0
Bit name
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
R W
Port P8
Port P8
Port P8
0
direction register
direction register
direction register
direction register
direction register
PD8_1
PD8_2
PD8_3
PD8_4
1
2
(Functions as an output port)
Port P8
Port P8
3
4
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_6
PD8_7
Port P8
Port P8
6
direction register
direction register
7
(Functions as an output port)
Figure 1.18.6. Direction register
145
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi register
Symbol
Pi (i = 0 to 10, except 8)
Address
When reset
03E016, 03E116, 03E416, 03E516, 03E816 Indeterminate
03E916, 03EC16, 03ED16, 03F116, 03F416 Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Pi_0
Bit name
Function
R W
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
1
2
3
4
register
register
register
register
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
Pi_1
Pi_2
Pi_3
1 : “H” level data (Note1)
Pi_4
(i = 0 to 10 except 8)
Pi_5
Pi_6
Pi_7
Port Pi
Port Pi
Port Pi
5
register
register
register
6
7
Note 1: Since P7
Note 2: P1, P4
within the microcomputer, so set the unused pin processing.
0
and P7
1
are N-channel open drain ports, the data is high-impedance.
4
to P4
7
, P7
2
to P7 , P9 are not connected to external pins, but are present
5
1
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P8
Address
03F016
When reset
Indeterminate
Bit symbol
P8_0
Bit name
Function
R W
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
0
1
2
3
4
5
6
7
register
register
register
register
register
register
register
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P85)
0 : “L” level data
1 : “H” level data
P8_1
P8_2
P8_3
P8_4
P8_5
P8_6
P8_7
Figure 1.18.7. Port register
146
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
When reset
0016
Bit symbol
PU00
Bit name
Function
R W
P0
P0
P1
P1
P2
P2
P3
P3
0
to P0
to P0
to P1
to P1
to P2
to P2
to P3
to P3
3
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU01
PU02
PU03
PU04
PU05
PU06
PU07
4
0
4
0
4
0
4
7
3
7
3
7
3
7
1 : Pulled high
Note: P1 is not connected to external pins, but are present within the microcomputer, so
set the unused pin processing.
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
When reset
0016 (Note 2)
R W
Bit symbol
PU10
Bit name
Function
P4
0
4
to P4
3
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU11
PU12
PU13
PU14
PU15
P4
to P4
7
P5
P5
P6
P6
0
4
0
4
to P5
to P5
to P6
to P6
3
7
3
7
1 : Pulled high
PU16
PU17
P7
0
to P7
3
pull-up (Note 1)
pull-up
P7
4
to P7
7
Note 1: Since P7
0
and P7
1
are N-channel open drain ports, pull-up is not available for them.
Note 2: When the VCC level is being impressed to the CNVSS terminal, this register becomes
to 0216 when reset (PU11 becomes to “1”).
Note 3: P4
4 to P47, P72 to P75 are not connected to external pins, but are present within the
microcomputer, so set the unused pin processing.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FE16
When reset
0016
Bit symbol
PU20
Bit name
Function
R W
P8
0
4
to P8
3
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU21
P8
to P8
7
pull-up
5)
(Except P8
P9 to P9
P9 to P9
P10
P10
1 : Pulled high
PU22
0
3
pull-up
PU23
PU24
4
7 pull-up
0
to P10
3
pull-up
pull-up
PU25
4
to P10
7
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Note: P9
1 is not connected to external pins, but are present within the microcomputer, so
set the unused pin processing.
Figure 1.18.8. Pull-up control register
147
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Table 1.18.1. Example connection of unused pins in single-chip mode
Pin name
Connection
Ports P0 to P10
After setting for input mode, connect every pin to VSS via a resistor;
or after setting for output mode, leave these pins open.
(excluding P8 ) (Note 1)
5
X
OUT (Note 2)
Open
Connect via resistor to VCC (pull-up)
Connect to VCC
NMI
AVCC
AVSS, VREF, BYTE
Connect to VSS
Note 1: P1, P4 to P47, P72 to P75, P91 are not connected to external pins, but are present within the
4
microcomputer, so set the unused pin processing.
Note 2: With external clock input to XIN pin.
Microcomputer
Port P0 to P10 (except for P85)
(Input mode)
·
·
·
·
·
·
(Input mode)
(Output mode)
Open
NMI
X
OUT
Open
VCC
AVCC
BYTE
AVSS
V
REF
V
SS
In single-chip mode
Note: P1, P44 to P47, P72 to P75, P91 are not connected to external pins.
Figure 1.18.9. Example connection of unused pins
148
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Usage Precaution
Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16”. Reading the
timer Ai register after setting a value in the timer Ai register with a count halted but before the counter
starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16” by underflow
or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with
a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0”
after the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0”
after the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance,
the level does not change, and the timer Ai interrupt request bit does not becomes “1”.
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the
value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the
timer Bi register after setting a value in the timer Bi register with a count halted but before the counter
starts counting gets a proper value.
149
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit
0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-
D conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the
WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction
queue are prefetched and then the program stops. So put at least four NOPs in succession either to
the WAIT instruction or to the instruction that sets the every-clock stop bit to “1”.
Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number
and interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an
interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to
set a value in the stack pointer before accepting an interrupt.
_______
When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning
_______
the first instruction immediately after reset, generating any interrupts including the NMI interrupt is
prohibited.
_______
(3) The NMI interrupt
_______
_______
• The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if
unused.
_______
• Do not get either into stop mode with the NMI pin set to “L”.
150
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
(4) External interrupt
_______
________
• When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set
to "1". After changing the polarity, set the interrupt request bit to "0".
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt
request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt
control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP
NOP
FSET
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
I
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
; Enable interrupts.
FSET
I
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
I
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled,
the interrupt request bit is not set sometimes even if the interrupt request for that register has
been generated. This will depend on the instruction. If this creates problems, use the below
instructions to change the register.
Instructions : AND, OR, BCLR, BSET
Noise
(1) VPP line of one-time PROM version or EPROM version
• VPP (This line is for PROM programming power line) line of internal PROM connected to CNVSS
with one-time PROM version or EPROM version. So CNVSS should be a short line for improve-
ment of noise resistance. If CNVSS line is long, you should insert an approximately 5K ohm
resistor close to CNVSS pin and connect to VSS or VCC.
Note 1: Inserting a 5 K ohm resistor will not cause any problem when switching to mask ROM version.
(2) Insert bypass capacitor between VCC and VSS pin for noise and latch up countermeasure.
• Insert bypass capacitor (about 0.1 µF) and connect short and wide line between VCC and VSS
lines.
151
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Built-in PROM version
(1) All built-in PROM versions
High voltage is required to program to the built-in PROM. Be careful not to apply excessive voltage.
Be especially careful during power-on.
(2) One Time PROM version
One Time PROM versions shipped in blank (M30623ECGP, M30621ECGP), of which built-in PROMs
are programmed by users, are also provided. For these microcomputers, a programming test and
screening are not performed in the assembly process and the following processes. To improve their
reliability after programming, we recommend to program and test as flow shown in Figure 1.19.1
before use.
Programming with PROM programmer
Screening (Note)
(Leave at 150˚C for 40 hours)
Verify test PROM programmer
Function check in target device
Note: Never expose to 150˚C exceeding 100 hours.
Figure 1.19.1. Programming and test flow for One Time PROM version
152
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Items to be submitted when ordering masked ROM version
Please submit the following when ordering masked ROM products:
(1) Mask ROM confirmation form
(2) Mark specification sheet
(3) ROM data : EPROMs or floppy disks
*: In the case of EPROMs, there sets of EPROMs are required per pattern.
*: In the case of floppy disks, 3.5-inch double-sided high-density disk (IBM format) is required per pattern.
Items to be submitted when ordering data to be written to ROM
Please submit the following when ordering data to be written to one-time PROM products at the factory:
(1) ROM writing order form
(2) Mark specification sheet
(3) ROM data : EPROMs or floppy disks
*: In the case of EPROMs, there sets of EPROMs are required per pattern.
*: In the case of floppy disks, 3.5-inch double-sided high-density disk (IBM format) is required per pattern.
153
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Table 1.20.1. Absolute maximum ratings
Parameter
Symbol
Supply voltage
Vcc
Condition
Unit
V
Rated value
-0.3 to 6.5
-0.3 to 6.5
V
CC=AVCC
CC=AVCC
V
Analog supply voltage
AVcc
V
(mask ROM : CNVSS(BYTE)),
RESET,
P0 to P0
P3 to P3
to P6
, P9 to P9
Input
voltage
0
7
, P2
, P4
, P7
0
to P2
to P4
to P7
, P10
7,
0
7
0
3
, P5
, P8
to P10
0
to P5
to P8
7,
7
,
-0.3 to Vcc+0.3
V
P6
0
0
7
6
7
7
0
7
,
VI
P9
2
0
V
REF, XIN
-0.3 to 6.5(Note 1)
-0.3 to Vcc+0.3
V
V
V
P7
P0
0
, P7
1
,(EPROM : CNVSS(BYTE))
, P2 to P2
Output
voltage
0
to P0
to P3
7
0
7,
P3
0
7
,P4
0
to P4
3
, P5
0
to P5
7,
P6
P8
0
6
to P6
7
,P7
6
to P7
7
, P8
0
to P84,
V
O
, P8
to P10
, P7
Power dissipation
7
, P9
0
, P92 to P97,
P10
0
7, XOUT
-0.3 to 6.5
300
P7
0
1
Ta=25
C
Pd
mW
C
T
opr
-20 to 85 / -40 to 85(Note 2)
-65 to 150
Operating ambient temperature
Storage temperature
T
stg
C
Note 1: When writing to EPROM ,only CNVss is –0.3 to 13 (V) .
Note 2: Specify a product of -40 to 85°C to use it.
154
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Table 1.20.2. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = – 20 to
85oC / – 40 to 85oC(Note3) unless otherwise specified)
Standard
Symbol
Vcc
Parameter
Unit
V
Max.
5.5
Min.
2.7
Typ.
5.0
Supply voltage
AVcc
Vss
Analog supply voltage
Supply voltage
Vcc
0
V
V
AVss
Analog supply voltage
0
V
P0
P3
P7
IN, RESET, CNVSS (BYTE)
0
to P0
to P3
, P7 , P8
7
, P2
, P4
to P8
0
to P2
7
,
HIGH input
voltage
0
7
0
to P4
3
, P5
0
to P57, P6
0
to P6
7,
V
IH
0.8Vcc
0.8Vcc
0
V
Vcc
6.5
6
7
0
7
,P9
0
, P9
2
to P9 , P10
7
0
to P107,
X
V
V
P70 , P7
1
LOW input
voltage
P0 to P0
0
7
, P2
0
to P2
to P57, P6
, P9 to P9
7
, P3
0
to P3
to P6
, P10
7,
P4
P8
0
0
to P4
to P8
3
7
, P5
, P9
0
0
7
, P7
0, P71,P76, P77,
V
IL
0.2Vcc
0
2
7
0
to P107,
X
IN, RESET, CNVSS (BYTE)
P0 to P0 , P2 to P2
to P5
, P8 , P9
0
7
0
7,P30 to P37,
HIGH peak output
current
P4
P8
0
0
to P4
to P8
3
4
, P5
, P8
0
6
7
, P6
0
to P6
7
, P7
7
6, P77,
IOH (peak)
–10.0
–5.0
mA
mA
mA
7
0
, P9
2
to P9 , P100 to P107
P0
0
to P0
to P4
7
, P2
0
0
to P2
7
, P30 to P3
, P6 to P6
, P9 to P9
,P30 to P3
, P6 to P6
, P87, P9 , P9 to P9
to P2 ,P30 to P3
to P5
7,
HIGH average output
IOH (avg) current
P4
0
3
, P5
to P5
7
0
7
, P7
6, P77,
P8
P0
P4
P8
P0
P4
P8
0
to P8
to P0
to P4
to P8
to P0
to P4
to P8
4
, P8
, P2
, P5
, P8
, P2
, P5
, P8
6
, P87, P9
to P2
to P5
0
2
7
, P100 to P107
LOW peak output
current
0
7
0
7
7,
7
IOL (peak)
0
3
0
7
0
, P7
0
, P7
1
, P7
6
, P7
7
10.
0
0
4
6
0
2
7
, P10
0
to P107
0
7
0
7
7,
LOW average
output current
IOL (avg)
0
3
0
7
, P6
0
to P6
7
, P7
, P10
0
, P7
1
, P7
6
, P7
7
5.
0
mA
0
4
6
, P87, P9
0
, P9
2
to P9
7
0
to P107
MHz
EPROM,
One time PROM
versions
Vcc=4.5V to 5.5V
Vcc=2.7V to 4.5V
Vcc=4.2V to 5.5V
Vcc=2.7V to 4.2V
0
16
6.95 X Vcc
–15.275
MHz
MHz
MHz
0
0
0
No wait
Mask ROM,
Flash memory 5V
version (Note5)
16
7.33 X Vcc
–14.791
Main clock input
oscillation
frequency
f (XIN
)
EPROM,
One time PROM
versions
Vcc=4.5V to 5.5V
Vcc=2.7V to 4.5V
0
0
16
MHz
MHz
5 X Vcc
–6.5
with wait
Mask ROM,
Flash memory 5V
version (Note5)
Vcc=4.2V to 5.5V
Vcc=2.7V to 4.2V
0
0
16
4 X Vcc
–0.8
MHz
MHz
kHz
f (XcIN
)
Subclock oscillation frequency
32.768
50
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for all ports must be 80mA max. The total IOH (peak) for all ports must be 80mA max.
Note 3: Specify a product of –40 to 85°C to use it.
Note 4: Relationship between main clock oscillation frequency and supply voltage.
Main clock input oscillation frequency
(EPROM, One-time PROM, No wait)
Main clock input oscillation frequency
(Mask ROM, No wait)
Main clock input oscillation frequency
(EPROM, One-time PROM, With wait)
Main clock input oscillation frequency
(Mask ROM, With wait)
16.0
16.0
16.0
7.0
16.0
10.0
6.95 X VCC - 15.275MH
Z
7.33 X VCC - 14.791MH
Z
5 X VCC - 6.5MH
Z
4 X VCC - 0.8MHZ
5.0
0.0
3.5
0.0
0.0
0.0
2.7
4.5
5.5
2.7
4.2
5.5
2.7
4.5
5.5
2.7
4.2
5.5
Supply voltage[V]
(BCLK: no division)
Supply voltage[V]
Supply voltage[V]
(BCLK: no division)
Supply voltage[V]
(BCLK: no division)
(BCLK: no division)
Note 5: Execute case without wait, program / erase of flash memory by VCC=4.2V to 5.5V and f(BCLK) ≤ 6.25 MHz.
Execute case with wait, program / erase of flash memory by VCC=4.2V to 5.5V and f(BCLK) ≤ 12.5 MHz.
155
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Table 1.20.3. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN) =
16MHz unless otherwise specified)
Standard
Measuring condition
Symbol
Parameter
Unit
V
Min. Typ.
Max.
HIGH output P0
0
0
0
6
to P0
to P3
to P6
7
7
7
, P2
, P4
, P7
0
0
6
to P2
to P4
7
,
voltage
P3
P6
P8
3, P50 to P57,
V
V
OH
OH
I
I
OH=–5mA
3.0
, P7
7, P8
0
to P8
, P10
4,
, P8
7, P9
0, P9
2
to P9
7
0
to P10
7
7
P0
P3
P6
P8
0
0
0
6
to P0
to P3
to P6
7, P2
7, P4
7, P7
0
0
6
to P2
to P4
7,
HIGH output
voltage
3, P5
0
to P5
to P8
, P10
7,
OH=–200µA
4.7
V
, P7
7, P8
0
4,
, P8
7, P9
0, P9
2
to P9
7
0
to P10
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
I
I
OH=–1mA
3.0
3.0
3.0
1.6
HIGH output
voltage
X
X
OUT
V
V
OH=–0.5mA
V
OH
With no load applied
With no load applied
HIGH output
voltage
COUT
LOW output P0
0
0
0
6
to P0
to P4
7
, P2
, P5
0
0
to P2
to P5
7
, P3
, P6
0
0
to P3
to P6
7
,
,
voltage
P4
P7
P8
3
7
7
V
V
OL
OL
I
I
OL=5mA
2.0
V
V
, P7
, P8
1
, P7
, P9
6
, P7
, P9
7, P80 to P84,
7
0
2
to P9
7, P10
0
to P10
7
7
LOW output P0
0
0
0
6
to P0
to P4
7
, P2
, P5
0
0
to P2
to P5
7
, P3
, P6
0
0
to P3
to P6
4,
7
,
,
voltage
P4
P7
P8
3
7
7
OL=200µA
0.45
, P7
, P8
1
, P7
, P9
6
, P7
, P9
7, P8
0
to P8
7
0
2
to P9
7, P100 to P10
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
I
I
OL=1mA
2.0
2.0
LOW output
voltage
X
X
OUT
V
V
OL=0.5mA
V
OL
0
0
With no load applied
With no load applied
LOW output
voltage
COUT
TA0IN, TA3IN, TA4IN
TB0IN, TB2IN to TB5IN, INT
ADTRG, CTS , CTS , CLK
CLK , TA3OUT, TA4OUT, NMI, KI
IN4, R to R
RESET
,
0
to INT
,CLK , CLK
to KI
2,
V
V
T+-
T+-
V
V
T-
T-
0.2
0.2
0.8
V
Hysteresis
Hysteresis
0
1
0
1
3
,
4
0
3
,
S
XD0
XD2
1.8
5.0
V
P0
P4
P7
P9
0
0
0
0
to P0
to P4
7
, P2
, P5
0
to P2
to P5
7
, P3
, P6
0
0
to P3
to P6
7,
7
,
,
3
0
7
7
µA
I
IH
HIGH input
current
V
V
I
=5V
=0V
, P7
, P9
1
, P7
to P9
6, P7
7, P8
0
to P8
2
7, P100 to P107,
X
IN, RESET, CNVss (BYTE)
P0
P4
P7
P9
0
0
6
0
to P0
to P4
7
, P2
, P5
0
0
to P2
to P5
7,
7
, P3
, P6
0
0
to P3
to P6
7
,
,
3
7
7
LOW input
current
IIL
I
–5.0
µA
, P7
, P9
7
, P8
to P9
0
to P8
2
7, P100 to P107,
X
IN, RESET, CNVss (BYTE)
P0
P4
P7
0
0
6
to P0
to P4
7
, P2
, P5
0
0
to P2
to P5
7
, P3
, P6
6,P87,
0
0
to P3
to P6
7
,
,
3
7
7
Pull-up
resistance
RPULLUP
50.0
KΩ
, P7
7, P8
0
to P8
4, P8
P90, P9
2
to P9
7, P10
0
to P107
Feedback resistance
Feedback resistance
R fXIN
X
IN
1.0
6.0
MΩ
MΩ
RfCXIN
X
CIN
VRAM
2.0
V
When clock is stopped
RAM retention voltage
EPROM, One time PROM,
mask ROM versions
f(XIN)=16MHz
The output pins
are open and
other pins are
30.0
50.0 mA
Square wave, no division
Flash memory 5V
version
f(XIN)=16MHz
Square wave, no division
35.0
90.0
90.0
50.0 mA
V
SS
EPROM, One time PROM,
mask ROM versions
f(XCIN)=32kHz
Square wave
µA
µA
f(XCIN)=32kHz
Square wave, in RAM
Flash memory 5V
version
Icc
Power supply current
f(XCIN)=32kHz
Square wave, in flash memory
Flash memory 5V
version
8.0
4.0
mA
f(XCIN)=32kHz
When a WAIT instruction
is executed (Note)
µA
Ta=25°C
when clock is stopped
1.0
µA
Ta=85°C
when clock is stopped
20.0
Note : With one timer operated using fC32.
156
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Table 1.20.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V
at Ta = 25oC, f(XIN) = 16MHz unless otherwise specified)
Standard
Symbol
Parameter
Measuring condition
Unit
Min. Typ. Max.
10 Bits
V
REF
REF = VCC = 5V
AN
=
V
CC
Resolution
Absolute
accuracy
Sample & hold function not available
V
LSB
LSB
±3
±3
0
to AN7 input
Sample & hold function available(10bit)
V
= 5V
REF =VCC
ANEX0, ANEX1 input,
LSB
±7
External op-amp connection mode
V
REF = VCC = 5V
Sample & hold function available(8bit)
LSB
±2
40
R
LADDER
kΩ
V
REF
=
V
CC
10
3.3
Ladder resistance
Conversion time(10bit)
Conversion time(8bit)
Sampling time
t
CONV
µs
t
CONV
2.8
0.3
2
µs
µs
V
t
SAMP
V
CC
V
REF
IA
Reference voltage
V
0
V
REF
V
Analog input voltage
Note: Divide the frequency if f(XIN) exceeds 10 MHz, and make ØAD equal to or lower than 10 MHz.
Table 1.20.5. D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V
at Ta = 25oC, f(XIN) = 16MHz unless otherwise specified)
Standard
Min. Typ. Max.
Symbol
Parameter
Measuring condition
Unit
Resolution
Absolute accuracy
Setup time
Bits
%
8
1.0
3
tsu
µs
RO
kΩ
Output resistance
4
10
20
IVREF
Reference power supply input current
1.5
mA
(Note)
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”.
The A-D converter's ladder resistance is not included.
Also, when DA register contents are not “00”, the current IVREF always flows even though Vref may
have been set to be “unconnected” by the A-D control register.
157
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (VCC=5V)
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.20.6. External clock input
Standard
Symbol
Parameter
Unit
Min.
62.5
25
Max.
t
c
ns
ns
ns
ns
ns
External clock input cycle time
t
w(H
)
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
t
w(L)
25
t
r
15
15
t
f
External clock fall time
158
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (VCC=5V)
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.20.7. Timer A input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
40
Table 1.20.8. Timer A input (gating input in timer mode)
Standard
Symbol
Parameter
Unit
Min.
400
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.20.9. Timer A input (external trigger input in one-shot timer mode)
Standard
Min. Max.
200
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
100
100
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.20.10. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.20.11. Timer A input (up/down input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN)
t
h(TIN-UP)
400
159
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (VCC=5V)
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.20.12. Timer B input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
t
t
200
80
t
w(TBH)
t
w(TBL)
80
Table 1.20.13. Timer B input (pulse period measurement mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.20.14. Timer B input (pulse width measurement mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.20.15. A-D trigger input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
t
c(AD)
w(ADL)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
Table 1.20.16. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
80
0
30
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 1.20.17. External interrupt INTi inputs
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
160
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (VCC=5V)
VCC = 5V
t
c(TA)
tw(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
th(TIN–UP)
tsu(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
t
c(TB)
tw(TBH)
TBiIN input
t
w(TBL)
t
t
c(AD)
tw(ADL)
ADTRG input
c(CK)
tw(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
tsu(D–C)
t
d(C–Q)
th(C–D)
tw(INL)
INTi input
t
w(INH)
161
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Table 1.20.18. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) =
7MHz(Note 1) with wait)
Standard
Symbol
VOH
Parameter
Measuring condition
Unit
V
Min.
2.5
Typ.
Max.
P00 to P07, P20 to P27, P30 to P37,
P40 to P43, P50 to P57, P60 to P67,
P76, P77, P80 to P84, P86, P87,
P90, P92 to P97, P100 to P107
HIGH output
voltage
IOH=–1mA
HIGHPOWER
IOH=–0.1mA
2.5
2.5
HIGH output
voltage
XOUT
VOH
VOL
V
V
LOWPOWER
IOH=–50µA
With no load applied
With no load applied
3.0
1.6
HIGHPOWER
XCOUT
HIGH output
voltage
LOWPOWER
P00 to P07, P20 to P27, P30 to P37,
P40 to P43, P50 to P57, P60 to P67,
P70, P71, P76, P77, P80 to P84, P86,
P87, P90, P92 to P97, P100 to P107
LOW output
voltage
IOL=1mA
0.5
V
IOL=0.1mA
0.5
0.5
HIGHPOWER
LOW output
voltage
XOUT
VOL
V
V
IOL=50µA
LOWPOWER
TA0IN, TA3IN, TA4IN,
TB0IN, TB2IN to TB5IN, INT0 to INT2,
ADTRG,CTS0,CTS1 CLK0,CLK1,CLK3,
CLK4, TA3OUT, TA4OUT, NMI, KI0 to KI3,
SIN4, RXD0 to RXD2
VT+-VT-
0.2
0.2
0.8
Hysteresis
VT+-VT-
IIH
1.8
4.0
V
RESET
Hysteresis
P00 to P07, P20 to P27, P30 to P37,
P40 to P43, P50 to P57, P60 to P67,
P70, P71, P76, P77, P80 to P87,
P90, P92 to P97, P100 to P107,
HIGH input
current
VI=3V
VI=0V
µA
XIN, RESET, CNVss (BYTE)
LOW input
current
P00 to P07, P20 to P27, P30 to P37,
P40 to P43, P50 to P57, P60 to P67,
P70, P71, P76, P77, P80 to P87,
P90, P92 to P97, P100 to P107,
XIN, RESET, CNVss (BYTE)
IIL
–4.0
µA
Feedback resistance
RfXIN
RfCXIN
VRAM
XIN
3.0
MΩ
MΩ
V
XCIN
10.0
Feedback resistance
RAM retention voltage
2.0
When clock is stopped
f(XIN)=7MHz
The output pins
are open and
other pins are
VSS
EPROM,One-time PROM
versions
6.0
8.5
15.0 mA
21.25 mA
21.25 mA
Square wave, no division
f(XIN)=10MHz
Square wave, no division
Mask ROM version
f(XIN)=10MHz
Square wave, no division
Flash memory 5V version
13.5
EPROM,One-time PROM,
mask ROM versions
f(XCIN)=32kHz
Square wave
40.0
µA
f(XCIN)=32kHz
Square wave, in RAM
40.0
4.5
µA
Flash memory 5V version
Flash memory 5V version
f(XCIN)=32kHz
Square wave, in flash
memory
mA
Icc
Power supply current
f(XCIN)=32kHz
When a WAITinstruction
is executed.
Oscillation capacity High
(Note2)
2.8
0.9
µA
µA
f(XCIN)=32kHz
When a WAIT instruction
is executed.
Oscillation capacity Low
(Note2)
Ta=25°C
when clock is stopped
1.0
µA
Ta=85°C
when clock is stopped
20.0
Note 1: 10 MHZ for the mask ROM version and flash memory version.
Note 2: With one timer operated using fC32.
162
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Table 1.20.19. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS
=
0V at Ta = 25oC, f(XIN) = 7MHz unless otherwise specified)
Standard
Min. Typ. Max
Symbol
Parameter
Measuring condition
Unit
Resolution
V
REF = VCC
10
±2
Bits
Absolute accuracy Sample & hold function not available (8 bit)
LSB
V
REF = VCC = 3V, φAD = f(XIN)/2
R
LADDER
VREF = VCC
kΩ
Ladder resistance
40
10
Conversion
time(8bit)
t
CONV
One-time PROM, EPROM versions
Mask ROM, flash memory 5V versions
14.0
µs
µs
V
9.8
2.7
V
REF
IA
V
CC
Reference voltage
Analog input voltage
V
0
V
REF
V
Note: 10 MHz for the mask ROM version and flash memory 5V version.
Table 1.20.20. D-A conversion characteristics (referenced to VCC = 3V, VSS = AVSS = 0V, VREF = 3V
at Ta = 25oC, f(XIN) = 7MHz(Note2) unless otherwise specified)
Standard
Min. Typ. Max
8
Symbol
Parameter
Measuring condition
Unit
Bits
Resolution
Absolute accuracy
Setup time
1.0
3
%
µs
t
su
RO
Output resistance
4
10
20
kΩ
Reference power supply input current
(Note1)
1.0
I
VREF
mA
Note 1: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
“0016”. The A-D converter's ladder resistance is not included.
Also, when DA register contents are not “00”, the current IVREF always flows even though Vref may
have been set to be “unconnected” by the A-D control register.
Note 2: 10 MHz for the mask ROM version and flash memory 5V version.
163
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.20.21. External clock input
Standard
Symbol
Parameter
Unit
Min.
143
100
60
Max.
One-time PROM, EPROM versions
ns
ns
ns
ns
ns
ns
ns
ns
External clock input
cycle time
t
c
Mask ROM, Flash memory 5V versions
One-time PROM, EPROM versions
Mask ROM, Flash memory 5V versions
One-time PROM, EPROM versions
External clock input
HIGH pulse width
t
w(H)
40
60
External clock input
LOW pulse width
t
w(L)
40
Mask ROM, Flash memory 5V versions
t
r
External clock rise time
External clock fall time
18
18
t
f
164
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.20.22. Timer A input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
60
Table 1.20.23. Timer A input (gating input in timer mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
Table 1.20.24. Timer A input (external trigger input in one-shot timer mode)
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
Table 1.20.25. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
ns
t
w(TAL)
Table 1.20.26. Timer A input (up/down input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
t
c(UP)
TAiOUT input cycle time
ns
ns
ns
ns
ns
t
w(UPH)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
t
w(UPL)
t
su(UP-TIN
)
t
h(TIN-UP)
TAiOUT input hold time
600
165
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.20.27. Timer B input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
t
c(TB)
TBiIN input cycle time (counted on one edge)
ns
ns
ns
ns
ns
ns
t
w(TBH)
w(TBL)
c(TB)
w(TBH)
w(TBL)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
t
60
t
300
160
160
t
t
Table 1.20.28. Timer B input (pulse period measurement mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
w(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
Table 1.20.29. Timer B input (pulse width measurement mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
w(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
Table 1.20.30. A-D trigger input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
t
c(AD)
w(ADL)
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
ns
ns
t
Table 1.20.31. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(CK)
w(CKH)
w(CKL)
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
ns
ns
ns
ns
ns
ns
ns
t
t
t
d(C-Q)
h(C-Q)
su(D-C)
160
t
0
50
90
t
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 1.20.32. External interrupt INTi inputs
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
t
w(INH)
INTi input HIGH pulse width
INTi input LOW pulse width
ns
ns
t
w(INL)
166
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
t
c(TA)
t
w(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
t
w(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
t
h(TIN–UP)
t
su(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
t
c(TB)
t
w(TBH)
TBiIN input
t
w(TBL)
t
c(AD)
t
w(ADL)
ADTRG input
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
d(C–Q)
t
su(D–C)
t
h(C–D)
t
w(INL)
INTi input
t
w(INH)
167
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 59B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30621M8-XXXGP
MASK ROM CONFIRMATION FORM
Date :
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
issued
Date :
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30621M8-XXXGP
Checksum code for total EPROM area :
EPROM type :
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30621M8 -
containing ASCII
code for M30621M8 -
0000F16
0001016
0000F16
0001016
2FFFF16
3000016
6FFFF16
7000016
ROM(64K)
ROM(64K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
'
'
'
'
'
'
M
3
0
6
2
1
M
8
'
'
'
'
'
'
= 4D16
'
—
'
= 2D16
FF16
0000916
0000A16
0000B16
= 3316
= 3016
= 3616
= 3216
= 3116
= 4D16
= 3816
FF16
FF16
0000216
0000316
0000416
The ASCII code for 'M30621M8-' is shown at right.
The data in this table must be written to address
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
168
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 59B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30621M8-XXXGP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30621M8- '
.BYTE
' M30621M8- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30621M8-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30621M8-XXXGP, submit the 80P6S mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
169
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 59B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30621M8-XXXGP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
170
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 61B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30621MA-XXXGP
MASK ROM CONFIRMATION FORM
Date :
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
issued
Date :
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30621MA-XXXGP
Checksum code for total EPROM area :
EPROM type :
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30621MA-
containing ASCII
code for M30621MA -
0000F16
0001016
0000F16
0001016
27FFF16
2800016
67FFF16
6800016
ROM(96K)
ROM(96K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
'
'
'
'
'
'
M
3
0
6
2
1
M
A
'
'
'
'
'
'
= 4D16
'
—
'
= 2D16
FF16
0000916
0000A16
0000B16
= 3316
= 3016
= 3616
= 3216
= 3116
= 4D16
= 4116
FF16
FF16
0000216
0000316
0000416
The ASCII code for 'M30621MA-' is shown at right.
The data in this table must be written to address
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
171
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 61B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30621MA-XXXGP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30621MA- '
.BYTE
' M30621MA- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30621MA-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30621MA-XXXGP, submit the 80P6S mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
172
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 61B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30621MA-XXXGP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
173
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 63B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30621MC-XXXGP
MASK ROM CONFIRMATION FORM
Date :
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
issued
Date :
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30621MC-XXXGP
Checksum code for total EPROM area :
EPROM type :
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30621MC-
containing ASCII
code for M30621MC -
0000F16
0001016
0000F16
0001016
1FFFF16
2000016
5FFFF16
6000016
ROM(128K)
ROM(128K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
'
'
'
'
'
'
M
3
0
6
2
1
M
C
'
'
'
'
'
'
= 4D16
'
—
'
= 2D16
FF16
0000916
0000A16
0000B16
= 3316
= 3016
= 3616
= 3216
= 3116
= 4D16
= 4316
FF16
FF16
0000216
0000316
0000416
The ASCII code for 'M30621MC-' is shown at right.
The data in this table must be written to address
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
174
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 63B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30621MC-XXXGP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30621MC- '
.BYTE
' M30621MC- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30621MC-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30621MC-XXXGP, submit the 80P6S mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
175
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 63B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30621MC-XXXGP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
176
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 75B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623M4-XXXGP
MASK ROM CONFIRMATION FORM
Date :
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
issued
Date :
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30623M4-XXXGP
Checksum code for total EPROM area :
EPROM type :
(hex)
27C401
27C101
27C201
Address
Address
Address
0000016
0000016
0000016
Product : Area
Product : Area
Product : Area
containing ASCII
code for M30623M4 -
containing ASCII
code for M30623M4-
containing ASCII
code for M30623M4 -
0000F16
0001016
0000F16
0001016
0000F16
0001016
77FFF16
7800016
17FFF16
1800016
37FFF16
3800016
ROM(32K)
ROM(32K)
ROM(32K)
7FFFF16
1FFFF16
3FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
'
'
'
'
'
'
M
3
0
6
2
3
M
4
'
'
'
'
'
'
= 4D16
'
—
'
= 2D16
FF16
0000916
0000A16
0000B16
= 3316
= 3016
= 3616
= 3216
= 3316
= 4D16
= 3416
FF16
FF16
0000216
0000316
0000416
The ASCII code for 'M30623M4-' is shown at right.
The data in this table must be written to address
0000016 to 0000F16.
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
177
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 75B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623M4-XXXGP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C401
.SECTION
ASCIICODE, ROM DATA
.ORG 080000H
27C101
.SECTION
ASCIICODE, ROM DATA
.ORG 0E0000H
27C201
.SECTION
ASCIICODE, ROM DATA
.ORG 0C0000H
EPROM type
Code entered in
source program
.BYTE
' M30623M4- '
.BYTE
' M30623M4- '
.BYTE
' M30623M4- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30623M4-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30623M4-XXXGP, submit the 80P6S mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
178
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 75B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623M4-XXXGP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
179
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 65B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623M8-XXXGP
MASK ROM CONFIRMATION FORM
Date :
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
issued
Date :
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30623M8-XXXGP
Checksum code for total EPROM area :
EPROM type :
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30623M8 -
containing ASCII
code for M30623M8 -
0000F16
0001016
0000F16
0001016
2FFFF16
3000016
6FFFF16
7000016
ROM(64K)
ROM(64K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
'
'
'
'
'
'
M
3
0
6
2
3
M
8
'
'
'
'
'
'
= 4D16
'
—
'
= 2D16
FF16
0000916
0000A16
0000B16
= 3316
= 3016
= 3616
= 3216
= 3316
= 4D16
= 3816
FF16
FF16
0000216
0000316
0000416
The ASCII code for 'M30623M8-' is shown at right.
The data in this table must be written to address
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
180
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 65B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623M8-XXXGP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30623M8- '
.BYTE
' M30623M8- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30623M8-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30623M8-XXXGP, submit the 80P6S mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
181
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 65B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623M8-XXXGP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
182
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 67B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623MA-XXXGP
MASK ROM CONFIRMATION FORM
Date :
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
issued
Date :
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30623MA-XXXGP
Checksum code for total EPROM area :
EPROM type :
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30623MA-
containing ASCII
code for M30623MA -
0000F16
0001016
0000F16
0001016
27FFF16
2800016
67FFF16
6800016
ROM(96K)
ROM(96K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
'
'
'
'
'
'
M
3
0
6
2
3
M
A
'
'
'
'
'
'
= 4D16
'
—
'
= 2D16
FF16
0000916
0000A16
0000B16
= 3316
= 3016
= 3616
= 3216
= 3316
= 4D16
= 4116
FF16
FF16
0000216
0000316
0000416
The ASCII code for 'M30623MA-' is shown at right.
The data in this table must be written to address
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
183
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 67B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623MA-XXXGP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30623MA- '
.BYTE
' M30623MA- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30623MA-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30623MA-XXXGP, submit the 80P6S mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
184
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 67B <82A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623MA-XXXGP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
185
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 04B <77A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623MC-XXXGP
MASK ROM CONFIRMATION FORM
Date :
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
issued
Date :
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30623MC-XXXGP
Checksum code for total EPROM area :
EPROM type :
(hex)
27C201
27C401
Address
Address
0000016
0000016
Product : Area
Product : Area
containing ASCII
code for M30623MC-
containing ASCII
code for M30623MC -
0000F16
0001016
0000F16
0001016
1FFFF16
2000016
5FFFF16
6000016
ROM(128K)
ROM(128K)
3FFFF16
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
'
'
'
'
'
'
M
3
0
6
2
3
M
C
'
'
'
'
'
'
= 4D16
'
—
'
= 2D16
FF16
0000916
0000A16
0000B16
= 3316
= 3016
= 3616
= 3216
= 3316
= 4D16
= 4316
FF16
FF16
0000216
0000316
0000416
The ASCII code for 'M30623MC-' is shown at right.
The data in this table must be written to address
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
186
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 04B <77A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623MC-XXXGP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
27C201
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 0C0000H
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30623MC- '
.BYTE
' M30623MC- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30623MC-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30623MC-XXXGP, submit the 80P6S mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
187
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 04B <77A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30623MC-XXXGP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
188
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 79B <83A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30625MG-XXXGP
MASK ROM CONFIRMATION FORM
Date :
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
issued
Date :
1. Check sheet
Name the product you order, and choose which to give in, EPROMs or floppy disks.
If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by
means of floppy disks, one floppy disk is required per pattern.
In the case of EPROMs
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30625MG-XXXGP
Checksum code for total EPROM area :
EPROM type :
(hex)
27C401
Address
0000016
Product : Area
containing ASCII
code for M30625MG-
0000F16
0001016
3FFFF16
4000016
ROM(128K)
7FFFF16
Address
Address
0000016
0000116
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
0000816
'
'
'
'
'
'
'
'
M
3
0
6
2
5
M
G
'
'
'
'
'
'
= 4D16
'
—
'
= 2D16
FF16
0000916
0000A16
0000B16
= 3316
= 3016
= 3616
= 3216
= 3516
= 4D16
= 4716
FF16
FF16
0000216
0000316
0000416
The ASCII code for 'M30625MG-' is shown at right.
The data in this table must be written to address
0000C16
0000D16
0000E16
FF16
FF16
FF16
0000016 to 0000F16
.
0000516
0000616
0000716
Both address and data are shown in hex.
'
'
0000F16
FF16
189
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 79B <83A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30625MG-XXXGP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
EPROM type
27C401
.SECTION ASCIICODE, ROM DATA
.ORG 080000H
Code entered in
source program
.BYTE
' M30625MG- '
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
Note:
In the case of floppy disks
Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on
the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that
there is any discrepancy between the contents of these mask files and the ROM data to be burned into
products we produce. Check thoroughly the contents of the mask files you give in.
Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. :
File code :
M30625MG-XXXGP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet
for submission to Mitsubishi.
For the M30625MG-XXXGP, submit the 80P6S mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
190
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH12 79B <83A0>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30625MG-XXXGP
MASK ROM CONFIRMATION FORM
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
(4) Which operating ambient temperature do you use?
–10 °C to 75 °C
–10 °C to 85 °C
–20 °C to 75 °C
–20 °C to 85 °C
–40 °C to 75 °C
–40 °C to 85 °C
(5) Which operating supply voltage do you use?
2.7V to 3.2V
4.2V to 4.7V
3.2V to 3.7V
4.7V to 5.2V
3.7V to 4.2V
5.2V to 5.5V
Thank you cooperation.
4. Special item (Indicate none if there is no specified item)
191
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Outline Performance
Table 1.21.1 shows the outline performance of the M16C/62 (80-pin flash memory version) and Table
1.21.2 shows the power supply current (Typ.).
Table 1.21.1. Outline Performance of the M16C/62 (flash memory version)
Item
Performance
Power supply voltage
5V version: 2.7V to 5.5 V
(f(XIN)=16MHz, without wait, 4.2V to 5.5V,
f(XIN)=10MHz, with one wait, 2.7V to 5.5V)
3V version: 2.4V to 3.6 V
(f(XIN)=10MHz, without wait, 2.7V to 3.6V,
f(XIN)=7MHz, without wait, 2.4V to 3.6V)
5V version: 4.2V to 5.5 V
Program/erase voltage
(f(XIN)=12.5MHz, with one wait,
f(XIN)=6.25MHz, without wait)
3V version: 2.7V to 3.6 V
(f(XIN)=10MHz, with one wait,
f(XIN)=6.25MHz, without wait)
Flash memory operation mode
Three modes (parallel I/O, standard serial I/O, CPU rewrite)
Erase block
division
See Figure 1.21.1
User ROM area
Boot ROM area
One division (8 Kbytes) (Note 1)
In units of pages (in units of 256 bytes)
Collective erase/block erase
Program/erase control by software command
Protected for each block by lock bit
8 commands
Program method
Erase method
Program/erase control method
Protect method
Number of commands
Program/erase count
100 times
Parallel I/O and standard serial modes are supported.
ROM code protect
3V version main clock input
oscillation frequency(Max.)
(Note2)
10MHz (VCC=2.7V to 3.6V,without wait)
10 X VCC - 17 MHz (VCC=2.4V to 2.7V,without wait)
3V version power supply
current (Notes 3, 4)
12.0mA(Typ.), 21.25mA(Max.) (VCC=3V, f(XIN)=10MHz, square wave, no division, without wait)
40µA(Typ.) (VCC=3V, f(XCIN)=32kHz, square wave, without wait) [operate in RAM]
700µA(Typ.) (VCC=3V, f(XCIN)=32kHz, square wave, without wait) [operate in flash memory]
Note1: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory.
This area can be erased and programmed in only parallel I/O mode.
Note2: Refer to recommended operating conditions about 5 V version. 3V version relationship between main clock oscillation
frequency and supply voltage are as follows.
Main clock input oscillation frequency
(flash memory 3V version, without wait)
10.0
10 X VCC - 17MH
Z
7.0
0.0
2.4
Supply voltage[V]
2.7
3.6
(BCLK: no division)
Note3: Refer to electric characteristic about 5V version.
Note4: A standard value in stop and wait modes do not depend on a kind of memory to have built-in and is the same class. Refer to
electric characteristic in VCC=3V.
Table 1.21.2. Power supply current (typ.) of the M16C/62 (80-pin flash memory version)
Standard (Typ.)
Remark
Parameter
Measuring condition
Read
Program
28mA
-
Erase
25mA
-
Division by 4 in program/erase
5V power supply current(5V version) f(XIN)=16MHz, without wait, No division
3V power supply current(5V version) f(XIN)=10MHz, with wait, No division
3V power supply current(3V version) f(XIN)=10MHz, without wait, No division
35mA
13.5mA
12mA
Division by 2 in program/erase
17mA
14mA
192
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Flash Memory
The M16C/62 (80-pin flash memory version) contains the DINOR (DIvided bit line NOR) type of flash
memory that can be rewritten with a single voltage of 5 V or 3.3 V. For this flash memory, three flash
memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O
modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in
which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed
in the pages to follow.
The flash memory is divided into several blocks as shown in Figure 1.21.1, so that memory can be erased
one block at a time. Each block has a lock bit to enable or disable execution of an erase or program
operation, allowing for data in each block to be protected.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and
standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored
in it when shipped from the factory. However, the user can write a rewrite control program in this area that
suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.
0C000016
Block 6 : 64K byte
0D000016
Block 5 : 64K byte
0E000016
Block 4 : 64K byte
Note 1: The boot ROM area can be rewritten in
only parallel input/output mode. (Access
to any other areas is inhibited.)
Note 2: To specify a block, use the maximum
address in the block that is an even
address.
0F000016
Block 3 : 32K byte
Flash memory
start address
Flash memory
size
0F800016
0FA00016
Block 2 : 8K byte
Block 1 : 8K byte
Block 0 : 16K byte
256 K byte
0C000016
0FC00016
0FFFFF16
0FE00016
8K byte
0FFFFF16
Boot ROM area
User ROM area
Figure 1.21.1. Block diagram of flash memory version
193
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control
of the Central Processing Unit (CPU).
In CPU rewrite mode, only the user ROM area shown in Figure 1.21.1 can be rewritten; the boot ROM area
cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM
area and each block area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to any area other than the internal flash memory before it can be executed.
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure 1.21.1 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In
this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P55 pin low, the CNVSS pin high, and the P50 pin high, the
CPU starts operating using the control program in the boot ROM area. This mode is called the “boot”
mode. The control program in the boot ROM area can also be used to rewrite the user ROM area.
Block Address
Block addresses refer to the maximum even address of each block. These addresses are used in the
block erase command, lock bit program command, and read lock status command.
194
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Outline Performance (CPU Rewrite Mode)
In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by
software commands. Operations must be executed from a memory other than the internal flash memory,
such as the internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 03B716) is set to “1”, transition to CPU rewrite mode
occurs and software commands can be accepted.
In the CPU rewrite mode, write to and read from software commands and data into even-numbered ad-
dress (“0” for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered
address. Commands are ignored with odd-numbered addresses.
Use software commands to control program and erase operations. Whether a program or erase operation
has terminated normally or in error can be verified by reading the status register.
Figure 1.22.1 shows the flash memory control register 0 and the flash memory control register 1.
_____
Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating
status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is “1”.
Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is
entered by setting this bit to “1”, so that software commands become acceptable. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area other
than the internal flash memory. To set this bit to “1”, it is necessary to write “0” and then write “1” in
succession. The bit can be set to “0” by only writing a “0” .
Bit 2 of the flash memory control register 0 is a lock bit disable bit. By setting this bit to “1”, it is possible to
disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable select bit
only disables the lock bit function; it does not change the lock data bit value. However, if an erase operation
is performed when this bit =“1”, the lock bit data that is “0” (locked) is set to “1” (unlocked) after erasure. To
set this bit to “1”, it is necessary to write “0” and then write “1” in succession. This bit can be manipulated
only when the CPU rewrite mode select bit = “1”.
Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of
the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access
has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control circuit. To
release the reset, it is necessary to set this bit to “0”.
Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot
mode. If this bit is set to “1” in boot mode, the area to be accessed is switched from the boot ROM area to
the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to “1”. Note
that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be
accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of
whether the CPU rewrite mode is on or off. Use the control program except in the internal flash memory to
rewrite this bit.
195
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Bit 3 of the flash memory control register 1 turns power supply to the internal flash memory on/off. When
this bit is set to “1”, power is not supplied to the internal flash memory, thus power consumption can be
reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit to “1”, it is
necessary to write “0” and then write “1” in succession. Use this bit mainly in the low speed mode (when
XCIN is the block count source of BCLK).
When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut
off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly neces-
sary to set flash memory control register 1.
Figure 1.22.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 1.22.3 shows a flow-
chart for shifting to the low speed mode. Always perform operation as indicated in these flowcharts.
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR0
Address
03B716
When reset
XX000001
2
0
R
W
Bit name
Function
Bit symbol
FMR00
0: Busy (being written or erased)
1: Ready
RY/BY status flag
CPU rewrite mode
select bit (Note 1)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
FMR01
(Software commands acceptable)
Lock bit disable bit
(Note 2)
0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
FMR02
FMR03
Flash memory reset bit 0: Normal operation
(Note 3)
1: Reset
Reserved bit
User ROM area select bit
Must always be set to “0”
0: Boot ROM area is accessed
1: User ROM area is accessed
FMR05
(Note 4) (Effective in only
boot mode)
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to
it in succession. When it is not this procedure, it is not enacted in “1”.
This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval. Use the control program except in the
internal flash memory for write to this bit.
Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to
it in succession when the CPU rewrite mode select bit = “1”. When it is
not this procedure, it is not enacted in “1”. This is necessary to ensure
that no interrupt or DMA transfer will be executed during the interval.
Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0
subsequently after setting it to 1 (reset).
Note 4: Use the control program except in the internal flash memory for write to
this bit.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR1
Address
03B616
When reset
XXXXX0XX
2
0
0
0
0
0
0
0
R
W
Bit name
Function
Bit symbol
Reserved bit
Must always be set to “0”
0: Flash memory power supply is
connected
1: Flash memory power supply-off
FMR13
Flash memory power
supply-OFF bit(Note)
Reserved bit
Must always be set to “0”
Note : For this bit to be set to “1”, the user needs to write a “0” and then a “1” to
it in succession. When it is not this procedure, it is not enacted in “1”.
This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval. Use the control program except in the
internal flash memory for write to this bit.
During parallel I/O mode,programming,erase or read of flash memory is
not controlled by this bit,only by external pins.
Figure 1.22.1. Flash memory control registers
196
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Program in ROM
Start
Program in RAM
*1
(Boot mode only)
Set user ROM area select bit to “1”
Single-chip mode, or boot mode
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)(Note 2)
Set processor mode register (Note 1)
Transfer CPU rewrite mode control
program to internal RAM
Using software command execute erase,
program, or other operation
(Set lock bit disable bit as required)
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
*1
Write “0” to CPU rewrite mode select bit
(Boot mode only)
Write “0” to user ROM area select bit (Note 4)
End
Note 1: During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio
select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716):
6.25 MHz or less when wait bit (bit 7 at address 000516) = “0” (without internal access wait state)
12.5 MHz or less when wait bit (bit 7 at address 000516) = “1” (with internal access wait state)
Note 2: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval.
Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Note 4: “1” can be set. However, when this bit is “1”, user ROM area is accessed.
Figure 1.22.2. CPU Rewrite Mode Set/Reset Flowchart
Program in ROM
Program in RAM
*1
Start
Transfer the program to be executed in the
low speed mode, to the internal RAM.
Set flash memory power supply-OFF bit to “1”
(by writing “0” and then “1” in succession)(Note 1)
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Switch the count source of BCLK.
X
IN stop. (Note 2)
Process of low speed mode
*1
X
IN oscillating
Wait until the XIN has stabilized
Switch the count source of BCLK (Note 2)
Set flash memory power supply-OFF bit to “0”
Wait time until the internal circuit stabilizes
(Set NOP instruction about twice)
End
Note 1: For flash memory power supply-OFF bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval.
Note 2: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably.
Figure 1.22.3. Shifting to The Low Speed Mode Flowchart
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide
ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716):
6.25 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state)
12.5 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
The address match interrupt cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be
_______
used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts each can
be used to change the flash memory’s operation mode forcibly to read array mode upon occurrence of
_______
the interrupt. Since the rewrite operation is halted when the NMI and watchdog timer interrupts occur,
the erase/program operation needs to be performed over again.
Disabling erase or rewrite operations for address FC00016 to address FFFFF16 in the user ROM block
disables these operations for all subsequent blocks as well. Therefore, it is recommended to rewrite
this block in the standard serial I/O mode.
(4) Internal reserved area expansion bit (Bit 3 at address 000516)
The reserved area of the internal memory can be changed by using the internal reserved area expan-
sion bit (bit 3 at address 000516). However, if the CPU rewrite mode select bit (bit 1 at address 03B716)
is set to 1, the internal reserved area expansion bit (bit 3 at address 000516) also is set to 1 automati-
cally. Similarly, if the CPU rewrite mode select bit (bit 1 at address 03B716) is set to 0, the internal
reserved area expansion bit (bit 3 at address 000516) also is set to 0 automatically.
The precautions above apply to the products which RAM size is over 15 Kbytes or flash memory size
is over 192 Kbyte.
(5) Reset
Reset input is always accepted. After a reset, the addresses 0C000016 through 0CFFFF16 are made
a reserved area and cannot be accessed. Therefore, if your product has this area in the user ROM
area, do not write any address of this area to the reset vector. This area is made accessible by
changing the internal reserved area expansion bit (bit 3 at address 000516) in a program.
(6) Access disable
Write CPU rewrite mode select bit, flash memory power supply-OFF bit and user ROM area select bit
in an area other than the internal flash memory.
(7) How to access
For CPU rewrite mode select bit, lock bit disable bit, and flash memory power supply-OFF bit to be set
to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it
is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed
during the interval.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Software Commands
Table 1.22.1 lists the software commands available with the M16C/62 (flash memory version).
After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or
program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored.
The content of each software command is explained below.
First bus cycle
Address
Second bus cycle
Third bus cycle
Command
Data
(D to D
Data
to D
Data
to D7)
Mode Address
Mode Address
Mode
0
7)
(D
0
7
)
(D
0
(Note 6)
Read array
Write
Write
Write
Write
Write
Write
Write
Write
X
FF16
7016
5016
4116
2016
A716
7716
7116
Read status register
Clear status register
X
X
X
X
X
X
X
Read
X
SRD (Note 2)
(Note 3)
(Note 3)
WA0(Note 3)
Page program
WD0
Write
WA1
WD1
Write
Write
Write
Write
Read
BA (Note 4)
Block erase
D016
D016
Erase all unlock block
Lock bit program
Read lock bit status
X
BA
BA
D016
(Note 5)
6
D
Note 1: When a software command is input, the high-order byte of data (D
Note 2: SRD = Status Register Data
8 to D15) is ignored.
Note 3: WA = Write Address, WD = Write Data
WA and WD must be set sequentially from 0016 to FE16 (byte address; however, an even address). The page size is
256 bytes.
Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)
Note 5: D6 corresponds to the block lock status. Block not locked when D6 = 1, block locked when D6 = 0.
Note 6: X denotes a given address in the user ROM area (that is an even address).
Table 1.22.1. List of Software Commands (CPU Rewrite Mode)
Read Array Command (FF16)
The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an
even address to be read is input in one of the bus cycles that follow, the content of the specified
address is read out at the data bus (D0–D15), 16 bits at a time.
The read array mode is retained intact until another command is written.
Read Status Register Command (7016)
When the command code “7016” is written in the first bus cycle, the content of the status register is
read out at the data bus (D0–D7) by a read in the second bus cycle.
The status register is explained in the next section.
Clear Status Register Command (5016)
This command is used to clear the bits SR3 to 5 of the status register after they have been set. These
bits indicate that operation has ended in an error. To use this command, write the command code
“5016” in the first bus cycle.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Page Program Command (4116)
Page program allows for high-speed programming in units of 256 bytes. Page program operation
starts when the command code “4116” is written in the first bus cycle. In the second bus cycle through
the 129th bus cycle, the write data is sequentially written 16 bits at a time. At this time, the addresses
A0-A7 need to be incremented by 2 from “0016” to “FE16.” When the system finishes loading the data,
it starts an auto write operation (data program and verify operation).
Whether the auto write operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto write operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to 0 at the same time the auto write operation starts and is returned to
1 upon completion of the auto write operation. In this case, the read status register mode remains
active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the
flash memory is reset using its reset bit.
____
The RY/BY status flag of the flash memory control register 0 is 0 during auto write operation and 1
when the auto write operation is completed as is the status register bit 7.
After the auto write operation is completed, the status register can be read out to know the result of the
auto write operation. For details, refer to the section where the status register is detailed.
Figure 1.22.4 shows an example of a page program flowchart.
Each block of the flash memory can be write protected by using a lock bit. For details, refer to the
section where the data protect function is detailed.
Additional writes to the already programmed pages are prohibited.
Start
Write 4116
n = 0
Write address n and
n = n + 2
data n
NO
n = FE16
YES
NO
RY/BY status flag
= 1?
YES
Check full status
Page program
completed
Figure 1.22.4. Page program flowchart
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows to the block address of a flash memory block, the system initiates
an auto erase (erase and erase verify) operation.
Whether the auto erase operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto erase operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned
to 1 upon completion of the auto erase operation. In this case, the read status register mode remains
active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the
flash memory is reset using its reset bit.
____
The RY/BY status flag of the flash memory control register 0 is 0 during auto erase operation and 1
when the auto erase operation is completed as is the status register bit 7.
After the auto erase operation is completed, the status register can be read out to know the result of
the auto erase operation. For details, refer to the section where the status register is detailed.
Figure 1.22.5 shows an example of a block erase flowchart.
Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer
to the section where the data protect function is detailed.
Start
Write 2016
Write D016
Block address
NO
RY/BY status flag
= 1?
YES
Check full status check
Block erase
completed
Figure 1.22.5. Block erase flowchart
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Erase All Unlock Blocks Command (A716/D016)
By writing the command code “A716” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows, the system starts erasing blocks successively.
Whether the erase all unlock blocks command is terminated can be confirmed by reading the status
register or the flash memory control register 0, in the same way as for block erase. Also, the status
register can be read out to know the result of the auto erase operation.
When the lock bit disable bit of the flash memory control register 0 = 1, all blocks are erased no matter
how the lock bit is set. On the other hand, when the lock bit disable bit = 0, the function of the lock bit
is effective and only nonlocked blocks (where lock bit data = 1) are erased.
Lock Bit Program Command (7716/D016)
By writing the command code “7716” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows to the block address of a flash memory block, the system sets the
lock bit for the specified block to 0 (locked).
Figure 1.22.6 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit
data) can be read out by a read lock bit status command.
Whether the lock bit program command is terminated can be confirmed by reading the status register
or the flash memory control register 0, in the same way as for page program.
For details about the function of the lock bit and how to reset the lock bit, refer to the section where the
data protect function is detailed.
Start
Write 7716
Write D016
block address
NO
RY/BY status flag
= 1?
YES
NO
Lock bit program in
error
SR4 = 0?
YES
Lock bit program
completed
Figure 1.22.6. Lock bit program flowchart
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Read Lock Bit Status Command (7116)
By writing the command code “7116” in the first bus cycle and then the block address of a flash
memory block in the second bus cycle that follows, the system reads out the status of the lock bit of
the specified block on to the data (D6).
Figure 1.22.7 shows an example of a read lock bit program flowchart.
Start
Write 7116
Enter block address
(Note)
D6 = 0?
NO
YES
Blocks locked
Blocks not locked
Note: Data bus bit 6.
Figure 1.22.7. Read lock bit status flowchart
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Data Protect Function (Block Lock)
Each block in Figure 1.21.1 has a nonvolatile lock bit to specify that the block be protected (locked)
against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of
each block can be read out using the read lock bit status command.
Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash
memory control register 0’s lock bit disable bit is set.
(1) When the lock bit disable bit = 0, a specified block can be locked or unlocked by the lock bit status
(lock bit data). Blocks whose lock bit data = 0 are locked, so they are disabled against erase/write.
On the other hand, the blocks whose lock bit data = 1 are not locked, so they are enabled for erase/
write.
(2) When the lock bit disable bit = 1, all blocks are nonlocked regardless of the lock bit data, so they are
enabled for erase/write. In this case, the lock bit data that is 0 (locked) is set to 1 (nonlocked) after
erasure, so that the lock bit-actuated lock is removed.
Status Register
The status register indicates the operating status of the flash memory and whether an erase or program
operation has terminated normally or in an error. The content of this register can be read out by only
writing the read status register command (7016). Table 1.22.2 details the status register.
The status register is cleared by writing the Clear Status Register command (5016).
After a reset, the status register is set to “8016.”
Each bit in this register is explained below.
Write state machine (WSM) status (SR7)
After power-on, the write state machine (WSM) status is set to 1.
The write state machine (WSM) status indicates the operating status of the device. This status bit is
set to 0 during auto write or auto erase operation and is set to 1 upon completion of these operations.
Erase status (SR5)
The erase status informs the operating status of auto erase operation to the CPU. When an erase
error occurs, it is set to 1.
The erase status is reset to 0 when cleared.
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M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Program status (SR4)
The program status informs the operating status of auto write operation to the CPU. When a write
error occurs, it is set to 1.
The program status is reset to 0 when cleared.
When an erase command is in error (which occurs if the command entered after the block erase
command (2016) is not the confirmation command (D016), both the program status and erase status
(SR5) are set to 1.
When the program status or erase status = 1, the following commands entered by command write are
not accepted.
Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error):
(1) When the valid command is not entered correctly
(2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase
(2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is
entered, read array is assumed and the command that has been set up in the first bus cycle is
canceled.
Block status after program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,
“9016” is output; and when excessive data is written, “8816” is output.
Table 1.22.2. Definition of each bit in status register
Definition
Each bit of
SRD
Status name
"1"
Ready
-
"0"
Busy
-
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Write state machine (WSM) status
Reserved
Erase status
Terminated normally
Terminated in error
Program status
Block status after program
Reserved
Terminated normally
Terminated in error
Terminated normally
Terminated in error
-
-
-
-
-
-
Reserved
Reserved
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Full Status Check
By performing full status check, it is possible to know the execution results of erase and program
operations. Figure 1.22.8 shows a full status check flowchart and the action to be taken when each
error occurs.
Read status register
YES
Execute the clear status register command (5016
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
)
Command
sequence error
SR4=1 and SR5
=1 ?
NO
NO
NO
Block erase error
Should a block erase error occur, the block in error
cannot be used.
SR5=0?
YES
Program error (page
or lock bit)
Execute the read lock bit status command (7116)
SR4=0?
YES
to see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be
used.
NO
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
Program error
(block)
SR3=0?
YES
End (block erase, program)
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase,
erase all unlock blocks and lock bit program commands is accepted. Execute the
clear status register command (5016) before executing these commands.
Figure 1.22.8. Full status check flowchart and remedial procedure for errors
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions To Inhibit Rewriting Flash Memory Version
Functions To Inhibit Rewriting Flash Memory Version
To prevent the contents of the flash memory version from being read out or rewritten easily, the device
incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for
use in standard serial I/O mode.
ROM code protect function
The ROM code protect function reading out or modifying the contents of the flash memory version by
using the ROM code protect control address (0FFFFF16) during parallel I/O mode. Figure 1.23.1 shows
the ROM code protect control address (0FFFFF16). (This address exists in the user ROM area.)
If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents
of the flash memory version are protected against readout and modification. ROM code protect is imple-
mented in two levels. If level 2 is selected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is
selected by default.
If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the
contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,
the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/
O or some other mode to rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
Symbol
ROMCP
Address
0FFFFF16
When reset
FF16
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Bit name
Function
Always set this bit to 1.
Reserved bit
b3 b2
ROM code protect level
2 set bit (Note 1, 2)
ROMCP2
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
b5 b4
ROM code protect reset
bit (Note 3)
ROMCR
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
b7 b6
ROM code protect level
1 set bit (Note 1)
ROMCP1
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against
readout or modification in parallel input/output mode.
Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, since these bits cannot be changed in parallel input/
output mode, they need to be rewritten in serial input/output or some other mode.
Figure 1.23.1. ROM code protect control address
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions To Inhibit Rewriting Flash Memory Version
ID Code Check Function
Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID
code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they
match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID
code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316,
0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program which has had the ID code
preset at these addresses to the flash memory.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFDC16 to 0FFFDF16
0FFFE016 to 0FFFE316
0FFFE416 to 0FFFE716
0FFFE816 to 0FFFEB16
0FFFEC16 to 0FFFEF16
0FFFF016 to 0FFFF316
0FFFF416 to 0FFFF716
0FFFF816 to 0FFFFB16
0FFFFC16 to 0FFFFF16
BRK instruction vector
ID3 Address match vector
ID4 Single step vector
ID5 Watchdog timer vector
ID6 DBC vector
ID7 NMI vector
Reset vector
4 bytes
Figure 1.23.2. ID code store addresses
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Parallel I/O Mode (Flash Memory Version)
Parallel I/O Mode
In this mode, the M16C/62 (80-pin flash memory version) operates in a manner similar to the flash memory
M5M29FB/T800 from Mitsubishi. Since there are some differences with regard to the functions not avail-
able with the microcomputer and matters related to memory capacity, the M16C/62 (80-pin flash memory
version) cannot be programed by a programer for the flash memory.
Use an exclusive programer supporting M16C/62 (80-pin flash memory version) .
Refer to the instruction manual of each programer maker for the details of use.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.21.1 can be rewritten. Both
areas of flash memory can be operated on in the same way.
Program and block erase operations can be performed in the user ROM area. The user ROM area and its
blocks are shown in Figure 1.21.1.
The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0FE00016 through
0FFFFF16. Make sure program and block erase operations are always performed within this address
range. (Access to any location outside this address range is prohibited.)
In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area
has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory.
Therefore, using the device in standard serial input/output mode, you do not need to write to the boot
ROM area.
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Pin functions (Flash memory standard serial I/O mode)
Pin
Name
Power input
Description
Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin.
Connect to Vcc pin.
I/O
V
CC,VSS
CNVSS
CNVSS (BYTE)
RESET
I
I
Reset input
Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
X
IN
OUT
AVCC, AVSS
REF
Connect a ceramic resonator or crystal oscillator between XIN and
Clock input
I
XOUT pins. To input an externally generated clock, input it to XIN pin
X
Clock output
and open XOUT pin.
O
Connect AVSS to Vss and AVcc to Vcc, respectively.
Analog power supply input
Reference voltage input
V
Enter the reference voltage for AD from this pin.
I
I
I
I
I
I
P0
0
0
to P0
to P2
7
7
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input port P0
Input port P2
P2
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
P3
0
0
to P3
to P4
7
3
Input port P3
Input port P4
Input port P5
P4
P5
P56, P5
1 to P54,
7
Input "H" level signal.
P5
0
5
CE input
I
I
Input "L" level signal.
P5
EPM input
Input port P6
BUSY output
SCLK input
RxD input
Input "H" or "L" level signal or open.
BUSY signal output pin
Serial clock input pin
P6
0
to P63
I
P6
P6
P6
P6
4
5
6
7
O
I
Serial data input pin
I
Serial data output pin
TxD output
Input port P7
O
I
Input "H" or "L" level signal or open.
P7
P7
0
7
, P71, P7
6,
Input "H" or "L" level signal or open.
P8
P8
0
7
to P8
4, P8
6,
Input port P8
NMI input
I
I
P85
Connect this pin to Vcc.
Input "H" or "L" level signal or open.
P9
0
, P9
2 to P9
7
Input port P9
Input port P10
I
I
Input "H" or "L" level signal or open.
P10
0
to P10
7
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Mode setup method
Value
Vcc
Signal
CNVss
EPM
RESET
CE
Vss
Vss to Vcc
Vcc
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
61
62
63
P4
P5
P5
3
P0
P0
P0
P0
P0
6
5
4
3
2
39
38
CE
0
1
64
65
66
67
68
69
37
36
P5
P5
P5
P5
P5
P5
2
3
4
5
6
7
35
34
33
32
P0
P0
1
0
EPM
P10
P10
P10
7
6
5
/AN
/AN
/AN
7
6
5
/KI3
/KI2
/KI1
/CLKOUT
70
71
72
73
74
31
30
29
P6
0
/CTS
0/RTS
0
1
M16C/62 Group (80-pin version)
P104/AN4/KI0
P6
P6
1
/CLK
0
0
P10
P10
P10
3
2
1
/AN
/AN
/AN
3
2
1
2
/RxD
28
P6
P6
3
/TX
D
0
BUSY
27
26
4
/CTS
1
/RTS
/CTS0/CLKS1
AVSS
75
76
SCLK
P6
P6
5
/CLK
1
1
25
24
23
P10
0
/AN
0
RXD
6
/RxD
V
REF
77
78
79
80
P67/TXD1
T
XD
AVcc
/ADTRG/SIN
/ANEX1/SOUT
P7
P7
0
1
/TxD
2/SDA/TA0OUT
22
21
P9
7
4
4
/RxD
2/SCL/TA0IN/TB5IN
P96
P76/TA3OUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
V
SS
V
CC
Connect
oscillator
circuit.
Figure 1.25.1. Pin connections for serial I/O mode (1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Standard Serial I/O Mode
The standard serial I/O mode serially inputs and outputs the software commands, addresses and data
necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific
peripheral unit.
The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like
rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard
_____
serial I/O mode is started by clearing the reset with an “H” level signal at the P50 (CE) pin, an “L” signal at
________
the P55 (EPM) pin and an “H” level at the CNVss pin. (For the normal microprocessor mode, set CNVss to
“L”.)
This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if
the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used.
Figures 1.25.1 show the pin connections for the standard serial I/O mode. Serial data I/O uses four UART1
pins: CLK1, RxD1, TxD1 and RTS1 (BUSY).
The CLK1 pin is the transfer clock input pin and it inputs the external transfer clock. The TxD1 pin outputs
the CMOS signal. The RTS1 (BUSY) pin outputs an “L” level when reception setup ends and an “H” level
when the reception operation starts. Transmission and reception data is transferred serially in 8-byte
blocks.
In the standard serial I/O mode, only the user ROM area shown in Figure 1.21.1 can be rewritten, the boot
ROM area cannot.
The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code
does not match the content of the flash memory, the command sent from the peripheral unit (programmer)
is not accepted.
Function Overview (Standard Serial I/O Mode)
In the standard serial I/O mode, software commands, addresses and data are input and output between
the flash memory and an external device (peripheral unit, etc.) using a 4-wire clock synchronized serial I/
O (UART1). In reception, the software commands, addresses and program data are synchronized with
the rise of the transfer clock input to the CLK1 pin and input into the flash memory via the RxD1 pin.
In transmission, the read data and status are synchronized with the fall of the transfer clock and output to
the outside from the TxD1 pin.
The TxD1 pin is CMOS output. Transmission is in 8-bit blocks and LSB first.
When busy, either during transmission or reception, or while executing an erase operation or program,
the RTS1 (BUSY) pin is “H” level. Accordingly, do not start the next transmission until the RTS1 (BUSY)
pin is “L” level.
Also, data in memory and the status register can be read after inputting a software command. It is pos-
sible to check flash memory operating status or whether a program or erase operation ended success-
fully or in error by reading the status register.
Software commands and the status register are explained here following.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Software Commands
Table 1.25.1 lists software commands. In the standard serial I/O mode, erase operations, programs and
reading are controlled by transferring software commands via the RxD pin. Software commands are
explained here below.
Table 1.25.1. Software commands (Standard serial I/O mode)
When ID is
not verificate
Not
Control command
Page read
2nd byte 3rd byte 4th byte 5th byte 6th byte
Data
output to
259th
Address
(high)
Data
output
Data
output output
Data
Address
(middle)
1
2
FF16
4116
acceptable
byte
Page program
Data input
to 259th
byte
Address
(high)
Data
input
Data
input
Data
input
Address
(middle)
Not
acceptable
Address
(high)
D016
Address
(middle)
D016
Not
acceptable
Not
acceptable
Acceptable
3
4
5
6
7
Block erase
2016
A716
7016
5016
7116
Erase all unlocked blocks
Read status register
Clear status register
Read lockbit status
SRD1
output
SRD
output
Not
acceptable
Not
Address Lock bit
(high)
Address
(middle)
data
output
D016
acceptable
Address
(high)
Address
(middle)
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
8
9
Lockbit program
Lockbit enable
7716
7A16
7516
F516
FA16
10 Lockbit disable
To ID7
Address Address ID size
(middle)
Size
ID1
To
Address
(low)
Size
11 ID check function
12 Download function
(high)
Check-
sum
Data
Not
acceptable
(high)
input required
number
(low)
of times
Version
data output
to 9th byte
Data
output to
259th byte
Version Version Version Version
Version
data
output
Address
(middle)
Acceptable
13 Version data output function
14 Boot area output function
FB16
FC16
data
output
Address
(high)
data
output
Data
data
output output
Data Data
output output
data
Not
acceptable
output
Note1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note2: SRD refers to status register data. SRD1 refers to status register 1 data.
Note3: All commands can be accepted when the flash memory is totally blank.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Send the “FF16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
CLK1
A
8
to
A
16 to
RxD1
(M16C reception data)
FF16
A15
A23
TxD1
(M16C transmit data)
data0
data255
RTS1(BUSY)
Figure 1.25.2. Timing for page read
Read Status Register Command
This command reads status information. When the “7016” command code is sent in the 1st byte of the
transmission, the contents of the status register (SRD) specified in the 2nd byte of the transmission
and the contents of status register 1 (SRD1) specified in the 3rd byte of the transmission are read.
CLK1
RxD1
7016
(M16C reception data)
SRD
output
SRD1
output
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.25.3. Timing for reading the status register
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Clear Status Register Command
This command clears the bits (SR3–SR5) which are set when the status register operation ends in
error. When the “5016” command code is sent in the 1st byte of the transmission, the aforementioned
bits are cleared. When the clear status register operation ends, the RTS1 (BUSY) signal changes
from the “H” to the “L” level.
CLK1
RxD1
5016
(M16C reception data)
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.25.4. Timing for clearing the status register
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Send the “4116” command code in the 1st byte of the transmission.
(2) Send addresses A
(3) From the 4th byte onward, as write data (D
to A23 is input sequentially from the smallest address first, that page is automatically written.
8
to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
0
–D ) for the page (256 bytes) specified with addresses
7
A8
When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the “H” to
the “L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed with already programmed pages.
CLK1
RxD1
(M16C reception data)
A
8
to
A
16 to
4116
data0
data255
A
15
A23
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.25.5. Timing for the page program
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Send the “2016” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) Send the verify command code “D016” in the 4th byte of the transmission. With the verify com-
mand code, the erase operation will start for the specified block in the flash memory. Write the
highest address of the specified block for addresses A16 to A23.
When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. After block
erase ends, the result of the block erase operation can be known by reading the status register. For
more information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.
CLK1
RxD1
(M16C reception data)
A8 to
A15
A16 to
A23
2016
D016
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.25.6. Timing for block erasing
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Send the “A716” command code in the 1st byte of the transmission.
(2) Send the verify command code “D016” in the 2nd byte of the transmission. With the verify com-
mand code, the erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register. Each block can be erase-protected with the
lock bit. For more information, see the section on the data protection function.
CLK1
RxD1
(M16C reception data)
A716
D016
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.25.7. Timing for erasing all unlocked blocks
Lock Bit Program Command
This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program
command as explained here following.
(1) Send the “7716” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) Send the verify command code “D016” in the 4th byte of the transmission. With the verify com-
mand code, “0” is written for the lock bit of the specified block. Write the highest address of the
specified block for addresses A8 to A23.
When writing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. Lock bit status can
be read with the read lock bit status command. For information on the lock bit function, reset proce-
dure and so on, see the section on the data protection function.
CLK1
RxD1
(M16C reception data)
A
8
to
A
16 to
23
7716
D016
A
15
A
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.25.8. Timing for the lock bit program
217
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Send the “7116” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) The lock bit data of the specified block is output in the 4th byte of the transmission. Write the
highest address of the specified block for addresses A8 to A23.
CLK1
A
8
to
A
16 to
23
RxD1
(M16C reception data)
7116
A
15
A
TxD1
(M16C transmit data)
DQ6
RTS1(BUSY)
Figure 1.25.9. Timing for reading lock bit status
Lock Bit Enable Command
This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-
mand. The command code “7A16” is sent in the 1st byte of the serial transmission. This command only
enables the lock bit function; it does not set the lock bit itself.
CLK1
RxD1
7A16
(M16C reception data)
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.25.10. Timing for enabling the lock bit
218
Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Lock Bit Disable Command
This command disables the lock bit. The command code “7516” is sent in the 1st byte of the serial
transmission. This command only disables the lock bit function; it does not set the lock bit itself.
However, if an erase command is executed after executing the lock bit disable command, “0” (locked)
lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is
cancelled, the lock bit is enabled.
CLK1
RxD1
7516
(M16C reception data)
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.25.11. Timing for disabling the lock bit
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Send the “FA16” command code in the 1st byte of the transmission.
(2) Send the program size in the 2nd and 3rd bytes of the transmission.
(3) Send the check sum in the 4th byte of the transmission. The check sum is added to all data sent
in the 5th byte onward.
(4) The program to execute is sent in the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
CLK1
Program
data
RxD1
(M16C reception data)
Check
sum
Program
data
FA16
Data size (low)
TxD1
Data size (high)
(M16C transmit data)
RTS1(BUSY)
Figure 1.25.12. Timing for download
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Send the “FB16” command code in the 1st byte of the transmission.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
CLK1
RxD1
FB16
(M16C reception data)
TxD1
'V'
'E'
'R'
'X'
(M16C transmit data)
RTS1(BUSY)
Figure 1.25.13. Timing for version information output
Boot Area Output Command
This command outputs the control program stored in the boot area in one page blocks (256 bytes).
Execute the boot area output command as explained here following.
(1) Send the “FC16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
CLK1
RxD1
(M16C reception data)
A
8
to
A
16 to
FC16
A
15
A23
TxD1
(M16C transmit data)
data0
data255
RTS1(BUSY)
Figure 1.25.14. Timing for boot area output
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Mitsubishi microcomputers
M16C / 62 Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Send the “F516” command code in the 1st byte of the transmission.
(2) Send addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code in the 2nd, 3rd
and 4th bytes of the transmission respectively.
(3) Send the number of data sets of the ID code in the 5th byte.
(4) The ID code is sent in the 6th byte onward, starting with the 1st byte of the code.
CLK1
RxD1
ID size
ID1
ID7
F516
DF16
FF16
0F16
(M16C reception
data)
TxD1
(M16C transmit
data)
RTS1(BUSY)
Figure 1.25.15. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the peripheral unit and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral unit is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write
a program into the flash memory, which already has the ID code set for these addresses.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFDC16 to 0FFFDF16
0FFFE016 to 0FFFE316
0FFFE416 to 0FFFE716
0FFFE816 to 0FFFEB16
0FFFEC16 to 0FFFEF16
0FFFF016 to 0FFFF316
0FFFF416 to 0FFFF716
0FFFF816 to 0FFFFB16
0FFFFC16 to 0FFFFF16
BRK instruction vector
ID3 Address match vector
ID4 Single step vector
ID5 Watchdog timer vector
ID6 DBC vector
ID7 NMI vector
Reset vector
4 bytes
Figure 1.25.16. ID code storage addresses
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Data Protection (Block Lock)
Each of the blocks in Figure 1.25.17 have a nonvolatile lock bit that specifies protection (block lock)
against erasing/writing. A block is locked (writing “0” for the lock bit) with the lock bit program command.
Also, the lock bit of any block can be read with the read lock bit status command.
Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock
bit disable and lock enable bit commands.
(1) After the reset has been cancelled and the lock bit enable command executed, the specified block
can be locked/unlocked using the lock bit (lock bit data). Blocks with a “0” lock bit data are locked
and cannot be erased or written in. On the other hand, blocks with a “1” lock bit data are unlocked
and can be erased or written in.
(2) After the lock bit enable command has been executed, all blocks are unlocked regardless of lock bit
data status and can be erased or written in. In this case, lock bit data that was “0” before the block
was erased is set to “1” (unlocked) after erasing, therefore the block is actually unlocked with the
lock bit.
0C000016
Block 6 : 64K byte
0D000016
Block 5 : 64K byte
0E000016
Block 4 : 64K byte
0F000016
Flash memory
size
Block 3 : 32K byte
Flash memory
start address
0F800016
0FA00016
256K byte
0C000016
Block 2 : 8K byte
Block 1 : 8K byte
Block 0 : 16K byte
0FC00016
0FFFFF16
User ROM area
Figure 1.25.17. Blocks in the user area
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 1.25.2 gives the definition of each status register bit. After clearing the reset, the status register
outputs “8016”.
Table 1.25.2. Status register (SRD)
Definition
SRD0 bits
Status name
"1"
"0"
Write state machine (WSM) status
Reserved
Ready
Busy
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
-
-
Erase status
Terminated in error
Terminated normally
Program status
Block status after program
Reserved
Terminated in error
Terminated normally
SR4 (bit4)
SR3 (bit3)
Terminated in error
Terminated normally
SR2 (bit2)
-
-
-
-
-
-
Reserved
SR1 (bit1)
SR0 (bit0)
Reserved
Write State Machine (WSM) Status (SR7)
The write state machine (WSM) status indicates the operating status of the flash memory. When
power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase
operation, but it is set back to “1” when the operation ends.
Erase Status (SR5)
The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is
set to “1”. When the erase status is cleared, it is set to “0”.
Program Status (SR4)
The program status reports the operating status of the auto write operation. If a write error occurs, it is
set to “1”. When the program status is cleared, it is set to “0”.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode
Program Status After Program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,
“9016” is output; and when excessive data is written, “8816” is output.
If “1” is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked
blocks and lock bit program commands are not accepted. Before executing these commands, execute
the clear status register command (5016) and clear the status register.
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Appendix Standard Serial I/O Mode
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table 1.25.3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON
and the flag status is maintained even after the reset.
Table 1.25.3. Status register 1 (SRD1)
Definition
SRD1 bits
Status name
"1"
"0"
Boot update completed bit
Reserved
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
Not update
Update completed
-
-
Reserved
-
-
Checksum match bit
ID check completed bits
Match
SR12 (bit4)
SR11 (bit3)
Mismatch
00
01
10
11
Not verified
Verification mismatch
Reserved
SR10 (bit2)
Verified
Data receive time out
Reserved
SR9 (bit1)
SR8 (bit0)
Time out
-
Normal operation
-
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to the RAM or not, using the down-
load function.
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a program, is downloaded for execu-
tion using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.
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Appendix Standard Serial I/O Mode
Full Status Check
Results from executed erase and program operations can be known by running a full status check. Figure
1.25.18 shows a flowchart of the full status check and explains how to remedy errors which occur.
Read status register
YES
Execute the clear status register command (5016
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
)
Command
sequence error
SR4=1 and SR5
=1 ?
NO
NO
NO
Block erase error
Should a block erase error occur, the block in error
cannot be used.
SR5=0?
YES
Program error (page
or lock bit)
Execute the read lock bit status command (7116)
SR4=0?
YES
to see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be
used.
NO
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
Program error
(block)
SR3=0?
YES
End (block erase, program)
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase,
erase all unlock blocks and lock bit program commands is accepted. Execute the
clear status register command (5016) before executing these commands.
Figure 1.25.18. Full status check flowchart and remedial procedure for errors
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Appendix Standard Serial I/O Mode
Example Circuit Application for The Standard Serial I/O Mode
The below figure shows a circuit application for the standard serial I/O mode. Control pins will vary ac-
cording to peripheral unit (programmer), therefore see the peripheral unit (programmer) manual for more
information.
Clock input
BUSY output
Data input
CLK1
RTS1(BUSY)
R
XD1
T
XD1
Data output
M16C/62 (80-pin)
flash memory
version
CNVss
NMI
P5
0(CE)
P5
5(EPM)
(1) Control pins and external circuitry will vary according to peripheral unit (programmer). For
more information, see the peripheral unit (programmer) manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are switched via a
switch.
Figure 1.25.19. Example circuit application for the standard serial I/O mode
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Revision History
Version
Revision
date
Contents for change
REV. C4 Page 35, Figure 1.9.6
00.07.03
Note: Writing a value to an address after “1” is written to this bit returns the bit to
“0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Page 123, Figure 1.14.32, bit 5 of the SI/Oi control register (i=3, 4)
Transfer direction lect bit --->Transfer direction select bit
Page 123, Figure 1.14.32, Note 2
When using the port as an input/output port by setting the SI/Oi port select bit (i =
3, 4) to “1”, be sure to set the sync clock select bit to “1”.
--->
When using the port as an input/output port by setting the SI/Oi port select bit (i =
3, 4) to “0”, be sure to set the sync clock select bit to “1”.
M16C/62 Group (80-pin) data sheet
Revision history
228
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MITSUBISHI SEMICONDUCTORS
M16C/62 Group (80-pin) Specification REV.C4
July First Edition 2000
Editioned by
Committee of editing of Mitsubishi Semiconductor
Published by
Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©2000 MITSUBISHI ELECTRIC CORPORATION
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