M306NKFHTGP [RENESAS]
Renesas MCU; 瑞萨MCU型号: | M306NKFHTGP |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | Renesas MCU |
文件: | 总84页 (文件大小:578K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Under development
This document is under development and its contents are subject to change
M16C/6N Group (M16C/6NK, M16C/6NM)
REJ03B0058-0210
Rev.2.10
Renesas MCU
Aug 25, 2006
1. Overview
The M16C/6N Group (M16C/6NK, M16C/6NM) of MCUs are built using the high-performance silicon gate
CMOS process using the M16C/60 Series CPU core and are packaged in 100-pin and 128-pin plastic
molded LQFP. These MCUs operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Being
equipped with two CAN (Controller Area Network) modules in the M16C/6N Group (M16C/6NK, M16C/6NM),
the MCU is suited to drive automotive and industrial control systems. The CAN modules comply with the 2.0B
specification. In addition, this MCU contains a multiplier and DMAC which combined with fast instruction
processing capability, makes it suitable for control of various OA, communication equipment which requires
high-speed arithmetic/logic operations.
1.1 Applications
• Car audio and industrial control systems, other (Normal-ver. product)
• Automotive, industrial control systems and other automobile, other (T/V-ver. product)
Specifications written in this manual are believed to be accurate, but are not
guaranteed to be entirely free of error. Specifications in this manual may be
changed for functional or performance improvements. Please make sure your
manual is the latest edition.
Rev.2.10 Aug 25, 2006 page 1 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
1.2 Performance Overview
Tables 1.1 and 1.2 list the Functions and Specifications for M16C/6N Group (M16C/6NK, M16C/6NM).
Table 1.1 Functions and Specifications for M16C/6N Group (100-pin Version: M16C/6NK)
Specification
Item
Normal-ver.
91 instructions
T/V-ver.
CPU
Number of fundamental
instructions
Minimum instruction
execution time
Operating mode
41.7 ns (f(BCLK) = 24 MHz,
50.0 ns (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Single-chip, memory expansion, Single-chip mode
and microprocessor modes
Address space
1 Mbyte
Memory capacity
Peripheral Ports
Refer to Table 1.3 Product Information
Input/Output: 87 pins, Input: 1 pin
Timer A: 16 bits ✕ 5 channels
Timer B: 16 bits ✕ 6 channels
Three-phase motor control circuit
3 channels
Function
Multifunction timers
Serial interfaces
Clock synchronous, UART, I2C-bus (1), IEBus
(2)
2 channels
Clock synchronous
A/D converter
D/A converter
DMAC
10-bit A/D converter: 1 circuit, 26 channels
8 bits ✕ 2 channels
2 channels
CRC calculation circuit
CAN module
Watchdog timer
Interrupts
CRC-CCITT
2 channels with 2.0B specification
15 bits ✕ 1 channel (with prescaler)
Internal: 32 sources, External: 9 sources
Software: 4 sources, Priority levels: 7 levels
Clock generation circuits 4 circuits
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with on-chip feedback resistor
Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function
Electrical
Characteristics
Supply voltage
VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Consumption Mask ROM 21 mA (f(BCLK) = 24 MHz,
-
current
PLL operation, no division)
Flash memory 23 mA (f(BCLK) = 24 MHz,
PLL operation, no division)
21 mA (f(BCLK) = 20 MHz,
PLL operation, no division)
Mask ROM 3 µA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)
Flash memory 0.8 µA (Stop mode, Topr = 25°C)
Flash Memory Programming and erasure voltage 3.0 0.3 V or 5.0 0.5 V
5.0 0.5 V
Version
I/O
Programming and erasure endurance 100 times
I/O withstand voltage
5.0 V
Characteristics Output current
5 mA
Operating Ambient Temperature
-40 to 85°C
T version: -40 to 85°C
V version: -40 to 125°C (option)
Device Configuration
Package
CMOS high-performance silicon gate
100-pin molded-plastic LQFP
NOTES:
1. I2C-bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
option: All options are on request basis.
Rev.2.10 Aug 25, 2006 page 2 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
Table 1.2 Functions and Specifications for M16C/6N Group (128-pin Version: M16C/6NM)
Specification
Item
Normal-ver.
91 instructions
T/V-ver.
CPU
Number of fundamental
instructions
Minimum instruction
execution time
Operating mode
41.7 ns (f(BCLK) = 24 MHz,
50.0 ns (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Single-chip, memory expansion, Single-chip mode
and microprocessor modes
Address space
1 Mbyte
Memory capacity
Peripheral Ports
Refer to Table 1.3 Product Information
Input/Output: 113 pins, Input: 1 pin
Timer A: 16 bits ✕ 5 channels
Timer B: 16 bits ✕ 6 channels
Three-phase motor control circuit
3 channels
Function
Multifunction timers
Serial interfaces
Clock synchronous, UART, I2C-bus (1), IEBus
(2)
4 channels
Clock synchronous
A/D converter
D/A converter
DMAC
10-bit A/D converter: 1 circuit, 26 channels
8 bits ✕ 2 channels
2 channels
CRC calculation circuit
CAN module
Watchdog timer
Interrupts
CRC-CCITT
2 channels with 2.0B specification
15 bits ✕ 1 channel (with prescaler)
Internal: 34 sources, External: 12 sources
Software: 4 sources, Priority levels: 7 levels
Clock generation circuits 4 circuits
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with on-chip feedback resistor
Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function
Electrical
Characteristics
Supply voltage
VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Consumption Mask ROM 21 mA (f(BCLK) = 24 MHz,
-
current
PLL operation, no division)
Flash memory 23 mA (f(BCLK) = 24 MHz,
PLL operation, no division)
21 mA (f(BCLK) = 20 MHz,
PLL operation, no division)
Mask ROM 3 µA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)
Flash memory 0.8 µA (Stop mode, Topr = 25°C)
Flash Memory Programming and erasure voltage 3.0 0.3 V or 5.0 0.5 V
5.0 0.5 V
Version
I/O
Programming and erasure endurance 100 times
I/O withstand voltage
5.0 V
Characteristics Output current
5 mA
Operating Ambient Temperature
-40 to 85°C
T version: -40 to 85°C
V version: -40 to 125°C (option)
Device Configuration
Package
CMOS high-performance silicon gate
128-pin molded-plastic LQFP
NOTES:
1. I2C-bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
option: All options are on request basis.
Rev.2.10 Aug 25, 2006 page 3 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
System clock generation circuit
A/D converter
(10 bits ✕ 8 channels
Expandable up to 26 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
Timer (16 bits)
On-chip oscillator
UART or
Clock synchronous serial I/O
(3 channels)
Output (timer A): 5
Input (timer B): 6
Clock synchronous serial I/O
(8 bits ✕ 4 channels) (4)
CRC calculation circuit (CCITT)
(Polynomial: X16+X12+X5+1)
CAN module
(2 channels)
Three-phase motor
control circuit
Watchdog timer
(15 bits)
M16C/60 Series CPU core
Memory
R0H
R1H
R0L
R1L
SB
USP
ISP
ROM (1)
RAM (2)
R2
R3
DMAC
(2 channels)
INTB
PC
FLG
A0
A1
Multiplier
D/A converter
(8 bits ✕ 2 channels)
FB
Port P11
Port P14
Port P13
Port P12
(3)
(3)
(3)
(3)
NOTES:
2
8
8
8
1: ROM size depends on MCU type.
2: RAM size depends on MCU type.
3: Ports P11 to P14 are only in the 128-pin version.
4: 8 bits ✕ 2 channels in the 100-pin version.
Figure 1.1 Block Diagram
Rev.2.10 Aug 25, 2006 page 4 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
1.4 Product Information
Table 1.3 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages.
Table 1.3 Product Information
Type No.
ROM Capacity RAM Capacity Package Type (2)
M306NKFHGP
As of Aug. 2006
Remarks
PLQP0100KB-A
PLQP0128KB-A
PLQP0100KB-A
PLQP0128KB-A
PLQP0100KB-A
PLQP0128KB-A
PLQP0100KB-A
PLQP0128KB-A
PLQP0100KB-A
PLQP0128KB-A
PLQP0100KB-A
PLQP0128KB-A
PLQP0100KB-A
PLQP0128KB-A
PLQP0100KB-A
PLQP0128KB-A
Normal-ver.
384 K + 4 Kbytes 31 Kbytes
512 K + 4 Kbytes 31 Kbytes
Flash
M306NMFHGP
M306NKFJGP
memory
version (1)
M306NMFJGP
M306NKFHTGP
M306NMFHTGP
M306NKFJTGP
M306NMFJTGP
M306NKFHVGP
M306NMFHVGP
M306NKFJVGP
M306NMFJVGP
M306NKME-XXXGP
M306NMME-XXXGP
M306NKMG-XXXGP
M306NMMG-XXXGP
(D): Under development
NOTES:
T-ver.
(D) 384 K + 4 Kbytes 31 Kbytes
(D)
512 K + 4 Kbytes 31 Kbytes
V-ver.
(D) 384 K + 4 Kbytes 31 Kbytes
(D)
(D) 512 K + 4 Kbytes 31 Kbytes
(D)
16
Normal-ver.
192 Kbytes
Kbytes
Mask
ROM
20
256 Kbytes
Kbytes
version
1. Data flash memory provides an additional 4 Kbytes of ROM capacity (block A).
2. The correspondence between new and old package types is as follows.
PLQP0100KB-A: 100P6Q-A
PLQP0128KB-A: 128P6Q-A
Type No. M30 6N K M G T XXX GP
Package type:
GP: Package PLQP0100KB-A (100P6Q-A)
PLQP0128KB-A (128P6Q-A)
ROM No.
Omitted on flash memory version
Characteristics
(no): Normal-ver.
T
V
: T-ver. (Automotive 85°C version)
: V-ver. (Automotive 125°C version)
ROM capacity:
E : 192 Kbytes
G: 256 Kbytes
H: 384 Kbytes
J : 512 Kbytes
Memory type:
M : Mask ROM version
F : Flash memory version
Shows the number of CAN module, pin count, etc.
6N Group
M16C Family
Figure 1.2 Type Number, Memory Size, and Package
Rev.2.10 Aug 25, 2006 page 5 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
1.5 Pin Assignments
Figures 1.3 and 1.4 show the Pin Assignment (Top View). Tables 1.4 to 1.8 list the List of Pin Names.
76
77
78
79
80
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
P1_2/D10
P1_1/D9
P1_0/D8
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_2/CLK2/TA1OUT/V
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
M16C/6N Group
(M16C/6NK)
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
31
30
VREF
AVCC
29
28
P9_7/ADTRG/SIN4
P9_6/ANEX1/CTX0/SOUT4
P9_5/ANEX0/CRX0/CLK4
27
26
NOTES:
1. P7_1 and P9_1 are N channel open-drain pins.
Package: PLQP0100KB-A (100P6Q-A)
2. Not available the bus control pins (except CLKOUT pin) in T/V-ver..
Figure 1.3 Pin Assignments (Top View) (1)
Rev.2.10 Aug 25, 2006 page 6 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
Table 1.4 List of Pin Names for 100-Pin Package (1)
Control
Pin
Interrupt
Pin
Analog CAN Module Bus Control
Pin No.
Port
Timer Pin
UART Pin
(1)
Pin
DA1
DA0
Pin
Pin
1
2
P9_4
P9_3
P9_2
P9_1
P9_0
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
3
SOUT3
4
SIN3
5
CLK3
6
BYTE
CNVSS
XCIN
7
8
P8_7
9
XCOUT P8_6
_____________
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NOTE:
RESET
XOUT
VSS
XIN
VCC1
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
P7_6
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
P5_5
P5_4
P5_3
P5_2
P5_1
P5_0
P4_7
P4_6
P4_5
P4_4
P4_3
P4_2
________
NMI
_________
INT2
ZP
_________
INT1
_________
INT0
___
TA4IN/U
TA4OUT/U
TA3IN
(SIN4)
CRX1
CTX1
TA3OUT
____
TA2IN/W
(SOUT4)
TA2OUT/W
(CLK4)
___
__________ __________
TA1IN/V
CTS2/RTS2
CLK2
TA1OUT/V
TA0IN/TB5IN RXD2/SCL2
TA0OUT
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
_________ _________ _________
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
__________ __________
CTS0/RTS0
_________
RDY/CLKOUT
ALE
___________
HOLD
___________
HLDA
BCLK
______
RD
__________________
WRH/BHE
_________ ______
WRL/WR
_______
CS3
_______
CS2
_______
CS1
_______
CS0
A19
A18
1. Not available the bus control pins (except CLKOUT pin; Pin No.37) in T/V-ver..
Rev.2.10 Aug 25, 2006 page 7 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
Table 1.5 List of Pin Names for 100-Pin Package (2)
Control
Pin
Interrupt
Pin
Analog CAN Module Bus Control
Pin No.
Port
Timer Pin
UART Pin
(1)
Pin
Pin
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
NOTE:
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A17
A16
A15
A14
A13
A12
A11
A10
A9
VCC2
VSS
P3_0
A8(/-/D7)
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
D15
_________
INT5
_________
INT4
D14
_________
INT3
D13
D12
D11
D10
D9
D8
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN7
D7
D6
D5
D4
D3
D2
D1
D0
______
P10_7 KI3
______
P10_6 KI2
AN6
______
P10_5 KI1
AN5
______
P10_4 KI0
P10_3
AN4
AN3
P10_2
AN2
P10_1
AN1
AVSS
P10_0
AN0
VREF
AVCC
______________
P9_7
P9_6
P9_5
SIN4
ADTRG
SOUT4
CLK4
ANEX1 CTX0
ANEX0 CRX0
1. Not available the bus control pins in T/V-ver..
Rev.2.10 Aug 25, 2006 page 8 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
64
63
62
61
60
59
58
57
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P11_7/SIN6
P11_6/SOUT6
P11_5/CLK6
P11_4
P11_3
P11_2/SOUT5
P11_1/SIN5
P11_0/CLK5
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
P12_5
P12_6
P12_7
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P13_0
56
55
P13_1
P13_2
P13_3
54
53
52
51
50
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P13_4
P13_5/INT6
P13_6/INT7
P13_7/INT8
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
M16C/6N Group
(M16C/6NM)
49
48
47
46
45
44
43
42
41
40
39
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
VSS
NOTES:
Package: PLQP0128KB-A (128P6Q-A)
1. P7_1 and P9_1 are N channel open-drain pins.
2. Not available the bus control pins (except CLKOUT pin) in T/V-ver..
Figure 1.4 Pin Assignments (Top View) (2)
Rev.2.10 Aug 25, 2006 page 9 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
Table 1.6 List of Pin Names for 128-Pin Package (1)
Control
Pin
Interrupt
Pin
Analog CAN Module Bus Control
Pin No.
Port
Timer Pin
UART Pin
(1)
Pin
Pin
Pin
1
2
VREF
AVCC
______________
3
P9_7
P9_6
P9_5
P9_4
P9_3
P9_2
P9_1
P9_0
P14_1
P14_0
SIN4
ADTRG
4
SOUT4
CLK4
ANEX1 CTX0
ANEX0 CRX0
DA1
5
6
TB4IN
7
TB3IN
TB2IN
TB1IN
TB0IN
DA0
8
SOUT3
SIN3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NOTE:
CLK3
BYTE
CNVSS
XCIN
P8_7
XCOUT P8_6
_____________
RESET
XOUT
VSS
XIN
VCC1
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
P7_6
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
VCC1
P6_6
VSS
________
NMI
_________
INT2
ZP
_________
INT1
_________
INT0
___
TA4IN/U
TA4OUT/U
TA3IN
(SIN4)
CRX1
CTX1
TA3OUT
____
TA2IN/W
(SOUT4)
TA2OUT/W
(CLK4)
___
__________ __________
TA1IN/V
CTS2/RTS2
CLK2
TA1OUT/V
TA0IN/TB5IN RXD2/SCL2
TA0OUT
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
CLK1
_________ _________ _________
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
__________ __________
CTS0/RTS0
_________
P13_7 INT8
_________
P13_6 INT7
_________
P13_5 INT6
P13_4
_________
P5_7
RDY/CLKOUT
1. Not available the bus control pins (except CLKOUT pin; Pin No.50) in T/V-ver..
Rev.2.10 Aug 25, 2006 page 10 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
Table 1.7 List of Pin Names for 128-Pin Package (2)
Control
Pin
Interrupt
Pin
Analog CAN Module Bus Control
Pin No.
Port
Timer Pin
UART Pin
(1)
Pin
Pin
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
NOTE:
P5_6
P5_5
P5_4
P13_3
P13_2
P13_1
P13_0
P5_3
P5_2
P5_1
P5_0
P12_7
P12_6
P12_5
P4_7
P4_6
P4_5
P4_4
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P12_4
P12_3
P12_2
P12_1
P12_0
ALE
___________
HOLD
___________
HLDA
BCLK
______
RD
__________________
WRH/BHE
_________ ______
WRL/WR
_______
CS3
_______
CS2
_______
CS1
_______
CS0
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
VCC2
VSS
P3_0
A8(/-/D7)
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
D15
_________
INT5
_________
INT4
D14
_________
INT3
D13
D12
D11
1. Not available the bus control pins in T/V-ver..
Rev.2.10 Aug 25, 2006 page 11 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
Table 1.8 List of Pin Names for 128-Pin Package (3)
Control
Pin
Interrupt
Pin
Analog CAN Module Bus Control
Pin No.
Port
Timer Pin
UART Pin
(1)
Pin
Pin
Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
P1_2
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
P1_1
P1_0
P0_7
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
SIN6
SOUT6
CLK6
SOUT5
SIN5
CLK5
______
P10_7 KI3
AN7
AN6
AN5
AN4
AN3
AN2
AN1
______
P10_6 KI2
______
P10_5 KI1
______
P10_4 KI0
P10_3
P10_2
P10_1
AVSS
P10_0
AN0
NOTE:
1. Not available the bus control pins in T/V-ver..
Rev.2.10 Aug 25, 2006 page 12 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
1.6 Pin Functions
Tables 1.9 to 1.11 list the Pin Functions.
Table 1.9 Pin Functions (100-pin and 128-pin Versions) (1)
Signal Name
Power supply VCC1, VCC2,
input
Pin Name
I/O Type
I
Description
Apply 3.0 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC2 = VCC1 (1)
VSS
.
Analog power AVCC, AVSS
I
Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
supply input
_____________
RESET
CNVSS
The MCU is in a reset state when applying “L” to the this pin.
Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1
to start up in microprocessor mode.
Reset input
CNVSS
I
I
(2)
Switches the data bus in external memory space. The data bus
is 16-bit long when the this pin is held “L” and 8-bit long when
the this pin is held “H”. Set it to either one. Connect this pin to
VSS when single-chip mode.
External data BYTE
bus width
select input
I
(2)
Inputs and outputs data (D0 to D7) when these pins are set as
the separate bus.
Inputs and outputs data (D8 to D15) when external 16-bit data
bus is set as the separate bus.
Bus control
pins
D0 to D7
I/O
I/O
(3)
D8 to D15
Output address bits (A0 to A19).
A0 to A19
O
Input and output data (D0 to D7) and output address bits (A0 to
A7) by time-sharing when external 8-bit data bus are set as the
multiplexed bus.
A0/D0 to A7/D7
I/O
Input and output data (D0 to D7) and output address bits (A1 to
A8) by time-sharing when external 16-bit data bus are set as the
multiplexed bus.
A1/D0 to A8/D7
I/O
_______
_______
O
O
Output _C__S___0_ to _C__S___3_ signals. _C__S___0_ to _C__S___3_ are chip-select signals
to specify an external space.
CS0 to CS3
_________ ______
Output _W___R___L_ , W____R___H__, (_W___R__, _B__H___E__), _R__D__ signals. _W___R___L_ and _W___R___H__ or
WRL/WR
_________ ________
________
BHE, and _W___R__ can be switched by program.
WRH/BHE
______
_________
• _W___R___L_, WRH, and _R__D__ are selected
RD
________
The WRL signal becomes “L” by writing data to an even address
in an external memory space.
_________
The WRH signal becomes “L” by writing data to an odd address
in an external memory space.
_____
The RD pin signal becomes “L” by reading data in an external
memory space.
• _W___R__, _B__H___E__, and _R__D__ are selected
______
The WR signal becomes “L” by writing data in an external
memory space.
_____
The RD signal becomes “L” by reading data in an external
memory space.
________
The BHE signal becomes “L” by accessing an odd address.
______
Select WR, _B__H___E__, and _R__D__ for an external 8-bit data bus.
ALE is a signal to latch the address.
While the HOLD pin is held “L”, the MCU is placed in a hold
O
I
ALE
HOLD
__________
__________
state.
__________
In a hold state, _H__L__D___A__ outputs a “L” signal.
While applying a “L” signal to the _R__D___Y__ pin, the MCU is placed in
a wait state.
O
I
H___L__D___A
RDY
I: Input
O: Output
I/O: Input/Output
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. Connect to VSS in T/V-ver..
3. Not available the bus control pins in T/V-ver..
Rev.2.10 Aug 25, 2006 page 13 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
Table 1.10 Pin Functions (100-pin and 128-pin Versions) (2)
Signal Name
Main clock
input
Pin Name
I/O Type
I
Description
I/O pins for the main clock oscillation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (1)
XIN
.
Main clock
output
XOUT
XCIN
O
I
To use the external clock, input the clock from XIN and leave
XOUT open.
I/O pins for a sub clock oscillation circuit. Connect a crystal
Sub clock
input
oscillator between XCIN and XCOUT (1)
.
To use the external clock, input the clock from XCIN and leave
XCOUT open.
Sub clock
output
XCOUT
O
BCLK output (3) BCLK
O
O
I
Outputs the BCLK signal.
The clock of the same cycle as fC, f8, or f32 is output.
Clock output
CLKOUT
______
INT interrupt input NT0 to INT8 (2)
Input pins for the INT interrupt.
_______
_______
________
Input pin for the NMI interrupt.
NMI interrupt NMI
I
input
______
______
Input pins for the key input interrupt.
Key input
interrupt input
Timer A
KI0 to KI3
I
These are timer A0 to timer A4 I/O pins.
These are timer A0 to timer A4 input pins.
Input pin for the Z-phase.
TA0OUT to TA4OUT
TA0IN to TA4IN
ZP
I/O
I
I
These are timer B0 to timer B5 input pins.
These are Three-phase motor control output pins.
Timer B
TB0IN to TB5IN
____
I
___
___
Three-phase motor
control output
Serial interface
U, U, V, V, W, W
O
__________
__________
These are transmit control input pins.
These are receive control output pins.
These are transfer clock I/O pins.
These are serial data input pins.
I
O
I/O
I
CTS0 to CTS2
__________
__________
RTS0 to RTS2
CLK0 to CLK6 (2)
RXD0 to RXD2
SIN3 to SIN6 (2)
TXD0 to TXD2
SOUT3 to SOUT6 (2)
CLKS1
These are serial data input pins.
I
These are serial data output pins.
These are serial data output pins.
This is output pin for transfer clock output from multiple pins
function.
O
O
O
I2C mode
SDA0 to SDA2
SCL0 to SCL2
These are serial data I/O pins.
I/O
I/O
These are transfer clock I/O pins. (however, SCL2 for
the N-channel open drain output.)
Applies the reference voltage for the A/D converter and D/A
converter.
Reference
voltage input
A/D converter
VREF
I
I
Analog input pins for the A/D converter.
AN0 to AN7
AN0_0 to AN0_7
AN2_0 to AN2_7
_____________
This is an A/D trigger input pin.
ADTRG
ANEX0
I
This is the extended analog input pin for the A/D converter,
and is the output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.
These are the output pins for the D/A converter.
These are the input pins for the CAN module.
These are the output pins for the CAN module.
I/O
ANEX1
I
D/A converter
CAN module
DA0, DA1
CRX0, CRX1
CTX0, CTX1
O
I
O
I: Input
O: Output
I/O: Input/Output
NOTES:
1. _A__s__k___the _o__s__c__i_llator maker the oscillation characteristic.
2. INT6 to INT8, CLK5, CLK6, SIN5, SIN6, SOUT5, SOUT6 are only in the 128-pin version.
3. Not available the bus control pins in T/V-ver..
Rev.2.10 Aug 25, 2006 page 14 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
1. Overview
Table 1.11 Pin Functions (100-pin and 128-pin Versions) (3)
Signal Name
I/O port
Pin Name
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
I/O Type
I/O
Description
8-bit I/O ports in CMOS, having a direction register to select
an input or output.
Each pin is set as an input port or output port. An input port
can be set for a pull-up or for no pull-up in 4-bit unit by
program.
P4_0
P4_7
to
P5_0 to P5_7
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_4
P8_6, P8_7
(however P7_1 and P9_1 for the N-channel open drain
output.)
P9_0 to P9_7
P10_0 to P10_7
P11_0 to P11_7
P12_0 to P12_7
P13_0 to P13_7
(1)
(1)
(1)
(1)
P14_0, P14_1
P8_5
_______
Input port
I
Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I: Input
NOTE:
O: Output
I/O: Input/Output
1. Ports P11 to P14 are only in the 128-pin version.
Rev.2.10 Aug 25, 2006 page 15 of 81
REJ03B0058-02100
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB
configure a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2
R3
R0H (R0's high bits) R0L (R0's low bits)
R1H (R1's high bits) R1L (R1's low bits)
Data Registers (1)
R2
R3
A0
A1
FB
Address Registers (1)
Frame Base Registers (1)
b19
b15
b0
Interrupt Table Register
INTBH
INTBL
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19
b0
b0
Program Counter
PC
b15
b15
USP
ISP
SB
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
b0
FLG
Flag Register
b15
b8 b7
U
b0
C
IPL
I
O
B
S
Z
D
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
2.1 Data Registers (R0, R1, R2, and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is analogous to R2R0.
2.2 Address Registers (A0 and A1)
The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.2.10 Aug 25, 2006 page 16 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
2. Central Processing Unit (CPU)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
This flag is used exclusively for debugging purpose. During normal use, set to 0.
2.8.3 Zero Flag (Z Flag)
This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.
2.8.4 Sign Flag (S Flag)
This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is 0; register bank 1 is selected when this flag is 1.
2.8.6 Overflow Flag (O Flag)
This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is set
to 0 when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0; USP is selected when the U flag is 1.
The U flag is set to 0 when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt request is enabled.
2.8.10 Reserved Area
When white to this bit, write 0. When read, its content is undefined.
Rev.2.10 Aug 25, 2006 page 17 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
3. Memory
3. Memory
Figure 3.1 shows a Memory Map. The address space extends the 1 Mbyte from address 00000h to FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a
512-Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is
mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the
start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a
31-Kbyte internal RAM is allocated to the addresses from 00400h to 07FFFh. In addition to storing data, the
internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The Special Function Registers (SFRs) are allocated to the addresses from 00000h to 003FFh. Peripheral
function control registers are located here. Of the SFR, any area which has no functions allocated is reserved
for future use and cannot be accessed by user.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by
the JMPS or JSRS instruction. For details, refer to M16C/60, M16C/20, M16C/Tiny Series Software Manual.
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.
Use T/V-ver. in single-chip mode. The memory expansion and microprocessor modes cannot be used.
00000h
SFR
00400h
Internal RAM
XXXXX
h
FFE00h
FFFDCh
FFFFFh
Reserved area (1)
0F000h
Internal ROM
(data flash) (3)
Special page
vector table
0FFFFh
10000h
External area
Reserved area
External area
27000h
28000h
Undefined instruction
Overflow
BRK instruction
Internal RAM
Internal ROM (4)
Capacity Address XXXXX
h
Capacity Address YYYYYh
Address match
Single step
80000h
Reserved area (2)
16 Kbytes
20 Kbytes
31 Kbytes
043FF
053FF
07FFF
h
h
h
192 Kbytes
256 Kbytes
384 Kbytes
512 Kbytes
D0000
C0000
A0000
80000
h
h
h
h
Oscillation stop and re-oscillation
detection / watchdog timer
YYYYY
h
DBC
NMI
Reset
Internal ROM
(program area) (4)
FFFFFh
NOTES:
1. During memory expansion mode or microprocessor mode, cannot be used.
2. In memory expansion mode, cannot be used.
3. As for the flash memory version, 4-Kbyte space (block A) exists.
4. When using the masked ROM version, write nothing to internal ROM area.
5. Shown here is a memory map for the case where the PM10 bit in the PM1 register is 1 (block A enabled, addresses 10000h to
26FFFh for CS2 area) and the PM13 bit in the PM1 register is 1 (internal RAM area is expanded over 192 Kbytes).
* Not available memory expansion and microprocessor modes in T/V-ver..
And not available external area in T/V-ver..
Figure 3.1 Memory Map
Rev.2.10 Aug 25, 2006 page 18 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
An SFR (Special Function Register) is a control register for a peripheral function.
Tables 4.1 to 4.16 list the SFR Information.
Table 4.1 SFR Information (1) (5)
Address
0000h
0001h
0002h
0003h
Register
Symbol
After Reset
00000000b (CNVSS pin is "L")
00000011b (CNVSS pin is "H") (3)
00001000b
0004h
Processor Mode Register 0 (1)
PM0
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Processor Mode Register 1
PM1
CM0
CM1
CSR
AIER
PRCR
01001000b
00100000b
00000001b
XXXXXX00b
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register (4)
Address Match Interrupt Enable Register
Protect Register
XX000000b
Oscillation Stop Detection Register (2)
CM2
0X000000b
XXh
00XXXXXXb
00h
Watchdog Timer Start Register
Watchdog Timer Control Register
WDTS
WDC
00h
X0h
Address Match Interrupt Register 0
RMAD0
00h
00h
X0h
Address Match Interrupt Register 1
RMAD1
Chip Select Expansion Control Register (4)
PLL Control Register 0
CSE
PLC0
00h
0001X010b
XXX00000b
Processor Mode Register 2
DMA0 Source Pointer
PM2
XXh
XXh
XXh
SAR0
XXh
XXh
XXh
DMA0 Destination Pointer
DMA0 Transfer Counter
DMA0 Control Register
DAR0
XXh
XXh
TCR0
00000X00b
DM0CON
XXh
XXh
XXh
DMA1 Source Pointer
SAR1
XXh
XXh
XXh
DMA1 Destination Pointer
DMA1 Transfer Counter
DMA1 Control Register
DAR1
XXh
XXh
TCR1
00000X00b
DM1CON
X: Undefined
NOTES:
1. Bits PM00 and PM01 in the PM0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset.
* Effective when memory expansion and microprocessor modes (= Normal-ver.).
2. Bits CM20, CM21, and CM27 in the CM2 register do not change at oscillation stop detection reset.
3. CNVSS pin = H is not available in T/V-ver.. Do not set a value.
4. These registers are not available in T/V-ver.
5. Blank spaces are reserved. No access is allowed.
Rev.2.10 Aug 25, 2006 page 19 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.2 SFR Information (2) (2)
Address
0040h
0041h
0042h
0043h
0044h
Register
Symbol
After Reset
C01WKIC
C0RECIC
C0TRMIC
INT3IC
TB5IC
S5IC
TB4IC
U1BCNIC
TB3IC
U0BCNIC
C1RECIC
S4IC
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
CAN0/1 Wake-up Interrupt Control Register
CAN0 Successful Reception Interrupt Control Register
CAN0 Successful Transmission Interrupt Control Register
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
0045h
0046h
0047h
XXXXX000b
XXXXX000b
XXXXX000b
SI/O5 Interrupt Control Register (1)
Timer B4 Interrupt Control Register
UART1 Bus Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register
UART0 Bus Collision Detection Interrupt Control Register
CAN1 Successful Reception Interrupt Control Register
SI/O4 Interrupt Control Register
0048h
XX00X000b
INT5IC
C1TRMIC
S3IC
INT4IC
U2BCNIC
DM0IC
DM1IC
C01ERRIC
ADIC
KUPIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
INT7IC
TA3IC
INT6IC
TA4IC
TB0IC
S6IC
TB1IC
INT8IC
TB2IC
INT0IC
INT1IC
INT2IC
INT5 Interrupt Control Register
CAN1 Successful Transmission Interrupt Control Register
SI/O3 Interrupt Control Register
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
0049h
XX00X000b
004Ah
004Bh
004Ch
004Dh
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
DMA1 Interrupt Control Register
CAN0/1 Error Interrupt Control Register
A/D Conversion Interrupt Control Register
Key Input Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
004Eh
XXXXX000b
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
0057h
XX00X000b
INT7 Interrupt Control Register (1)
Timer A3 Interrupt Control Register
0058h
0059h
005Ah
XX00X000b
XXXXX000b
XXXXX000b
INT6 Interrupt Control Register (1)
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
SI/O6 Interrupt Control Register (1)
Timer B1 Interrupt Control Register
005Bh
XX00X000b
INT8 Interrupt Control Register (1)
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
INT2 Interrupt Control Register
XXXXX000b
XX00X000b
XX00X000b
XX00X000b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 0: Identifier / DLC
CAN0 Message Box 0: Data Field
CAN0 Message Box 0: Time Stamp
CAN0 Message Box 1: Identifier / DLC
CAN0 Message Box 1: Data Field
CAN0 Message Box 1: Time Stamp
X: Undefined
NOTES:
1. These registers exist only in the 128-pin version.
2. Blank spaces are reserved. No access is allowed.
Rev.2.10 Aug 25, 2006 page 20 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.3 SFR Information (3)
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 2: Identifier / DLC
CAN0 Message Box 2: Data Field
CAN0 Message Box 2: Time Stamp
CAN0 Message Box 3: Identifier / DLC
CAN0 Message Box 3: Data Field
CAN0 Message Box 3: Time Stamp
CAN0 Message Box 4: Identifier / DLC
CAN0 Message Box 4: Data Field
CAN0 Message Box 4: Time Stamp
CAN0 Message Box 5: Identifier / DLC
CAN0 Message Box 5: Data Field
CAN0 Message Box 5: Time Stamp
X: Undefined
Rev.2.10 Aug 25, 2006 page 21 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.4 SFR Information (4)
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 6: Identifier / DLC
CAN0 Message Box 6: Data Field
CAN0 Message Box 6: Time Stamp
CAN0 Message Box 7: Identifier / DLC
CAN0 Message Box 7: Data Field
CAN0 Message Box 7: Time Stamp
CAN0 Message Box 8: Identifier / DLC
CAN0 Message Box 8: Data Field
CAN0 Message Box 8: Time Stamp
CAN0 Message Box 9: Identifier / DLC
CAN0 Message Box 9: Data Field
CAN0 Message Box 9: Time Stamp
X: Undefined
Rev.2.10 Aug 25, 2006 page 22 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.5 SFR Information (5)
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 10: Identifier / DLC
CAN0 Message Box 10: Data Field
CAN0 Message Box 10: Time Stamp
CAN0 Message Box 11: Identifier / DLC
CAN0 Message Box 11: Data Field
CAN0 Message Box 11: Time Stamp
CAN0 Message Box 12: Identifier / DLC
CAN0 Message Box 12: Data Field
CAN0 Message Box 12: Time Stamp
CAN0 Message Box 13: Identifier / DLC
CAN0 Message Box 13: Data Field
CAN0 Message Box 13: Time Stamp
X: Undefined
Rev.2.10 Aug 25, 2006 page 23 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.6 SFR Information (6) (1)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 14: Identifier /DLC
CAN0 Message Box 14: Data Field
CAN0 Message Box 14: Time Stamp
CAN0 Message Box 15: Identifier /DLC
CAN0 Message Box 15: Data Field
CAN0 Message Box 15: Time Stamp
CAN0 Global Mask Register
C0GMR
CAN0 Local Mask A Register
CAN0 Local Mask B Register
C0LMAR
C0LMBR
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
Rev.2.10 Aug 25, 2006 page 24 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.7 SFR Information (7) (2)
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
Register
Symbol
After Reset
Flash Memory Control Register 1 (1)
Flash Memory Control Register 0 (1)
Address Match Interrupt Register 2
FMR1
0X00XX0Xb
FMR0
00000001b
00h
00h
X0h
XXXXXX00b
00h
RMAD2
AIER2
RMAD3
Address Match Interrupt Enable Register 2
Address Match Interrupt Register 3
00h
X0h
X: Undefined
NOTES:
1. These registers are included in the flash memory version. Cannot be accessed by users in the mask ROM version.
2. Blank spaces are reserved. No access is allowed.
Rev.2.10 Aug 25, 2006 page 25 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.8 SFR Information (8) (3)
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
Register
Symbol
TBSR
After Reset
000XXXXXb
Timer B3, B4, B5 Count Start Flag
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
Timer A1-1 Register
Timer A2-1 Register
Timer A4-1 Register
TA11
TA21
TA41
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
INVC0
INVC1
IDB0
IDB1
DTT
00111111b
00111111b
XXh
Timer B2 Interrupt Generation Frequency Set Counter
ICTB2
XXh
Interrupt Source Select Register 2
Timer B3 Register
IFSR2
TB3
X0000000b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Timer B4 Register
TB4
Timer B5 Register
TB5
SI/O6 Transmit/Receive Register (1)
S6TRR
SI/O6 Control Register (1)
SI/O6 Bit Rate Register (1)
S6C
01000000b
XXh
S6BRG
S3456TRR
TB3MR
TB4MR
TB5MR
IFSR0
SI/O3, 4, 5, 6 Transmit/Receive Register (2)
Timer B3 Mode Register
XXXX0000b
00XX0000b
00XX0000b
00XX0000b
00h
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Source Select Register 0
Interrupt Source Select Register 1
SI/O3 Transmit/Receive Register
IFSR1
S3TRR
00h
XXh
SI/O3 Control Register
SI/O3 Bit Rate Register
SI/O4 Transmit/Receive Register
S3C
S3BRG
S4TRR
01000000b
XXh
XXh
SI/O4 Control Register
SI/O4 Bit Rate Register
SI/O5 Transmit/Receive Register (1)
S4C
S4BRG
S5TRR
01000000b
XXh
XXh
SI/O5 Control Register (1)
SI/O5 Bit Rate Register (1)
S5C
01000000b
XXh
S5BRG
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
U2BRG
XXh
XXh
XXh
UART2 Transmit Buffer Register
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
U2C0
U2C1
00001000b
00000010b
XXh
UART2 Receive Buffer Register
U2RB
XXh
X: Undefined
NOTES:
1. These registers exist only in the 128-pin version.
2. Bits S5TRF and S6TRF in the S3456TRR register are used in the 128-pin version.
3. Blank spaces are reserved. No access is allowed.
Rev.2.10 Aug 25, 2006 page 26 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.9 SFR Information (9)
Address
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
Register
Symbol
After Reset
00h
CAN0 Message Control Register 0
CAN0 Message Control Register 1
CAN0 Message Control Register 2
CAN0 Message Control Register 3
CAN0 Message Control Register 4
CAN0 Message Control Register 5
CAN0 Message Control Register 6
CAN0 Message Control Register 7
CAN0 Message Control Register 8
CAN0 Message Control Register 9
CAN0 Message Control Register 10
CAN0 Message Control Register 11
CAN0 Message Control Register 12
CAN0 Message Control Register 13
CAN0 Message Control Register 14
CAN0 Message Control Register 15
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X0000001b
XX0X0000b
00h
X0000001b
00h
CAN0 Control Register
C0CTLR
C0STR
C0SSTR
C0ICR
CAN0 Status Register
CAN0 Slot Status Register
CAN0 Interrupt Control Register
CAN0 Extended ID Register
00h
00h
00h
00h
C0IDR
00h
XXh
XXh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
CAN0 Configuration Register
C0CONR
CAN0 Receive Error Count Register
CAN0 Transmit Error Count Register
C0RECR
C0TECR
CAN0 Time Stamp Register
C0TSR
CAN1 Message Control Register 0
CAN1 Message Control Register 1
CAN1 Message Control Register 2
CAN1 Message Control Register 3
CAN1 Message Control Register 4
CAN1 Message Control Register 5
CAN1 Message Control Register 6
CAN1 Message Control Register 7
CAN1 Message Control Register 8
CAN1 Message Control Register 9
CAN1 Message Control Register 10
CAN1 Message Control Register 11
CAN1 Message Control Register 12
CAN1 Message Control Register 13
CAN1 Message Control Register 14
CAN1 Message Control Register 15
C1MCTL0
C1MCTL1
C1MCTL2
C1MCTL3
C1MCTL4
C1MCTL5
C1MCTL6
C1MCTL7
C1MCTL8
C1MCTL9
C1MCTL10
C1MCTL11
C1MCTL12
C1MCTL13
C1MCTL14
C1MCTL15
00h
00h
00h
00h
00h
X0000001b
XX0X0000b
00h
X0000001b
00h
CAN1 Control Register
C1CTLR
C1STR
C1SSTR
C1ICR
CAN1 Status Register
CAN1 Slot Status Register
CAN1 Interrupt Control Register
CAN1 Extended ID Register
CAN1 Configuration Register
00h
00h
00h
00h
C1IDR
00h
XXh
XXh
00h
00h
00h
C1CONR
CAN1 Receive Error Count Register
CAN1 Transmit Error Count Register
C1RECR
C1TECR
CAN1 Time Stamp Register
C1TSR
00h
X: Undefined
Rev.2.10 Aug 25, 2006 page 27 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.10 SFR Information (10) (1)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
CAN0 Acceptance Filter Support Register
C0AFS
CAN1 Acceptance Filter Support Register
C1AFS
Peripheral Clock Select Register
CAN0/1 Clock Select Register
PCLKR
CCLKR
00h
00h
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN1 Message Box 0: Identifier / DLC
CAN1 Message Box 0: Data Field
CAN1 Message Box 0:Time Stamp
CAN1 Message Box 1: Identifier / DLC
CAN1 Message Box 1: Data Field
CAN1 Message Box 1:Time Stamp
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
Rev.2.10 Aug 25, 2006 page 28 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.11 SFR Information (11)
Address
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN1 Message Box 2: Identifier / DLC
CAN1 Message Box 2: Data Field
CAN1 Message Box 2: Time Stamp
CAN1 Message Box 3: Identifier / DLC
CAN1 Message Box 3: Data Field
CAN1 Message Box 3: Time Stamp
CAN1 Message Box 4: Identifier / DLC
CAN1 Message Box 4: Data Field
CAN1 Message Box 4: Time Stamp
CAN1 Message Box 5: Identifier / DLC
CAN1 Message Box 5: Data Field
CAN1 Message Box 5: Time Stamp
X: Undefined
Rev.2.10 Aug 25, 2006 page 29 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.12 SFR Information (12)
Address
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN1 Message Box 6: Identifier / DLC
CAN1 Message Box 6: Data Field
CAN1 Message Box 6: Time Stamp
CAN1 Message Box 7: Identifier / DLC
CAN1 Message Box 7: Data Field
CAN1 Message Box 7: Time Stamp
CAN1 Message Box 8: Identifier / DLC
CAN1 Message Box 8: Data Field
CAN1 Message Box 8: Time Stamp
CAN1 Message Box 9: Identifier / DLC
CAN1 Message Box 9: Data Field
CAN1 Message Box 9: Time Stamp
X: Undefined
Rev.2.10 Aug 25, 2006 page 30 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.13 SFR Information (13)
Address
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
0308h
0309h
030Ah
030Bh
030Ch
030Dh
030Eh
030Fh
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
0318h
0319h
031Ah
031Bh
031Ch
031Dh
031Eh
031Fh
0320h
0321h
0322h
0323h
0324h
0325h
0326h
0327h
0328h
0329h
032Ah
032Bh
032Ch
032Dh
032Eh
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN1 Message Box 10: Identifier / DLC
CAN1 Message Box 10: Data Field
CAN1 Message Box 10: Time Stamp
CAN1 Message Box 11: Identifier / DLC
CAN1 Message Box 11: Data Field
CAN1 Message Box 11: Time Stamp
CAN1 Message Box 12: Identifier / DLC
CAN1 Message Box 12: Data Field
CAN1 Message Box 12: Time Stamp
CAN1 Message Box 13: Identifier / DLC
CAN1 Message Box 13: Data Field
CAN1 Message Box 13: Time Stamp
X: Undefined
Rev.2.10 Aug 25, 2006 page 31 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.14 SFR Information (14) (1)
Address
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN1 Message Box 14: Identifier / DLC
CAN1 Message Box 14: Data Field
CAN1 Message Box 14: Time Stamp
CAN1 Message Box 15: Identifier / DLC
CAN1 Message Box 15: Data Field
CAN1 Message Box 15: Time Stamp
CAN1 Global Mask Register
C1GMR
CAN1 Local Mask A Register
CAN1 Local Mask B Register
C1LMAR
C1LMBR
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
Rev.2.10 Aug 25, 2006 page 32 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.15 SFR Information (15) (2)
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
Register
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After Reset
00h
0XXXXXXXb
00h
Count Start Flag
Clock Prescaler Reset Flag
One-Shot Start Flag
Trigger Select Register
Up/Down Flag
00h
00h (1)
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
Timer A0 Register
Timer A1 Register
Timer A2 Register
Timer A3 Register
Timer A4 Register
Timer B0 Register
Timer B1 Register
Timer B2 Register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
00h
00h
00h
00h
00XX0000b
00XX0000b
00XX0000b
XXXXXX00b
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
U0MR
U0BRG
00h
XXh
XXh
U0TB
UART0 Transmit Buffer Register
XXh
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
U0C0
U0C1
00001000b
00XX0010b
XXh
U0RB
UART0 Receive Buffer Register
XXh
00h
XXh
XXh
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
U1MR
U1BRG
U1TB
UART1 Transmit Buffer Register
XXh
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
U1C0
U1C1
00001000b
00XX0010b
XXh
XXh
X0000000b
U1RB
UART1 Receive Buffer Register
UART Transmit/Receive Control Register 2
UCON
DMA0 Request Source Select Register
DMA1 Request Source Select Register
DM0SL
DM1SL
00h
00h
XXh
XXh
XXh
CRC Data Register
CRC Input Register
CRCD
CRCIN
X: Undefined
NOTES:
1. Bits TA2P to TA4P in the UDF register are set to 0 after reset. However, the contents in these bits are undefined when read.
2. Blank spaces are reserved. No access is allowed.
Rev.2.10 Aug 25, 2006 page 33 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Registers (SFRs)
Table 4.16 SFR Information (16) (3)
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
Register
Symbol
AD0
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
A/D Register 0
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
D/A Register 0
ADCON0
ADCON1
DA0
00000XXXb
00h
00h
D/A Register 1
DA1
00h
00h
D/A Control Register
DACON
Port P14 Control Register (2)
Pull-Up Control Register 3 (2)
Port P0 Register
PC14
PUR3
P0
XX00XXXXb
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
Port P1 Register
P1
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
PD0
PD1
P2
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
Port P5 Register
P5
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
PD4
PD5
P6
Port P7 Register
P7
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
PD6
PD7
P8
XXh
XXh
Port P9 Register
P9
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
PUR0
00X00000b
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
Port P11 Register (2)
Port P10 Direction Register
Port P11 Direction Register (2)
Port P12 Register (2)
Port P13 Register (2)
Port P12 Direction Register (2)
Port P13 Direction Register (2)
Pull-up Control Register 0
00h
00000000b (1)
00000010b
00h
Pull-up Control Register 1
PUR1
03FDh
Pull-up Control Register 2
Port Control Register
PUR2
PCR
03FEh
03FFh
00h
X: Undefined
NOTES:
1. At hardware reset, the register is as follows:
00000000b where "L" is input to the CNVSS pin
00000010b where "H" is input to the CNVSS pin (CNVSS pin = H is not available in T/V-ver..)
At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
00000000b where the PM01 to PM00 bits in the PM0 register are 00b (single-chip mode)
00000010b where the PM01 to PM00 bits in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode)
* Not available memory expansion and microprocessor modes in T/V-ver..
2. These registers exist only in the128-pin version.
3. Blank spaces are reserved. No access is allowed.
Rev.2.10 Aug 25, 2006 page 34 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
5. Electrical Characteristics
5.1 Electrical Characteristics (Normal-ver.)
Table 5.1 Absolute Maximum Ratings
Condition
Symbol
Parameter
Rated Value
–0.3 to 6.5
Unit
V
VCC
AVCC
VI
Supply voltage (VCC1 = VCC2)
VCC = AVCC
VCC = AVCC
Analog supply voltage
–0.3 to 6.5
V
_____________
Input
–0.3 to VCC+0.3
V
RESET, CNVSS, BYTE,
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7,
P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, VREF, XIN
–0.3 to 6.5
V
V
P7_1, P9_1
Output
voltage
–0.3 to VCC+0.3
VO
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_0, P14_1, XOUT
P7_1, P9_1
–0.3 to 6.5
700
V
Pd
Power dissipation
Topr = 25°C
mW
°C
Topr
Operating ambient During MCU operation
–40 to 85
0 to 60
temperature
During flash memory program and
erase operation
Storage temperature
Tstg
–65 to 150
°C
NOTE:
1. Ports P11 to P14 are only in the 128-pin version.
Rev.2.10 Aug 25, 2006 page 35 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Table 5.2 Recommended Operating Conditions (1) (1)
Standard
Unit
Symbol
Parameter
Min.
3.0
Typ.
5.0
VCC
0
Max.
5.5
VCC
Supply voltage (VCC1 = VCC2)
V
V
V
V
V
AVCC
VSS
Analog supply voltage
Supply voltage
AVSS
VIH
Analog supply voltage
0
HIGH input
voltage
0.8 VCC
VCC
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,
P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0
to P13_7, P14_0, P14_1,
_____________
XIN, RESET, CNVSS, BYTE
V
V
6.5
VCC
0.8 VCC
0.8 VCC
P7_1, P9_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(During single-chip mode)
VCC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(Data input during memory expansion and microprocessor modes)
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,
P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to
0.5 VCC
0
VIL
LOW input
voltage
0.2 VCC
V
V
P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
_____________
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(During single-chip mode)
0.2 VCC
0.16 VCC
–10.0
V
V
0
0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(Data input during memory expansion and microprocessor modes)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to
P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0
to P13_7, P14_0, P14_1
IOH(peak)
HIGH peak
mA
output current
IOH(avg)
HIGH average
output current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to
P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0
to P13_7, P14_0, P14_1
–5.0
10.0
5.0
mA
mA
mA
IOL(peak)
LOW peak
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
IOL(avg)
LOW average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
output current
NOTES:
1. Referenced to VCC = 3.0 to 5.5 V at Topr = –40 to 85°C unless otherwise specified.
2. Average output current values during 100 ms period.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be 80 mA max.
The total IOL(peak) for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80 mA max.
The total IOH(peak) for ports P0, P1, and P2 must be –40 mA max.
The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be –40 mA max.
The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be –40 mA max.
The total IOH(peak) for ports P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be –40 mA max.
4. P11 to P14 are only in the 128-pin version.
Rev.2.10 Aug 25, 2006 page 36 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Table 5.3 Recommended Operating Conditions (2) (1)
Standard
Unit
Symbol
f(XIN)
Parameter
Min.
0
Typ.
Max.
16
Main clock input oscillation No wait Mask ROM version VCC = 3.0 to 5.5 V
MHz
(2) (3) (4)
frequency
Flash memory version
f(XCIN)
f(Ring)
f(PLL)
Sub clock oscillation frequency
On-chip oscillation frequency
PLL clock oscillation frequency
CPU operation clock
32.768
1
50
kHz
MHz
MHz
MHz
ms
16
0
24
24
20
f(BCLK)
tsu(PLL)
VCC = 3.0 to 5.5 V
PLL frequency synthesizer stabilization wait time
NOTES:
Main clock input oscillation frequency
(Mask ROM version / Flash memory
version: no wait)
1. Referenced to VCC = 3.0 to 5.5 V at Topr = –40 to 85°C unless
otherwise specified.
16.0
2. Relationship between main clock oscillation frequency and supply
voltage is shown right.
3. Execute program/erase of flash memory by VCC = 3.3 0.3 V or
VCC = 5.0 0.5 V.
4. When using 16 MHz and over, use PLL clock. PLL clock oscillation
frequency which can be used is 16 MHz, 20 MHz or 24 MHz.
0.0
3.0
5.5
VCC [V] (main clock: no division)
Rev.2.10 Aug 25, 2006 page 37 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Table 5.4 Electrical Characteristics (1) (1)
VCC = 5V
Standard
Symbol
VOH
Parameter
Measuring Condition
Unit
Min. Typ. Max.
VCC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –5 mA
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
V
CC-2.0
V
HIGH output
voltage
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –200 µA
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
V
CC-0.3
VOH
HIGH output
voltage
VCC
VCC
V
V
V
IOH = –1 mA
VOH
VOL
XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
3.0
3.0
HIGH output
voltage
IOH = –0.5 mA
With no load applied
With no load applied
IOL = 5 mA
XCOUT
2.5
1.6
HIGH output
voltage
2.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
LOW output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
0.45
V
VOL
IOL = 200 µA
LOW output
voltage
2.0
2.0
V
V
V
VOL
XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
IOL = 1 mA
IOL = 0.5 mA
With no load applied
With no load applied
LOW output
voltage
0
0
XCOUT
LOW output
voltage
Hysteresis
__________
HOLD, _R__D___Y__, TA0IN to TA4IN, TB0IN to TB5IN,
0.2
0.2
1.0
VT+-VT-
_________
_________ ________ ______________ __________
__________
INT0 to INT8, NMI, ADTRG, CTS0 to CTS2,
SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK6,
TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2,
______
______
SIN3 to SIN6
_____________
Hysteresis
HIGH input
current
2.5
5.0
V
µA
VT+-VT-
IIH
RESET
VI = 5 V
VI = 0 V
VI = 0 V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
____________
XIN, RESET, CNVSS, BYTE
µA
–5.0
IIL
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
LOW input
current
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
____________
XIN, RESET, CNVSS, BYTE
170
kΩ
Pull-up
resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
30
RPULLUP
50
RfXIN
RfXCIN
VRAM
XIN
XCIN
1.5
15
MΩ
MΩ
V
Feedback resistance
Feedback resistance
RAM retention voltage
2.0
At stop mode
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.
2. P11 to P14, _I_N__T__6__ to _I_N__T__8__, CLK5, CLK6, SIN5, and SIN6 are only in the 128-pin version.
Rev.2.10 Aug 25, 2006 page 38 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Standard
Table 5.5 Electrical Characteristics (2) (1)
Symbol
Parameter
Measuring Condition
Unit
mA
Min. Typ. Max.
ICC
Power supply
current
Mask ROM
f(BCLK) = 24 MHz,
PLL operation,
No division
21
37
In single-chip mode,
the output pins are
(VCC= 3.0 to 5.5 V) open and other pins
are VSS.
On-chip oscillation,
No division
1
mA
mA
Flash memory f(BCLK) = 24 MHz,
PLL operation,
23
39
No division
On-chip oscillation,
No division
1.8
15
25
25
mA
mA
mA
µA
Flash memory f(BCLK) = 10 MHz,
program
VCC = 5 V
Flash memory f(BCLK) = 10 MHz,
erase
VCC = 5 V
Mask ROM
f(BCLK) = 32 kHz,
Low power dissipation
(2)
mode, ROM
Flash memory f(BCLK) = 32 kHz,
Low power dissipation
25
µA
µA
(2)
mode, RAM
f(BCLK) = 32 kHz,
Low power dissipation
mode,
420
Flash memory (2)
Mask ROM
Flash memory Wait mode
f(BCLK) = 32 kHz,
Wait mode (3)
On-chip oscillation,
50
µA
µA
8.5
,
Oscillation capacity High
f(BCLK) = 32 kHz,
3.0
0.8
µA
µA
Wait mode (3)
,
Oscillation capacity Low
Stop mode,
3.0
Topr = 25°C
NOTES:
1. Referenced to VCC = 3.0 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.
2. This indicates the memory in which the program to be executed exists.
3. With one timer operated using fC32.
Rev.2.10 Aug 25, 2006 page 39 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Table 5.6 A/D Conversion Characteristics (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min. Typ. Max.
Bit
–
Resolution
VREF = VCC
10
3
LSB
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
INL
Integral
nonlinearity
error
10 bits
VREF
= VCC
= 5 V
LSB
LSB
7
5
VREF
= VCC
= 3.3 V
LSB
LSB
LSB
7
2
3
8 bits
VREF = AVCC = VCC = 3.3 V
ANEX0, ANEX1 input, AN0 to AN7 input,
–
Absolute
accuracy
10 bits
VREF
= VCC
= 5 V
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
LSB
LSB
7
5
VREF
= VCC
= 3.3 V
LSB
LSB
LSB
LSB
LSB
kΩ
7
2
8 bits
VREF = AVCC = VCC = 3.3 V
DNL
–
Differential nonlinearity error
Offset error
1
3
–
Gain error
3
10
RLADDER
tCONV
Resistor ladder
VREF = VCC
40
µs
3.3
10-bit conversion time,
sample & hold available
8-bit conversion time,
sample & hold available
Sampling time
VREF = VCC = 5 V, φAD = 10 MHz
µs
2.8
VREF = VCC = 5 V, φAD = 10 MHz
µs
V
tSAMP
VREF
0.3
2.0
0
Reference voltage
Analog input voltage
VCC
VIA
VREF
V
NOTES:
1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. φAD frequency must be 10 MHz or less.
3. When sample & hold is disabled, φAD frequency must be 250 kHz or more in addition to a limit of NOTE 2.
When sample & hold is enabled, φAD frequency must be 1 MHz or more in addition to a limit of NOTE 2.
Table 5.7 D/A conversion Characteristics (1)
Standard
Typ. Max.
Symbol
Parameter
Measuring Condition
Unit
Min.
–
Resolution
8
1.0
3
Bits
%
–
Absolute accuracy
tsu
µs
Setup time
RO
IVREF
4
10
20
kΩ
mA
Output resistance
(NOTE 2)
Reference power supply input current
1.5
NOTES:
1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h.
The resistor ladder of the A/D converter is not included. Also, the IVREF will flow even if VREF is disconnected by the
ADCON1 register.
Rev.2.10 Aug 25, 2006 page 40 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Table 5.8 Flash Memory Version Electrical Characteristics (1)
Standard
Unit
Symbol
Parameter
Min.
100
Typ.
Max.
(2)
-
-
-
-
Programming and erasure endurance
Word program time (VCC = 5.0 V)
Lock bit program time
cycle
µs
µs
s
25
25
200
200
Block erase time
(VCC = 5.0 V)
4-Kbyte block
8-Kbyte block
32-Kbyte block
64-Kbyte block
0.3
0.3
0.5
0.8
4
s
4
s
4
s
4
4 ✕ n (3)
-
Erase all unlocked blocks time
s
tps
Flash memory circuit stabilization wait time
µs
15
NOTES:
1. Referenced to VCC = 4.5 to 5.5 V, 3.0 to 3.6 V, Topr = 0 to 60°C unless otherwise specified.
2. Programming and erasure endurance refers to the number of times a block erase can be performed.
If the programming and erasure endurance is n (n = 100), each block can be erased n times.
For example, if a 4-Kbyte block A is erased after writing 1 word data 2,048 times, each to a different address,
this counts as one programming and erasure endurance. Data cannot be written to the same address more
than once without erasing the block (rewrite prohibited).
3. n denotes the number of blocks to erase.
Table 5.9 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
(at Topr = 0 to 60°C)
Flash Program, Erase Voltage
VCC = 3.3 0.3 V or 5.0 0.5 V
Flash Read Operation Voltage
VCC = 3.0 to 5.5 V
Table 5.10 Power Supply Circuit Timing Characteristics
Standard
Typ.
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
2
td(P-R)
td(R-S)
td(W-S)
Time for internal power supply stabilization during powering-on VCC = 3.0 to 5.5 V
STOP release time
ms
µs
µs
150
150
Low power dissipation mode wait mode release time
td(P-R)
Time for internal power supply
stabilization during powering-on
VCC
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
td(R-S)
STOP release time
(b) Wait mode release
td(W-S)
Low power dissipation mode
wait mode release time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
Figure 5.1 Power Supply Circuit Timing Diagram
Rev.2.10 Aug 25, 2006 page 41 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.11 External Clock Input (XIN Input)
Standard
Symbol
tC
Parameter
Unit
Min.
62.5
25
Max.
External clock input cycle time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
25
15
15
tf
External clock fall time
Table 5.12 Memory Expansion Mode and Microprocessor Mode
Standard
Unit
Symbol
Parameter
Min.
Max.
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
(NOTE 1) ns
(NOTE 2) ns
(NOTE 3) ns
Data input access time (when accessing multiplexed bus area)
40
30
40
0
ns
ns
ns
ns
ns
ns
Data input setup time
________
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
RDY input setup time
__________
HOLD input setup time
Data input hold time
________
th(BCLK-RDY)
th(BCLK-HOLD)
0
RDY input hold time
__________
0
HOLD input hold time
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 45 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 45 [ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
f(BCLK)
3. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 45 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
f(BCLK)
Rev.2.10 Aug 25, 2006 page 42 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.13 Timer A Input (Counter Input in Event Counter Mode)
Standard
Parameter
Unit
Symbol
Min.
100
40
Max.
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
40
Table 5.14 Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
400
200
200
Max.
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.15 Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
200
100
100
Max.
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.16 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
tw(TAH)
Parameter
Unit
Min.
100
100
Max.
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
ns
tw(TAL)
Table 5.17 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
tc(UP)
Parameter
Unit
Min.
2000
1000
1000
400
Max.
TAiOUT input cycle time
ns
ns
ns
ns
ns
tw(UPH)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
400
TAiOUT input hold time
Table 5.18 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
800
200
200
Max.
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
ns
ns
ns
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
Rev.2.10 Aug 25, 2006 page 43 of 81
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Under development
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.19 Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 5.20 Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.21 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.22 A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
_____________
tC(AD)
ADTRG input cycle time (trigger able minimum)
ns
ns
_____________
tw(ADL)
ADTRG input LOW pulse width
Table 5.23 Serial Interface
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
tc(CK)
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TXDi output delay time
TXDi hold time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
80
0
70
90
RXDi input setup time
RXDi input hold time
_______
Table 5.24 External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
_______
tw(INH)
tw(INL)
INTi input HIGH pulse width
ns
ns
_______
INTi input LOW pulse width
Rev.2.10 Aug 25, 2006 page 44 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.25 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.2
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
0
th(WR-AD)
(NOTE 1)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
15
25
25
40
Chip select output hold time (rin relation to BCLK)
ALE signal output delay time
4
–4
0
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
Data output delay time (in relation to BCLK)
(3)
Data output hold time (in relation to BCLK)
4
Data output delay time (in relation to WR)
(NOTE 2)
(NOTE 1)
(3)
th(WR-DB)
Data output hold time (rin relation to WR)
__________
td(BCLK-HLDA)
NOTES:
HLDA output delay time
40
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 40 [ns]
f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
R
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
DBi
C
by a circuit of the right figure.
P0
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
P1
P2
30 pF
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
NOTE:
1. P11 to P14 are only in the 128-pin version.
Figure 5.2 Port P0 to P14 Measurement Circuit
Rev.2.10 Aug 25, 2006 page 45 of 81
REJ03B0058-0210
Under development
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.26 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.2
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
0
th(WR-AD)
(NOTE 1)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
15
25
25
40
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
4
–4
0
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
Data output delay time (in relation to BCLK)
Data output hold time (rin relation to BCLK) (3)
Data output delay time (in relation to WR)
4
(NOTE 2)
(NOTE 1)
(3)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
HLDA output delay time
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n – 0.5) ✕ 109
n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
– 40 [ns]
f(BCLK)
When n = 1, f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
R
C
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
DBi
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
Rev.2.10 Aug 25, 2006 page 46 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.27 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.2
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
(NOTE 1)
(NOTE 1)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
25
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
4
(NOTE 1)
(NOTE 1)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
25
40
RD signal output hold time
0
0
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
4
(NOTE 2)
(NOTE 1)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
HLDA output delay time
40
15
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
–4
(NOTE 3)
(NOTE 4)
0
0
td(AD-WR)
tdZ(RD-AD)
8
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 40 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
f(BCLK)
3. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 25 [ns]
4. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 15 [ns]
Rev.2.10 Aug 25, 2006 page 47 of 81
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Under development
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
XIN input
tr
tr
tw(H)
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling edge
is selected)
t
h(TIN—UP) su(UP—TIN)
t
TAiIN input
(When count on rising edge
is selected)
Two-phase pulse input in event counter mode
tC(TA)
TAiIN input
tsu(TAIN—TAOUT)
tsu(TAIN—TAOUT)
tsu(TAOUT—TAIN)
TAiOUT input
tsu(TAOUT—TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
CLKi
tc(CK)
tw(CKH)
tw(CKL)
th(C—Q)
TXDi
RXDi
tsu(D—C)
td(C—Q)
th(C—D)
tw(INL)
INTi input
tw(INH)
Figure 5.3 Timing Diagram (1)
Rev.2.10 Aug 25, 2006 page 48 of 81
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
VCC = 5 V
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Common to setting with wait and setting without wait)
BCLK
t
su(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
Hi–Z
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
NOTE:
1. The above pins are set to high-impedance regardless of the input level of the BYTE pin,
the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.
Measuring conditions :
VCC = 5 V
Input timing voltage : Determined with VIL = 1.0 V, VIH = 4.0 V
Output timing voltage: Determined with VOL = 2.5 V, VOH = 2.5 V
Figure 5.4 Timing Diagram (2)
Rev.2.10 Aug 25, 2006 page 49 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
VCC = 5 V
(For setting with no wait)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
t
h(RD-AD)
-4ns.min
25ns.max
0ns.min
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
25ns.max
0ns.min
t
ac1(RD-DB)
(0.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
t
h(RD-DB)
40ns.min
0ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
25ns.max
-4ns.min
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
25ns.max
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-40)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.5 Timing Diagram (3)
Rev.2.10 Aug 25, 2006 page 50 of 81
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Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
h(RD-AD)
t
h(BCLK-ALE)
t
d(BCLK-ALE)
0ns.min
-4ns.min
25ns.max
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
25ns.max
0ns.min
t
ac2(RD-DB)
(1.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
h(RD-DB)
tSU(DB-RD)
0ns.min
40ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
-4ns.min
25ns.max
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
25ns.max
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-40)ns.min
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.6 Timing Diagram (4)
Rev.2.10 Aug 25, 2006 page 51 of 81
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Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
t
ac2(RD-DB)
(2.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DBi
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.7 Timing Diagram (5)
Rev.2.10 Aug 25, 2006 page 52 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
tac2(RD-DB)
(3.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DBi
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.8 Timing Diagram (6)
Rev.2.10 Aug 25, 2006 page 53 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplexed bus selection)
Read timing
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
25ns.max
th(RD-CS)
tcyc
(0.5 ✕ tcyc-10)ns.min
CSi
td(AD-ALE)
th(ALE-AD)
(0.5 ✕ tcyc-25)ns.min
(0.5 ✕ tcyc-15)ns.min
ADi
/DBi
Address
Address
Data input
tdZ(RD-AD)
8ns.max
th(RD-DB)
0ns.min
tac3(RD-DB)
tSU(DB-RD)
40ns.min
(1.5 ✕ tcyc-45)ns.max
td(AD-RD)
0ns.min
th(BCLK-AD)
4ns.min
td(BCLK-AD)
25ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
th(RD-AD)
25ns.max
(0.5 ✕ tcyc-10)ns.min
ALE
RD
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
Write timing
BCLK
th(BCLK-CS)
4ns.min
th(WR-CS)
tcyc
td(BCLK-CS)
25ns.max
(0.5 ✕ tcyc-10)ns.min
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
40ns.max
ADi
Address
Data output
Address
/DBi
td(DB-WR)
(1.5 ✕ tcyc-40)ns.min
th(WR-DB)
(0.5 ✕ tcyc-10)ns.min
td(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
td(AD-WR)
0ns.min
th(WR-AD)
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.9 Timing Diagram (7)
Rev.2.10 Aug 25, 2006 page 54 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
Read timing
tcyc
BCLK
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
t
h(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
ADi
/DBi
Data input
Address
t
h(RD-DB)
0ns.min
t
dZ(RD-AD)
t
ac3(RD-DB)
t
d(BCLK-AD)
8ns.max
t
SU(DB-RD)
40ns.min
td(AD-RD)
t
h(BCLK-AD)
4ns.min
25ns.max
(2.5 ✕ tcyc-45)ns.max
0ns.min
ADi
BHE
(no multiplex)
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
h(WR-CS)
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-DB)
4ns.min
t
d(BCLK-DB)
40ns.max
ADi
/DBi
Address
Data output
t
d(AD-ALE)
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-25)ns.min
(2.5 ✕ tcyc-40)ns.min
t
d(BCLK-AD)
25ns.max
t
h(BCLK-AD)
4ns.min
ADi
BHE
(no multiplex) td(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
td(AD-WR)
0ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.10 Timing Diagram (8)
Rev.2.10 Aug 25, 2006 page 55 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Table 5.28 Electrical Characteristics (1)
VCC = 3.3 V
Standard
Symbol
VOH
Parameter
Measuring Condition
Unit
Min. Typ. Max.
HIGH output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –1 mA
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0toP6_7, P7_0, P7_2toP7_7, P8_0toP8_4,
P8_6,P8_7,P9_0,P9_2toP9_7,P10_0toP10_7,
P11_0toP11_7,P12_0toP12_7, P13_0toP13_7,
P14_0, P14_1
V
CC-0.5
VCC
V
XOUT
HIGHPOWER
LOWPOWER
V
V
CC-0.5
CC-0.5
VOH
VOL
HIGH output
voltage
IOH = –0.1 mA
IOH = –50 µA
VCC
VCC
V
V
V
XCOUT HIGHPOWER
HIGH output
voltage
With no load applied
With no load applied
IOL = 1 mA
2.5
1.6
LOWPOWER
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0toP11_7,P12_0toP12_7, P13_0toP13_7,
P14_0, P14_1
LOW output
voltage
0.5
XOUT
HIGHPOWER
LOWPOWER
0.5
0.5
VOL
LOW output
voltage
IOL = 0.1 mA
V
V
V
IOL = 50 µA
XCOUT HIGHPOWER
0
0
LOW output
voltage
With no load applied
With no load applied
LOWPOWER
_________
HOLD, _R__D__Y__, TA0IN to TA4IN, TB0IN to TB5IN,
0.2
0.2
0.8
Hysteresis
VT+-VT-
I_N___T__0__ to INT8, NMI, ADTRG, C___T__S__0__ to CTS2,
________ _______ _____________
_________
SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK6,
TA0OUT to TA4OUT, KI0 to KI3,
_____
_____
RXD0 to RXD2, SIN3 to SIN6
_____________
Hysteresis
RESET
VT+-VT-
V
µA
1.8
4.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7,
IIH
HIGH input
current
VI = 3.3 V
VI = 0 V
VI = 0 V
P13_0 to P13_7, P14_0, P14_1,
____________
XIN, RESET, CNVSS, BYTE
IIL
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
LOW input
current
–4.0 µA
P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_0, P14_1,
____________
XIN, RESET, CNVSS, BYTE
RPULLUP
Pull-up
resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to
P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
500
50
kΩ
100
RfXIN
RfXCIN
VRAM
Feedback resistance
Feedback resistance
RAM retention voltage
XIN
XCIN
MΩ
MΩ
V
3.0
25
2.0
At stop mode
NOTES:
1. Referenced to VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.
________
2. P11 to P14, _I_N__T__6__ to INT8, CLK5, CLK6, SIN5, and SIN6 are only in the 128-pin version.
Rev.2.10 Aug 25, 2006 page 56 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.29 External Clock Input (XIN Input)
Standard
Symbol
tC
Parameter
Unit
Min.
62.5
25
Max.
External clock input cycle time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
25
15
15
tf
External clock fall time
Table 5.30 Memory Expansion Mode and Microprocessor Mode
Standard
Unit
Symbol
Parameter
Min.
Max.
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
(NOTE 1) ns
(NOTE 2) ns
(NOTE 3) ns
Data input access time (when accessing multiplexed bus area)
50
40
50
0
ns
ns
ns
ns
ns
ns
Data input setup time
________
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
RDY input setup time
__________
HOLD input setup time
Data input hold time
________
th(BCLK-RDY)
th(BCLK-HOLD)
0
RDY input hold time
__________
0
HOLD input hold time
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 60 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 60 [ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
f(BCLK)
3. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 60 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
f(BCLK)
Rev.2.10 Aug 25, 2006 page 57 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.31 Timer A Input (Counter Input in Event Counter Mode)
Standard
Parameter
Unit
Symbol
Min.
150
60
Max.
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
60
Table 5.32 Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
600
300
300
Max.
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.33 Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
300
150
150
Max.
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.34 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
tw(TAH)
Parameter
Unit
Min.
150
150
Max.
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
ns
tw(TAL)
Table 5.35 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
tc(UP)
Parameter
Unit
Min.
3000
1500
1500
600
Max.
TAiOUT input cycle time
ns
ns
ns
ns
ns
tw(UPH)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
600
TAiOUT input hold time
Table 5.36 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
2
Max.
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
µs
ns
ns
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
500
500
Rev.2.10 Aug 25, 2006 page 58 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.37 Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
60
300
120
120
tw(TBH)
tw(TBL)
Table 5.38 Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.39 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.40 A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
_____________
tC(AD)
ADTRG input cycle time (trigger able minimum)
ns
ns
_____________
tw(ADL)
ADTRG input LOW pulse width
Table 5.41 Serial Interface
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
tc(CK)
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TXDi output delay time
TXDi hold time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
160
0
100
90
RXDi input setup time
RXDi input hold time
_______
Table 5.42 External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
_______
tw(INH)
tw(INL)
INTi input HIGH pulse width
ns
ns
_______
INTi input LOW pulse width
Rev.2.10 Aug 25, 2006 page 59 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.43 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.11
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
0
th(WR-AD)
(NOTE 1)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
30
25
30
30
40
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
4
–4
0
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
Data output delay time (in relation to BCLK)
(3)
Data output hold time (in relation to BCLK)
4
Data output delay time (in relation to WR)
(NOTE 2)
(NOTE 1)
(3)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
NOTES:
HLDA output delay time
40
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 40 [ns]
f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
R
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
DBi
C
by a circuit of the right figure.
P0
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
P1
P2
30 pF
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
NOTE:
1. P11 to P14 are only in the 128-pin version.
Figure 5.11 Port P0 to P14 Measurement Circuit
Rev.2.10 Aug 25, 2006 page 60 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.44 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.11
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
0
th(WR-AD)
(NOTE 1)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
30
25
30
30
40
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
4
–4
0
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
Data output delay time (in relation to BCLK)
(3)
Data output hold time (in relation to BCLK)
4
Data output delay time (in relation to WR)
(NOTE 2)
(NOTE 1)
(3)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
HLDA output delay time
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n – 0.5) ✕ 109
n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
– 40 [ns]
f(BCLK)
When n = 1, f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
R
C
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
DBi
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
Rev.2.10 Aug 25, 2006 page 61 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.45 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.11
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
(NOTE 1)
(NOTE 1)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
50
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
4
(NOTE 1)
(NOTE 1)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
40
40
50
RD signal output hold time
0
0
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
4
(NOTE 2)
(NOTE 1)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
HLDA output delay time
40
25
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (rin relation to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
–4
(NOTE 3)
(NOTE 4)
0
0
td(AD-WR)
tdZ(RD-AD)
8
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 50 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
f(BCLK)
3. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 40 [ns]
4. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 15 [ns]
Rev.2.10 Aug 25, 2006 page 62 of 81
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 3.3 V
XIN input
tr
tr
tw(H)
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling edge
is selected)
t
h(TIN—UP) su(UP—TIN)
t
TAiIN input
(When count on rising edge
is selected)
Two-phase pulse input in event counter mode
tC(TA)
TAiIN input
tsu(TAIN—TAOUT)
tsu(TAIN—TAOUT)
tsu(TAOUT—TAIN)
TAiOUT input
tsu(TAOUT—TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
CLKi
tc(CK)
tw(CKH)
tw(CKL)
th(C—Q)
TXDi
RXDi
tsu(D—C)
td(C—Q)
th(C—D)
tw(INL)
INTi input
tw(INH)
Figure 5.12 Timing Diagram (1)
Rev.2.10 Aug 25, 2006 page 63 of 81
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 3.3 V
Memory Expansion Mode and Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Common to setting with wait and setting without wait)
BCLK
t
su(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
Hi–Z
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
NOTE:
1. The above pins are set to high-impedance regardless of the input level of the BYTE pin,
the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.
Measuring conditions :
VCC = 3.3 V
Input timing voltage : Determined with VIL = 0.6 V, VIH = 2.7 V
Output timing voltage: Determined with VOL = 1.65 V, VOH = 1.65 V
Figure 5.13 Timing Diagram (2)
Rev.2.10 Aug 25, 2006 page 64 of 81
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 3.3 V
Memory Expansion Mode and Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
t
h(RD-AD)
-4ns.min
30ns.max
0ns.min
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
30ns.max
0ns.min
t
ac1(RD-DB)
(0.5 ✕ tcyc-60)ns.max
Hi-Z
DBi
t
SU(DB-RD)
t
h(RD-DB)
50ns.min
0ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
30ns.max
-4ns.min
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
30ns.max
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-40)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.14 Timing Diagram (3)
Rev.2.10 Aug 25, 2006 page 65 of 81
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 3.3 V
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
t
h(RD-AD)
t
h(BCLK-ALE)
t
d(BCLK-ALE)
0ns.min
-4ns.min
30ns.max
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
30ns.max
0ns.min
t
ac2(RD-DB)
(1.5 ✕ tcyc-60)ns.max
Hi-Z
DBi
t
h(RD-DB)
tSU(DB-RD)
0ns.min
50ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
-4ns.min
30ns.max
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
30ns.max
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-40)ns.min
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.15 Timing Diagram (4)
Rev.2.10 Aug 25, 2006 page 66 of 81
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 3.3 V
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
d(BCLK-ALE)
30ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
30ns.max
t
ac2(RD-DB)
(2.5 ✕ tcyc-60)ns.max
Hi-Z
DBi
t
SU(DB-RD)
50ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-ALE)
30ns.max
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
30ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DBi
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.16 Timing Diagram (5)
Rev.2.10 Aug 25, 2006 page 67 of 81
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 3.3 V
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
d(BCLK-ALE)
30ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
30ns.max
tac2(RD-DB)
(3.5 ✕ tcyc-60)ns.max
Hi-Z
DBi
t
SU(DB-RD)
50ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
d(BCLK-ALE)
30ns.max
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
30ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DBi
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.17 Timing Diagram (6)
Rev.2.10 Aug 25, 2006 page 68 of 81
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Under development
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
VCC = 3.3 V
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting, external area access and multiplexed bus selection)
Read timing
BCLK
t
h(BCLK-CS)
t
d(BCLK-CS)
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
4ns.min
tcyc
40ns.max
CSi
t
d(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
t
h(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
ADi
/DBi
Address
Address
Data input
t
dZ(RD-AD)
8ns.max
t
h(RD-DB)
t
ac3(RD-DB)
tSU(DB-RD)
0ns.min
(1.5 ✕ tcyc-60)ns.max
50ns.min
t
d(AD-RD)
0ns.min
t
h(BCLK-AD)
t
d(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
t
h(BCLK-ALE)
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
40ns.max
-4ns.min
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
0ns.min
40ns.max
Write timing
BCLK
t
h(BCLK-CS)
t
h(WR-CS)
(0.5 ✕ tcyc-10)ns.min
tcyc
t
d(BCLK-CS)
4ns.min
40ns.max
CSi
t
h(BCLK-DB)
t
d(BCLK-DB)
4ns.min
50ns.max
ADi
Address
Data output
Address
/DBi
t
d(DB-WR)
t
h(WR-DB)
t
d(AD-ALE)
(1.5 ✕ tcyc-50)ns.min
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-40)ns.min
t
d(BCLK-AD)
t
h(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
d(AD-WR)
t
h(WR-AD)
40ns.max
-4ns.min
0ns.min
(0.5 ✕ tcyc-10)ns.min
ALE
t
d(BCLK-WR)
t
h(BCLK-WR)
40ns.max
0ns.min
WR,WRL,
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.18 Timing Diagram (7)
Rev.2.10 Aug 25, 2006 page 69 of 81
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Under development
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
VCC = 3.3 V
Read timing
tcyc
BCLK
th(RD-CS)
th(BCLK-CS)
6ns.min
(0.5 ✕ tcyc-10)ns.min
td(BCLK-CS)
40ns.max
CSi
td(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
th(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
ADi
/DBi
Data input
Address
th(RD-DB)
tdZ(RD-AD)
8ns.max
0ns.min
tac3(RD-DB)
(2.5 ✕ tcyc-60)ns.max
td(BCLK-AD)
40ns.max
tSU(DB-RD)
50ns.min
td(AD-RD)
0ns.min
th(BCLK-AD)
4ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE)
40ns.max
th(RD-AD)
th(BCLK-ALE)
-4ns.min
(0.5 ✕ tcyc-10)ns.min
ALE
RD
th(BCLK-RD)
0ns.min
td(BCLK-RD)
40ns.max
Write timing
tcyc
BCLK
th(BCLK-CS)
th(WR-CS)
td(BCLK-CS)
40ns.max
4ns.min
(0.5 ✕ tcyc-10)ns.min
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
50ns.max
ADi
/DBi
Address
Data output
td(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
td(DB-WR)
(2.5 ✕ tcyc-50)ns.min
th(WR-DB)
(0.5 ✕ tcyc-10)ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
(no multiplex) td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5 ✕ tcyc-10)ns.min
td(AD-WR)
0ns.min
ALE
th(BCLK-WR)
0ns.min
td(BCLK-WR)
40ns.max
WR, WRL
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.19 Timing Diagram (8)
Rev.2.10 Aug 25, 2006 page 70 of 81
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This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5.2 Electrical Characteristics (T/V-ver.)
Table 5.46 Absolute Maximum Ratings
5. Electric Characteristics (T/V-ver.)
Symbol
Parameter
Condition
Rated Value
–0.3 to 6.5
Unit
V
VCC
AVCC
VI
Supply voltage (VCC1 = VCC2)
VCC = AVCC
VCC = AVCC
Analog supply voltage
–0.3 to 6.5
V
_____________
Input
–0.3 to VCC+0.3
V
RESET, CNVSS, BYTE,
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7,
P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, VREF, XIN
P7_1, P9_1
–0.3 to 6.5
V
V
Output
voltage
–0.3 to VCC+0.3
VO
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_0, P14_1, XOUT
P7_1, P9_1
–0.3 to 6.5
700
V
Pd
Power dissipation
Topr = 25°C
mW
°C
Topr
Operating ambient During MCU operation
temperature
T version: –40 to 85
V version: –40 to 125 (option)
0 to 60
During flash memory program and
erase operation
Storage temperature
Tstg
–65 to 150
°C
option: All options are on request basis.
NOTE:
1. Ports P11 to P14 are only in the 128-pin version.
Rev.2.10 Aug 25, 2006 page 71 of 81
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M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (T/V-ver.)
Table 5.47 Recommended Operating Conditions (1) (1)
Standard
Unit
Symbol
Parameter
Min.
4.2
Typ.
5.0
VCC
0
Max.
5.5
VCC
Supply voltage (VCC1 = VCC2)
V
V
V
V
V
AVCC
VSS
Analog supply voltage
Supply voltage
AVSS
VIH
Analog supply voltage
0
0.8 VCC
VCC
HIGH input
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
_____________
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
P7_1, P9_1
V
V
0.8 VCC
0
6.5
VIL
LOW input
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
0.2 VCC
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
_____________
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
mA
mA
mA
mA
–10.0
–5.0
10.0
5.0
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
NOTES:
HIGH peak
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to
P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0
to P13_7, P14_0, P14_1
output current
HIGH average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to
P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0
to P13_7, P14_0, P14_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
LOW peak
output current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
LOW average
output current
1. Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85°C unless otherwise specified.
2. Average output current values during 100 ms period.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be 80 mA max.
The total IOL(peak) for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80 mA max.
The total IOH(peak) for ports P0, P1, and P2 must be –40 mA max.
The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be –40 mA max.
The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be –40 mA max.
The total IOH(peak) for ports P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be –40 mA max.
4. P11 to P14 are only in the 128-pin version.
Rev.2.10 Aug 25, 2006 page 72 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (T/V-ver.)
Table 5.48 Recommended Operating Conditions (2) (1)
Standard
Unit
Symbol
f(XIN)
Parameter
Min.
0
Typ.
Max.
16
Main clock input oscillation No wait Flash memory
VCC = 4.2 to 5.5 V
VCC = 4.2 to 5.5 V
MHz
(2) (3) (4)
frequency
version
f(XCIN)
f(Ring)
f(PLL)
Sub clock oscillation frequency
On-chip oscillation frequency
PLL clock oscillation frequency
CPU operation clock
32.768
1
50
kHz
MHz
MHz
MHz
ms
16
0
20
20
20
f(BCLK)
tsu(PLL)
PLL frequency synthesizer stabilization wait time
NOTES:
Main clock input oscillation frequency
(Flash memory version: no wait)
1. Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85°C unless
otherwise specified.
16.0
2. Relationship between main clock oscillation frequency and supply
voltage is shown right.
3. Execute program/erase of flash memory by VCC = 5.0 0.5 V.
4. When using over 16 MHz, use PLL clock. PLL clock oscillation
frequency which can be used is 16 MHz or 20 MHz.
0.0
4.2
5.5
VCC [V] (main clock: no division)
Rev.2.10 Aug 25, 2006 page 73 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (T/V-ver.)
Standard
Table 5.49 Electrical Characteristics (1) (1)
Symbol
VOH
Parameter
Measuring Condition
Unit
V
Min. Typ. Max.
HIGH output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –5 mA
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
V
CC-2.0
VCC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
VOH
HIGH output
voltage
IOH = –200 µA
VCC
V
V
CC-0.3
XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
VCC
VCC
IOH = –1 mA
3.0
3.0
V
V
V
VOH
VOL
HIGH output
voltage
IOH = –0.5 mA
With no load applied
With no load applied
IOL = 5 mA
XCOUT
2.5
1.6
HIGH output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
2.0
LOW output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
IOL = 200 µA
VOL
LOW output
voltage
0.45
V
XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
VOL
IOL = 1 mA
IOL = 0.5 mA
With no load applied
With no load applied
_________
V
V
V
2.0
2.0
LOW output
voltage
XCOUT
0
0
LOW output
voltage
Hysteresis
_________
VT+-VT-
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT8,
1.0
0.2
0.2
______________ __________ __________
N___M___I_,_ ADTRG, CTS0 to CTS2, SCL0 to SCL2,
SDA0 to SDA2, CLK0 to CLK6, TA0OUT to TA4OUT,
______
______
KI0 to KI3, RXD0 to RXD2, SIN3 to SIN6
_____________
VT+-VT- Hysteresis
IIH
RESET
V
µA
2.5
5.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
VI = 5 V
VI = 0 V
VI = 0 V
HIGH input
current
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
IIL
LOW input
current
µA
–5.0
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
____________
XIN, RESET, CNVSS, BYTE
RPULLUP
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
Pull-up
resistance
50
kΩ
30
170
RfXIN
RfXCIN
VRAM
Feedback resistance
Feedback resistance
RAM retention voltage
MΩ
MΩ
V
XIN
1.5
15
XCIN
At stop mode
2.0
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified.
2. P11 to P14, _I_N__T__6__ to _I_N__T__8__, CLK5, CLK6, SIN5, and SIN6 are only in the 128-pin version.
Rev.2.10 Aug 25, 2006 page 74 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (T/V-ver.)
Table 5.50 Electrical Characteristics (2) (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min. Typ. Max.
ICC
Power supply
current
Flash memory f(BCLK) = 20 MHz,
PLL operation,
21
36
mA
Output pins are open
and other pins are VSS.
(VCC= 4.2 to 5.5 V)
No division
On-chip oscillation,
No division
1.8
15
25
25
mA
mA
mA
µA
Flash memory f(BCLK) = 10 MHz,
Program
Flash memory f(BCLK) = 10 MHz,
Erase VCC = 5 V
VCC = 5 V
Flash memory f(BCLK) = 32 kHz,
Low power dissipation
(2)
mode, RAM
f(BCLK) = 32 kHz,
Low power dissipation
mode,
420
µA
(2)
Flash memory
Flash memory On-chip oscillation,
Wait mode
50
µA
µA
f(BCLK) = 32 kHz,
8.5
(3)
Wait mode
,
Oscillation capacity High
f(BCLK) = 32 kHz,
3.0
0.8
µA
µA
(3)
Wait mode
,
Oscillation capacity Low
Stop mode,
3.0
Topr = 25°C
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified.
2. This indicates the memory in which the program to be executed exists.
3. With one timer operated using fC32.
Rev.2.10 Aug 25, 2006 page 75 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (T/V-ver.)
Table 5.51 A/D Conversion Characteristics (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min. Typ. Max.
Bit
–
Resolution
VREF = VCC
10
3
LSB
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
INL
integral
nonlinearity
erro
10 bits
VREF
= VCC
= 5 V
LSB
LSB
LSB
7
2
3
8 bits
VREF = AVCC = VCC = 5 V
ANEX0, ANEX1 input, AN0 to AN7 input,
–
Absolute
accuracy
10 bits
VREF
= VCC
= 5 V
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
LSB
LSB
LSB
LSB
LSB
kΩ
7
2
8 bits
VREF = AVCC = VCC = 5 V
DNL
–
Differential nonlinearity error
Offset error
1
3
–
Gain error
3
10
RLADDER
tCONV
Resistor ladder
VREF = VCC
40
µs
3.3
10-bit conversion time,
sample & hold available
8-bit conversion time,
sample & hold available
Sampling time
VREF = VCC = 5 V, φAD = 10 MHz
µs
2.8
VREF = VCC = 5 V, φAD = 10 MHz
µs
V
tSAMP
VREF
0.3
2.0
0
Reference voltage
Analog input voltage
VCC
VIA
VREF
V
NOTES:
1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. φAD frequency must be 10 MHz or less.
3. When sample & hold is disabled, φAD frequency must be 250 kHz or more in addition to a limit of NOTE 2.
When sample & hold is enabled, φAD frequency must be 1 MHz or more in addition to a limit of NOTE 2.
Table 5.52 D/A conversion Characteristics (1)
Standard
Symbol
Parameter
Measuring Condition
Unit
Min.
Max.
8
Typ.
–
Resolution
Bits
%
–
Absolute accuracy
1.0
3
tsu
µs
Setup time
RO
IVREF
4
10
20
1.5
kΩ
mA
Output tesistance
(NOTE 2)
Reference power supply input current
NOTES:
1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h.
The resistor ladder of the A/D converter is not included. Also, the IVREF will flow even if VREF is disconnected by the
ADCON1 register.
Rev.2.10 Aug 25, 2006 page 76 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (T/V-ver.)
Table 5.53 Flash Memory Version Electrical Characteristics (1)
Standard
Unit
Symbol
Parameter
Min.
100
Typ.
Max.
(2)
-
-
-
-
Programming and erasure endurance
Word program time (VCC = 5.0 V)
Lock bit program time
cycle
µs
µs
s
25
25
200
200
Block erase time
(VCC = 5.0 V)
4-Kbyte block
8-Kbyte block
32-Kbyte block
64-Kbyte block
0.3
0.3
0.5
0.8
4
s
4
s
4
s
4
4 ✕ n (3)
-
Erase all unlocked blocks time
s
tps
Flash memory circuit stabilization wait time
µs
15
NOTES:
1. Referenced to VCC = 4.5 to 5.5 V, Topr = 0 to 60°C unless otherwise specified.
2. Programming and erasure endurance refers to the number of times a block erase can be performed.
If the programming and erasure endurance is n (n = 100), each block can be erased n times.
For example, if a 4-Kbyte block A is erased after writing 1 word data 2,048 times, each to a different address,
this counts as one programming and erasure endurance. Data cannot be written to the same address more
than once without erasing the block (rewrite prohibited).
3. n denotes the number of blocks to erase.
Table 5.54 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
(at Topr = 0 to 60°C)
Flash Program, Erase Voltage
VCC = 5.0 0.5 V
Flash Read Operation Voltage
VCC = 4.2 to 5.5 V
Table 5.55 Power Supply Circuit Timing Characteristics
Standard
Typ.
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
2
td(P-R)
td(R-S)
td(W-S)
Time for internal power supply stabilization during powering-on VCC = 4.2 to 5.5 V
STOP release time
ms
µs
µs
150
150
Low power dissipation mode wait mode release time
td(P-R)
Time for internal power supply
stabilization during powering-on
VCC
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
td(R-S)
STOP release time
(b) Wait mode release
td(W-S)
Low power dissipation mode
wait mode release time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
Figure 5.20 Power Supply Circuit Timing Diagram
Rev.2.10 Aug 25, 2006 page 77 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (T/V-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.56 External Clock Input (XIN Input)
Standard
Symbol
Parameter
Unit
Min.
62.5
25
Max.
tC
External clock input cycle time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
25
15
15
tf
External clock fall time
Table 5.57 Timer A Input (Counter Input in Event Counter Mode)
Standard
Parameter
Unit
Symbol
Min.
100
40
Max.
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
40
Table 5.58 Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.59 Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.60 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
tw(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
ns
tw(TAL)
Table 5.61 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
tc(UP)
TAiOUT input cycle time
ns
ns
ns
ns
ns
tw(UPH)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
400
TAiOUT input hold time
Table 5.62 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
tc(TA)
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
ns
ns
ns
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
Rev.2.10 Aug 25, 2006 page 78 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (T/V-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.63 Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 5.64 Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.65 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.66 A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
_____________
tC(AD)
ADTRG input cycle time (trigger able minimum)
ns
ns
_____________
tw(ADL)
ADTRG input LOW pulse width
Table 5.67 Serial Interface
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
tc(CK)
CLKi Input cycle time
CLKi Input HIGH pulse width
CLKi Input LOW pulse width
TXDi output delay time
TXDi hold time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
80
0
70
90
RXDi input setup time
RXDi input hold time
_______
Table 5.68 External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
_______
tw(INH)
tw(INL)
INTi input HIGH pulse width
ns
ns
_______
INTi input LOW pulse width
Rev.2.10 Aug 25, 2006 page 79 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
5. Electric Characteristics (T/V-ver.)
VCC = 5 V
XIN input
tr
tr
tw(H)
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling edge
is selected)
t
h(TIN—UP) su(UP—TIN)
t
TAiIN input
(When count on rising edge
is selected)
Two-phase pulse input in event counter mode
tC(TA)
TAiIN input
tsu(TAIN—TAOUT)
tsu(TAIN—TAOUT)
tsu(TAOUT—TAIN)
TAiOUT input
tsu(TAOUT—TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
CLKi
tc(CK)
tw(CKH)
tw(CKL)
th(C—Q)
TXDi
RXDi
tsu(D—C)
td(C—Q)
th(C—D)
tw(INL)
INTi input
tw(INH)
Figure 5.21 Timing Diagram
Rev.2.10 Aug 25, 2006 page 80 of 81
REJ03B0058-0210
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
PLQP0100KB-A
Previous Code
MASS[Typ.]
0.6g
P-LQFP100-14x14-0.50
100P6Q-A / FP-100U / FP-100UV
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
76
50
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
13.9 14.0 14.1
13.9 14.0 14.1
1.4
Terminal cross section
A2
HD
HE
A
15.8 16.0 16.2
15.8 16.0 16.2
1.7
100
26
A1
bp
b1
c
0.1
0.05
0.15
1
25
Index mark
0.15 0.20 0.25
0.18
ZD
F
0.145
0.125
0.09
0.20
c1
0°
8°
e
0.5
y
*3
x
L
0.08
0.08
bp
e
x
y
L1
ZD
ZE
L
1.0
1.0
0.5
1.0
Detail F
0.35
0.65
L1
JEITA Package Code
RENESAS Code
PLQP0128KB-A
Previous Code
128P6Q-A
MASS[Typ.]
0.9g
P-LQFP128-14x20-0.50
HD
*1
D
102
65
103
64
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
Dimension in Millimeters
Reference
Symbol
Terminal cross section
Min Nom Max
D
E
19.9 20.0 20.1
13.9 14.0 14.1
1.4
A2
HD
HE
A
128
39
21.8 22.0 22.2
15.8 16.0 16.2
1.7
1
38
ZD
Index mark
A1
bp
b1
c
0.2
0.125
0.05
0.17 0.22 0.27
0.20
F
0.145
0.125
0.09
0.20
c1
L
0°
8°
L1
*3
y
bp
e
e
0.5
x
DetailF
x
0.10
0.10
y
ZD
ZE
L
0.75
0.75
0.5
0.35
0.65
L1
1.0
Rev.2.10 Aug 25, 2006 page 81 of 81
REJ03B0058-0210
REVISION HISTORY
M16C/6N Group (M16C/6NK, M16C/6NM) Data Sheet
Description
Summary
Rev.
Date
Page
1.00 Jul. 20, 2004
1.01 Nov. 01, 2004
–
–
First edition issued
Revised edition issued
* Revised parts and revised contents are as follows (except for expressional change).
Table 5.2 Recommended Operating Conditions (1)
30
31
• IOH(peak): Unit is revised from “V” to “mA”.
Table 5.3 Recommended Operating Conditions (2)
• NOTE 3: “VCC = 3.0 0.3 V” is revised to “VCC = 3.3 0.3 V”.
Table 5.4 IIH, IIL: “P3_3” is revised to “P3_7” in Parameter.
Table 5.9: VCC = 3.0 0.3 V” is revised to “VCC = 3.3 0.3 V” in Flash Program, Erase
Voltage.
32
35
1.10 Jul. 01, 2005
–
Revised edition issued
* The contents of product are revised. (T/V-ver. is added.)
* Revised parts and revised contents are as follows (except for expressional change).
Table 1.1 Performance outline of M16C/6N Group (100-pin Version: M16C/6NM)
• Performance outline of T/V-ver. is added.
2
3
5
Table 1.2 Performance outline of M16C/6N Group (128-pin Version: M16C/6NN)
• Performance outline of T/V-ver. is added.
Table 1.3 Product List is revised. (T/V-ver. is added.)
Figure 1.2 Type No., Memory Size, and Package: “Characteristics” is added.
FIgure 4.1 SFR Information (1): The value of After Reset in CM2 Register is revised.
Figure 4.7 SFR Information (7): NOTE 1 is revised.
13
19
32
Table 5.4 Electrical Characteristics (1)
• Measuring Condition of VOL is revised from “LOL = –200µA” to “LOL = 200µA”.
Table 5.5 Electrical Characteristics (2): Mask ROM (5th item)
• “f(XCIN)” is changed to “(f(BCLK)).
33
34
–
Table 5.6 A/D Conversion Characteristics: “Tolerance Level Impedance” is deleted.
Revised edition issued
2.10 Aug.25, 2006
* Memory expansion and microprocessor modes are added to Normal-ver..
* Electric Characteristics of T/V-ver. is added.
* Revised parts and revised contents are as follows (except for expressional change).
1.1 Applications: Comment of T/V-ver. is added.
1
2
Table 1.1 Fuictions and Specifications for M16C/6N Group (100-pin version)
• Operating Mode of Normal-ver. is revised.
3
5
Table 1.2 Fuictions and Specifications for M16C/6N Group (128-pin version)
• Operating Mode of Normal-ver. is revised.
Table 1.3 Product Information
• Status of development is revised and NOTES 1 and 2 are added.
Figure 1.3 Pin Assignments (1): Bus control pins are added and NOTE 2 is added.
Tables 1.4 and 1.5 List of Pin Names for 100-pin package (1)(2) are added.
Figure 1.4 Pin Assignments (2): Bus control pins are added and NOTE 2 is added.
6
7, 8
9
10 to 12 Tables 1.6 to 1.8 List of Pin Names for 128-pin package (1)(2)(3) are added.
13 to 15 Tables 1.9 to 1.11 Pin Functions (1)(2)(3) are revised.
A-1
REVISION HISTORY
M16C/6N Group (M16C/6NK, M16C/6NM) Data Sheet
Description
Summary
Rev.
Date
Page
2.10 Aug.25, 2006
18
3. Memory: Last 2 sentences (In memory expansion ... / Use T-V-ver.) are added.
Figure 3.1 Memory Map: NOTES 1 and 2 are added.
Table 4.1 SFR Information (1)
19
• Value of After Reset in PM0 is revised.
• CSR Register is added to 0008h.
• CSE Register is added to 001Bh.
• NOTES 1, 3 and 4 are added.
26
34
Table 4.8 SFR Information (8)
• The value of After Reset in IDB0 register is revised.
• The value of After Reset in IDB1 register is revised.
Table 4.16 SFR Information (16)
• Value of After Reset in PUR1 is revised.
• NOTE 1 is added.
36
37
Table 5.2 Recommended Operating Conditions (1) is partly revised.
Table 5.3 Recommended Operating Conditions (2)
• Power supply ripple is deleted. (three items)
Figure 5.1 Voltage Fluctuation Timing is deleted.
Table 5.4 Electrical Characteristics (1)
38
__________
________
• HOLD and RDY are added to Hysteresis.
• Hysteresis XIN is deleted.
41
42
Table 5.8 Flash Memory Version Electrical Characteristics is revised.
Table 5.12 Memory Expansion Mode and Microprocessor Mode is added.
45 to 47 Switching Characteristics are added.
49 to 55 Figures 5.4 to 5.10 Timing Diagram (2) to (8) are added.
56 to 70 Characteristics of 3.3 V in Normal-ver. are added.
71 to 80 5.2 Electrical Characteristics (T/V-ver.) is added.
A-2
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Colophon .6.0
相关型号:
M306NMFHGP#U3
M16C Series, 6NM Group, 3-ch IEBus, 3-phase PWM, CRC 128P6Q-A; Vcc= 3.0 to 5.5 volts, Temp= -40 to 85 C; Package: PLQP0128KB-A
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