M34508G4-XXXFP [RENESAS]
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER; 单片4位微机的CMOS
| 型号： | M34508G4-XXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| 文件： | 总142页 (文件大小：1073K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4508 Group
REJ03B0148-0102
Rev.1.02
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
2006.12.22
DESCRIPTION
ꢀKey-on wakeup function pins ................................................... 12
ꢀInput/Output port ...................................................................... 14
ꢀA/D converter
The 4508 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a simple,
high-speed instruction set. The computer is equipped with two 8-bit
timers (each timer has two reload registers), interrupts, 10-bit A/D
converter, Serial interface and oscillation circuit switch function.
10-bit successive comparison method ........................ 4 channel
ꢀSerial intereface ............................................................. 8-bit ꢀ 1
ꢀVoltage drop detection circuit (only for H version)
Reset occurrence .................................... Typ. 2.6 V (Ta = 25 °C)
Reset release .......................................... Typ. 2.7 V (Ta = 25 °C)
ꢀPower-on reset circuit (only for H version)
FEATURES
ꢀMinimum instruction execution time .................................. 0.5 µs
(at 6 MHz oscillation frequency, in through-mode)
ꢀSupply voltage .......................................................... 1.8 V to 5.5 V
(It depends on operation source clock, oscillation frequency and
operating mode.)
ꢀWatchdog timer
ꢀClock generating circuit (on-chip oscillator/ceramic resonator/RC
oscillation)
ꢀLED drive directly enabled (port D)
ꢀTimers
Timer 1................................. 8-bit timer with two reload registers
Timer 2................................. 8-bit timer with two reload registers
ꢀInterrupt ........................................................................ 5 sources
APPLICATION
Electrical household appliance, consumer electronic products, office
automation equipment, etc.
ROM (PROM) size
(ꢀ 10 bits)
RAM size
(ꢀ 4 bits)
Part number
M34508G4FP (Note)
Package
ROM type
4096 words
4096 words
4096 words
4096 words
4096 words
4096 words
4096 words
4096 words
PRSP0020DA-A
PRSP0020DA-A
PRSP0020DA-A
PRSP0020DA-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
QzROM
QzROM
QzROM
QzROM
QzROM
QzROM
QzROM
QzROM
256 words
256 words
256 words
256 words
256 words
256 words
256 words
256 words
M34508G4-XXXFP
M34508G4HFP (Note)
M34508G4H-XXXFP
M34508G4GP * (Note)
M34508G4-XXXGP *
M34508G4HGP * (Note)
M34508G4H-XXXGP *
Note: Shipped in blank.
*: Under development
PIN CONFIGURATION
P0
P0
P0
0
1
2
/SIN
1
2
20
19
18
17
16
15
14
13
12
11
V
DD
SS
IN
OUT
/SOUT
/SCK
V
3
X
4
P0
P1
P1
P1
3
0
1
2
X
5
CNVSS
RESET
6
/CNTR1
/CNTR0
7
P2
P2
1
/AIN1
/AIN0
/AIN5
/AIN4
8
P13/INT
0
9
D
0
1
D
D
3
2
10
D
Outline FP: PRSP0020DA-A (20P2N-A)
GP: PLSP0020JB-A (20P2F-A)
Pin configuration (top view) (4508 Group)
Rev.1.02 2006.12.22 page 1 of 140
REJ03B0148-0102
4508 Group
Block diagram (4508 Group)
Rev.1.02 2006.12.22 page 2 of 140
REJ03B0148-0102
4508 Group
PERFORMANCE OVERVIEW
Parameter
Function
Number of
131
132
M34508G4
basic instructions
M34508G4H
Minimum instruction execution time
0.5 µs (at 6 MHz oscillation frequency, in through mode)
4096 words ꢀ 10 bits
Memory sizes
ROM
RAM
256 words ꢀ 4 bits
Input/Output
ports
Four independent I/O ports.
Input is examined by skip decision.
D0–D3
I/O
Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function.
Both functions can be switched by software.
Ports D2 and D3 are also used as AIN4, and AIN5, respectively.
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P00, P01 and P02 are also used as SIN, SOUT and SCK, respectively.
P00–P03
P10–P13
P20, P21
I/O
I/O
I/O
4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P11, P12 and P13 are also used as CNTR1, CNTR0 and INT, respectively.
2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function.
Both functions and output structure can be switched by software.
Ports P20 and P21 are also used as AIN0 and AIN1, respectively.
Two independent I/O; CNTR1 and CNTR0 pins are also used as ports P11 and P12, respectively.
CNTR0,
CNTR1
Timer I/O
1-bit input; INT pin is also used as port P13.
Three independent I/O;
SIN, SOUT, and SCK are also used as ports P00, P01, and P02, respectively.
INT
Interrupt input
S
IN, SOUT,
Serial interface
input/output
SCK
Four independent input; AIN0, AIN1, AIN4, AIN5 are also used as P20, P21, D2 and D3, respectively.
AIN0, AIN1,
Analog input
AIN4, AIN5
Timers
8-bit programmable timer/event counter with two reload registers and PWM output function.
8-bit programmable timer/event counter with two reload registers and PWM output function.
16-bit timer (fixed dividing frequency) (for watchdog)
10-bit wide, This is equipped with an 8-bit comparator function.
4 channel (AIN0, AIN1, AIN4, AIN5 pins)
Timer 1
Timer 2
Watchdog timer function
A/D
converter
Analog input
Serial interface
Voltage drop
detection
8-bit ꢀ 1
Typ. 2.6 V (Ta = 25 °C)
Reset occurrence
Reset release
Typ. 2.7 V (Ta = 25 °C)
circuit (Note)
Power-on reset circuit (Note)
Built-in type
Interrupt
5 (one for external, two for timer, one for A/D, one for Serial interface)
Sources
Nesting
1 level
Subroutine nesting
Device structure
Package
8 levels
CMOS silicon gate
FP: 20-pin plastic molded SOP (PRSP0020DA-A)
GP: 20-pin plastic molded SSOP (PLSP0020JB-A)
–20 °C to 85 °C
Operating temperature range
Supply voltage
1.8 V to 5.5 V (It depends on operation source clock, oscillation frequency and operating mode.)
2.2 mA (Ta = 25°C, VDD = 5.0 V, f(XIN) = 6.0 MHz, f(STCK) = f(XIN)/1)
0.1 µA (Ta = 25°C, VDD = 5.0 V, output transistors in the cut-off state)
Power
Active mode
dissipation
RAM back-up mode
(typical value)
Note: These circuits are equipped with only the H version.
Rev.1.02 2006.12.22 page 3 of 140
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4508 Group
PIN DESCRIPTION
Pin
Name
Input/Output
Function
VDD
Power supply
—
—
Connected to a plus power supply.
Connected to a 0 V power supply.
VSS
Ground
CNVSS
RESET
CNVSS
—
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
Reset input/output
I/O
An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watch-
dog timer, the voltage drop detection circuit (only for H version) or the built-in power-on
reset (only for H version) causes the system to be reset, the RESET pin outputs “L”
level.
I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it be-
tween pins XIN and XOUT. A feedback resistor is built-in between them. When using the RC
oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open.
XIN
System clock input
System clock output
Input
Output
I/O
XOUT
D0–D3
I/O port D
Each pin of port D has an independent 1-bit wide I/O function.
Input is examined by
skip decision.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function.
Both functions can be switched by software.
Ports D2 and D3 are also used as AIN4 and AIN5, respectively.
P00–P03
P10–P13
P20, P21
I/O port P0
I/O port P1
I/O port P2
I/O
I/O
I/O
Port P0 serves as a 4-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P0 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P00, P01 and P02 are also used as SIN, SOUT and SCK, respectively.
Port P1 serves as a 4-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P1 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P11, P12 and P13 are also used as CNTR1, CNTR0 and INT, respectively.
Port P2 serves as a 2-bit I/O port.
The output structure can be switched to N-channel open-drain or CMOS by software.
For input use, set the latch of the specified bit to “1” and select the N-channel open-drain.
Port P2 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Ports P20 and P21 are also used as AIN0 and AIN1, respectively.
CNTR0
CNTR1
INT
CNTR0 pin has the function to input the clock for the timer 2 event counter, and to out-
put the PWM signal generated by timer 1.
This pin is also used as port P12.
Timer input/output
Timer input/output
Interrupt input
I/O
I/O
CNTR1 pin has the function to input the clock for the timer 1 event counter, and to out-
put the PWM signal generated by timer 2.
This pin is also used as port P11.
INT pin accepts external interrupts. It has the key-on wakeup function which can be
switched by software.
This pin is also used as port P13.
Input
Input
AIN0, AIN1,
AIN4, AIN5,
A/D converter analog input pins.
AIN0, AIN1, AIN4, AIN5 are also used as ports P20, P21, D2 and D3, respectively.
Analog input
SCK
SOUT
SIN
Serial interface data transfer synchronous clock I/O pin. SCK pin is also used as port P0
Serial interface data output pin. SOUT pin is also used as port P01.
Serial interface data input pin. SIN pin is also used as port P00.
2.
Serial interface clock I/O
Serial interface data output
Serial interface data input
I/O
Output
Input
Rev.1.02 2006.12.22 page 4 of 140
REJ03B0148-0102
4508 Group
MULTIFUNCTION
Pin
Pin
Pin
Multifunction
Multifunction
P00
Pin
P20
Multifunction
Multifunction
P20
SIN
AIN0
P00
SIN
AIN0
SOUT
SCK
AIN1
AIN4
AIN5
P01
P02
P11
P12
P13
SOUT
SCK
P01
P02
P11
P12
P13
P21
D2
AIN1
AIN4
AIN5
P21
D2
CNTR1
CNTR0
INT
CNTR1
CNTR0
INT
D3
D3
Notes 1: Pins except above have just single function.
2: The input/output of P00 can be used even when SIN is used. Be careful when using inputs of both SIN and P00 since the input threshold value of SIN pin
is different from that of port P00.
3: The input of P01 can be used even when SOUT is used.
4: The input of P02 can be used even when SCK is used. Be careful when using inputs of both SCK and P02 since the input threshold value of SCK pin is
different from that of port P02.
5: The input of P11 can be used even when CNTR1 (output) is selected.
The input/output of P11 can be used even when CNTR1 (input) is selected. Be careful when using inputs of both CNTR1 and P11 since the input thresh-
old value of CNTR1 pin is different from that of port P11.
6: The input of P12 can be used even when CNTR0 (output) is selected.
The input/output of P12 can be used even when CNTR0 (input) is selected. Be careful when using inputs of both CNTR0 and P12 since the input thresh-
old value of CNTR0 pin is different from that of port P12.
7: The input/output of P13 can be used even when INT is used. Be careful when using inputs of both INT and P13 since the input threshold value of INT
pin is different from that of port P13.
8: The input/output of P20, P21, D2, D3 can be used even when AIN0, AIN1, AIN4, AIN5 are used.
PORT FUNCTION
Input
Output
I/O
Control
Control
Port
Pin
Output structure
Remark
unit instructions registers
I/O
(4)
1
SD, RD
SZD, CLD
Port D D0, D1
N-channel open-drain/
CMOS
Programmable output structure selection
function
FR3
D2/AIN4
D3/AIN5
Programmable pull-up function
Programmable key-on wakeup function
Programmable output structure selection
function
FR3, PU2
K2
Q1
I/O
(4)
4
4
2
OP0A
IAP0
FR0, PU0
K0
J1
Port P0 P00/SIN, P01/SOUT,
P02/SCK, P03
N-channel open-drain/
CMOS
Programmable pull-up function
Programmable key-on wakeup function
Programmable output structure selection
function
I/O
(4)
OP1A
IAP1
FR1, PU1
K1, L1, I1
W1, W2
Port P1 P10, P11/CNTR1,
P12/CNT0,
N-channel open-drain/
CMOS
Programmable pull-up function
Programmable key-on wakeup function
Programmable output structure selection
function
P13/INT
W5, W6
I/O
(2)
OP2A
IAP2
FR2, PU2
Q1
K2
Port P2 P20/AIN0
P21/AIN1
N-channel open-drain/
CMOS
Programmable pull-up function
Programmable key-on wakeup function
Programmable output structure selection
function
Rev.1.02 2006.12.22 page 5 of 140
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4508 Group
DEFINITION OF CLOCK AND CYCLE
ꢀꢀInstruction clock
ꢀꢀOperation source clock
The instruction clock is a signal derived by dividing the system
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
clock by 3. The one instruction clock cycle generates the one ma-
chine cycle.
ꢀꢀMachine cycle
The machine cycle is the standard cycle required to execute the
instruction.
• Clock (f(RING)) of the on-chip oscillator which is the internal os-
cillator.
ꢀꢀSystem clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the register MR and register RG.
Table Selection of system clock
Register MR, RG
System clock
f(STCK) = f(RING)/8
Operation mode
MR3
1
MR2
MR1
–
MR0
RG0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
Internal frequency divided by 8 mode
Internal frequency divided by 4 mode
Internal frequency divided by 2 mode
Internal frequency through mode
1
–
0
f(STCK) = f(RING)/4
f(STCK) = f(RING)/2
f(STCK) = f(RING)
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
0
–
0
0
–
0
1
0
–
High-speed frequency divided by 8 mode
High-speed frequency divided by 4 mode
High-speed frequency divided by 2 mode
High-speed through mode
1
0
–
0
0
–
0
0
–
Note: The internal frequency divided by 8 is selected after system is released from reset.
Rev.1.02 2006.12.22 page 6 of 140
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4508 Group
CONNECTIONS OF UNUSED PINS
Connection
Connect to VSS.
Open.
Usage condition
Pin
RC oscillation circuit is not selected. (CRCK instruction is not executed.)
XIN
XOUT
D0, D1
Open.
Connect to VSS.
Open.
N-channel open-drain is selected for the output structure (FR30, FR31 = “0”).
The key-on wakeup function is invalid (K22, K23 = “0”).
N-channel open-drain is selected for the output structure (FR32, FR33 = “0”).
Pull-up transistor is OFF (PU22, PU23 = “0”).
D2/AIN4, D3/AIN5
Connect to VSS.
The key-on wakeup function is invalid (K22, K23 = “0”).
SIN pin is not selected (J11 = “0”).
Open.
P00/SIN
The key-on wakeup function is invalid (K00 = “0”).
N-channel open-drain is selected for the output structure (FR00 = “0”).
Pull-up transistor is OFF (PU00 = “0”).
Connect to VSS.
The key-on wakeup function is invalid (K00 = “0”).
The key-on wakeup function is invalid (K01 = “0”).
N-channel open-drain is selected for the output structure (FR01 = “0”).
Pull-up transistor is OFF (PU01 = “0”).
Open.
P01/SOUT
P02/SCK
Connect to VSS.
The key-on wakeup function is invalid (K01 = “0”).
SCK pin is not selected (J11J10 = “00”).
Open.
The key-on wakeup function is invalid (K02 = “0”).
N-channel open-drain is selected for the output structure (FR02 = “0”).
Pull-up transistor is OFF (PU02 = “0”).
Connect to VSS.
The key-on wakeup function is invalid (K02 = “0”).
The key-on wakeup function is invalid (K03 = “0”).
N-channel open-drain is selected for the output structure (FR03 = “0”).
Pull-up transistor is OFF (PU03 = “0”).
Open.
P03
Connect to VSS.
The key-on wakeup function is invalid (K03 = “0”).
The key-on wakeup function is invalid (K10 = “0”).
N-channel open-drain is selected for the output structure (FR10 = “0”).
Pull-up transistor is OFF (PU10 = “0”).
Open.
P10
Connect to VSS.
The key-on wakeup function is invalid (K10 = “0”).
CNTR1 input is not selected for the timer 1 count source (W11, W10 ≠ “10”).
The key-on wakeup function is invalid (K11 = “0”).
N-channel open-drain is selected for the output structure (FR11 = “0”).
Pull-up transistor is OFF (PU11 = “0”).
Open.
P11/CNTR1
Connect to VSS.
The key-on wakeup function is invalid (K11 = “0”).
CNTR0 input is not selected for the timer 2 count source (W21, W20 ≠ “10”).
The key-on wakeup function is invalid (K12 = “0”).
N-channel open-drain is selected for the output structure (FR12 = “0”).
Pull-up transistor is OFF (PU12 = “0”).
Open.
P12/CNTR0
P13/INT
Connect to VSS.
The key-on wakeup function is invalid (K12 = “0”).
INT pin input is disabled (I13 = “0”).
Open.
The key-on wakeup function is invalid (K13 = “0”).
N-channel open-drain is selected for the output structure (FR13 = “0”).
Pull-up transistor is OFF (PU13 = “0”).
Connect to VSS.
The key-on wakeup function is invalid (K13 = “0”).
The key-on wakeup function is invalid (K20, K21 = “0”).
N-channel open-drain is selected for the output structure (FR20, FR21 = “0”).
Pull-up transistor is OFF (PU20, PU21 = “0”).
Open.
P20/AIN0, P21/AIN1
Connect to VSS.
The key-on wakeup function is invalid (K20, K21 = “0”).
(Note when connecting to VSS or VDD)
ꢀꢀConnect the unused pins to VSS using the thickest wire at the shortest distance against noise.
Rev.1.02 2006.12.22 page 7 of 140
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4508 Group
PORT BLOCK DIAGRAMS
Skip decision
Register Y
Decoder
SZD instruction
(Note 3)
FR3
j
CLD
instruction
(Note 1)
S
R
D0, D1
(Note 2)
SD instruction
RD instruction
(Note 1)
Q
(Note 4)
K2
k
Pull-up transistor
“L” level
detection circuit
PU2
k
(Note 4)
Key-on wakeup input
Skip decision
SZD instruction
(Note 4)
Register Y
Decoder
FR3
K
(Note 1)
CLD
(Note 2)
instruction
S
R
D2/AIN4, D3/AIN5
SD instruction
RD instruction
(Note 1)
Q
Q1
Decoder
Analog input
This symbol represents a parasitic diode on the port.
Notes 1:
2: Applied potential to these ports must be VDD or less.
3: j represents bits 0 or 1.
4: k represents bits 2 or 3.
Port block diagram (1)
Rev.1.02 2006.12.22 page 8 of 140
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4508 Group
K00
Level
detection circuit
Key-on wakeup input
PU0
0
IAP0 instruction
Register A
A
0
FR0
0
(Note 1)
(Note 2)
P00/SIN
D
A
0
(Note 1)
OP0A instruction
T
Q
Serial interface data input
J11
K01
Level
detection circuit
Key-on wakeup input
PU0
1
IAP0 instruction
Register A
A
1
FR0
1
(Note 1)
A
1
D
T
OUT (Note 2)
P01/S
J1
0
0
OP0A instruction
Q
(Note 1)
1
Serial interface data output
K02
Level
detection circuit
Key-on wakeup input
PU0
2
IAP0 instruction
Register A
A
2
FR0
2
(Note 1)
D
T
A
2
(Note 2)
P02/SCK
(Note 1)
OP0A instruction
Q
Synchronous clock (output) for
serial interface data transfer
Synchronous clock (input) for
serial interface data transfer
J1
J1
0
1
This symbol represents a parasitic diode on the port.
Notes 1:
2: Applied potential to these ports must be VDD or less.
Port block diagram (2)
Rev.1.02 2006.12.22 page 9 of 140
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4508 Group
K03
Level
detection circuit
Key-on wakeup input
PU0
3
IAP0 instruction
Register A
A3
FR0
3
(Note 1)
A
3
D
T
(Note 2)
P0
3
(Note 1)
Q
OP0A instruction
K10
L1
0
3
L1
0
2
Key-on
Level detection circuit
Edge detection circuit
wakeup
input
PU1
0
1
1
IAP1 instruction
Register A
A0
FR1
0
(Note 1)
A
0
D
T
0 (Note 2)
P1
(Note 1)
Q
OP1A instruction
K11
L1
0
3
L1
0
2
Key-on
wakeup
input
Level detection circuit
Edge detection circuit
PU1
1
1
1
IAP1 instruction
Register A
A1
FR1
1
(Note 1)
A
1
D
T
(Note 2)
P11/CNTR1
W6
0
3
Q
(Note 1)
OP1A instruction
PWMOD2
W6
1
0
0
Clock (input) for
timer 1 event count
1
W1
0
W1
1
This symbol represents a parasitic diode on the port.
Notes 1:
2: Applied potential to these ports must be VDD or less.
Port block diagram (3)
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4508 Group
K12
L1
0
3
L1
0
2
Key-on
wakeup
input
Level detection circuit
Edge detection circuit
PU1
2
1
1
IAP1 instruction
Register A
A2
FR1
2
(Note 1)
A
2
D
T
(Note 2)
P12/CNTR0
W5
0
3
Q
(Note 1)
OP1A instruction
1
PWM1
W5
0
0
Clock (input) for
timer 2 event count
1
W2
0
W2
1
K13
L1
0
3
L1
0
2
Key-on
Level detection circuit
Edge detection circuit
wakeup
input
PU1
3
1
1
IAP1 instruction
Register A
A3
FR1
3
(Note 1)
A
3
D
P1
3/INT(Note 2)
(Note 1)
T
Q
OP1A instruction
(Notes 3, 4)
External 0 interrupt circuit
External 0 interrupt
Key-on wakeup input
Timer 1 count start synchronous circuit input
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: As for details, refer to the external interrupt structure.
4: The threshold value of port input is different from that of external interrupt input.
Port block diagram (4)
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(Note 3)
K2
j
Level
detection circuit
Key-on wakeup input
(Note 3)
(Note 3)
PU2
j
IAP2 instruction
Register A
Aj
FR2
j
(Note 1)
(Note 2)
,
/AIN1
D
T
P2
0
/AIN0
A
j
P21
Q
OP2A instruction
(Note 1)
Q1
Decoder
Analog input
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: j represents 0 or 1.
Port block diagram (5)
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I1
Falling
2
One-sided edge
detection circuit
I11
(Note 1)
0
0
External 0
interrupt
P13/INT
EXF0
1
1
Both edges
detection circuit
Rising
Timer 1 count start
synchronization
circuit input
SNZI0 instruction
Skip
I13
L1
0
1
(Note 2)
Level detection circuit
Edge detection circuit
Key-on wakeup input
L10
1
(Note 3)
•
This symbol represents a parasitic diode on the port.
is 0, “L” level is detected.
is 1, “H” level is detected.
is 0, falling edge is detected.
is 1, rising edge is detected.
Note 1:
2: When I1
When I1
3: When I1
When I1
2
2
2
2
External interrupt circuit structure
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FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
(M(DP))
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit
data addition, comparison, AND operation, OR operation, and bit
manipulation.
ALU
Addition
(A)
<Result>
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange,
and I/O operation.
Fig. 1 AMC instruction execution example
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
<Set>
<Clear>
SC instruction
RC instruction
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Figure
2).
Carry flag CY can be set to “1” with the SC instruction and cleared to
“0” with the RC instruction.
CY
A
3
A2
A1 A0
<Rotation>
RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit data,
and for 8-bit data transfer together with register A.
A
0
CY A
3
A2 A1
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Fig. 2 RAR instruction execution example
Register E is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.
Register B TAB instruction Register A
B3
B2
B1
B0
A3 A2 A1 A0
(4) Register D
Register D is a 3-bit register.
TEAB instruction
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p, BLA
p, or BMLA p instruction is executed (Figure 4).
Register E E
7
E6
E5
E4
E3
E2
E1
E0
Also, when the TABP p instruction is executed at UPTF flag = “1”,
the high-order 2 bits of ROM reference data is stored to the low-or-
der 2 bits of register D, the high-order 1 bit of register D is “0”. When
the TABP p instruction is executed at UPTF flag = “0”, the contents
of register D remains unchanged. The UPTF flag is set to “1” with the
SUPT instruction and cleared to “0” with the RUPT instruction. The
initial value of UPTF flag is “0”.
TABE instruction
A3
A2
A1
A0
B3
B2
B1
B0
Register B TBA instruction Register A
Fig. 3 Registers A, B and register E
Register D is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.
TABP p instruction
Specifying address
ROM
8
4
0
Low-order 4bits
PCH
PCL
Register A (4)
Register B (4)
Register D (3)
p6 p5 p4 p3 p2 p1 p0
A3 A2 A1 A0
DR2DR1DR0
Middle-order 4 bits
High-order 2 bits
Immediate field
value p
The contents of The contents of
register D register A
* Flag UPTF = 1;
High-order
2
bits of reference data is
transferred to the low-order 2 bits of register D.
“0” is stored to the high-order 1 bit of register D.
Flag UPTF = 0;
Data is not transferred to register D.
Fig. 4 TABP p instruction execution example
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(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
• branching to an interrupt service routine (referred to as an interrupt
service routine),
SK
0
(SP) = 0
(SP) = 1
(SP) = 2
(SP) = 3
(SP) = 4
(SP) = 5
(SP) = 6
(SP) = 7
SK
SK
SK
SK
SK
SK
SK
1
2
3
4
5
6
7
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that subrou-
tines can be nested up to 8 levels. However, one of stack registers is
used respectively when using an interrupt service routine and when
executing a table reference instruction. Accordingly, be careful not to
over the stack when performing these operations together. The con-
tents of registers SKs are destroyed when 8 levels are exceeded.
The register SK nesting level is pointed automatically by 3-bit stack
pointer (SP). The contents of the stack pointer (SP) can be trans-
ferred to register A with the TASP instruction.
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
and the contents of SK0 is destroyed.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt
occurs, this register (SDP) is used to temporarily store the contents
of data pointer, carry flag, skip flag, register A, and register B just be-
fore an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used when
executing the subroutine call instruction and the table reference in-
struction.
Fig. 5 Stack registers (SKs) structure
(SP) ← 0
(SK ) ← 000116
0
(PC) ← SUB1
Main program
Address
Subroutine
SUB1 :
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions
and continuous described skip instructions. When an interrupt oc-
curs, the contents of skip flag is stored automatically in the interrupt
stack register (SDP) and the skip condition is retained.
000016 NOP
NOP
·
·
·
000116 BM SUB1
000216 NOP
RT
(PC) ← (SK
(SP) ← 7
0)
Note :
Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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(8) Program counter (PC)
Program counter
Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table refer-
ence instruction (TABP p) is executed.
p6
p
5
p
4
p
3
p
2
p
1
p0
a6 a5 a4 a3 a2 a1 a0
PC
H
PC
L
Specifying page
Specifying address
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which speci-
fies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Make sure that the PCH does not specify after the last page of the
built-in ROM.
Z
1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, reg-
ister X specifies a file, and register Y specifies a RAM digit (Figure
8).
Specifying
RAM digit
Register Y (4)
Register X (4)
Specifying RAM file
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).
Register Z (2)
Specifying RAM file group
• Note
Register Z of data pointer is undefined after system is released
from reset.
Fig. 8 Data pointer (DP) structure
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
Specifying bit position
Set
D3
D2
D1
D0
0
0
0
1
1
Register Y (4)
Port D output latch
Fig. 9 SD instruction execution example
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PROGRAM MEMOY (ROM)
1 word of program memory is composed of 10 bits. ROM is sepa-
rated every 128 words by the unit of page (addresses 0 to 127).
Table 1 shows the ROM size and pages. Figure 10 shows the ROM
map of M34508G4.
9
8
7
6
5
4
3
2 1 0
000016
007F16
008016
00FF16
010016
017F16
018016
Page 0
Page 1
Page 2
Page 3
Interrupt address page
Subroutine special page
Table 1 ROM size and pages
ROM (PROM) size
Part number
Pages
(✕ 10 bits)
4096 words
4096 words
M34508G4
M34508G4H
32 (0 to 31)
32 (0 to 31)
A part of page 1 (addresses 008016 to 00FF16) is reserved for inter-
rupt addresses (Figure 11). When an interrupt occurs, the address
(interrupt address) corresponding to each interrupt is set in the pro-
gram counter, and the instruction at the interrupt address is
executed. When using an interrupt service routine, write the instruc-
tion generating the branch to that routine at an interrupt address.
Page 2 (addresses 010016 to 017F16) is the special page for subrou-
tine calls. Subroutines written in this page can be called from any
page with the 1-word instruction (BM). Subroutines extending from
page 2 to another page can also be called with the BM instruction
when it starts on page 2.
0
FFF16
Page 31
Fig. 10 ROM map of M34508G4
9 8
7
6
5
4 3 2 1 0
008016
008216
External 0 interrupt address
ROM pattern (bits 7 to 0) of all addresses can be used as data areas
with the TABP p instruction.
Timer 1 interrupt address
Timer 2 interrupt address
008416
008616
ROM Code Protect Address
When selecting the protect bit write by using a serial programmer or
selecting protect enabled for writing shipment by Renesas Technol-
ogy corp., reading or writing from/to QzROM is disabled by a serial
programmer.
008816
008A16
As for the QzROM product in blank, the ROM code is protected by
selecting the protect bit write at ROM writing with a serial pro-
grammer.
008C16
008E16
A/D interrupt address
As for the QzROM product shipped after writing, whether the ROM
code protect is used or not can be selected as ROM option setup
(“MASK option” written in the mask file converter) when ordering.
Serial interface interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
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Table 2 RAM size
Part number
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM.
RAM size
M34508G4
256 words ✕ 4 bits (1024 bits)
256 words ✕ 4 bits (1024 bits)
M34508G4H
Table 2 shows the RAM size. Figure 12 shows the RAM map.
• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.
RAM 256 words ✕ 4 bits (1024 bits)
Register Z
0
...
........
15
Register X
0
2
3
6
7
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Fig. 12 RAM map
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Table 3 Interrupt sources
INTERRUPT FUNCTION
Priority
level
Interrupt
address
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit is enabled (“1”)
Interrupt name
Activated condition
1
2
3
4
5
External 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
A/D interrupt
Address 0
in page 1
Level change of INT
pin
Timer 1 underflow
Address 4
in page 1
• Interrupt enable flag is enabled (INTE = “1”)
Timer 2 underflow
Address 6
in page 1
Table 3 shows interrupt sources. (Refer to each interrupt request flag
for details of activated conditions.)
Completion of
A/D conversion
Address C
in page 1
Serial interface
interrupt
Completion of serial
interface transmit/
recieve
Address E
in page 1
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt
enable/disable. Interrupts are enabled when INTE flag is set to “1”
with the EI instruction and disabled when INTE flag is cleared to “0”
with the DI instruction. When any interrupt occurs, the INTE flag is
automatically cleared to “0,” so that other interrupts are disabled un-
til the EI instruction is executed.
Table 4 Interrupt request flag, interrupt enable bit and skip in-
struction
Interrupt
request flag
Interrupt
enable bit
Skip instruction
Interrupt name
EXF0
T1F
SNZ0
SNZT1
SNZT2
SNZAD
SNZSI
V10
V12
V13
V22
V23
External 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
A/D interrupt
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2 to
select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and skip
instruction.
T2F
ADF
SIOF
Serial interface
interrupt
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
Table 5 Interrupt enable bit function
When the activated condition for each interrupt is satisfied, the corre-
sponding interrupt request flag is set to “1.” Each interrupt request
flag is cleared to “0” when either;
Occurrence of interrupt
Interrupt enable bit
Skip instruction
Enabled
Disabled
1
0
Invalid
Valid
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition is sat-
isfied even if the interrupt is disabled by the INTE flag or its interrupt
enable bit. Once set, the interrupt request flag retains set until a
clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt dis-
able state is released, the interrupt priority level is as follows shown
in Table 3.
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(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as fol-
lows (Figure 14).
• Program counter (PC)
............................................................... Each interrupt address
• Program counter (PC)
• Stack register (SK)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
The address of main routine to be
.............................................
executed when returning
• Interrupt enable flag (INTE)
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
.................................................................. 0 (Interrupt disabled)
Only the request flag for the current interrupt source is cleared to
“0.”
• Interrupt request flag (only the flag for the current interrupt
source) ................................................................................... 0
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
• Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
(5) Interrupt processing
Fig. 14 Internal state when interrupt occurs
When an interrupt occurs, a program at an interrupt address is ex-
ecuted after branching a data store sequence to stack register. Write
the branch instruction to an interrupt service routine at an interrupt
address.
INT pin
Address 0
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
(L→H or
in page 1
EXF0
T1F
V1
0
2
H→L input)
Timer 1
underflow
Address 4
in page 1
V1
Address 6
in page 1
Timer 2
underflow
T2F
V1
3
Main
routine
Address C
in page 1
Completion of
A/D conversion
ADF
SIOF
V22
Interrupt
service routine
Serial interface
transmit/receive
completed
Address E
in page 1
V2
3
INTE
Interrupt
occurs
Activated
condition
Request flag
(state retained)
Enable
bit
Enable
flag
•
•
•
•
Fig. 15 Interrupt system diagram
EI
RTI
Interrupt is
enabled
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
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(6) Interrupt control registers
• Interrupt control register V2
• Interrupt control register V1
The A/D interrupt enable bit and serial interface interrupt enable bit
are assigned to register V2. Set the contents of this register
through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Interrupt enable bits of external 0, timer 1 and timer 2 are as-
signed to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
Table 6 Interrupt control registers
R/W
at RAM back-up : 00002
TAV1/TV1A
Interrupt control register V1
Timer 2 interrupt enable bit
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
V13
V12
V11
V10
Timer 1 interrupt enable bit
Not used
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
External 0 interrupt enable bit
R/W
Interrupt control register V2
Serial interface interrupt enable bit
A/D interrupt enable bit
Not used
at reset : 00002
at RAM back-up : 00002
TAV2/TV2A
0
1
0
1
0
1
0
1
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
V23
V22
V21
V20
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Not used
Note: “R” represents read enabled, and “W” represents write enabled.
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable
bits (V10, V12, V13, V22, V23), and interrupt request flag are “1.” The
interrupt actually occurs 2 to 3 machine cycles after the cycle in
which all three conditions are satisfied. The interrupt occurs after 3
machine cycles only when the three interrupt conditions are satisfied
on execution of other than one-cycle instructions (Refer to Figure
16).
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Fig. 16 Interrupt sequence
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4508 Group
EXTERNAL INTERRUPTS
The 4508 Group has the external 0 interrupt. An external interrupt
request occurs when a valid waveform is input to an interrupt input
pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.
Table 7 External interrupt activated conditions
Valid waveform
selection bit
Name
Input pin
P13/INT
Activated condition
I11
I12
External 0 interrupt
When the next waveform is input to P13/INT pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
I1
Falling
2
One-sided edge
detection circuit
I11
(Note 1)
0
0
External 0
interrupt
P13/INT
EXF0
1
1
Both edges
detection circuit
Rising
Timer 1 count start
synchronization
circuit input
SNZI0 instruction
Skip
I13
L1
0
1
(Note 2)
Level detection circuit
Edge detection circuit
Key-on wakeup input
L10
1
(Note 3)
•
This symbol represents a parasitic diode on the port.
is 0, “L” level is detected.
is 1, “H” level is detected.
is 0, falling edge is detected.
is 1, rising edge is detected.
Note 1:
2: When I1
When I1
3: When I1
When I1
2
2
2
2
Fig. 17 External interrupt circuit structure
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a valid
➀➀Set the bit 3 of register I1 to “1” for the INT pin to be in the input
enabled state.
waveform is input to P13/INT pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure
16).
➀ Select the valid waveform with the bits 1 and 2 of register I1.
➀ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➀ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt or
the skip instruction. The EXF0 flag is cleared to “0” when an interrupt
occurs or when the next instruction is skipped with the skip instruc-
tion.
➀ Set both the external 0 interrupt enable bit (V10) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid wave-
form is input to the P13/INT pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to P13/INT pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of how
to use the external 0 interrupt is as follows.
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(2) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 interrupt.
Set the contents of this register through register A with the TI1A in-
struction. The TAI1 instruction can be used to transfer the contents
of register I1 to register A.
Table 8 External interrupt control register
R/W
Interrupt control register I1
at reset : 00002
INT pin input disabled
INT pin input enabled
at RAM back-up : state retained
TAI1/TI1A
0
1
INT pin input control bit (Note 2)
I13
I12
Falling waveform (“L” level of INT pin is recognized with the SNZI0
0
1
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
0
1
0
1
I11
I10
INT pin edge detection circuit control bit
INT pin
timer 1 control enable bit
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
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(3) Notes on interrupts
➀ Note [3] on bit 2 of register I1
➀ Note [1] on bit 3 of register I1
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the follow-
ing notes.
When the input of the INT pin is controlled with the bit 3 of register
I1 in software, be careful about the following notes.
• Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register I1
is changed. In order to avoid the occurrence of an unexpected in-
terrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀) and
then, change the bit 2 of register I1 is changed.
• Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register I1
is changed. In order to avoid the occurrence of an unexpected in-
terrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀) and
then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0”
after executing at least one instruction (refer to Figure 20➀).
Also, set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction (refer to Figure 20➀).
In addition, execute the SNZ0 instruction to clear the EXF0 flag to “0”
after executing at least one instruction (refer to Figure 18➀).
Also, set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction (refer to Figure 18➀).
LA
4
; (➀➀➀02)
LA
4
8
; (➀➀➀02)
TV1A
LA
; The SNZ0 instruction is valid ...........➀
; (1➀➀➀2)
TV1A
LA
; The SNZ0 instruction is valid ...........➀
; (1➀➀➀2)
12
TI1A
NOP
SNZ0
; Interrupt valid waveform is changed
........................................................... ➀
; The SNZ0 instruction is executed
(EXF0 flag cleared)
TI1A
NOP
SNZ0
; Control of INT pin input is changed
........................................................... ➀
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
........................................................... ➀
NOP
........................................................... ➀
➀ : these bits are not used here.
➀ : these bits are not used here.
Fig. 18 External 0 interrupt program example-1
Fig. 20 External 0 interrupt program example-3
➀ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
• When the INT pin input is disabled (register I13 = “0”), set the key-
on wakeup of INT pin to be invalid (register L10 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 19➀).
LA
0
; (➀➀➀02)
TI1A
DI
; INT key-on wakeup disabled ...........➀
EPOF
POF
; RAM back-up
➀ : these bits are not used here.
Fig. 19 External 0 interrupt program example-2
Rev.1.02 2006.12.22 page 25 of 140
REJ03B0148-0102
4508 Group
TIMERS
• Fixed dividing frequency timer
The 4508 Group has the following timers.
The fixed dividing frequency timer has the fixed frequency dividing
ratio (n). An interrupt request flag is set to “1” after every n count of
a count pulse.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a setting
value n. When it underflows (count to n + 1), a timer interrupt re-
quest flag is set to “1,” new data is loaded from the reload register,
and count continues (auto-reload function).
FF16
n : Counter initial value
Count starts
Reload
Reload
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
“1”
Timer interrupt
request flag
“0”
An interrupt occurs or
a skip instruction is executed.
Fig. 21 Auto-reload function
The 4508 Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
(Timers 1 and 2 have the interrupt function, respectively)
• 16-bit timer
Prescaler and timers 1 and 2 can be controlled with the timer control
registers PA, W1, W2 , W5 and W6. The 16-bit timer is a free counter
which is not controlled with the control register.
Each function is described below.
Table 9 Function related timers
Frequency
dividing ratio
Control
register
Circuit
Structure
Count source
Use of output signal
Prescaler 8-bit programmable
binary down counter
• Instruction clock (INSTCK)
1 to 256
• Timer 1 and 2 count sources
PA
Timer 1
8-bit programmable
binary down counter
(link to INT input)
• PWM2 signal (PWMOD2)
• Prescaler output (ORCLK)
• CNTR1 input
1 to 256
• Timer 2 count source
• CNTR0 output
W1
W5
W6
• Timer 1 interrupt
(with PWM output function) • On-chip oscillator clock (f(RING))
Timer 2
8-bit programmable
binary down counter
(INT input period count
function)
• Timer 1 underflow (T1UDF)
• Prescaler output (ORCLK)
• CNTR0 input
1 to 256
65536
• Timer 1 count source
• CNTR1 output
W2
W5
W6
• Timer 2 interrupt
• System clock (STCK)
(with PWM output function)
Watchdog 16-bit fixed dividing
timer
• Instruction clock (INSTCK)
• System reset (counting twice)
• Decision of flag WDF1
-
frequency
Rev.1.02 2006.12.22 page 26 of 140
REJ03B0148-0102
4508 Group
MR3, MR2
System clock (STCK)
Division circuit
Divided by 8
Divided by 4
Divided by 2
11
10
01
00
Internal clock
generating circuit
(divided by 3)
Instruction clock
(INSTCK)
MR0
On-chip oscillator
1
0
Multi-
plexer
Ceramic resonance
RC oscillation
XIN
(CRCK)
(Note 1)
Prescaler (8)
ORCLK
PA0
Reload register RPS (8)
(TPSAB)
(TPSAB)
(TPSAB)
(TABPS)
(TABPS)
Register B
Register A
Watchdog timer (16)
1 - - - - - - - - - - - - - - 16
INSTCK
(Note 2)
S
Q
WDF1
WRST instruction
R
RESET signal
(Note 4)
S
Q
WEF
D
T
Q
R
Watchdog reset signal
RESET signal
DWDT instruction
+
WRST instruction
R
(Note 3)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Notes 1: When CRCK instruction is executed, RC oscillation is selected.
When CRCK instruction is not executed, ceramic resonance is selected.
2: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST
instruction is executed while flag WDF1 = “1”.
The next instruction is not skipped even when the WRST instruction is executed
while flag WDF1 = “0”.
3: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the
DWDT instruction and WRST instruction are executed continuously.
4: The WEF flag is set to “1” at system reset or RAM back-up mode.
Fig. 22 Timers structure (1)
Rev.1.02 2006.12.22 page 27 of 140
REJ03B0148-0102
4508 Group
I1
2
I1
0
1
One-sided edge
detection circuit
P1
3
/INT
I1
0
INTSNC
3
1
1
Both edges
detection circuit
W60
P11/CNTR1
0
1
Register B
Register A
W11, W10
00
(T1HAB)
(Note 3)
Reload control circuit
Reload register R1H (8)
Timer 1 (8)
PWM2
01
10
11
W5
1
ORCLK
0
T
Q
R
PWM1
1
f(RING)
(T1R1L)
W13
W12
Reload register R1L (8)
(T1AB)
(T1AB)
(Note 1)
Timer 1
interrupt
Timer 1 underflow signal
(T1UDF)
(T1AB)
T1F
(TAB1)
(TAB1)
INTSNC
S
R
Q
Register B
Register A
I1
0
W5
2
T1UDF
P12/CNTR0
W50
0
1
Register A
Register B
W21, W20
00
(T2HAB)
(Note 4)
Reload register R2H (8)
T1UDF
01
10
11
W6
1
Reload control circuit
ORCLK
0
Timer 2 (8)
T
Q
PWM2
1
STCK
(T2R2L)
W23
W2
2
R
Reload register R2L (8)
(T2AB)
(T2AB)
(Note 2)
Timer 2
interrupt
(T2AB)
INTSNC
W6
T2F
(TAB2)
(TAB2)
D
T
Q
Register B
Register A
1
R
I13
W53
0
Port P12 output
PWM1
P12/CNTR0
1
W6
0
3
Port P11 output
P11/CNTR1
PWMOD2
PWM2
T1UDF
1
Notes 1: Timer 1 count start synchronous circuit is synchronized
with the valid edge of INT pin selected by bits 1 (I1 ) and
2 (I1 ) of register I1.
2: Timer 2 INT input period count circuit is used to count
the valid edge period of INT pin selected by bits 1 (I1
and 2 (I1 ) of register I1.
3: When the PWM1 function is valid (W1
1
D
T
Q
R
2
W6
2
W12
1
)
2
3
=“1”), the value is
auto-reloaded alternately from reload register R1L and
R1H every timer 1 underflow.
This instruction is used to transfer the contents of
reload register R1L to timer 1.
This instruction is used to transfer the contents of
reload register R2L to timer 2.
System clock
T1R1L:
T2R2L:
When the PWM1 function is invalid (W1
is auto-reloaded from reload register R1L only.
4: When the PWM2 function is valid (W2 =“1”), the value is
3=“0”), the value
3
STCK:
ORCLK:
auto-reloaded alternately from reload register R2L and
R2H every timer 2 underflow.
Prescaler output
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
When the PWM2 function is invalid (W2
3=“0”), the value
is auto-reloaded from reload register R2L only.
Fig. 23 Timers structure (2)
Rev.1.02 2006.12.22 page 28 of 140
REJ03B0148-0102
4508 Group
Table 10 Timer control registers
W
Timer control register PA
Prescaler control bit
at reset : 02
at RAM back-up : 02
TPAA
Stop (state initialized)
Operating
0
1
PA0
R/W
at RAM back-up : 00002
Timer control register W1
PWM1 function control bit
at reset : 00002
TAW1/TW1A
PWM1 function invalid
PWM1 function valid
Stop (state retained)
Operating
0
1
0
1
W13
W12
Timer 1 control bit
Count source
W11 W10
W11
W10
PWM2 signal
0
0
1
1
0
1
0
1
Timer 1 count source selection bits
Prescaler output (ORCLK)
CNTR1 input
On-chip oscillator clock (f(RING))
R/W
Timer control register W2
PWM2 function control bit
at reset : 00002
at RAM back-up : 00002
TAW2/TW2A
0
1
0
1
PWM2 function invalid
PWM2 function valid
Stop (state retained)
Operating
W23
W22
Timer 2 control bit
W21
Count source
W20
W21
W20
0
0
1
1
Timer 1 underflow signal (T1UDF)
Prescaler output (ORCLK)
CNTR0 input
0
1
0
1
Timer 2 count source selection bits
System clock (STCK)
R/W
Timer control register W5
at reset : 00002
at RAM back-up : state retained
TAW5/TW5A
P12 (I/O) / CNTR0 (input)
0
W53
W52
W51
W50
P12/CNTR0 pin function selection bit
P12 (input) /CNTR0 (I/O)
1
0
1
0
1
0
1
Count auto-stop circuit not selected
Count auto-stop circuit selected
Count start synchronous circuit not selected
Count start synchronous circuit selected
Falling edge
Timer 1 count auto-stop circuit
selection bit (Note 2)
Timer 1 count start synchronous circuit
selection bit (Note 3)
CNTR0 pin input count edge selection bit
Rising edge
R/W
Timer control register W6
at reset : 00002
at RAM back-up : state retained
TAW6/TW6A
P11 (I/O) / CNTR1 (input)
0
1
0
1
0
1
0
1
W63
W62
W61
W60
P11/CNTR1 pin function selection bit
P11 (input) /CNTR1 (I/O)
Output auto-control circuit not selected
Output auto-control circuit selected
INT pin input period count circuit not selected
INT pin input period count circuit selected
Falling edge
CNTR 1 pin output auto-control circuit
selection bit
Timer 2
INT pin input period count circuit selection bit
CNTR1 pin input count edge selection bit
Rising edge
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”) and the timer 1 count start synchronous circuit is selected (W51=“1”).
3: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”).
Rev.1.02 2006.12.22 page 29 of 140
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4508 Group
(3) Timer 1 (interrupt function)
(1) Timer control registers
Timer 1 is an 8-bit binary down counter with two timer 1 reload regis-
ters (R1L, R1H). Data can be set simultaneously in timer 1 and the
reload register R1L with the T1AB instruction. Data can be set in the
reload register R1H with the T1HAB instruction. The contents of re-
load register R1L set with the T1AB instruction can be set to timer 1
again with the T1R1L instruction. Data can be read from timer 1 with
the TAB1 instruction.
• Timer control register PA
Register PA controls the count operation of prescaler. Set the con-
tents of this register through register A with the TPAA instruction.
• Timer control register W1
Register W1 controls the count operation and count source of
timer 1, and PWM1 function. Set the contents of this register
through register A with the TW1A instruction. The TAW1 instruction
can be used to transfer the contents of register W1 to register A.
• Timer control register W2
Stop counting and then execute the T1AB or TAB1 instruction to
read or set timer 1 data.
When executing the T1HAB instruction to set data to reload register
R1H while timer 1 is operating, avoid a timing when timer 1
underflows.
Register W2 controls the count operation and count source of
timer 2, and PWM2 function. Set the contents of this register
through register A with the TW2A instruction. The TAW2 instruction
can be used to transfer the contents of register W2 to register A.
• Timer control register W5
Timer 1 starts counting after the following process;
➀ set data in timer 1
➀ set count source by bits 0 and 1 of register W1, and
➀ set the bit 2 of register W1 to “1.”
Register W5 controls the input count edge of CNTR0 pin, timer 1
count start synchronous circuit, timer 1 auto-stop circuit and P12/
CNTR0 pin function. Set the contents of this register through reg-
ister A with the TW5A instruction. The TAW5 instruction can be
used to transfer the contents of register W5 to register A.
• Timer control register W6
When a value set in reload register R1L is n and a value set in re-
load register R1H is m, timer 1 divides the count source signal by n
+ 1 or m + 1 (n = 0 to 255, m = 0 to 255).
<Bit 3 of register W1 = “0” (PWM1 function invalid)>
Register W6 controls the input count edge of CNTR1 pin, the INT
pin input count start synchronous circuit and CNTR1 pin output
auto-control circuit and the P11/CNTR1 pin function. Set the con-
tents of this register through register A with the TW6A instruction.
The TAW6 instruction can be used to transfer the contents of reg-
ister W6 to register A.
Once count is started, when timer 1 underflows (the next count pulse
is input after the contents of timer 1 becomes “0”), the timer 1 inter-
rupt request flag (T1F) is set to “1,” new data is loaded from reload
register R1L, and count continues (auto-reload function).
<Bit 3 of register W1 = “1” (PWM1 function valid)>
Timer 1 generates the PWM1 signal of the “L” interval set as reload
register R1L, and the “H” interval set as reload register R1H. The
PWM1 signal generated by timer 1 is output from CNTR0 pin by set-
ting “1” to bit 3 of register W5.
(2) Prescaler
Prescaler is an 8-bit binary down counter with the prescaler reload
register RPS. Data can be set simultaneously in prescaler and the
reload register RPS with the TPSAB instruction. Data can be read
from reload register RPS with the TABPS instruction.
Stop counting and then execute the TPSAB or TABPS instruction to
read or set prescaler data.
After timer 1 control by INT pin is enabled by setting the bit 0 of reg-
ister I1 to “1”, INT pin input can be used as the start trigger for timer
1 count operation by setting the bit 1 of register W5 to “1”.
Also, in this time, the auto-stop function by timer 1 underflow can be
performed by setting the bit 2 of register W5 to “1.”
Prescaler starts counting after the following process;
➀ set data in prescaler, and
➀ set the bit 0 of register PA to “1.”
When a value set in reload register RPS is n, prescaler divides the
count source signal by n + 1 (n = 0 to 255).
Count source for prescaler is the instruction clock (INSTCK).
Once count is started, when prescaler underflows (the next count
pulse is input after the contents of prescaler becomes “0”), new data
is loaded from reload register RPS, and count continues (auto-reload
function).
The output signal (ORCLK) of prescaler can be used for timer 1 and
2 count sources.
Rev.1.02 2006.12.22 page 30 of 140
REJ03B0148-0102
4508 Group
(4) Timer 2 (interrupt function)
(5) Count start synchronization circuit (timer 1)
Timer 1 has the count start synchronous circuit which synchronizes
the input of INT pin, and can start the timer count operation.
Timer 1 count start synchronous circuit function can be selected af-
ter timer 1 control by INT pin is enabled by setting the bit 0 of
register I1 to “1” and its function is selected by setting the bit 1 of
register W5 to “1”.
Timer 2 is an 8-bit binary down counter with two timer 2 reload regis-
ters (R2L, R2H). Data can be set simultaneously in timer 2 and the
reload register R2L with the T2AB instruction. Data can be set in the
reload register R2H with the T2HAB instruction. The contents of re-
load register R2L set with the T2AB instruction can be set to timer 2
again with the T2R2L instruction. Data can be read from timer 2 with
the TAB2 instruction.
When timer 1 count start synchronous circuit is used, the count start
synchronous circuit is set, the count source is input to timer by input-
ting valid waveform to INT pin.
Stop counting and then execute the T2AB or TAB2 instruction to read
or set timer 2 data.
When executing the T2HAB instruction to set data to reload register
R2H while timer 2 is operating, avoid a timing when timer 2
underflows.
The valid waveform of INT pin to set the count start synchronous cir-
cuit is the same as the external interrupt activated condition.
Once set, the count start synchronous circuit is cleared by clearing
the bit I10 to “0” or system reset.
Timer 2 starts counting after the following process;
➀ set data in timer 2
However, when the count auto-stop circuit is selected (W22 = “1”),
the count start synchronous circuit is cleared (auto-stop) at the timer
1 underflow.
➀ set count source by bits 0 and 1 of register W2, and
➀ set the bit 2 of register W2 to “1.”
When a value set in reload register R2L is n and a value set in re-
load register R2H is m, timer 2 divides the count source signal by n +
1 or m + 1 (n = 0 to 255, m = 0 to 255).
(6) Count auto-stop circuit (timer 1)
Timer 1 has the count auto-stop circuit which is used to stop timer 1
automatically by the timer 1 underflow when the count start synchro-
nous circuit is used.
Once count is started, when timer 2 underflows (the next count pulse
is input after the contents of timer 2 becomes “0”), the timer 2 inter-
rupt request flag (T2F) is set to “1,” new data is loaded from reload
register R2L, and count continues (auto-reload function).
The count auto-stop circuit is valid by setting the bit 2 of register W5
to “1”. It is cleared by the timer 1 underflow and the count source to
timer 1 is stopped.
This function is valid only when the timer 1 count start synchronous
circuit is selected.
<Bit 3 of register W2 = “0” (PWM2 function invalid)>
Once count is started, when timer 2 underflows (the next count pulse
is input after the contents of timer 2 becomes “0”), the timer 2 inter-
rupt request flag (T2F) is set to “1,” new data is loaded from reload
register R2L, and count continues (auto-reload function).
<Bit 3 of register W2 = “1” (PWM2 function valid)>
(7) INT pin input period count circuit (timer 2)
Timer 2 has the INT pin input period count circuit to count the valid
waveform input interval of the INT pin.
When bit 1 of register W6 is set to “1”, the INT pin input period count
circuit of timer 2 becomes valid, and the count source is input. The
count source input is stopped by the next input of valid waveform to
the INT pin.
Timer 2 generates the PWM2 signal of the “L” interval set as reload
register R2L, and the “H” interval set as reload register R2H. The
PWM2 signal generated by timer 2 is output from CNTR1 pin by set-
ting “1” to bit 3 of register W6.
Then, every a valid waveform is input to the INT pin, start/stop of the
count source input is alternately repeated.
PWM2 output to CNTR1 pin combined with timer 1 can be controlled
by setting the bit 2 of register W6 to “1.”
A valid waveform of the INT pin input is the same as the activated
condition of an external interrupt.
Input period of INT pin by timer 2 can be counted by setting the bit 1
of register W6 to “1.”
The INT pin input period count circuit set once is cleared by setting
the INT pin input to be disabled state. The INT pin input can be dis-
abled by clearing bit 3 of register I1 to “0”.
(8) Timer input/output pin (P12/CNTR0 pin, P11/
CNTR1 pin)
CNTR0 pin is used to input the timer 2 count source and output the
PWM1 signal generated by timer 1.
CNTR1 pin is used to input the timer 1 count source and output the
PWM2 signal generated by timer 2.
The P12/CNTR0 pin function can be selected by bit 3 of register W5.
The P11/CNTR1 pin function can be selected by bit 3 of register W6.
When the CNTR0 input is selected for timer 2 count source, timer 2
counts the falling or rising waveform of CNTR0 input. The count
edge is selected by bit 0 of register W5.
When the CNTR1 input is selected for timer 1 count source, timer 1
counts the falling or rising waveform of CNTR1 input. The count
edge is selected by bit 0 of register W6.
Rev.1.02 2006.12.22 page 31 of 140
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4508 Group
(9) PWM1 output function (P12/CNTR0, timer 1)
When bit 3 of register W1 is set to “1”, the data is reloaded alter-
nately from reload register R1L and R1H every timer 1 underflow.
Timer 1 generates the PWM1 signal of the “L” interval set as reload
register R1L, and the “H” interval set as reload register R1H.
In this time, the PWM1 signal generated by timer 1 is output from
CNTR0 pin by setting “1” to bit 3 of register W5.
(12) Precautions
- Prescaler
Stop prescaler counting and then execute the TABPS instruction to
read its data.
Stop prescaler counting and then execute the TPSAB instruction to
write data to prescaler.
When the TW1A instruction is executed while the PWM1 signal is
“H”, the contents of register W1 is changed after the “H” interval of
the PWM1 signal is ended.
- Timer count source
Stop timer 1 or 2 counting to change its count source.
(10) PWM2 output function (P11/CNTR1, timer
1, timer 2)
- Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 in-
struction to read its data.
When bit 3 of register W2 is set to “1”, the data is reloaded alter-
nately from reload register R2L and R2H every timer 2 underflow.
Timer 2 generates the PWM2 signal of the “L” interval set as reload
register R2L, and the “H” interval set as reload register R2H.
In this time, the PWM2 signal generated by timer 2 is output from
CNTR1 pin by setting “1” to bit 3 of register W6.
- Writing to the timer
Stop timer 1 or 2 counting and then execute the T1AB, T1R1L,
T2AB or T2R2L instruction to write data to timer.
When bit 2 of register W6 is set to “1”, the PWM2 signal output to
CNTR1 pin is switched to valid/invalid alternately each timer 1 un-
derflow. However, when timer 1 is stopped (bit 2 of register W1 is
cleared to “0”), this function is canceled.
- Writing to reload register
In order to write a data to the reload register R1H while the timer 1
is operating, execute the T1HAB instruction except a timing of the
timer 1 underflow.
When the TW2A instruction is executed while the PWM2 signal is
“H”, the contents of register W2 is changed after the “H” interval of
the PWM2 signal is ended.
In order to write a data to the reload register R2H while the timer 2
is operating, execute the T2HAB instruction except a timing of the
timer 2 underflow.
(11) Timer interrupt request flags (T1F, T2F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2).
- PWM signal (PWM1, PWM2)
If the timer 1 count stop timing and the timer 1 underflow timing
overlap during output of the PWM1 signal, a hazard may occur in
the PWM1 output waveform.
Use the interrupt control register V1, V2 to select an interrupt or a
skip instruction.
If the timer 2 count stop timing and the timer 2 underflow timing
overlap during output of the PWM2 signal, a hazard may occur in
the PWM2 output waveform.
An interrupt request flag is cleared to “0” when an interrupt occurs or
when the next instruction is skipped with a skip instruction.
- Prescaler, timer 1 and timer 2 count start timing and count time
when operation starts
Count starts from the first rising edge of the count source (2) after
prescaler and timer operations start (1).
Time to first underflow (3) is shorter (for up to 1 period of the count
source) than time among next underflow (4) by the timing to start
the timer and count source operations after count starts.
When selecting CNTR input as the count source of timer, timer
operates synchronizing with the count edge (falling edge or rising
edge) of CNTR input selected by software.
➀
Count source
Count source
(When falling edge of
CNTR input is selected)
Timer value
3
2
1
0
3
2
1
0
3
2
Timer underflow signal
➀
➀
➀ Timer start
Fig. 24 Timer count start timing and count time when operation starts
Rev.1.02 2006.12.22 page 32 of 140
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4508 Group
➀ PWM1 function invalid (W13 = “0”)
Timer 1 count source
0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
(R1L)
Timer 1 count value
(Reload register)
(R1L)
(R1L)
(R1L)
(R1L)
Timer 1 underflow signal
PWM1 signal
PWM1 signal “L” fixed
Timer 1 start
➀ PWM1 function valid (W13 = “1”)
Timer 1 count source
0216
Timer 1 count value
(Reload register)
0316
(R1L)
0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
(R1H)
(R1L)
(R1H)
(R1L)
(R1H)
Timer 1 underflow signal
PWM1 signal
3 clock
PWM period 7 clock
3 clock
PWM period 7 clock
4 clock
4 clock
4 clock
Timer 1 start
* : “0316” is set to reload register R1L and “0216” is set to reload register R1H.
Fig. 25 Timer 1 operation example
Rev.1.02 2006.12.22 page 33 of 140
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4508 Group
➀ CNTR1 output auto-control circuit operation example 1 (W23 = “1”, W63 = “1”, W62 = “1”)
PWM2 signal
Timer 1 underflow signal
Timer 1 start
CNTR1 output
CNTR1 output start
* When the CNTR1 output auto-control circuit is selected, valid/invalid of CNTR1 output is repeated every timer 1 underflows.
➀ CNTR1 output auto-control circuit operation example 2 (W2
3
= “1”, W63 = “1”)
PWM2 signal
Timer 1 underflow signal
Timer 1 start
Timer 1 stop
➀
➀
Register W6
2
➀
CNTR1 output
CNTR1 output stop
CNTR1 output start
➀ When the CNTR1 output auto-control function is not selected while the CNTR output is invalid, CNTR1 output invalid state is retained.
➀ When the CNTR1 output auto-control function is not selected while the CNTR output is valid, CNTR1 output valid state is retained.
➀ When the timer 1 is stopped, the CNTR1 output auto-control function becomes invalid.
Fig. 26 CNTR1 output auto-control function by timer 1
Rev.1.02 2006.12.22 page 34 of 140
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➀ Timer 2 count start timing (R2L = “0216”, R2H = ”0216”, W23 = “1”)
Machine cycle
Mi
Mi + 1
TW2A instruction execution (W2
Mi + 2
Mi + 3
2
←“1”)
Timer 2 count source
(System clock (STCK))
Register W2
2
Timer 2 count value
(Reload register)
0216
0116
0016
0216
0116
0016
0216
(R2L)
(R2H)
(R2L)
Timer 2 undeflow signal
PWM2 signal
Timer 2 count start timing
➀ Timer 2 count stop timing (R2L = “0216”, R2H = ”0216”, W2
3
= “1”)
Machine cycle
Mi
Mi + 1
Mi + 2
TW2A instruction execution (W2
Mi + 3
2
←“0”)
Timer 2 count source
(System clock (STCK))
Register W2
2
Timer 2 count value
(Reload register)
0216
0116
0016
0216
0116
0016
0216
(R2H)
(R2L)
(R2H)
Timer 2 undeflow signal
PWM2 signal
(Note 1)
Timer 2 count stop timing
Notes 1: If the timer count stop timing and the timer underflow timing overlap while the PWM function is valid (W1
a hazard may occur in the PWM signal waveform.
3
=“1” or W23=“1”),
2: When timer count is stopped during “H” duration of the PWM signal, timer is stopped after the end of the “H” output duration.
Fig. 27 Timer count start/stop timing
Rev.1.02 2006.12.22 page 35 of 140
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4508 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a pro-
gram run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
When the WEF flag is set to “1” after system is released from reset,
the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are ex-
ecuted continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
The timer WDT downcounts the instruction clocks as the count
source from “FFFF16” after system is released from reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “FFFF16,” the next
count pulse is input), the WDF1 flag is set to “1.”
The WEF flag is set to "1" at system reset or RAM back-up mode.
The WRST instruction has the skip function. When the WRST in-
struction is executed while the WDF1 flag is “1”, the WDF1 flag is
cleared to “0” and the next instruction is skipped.
If the WRST instruction is never executed until the timer WDT un-
derflow occurs (until timer WDT counts 65534), WDF2 flag is set to
“1,” and the RESET pin outputs “L” level to reset the microcom-
puter.
When the WRST instruction is executed while the WDF1 flag is “0”,
the next instruction is not skipped.
The skip function of the WRST instruction can be used even when
the watchdog timer function is invalid.
Execute the WRST instruction at each period of 65534 machine
cycle or less by software when using watchdog timer to keep the
microcomputer operating normally.
FFFF16
Value of 16-bit timer (WDT)
000016
➀
➀
WDF1 flag
65534 count
(Note)
➀
WDF2 flag
RESET pin output
➀ Reset
released
➀ WRST instruction
executed
➀ System reset
(skip executed)
➀ After system is released from reset (= after program is started), timer WDT starts count down.
➀ When timer WDT underflow occurs, WDF1 flag is set to “1.”
➀ When the WRST instruction is executed while the WDF1 flag is “1”, WDF1 flag is cleared to “0,”
the next instruction is skipped.
➀ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the
watchdog reset signal is output.
➀ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.
Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer
is the instruction clock.
Fig. 28 Watchdog timer function
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When the watchdog timer is used, clear the WDF1 flag at the period
of 65534 machine cycles or less with the WRST instruction.
When the watchdog timer is not used, execute the DWDT instruction
and the WRST instruction continuously (refer to Figure 29).
The watchdog timer is not stopped with only the DWDT instruction.
The contents of WDF1 flag and timer WDT are initialized at the RAM
back-up mode.
WRST
; WDF1 flag cleared
DI
DWDT
WRST
; Watchdog timer function enabled/disabled
; WEF and WDF1 flags cleared
When using the watchdog timer and the RAM back-up mode, initial-
ize the WDF1 flag with the WRST instruction just before the
microcomputer enters the RAM back-up state (refer to Figure 30)
Also, set the NOP instruction after the WRST instruction, for the
case when a skip is performed with the WRST instruction.
Fig. 29 Program example to start/stop watchdog timer
WRST
; WDF1 flag cleared
NOP
DI
; Interrupt disabled
EPOF
; POF instruction enabled
; RAM back-up mode
POF
↓
Oscillation stop
Fig. 30 Program example to enter the RAM back-up mode
when using the watchdog timer
Rev.1.02 2006.12.22 page 37 of 140
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4508 Group
A/D CONVERTER
Table 11 A/D converter characteristics
The 4508 Group has a built-in A/D conversion circuit that performs
conversion by 10-bit successive comparison method. Table 11
shows the characteristics of this A/D converter. This A/D converter
can also be used as an 8-bit comparator to compare analog voltages
input from the analog input pin with preset values.
Parameter
Characteristics
Conversion format Successive comparison method
Resolution
10 bits
Relative accuracy
Linearity error: ±2LSB (VDD=2.7 to 5.5 V)
Differential non-linearity error: ±0.9LSB
(VDD=2.7 to 5.5 V)
Conversion speed
Analog input pin
31 µs (f(XIN)=6 MHz, f(STCK)=f(XIN))
4
Register B (4)
Register A (4)
4
8
4
8
4
4
TAQ1
TQ1A
2
Q13 Q12 Q11 Q10
TALA
TABAD
TADAB
Instruction clock
1/6
2
Q13
0
1
ADF
(1)
A/D
interrupt
A/D control circuit
P2
P2
0
/AIN0
/AIN1
1
Comparator
Successive comparison
register (AD) (10)
0
1
Q13
Q1
3
8
10
10
D
D
2
/AIN4
/AIN5
1
0
1
DAC
operation
signal
0
1
Q13
3
8
8
8
DA converter
(Note 1)
V
DD
V
SS
Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage.
2: Writing/reading data to the comparator register is possible only in the comparator mode (Q1 =1).
The value of the comparator register is retained even when the mode is switched to the A/D conversion
mode (Q1 =0) because it is separated from the successive comparison register (AD). Also, the resolution
in the comparator mode is 8 bits because the comparator register consists of 8 bits.
3
3
Fig. 31 A/D conversion circuit structure
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Table 12 A/D control registers
R/W
A/D control register Q1
at reset : 00002
at RAM back-up : state retained
TAQ1/TQ1A
A/D conversion mode
Comparator mode
Q11 Q10
0
1
A/D operation mode selection bit
Q13
Q12
Q12
Selected pins
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN0
AIN1
Not available
Not available
AIN4
Analog input pin selection bits
Q11
Q10
AIN5
Not available
Not available
Note: “R” represents read enabled, and “W” represents write enabled.
(1) A/D control register Q1
(6) Operation description
Register Q1 is used to select the operation mode and one of analog
input pins. Set the contents of this register through register A with the
TQ1A instruction. The TAQ1 instruction can be used to transfer the
contents of register Q1 to register A.
A/D conversion is started with the A/D conversion start instruction
(ADST). The internal operation during A/D conversion is as follows:
➀ When the A/D conversion starts, the register AD is cleared to
“00016.”
(2) Operating at A/D conversion mode
➀ Next, the topmost bit of the register AD is set to “1,” and the com-
parison voltage Vref is compared with the analog input voltage VIN.
➀ When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is Vref
> VIN, it is cleared to “0.”
The A/D conversion mode is set by setting the bit 3 of register Q1 to “0.”
(3) Successive comparison register AD
Register AD stores the A/D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of this
register can be stored in register B and register A with the TABAD in-
struction. The contents of the low-order 2 bits of this register can be
stored into the high-order 2 bits of register A with the TALA instruc-
tion. However, do not execute these instructions during A/D
conversion.
The 4508 Group repeats this operation to the lowermost bit of the
register AD to convert an analog value to a digital value. A/D conver-
sion stops after 62 machine cycles (31 µs when f(XIN) = 6.0 MHz in
high-speed mode) from the start, and the conversion result is stored
in the register AD. An A/D interrupt activated condition is satisfied
and the ADF flag is set to “1” as soon as A/D conversion completes
(Figure 32).
When the contents of register AD is n, the logic value of the compari-
son voltage Vref generated from the built-in DA converter can be
obtained with the reference voltage VDD by the following formula:
Logic value of comparison voltage Vref
VDD
Vref =
➀ n
1024
n: The value of register AD (n = 0 to 1023)
(4) A/D conversion completion flag (ADF)
A/D conversion completion flag (ADF) is set to “1” when A/D conver-
sion completes. The state of ADF flag can be examined with the skip
instruction (SNZAD). Use the interrupt control register V2 to select
the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when the
next instruction is skipped with the skip instruction.
(5) A/D conversion start instruction (ADST)
A/D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
Rev.1.02 2006.12.22 page 39 of 140
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4508 Group
Table 13 Change of successive comparison register AD during A/D conversion
Comparison voltage (Vref) value
VDD
At starting conversion
1st comparison
Change of successive comparison register AD
-------------
VDD
2
1
0
1
0
0
1
-----
0
0
0
0
0
0
0
0
0
-------------
-------------
VDD
2
➀1
➀1
-----
2nd comparison
3rd comparison
±
-------------
4
VDD
4
-------------
VDD
2
VDD
8
➀2
-----
±
±
±
±
-------------
A/D conversion result
After 10th comparison
completes
VDD
2
VDD
-------------
➀1
➀2
➀3
-----
➀8
➀9
➀A
1024
-------------
➀2: 2nd comparison result
➀8: 8th comparison result
➀A: 10th comparison result
➀1: 1st comparison result
➀3: 3rd comparison result
➀9: 9th comparison result
(7) A/D conversion timing chart
Figure 32 shows the A/D conversion timing chart.
ADST instruction
62 machine cycles
A/D conversion
completion flag (ADF)
DAC operation signal
Fig. 32 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which
the analog input from P20/AIN0 pin is A/D converted, and the high-or-
der 4 bits of the converted data are stored in address M(Z, X, Y) =
(0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and
the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/
D interrupt is not used in this example.
(Bit 3)
(Bit 0)
A/D control register Q1
0
0
0
0
AIN0 pin selected
A/D conversion mode
➀ Select the AIN0 pin function and A/D conversion mode with the
register Q1 (refer to Figure 33).
Fig. 33 Setting registers
➀ Execute the ADST instruction and start A/D conversion.
➀ Examine the state of ADF flag with the SNZAD instruction to de-
termine the end of A/D conversion.
➀ Transfer the low-order 2 bits of converted data to the high-order 2
bits of register A (TALA instruction).
➀ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
➀ Transfer the high-order 8 bits of converted data to registers A and
B (TABAD instruction).
➀ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
➀ Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
Rev.1.02 2006.12.22 page 40 of 140
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4508 Group
(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the
register Q1 to “1.”
(12) Comparator operation start instruction
(ADST instruction)
In comparator mode, executing ADST starts the comparator operat-
Below, the operation at comparator mode is described.
ing.
The comparator stops 8 machine cycles after it has started (6 µs at
f(XIN) = 4.0 MHz in high-speed through mode). When the analog in-
put voltage is lower than the comparison voltage, the ADF flag is set
to “1.”
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the
8-bit comparator register as a register for setting comparison volt-
ages. The contents of register B is stored in the high-order 4 bits of
the comparator register and the contents of register A is stored in the
low-order 4 bits of the comparator register with the TADAB instruc-
tion.
(13) Notes for the use of A/D conversion 1
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of reg-
ister AD is transferred to the high-order 2 bits of register A,
simultaneously, the low-order 2 bits of register A is “0.”
• Operating mode of A/D converter
When changing from A/D conversion mode to comparator mode, the
result of A/D conversion (register AD) is undefined.
However, because the comparator register is separated from register
AD, the value is retained even when changing from comparator
mode to A/D conversion mode. Note that the comparator register
can be written and read at only comparator mode.
Do not change the operating mode (both A/D conversion mode
and comparator mode) of A/D converter with the bit 3 of register
Q1 while the A/D converter is operating.
If the value in the comparator register is n, the logic value of com-
parison voltage Vref generated by the built-in DA converter can be
determined from the following formula:
Clear the bit 2 of register V2 to “0” to change the operating mode
from the comparator mode to A/D conversion mode.
The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the compara-
tor mode to the A/D conversion mode. Accordingly, set a value to
the bit 3 of register Q1, and execute the SNZAD instruction to clear
the ADF flag.
Logic value of comparison voltage Vref
VDD
Vref =
➀ n
256
n: The value of register AD (n = 0 to 255)
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D
conversion, stores the results of comparing the analog input voltage
with the comparison voltage. When the analog input voltage is lower
than the comparison voltage, the ADF flag is set to “1.” The state of
ADF flag can be examined with the skip instruction (SNZAD). Use
the interrupt control register V2 to select the interrupt or the skip in-
struction.
The ADF flag is cleared to “0” when the interrupt occurs or when the
next instruction is skipped with the skip instruction.
ADST instruction
8 machine cycles
Comparison result
store flag(ADF)
DAC operation signal
Comparator operation completed.
(The value of ADF is determined)
Fig. 34 Comparator operation timing chart
Rev.1.02 2006.12.22 page 41 of 140
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4508 Group
(14) Definition of A/D converter accuracy
The A/D conversion accuracy is defined below (refer to Figure 35).
Vn: Analog input voltage when the output data changes from “n” to
“n+1” (n = 0 to 1022)
VFST–V0T
• Relative accuracy
• 1LSB at relative accuracy →
(V)
1022
➀ Zero transition voltage (V0T)
This means an analog input voltage when the actual A/D con-
version output data changes from “0” to “1.”
➀ Full-scale transition voltage (VFST)
VDD
• 1LSB at absolute accuracy →
(V)
1024
This means an analog input voltage when the actual A/D con-
version output data changes from “1023” to ”1022.”
➀ Linearity error
This means a deviation from the line between V0T and VFST of
a converted value between V0T and VFST.
➀ Differential non-linearity error
This means a deviation from the input potential difference re-
quired to change a converter value between V0T and VFST by 1
LSB at the relative accuracy.
• Absolute accuracy
This means a deviation from the ideal characteristics between 0
to VDD of actual A/D conversion characteristics.
Output data
Full-scale transition voltage (VFST
)
1023
1022
b–a
a
Differential non-linearity error =
c
[LSB]
Linearity error =
[LSB]
b
a
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB by relative accuracy
b: Vn+1–V
c: Difference between ideal V
and actual V
n
n
n
Ideal line of A/D conversion
between V
0
–V1022
1
0
V
n
Vn+1
V
0
V1
V
1022
V
DD
Analog voltage
Zero transition voltage (V0T
)
Fig. 35 Definition of A/D conversion accuracy
Rev.1.02 2006.12.22 page 42 of 140
REJ03B0148-0102
4508 Group
SERIAL INTERFACE
Table 14 Serial interface pins
The 4508 Group has a built-in clock synchronous serial interface
which can serially transmit or receive 8-bit data.
Serial interface consists of;
Pin
Pin function when selecting serial interface
P02/SCK
P01/SOUT
P03/SIN
Clock I/O (SCK)
Serial data output (SOUT)
Serial data input (SIN)
• Serial interface register SI
• Serial interface control register J1
Note: Even when the SIN pin function is used, the I/O of port P00 is valid.
Even when the SOUT pin function is used, the input of port P01 is valid.
Even when the SCK pin function is used, the input of P02 is valid.
Be careful when using inputs of both SCK and P02 since the input
threshold value of SCK pin is different from that of port P02.
• Serial interface transmit/receive completion flag (SIOF)
• Serial interface counter
Registers A and B are used to perform data transfer with internal
CPU.
The pin functions of the serial interface pins can be set with the reg-
ister J1.
J13J12
00
1/8
01
1/4
1/2
Synchronous
circuit
Serial
interface
interrupt
Serial interface counter (3)
SIOF
10
11
INSTCK
S
CK
P0
2
/SCK
Q
S
R
SST
instruction
Internal reset signal
S
S
OUT
IN
P0
1
/SOUT
MSB Serial interface register (8) LSB
P00/SIN
TABSI
TSIAB
TABSI
Register B (4)
Register A (4)
J11 J10
Fig. 36 Serial interface structure
Table 15 Serial interface control register
Serial interface control register J1
R/W
TAJ1/TJ1A
at reset : 00002
at RAM back-up : state retained
Synchronous clock
J12
0
J13
0
J13
J12
Instruction clock (INSTCK) divided by 8
Instruction clock (INSTCK) divided by 4
Instruction clock (INSTCK) divided by 2
External clock (SCK input)
Serial interface synchronous clock
selection bits
1
0
0
1
1
1
J10
0
Port function
J11
0
J11
J10
P00, P01,P02 selected/SIN, SOUT, SCK not selected
P00, SOUT, SCK selected/SIN, P01, P02 not selected
SIN, P01, SCK selected/P00, SOUT, P02 not selected
SIN, SOUT, SCK selected/P00, P01,P02 not selected
1
0
Serial interface port function selection bits
0
1
1
1
Note: “R” represents read enabled, and “W” represents write enabled.
Rev.1.02 2006.12.22 page 43 of 140
REJ03B0148-0102
4508 Group
At transmit (D
7–D0: transfer data)
At receive
S
IN pin
S
OUT pin
Serial interface register (SI)
Serial interface register (SI)
S
OUT pin
SIN pin
D
7
D
6
D
5
5
D
4
4
D
3
D
2
D
1
D
0
* * * * * * * *
D7
D
6
7
D
D
D
D
D
3
D2
D1
D
D
D
0
Transfer data set
Transfer start
* * * * * * * *
D
D
6
D
5
6
4
5
D
3
4
D
2
3
1
2
D0
* * * * * * *
*
* * D
7
D
D
D
D1
D0
* * * * * *
Transfer complete
D7
D6
D5 D4 D3 D2 D1 D0
* * * * * * * *
Fig. 37 Serial interface register state when transferring
(1) Serial interface register SI
(3) Serial interface start instruction (SST)
When the SST instruction is executed, the SIOF flag is cleared to
“0” and then serial interface transmission/reception is started.
Serial interface register SI is the 8-bit data transfer serial/parallel
conversion register. Data can be set to register SI through registers
A and B with the TSIAB instruction. The contents of register A is
transmitted to the low-order 4 bits of register SI, and the contents
of register B is transmitted to the high-order 4 bits of register SI.
During transmission, each bit data is transmitted LSB first from the
lowermost bit (bit 0) of register SI, and during reception, each bit
data is received LSB first to register SI starting from the topmost bit
(bit 7).
(4) Serial interface control register J1
Register J1 controls the synchronous clock, P02/SCK, P01/SOUT
and P00/SIN pin function. Set the contents of this register through
register A with the TJ1A instruction. The TAJ1 instruction can be
used to transfer the contents of register J1 to register A.
When register SI is used as a work register without using serial in-
terface, do not select the SCK pin.
(2) Serial interface transmit/receive
completion flag (SIOF)
Serial interface transmit/receive completion flag (SIOF) is set to “1”
when serial data transmission or reception completes. The state of
SIOF flag can be examined with the skip instruction (SNZSI). Use
the interrupt control register V2 to select the interrupt or the skip
instruction.
The SIOF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
Rev.1.02 2006.12.22 page 44 of 140
REJ03B0148-0102
4508 Group
up the wiring between each pin with a resistor. Figure 38 shows the
data transfer timing and Table 16 shows the data transfer sequence.
(5) How to use serial interface
Figure 38 shows the serial interface connection example. Serial in-
terface interrupt is not used in this example. In the actual wiring, pull
Master (clock control)
Slave (external clock)
S
RDY signal
D3
D3
S
CK
S
S
CK
IN
S
OUT
S
IN
S
OUT
(Bit 0)
(Bit 3)
1
(Bit 3)
0
(Bit 0)
1
Serial interface
Serial interface
1
1
1
0
1
control register J1
Serial interface port
control register J1
Serial interface port
S
CK,SOUT,SIN
S
CK,SOUT,SIN
Instruction clock/8 selected
as synchronous clock
External clock selected
as synchronous clock
(Bit 3)
0
(Bit 3)
0
(Bit 0)
(Bit 0)
Interrupt control
register V2
Interrupt control
register V2
➀
➀
➀
➀
➀
➀
Serial interface
interrupt enable bit
(SNZSI instruction
valid)
Serial interface
interrupt enable bit
(SNZSI instruction
valid)
➀: Set an arbitrary value.
Fig. 38 Serial interface connection example
Rev.1.02 2006.12.22 page 45 of 140
REJ03B0148-0102
4508 Group
Master
M3
M4
M5
M
6
M7
SOUT
M7’
M0
M1
M2
SIN
S7’
S0
S1
S2
S3
S4
S5
S6
S7
SST instruction
S
CK
Slave
SST instruction
SRDY signal
S0
S1
S2
S3
S4
S5
S6
S7
SOUT
S7’
SIN
M7’
M0
M1
M2
M3
M4
M5
M6
M7
M0–M7: Contents of master serial interface register
S0–S
7: Contents of slave serial interface register
Rising of SCK: Serial input
Falling of SCK: Serial output
Fig. 39 Timing of serial interface data transfer
Table 16 Processing sequence of data transfer from master to slave
Slave (reception)
Master (transmission)
[Initial setting]
[Initial setting]
• Setting serial interface control register J1, and interrupt control register V2
• Setting the serial interface control register J1 and inter-
shown in Figure 38.
rupt control register V2 shown in Figure 38.
TJ1A and TV2A instructions
TJ1A and TV2A instructions
• Setting the port transmitted the reception enable signal (SRDY) and output-
ting “H” level.
• Setting the port received the reception enable signal
(SRDY) to the input mode.
(Port D3 is used in this example)
SD instruction
(Port D3 is used in this example)
SD instruction
* [Transmission enable state]
• Storing transmission data to serial interface register SI.
TSIAB instruction
*[Reception enable state]
• The SIOF flag is cleared to “0.”
SST instruction
• “L” level (reception possible) is output from port D3.
RD instruction
[Reception]
[Transmission]
•Check port D3 is “L” level.
SZD instruction
•Serial transfer starts.
SST instruction
•Check transmission completes.
SNZSI instruction
• Check reception completes.
SNZSI instruction
•Wait (timing when continuously transferring)
• “H” level is output from port D3.
SD instruction
[Data processing]
1-byte data is serially transferred on this process. Subsequently, data
can be transferred continuously by repeating the process from *.
When an external clock is selected as a synchronous clock, control
the clock externally because serial transfer is performed as long as
clock is externally input. (Unlike an internal clock, an external clock
is not stopped when serial transfer is completed.) However, the
SIOF flag is set to “1” when the clock is counted 8 times after ex-
ecuting the SST instruction. Be sure to set the initial level of the
external clock to “H.”
Rev.1.02 2006.12.22 page 46 of 140
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4508 Group
RESET FUNCTION
(1) RESET pin input
System reset is performed by the followings:
• “L” level is applied to the RESET pin externally,
• System reset instruction (SRST) is executed,
• Reset occurs by watchdog timer,
System reset is performed certainly by applying “L” level to RESET
pin for 1 machine cycle or more when the following condition is sat-
isfied;
the value of supply voltage is the minimum value or more of the rec-
ommended operating conditions.
• Reset occurs by built-in power-on reset (only for H version)
• Reset occurs by voltage drop detection circuit (only for H version)
Then when “H” level is applied to RESET pin, software starts from
address 0 in page 0.
Pull-up transistor
Internal reset signal
SRST instruction
RESET
pin
Power-on reset circuit(Note 3)
(Note 3)
Voltage drop detection circuit
Watchdog reset signal
(Note 2)
(Note 1)
WEF
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
3: These are equipped with only H version.
Fig. 40 Structure of reset pin and its peripherals
Reset input
1 machine cycle or more
0.85VDD
Program starts
(address 0 in page 0)
RESET
0.3VDD
(Note 1)
f(RING)
On-chip oscillator (internal oscillator) is
counted 120 to 144 times (Note 2).
Notes 1: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
2: It depends on the internal state at reset.
Fig. 41 RESET pin input waveform and reset release timing
Rev.1.02 2006.12.22 page 47 of 140
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4508 Group
(2) Power-on reset (only for H version)
Reset can be automatically performed at power on (power-on reset)
by the built-in power-on reset circuit. When the built-in power-on re-
set circuit is used, set the time for the supply voltage to rise from 0 V
to the minimum voltage of recommended operating conditions to
100 µs or less.
100 µs or less
V
DD
→ ←
Power-on reset
circuit output
If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and Vss at the shortest distance, and input “L” level to
RESET pin until the value of supply voltage reaches the minimum
operating voltage.
Reset
state
Internal reset signal
(3) System reset instruction (SRST)
By executing the SRST instruction, “L” level is output to RESET pin
and system reset is performed.
Reset released
Reset state
Power-on
Note: Keep the value of supply voltage to
the minimum value or more of the
recommended operating conditions.
Fig. 42 Power-on reset operation
Table 17 Port state at reset
State
Name
Function
D0, D1
High-impedance (Notes 1, 2)
D0, D1
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
D2/AIN4, D3/AIN5
P00/SIN, P01/SOUT, P02/SCK
P03
D2, D3
P00, P01, P02
P03
P10
P10
P11/CNTR1
P11
P12/CNTR0
P12
P13/INT
P13
P20/AIN0, P21/AIN1
P20, P21
Notes 1: Output latch is set to “1.”
2: The output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
Rev.1.02 2006.12.22 page 48 of 140
REJ03B0148-0102
4508 Group
(4) Internal state at reset
Figure 43 shows internal state at reset (they are the same after sys-
tem is released from reset). The contents of timers, registers, flags
and RAM except shown in Figure 43 are undefined, so set the initial
value to them.
• Program counter (PC) ............................................................................00000
Address 0 in page 0 is set to program counter.
0
0
0
0
0
0
0
0
0
• Interrupt enable flag (INTE)..................................................................................................
• Power down flag (P) .............................................................................................................
• External 0 interrupt request flag (EXF0) ..............................................................................
• Interrupt control register V1................................................................................000
• Interrupt control register V2................................................................................000
• Interrupt control register I1 .................................................................................000
• Timer 1 interrupt request flag (T1F) .....................................................................................
• Timer 2 interrupt request flag (T2F) .....................................................................................
• Watchdog timer flags (WDF1, WDF2)..................................................................................
• Watchdog timer enable flag (WEF) ......................................................................................
• Timer control register PA ......................................................................................................
• Timer control register W1 ...................................................................................000
• Timer control register W2 ...................................................................................000
• Timer control register W5 ...................................................................................000
• Timer control register W6 ...................................................................................000
• Clock control register MR ...................................................................................110
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
(Interrupt disabled)
(Interrupt disabled)
(Interrupt disabled)
(Prescaler stopped)
(Timer 1 stopped)
(Timer 2 stopped)
• Clock control register RG ..................................................................................................... 0 (On-chip oscillator operating)
• Serial interface transmit/receive completion flag (SIOF) .....................................................
• Serial interface control register J1 .....................................................................000
• Serial interface register SI .........................................................➀➀➀➀➀➀➀
• A/D conversion completion flag (ADF) .................................................................................
• A/D control register Q1 .......................................................................................000
• Successive comparison register AD ............................➀➀➀➀➀➀➀➀➀
• Comparator register...................................................................➀➀➀➀➀➀➀
• Key-on wakeup control register K0 ....................................................................000
• Key-on wakeup control register K1 ....................................................................000
• Key-on wakeup control register K2 ....................................................................000
• Key-on wakeup control register L1 ....................................................................000
• Pull-up control register PU0 ...............................................................................000
• Pull-up control register PU1 ...............................................................................000
• Pull-up control register PU2 ...............................................................................000
• Port output structure control register FR0 .........................................................000
• Port output structure control register FR1 .........................................................000
• Port output structure control register FR2 .........................................................000
• Port output structure control register FR3 .........................................................000
• Carry flag (CY)......................................................................................................................
• Register A ...........................................................................................................000
• Register B ...........................................................................................................000
• Register D .................................................................................................................➀➀
• Register E ..................................................................................➀➀➀➀➀➀➀
• Register X ...........................................................................................................000
• Register Y ...........................................................................................................000
• Register Z ........................................................................................................................➀
• Stack pointer (SP) ....................................................................................................11
• Operation source clock.......................................................... On-chip oscillator (operating)
• Ceramic resonator circuit ..................................................................................... Operating
• RC oscillation circuit ...................................................................................................... Stop
0
0
(Serial interface port not selected)
➀
0
0
➀
➀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
➀
➀
0
0
➀
1
“➀” represents undefined.
Fig. 43 Internal state at reset
Rev.1.02 2006.12.22 page 49 of 140
REJ03B0148-0102
4508 Group
VOLTAGE DROP DETECTION CIRCUIT
(only for H version)
(1) SVDE instruction
If the SVDE instruction is not executed (initial state), the voltage
drop detection circuit becomes invalid at RAM back-up mode.
When the SVDE instruction is executed, the voltage drop deteciton
circuit is valid even after system enters into the RAM back-up mode.
The SVDE instruction can be executed only once.
In order to release the execution of the SVDE instruction, the system
reset is required.
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer by outputting “L”
level to RESET pin if the supply voltage drops below a set value.
S
R
EPOF instruction +POF instruction
Internal reset signal
Key-on wakeup signa
Q
Q
S
R
SVDE instruction
Internal reset signal
Voltage drop detection circuit
Reset signal
–
+
VRST
Voltage drop detection circuit
Fig. 44 Voltage drop detection reset circuit
V
DD
+
V
RST (reset release voltage)
-
VRST
(
reset occurrence voltage
)
Voltage drop detection circuit
Reset signal
Microcomputer starts operation after
on-chip oscillator (internal oscillator)
clock is counted 120 to 144 times.
RESET pin
Note: Detection voltage hysteresis of voltage drop detection circuit is 0.2 V (Typ).
Fig. 45 Voltage drop detection circuit operation waveform
Table 18 Voltage drop detection circuit operation state
At CPU operating
At RAM back-up mode
SVDE instruction not executed
SVDE instruction executed
Valid
Valid
Invalid
Valid
Rev.1.02 2006.12.22 page 50 of 140
REJ03B0148-0102
4508 Group
RAM BACK-UP MODE
Table 19 Functions and states retained at RAM back-up
The 4508 Group has the RAM back-up mode.
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
RAM back-up
When the POF instruction is executed continuously after the EPOF
instruction, system enters the RAM back-up state.
The POF instruction is equal to the NOP instruction when the EPOF
instruction is not executed before the POF instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM.
✕
O
Interrupt control registers V1, V2
Interrupt control register I1
✕
O
Selected oscillation circuit (execution of CRCK)
Clock control register MR
O
✕
Table 19 shows the function and states retained at RAM back-up.
Figure 46 shows the state transition.
Clock control register RG
✕
Timer 1, Timer 2 function
(Note 3)
Watchdog timer function
✕ (Note 4)
(1) Identification of the start condition
Timer control register PA
✕
Warm start (return from the RAM back-up state) or cold start (return
from the normal reset state) can be identified by examining the state
of the power down flag (P) with the SNZP instruction.
Timer control registers W1, W2
Timer control registers W5, W6
Serial interface function
✕
O
✕
(2) Warm start condition
Serial interface control register J1
A/D conversion function
O
When the external wakeup signal is input after the system enters the
RAM back-up state by executing the EPOF instruction and POF in-
struction continuously, the CPU starts executing the program from
address 0 in page 0. In this case, the P flag is “1.”
✕
A/D control register Q1
O
Voltage drop detection circuit
Port level
(Note 5)
O
Key-on wakeup control registers K0 to K2, L1
Pull-up control registers PU0 to PU2
Port output structure control registers FR0 to FR3
External interrupt request flag (EXF0)
Timer interrupt request flags (T1F, T2F)
A/D conversion completion flag (ADF)
O
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
O
O
✕
• “L” level is applied to RESET pin,
• system reset (SRST) is performed,
• reset by watchdog timer is performed,
• reset by the built-in power-on reset circuit is performed (only for H
version), or
(Note 3)
✕
Serial interface transmit/receive completion flag
(SIOF)
✕
Interrupt enable flag (INTE)
✕
• reset by the voltage drop detection circuit is performed (only for H
version).
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
✕ (Note 4)
✕ (Note 4)
In this case, the P flag is “0.”
Notes 1:“O” represents that the function can be retained, and “✕” represents
that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction,
and then set the system to be in the RAM back-up mode.
5: The voltage drop detection circuit is equipped with only H version.
In the RAM back-up mode, when the SVDE instruction is not ex-
ecuted, the voltage drop detection circuit is invalid, and when the
SVDE instruction is executed, the voltage drop detection circuit is
valid.
Rev.1.02 2006.12.22 page 51 of 140
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4508 Group
• Pull-up control register PU0
(4) Return signal
Register PU0 controls the ON/OFF of the port P0 pull-up transis-
tor. Set the contents of this register through register A with the
TPU0A instruction. In addition, the TAK1 instruction can be used to
transfer the contents of register K0 to register A.
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped. Table 20 shows the return
condition for each return source.
• Pull-up control register PU1
(5) Control registers
Register PU1 controls the ON/OFF of the port P1 pull-up transis-
tor. Set the contents of this register through register A with the
TPU1A instruction. In addition, the TAPU1 instruction can be used
to transfer the contents of register PU1 to register A.
• Pull-up control register PU2
• Key-on wakeup control register K0
Register K0 controls the port P0 key-on wakeup function. Set the
contents of this register through register A with the TK0A instruc-
tion. In addition, the TAK0 instruction can be used to transfer the
contents of register K0 to register A.
Register PU2 controls the ON/OFF of the ports P2, D2 and D3 pull-
up transistor. Set the contents of this register through register A
with the TPU2A instruction. In addition, the TAPU2 instruction can
be used to transfer the contents of register PU2 to register A.
• Interrupt control register I1
• Key-on wakeup control register K1
Register K1 controls the port P1 key-on wakeup function. Set the
contents of this register through register A with the TK1A instruc-
tion. In addition, the TAK1 instruction can be used to transfer the
contents of register K1 to register A.
Register I1 controls the valid waveform/level of the external 0 inter-
rupt and the input control of INT pin. Set the contents of this
register through register A with the TI1A instruction. In addition, the
TAI1 instruction can be used to transfer the contents of register I1
to register A.
• Key-on wakeup control register K2
Register K2 controls the ports P2, D2 and D3 key-on wakeup func-
tion. Set the contents of this register through register A with the
TK2A instruction. In addition, the TAK2 instruction can be used to
transfer the contents of register K2 to register A.
• Key-on wakeup control register L1
Register L1 controls the selection of the return condition and valid
waveform/level of port P1, and the selection of the INT pin return
condition and INT pin key-on wakeup function. Set the contents of
this register through register A with the TL1A instruction. In addi-
tion, the TAL1 instruction can be used to transfer the contents of
register L1 to register A.
Table 20 Return source and return condition
Remarks
Return source
Return condition
The key-on wakeup function can be selected by one port unit. Set the port
using the key-on wakeup function to “H” level before going into the RAM
back-up state.
Port P00–P03
Port P20, P21
Port D2, D3
Return by an external “L” level in-
put.
The key-on wakeup function can be selected by one port unit. Select the
return level (“L” level or “H” level) and return condition (level or edge) with
the register L1 according to the external state before going into the RAM
back-up state.
Port P10–P13 Return by an external “H” level or
“L” level input, or falling edge
(“H”→“L”) or rising edge (“L”→“H”).
Before going into the RAM backup state, set an opposite level of the
selected return level (edge) to the port using the key-on wakeup function.
The key-on wakeup function can be selected by one port unit. Select the
return level (“L” level or “H” level) with the register I1 and return condition
(level or edge) with the register L1 according to the external state before
going into the RAM back-up state.
INT pin
Return by an external “H” level or
“L” level input, or falling edge
(“H”→“L”) or rising edge (“L”→“H”).
When the return level is input, the
EXF0 flag is not set.
Rev.1.02 2006.12.22 page 52 of 140
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4508 Group
Internal mode
D
Operating state
A
POF instruction execution
(Note 5)
Operating state
RAM back-up
(Note 1)
Operation source clock:
f(RING)
Reset
Key-on wakeup
(Note 6)
On-chip oscillator
(MR0)←1
(Note 3)
(MR0)←0
(Note 2)
CRCK instruction no execution
B
POF instruction execution
(Note 5)
Operating state
Operation source clock: f(XIN)
Ceramic resonator: operating
(Note 4)
CRCK instruction execution
C
POF instruction execution
(Note 5)
Operating state
Operation source clock: f(XIN)
RC oscillation
f(RING): stop
f(XIN): stop
High-speed mode
Notes 1: Microcomputer starts its operation after counting f(RING) 120 to 144 times from system is released from reset.
2: When changing the operation source clock from f(RING) to f(XIN), first make the setting to enable f(XIN) oscillation (set MR1 to “0”),
allow the oscillation stabilization time to elapse using software, and then set the operation source clock to f(XIN) (set MR0 to “0”).
After this, stop f(RING) (set RG0 to “1”). (Do not start f(XIN) oscillation and change the operation source clock at the same time.)
3: When changing the operation source clock from f(XIN) to f(RING), first make the setting to enable f(RING) oscillation (set RG0 to “0”),
allow the oscillation stabilization time to elapse using software, and then set the operation source clock to f(RING) (set MR0 to “1”).
After this, stop f(XIN) (set MR1 to “1”). (Do not change the operation source clock and stop f(XIN) at the same time.)
4: After system is released from reset, the ceramic oscillation circuit is selected for the main clock f(XIN).
When the RC oscillation circuit is used, execute the CRCK instruction.
5: Continuous execution of the EPOF instruction and the POF instruction is required to go into the RAM back-up state.
6: Microcomputer starts its operation after counting f(RING) 120 to 144 times.
System returns to state A certainly when returning from the RAM back-up mode. The operation mode (system clock frequency divided)
also returns to the initial state (internal frequency divided by 8 mode) (registers RG and MR initialized).
However, the selected contents (CRCK instruction execution state) of f(XIN) oscillation circuit is retained.
Fig. 46 State transition
Power down flag P
EPOF
instruction instruction
POF
+
Program start
S
Q
Yes
R
Reset input
P = “1”
?
SNTP
No
• • • • • • • EPOF instruction + POF instruction
✕ Set source
Warm start
Cold start
✕ Clear source• • • • • •Reset input
Fig. 47 Set source and clear source of the P flag
Fig. 48 Start condition identified example using the SNZP in-
struction
Rev.1.02 2006.12.22 page 53 of 140
REJ03B0148-0102
4508 Group
Table 21 Key-on wakeup control register
R/W
Key-on wakeup control register K0
at reset : 00002
at RAM back-up : state retained
TAK0/TK0A
Port P03 key-on wakeup
0
1
0
1
0
1
0
1
Key-on wakeup not used
K03
control bit
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Port P02 key-on wakeup
K02
control bit
Port P01 key-on wakeup
K01
control bit
Port P00 key-on wakeup
K00
control bit
R/W
Key-on wakeup control register K1
at reset : 00002
at RAM back-up : state retained
TAK1/TK1A
Port P13 key-on wakeup
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
K13
control bit
Port P12 key-on wakeup
K12
control bit
Port P11 key-on wakeup
K11
control bit
Port P10 key-on wakeup
K10
control bit
R/W
Key-on wakeup control register K2
at reset : 00002
at RAM back-up : state retained
TAK2/TK2A
Port D3 key-on wakeup
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
K23
control bit
Port D2 key-on wakeup
K22
control bit
Port P21 key-on wakeup
K21
control bit
Port P20 key-on wakeup
K20
control bit
R/W
Key-on wakeup control register L1
at reset : 00002
at RAM back-up : state retained
TAL1/TL1A
Ports P10–P13 return condition selection
0
1
0
1
0
1
0
1
Return by level
L13
bit
Return by edge
Ports P10–P13 valid waveform/
Falling waveform/“L” level
Rising waveform/“H” level
Return by level
L12
level selection bit
INT pin
L11
return condition selection bit
Return by edge
INT pin
L10
Key-on wakeup not used
Key-on wakeup used
key-on wakeup control bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
Rev.1.02 2006.12.22 page 54 of 140
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4508 Group
Table 22 Pull-up control register and interrupt control register
R/W
Pull-up control register PU0
at reset : 00002
at RAM back-up : state retained
TAPU0/TPU0A
Port P03 pull-up transistor
control bit
0
1
0
1
0
1
0
1
Pull-up transistor OFF
PU03
PU02
PU01
PU00
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Port P02 pull-up transistor
control bit
Port P01 pull-up transistor
control bit
Port P00 pull-up transistor
control bit
R/W
Pull-up control register PU1
at reset : 00002
at RAM back-up : state retained
TAPU1/TPU1A
Port P13 pull-up transistor
control bit
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
PU13
PU12
PU11
PU10
Port P12 pull-up transistor
control bit
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
control bit
R/W
Pull-up control register PU2
at reset : 00002
at RAM back-up : state retained
TAPU2/TPU2A
Port D3 pull-up transistor
control bit
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
PU23
PU22
PU21
PU20
Port D2 pull-up transistor
control bit
Port P21 pull-up transistor
control bit
Port P20 pull-up transistor
control bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
Rev.1.02 2006.12.22 page 55 of 140
REJ03B0148-0102
4508 Group
CLOCK CONTROL
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
The clock control circuit consists of the following circuits.
• On-chip oscillator (internal oscillator)
• Ceramic oscillation circuit
Figure 49 shows the structure of the clock control circuit.
The 4508 Group operates by the on-chip oscillator clock (f(RING))
which is the internal oscillator after system is released from reset.
Also, the ceramic resonator or the RC oscillation can be used for the
source oscillation (f(XIN)) of the 4508 Group.
• RC oscillation circuit
• Multi-plexer (clock selection circuit)
• Frequency divider
• Internal clock generating circuit
MR3, MR
11
2
Division circuit
divided by 8
System clock
Internal clock
generation circuit
(divided by 3)
10
01
00
divided by 4
divided by 2
MR
0
Instruction clock
(INSTCK)
f(RING)
1
On-chip oscillator
0
f(XIN
)
RG0
X
IN
Ceramic resonator
circuit
Multiplexer
X
OUT
Q
Q
S
CRCK instruction
Internal reset signal
R
RC oscillation circuit
MR1
Q
S
R
Key-on wakeup signal
EPOF instruction + POF instruction
Fig. 49 Clock control circuit structure
Rev.1.02 2006.12.22 page 56 of 140
REJ03B0148-0102
4508 Group
(1) On-chip oscillator operation
After system is released from reset, the MCU starts operation by the
clock output from the on-chip oscillator which is the internal oscilla-
tor.
Main clock f(XIN)
• Ceramic oscillation valid
• RC oscillation invalid
Reset
The clock frequency of the on-chip oscillator depends on the supply
voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
CRCK instruction
(2) Main clock generating circuit (f(XIN))
The ceramic resonator or RC oscillation can be used for the main
clock of this product.
• Ceramic oscillation invalid
• RC oscillation valid
After system is released from reset, the ceramic oscillation is active
for main clock.
Fig. 50 Switch to ceramic oscillation/RC oscillation
The ceramic oscillation is invalid and the RC oscillation circuit is
valid with the CRCK instruction.
Execute the CRCK instruction in the initial setting routine of program
(executing it in address 0 in page 0 is recommended).
The execution of the CRCK instruction can be valid only once.
Register MR controls the enable/disable of the oscillation and the
selection of the operation source clock.
4508
Do not execute the CRCK
instruction in program.
*
XIN
XOUT
Also, when the MCU operates only by the on-chip oscillator without
using main clock f(XIN), connect XIN pin to Vss and leave XOUT pin
open, and do not execute the CRCK instruction (Figure 51).
Fig. 51 Handling of XIN and XOUT when main clock is not used
(3) Ceramic resonator
When the ceramic resonator is used as the main clock (f(XIN)), con-
nect the ceramic resonator and the external circuit to pins XIN and
XOUT at the shortest distance. A feedback resistor is built in between
pins XIN and XOUT (Figure 52).
4508
Do not execute the CRCK
*
instruction in program.
X
IN
XOUT
Note: Externally connect a damping
resistor Rd depending on the
oscillation frequency.
Do not execute the CRCK instruction.
Rd
Set “0” to bit 0 of register MR after the oscillation stabilizing wait
time is generated by software to select the clock generated by the
ceramic oscillation circuit for the source oscillation clock.
(A feedback resistor is built-in.)
Use the resonator manu-
facturer’s recommended value
because constants such as ca-
pacitance depend on the
resonator.
CIN
COUT
(4) RC oscillation
When the RC oscillation is used as the main clock (f(XIN)), connect
the XIN pin to the external circuit of resistor R and the capacitor C at
the shortest distance and leave XOUT pin open. Then, execute the
CRCK instruction (Figure 53).
Fig. 52 Ceramic resonator external circuit
The frequency is affected by a capacitor, a resistor and a microcom-
puter. So, set the constants within the recommended operating
condition of the frequency limits.
4508
Execute the CRCK
instruction in program.
*
XIN
XOUT
R
C
Fig. 53 External RC circuit
Rev.1.02 2006.12.22 page 57 of 140
REJ03B0148-0102
4508 Group
(5) External clock
When the external signal clock is used for the main clock (f(XIN)),
connect the XIN pin to the clock source and leave XOUT pin open
(Figure 54). Do not execute the CRCK instruction in program.
Be careful that the maximum value of the oscillation frequency when
using the external clock differs from the value when using the ce-
ramic resonator (refer to the recommended operating condition).
Also, note that the RAM back-up mode (POF instruction) cannot be
used when using the external clock.
Do not execute the CRCK
instruction in program.
*
4508
V
DD
XIN
XOUT
V
SS
(6) Clock control register MR
Register MR controls the selection of operation mode and the opera-
tion source clock, and enable/stop of main clock. Set the contents of
this register through register A with the TMRA instruction. In addition,
the TAMR instruction can be used to transfer the contents of register
MR to register A.
External oscillation circuit
Fig. 54 External clock input circuit
(7) Clock control register RG
Register RG controls the on-chip oscillator. Set the contents of this
register through register A with the TRGA instruction.
Table 23 Clock control register MR
R/W
Clock control register MR
at reset : 11012
MR3 MR2
at RAM back-up : 11012
TAMR/TMRA
Operation mode
Through mode (frequency not divided)
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
Main clock (f(XIN)) oscillation enabled
Main clock (f(XIN)) oscillation stop
Main clock (f(XIN))
MR3
MR2
0
0
1
1
0
1
0
1
Operation mode selection bits
0
1
0
1
MR1
MR0
Main clock f(XIN) control bit (Notes 2, 5)
Operation source clock selection bit (Notes 3, 5)
On-chip oscillator clock (f(RING))
W
Clock control register RG
at reset : 02
at RAM back-up : 02
TRGA
On-chip oscillator (f(RING)) oscillation enabled
On-chip oscillator (f(RING)) oscillation stop
0
1
On-chip oscillator (f(RING)) control bit
(Note 4)
RG0
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Main clock cannot be stopped when the main clock is selected for the operation source clock.
3: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabiliz-
ing wait time by software first and set the oscillation of the destination clock to be enabled.
4: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock.
5: When changing the setting of MR1 and MR0 from “00” to “11”, make settings in the sequence “00” → “01” → “11”.
When changing the setting of MR1 and MR0 from “11” to “0”, make settings in the sequence “11” → “01” → “00”.
Rev.1.02 2006.12.22 page 58 of 140
REJ03B0148-0102
4508 Group
QzROM Writing Mode
In the QzROM writing mode, the user ROM area can be rewritten
while the microcomputer is mounted on-board by using a serial pro-
grammer which is applicable for this microcomputer.
Table 24 lists the pin description (QzROM writing mode) and Figure
55 shows the pin connections.
Refer to Figure 56 for examples of a connection with a serial pro-
grammer.
Contact the manufacturer of your serial programmer for serial pro-
grammer. Refer to the user’s manual of your serial programmer for
details on how to use it.
Table 24 Pin description (QzROM writing mode)
Pin
Name
I/O
Function
VDD
Power source
• Power supply voltage pin.
• GND pin.
VSS
GND
CNVSS
VPP input
• QzROM programmable power source pin.
• VPP input is possible with VSS connected via a resistor of about 5 kΩ.
P20/AIN0
P21/AIN1
SDA input/output
I/O
• QzROM serial data I/O pin.
SCLK input
Input
Input
Input
• QzROM serial clock input pin.
• QzROM read/program pulse input pin.
________
D3/AIN5
PGM input
Reset input
____________
RESET
• Reset input pin.
• Input “L” level signal.
XIN
Clock input
Clock output
I/O port
• Either connect an oscillation circuit or connect XIN pin to VSS and leave the
XOUT pin open.
XOUT
D0, D1, D2/AIN4,
P00/SIN, P01/SOUT,
P02/SCK, P03, P10,
P11/CNTR1,
I/O
• Input “H” or “L” level signal or leave the pin open.
P12/CNTR0, P13/INT
Rev.1.02 2006.12.22 page 59 of 140
REJ03B0148-0102
4508 Group
P0
P0
P0
0
1
2
/SIN
1
2
20
19
18
17
16
15
14
13
12
11
V
V
DD
SS
V
DD
SS
IN
OUT
/SOUT
/SCK
V
3
X
(Note 1)
4
P0
P1
P1
P1
3
0
1
2
X
5
CNVSS (Note 2)
RESET
V
PP
6
/CNTR1
/CNTR0
1kΩ
7
P2
P2
1
/AIN1
/AIN0
/AIN5
/AIN4
SCLK
8
P13/INT
0
SDA
9
D
0
1
PGM
D
D
3
2
10
D
Package type FP: PRSP0020DA-A (20P2N-A)
GP: PLSP0020JB-A (20P2F-A)
Notes 1: Either connect an oscillation circuit or connect XIN pin to VSS and leave
the XOUT pin open.
2: VPP input is possible with VSS connected via a resistor of about 5 kΩ.
: QzROM pin
Fig. 55 Pin connection diagram
Rev.1.02 2006.12.22 page 60 of 140
REJ03B0148-0102
4508 Group
4508 Group
T_VDD
T_VPP
V
DD
CNVSS
1 kΩ
T_TXD
T_RXD
P20/AIN0 (SDA)
P21/AIN1 (SCLK)
T_SCLK
T_BUSY
N.C.
D3/AIN5 (PGM)
T_PGM/OE/MD
RESET circuit
RESET
Vss
T_RESET
GND
X
IN
XOUT
Either connect an oscillation circuit or
connect XIN pin to VSS and leave the
XOUT pin open.
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig. 56 When using programmer of Suisei Electronics System Co., LTD, connection example
Rev.1.02 2006.12.22 page 61 of 140
REJ03B0148-0102
4508 Group
DATA REQUIRED FOR QzROM WRITING
ORDERS
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark specifica-
tion form, refer to the “Renesas Technology Corp.” Homepage (http:/
/www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
Rev.1.02 2006.12.22 page 62 of 140
REJ03B0148-0102
4508 Group
LIST OF PRECAUTIONS
✕ Multifunction
- The input/output of P00 can be used even when SIN is used. Be
careful when using inputs of both SIN and P00 since the input
threshold value of SIN pin is different from that of port P00.
- The input of P01 can be used even when SOUT is used.
- The input of P02 can be used even when SCK is used. Be careful
when using inputs of both SCK and P02 since the input threshold
value of SCK pin is different from that of port P02.
- The input of P11 can be used even when CNTR1 (output) is se-
lected.
✕Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
CNVSS pin is also used as VPP pin. Accordingly, when using this
pin, connect this pin to VSS through a resistor about 5 kΩ (connect
this resistor to CNVSS/VPP pin as close as possible).
The input/output of P11 can be used even when CNTR1 (input) is
selected. Be careful when using inputs of both CNTR1 and P11
since the input threshold value of CNTR1 pin is different from that
of port P11.
✕Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
- The input of P12 can be used even when CNTR0 (output) is se-
lected.
The input/output of P12 can be used even when CNTR0 (input) is
selected. Be careful when using inputs of both CNTR0 and P12
since the input threshold value of CNTR0 pin is different from that
of port P12.
In a system where the power source voltage drops slowly when the
power source voltage drops or the power supply is turned off, reset
a microcomputer when the supply voltage is less than the recom-
mended operating conditions and design a system not to cause
errors to the system by this unstable operation.
- The input/output of P13 can be used even when INT is used. Be
careful when using inputs of both INT and P13 since the input
threshold value of INT pin is different from that of port P13.
- The input/output of P20, P21, D2, D3 can be used even when AIN0,
AIN1, AIN4 or AIN5 are used.
✕Register initial values 1
The initial value of the following registers are undefined after sys-
tem is released from reset. After system is released from reset, set
✕Power-on reset (only for H version)
initial values.
When the built-in power-on reset circuit is used, set the time for
the supply voltage to rise from 0 V to the minimum voltage of rec-
ommended operating conditions to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and Vss at the shortest distance, and input “L” level to
RESET pin until the value of supply voltage reaches the minimum
operating voltage.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
✕Register initial values 2
The initial value of the following registers are undefined at RAM
back-up. After system is returned from RAM back-up, set initial val-
ues.
✕POF instruction
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
When the POF instruction is executed continuously after the EPOF
instruction, system enters the RAM back-up state.
Note that system cannot enter the RAM back-up state when ex-
ecuting only the POF instruction.
Be sure to disable interrupts by executing the DI instruction before
executing the EPOF instruction and the POF instruction continu-
ously.
✕Program counter
Make sure that the PCH does not specify after the last page of the
built-in ROM.
✕Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are eight identical registers, so that subrou-
tines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be care-
ful not to over the stack when performing these operations
together.
Rev.1.02 2006.12.22 page 63 of 140
REJ03B0148-0102
4508 Group
10
Note [3] on bit 2 of register I1
P13/INT pin
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the fol-
lowing notes.
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
• Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 59✕)
and then, change the bit 2 of register I1.
• Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 57✕)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 59✕).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 59✕).
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 57✕).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 57✕).
LA
4
8
; (✕✕✕02)
LA
4
; (✕✕✕02)
TV1A
LA
; The SNZ0 instruction is valid ...........✕
; (1✕✕✕2)
TV1A
LA
; The SNZ0 instruction is valid ...........✕
; (1✕✕✕2)
12
TI1A
NOP
SNZ0
; Control of INT pin input is changed
........................................................... ✕
; The SNZ0 instruction is executed
(EXF0 flag cleared)
TI1A
NOP
SNZ0
; Interrupt valid waveform is changed
........................................................... ✕
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
........................................................... ✕
NOP
........................................................... ✕
✕ : these bits are not used here.
Fig. 57 External 0 interrupt program example-1
✕ : these bits are not used here.
✕ Note [2] on bit 3 of register I1
Fig. 59 A/D conversion interrupt program example
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
• When the INT pin input is disabled (register I13 = “0”), set the key-
on wakeup of INT pin to be invalid (register L10 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 58✕).
LA
0
; (✕✕✕02)
TI1A
DI
; INT key-on wakeup disabled ...........✕
EPOF
POF2
; RAM back-up
✕ : these bits are not used here.
Fig. 58 External 0 interrupt program example-2
Rev.1.02 2006.12.22 page 64 of 140
REJ03B0148-0102
4508 Group
11
18
Prescaler
Watchdog timer
Stop prescaler counting and then execute the TABPS instruction
to read its data.
• The watchdog timer function is valid after system is released from
reset. When not using the watchdog timer function, execute the
DWDT instruction and the WRST instruction continuously, and
clear the WEF flag to “0” to stop the watchdog timer function.
• The contents of WDF1 flag and timer WDT are initialized at the
RAM back-up mode.
Stop prescaler counting and then execute the TPSAB instruction
to write data to prescaler.
12
Timer count source
Stop timer 1 or 2 counting to change its count source.
• When using the watchdog timer and the RAM back-up mode, ini-
tialize the WDF1 flag with the WRST instruction just before the
microcomputer enters the RAM back-up state.
13
Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 in-
struction to read its data.
Also, set the NOP instruction after the WRST instruction, for the
case when a skip is performed with the WRST instruction.
19 Clock control
14
Writing to the timer
Stop timer 1 or 2 counting and then execute the T1AB, T1R1L,
T2AB or T2R2L instruction to write data to timer.
When the RC oscillation is used as the main clock f(XIN), execute
the CRCK instruction in the initial setting routine of program (ex-
ecuting it in address 0 in page 0 is recommended).
15
Writing to reload register
The oscillation circuit by the CRCK instruction can be selected
only once. When the CRCK instruction is not executed, the ce-
ramic oscillation is selected for the main clock f(XIN).
Also, when the MCU operates only by the on-chip oscillator with-
out using main clock f(XIN), connect XIN pin to Vss and leave XOUT
pin open, and do not execute the CRCK instruction.
In order to switch the operation source clock (f(RING)) or f(XIN)),
generate the oscillation stabilizing wait time by software first and
set the oscillation of the destination clock to be enabled.
Registers RG and MR are initialized when system returns from
RAM back-up mode.
In order to write a data to the reload register R1H while the timer
1 is operating, execute the T1HAB instruction except a timing of
the timer 1 underflow.
In order to write a data to the reload register R2H while the timer
2 is operating, execute the T2HAB instruction except a timing of
the timer 2 underflow.
16
Prescaler, timer 1 and timer 2 count start timing and count time
when operation starts
Count starts from the first rising edge of the count source (2) after
prescaler and timer operations start (1).
However, the selected contents (CRCK instruction execution state)
of main clock (f(XIN)) oscillation circuit is retained.
Time to first underflow (3) is shorter (for up to 1 period of the count
source) than time among next underflow (4) by the timing to start
the timer and count source operations after count starts.
When selecting CNTR input as the count source of timer, timer
operates synchronizing with the count edge (falling edge or rising
edge) of CNTR input selected by software.
20
On-chip oscillator
The clock frequency of the on-chip oscillator depends on the sup-
ply voltage and the operation temperature range.
Be careful that variable frequencies when designing application products.
Also, when considering the oscillation stabilize wait time for switch-
ing clock, be careful that the variable frequency of the on-chip
oscillator clock.
✕
Count source
Count source
(When falling edge of
CNTR input is selected)
21
External clock
When the external clock is used for the main clock (f(XIN)), con-
nect the XIN pin to the clock source and leave XOUT pin open. Do
not execute the CRCK instruction in program.
Timer value
3
2
1
0
3
2
1
0
3
2
Timer underflow signal
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using
the ceramic resonator (refer to the recommended operating condi-
tion).
✕
✕
Timer start
✕
Also, note that the RAM back-up mode (POF instruction) cannot
be used when using the external clock.
Fig. 60 Timer count start timing and count time when operation starts
17
PWM signal (PWM1, PWM2)
If the timer 1 count stop timing and the timer 1 underflow timing
overlap during output of the PWM1 signal, a hazard may occur in
the PWM1 output waveform.
If the timer 2 count stop timing and the timer 2 underflow timing
overlap during output of the PWM2 signal, a hazard may occur in
the PWM2 output waveform.
Rev.1.02 2006.12.22 page 65 of 140
REJ03B0148-0102
4508 Group
23 Notes for the use of A/D conversion 2
22
Notes for the use of A/D conversion 1
Each analog input pin is equipped with a capacitor which is used to
compare the analog voltage. Accordingly, when the analog voltage
is input from the circuit with high-impedance and, charge/dis-
charge noise is generated and the sufficient A/D accuracy may not
be obtained. Therefore, reduce the impedance or, connect a ca-
pacitor (0.01 µF to 1 µF) to analog input pins (Figure 62).
When the overvoltage applied to the A/D conversion circuit may
occur, connect an external circuit in order to keep the voltage
within the rated range as shown the Figure 61. In addition, test the
application products sufficiently.
• TALA instruction
When the TALA instruction is executed, the low-order 2 bits of reg-
ister AD is transferred to the high-order 2 bits of register A,
simultaneously, the low-order 2 bits of register A is “0.”
• Do not change the operating mode (both A/D conversion mode and
comparator mode) of A/D converter with the bit 3 of register Q1
while the A/D converter is operating.
• Clear the bit 2 of register V2 to “0” to change the operating mode
from the comparator mode to A/D conversion mode.
• The A/D conversion completion flag (ADF) may be set when the
operating mode of the A/D converter is changed from the compara-
tor mode to the A/D conversion mode. Accordingly, set a value to
the bit 3 of register Q1, and execute the SNZAD instruction to clear
the ADF flag.
Sensor
AIN
LA
8
0
; (✕0✕✕2)
TV2A
LA
; The SNZAD instruction is valid ........✕
; (0✕✕✕2)
Apply the voltage withiin the specifications
to an analog input pin.
TQ1A
; Operation mode of A/D converter is
changed from comparator mode to A/D
conversion mode.
Fig. 62 Analog input external circuit example-1
SNZAD
NOP
About 1kΩ
✕ : this bit is not related to change the operation
Sensor
AIN
mode of A/D converter.
Fig. 61 External 0 interrupt program example-3
Fig. 63 Analog input external circuit example-2
Rev.1.02 2006.12.22 page 66 of 140
REJ03B0148-0102
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24
QzROM
(1) Be careful not to apply overvoltage to MCU. The contents of
QzROM may be overwritten because of overvoltage. Take care
especially at turning on the power.
(2) As for the product shipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approx.0.1 %
may occur. Moreover, please note the contact of cables and for-
eign bodies on a socket, etc. because a writing environment may
cause some writing errors.
25
Notes On ROM Code Protect
(QzROM product shipped after writing)
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the ROM option setup data in the
mask file which is submitted at ordering.
The ROM option setup data in the mask file is “0016” for protect
enabled or “FF16” for protect disabled.
Note that the mask file which has nothing at the ROM option data
or has the data other than “0016” and “FF16” can not be accepted.
Rev.1.02 2006.12.22 page 67 of 140
REJ03B0148-0102
4508 Group
NOTES ON NOISE
(2) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as
short as possible.
Countermeasures against noise are described below.
The following countermeasures are effective against noise in theory,
however, it is necessary not only to take measures as follows but to
evaluate before actual use.
• Make the length of wiring across the grounding lead of a capacitor
which is connected to an oscillator and the VSS pin of a microcom-
puter as short as possible.
• Separate the VSS pattern only for oscillation from other VSS pat-
terns.
1. Shortest wiring length
(1) Wiring for RESET pin
<Reason>
Make the length of wiring which is connected to the RESET pin as
short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring.
If noise enters clock I/O pins, clock waveforms may be deformed.
This may cause a program failure or program runaway. Also, if a po-
tential difference is caused by the noise between the VSS level of a
microcomputer and the VSS level of an oscillator, the correct clock
will not be input in the microcomputer.
<Reason>
In order to reset a microcomputer correctly, 1 machine cycle or more
of the width of a pulse input into the RESET pin is required.
If noise having a shorter pulse width than this is input to the RESET
input pin, the reset is released before the internal state of the micro-
computer is completely initialized.
Noise
This may cause a program runaway.
X
X
V
IN
X
X
V
IN
OUT
OUT
Noise
SS
SS
O.K.
N.G.
Reset
RESET
circuit
Fig. 65 Wiring for clock I/O pins
V
SS
V
SS
(3) Wiring to CNVSS pin
N.G.
Connect CNVSS pin to a GND pattern at the shortest distance.
The GND pattern is required to be as close as possible to the GND
supplied to VSS.
In order to improve the noise reduction, to connect a 5 kΩ resistor
serially to the CNVSS pin - GND line may be valid.
Reset
circuit
RESET
As well as the above-mentioned, in this case, connect to a GND pat-
tern at the shortest distance. The GND pattern is required to be as
close as possible to the GND supplied to VSS.
V
SS
V
SS
<Reason>
O.K.
Fig. 64 Wiring for the RESET pin
The CNVSS pin of the QzROM is the power source input pin for the
built-in QzROM. When programming in the built-in QzROM, the im-
pedance of the CNVSS pin is low to allow the electric current for
writing flow into the QzROM. Because of this, noise can enter easily.
If noise enters the CNVSS pin, abnormal instruction codes or data
are read from the built-in QzROM, which may cause a program run-
away.
(Note)
(Note)
The shortest
CNVSS
About 5kΩ
VSS
The shortest
Note: This indicates pin.
Fig. 66 Wiring for the CNVSS pin of the QzPROM
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2. Connection of bypass capacitor across VSS line and VDD line
Connect an approximately 0.1 µF bypass capacitor across the VSS
line and the VDD line as follows:
3. Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog sig-
nal line which is connected to an analog input pin in series.
Besides, connect the resistor to the microcomputer as close as
possible.
• Connect a bypass capacitor across the VSS pin and the VDD pin at
equal length.
• Connect a bypass capacitor across the VSS pin and the VDD pin
with the shortest possible wiring.
• Connect an approximately 1000 pF capacitor across the Vss pin
and the analog input pin. Besides, connect the capacitor to the Vss
pin as close as possible. Also, connect the capacitor across the
analog input pin and the Vss pin at equal length.
• Use lines with a larger diameter than other signal lines for VSS line
and VDD line.
• Connect the power source wiring via a bypass capacitor to the VSS
pin and the VDD pin.
<Reason>
Signals which is input in an analog input pin (such as an A/D con-
verter/comparator input pin) are usually output signals from sensor.
The sensor which detects a change of event is installed far from the
printed circuit board with a microcomputer, the wiring to an analog
input pin is longer necessarily. This long wiring functions as an an-
tenna which feeds noise into the microcomputer, which causes noise
to an analog input pin.
V
DD
V
DD
V
SS
V
SS
Noise
N.G.
O.K.
(Note)
Microcomputer
Fig. 67 Bypass capacitor across the VSS line and the VDD line
Analog
input pin
Thermistor
N.G.
O.K.
V
SS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 68 Analog signal line and a resistor and a capacitor
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4. Oscillator concerns
(3) Oscillator protection using Vss pattern
Take care to prevent an oscillator that generates clocks for a micro-
computer operation from being affected by other signals.
As for a two-sided printed circuit board, print a Vss pattern on the
underside (soldering side) of the position (on the component side)
where an oscillator is mounted.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as pos-
sible from signal lines where a current larger than the tolerance of
current value flows.
Connect the Vss pattern to the microcomputer Vss pin with the
shortest possible wiring. Besides, separate this Vss pattern from
other Vss patterns.
<Reason>
In the system using a microcomputer, there are signal lines for con-
trolling motors, LEDs, and thermal heads or others. When a large
current flows through those signal lines, strong noise occurs be-
cause of mutual inductance.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
(2) Installing oscillator away from signal lines where potential levels
change frequently
X
X
V
IN
Install an oscillator and a connecting pattern of an oscillator away
from signal lines where potential levels change frequently. Also, do
not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
OUT
SS
Separate the VSS line for oscillation from other VSS lines
<Reason>
Signal lines where potential levels change frequently (such as the
CNTR pin signal line) may affect other lines at signal rising edge or
falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a pro-
gram runaway.
Fig. 71 Vss pattern on the underside of an oscillator
5. Setup for I/O ports
Setup I/O ports using hardware and software as follows:
Microcomputer
<Hardware>
Mutual inductance
M
• Connect a resistor of 100 Ω or more to an I/O port in series.
X
X
IN
<Software>
Large
current
OUT
• As for an input port, read data several times by a program for
checking whether input levels are equal or not.
• As for an output port or an I/O port, since the output data may re-
verse because of noise, rewrite data to its port latch at fixed
periods.
V
SS
GND
Fig. 69 Wiring for a large current signal line
• Rewrite data to pull-up control registers at fixed periods.
6. Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be
detected by a software watchdog timer and the microcomputer can
be reset to normal operation. This is equal to or more effective than
program runaway detection by a hardware watchdog timer. The fol-
lowing shows an example of a watchdog timer provided by software.
In the following example, to reset a microcomputer to normal opera-
tion, the main routine detects errors of the interrupt processing
routine and the interrupt processing routine detects errors of the
main routine.
N.G.
Do not cross
CNTR
X
X
V
IN
OUT
SS
This example assumes that interrupt processing is repeated multiple
times in a single main routine processing.
Fig. 70 Wiring to a signal line where potential levels change fre-
quently
Rev.1.02 2006.12.22 page 70 of 140
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<The main routine>
• Assigns a single word of RAM to a software watchdog timer
(SWDT) and writes the initial value N in the SWDT once at each
execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ (Counts of interrupt processing executed in each main rou-
tine)
As the main routine execution cycle may change because of an in-
terrupt processing or others, the initial value N should have a
margin.
• Watches the operation of the interrupt processing routine by com-
paring the SWDT contents with counts of interrupt processing after
the initial value N has been set.
• Detects that the interrupt processing routine has failed and deter-
mines to branch to the program initialization routine for recovery
processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the
SWDT contents are reset to the initial value N at almost fixed
cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch
to the program initialization routine for recovery processing in the
following case:
If the SWDT contents are not initialized to the initial value N but
continued to decrement and if they reach 0 or less.
Interrupt processing routine
(SWDT) ← (SWDT)—1
Interrupt processing
Main routine
(SWDT)← N
EI
>0
Main processing
(SWDT)
≤0?
RTI
≠N
≤0
(SWDT)
=N?
Return
N
Interrupt processing
routine errors
Main routine
errors
Fig. 72 Watchdog timer by software
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CONTROL REGISTERS
R/W
Interrupt control register V1
at reset : 00002
at RAM back-up : 00002
TAV1/TV1A
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
Not used
V13
V12
V11
V10
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
External 0 interrupt enable bit
R/W
Interrupt control register V2
Serial interface interrupt enable bit
A/D interrupt enable bit
Not used
at reset : 00002
at RAM back-up : 00002
TAV2/TV2A
0
1
0
1
0
1
0
1
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
V23
V22
V21
V20
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Not used
R/W
Interrupt control register I1
at reset : 00002
INT pin input disabled
INT pin input enabled
at RAM back-up : state retained
TAI1/TI1A
0
1
INT pin input control bit (Note 2)
I13
I12
Falling waveform (“L” level of INT pin is recognized with the SNZI0
0
1
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
0
1
0
1
I11
I10
INT pin edge detection circuit control bit
INT pin
timer 1 control enable bit
Enabled
R/W
Clock control register MR
at reset : 11012
at RAM back-up : 11012
Operation mode
TAMR/TMRA
MR3 MR2
MR3
MR2
0
0
1
1
0
1
0
1
Through mode (frequency not divided)
Operation mode selection bits
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
Main clock (f(XIN)) oscillation enabled
Main clock (f(XIN)) oscillation stop
Main clock (f(XIN))
0
1
0
1
Main clock f(XIN) control bit (Note 3)
MR1
MR0
Operation source clock selection bit (Note 4)
On-chip oscillator clock (f(RING))
W
Clock control register RG
at reset : 02
at RAM back-up : 02
TRGA
On-chip oscillator (f(RING)) control bit
(Note 5)
0
1
On-chip oscillator (f(RING)) oscillation enabled
On-chip oscillator (f(RING)) oscillation stop
RG0
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
3: Main clock cannot be stopped when the main clock is selected for the operation source clock.
4: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabiliz-
ing wait time by software first and set the oscillation of the destination clock to be enabled.
5: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock.
Rev.1.02 2006.12.22 page 72 of 140
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4508 Group
W
Timer control register PA
Prescaler control bit
at reset : 02
at RAM back-up : 02
TPAA
Stop (state initialized)
Operating
0
1
PA0
R/W
at RAM back-up : 00002
Timer control register W1
PWM1 function control bit
at reset : 00002
TAW1/TW1A
PWM1 function invalid
PWM1 function valid
Stop (state retained)
Operating
0
1
0
1
W13
W12
Timer 1 control bit
Count source
W11
W10
W11
W10
PWM2 signal
0
0
1
1
0
1
0
1
Timer 1 count source selection bits
Prescaler output (ORCLK)
CNTR1 input
On-chip oscillator clock (f(RING))
R/W
Timer control register W2
PWM2 function control bit
at reset : 00002
at RAM back-up : 00002
TAW2/TW2A
0
1
0
1
PWM2 function invalid
PWM2 function valid
Stop (state retained)
Operating
W23
W22
Timer 2 control bit
W21 W20
Count source
W21
W20
0
0
1
1
0
1
0
1
Timer 1 underflow signal (T1UDF)
Prescaler output (ORCLK)
CNTR0 input
Timer 2 count source selection bits
System clock (STCK)
R/W
Timer control register W5
at reset : 00002
at RAM back-up : state retained
TAW5/TW5A
P12 (I/O) / CNTR0 (input)
0
1
0
1
0
1
0
1
W53
W52
W51
W50
P12/CNTR0 pin function selection bit
P12 (input) /CNTR0 (I/O)
Count auto-stop circuit not selected
Count auto-stop circuit selected
Count start synchronous circuit not selected
Count start synchronous circuit selected
Falling edge
Timer 1 count auto-stop circuit
selection bit (Note 2)
Timer 1 count start synchronous circuit
selection bit (Note 3)
CNTR0 pin input count edge selection bit
Rising edge
R/W
Timer control register W6
at reset : 00002
at RAM back-up : state retained
TAW6/TW6A
P11 (I/O) / CNTR1 (input)
0
1
0
1
0
1
0
1
W63
W62
W61
W60
P11/CNTR1 pin function selection bit
P11 (input) /CNTR1 (I/O)
Output auto-control circuit not selected
Output auto-control circuit selected
INT pin input period count circuit not selected
INT pin input period count circuit selected
Falling edge
CNTR 1 pin output auto-control circuit
selection bit
Timer 2
INT pin input period count circuit selection bit
CNTR1 pin input count edge selection bit
Rising edge
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”) and the timer 1 count start synchronous circuit is selected (W51=“1”).
3: This function is valid only when the INT pin/timer 1 control is enabled (I10=“1”).
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4508 Group
R/W
A/D control register Q1
at reset : 00002
at RAM back-up : state retained
TAQ1/TQ1A
A/D conversion mode
Comparator mode
0
1
A/D operation mode selection bit
Q13
Q12
Q12 Q11 Q10
Selected pins
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN0
AIN1
Not available
Not available
AIN4
Analog input pin selection bits
Q11
Q10
AIN5
Not available
Not available
R/W
Serial interface control register J1
at reset : 00002
J12
at RAM back-up : state retained
Synchronous clock
TAJ1/TJ1A
J13
0
J13
J12
0
1
Instruction clock (INSTCK) divided by 8
Serial interface synchronous clock
selection bits
0
Instruction clock (INSTCK) divided by 4
Instruction clock (INSTCK) divided by 2
External clock (SCK input)
0
1
1
1
J10
0
Port function
J11
0
J11
J10
P00, P01, P02 selected/SIN, SOUT, SCK not selected
P00, SOUT, SCK selected/SIN, P01, P02 not selected
SIN, P01, SCK selected/P00, SOUT, P02 not selected
SIN, SOUT, SCK selected/P00, P01, P02 not selected
1
0
Serial interface port function selection bits
0
1
1
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
Rev.1.02 2006.12.22 page 74 of 140
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4508 Group
R/W
Key-on wakeup control register K0
at reset : 00002
at RAM back-up : state retained
TAK0/TK0A
Port P03 key-on wakeup
control bit
0
1
0
1
0
1
0
1
Key-on wakeup not used
K03
K02
K01
K00
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Port P02 key-on wakeup
control bit
Port P01 key-on wakeup
control bit
Port P00 key-on wakeup
control bit
R/W
Key-on wakeup control register K1
at reset : 00002
at RAM back-up : state retained
TAK1/TK1A
Port P13 key-on wakeup
control bit
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
K13
K12
K11
K10
Port P12 key-on wakeup
control bit
Port P11 key-on wakeup
control bit
Port P10 key-on wakeup
control bit
R/W
Key-on wakeup control register K2
at reset : 00002
at RAM back-up : state retained
TAK2/TK2A
Port D3 key-on wakeup
control bit
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
K23
K22
K21
K20
Port D2 key-on wakeup
control bit
Port P21 key-on wakeup
control bit
Port P20 key-on wakeup
control bit
R/W
Key-on wakeup control register L1
at reset : 00002
at RAM back-up : state retained
TAL1/TL1A
Ports P10–P13 return condition selection
bit
0
1
0
1
0
1
0
1
Return by level
L13
L12
L11
L10
Return by edge
Ports P10–P13 valid waveform/
level selection bit
Falling waveform/“L” level
Rising waveform/“H” level
Return by level
INT pin
return condition selection bit
INT pin
Return by edge
Key-on wakeup not used
Key-on wakeup used
key-on wakeup control bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
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4508 Group
R/W
Pull-up control register PU0
at reset : 00002
at RAM back-up : state retained
TAPU0/TPU0A
Port P03 pull-up transistor
control bit
0
1
0
1
0
1
0
1
Pull-up transistor OFF
PU03
PU02
PU01
PU00
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Port P02 pull-up transistor
control bit
Port P01 pull-up transistor
control bit
Port P00 pull-up transistor
control bit
R/W
Pull-up control register PU1
at reset : 00002
at RAM back-up : state retained
TAPU1/TPU1A
Port P13 pull-up transistor
control bit
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
PU13
PU12
PU11
PU10
Port P12 pull-up transistor
control bit
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
control bit
R/W
Pull-up control register PU2
at reset : 00002
at RAM back-up : state retained
TAPU2/TPU2A
Port D3 pull-up transistor
control bit
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
PU23
PU22
PU21
PU20
Port D2 pull-up transistor
control bit
Port P21 pull-up transistor
control bit
Port P20 pull-up transistor
control bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
Rev.1.02 2006.12.22 page 76 of 140
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4508 Group
W
Port output structure control register FR0
at reset : 00002
at RAM back-up : state retained
TFR0A
0
1
0
1
0
1
0
1
N-channel open-drain output
CMOS output
FR03
FR02
FR01
FR00
Port P03 output structure selection bit
Port P02 output structure selection bit
Port P01 output structure selection bit
Port P00 output structure selection bit
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
W
Port output structure control register FR1
at reset : 00002
at RAM back-up : state retained
TFR1A
0
1
0
1
0
1
0
1
N-channel open-drain output
CMOS output
FR13
Port P13 output structure selection bit
Port P12 output structure selection bit
Port P11 output structure selection bit
Port P10 output structure selection bit
N-channel open-drain output
CMOS output
FR12
FR11
FR10
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
W
Port output structure control register FR2
at reset : 00002
at RAM back-up : state retained
TFR2A
0
1
0
1
0
1
0
1
FR23
Not used
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
FR22
FR21
FR20
Not used
N-channel open-drain output
CMOS output
Port P21 output structure selection bit
Port P20 output structure selection bit
N-channel open-drain output
CMOS output
W
Port output structure control register FR3
at reset : 00002
at RAM back-up : state retained
TFR3A
0
1
0
1
0
1
0
1
N-channel open-drain output
FR33
Port D3 output structure selection bit
Port D2 output structure selection bit
Port D1 output structure selection bit
Port D0 output structure selection bit
CMOS output
N-channel open-drain output
CMOS output
FR32
FR31
FR30
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
Notes 1: “R” represents read enabled, and “W” represents write enabled.
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INSTRUCTIONS
SYMBOL
Each instruction is described as follows;
(1) Index list of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
The symbols shown below are used in the following list of instruction
function and the machine instructions.
Symbol
Contents
Symbol
RPS
Contents
Prescaler reload register (8 bits)
Timer 1 reload register (8 bits)
Timer 1 reload register (8 bits)
Timer 2 reload register (8 bits)
Timer 2 reload register (8 bits)
Prescaler
A
B
Register A (4 bits)
Register B (4 bits)
R1L
R1H
R2L
R2H
PS
Register D (3 bits)
DR
E
Register E (8 bits)
Q1
V1
A/D control register Q1 (4 bits)
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W5 (4 bits)
Timer control register W6 (4 bits)
Port output structure control register FR0 (4 bits)
Port output structure control register FR1 (4 bits)
Port output structure control register FR2 (4 bits)
Port output structure control register FR3 (4 bits)
Serial interface control register J1 (4 bits)
Clock control register MR (4 bits)
Key-on wakeup control register K0 (4 bits)
Key-on wakeup control register K1 (4 bits)
Key-on wakeup control register K2 (4 bits)
Key-on wakeup control register L1 (4 bits)
Pull-up control register PU0 (4 bits)
Pull-up control register PU1 (4 bits)
Pull-up control register PU2 (4 bits)
Register X (4 bits)
V2
T1
Timer 1
I1
T2
Timer 2
W1
W2
W5
W6
FR0
FR1
FR2
FR3
J1
T1F
T2F
WDF1
WEF
INTE
EXF0
P
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
Power down flag
ADF
SIOF
A/D conversion completion flag
Serial interface transmit/receive completion flag
MR
K0
D
Port D (4 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (2 bits)
K1
P0
P1
P2
K2
L1
PU0
PU1
PU2
X
x
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
y
z
Register Y (4 bits)
Y
p
Z
Register Z (2 bits)
n
DP
Data pointer (10 bits)
i
(It consists of registers X, Y, and Z)
Program counter (14 bits)
j
PC
A3A2A1A0
PCH
PCL
SK
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
←
Direction of data movement
SP
Stack pointer (3 bits)
↔
?
Data exchange between a register and memory
Decision of state shown before “?”
CY
Carry flag
( )
—
Contents of registers and memories
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p6 p5 p4 p3 p2 p1 p0
M(DP)
a
p, a
C
+
x
Hex. C + Hex. number x (also same for others)
Note :The 4508 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the
number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.
Rev.1.02 2006.12.22 page 78 of 140
REJ03B0148-0102
4508 Group
INDEX LIST OF INSTRUCTION FUNCTION
Group-
Group-
ing
Mnemonic
Function
Mnemonic
XAMI j
Function
ing
TAB
(A) ← (B)
(B) ← (A)
(A) ← (Y)
(Y) ← (A)
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
TBA
TAY
(Y) ← (Y) + 1
TMA j
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
TYA
TEAB
(E7–E4) ← (B)
(E3–E0) ← (A)
LA n
(A) ← n
n = 0 to 15
TABE
(B) ← (E7–E4)
(A) ← (E3–E0)
TABP p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
(UPTF) = 1,
TDA
TAD
(DR2–DR0) ← (A2–A0)
(A2–A0) ← (DR2–DR0)
(A3) ← 0
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
TAZ
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(A) ← (X)
TAX
(SP) ← (SP) – 1
TASP
(A2–A0) ← (SP2–SP0)
(A3) ← 0
AM
(A) ← (A) + (M(DP))
AMC
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
LXY x, y
A n
(A) ← (A) + n
LZ z
INY
(Z) ← z z = 0 to 3
(Y) ← (Y) + 1
n = 0 to 15
AND
OR
(A) ← (A) AND (M(DP))
(A) ← (A) OR (M(DP))
(CY) ← 1
DEY
TAM j
(Y) ← (Y) – 1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
SC
RC
(CY) ← 0
XAM j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
SZC
CMA
RAR
(CY) = 0 ?
(A) ← (A)
XAMD j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
→ CY → A3A2A1A0
(Y) ← (Y) – 1
Note: p is 0 to 31.
Rev.1.02 2006.12.22 page 79 of 140
REJ03B0148-0102
4508 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Group-
ing
Group-
ing
Mnemonic
Function
Mnemonic
DI
Function
SB j
(Mj(DP)) ← 1
j = 0 to 3
(INTE) ← 0
(INTE) ← 1
EI
RB j
(Mj(DP)) ← 0
SNZ0
V10 = 0: (EXF0) = 1 ?
(EXF0) ← 0
j = 0 to 3
V10 = 1: SNZ0 = NOP
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
SNZI0
I12 = 0 : (INT) = “L” ?
I12 = 1 : (INT) = “H” ?
SEAM
SEA n
(A) = (M(DP)) ?
TAV1
TV1A
TAV2
TV2A
TAI1
(A) ← (V1)
(V1) ← (A)
(A) ← (V2)
(V2) ← (A)
(A) ← (I1)
(A) = n ?
n = 0 to 15
B a
(PCL) ← a6–a0
BL p, a
(PCH) ← p (Note)
(PCL) ← a6–a0
BLA p
BM a
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
TI1A
(I1) ← (A)
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
TPAA
TAW1
TW1A
TAW2
TW2A
TAW5
TW5A
TAW6
TW6A
TABPS
(PA) ← (A)
(A) ← (W1)
(W1) ← (A)
(A) ← (W2)
(W2) ← (A)
(A) ← (W5)
(W5) ← (A)
(A) ← (W6)
(W6) ← (A)
(PCL) ← a6–a0
BML p, a (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← a6–a0
BMLA p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
RTI
RT
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
TPSAB
TAB1
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
(B) ← (T17–T14)
(A) ← (T13–T10)
Note: p is 0 to 31.
Rev.1.02 2006.12.22 page 80 of 140
REJ03B0148-0102
4508 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Group-
ing
Group-
ing
Mnemonic
Function
Mnemonic
SZD
Function
T1AB
(R1L7–R1L4) ← (B)
(D(Y)) = 0 ?
(Y) = 0 to 3
(T17–T14) ← (B)
(R1L3–R1L0) ← (A)
(T13–T10) ← (A)
TFR0A
TFR1A
TFR2A
TFR3A
TK0A
(FR0) ← (A)
(FR1) ← (A)
(FR2) ← (A)
(FR3) ← (A)
(K0) ← (A)
(A) ← (K0)
(K1) ← (A)
(A) ← (K1)
(K2) ← (A)
(A) ← (K2)
(PU0) ← (A)
(A) ← (PU0)
(PU1) ← (A)
(A) ← (PU1)
(PU2) ← (A)
(A) ← (PU2)
(L1) ← (A)
T1HAB
TAB2
(R1H7–R1H4) ← (B)
(R1H3–R1H0) ← (A)
(B) ← (T27–T24)
(A) ← (T23–T20)
T2AB
(R2L7–R2L4) ← (B)
(T27–T24) ← (B)
(R2L3–R2L0) ← (A)
(T23–T20) ← (A)
TAK0
TK1A
T2HAB
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
TAK1
T1R1L
T2R2L
SNZT1
(T17–T10) ← (R1L7–R1L0)
(T27–T20) ← (R2L7–R2L0)
TK2A
TAK2
V12 = 0: (T1F) = 1 ?
(T1F) ← 0
V12 = 1: SNZT1 = NOP
TPU0A
TAPU0
TPU1A
TAPU1
TPU2A
TAPU2
TL1A
SNZT2
V13 = 0: (T2F) = 1 ?
(T2F) ← 0
V13 = 1: SNZT2 = NOP
IAP0
OP0A
IAP1
OP1A
IAP2
(A) ← (P0)
(P0) ← (A)
(A) ← (P1)
(P1) ← (A)
TAL1
(A) ← (L1)
(A1, A0) ← (P21, P20)
(A3, A2) ← 0
OP2A
CLD
RD
(P21, P20) ← (A1, A0)
(D) ← 1
(D(Y)) ← 0
(Y) = 0 to 3
SD
(D(Y)) ← 1
(Y) = 0 to 3
Rev.1.02 2006.12.22 page 81 of 140
REJ03B0148-0102
4508 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Group-
ing
Group-
ing
Mnemonic
Function
Mnemonic
NOP
Function
TABSI
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
(PC) ← (PC) + 1
POF
RAM back-up
TSIAB
SST
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
(SIOF) ← 0
Serial interface transmit/receive starting
EPOF
SNZP
DWDT
POF instruction valid
(P) = 1 ?
SNZSI
V23=0: (SIOF)=1?
(SIOF) ← 0
Stop of watchdog timer function enabled
V23 = 1: SNZSI = NOP
WRST
(WDF1) = 1 ?,
TAJ1
(A) ← (J1)
(WDF1) ← 0
TJ1A
(J1) ← (A)
SRST
RUPT
SUPT
SVDE**
System reset
(UPTF) ← 0
(UPTF) ← 1
CRCK
TRGA
TAMR
TMRA
TABAD
RC oscillator selected
(RG0) ← (A0)
(A) ← (MR)
Voltage drop detection circuit valid at RAM back-
up
(MR) ← (A)
Q13 = 0,
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
Q13 = 1,
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
TALA
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
TADAB
Q13 = 1 : (AD7–AD4) ← (B)
(AD3–AD0) ← (A)
Q13 = 0 : TABAD = NOP
TAQ1
TQ1A
ADST
(A) ← (Q1)
(Q1) ← (A)
(ADF) ← 0
Q13 = 0 : A/D conversion starting
Q13 = 1 : Comparator operation starting
SNZAD
V22 = 0: (ADF) = 1 ?
(ADF) ← 0
V22 = 1: SNZAD = NOP
Note: The SVDE instruction can be used only in the H version.
Rev.1.02 2006.12.22 page 82 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction
D9
D0
n
Number of Number of Flag CY
Skip condition
Overflow = 0
words
cycles
code
0
0
0
1
1
0
n
n
n
0
2
0
0
6
9
0
0
n
16
16
16
16
2
2
2
2
1
1
–
Grouping:
Arithmetic operation
Operation:
(A) ← (A) + n
n = 0 to 15
Description: Adds the value n in the immediate field to
register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no
overflow as the result of operation.
Executes the next instruction when there is
overflow as the result of operation.
ADST (A/D conversion STart)
Instruction
Flag CY
–
Skip condition
–
D9
D0
1
Number of Number of
words
cycles
code
1
0
1
0
0
1
1
1
1
F
A
B
1
1
Grouping:
A/D conversion operation
Operation:
(ADF) ← 0
Q13 = 0: A/D conversion starting
Description: Clears (0) to A/D conversion completion
flag ADF, and the A/D conversion at the A/D
conversion mode (Q13 = 0) or the compara-
tor operation at the comparator mode (Q13
= 1) is started.
Q13 = 1: Comparator operation starting
(Q13 : bit 3 of A/D control register Q1)
AM (Add accumulator and Memory)
Instruction
D9
D0
0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
0
0
0
0
0
0
1
0
1
1
1
–
Grouping:
Arithmetic operation
Operation:
(A) ← (A) + (M(DP))
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents
of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction
Flag CY
0/1
Skip condition
–
D9
D0
1
Number of Number of
words
cycles
code
0
0
0
0
0
0
1
0
1
1
1
Grouping:
Arithmetic operation
Operation:
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
Description: Adds the contents of M(DP) and carry flag
CY to register A. Stores the result in regis-
ter A and carry flag CY.
Rev.1.02 2006.12.22 page 83 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
AND (logical AND between accumulator and memory)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
1
1
0
0
0
0
1
8
16
2
1
1
–
Grouping:
Arithmetic operation
Operation:
(A) ← (A) AND (M(DP))
Description: Takes the AND operation between the con-
tents of register A and the contents of
M(DP), and stores the result in register A.
B a (Branch to address a)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
words
cycles
8
+a
code
0
1
1
a6 a5 a4 a3 a2 a1 a0
1
a
16
2
1
1
Grouping:
Branch operation
Operation:
(PCL) ← a6 to a0
Description: Branch within a page : Branches to address
a in the identical page.
Note:
Specify the branch address within the page
including this instruction.
BL p, a (Branch Long to address a in page p)
Number of Flag CY
cycles
Instruction
D9
D0
Number of
words
Skip condition
–
E
+p
code
0
0
0
1
0
1
1
p4 p3 p2 p1 p0
0
2
p
a
16
16
2
2
2
2
–
1
a6 a5 a4 a3 a2 a1 a0
a
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
Operation:
(PCH) ← p
(PCL) ← a6 to a0
a in page p.
Note:
p is 0 to 31.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
2
1
p
0
p
16
16
2
2
2
2
–
1
p4
p3 p2 p1 p0
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
(DR2 DR1 DR0 A3 A2 A1 A0)2 specified by
registers D and A in page p.
Operation:
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
Note:
p is 0 to 31.
Rev.1.02 2006.12.22 page 84 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BM a (Branch and Mark to address a in page 2)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
1
0
a6 a5 a4 a3 a2 a1 a0
1
a
a
16
2
1
1
–
Grouping:
Subroutine call operation
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
Description: Call the subroutine in page 2 : Calls the
subroutine at address a in page 2.
Note:
Subroutine extending from page 2 to an-
other page can also be called with the BM
instruction when it starts on page 2.
(PCL) ← a6–a0
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
BML p, a (Branch and Mark Long to address a in page p)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
C
+p
words
cycles
code
0
0
0
1
0
1
0
p4 p3 p2 p1 p0
0
2
p
a
16
16
2
2
2
2
1
a6 a5 a4 a3 a2 a1 a0
a
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
address a in page p.
Note:
p is 0 to 31.
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
(PCL) ← a6–a0
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
2
3
p
0
p
16
16
2
2
2
2
–
1
p4
p3 p2 p1 p0
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address (DR2 DR1 DR0 A3 A2 A1 A0)2 speci-
fied by registers D and A in page p.
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
Note:
p is 0 to 31.
(PCL) ← (DR2–DR0, A3–A0)
Be careful not to over the stack because the
maximum level of subroutine nesting is 8.
CLD (CLear port D)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
1
words
cycles
code
0
0
0
0
0
1
0
0
0
0
1
1
16
2
1
1
Grouping:
Input/Output operation
Operation:
(D) ← 1
Description: Sets (1) to port D.
Rev.1.02 2006.12.22 page 85 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
CMA (CoMplement of Accumulator)
Instruction
D9
D0
0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
1
1
1
0
0
2
0
1
9
1
C
B
7
16
16
16
16
2
2
2
2
1
1
–
Grouping:
Arithmetic operation
Operation:
(A) ← (A)
Description: Stores the one’s complement for register
A’s contents in register A.
CRCK (Clock select: Rc oscillation ClocK)
Instruction
Number of Number of
Flag CY
–
Skip condition
–
D9
D0
1
words
cycles
code
1
0
1
0
0
1
1
0
1
1
1
Grouping:
Other operation
Operation:
RC oscillation circuit selected
Description: Selects the RC oscillation circuit for main
clock f(XIN).
DEY (DEcrement register Y)
Number of Flag CY
cycles
Instruction
code
D9
0
D0
1
Number of
words
Skip condition
(Y) = 15
0
0
0
0
1
0
1
1
1
1
–
Grouping:
RAM addresses
Operation:
(Y) ← (Y) – 1
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the con-
tents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
DI (Disable Interrupt)
Instruction
D9
D0
0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
0
0
1
0
0
0
4
1
1
–
Grouping:
Interrupt control operation
Operation:
(INTE) ← 0
Description: Clears (0) to interrupt enable flag INTE, and
disables the interrupt.
Note:
Interrupt is disabled by executing the DI in-
struction after executing 1 machine cycle.
Rev.1.02 2006.12.22 page 86 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
DWDT (Disable WatchDog Timer)
Instruction
D9
D0
0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
1
0
0
1
1
1
0
2
0
0
2
9
0
5
6
C
16
16
16
16
2
2
2
2
1
1
–
Grouping:
Other operation
Operation:
Stop of watchdog timer function enabled
Description: Stops the watchdog timer function by the
WRST instruction after executing the
DWDT instruction.
EI (Enable Interrupt)
Instruction
Flag CY
–
Skip condition
–
D9
D0
1
Number of Number of
words
cycles
code
0
0
0
0
0
0
0
1
0
1
0
5
1
1
Grouping:
Interrupt control operation
Operation:
(INTE) ← 1
Description: Sets (1) to interrupt enable flag INTE, and
enables the interrupt.
Note:
Interrupt is enabled by executing the EI in-
struction after executing 1 machine cycle.
EPOF (Enable POF instruction)
Instruction
D9
D0
1
Number of Number of Flag CY
words
Skip condition
–
cycles
code
0
0
0
1
0
1
1
0
B
1
1
–
Grouping:
Other operation
Operation:
POF instruction valid
Description: Makes the immediate after POF instruction
valid by executing the EPOF instruction.
IAP0 (Input Accumulator from port P0)
Instruction
Flag CY
–
Skip condition
–
D9
D0
0
Number of Number of
words
cycles
code
1
0
0
1
1
0
0
0
0
1
1
Grouping:
Input/Output operation
Operation:
(A) ← (P0)
Description: Transfers the input of port P0 to register A.
Rev.1.02 2006.12.22 page 87 of 140
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4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP1 (Input Accumulator from port P1)
Instruction
D9
D0
1
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
1
1
0
0
0
0
1
1
n
2
2
0
0
6
6
1
7
1
2
3
n
16
16
16
16
2
2
2
2
1
1
–
Grouping:
Input/Output operation
Operation:
(A) ← (P1)
Description: Transfers the input of port P1 to register A.
IAP2 (Input Accumulator from port P2)
Instruction
Flag CY
–
Skip condition
–
D9
D0
0
Number of Number of
words
cycles
code
1
0
0
1
1
0
1
1
0
0
n
0
0
n
1
1
Grouping:
Input/Output operation
Operation:
(A1, A0) ← (P21, P20)
(A3, A2) ← 0
Description: Transfers the input of port P2 to the low-or-
der 2 bits (A1, A0) of register A.
Note:
After this instruction is executed, “0” is
stored to the high-order 2 bits (A3, A2) of
register A.
INY (INcrement register Y)
Instruction
Number of Flag CY
cycles
D9
D0
1
Number of
words
Skip condition
(Y) = 0
code
0
0
0
0
0
1
1
–
Grouping:
RAM addresses
Operation:
(Y) ← (Y) + 1
Description: Adds 1 to the contents of register Y. As a re-
sult of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.
LA n (Load n in Accumulator)
Instruction
D9
D0
n
Number of Number of Flag CY
words
Skip condition
cycles
code
0
0
0
1
1
1
1
–
Continuous
description
Grouping:
Arithmetic operation
Operation:
(A) ← n
n = 0 to 15
Description: Loads the value n in the immediate field to
register A.
When the LA instructions are continuously
coded and executed, only the first LA in-
struction is executed and other LA
instructions coded continuously are
skipped.
Rev.1.02 2006.12.22 page 88 of 140
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
LXY x, y (Load register X and Y with x and y)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
words
cycles
code
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3
0
0
2
x
4
0
2
y
16
16
16
16
2
2
2
2
1
1
–
Continuous
description
Grouping:
RAM addresses
Operation:
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
Description: Loads the value x in the immediate field to
register X, and the value y in the immediate
field to register Y. When the LXY instruc-
tions are continuously coded and executed,
only the first LXY instruction is executed
and other LXY instructions coded continu-
ously are skipped.
LZ z (Load register Z with z)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
8
cycles
code
0
0
0
1
0
0
1
0
z1 z0
+z
1
1
Grouping:
RAM addresses
Operation:
(Z) ← z z = 0 to 3
Description: Loads the value z in the immediate field to
register Z.
NOP (No OPeration)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
0
0
0
0
0
0
1
1
–
Grouping:
Other operation
Operation:
(PC) ← (PC) + 1
Description: No operation; Adds 1 to program counter
value, and others remain unchanged.
OP0A (Output port P0 from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
0
Number of Number of
words
cycles
code
1
0
0
0
1
0
0
0
0
0
1
1
Grouping:
Input/Output operation
Operation:
(P0) ← (A)
Description: Outputs the contents of register A to port
P0.
Rev.1.02 2006.12.22 page 89 of 140
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP1A (Output port P1 from Accumulator)
Instruction
D9
D0
1
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
0
1
0
0
0
0
2
2
2
1
0
1
2
9
2
16
16
16
16
2
1
1
–
Grouping:
Input/Output operation
Operation:
(P1) ← (A)
Description: Outputs the contents of register A to port
P1.
OP2A (Output port P2 from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
0
Number of Number of
words
cycles
code
1
0
0
0
1
0
0
0
1
2
2
1
1
Grouping:
Input/Output operation
Operation:
(P21, P20) ← (A1, A0)
Description: Outputs the contents of the low-order 2 bits
(A1, A0) of register A to port P2.
OR (logical OR between accumulator and memory)
Instruction
Number of Flag CY
cycles
D9
D0
Number of
words
Skip condition
–
code
0
0
0
0
0
1
1
0
0
1
0
2
1
1
–
Grouping:
Arithmetic operation
Operation:
(A) ← (A) OR (M(DP))
Description: Takes the OR operation between the con-
tents of register A and the contents of
M(DP), and stores the result in register A.
POF (Power OFF)
Instruction
D9
D0
0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
0
0
0
0
0
0
0
0
1
0
2
1
1
–
Grouping:
Other operation
Operation:
RAM back-up
Description: Puts the system in RAM back-up state by ex-
ecuting the POF instruction after executing
the EPOF instruction.
Note:
If the EPOF instruction is not executed just
before this instruction, this instruction is
equivalent to the NOP instruction.
Rev.1.02 2006.12.22 page 90 of 140
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RAR (Rotate Accumulator Right)
Instruction
D9
D0
1
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
1
1
1
0
1
1
1
0
0
0
0
0
1
4
0
1
D
16
16
16
16
2
2
2
2
1
1
0/1
Grouping:
Arithmetic operation
Operation:
→ CY → A3A2A1A0
Description: Rotates 1 bit of the contents of register A in-
cluding the contents of carry flag CY to the
right.
RB j (Reset Bit)
Instruction
Number of Number of
Flag CY
–
Skip condition
–
D9
D0
j
words
cycles
C
+j
code
0
0
0
1
0
0
j
1
1
Grouping:
Bit operation
Operation:
(Mj(DP)) ← 0
j = 0 to 3
Description: Clears (0) the contents of bit j (bit specified
by the value j in the immediate field) of
M(DP).
RC (Reset Carry flag)
Instruction
D9
D0
0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
0
1
6
1
1
0
Grouping:
Arithmetic operation
Operation:
(CY) ← 0
Description: Clears (0) to carry flag CY.
RD (Reset port D specified by register Y)
Instruction
Number of Number of
Flag CY
–
Skip condition
–
D9
D0
0
words
cycles
code
0
0
0
0
0
1
0
1
0
4
1
1
Grouping:
Input/Output operation
Operation:
(D(Y)) ← 0
However,
Description: Clears (0) to a bit of port D specified by register Y.
Note:
(Y) = 0 to 3.
Do not execute this instruction if values ex-
cept above are set to register Y.
(Y) = 0 to 3
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RT (ReTurn from subroutine)
Instruction
D9
D0
0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
4
4
4
5
4
6
5
8
16
16
16
16
2
2
2
2
1
2
–
Operation:
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine.
RTI (ReTurn from Interrupt)
Instruction
Number of Number of
words
Flag CY
–
Skip condition
–
D9
D0
0
cycles
code
0
0
0
1
0
0
0
1
1
1
Grouping:
Return operation
Operation:
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Description: Returns from interrupt service routine to
main routine.
Returns each value of data pointer (X, Y, Z),
carry flag, skip status, NOP mode status by
the continuous description of the LA/LXY in-
struction, register A and register B to the
states just before interrupt.
RTS (ReTurn from subroutine and Skip)
Instruction
Number of Flag CY
cycles
D9
D0
1
Number of
words
Skip condition
code
0
0
0
1
0
0
0
1
1
2
–
Skip at uncondition
Grouping:
Return operation
Operation:
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Description: Returns from subroutine to the routine
called the subroutine, and skips the next in-
struction at uncondition.
RUPT (Reset UPT flag)
Instruction
D9
D0
0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
0
0
0
1
0
1
1
0
1
1
–
Grouping:
Other operation
Operation:
(UPTF) ← 0
Description: Clears (0) to the high-order bit reference
enable flag UPTF.
Rev.1.02 2006.12.22 page 92 of 140
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SB j (Set Bit)
Instruction
D9
D0
j
Number of Number of Flag CY
Skip condition
–
words
cycles
C
code
0
0
0
1
0
1
1
1
j
0
0
0
5
0
1
+j
16
16
16
2
2
2
1
1
–
Grouping:
Bit operation
Operation:
(Mj(DP)) ← 0
j = 0 to 3
Description: Sets (1) the contents of bit j (bit specified by
the value j in the immediate field) of M(DP).
SC (Set Carry flag)
Instruction
Number of Number of
Flag CY
1
Skip condition
–
D9
D0
1
words
cycles
code
0
0
0
0
0
0
0
1
1
7
1
1
Grouping:
Arithmetic operation
Operation:
(CY) ← 1
Description: Sets (1) to carry flag CY.
SD (Set port D specified by register Y)
Instruction
D9
D0
1
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
1
0
1
0
5
1
1
–
Grouping:
Input/Output operation
Operation:
(D(Y)) ← 1
(Y) = 0 to 3
Description: Sets (1) to a bit of port D specified by register Y.
Note:
(Y) = 0 to 3.
Do not execute this instruction if values ex-
cept above are set to register Y.
SEA n (Skip Equal, Accumulator with immediate data n)
Number of Number of
Flag CY
–
Skip condition
(A) = n
Instruction
D9
D0
words
cycles
code
0
0
0
0
0
0
1
1
1
0
1
0
n
1
n
0
n
1
0
0
2
7
5
n
16
16
2
2
2
2
0
n
Grouping:
Comparison operation
Description: Skips the next instruction when the con-
tents of register A is equal to the value n in
the immediate field.
Operation:
(A) = n ?
n = 0 to 15
Executes the next instruction when the con-
tents of register A is not equal to the value n
in the immediate field.
Rev.1.02 2006.12.22 page 93 of 140
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SEAM (Skip Equal, Accumulator with Memory)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
(A) = (M(DP))
words
cycles
code
0
0
0
0
1
0
0
1
1
0
0
2
6
16
2
1
1
–
Grouping:
Comparison operation
Operation:
(A) = (M(DP)) ?
Description: Skips the next instruction when the con-
tents of register A is equal to the contents of
M(DP).
Executes the next instruction when the con-
tents of register A is not equal to the
contents of M(DP).
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
Number of Number of
Flag CY
–
Skip condition
Instruction
D9
D0
words
cycles
code
0
0
0
0
1
1
1
0
0
0
0
3
8
16
2
1
1
V10 = 0: (EXF0) = 1
Grouping:
Interrupt operation
Operation:
V10 = 0: (EXF0) = 1 ?
(EXF0) ← 0
V10 = 1: SNZ0 = NOP
Description: When V10 = 0 : Clears (0) to the EXF0 flag
and skips the next instruction when external
0 interrupt request flag EXF0 is “1.” When
the EXF0 flag is “0,” executes the next in-
struction.
(V10 : bit 0 of the interrupt control register V1)
When V10 = 1 : This instruction is equiva-
lent to the NOP instruction.
SNZAD (Skip if Non Zero condition of A/D conversion completion flag)
Number of Flag CY
cycles
Instruction
D9
D0
Number of
words
Skip condition
code
1
0
1
0
0
0
0
1
1
1
2
8
7
16
2
1
1
–
V22 = 0: (ADF) = 1
Grouping:
A/D conversion operation
Operation:
V22 = 0: (ADF) = 1 ?
Description: When V22 = 0 : Clears (0) to the ADF flag
and skips the next instruction when A/D
conversion completion flag ADF is “1.”
When the ADF flag is “0,” executes the next
instruction.
(ADF) ← 0
V22 = 1: SNZAD = NOP
(V22 : bit 2 of the interrupt control register V2)
When V22 = 1 : This instruction is equiva-
lent to the NOP instruction.
SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
words
cycles
code
0
0
0
0
1
1
1
0
1
0
0
3
A
16
2
1
1
–
I12 = 0 : (INT) = “L”
I12 = 1 : (INT) = “H”
Grouping:
Interrupt operation
Operation:
I12 = 0 : (INT) = “L” ?
I12 = 1 : (INT) = “H” ?
Description: When I12 = 0 : Skips the next instruction
when the level of INT pin is “L.” Executes
the next instruction when the level of INT
pin is “H.”
(I12 : bit 2 of the interrupt control register I1)
When I12 = 1 : Skips the next instruction
when the level of INT pin is “H.” Executes
the next instruction when the level of INT
pin is “L.”
Rev.1.02 2006.12.22 page 94 of 140
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZP (Skip if Non Zero condition of Power down flag)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
(P) = 1
words
cycles
code
0
0
0
0
0
0
0
0
1
1
0
0
3
16
2
1
1
–
Grouping:
Other operation
Operation:
(P) = 1 ?
Description: Skips the next instruction when the P flag is
“1”.
After skipping, the P flag remains un-
changed.
Executes the next instruction when the P
flag is “0.”
SNZSI (Skip if Non Zero condition of Serial Interface interrupt request flag)
Number of Number of
Flag CY
–
Skip condition
Instruction
D9
D0
words
cycles
code
1
0
1
0
0
0
1
0
0
0
2
8
8
16
2
1
1
V23 = 0: (SIOF) =1
Grouping:
Serial interface operation
Operation:
V23=0: (SIOF)=1?
Description: Clears (0) to SIOF flag and skips the next
instruction when the contents of bit 3 (V23)
of interrupt control register V2 is “0” and
contents of SIOF flag is “1.”
(SIOF) ← 0
V23 = 1: SNZSI = NOP
When V23 = 1: This instruction is equivalent
to the NOP instruction.
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
words
cycles
code
1
0
1
0
0
0
0
0
0
0
2
8
0
16
2
1
1
–
V12 = 0: (T1F) = 1
Grouping:
Timer operation
Operation:
V12 = 0: (T1F) = 1 ?
Description: When V12 = 0 : Clears (0) to the T1F flag
and skips the next instruction when timer 1
interrupt request flag T1F is “1.” When the
T1F flag is “0,” executes the next instruc-
tion.
(T1F) ← 0
V12 = 1: SNZT1 = NOP
(V12 = bit 2 of interrupt control register V1)
When V12 = 1 : This instruction is equiva-
lent to the NOP instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Number of Number of
Flag CY
–
Skip condition
Instruction
D9
D0
words
cycles
code
1
0
1
0
0
0
0
0
0
1
2
8
1
16
2
1
1
V13 = 0: (T2F) = 1
Grouping:
Timer operation
Operation:
V13 = 0: (T2F) = 1 ?
Description: When V13 = 0 : Clears (0) to the T2F flag
and skips the next instruction when timer 2
interrupt request flag T2F is “1.” When the
T2F flag is “0,” executes the next instruc-
tion.
(T2F) ← 0
V13 = 1: SNZT2 = NOP
(V13 = bit 3 of interrupt control register V1)
When V13 = 1 : This instruction is equiva-
lent to the NOP instruction.
Rev.1.02 2006.12.22 page 95 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SRST (System ReSet)
Instruction
D9
D0
1
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
0
0
0
0
0
0
9
5
9
1
E
9
3
16
16
16
16
2
1
1
–
Grouping:
Other operation
Operation:
System reset
Description: System reset occurs.
SST (Serial interface transmission/reception STart)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
1
0
1
0
0
1
1
1
1
0
2
0
2
2
2
2
1
1
Grouping:
Serial interface operation
Operation:
(SIOF) ← 0
Serial interface transmit/receive starting
Description: Clears (0) to SIOF flag and starts serial in-
terface.
SUPT (Set UPT flag)
Instruction
Number of Flag CY
cycles
D9
D0
1
Number of
words
Skip condition
–
code
0
0
0
1
0
1
1
0
0
1
1
–
Grouping:
Other operation
Operation:
(UPTF) ← 1
Description: Sets (1) to the high-order bit reference en-
able flag UPTF. When the table reference
instruction (TABP p) is executed, the high-
order 2 bits of ROM reference data is
transferred to the low-order 2 bits of regis-
ter D.
SVDE (Set Voltage Detector Enable flag)
Instruction
D9
D0
1
Number of Number of Flag CY
words
Skip condition
–
cycles
code
1
0
1
0
0
1
0
0
1
1
1
–
Grouping:
Other operation
Operation:
Voltage drop detection circuit valid at RAM back-up
Description: Validates the voltage drop detection circuit
at RAM back-up.
Note:
This instruction can be executed only for
the H version.
Rev.1.02 2006.12.22 page 96 of 140
REJ03B0148-0102
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZB j (Skip if Zero, Bit)
Instruction
D9
D0
j
Number of Number of Flag CY
Skip condition
words
cycles
code
0
0
0
0
1
0
0
0
j
0
2
j
16
2
1
1
–
(Mj(DP)) = 0
j = 0 to 3
Grouping:
Bit operation
Operation:
(Mj(DP)) = 0 ?
j = 0 to 3
Description: Skips the next instruction when the con-
tents of bit j (bit specified by the value j in
the immediate field) of M(DP) is “0.”
Executes the next instruction when the con-
tents of bit j of M(DP) is “1.”
SZC (Skip if Zero, Carry flag)
Number of Number of
Flag CY
–
Skip condition
(CY) = 0
Instruction
D9
D0
1
words
cycles
code
0
0
0
0
1
0
1
1
1
0
2
F
16
2
1
1
Grouping:
Arithmetic operation
Operation:
(CY) = 0 ?
Description: Skips the next instruction when the con-
tents of carry flag CY is “0.”
After skipping, the CY flag remains un-
changed.
Executes the next instruction when the con-
tents of the CY flag is “1.“
SZD (Skip if Zero, port D specified by register Y)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
words
cycles
code
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
2
2
4
16
16
2
2
2
2
–
(D(Y)) = 0
(Y) = 0 to 3
0
1
B
Grouping:
Input/Output operation
Operation:
(D(Y)) = 0 ?
(Y) = 0 to 3
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
Note:
(Y) = 0 to 3.
Do not execute this instruction if values ex-
cept above are set to register Y.
T1AB (Transfer data to timer 1 and register R1L from Accumulator and register B)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
words
cycles
code
1
0
0
0
1
1
0
0
0
0
2
3
0
16
2
1
1
Grouping:
Timer operation
Operation:
(R1L7–R1L4) ← (B)
(T17–T14) ← (B)
(R1L3–R1L0) ← (A)
(T13–T10) ← (A)
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 and timer 1 re-
load register R1L. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1L.
Rev.1.02 2006.12.22 page 97 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T1HAB (Transfer data to register R1H from Accumulator and register B)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
1
0
0
1
0
0
1
0
2
9
2
16
2
1
1
–
Grouping:
Timer operation
Operation:
(R1H7–R1H4) ← (B)
(R1H3–R1H0) ← (A)
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 reload register
R1H. Transfers the contents of register A to
the low-order 4 bits of timer 1 reload regis-
ter R1H.
T1R1L (Transfer data to timer 1 from register R1L)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
words
cycles
code
1
0
1
0
1
0
0
1
1
1
2
A
7
16
2
1
1
Grouping:
Timer operation
Operation:
(T17–T10) ← (R1L7–R1L0)
Description: Transfers the contents of timer 1 reload
register R1L to timer 1.
T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B)
Number of Flag CY
cycles
Instruction
D9
D0
Number of
words
Skip condition
–
code
1
0
0
0
1
1
0
0
0
1
2
3
1
16
2
1
1
–
Grouping:
Timer operation
Operation:
(R2L7–R2L4) ← (B)
(T27–T24) ← (B)
(R2L3–R2L0) ← (A)
(T23–T20) ← (A)
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 re-
load register R2L. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2L.
T2HAB (Transfer data to register R2H from Accumulator and register B)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
1
0
0
1
0
1
0
0
2
9
4
16
2
1
1
–
Grouping:
Timer operation
Operation:
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 reload register
R2H. Transfers the contents of register A to
the low-order 4 bits of timer 2 reload regis-
ter R2H.
Rev.1.02 2006.12.22 page 98 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T2R2L (Transfer data to timer 2 from register R2L)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
1
0
0
1
0
1
0
1
2
9
5
16
2
1
1
–
Grouping:
Timer operation
Operation:
(T27–T20) ← (R2L7–R2L0)
Description: Transfers the contents of timer 2 reload
register R2L to timer 2.
TAB (Transfer data to Accumulator from register B)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
words
cycles
code
0
0
0
0
0
1
1
1
1
0
0
1
E
16
2
1
1
Grouping:
Register to register transfer
Operation:
(A) ← (B)
Description: Transfers the contents of register B to reg-
ister A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
1
1
1
0
0
0
0
2
7
0
16
2
1
1
–
Grouping:
Timer operation
Operation:
(B) ← (T17–T14)
(A) ← (T13–T10)
Description: Transfers the high-order 4 bits (T17–T14) of
timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of
timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
words
cycles
code
1
0
0
1
1
1
0
0
0
1
2
7
1
16
2
1
1
Grouping:
Timer operation
Operation:
(B) ← (T27–T24)
(A) ← (T23–T20)
Description: Transfers the high-order 4 bits (T27–T24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of
timer 2 to register A.
Rev.1.02 2006.12.22 page 99 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
1
1
1
1
0
0
1
2
7
9
16
2
1
1
–
Grouping:
A/D conversion operation
Operation:
In A/D conversion mode (Q13 = 0),
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
In comparator mode (Q13 = 1),
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
Description: In the A/D conversion mode (Q1
fers the high-order 4 bits (AD –AD
AD to register B, and the middle-order 4 bits
(AD –AD ) of register AD to register A. In the
comparator mode (Q1 = 1), transfers the high-
order 4 bits (AD –AD ) of comparator register
to register B, and the low-order 4 bits (AD
AD ) of comparator register to register A.
3
= 0), trans-
9
6) of register
5
2
3
7
4
(Q13 : bit 3 of A/D control register Q1)
3
–
0
TABE (Transfer data to Accumulator and register B from register E)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
words
cycles
code
0
0
0
0
1
0
1
0
1
0
0
2
A
16
2
1
1
Grouping:
Register to register transfer
Operation:
(B) ← (E7–E4)
(A) ← (E3–E0)
Description: Transfers the high-order 4 bits (E7–E4) of
register E to register B, and low-order 4 bits
of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Number of Number of
Flag CY
Skip condition
–
Instruction
D9
D0
words
cycles
8
+p
code
0
0
1
0
0
p4 p3 p2 p1 p0
0
p
16
2
1
3
–
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(UPTF) ← 1
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Grouping:
Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7
to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified
by registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the
low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least
significant bit (DR2) of register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
p is 0 to 31.
When this instruction is executed, be careful not to over the stack be-
cause 1 stage of stack register is used.
Note:
TABPS (Transfer data to Accumulator and register B from Pre-Scaler)
Number of Flag CY
cycles
Instruction
D9
D0
Number of
words
Skip condition
–
code
1
0
0
1
1
1
0
1
0
1
2
7
5
16
2
1
1
–
Grouping:
Timer operation
Operation:
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
Description: Transfers the high-order 4 bits of prescaler
to register B.
Transfers the low-order 4 bits of prescaler to
register A.
Rev.1.02 2006.12.22 page 100 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABSI (Transfer data to Accumulator and register B from register SI)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
1
1
1
1
0
0
0
2
7
8
16
2
1
1
–
Grouping:
Serial interface operation
Operation:
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
Description: Transfers the high-order 4 bits of serial inter-
face register SI to register B, and transfers
the low-order 4 bits of serial interface regis-
ter SI to register A.
TAD (Transfer data to Accumulator from register D)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
words
cycles
code
0
0
0
1
0
1
0
0
0
1
0
5
1
16
2
1
1
Grouping:
Register to register transfer
Operation:
(A2–A0) ← (DR2–DR0)
(A3) ← 0
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
TADAB (Transfer data to register AD from Accumulator from register B)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
0
1
1
1
0
0
1
2
3
9
16
2
1
1
–
Grouping:
A/D conversion operation
Operation:
Q13 = 1: (AD7–AD4) ← (B)
Description: In the comparator mode (Q13 = 1), transfers
the contents of register B to the high-order 4
bits (AD7–AD4) of comparator register, and
the contents of register A to the low-order 4
bits (AD3–AD0) of comparator register.
(AD3–AD0) ← (A)
Q13 = 0: TADAB = NOP
In the A/D conversion mode (Q13 = 0), this in-
struction is equivalent to the NOP instruction.
(Q13 = bit 3 of A/D control register Q1)
TAI1 (Transfer data to Accumulator from register I1)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
code
D9
D0
words
cycles
1
0
0
1
0
1
0
0
1
1
2
5
3
16
2
1
1
Grouping:
Interrupt operation
Operation:
(A) ← (I1)
Description: Transfers the contents of interrupt control
register I1 to register A.
Rev.1.02 2006.12.22 page 101 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAJ1 (Transfer data to Accumulator from register J1)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
1
0
0
0
0
1
0
2
4
5
5
5
2
6
9
A
16
16
16
16
2
1
1
–
Grouping:
Serial interface operation
Operation:
(A) ← (J1)
Description: Transfers the contents of serial interface
control register J1 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
1
0
0
1
0
1
0
1
1
0
2
2
1
1
Grouping:
Input/Output operation
Operation:
(A) ← (K0)
Description: Transfers the contents of key-on wakeup
control register K0 to register A.
TAK1 (Transfer data to Accumulator from register K1)
Instruction
Number of Flag CY
cycles
D9
D0
Number of
words
Skip condition
–
code
1
0
0
1
0
1
1
0
0
1
2
2
1
1
–
Grouping:
Input/Output operation
Operation:
(A) ← (K1)
Description: Transfers the contents of key-on wakeup
control register K1 to register A.
TAK2 (Transfer data to Accumulator from register K2)
Instruction
D9
D0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
1
0
0
1
0
1
1
0
1
0
2
2
1
1
–
Grouping:
Input/Output operation
Operation:
(A) ← (K2)
Description: Transfers the contents of key-on wakeup
control register K2 to register A.
Rev.1.02 2006.12.22 page 102 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAL1 (Transfer data to Accumulator from register L1)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
1
0
0
1
0
1
0
2
4
4
C
A
9
j
16
16
16
16
2
1
1
–
Grouping:
Input/Output operation
Operation:
(A) ← (L1)
Description: Transfers the contents of key-on wakeup
control register L1 to register A.
TALA (Transfer data to Accumulator from register LA)
Instruction
Number of Number of
Flag CY
–
Skip condition
–
D9
D0
words
cycles
code
1
0
0
1
0
0
1
0
0
1
2
2
1
1
Grouping:
A/D conversion operation
Operation:
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
Description: Transfers the low-order 2 bits (AD1, AD0) of
register AD to the high-order 2 bits (A3, A2)
of register A. “0” is stored to the low-order 2
bits (A1, A0) of register A.
TAM j (Transfer data to Accumulator from Memory)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
1
1
0
0
j
j
j
j
2
2
1
1
–
Grouping:
RAM to register transfer
Operation:
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Description: After transferring the contents of M(DP) to
register A, an exclusive OR operation is
performed between register X and the value
j in the immediate field, and stores the re-
sult in register X.
TAMR (Transfer data to Accumulator from register MR)
Instruction
Number of Number of
Flag CY
–
Skip condition
–
D9
D0
words
cycles
code
1
0
0
1
0
1
0
0
1
0
2
5
2
2
1
1
Grouping:
Clock operation
Operation:
(A) ← (MR)
Description: Transfers the contents of clock control reg-
ister MR to register A.
Rev.1.02 2006.12.22 page 103 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAPU0 (Transfer data to Accumulator from register PU0)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
1
0
1
0
1
1
1
2
5
7
E
F
4
16
16
16
16
2
1
1
–
Grouping:
Input/Output operation
Operation:
(A) ← (PU0)
Description: Transfers the contents of pull-up control
register PU0 to register A.
TAPU1 (Transfer data to Accumulator from register PU1)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
1
0
0
1
0
1
1
1
1
0
2
5
2
1
1
Grouping:
Input/Output operation
Operation:
(A) ← (PU1)
Description: Transfers the contents of pull-up control
register PU1 to register A.
TAPU2 (Transfer data to Accumulator from register PU2)
Instruction
Number of Flag CY
cycles
D9
D0
Number of
words
Skip condition
–
code
1
0
0
1
0
1
1
1
1
1
2
5
2
1
1
–
Grouping:
Input/Output operation
Operation:
(A) ← (PU2)
Description: Transfers the contents of pull-up control
register PU2 to register A.
TAQ1 (Transfer data to Accumulator from register Q1)
Instruction
D9
D0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
1
0
0
1
0
0
0
1
0
0
2
4
2
1
1
–
Grouping:
A/D conversion operation
Operation:
(A) ← (Q1)
Description: Transfers the contents of A/D control regis-
ter Q1 to register A.
Rev.1.02 2006.12.22 page 104 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
1
0
1
0
0
0
0
0
5
5
5
0
4
5
B
16
16
16
16
2
1
1
–
Grouping:
Register to register transfer
Operation:
(A2–A0) ← (SP2–SP0)
(A3) ← 0
Description: Transfers the contents of stack pointer (SP)
to the low-order 3 bits (A2–A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
TAV1 (Transfer data to Accumulator from register V1)
Instruction
Number of Number of
Flag CY
–
Skip condition
–
D9
D0
words
cycles
code
0
0
0
1
0
1
0
1
0
0
0
2
1
1
Grouping:
Interrupt operation
Operation:
(A) ← (V1)
Description: Transfers the contents of interrupt control
register V1 to register A.
TAV2 (Transfer data to Accumulator from register V2)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
1
0
1
0
1
0
1
0
2
1
1
–
Grouping:
Interrupt operation
Operation:
(A) ← (V2)
Description: Transfers the contents of interrupt control
register V2 to register A.
TAW1 (Transfer data to Accumulator from register W1)
Instruction
Number of Number of
Flag CY
–
Skip condition
–
D9
D0
words
cycles
code
1
0
0
1
0
0
1
0
1
1
2
4
2
1
1
Grouping:
Timer operation
Operation:
(A) ← (W1)
Description: Transfers the contents of timer control reg-
ister W1 to register A.
Rev.1.02 2006.12.22 page 105 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW2 (Transfer data to Accumulator from register W2)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
1
0
0
1
1
0
0
2
4
C
F
0
16
16
16
16
2
1
1
–
Grouping:
Timer operation
Operation:
(A) ← (W2)
Description: Transfers the contents of timer control reg-
ister W2 to register A.
TAW5 (Transfer data to Accumulator from register W5)
Instruction
Number of Number of
Flag CY
–
Skip condition
–
D9
D0
words
cycles
code
1
0
0
1
0
0
1
1
1
1
2
4
2
1
1
Grouping:
Timer operation
Operation:
(A) ← (W5)
Description: Transfers the contents of timer control reg-
ister W5 to register A.
TAW6 (Transfer data to Accumulator from register W6)
Instruction
Number of Flag CY
cycles
D9
D0
Number of
words
Skip condition
–
code
1
0
0
1
0
1
0
0
0
0
2
5
2
1
1
–
Grouping:
Timer operation
Operation:
(A) ← (W6)
Description: Transfers the contents of timer control reg-
ister W6 to register A.
TAX (Transfer data to Accumulator from register X)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
1
0
1
0
0
1
0
0
5
2
2
1
1
–
Grouping:
Register to register transfer
Operation:
(A) ← (X)
Description: Transfers the contents of register X to reg-
ister A.
Rev.1.02 2006.12.22 page 106 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAY (Transfer data to Accumulator from register Y)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
1
1
1
1
1
0
1
F
16
16
16
16
2
1
1
–
Grouping:
Register to register transfer
Operation:
(A) ← (Y)
Description: Transfers the contents of register Y to regis-
ter A.
TAZ (Transfer data to Accumulator from register Z)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
0
0
0
1
0
1
0
0
1
1
0
5
0
2
3
E
9
2
1
1
Grouping:
Register to register transfer
Operation:
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
Description: Transfers the contents of register Z to the
low-order 2 bits (A1, A0) of register A. “0” is
stored to the high-order 2 bits (A3, A2) of
register A.
TBA (Transfer data to register B from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
0
0
0
0
0
0
1
1
1
0
0
2
1
1
–
Grouping:
Register to register transfer
Operation:
(B) ← (A)
Description: Transfers the contents of register A to regis-
ter B.
TDA (Transfer data to register D from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
0
0
0
0
1
0
1
0
0
1
0
2
1
1
Grouping:
Register to register transfer
Operation:
(DR2–DR0) ← (A2–A0)
Description: Transfers the contents of the low-order 3
bits (A2–A0) of register A to register D.
Rev.1.02 2006.12.22 page 107 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TEAB (Transfer data to register E from Accumulator and register B)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
0
0
0
0
0
1
1
0
1
0
0
1
A
8
9
A
16
16
16
16
2
1
1
–
Grouping:
Register to register transfer
Operation:
(E7–E4) ← (B)
(E3–E0) ← (A)
Description: Transfers the contents of register B to the
high-order 4 bits (E3–E0) of register E, and
the contents of register A to the low-order 4
bits (E3–E0) of register E.
TFR0A (Transfer data to register FR0 from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
1
0
0
0
1
0
1
0
0
0
2
2
2
1
1
Grouping:
Input/Output operation
Operation:
(FR0) ← (A)
Description: Transfers the contents of register A to port
output structure control register FR0.
TFR1A (Transfer data to register FR1 from Accumulator)
Instruction
Number of Flag CY
cycles
D9
D0
Number of
words
Skip condition
–
code
1
0
0
0
1
0
1
0
0
1
2
2
2
1
1
–
Grouping:
Input/Output operation
Operation:
(FR1) ← (A)
Description: Transfers the contents of register A to port
output structure control register FR1.
TFR2A (Transfer data to register FR2 from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
1
0
0
0
1
0
1
0
1
0
2
2
2
1
1
–
Grouping:
Input/Output operation
Operation:
(FR2) ← (A)
Description: Transfers the contents of register A to port
output structure control register FR2.
Rev.1.02 2006.12.22 page 108 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TFR3A (Transfer data to register FR3 from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
0
1
0
1
0
1
1
2
2
1
0
1
B
7
2
B
16
16
16
16
2
1
1
–
Grouping:
Input/Output operation
Operation:
(FR3) ← (A)
Description: Transfers the contents of register A to port
output structure control register FR3.
TI1A (Transfer data to register I1 from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
1
0
0
0
0
1
0
1
1
1
2
2
1
1
Grouping:
Interrupt operation
Operation:
(I1) ← (A)
Description: Transfers the contents of register A to inter-
rupt control register I1.
TJ1A (Transfer data to register J1 from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
1
0
0
0
0
0
0
0
1
0
2
2
1
1
–
Grouping:
Serial interface operation
Operation:
(J1) ← (A)
Description: Transfers the contents of register A to serial
interface control register J1.
TK0A (Transfer data to register K0 from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
1
0
0
0
0
1
1
0
1
1
2
2
1
1
Grouping:
Input/Output operation
Operation:
(K0) ← (A)
Description: Transfers the contents of register A to key-
on wakeup control register K0.
Rev.1.02 2006.12.22 page 109 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK1A (Transfer data to register K1 from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
0
0
1
0
1
0
0
2
1
1
0
B
4
5
A
j
16
16
16
16
2
1
1
–
Grouping:
Input/Output operation
Operation:
(K1) ← (A)
Description: Transfers the contents of register A to key-
on wakeup control register K1.
TK2A (Transfer data to register K2 from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
1
0
0
0
0
1
0
1
0
1
2
2
1
1
Grouping:
Input/Output operation
Operation:
(K2) ← (A)
Description: Transfers the contents of register A to key-
on wakeup control register K2.
TL1A (Transfer data to register L1 from Accumulator)
Instruction
Number of Flag CY
cycles
D9
D0
Number of
words
Skip condition
–
code
1
0
0
0
0
0
1
0
1
0
2
2
1
1
–
Grouping:
Input/Output operation
Operation:
(L1) ← (A)
Description: Transfers the contents of register A to key-
on wakeup control register L1.
TMA j (Transfer data to Memory from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
1
0
1
0
1
1
j
j
j
j
2
2
1
1
–
Grouping:
RAM to register transfer
Operation:
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Description: After transferring the contents of register A
to M(DP), an exclusive OR operation is per-
formed between register X and the value j
in the immediate field, and stores the result
in register X.
Rev.1.02 2006.12.22 page 110 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TMRA (Transfer data to register MR from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
0
0
1
0
1
1
0
2
1
6
16
2
1
1
–
Grouping:
Clock operation
Operation:
(MR) ← (A)
Description: Transfers the contents of register A to clock
control register MR.
TPAA (Transfer data to register PA from Accumulator)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
words
cycles
code
1
0
1
0
1
0
1
0
1
0
2
A
A
16
2
1
1
Grouping:
Timer operation
Operation:
(PA0) ← (A0)
Description: Transfers the least significant bit of register
A to timer control register PA.
TPSAB (Transfer data to Pre-Scaler and register RPS from Accumulator and register B)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
0
1
1
0
1
0
1
2
3
5
16
2
1
1
–
Grouping:
Timer operation
Operation:
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
Description: Transfers the contents of register B to the
high-order 4 bits of prescaler and prescaler
reload register RPS. Transfers the contents
of register A to the low-order 4 bits of
prescaler and prescaler reload register
RPS.
TPU0A (Transfer data to register PU0 from Accumulator)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
words
cycles
code
1
0
0
0
1
0
1
1
0
1
2
2
D
16
2
1
1
Grouping:
Input/Output operation
Operation:
(PU0) ← (A)
Description: Transfers the contents of register A to pull-
up control register PU0.
Rev.1.02 2006.12.22 page 111 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
0
1
0
1
1
1
0
2
2
E
F
4
9
16
16
16
16
2
1
1
–
Grouping:
Input/Output operation
Operation:
(PU1) ← (A)
Description: Transfers the contents of register A to pull-
up control register PU1.
TPU2A (Transfer data to register PU2 from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
1
0
0
0
1
0
1
1
1
1
2
2
2
1
1
Grouping:
Input/Output operation
Operation:
(PU2) ← (A)
Description: Transfers the contents of register A to pull-
up control register PU2.
TQ1A (Transfer data to register Q1 from Accumulator)
Instruction
Number of Flag CY
cycles
D9
D0
Number of
words
Skip condition
–
code
1
0
0
0
0
0
0
1
0
0
2
0
2
1
1
–
Grouping:
A/D conversion operation
Operation:
(Q1) ← (A)
Description: Transfers the contents of register A to A/D
control register Q1.
TRGA (Transfer data to register RG from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
1
0
0
0
0
0
1
0
0
1
2
0
2
1
1
–
Grouping:
Clock operation
Operation:
(RG0) ← (A0)
Description: Transfers the least significant bit (A0) of
register A to clock control regiser RG.
Rev.1.02 2006.12.22 page 112 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TSIAB (Transfer data to register SI from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
0
1
1
1
0
0
0
2
3
8
16
16
16
16
2
1
1
–
Grouping:
Serial interface operation
Operation:
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
Description: Transfers the contents of register B to the
high-order 4 bits of serial interface register
SI, and transfers the contents of register A
to the low-order 4 bits of serial interface
register SI.
TV1A (Transfer data to register V1 from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
0
0
0
0
1
1
1
1
1
1
0
3
F
2
1
1
Grouping:
Interrupt operation
Operation:
(V1) ← (A)
Description: Transfers the contents of register A to inter-
rupt control register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
0
0
0
0
1
1
1
1
1
0
0
3
E
2
1
1
–
Grouping:
Interrupt operation
Operation:
(V2) ← (A)
Description: Transfers the contents of register A to inter-
rupt control register V2.
TW1A (Transfer data to register W1 from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
1
0
0
0
0
0
1
1
1
0
2
0
E
2
1
1
Grouping:
Timer operation
Operation:
(W1) ← (A)
Description: Transfers the contents of register A to timer
control register W1.
Rev.1.02 2006.12.22 page 113 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW2A (Transfer data to register W2 from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
–
words
cycles
code
1
0
0
0
0
0
1
1
1
1
2
0
F
16
16
16
16
2
1
1
–
Grouping:
Timer operation
Operation:
(W2) ← (A)
Description: Transfers the contents of register A to timer
control register W2.
TW5A (Transfer data to register W5 from Accumulator)
Instruction
Flag CY
–
Skip condition
–
D9
D0
Number of Number of
words
cycles
code
1
0
0
0
0
1
0
0
1
0
2
1
2
2
1
1
Grouping:
Timer operation
Operation:
(W5) ← (A)
Description: Transfers the contents of register A to timer
control register W5.
TW6A (Transfer data to register W6 from Accumulator)
Instruction
Number of Flag CY
cycles
D9
D0
Number of
words
Skip condition
–
code
1
0
0
0
0
1
0
0
1
1
2
1
3
2
1
1
–
Grouping:
Timer operation
Operation:
(W6) ← (A)
Description: Transfers the contents of register A to timer
control register W6.
TYA (Transfer data to register Y from Accumulator)
Instruction
D9
D0
Number of Number of Flag CY
words
Skip condition
–
cycles
code
0
0
0
0
0
0
1
1
0
0
0
0
C
2
1
1
–
Grouping:
Register to register transfer
Operation:
(Y) ← (A)
Description: Transfers the contents of register A to regis-
ter Y.
Rev.1.02 2006.12.22 page 114 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
WRST (Watchdog timer ReSeT)
Instruction
D9
D0
0
Number of Number of Flag CY
Skip condition
(WDF1) = 1
words
cycles
code
1
0
1
0
1
0
0
0
0
2
A
0
16
2
1
1
–
Grouping:
Other operation
Operation:
(WDF1) = 1 ?
Description: Clears (0) to the WDF1 flag and skips the
next instruction when watchdog timer flag
WDF1 is “1.” When the WDF1 flag is “0,” ex-
ecutes the next instruction. Also, stops the
watchdog timer function when executing the
WRST instruction immediately after the
DWDT instruction.
(WDF1) ← 0
XAM j (eXchange Accumulator and Memory data)
Number of Number of
Flag CY
–
Skip condition
–
Instruction
D9
D0
words
cycles
code
1
0
1
1
0
1
j
j
j
j
2
D
j
16
2
1
1
Grouping:
RAM to register transfer
Operation:
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between regis-
ter X and the value j in the immediate field,
and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction
D9
D0
Number of Number of Flag CY
Skip condition
(Y) = 15
words
cycles
code
1
0
1
1
1
1
j
j
j
j
2
F
j
16
2
1
1
–
Grouping:
RAM to register transfer
Operation:
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between regis-
ter X and the value j in the immediate field,
and stores the result in register X.
(Y) ← (Y) – 1
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the con-
tents of register Y is 15, the next instruction
is skipped. When the contents of register Y
is not 15, the next instruction is executed.
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Number of Number of
Flag CY
–
Skip condition
(Y) = 0
Instruction
D9
D0
words
cycles
code
1
0
1
1
1
0
j
j
j
j
2
E
j
16
2
1
1
Grouping:
RAM to register transfer
Operation:
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between regis-
ter X and the value j in the immediate field,
and stores the result in register X.
(Y) ← (Y) + 1
Adds 1 to the contents of register Y. As a re-
sult of addition, when the contents of
register Y is 0, the next instruction is
skipped. When the contents of register Y is
not 0, the next instruction is executed.
Rev.1.02 2006.12.22 page 115 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
TAB
TBA
TAY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
0
1
0
0
0
1
0
1
0
1
E
1
1
1
1
1
1
1
1
1
1
(A) ← (B)
(B) ← (A)
(A) ← (Y)
(Y) ← (A)
0
0
0
0
E
F
C
A
TYA
TEAB
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0
2
A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
TAD
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
2
5
9
1
1
1
1
1
(DR2–DR0) ← (A2–A0)
(A2–A0) ← (DR2–DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0
5
3
1
1
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
0
0
0
5
5
2
0
1
1
1
1
(A) ← (X)
TASP
(A2–A0) ← (SP2–SP0)
(A3) ← 0
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3
x
y
1
1
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
LZ z
INY
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
1
z1 z0
0
0
0
4
1
1
8
+z
1
1
1
1
1
1
(Z) ← z z = 0 to 3
(Y) ← (Y) + 1
1
1
1
1
3
7
DEY
(Y) ← (Y) – 1
TAM j
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
0
1
1
j
j
j
j
j
j
j
j
j
j
j
j
2
2
2
C j
D j
1
1
1
1
1
1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
XAMD j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
F
j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) – 1
XAMI j
TMA j
1
1
0
0
1
1
1
0
1
1
0
1
j
j
j
j
j
j
j
j
2
2
E j
1
1
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
B j
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Rev.1.02 2006.12.22 page 116 of 140
REJ03B0148-0102
4508 Group
Skip condition
Datailed description
–
–
–
–
–
–
–
–
–
–
Transfers the contents of register B to register A.
Transfers the contents of register A to register B.
Transfers the contents of register Y to register A.
Transfers the contents of register A to register Y.
Transfers the contents of register B to the high-order 4 bits (E7–E4) of register E, and the contents of regis-
ter A to the low-order 4 bits (E3–E0) of register E.
–
–
Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to regis-
ter A.
–
–
–
–
Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D.
Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
–
–
Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A.
“0” is stored to the high-order 2 bits (A3, A2) of register A.
–
–
–
–
Transfers the contents of register X to register A.
Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
–
–
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
(Y) = 15
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in-
struction is skipped. When the contents of register Y is not 0, the next instruction is executed.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
–
–
–
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between reg-
ister X and the value j in the immediate field, and stores the result in register X.
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
(Y) = 0
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-
formed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in-
struction is skipped. when the contents of register Y is not 0, the next instruction is executed.
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg-
ister X and the value j in the immediate field, and stores the result in register X.
Rev.1.02 2006.12.22 page 117 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(A) ← n
LA n
0
0
0
0
0
1
1
0
1
0
1
n
n
n
n
0
7
n
1
1
1
3
n = 0 to 15
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
TABP p
p4 p3 p2 p1 p0
0
8
+p
p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(UPTF) = 1
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(A) ← (A) + (M(DP))
AM
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
n
0
0
n
1
1
n
0
1
n
0
0
0
0
0
6
A
B
n
1
1
1
1
1
1
(A) ← (A) + (M(DP)) +(CY)
(CY) ← Carry
AMC
A n
(A) ← (A) + n
n = 0 to 15
(A) ← (A) AND (M(DP))
(A) ← (A) OR (M(DP))
AND
OR
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
1
1
8
9
1
1
1
1
(CY) ← 1
SC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
2
1
1
7
1
1
1
1
1
1
1
1
1
1
(CY) ← 0
RC
6
(CY) = 0 ?
SZC
CMA
RAR
F
C
D
(A) ← (A)
→ CY → A3A2A1A0
(Mj(DP)) ← 1
SB j
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
1
1
0
j
j
j
j
j
j
0
0
0
5
4
2
C
+j
1
1
1
1
1
1
j = 0 to 3
(Mj(DP)) ← 0
j = 0 to 3
RB j
SZB j
C
+j
(Mj(DP)) = 0 ?
j = 0 to 3
j
(A) = (M(DP)) ?
SEAM
SEA n
0
0
0
0
1
0
0
1
1
0
0
2
6
1
2
1
2
(A) = n ?
n = 0 to 15
0
0
0
0
0
0
0
1
1
1
0
1
0
n
1
n
0
n
1
n
0
0
2
7
5
n
Note :p is 0 to 31.
Rev.1.02 2006.12.22 page 118 of 140
REJ03B0148-0102
4508 Group
Skip condition
Datailed description
Continuous
description
–
–
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad-
dress (DR
2
DR
1
DR
0
A
3
A
2
A
1
A
0
)
2
specified by registers A and D in page p. When UPTF is 1, Transfers bits
9, 8 to the low-order 2 bits (DR
1
, DR ) of register D, and “0” is stored to the least significant bit (DR ) of reg-
0
2
ister D.
When this instruction is executed, 1 stage of stack register (SK) is used.
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY re-
mains unchanged.
–
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
–
Adds the value n in the immediate field to register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
Executes the next instruction when there is overflow as the result of operation.
–
–
–
–
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the re-
sult in register A.
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
–
1
0
–
–
Sets (1) to carry flag CY.
–
Clears (0) to carry flag CY.
(CY) = 0
Skips the next instruction when the contents of carry flag CY is “0.”
Stores the one’s complement for register A’s contents in register A.
–
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
–
–
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
j = 0 to 3
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0.”
Executes the next instruction when the contents of bit j of M(DP) is “1.”
(A) = (M(DP))
–
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
(A) = n
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
n = 0 to 15
Executes the next instruction when the contents of register A is not equal to the value n in the immediate
field.
Rev.1.02 2006.12.22 page 119 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
B a
0
0
1
1
0
0
1
1
0
a6 a5 a4 a3 a2 a1 a0
1
0
2
8
+a
a
1
2
1
2
(PCL) ← a6–a0
BL p, a
1
1
p4 p3 p2 p1 p0
E p
+p
(PCH) ← p (Note)
(PCL) ← a6–a0
a6 a5 a4 a3 a2 a1 a0
a
a
BLA p
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
2
1
p
0
p
2
1
2
2
1
2
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
p4
p3 p2 p1 p0
BM a
0
1
0
a6 a5 a4 a3 a2 a1 a0
1
a
a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
1
0
0
1
0
1
0
p4 p3 p2 p1 p0
0
2
C p
+p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← a6–a0
a6 a5 a4 a3 a2 a1 a0
a
a
BMLA p
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
2
3
p
0
p
2
2
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
p4
p3 p2 p1 p0
(PCH) ← p (Note)
(PCL) ← (DR2–DR0,A3–A0)
RTI
RT
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
4
4
4
6
4
5
1
1
1
1
2
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Note :p is 0 to 31.
Rev.1.02 2006.12.22 page 120 of 140
REJ03B0148-0102
4508 Group
Skip condition
Datailed description
Branch within a page : Branches to address a in the identical page.
Branch out of a page : Branches to address a in page p.
–
–
–
–
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
–
–
–
–
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
Call the subroutine : Calls the subroutine at address a in page p.
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous de-
scription of the LA/LXY instruction, register A and register B to the states just before interrupt.
–
–
–
–
Returns from subroutine to the routine called the subroutine.
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Skip at uncondition
Rev.1.02 2006.12.22 page 121 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
3
4
5
8
1
1
1
1
1
1
(INTE) ← 0
(INTE) ← 1
EI
SNZ0
V10 = 0: (EXF0) = 1 ?
(EXF0) ← 0
V10 = 1: SNZ0 = NOP
SNZI0
0
0
0
0
1
1
1
0
1
0
0
3
A
1
1
I12 = 0 : (INT) = “L” ?
I12 = 1 : (INT) = “H” ?
TAV1
TV1A
TAV2
TV2A
TAI1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
1
1
1
0
1
0
0
1
1
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
5
3
5
3
5
1
4
F
5
E
3
7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(A) ← (V1)
(V1) ← (A)
(A) ← (V2)
(V2) ← (A)
(A) ← (I1)
TI1A
(I1) ← (A)
TPAA
TAW1
TW1A
TAW2
TW2A
TAW5
TW5A
TAW6
TW6A
TABPS
A A
(PA0) ← (A0)
(A) ← (W1)
(W1) ← (A)
(A) ← (W2)
(W2) ← (A)
(A) ← (W5)
(W5) ← (A)
(A) ← (W6)
(W6) ← (A)
4
0
4
0
4
1
5
1
7
B
E
C
F
F
2
0
3
5
(B) ← (TPS7–TPS4)
(A) ← (TPS3–TPS0)
TPSAB
1
0
0
0
1
1
0
1
0
1
2
3
5
1
1
(RPS7–RPS4) ← (B)
(TPS7–TPS4) ← (B)
(RPS3–RPS0) ← (A)
(TPS3–TPS0) ← (A)
TAB1
T1AB
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
2
2
7
3
0
0
1
1
1
1
(B) ← (T17–T14)
(A) ← (T13–T10)
(R1L7–R1L4) ← (B)
(T17–T14) ← (B)
(R1L3–R1L0) ← (A)
(T13–T10) ← (A)
T1HAB
1
0
1
0
0
1
0
0
1
0
2
9
2
1
1
(R1H7–R1H4) ← (B)
(R1H3–R1H0) ← (A)
Rev.1.02 2006.12.22 page 122 of 140
REJ03B0148-0102
4508 Group
Skip condition
Datailed description
–
–
–
–
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
–
V10 = 0: (EXF0) = 1
When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request
flag EXF0 is “1.” When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register
V1)
(INT) = “L”
However, I12 = 0
–
When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when
the level of INT pin is “H.”
(INT) = “H”
However, I12 = 1
When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when
the level of INT pin is “L.” (I12: bit 2 of interrupt control register I1)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Transfers the contents of interrupt control register V1 to register A.
Transfers the contents of register A to interrupt control register V1.
Transfers the contents of interrupt control register V2 to register A.
Transfers the contents of register A to interrupt control register V2.
Transfers the contents of interrupt control register I1 to register A.
Transfers the contents of register A to interrupt control register I1.
Transfers the contents of register A to timer control register PA.
Transfers the contents of timer control register W1 to register A.
Transfers the contents of register A to timer control register W1.
Transfers the contents of timer control register W2 to register A.
Transfers the contents of register A to timer control register W2.
Transfers the contents of timer control register W5 to register A.
Transfers the contents of register A to timer control register W5.
Transfers the contents of timer control register W6 to register A.
Transfers the contents of register A to timer control register W6.
Transfers the high-order 4 bits of prescaler to register B.
Transfers the low-order 4 bits of prescaler to register A.
–
–
Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS.
Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS.
–
–
–
–
Transfers the high-order 4 bits (T17–T14) of timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of timer 1 to register A.
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1L.
Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L.
–
–
Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1H. Transfers the
contents of register A to the low-order 4 bits of timer 1 reload register R1H.
Rev.1.02 2006.12.22 page 123 of 140
REJ03B0148-0102
4508 Group
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
(B) ← (T27–T24)
(A) ← (T23–T20)
TAB2
T2AB
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
1
1
2
2
7
3
1
1
1
1
1
1
(R2L7–R2L4) ← (B)
(T27–T24) ← (B)
(R2L3–R2L0) ← (A)
(T23–T20) ← (A)
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
T2HAB
1
0
1
0
0
1
0
1
0
0
2
9
4
1
1
(T1) ← (R1L)
(T2) ← (R2L)
T1R1L
T2R2L
1
1
0
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
1
2
2
A 7
1
1
1
1
9
8
5
0
V12 = 0: (T1F) = 1 ?
(T1F) ← 0
V12 = 1: SNZT1 = NOP
SNZT1
SNZT2
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
2
1
1
1
1
V13 = 0: (T2F) = 1 ?
(T2F) ← 0
V13 = 1: SNZT2 = NOP
8
1
(A) ← (P0)
(P0) ← (A)
(A) ← (P1)
(P1) ← (A)
IAP0
OP0A
IAP1
OP1A
IAP2
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
2
2
2
2
2
6
2
6
2
6
0
0
1
1
2
1
1
1
1
1
1
1
1
1
1
(A1, A0) ← (P21, P20)
(A3, A2) ← 0
(P21, P20) ← (A1, A0)
(D) ← 1
OP2A
CLD
RD
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
1
0
2
0
0
2
1
1
2
1
4
1
1
1
1
1
1
(D(Y)) ← 0
(Y) = 0 to 3
(D(Y)) ← 1
SD
0
0
0
0
0
1
0
1
0
1
0
1
5
1
2
1
2
(Y) = 0 to 3
(D(Y)) = 0 ?
(Y) = 0 to 3
SZD
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
0
1
0
0
1
1
1
1
0
1
0
1
0
1
1
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
1
5
4
B
8
9
A
B
B
6
(FR0) ← (A)
(FR1) ← (A)
(FR2) ← (A)
(FR3) ← (A)
(K0) ← (A)
(A) ← (K0)
TFR0A
TFR1A
TFR2A
TFR3A
TK0A
1
1
1
1
1
1
1
1
1
1
1
1
TAK0
Rev.1.02 2006.12.22 page 124 of 140
REJ03B0148-0102
4508 Group
Skip condition
Datailed description
Transfers the high-order 4 bits (T27–T24) of timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of timer 2 to register A.
–
–
–
–
Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2L. Trans-
fers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L.
Transfers the contents of register B to the high-order 4 bits of timer 2 reload register R2H. Transfers the con-
tents of register A to the low-order 4 bits of timer 2 reload register R2H.
–
–
Transfers the contents of timer 1 reload register R1L to timer 1.
Transfers the contents of timer 2 reload register R2L to timer 2.
–
–
–
–
When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag
T1F is “1.” When the T1F flag is “0,” executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1)
V12 = 0: (T1F) = 1
V13 = 0: (T2F) =1
–
–
When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag
T2F is “1.” When the T2F flag is “0,” executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction. (V1
3: bit 3 of interrupt control register V1)
Transfers the input of port P0 to register A.
–
–
–
–
–
–
–
–
–
–
Outputs the contents of register A to port P0.
Transfers the input of port P1 to register A.
Outputs the contents of register A to port P1.
Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2.
Sets (1) to port D.
–
–
–
–
–
–
Clears (0) to a bit of port D specified by register Y.
Sets (1) to a bit of port D specified by register Y.
–
–
–
Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction
when a bit of port D specified by register Y is “1.”
(D(Y)) = 0 ?
Transfers the contents of register A to port output structure control register FR0.
Transfers the contents of register A to port output structure control register FR1.
Transfers the contents of register A to port output structure control register FR2.
Transfers the contents of register A to port output structure control register FR3.
Transfers the contents of register A to key-on wakeup control register K0.
Transfers the contents of key-on wakeup control register K0 to register A.
–
–
–
–
–
–
–
–
–
–
–
–
Rev.1.02 2006.12.22 page 125 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TK1A
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
0
1
0
1
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
1
5
1
5
2
5
2
5
2
5
0
4
7
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(K1) ← (A)
(A) ← (K1)
(K2) ← (A)
(A) ← (K2)
(PU0) ← (A)
(A) ← (PU0)
(PU1) ← (A)
(A) ← (PU1)
(PU2) ← (A)
(A) ← (PU2)
(L1) ← (A)
(A) ← (L1)
TAK1
9
TK2A
5
TAK2
A
D
7
TPU0A
TAPU0
TPU1A
TAPU1
TPU2A
TAPU2
TL1A
E
E
F
F
A
A
8
TAL1
TABSI
(B) ← (SI7–SI4) (A) ← (SI3–SI0)
TSIAB
SST
1
1
1
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
1
1
1
0
1
0
0
1
0
0
0
0
2
2
2
3
9
8
8
E
8
1
1
1
1
1
1
(SI7–SI4) ← (B) (SI3–SI0) ← (A)
(SIOF) ← 0
Serial interface transmit/receive starting
SNZSI
V23=0: (SIOF)=1?
(SIOF) ← 0
V23 = 1: SNZSI = NOP
TAJ1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
2
2
2
2
2
2
4
0
9
0
5
1
2
2
B
9
2
6
1
1
1
1
1
1
1
1
1
1
1
1
(A) ← (J1)
TJ1A
(J1) ← (A)
CRCK
TRGA
TAMR
TMRA
RC oscillator selected
(RG0) ← (A0)
(A) ← (MR)
(MR) ← (A)
Rev.1.02 2006.12.22 page 126 of 140
REJ03B0148-0102
4508 Group
Skip condition
Datailed description
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Transfers the contents of register A to key-on wakeup control register K1.
Transfers the contents of key-on wakeup control register K1 to register A.
Transfers the contents of register A to key-on wakeup control register K2.
Transfers the contents of key-on wakeup control register K2 to register A.
Transfers the contents of register A to pull-up control register PU0.
Transfers the contents of pull-up control register PU0 to register A.
Transfers the contents of register A to pull-up control register PU1.
Transfers the contents of pull-up control register PU1 to register A.
Transfers the contents of register A to pull-up control register PU2.
Transfers the contents of pull-up control register PU2 to register A.
Transfers the contents of register A to key-on wakeup control register L1.
Transfers the contents of key-on wakeup control register L1 to register A.
Transfers the high-order 4 bits of serial interface register SI to register B, and transfers the low-order 4 bits
of serial interface register SI to register A.
–
–
–
–
Transfers the contents of register B to the high-order 4 bits of serial interface register SI, and transfers the
contents of register A to the low-order 4 bits of serial interface register SI.
–
Clears (0) to SIOF flag and starts serial interface transmit/receive.
V23 = 0: (SIOF) =1
Clears (0) to SIOF flag and skips the next instruction when the contents of bit 3 (V23) of interrupt control reg-
ister V2 is “0” and contents of SIOF flag is “1.” When V23 = 1: This instruction is equivalent to the NOP
instruction.
–
–
–
–
–
–
–
–
–
–
–
–
Transfers the contents of serial interface control register J1 to register A.
Transfers the contents of register A to serial interface control register J1.
Selects the RC oscillation circuit for main clock f(XIN).
Transfers the least significant bit (A0) of register A to clock control regiser RG.
Transfers the contents of clock control regiser MR to register A.
Transfers the contents of register A to clock control register MR.
Rev.1.02 2006.12.22 page 127 of 140
REJ03B0148-0102
4508 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Parameter
Function
Mnemonic
Hexadecimal
notation
Type of
instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TABAD
1
0
0
1
1
1
1
0
0
1
2
7
9
1
1
Q13 = 0:
(B) ← (AD9–AD6)
(A) ← (AD5–AD2)
Q13 = 1:
(B) ← (AD7–AD4)
(A) ← (AD3–AD0)
TALA
1
1
0
0
0
0
1
0
0
1
0
1
1
1
0
0
0
0
1
1
2
2
4
3
9
9
1
1
1
1
(A3, A2) ← (AD1, AD0)
(A1, A0) ← 0
TADAB
Q13 = 0:
(AD7–AD4) ← (B)
(AD3–AD0) ← (A)
Q13 = 1: TADAB = NOP
TAQ1
TQ1A
ADST
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
1
0
0
1
2
2
2
4
0
9
4
4
F
1
1
1
1
1
1
(A) ← (Q1)
(Q1) ← (A)
(ADF) ← 0
Q13 = 0: A/D conversion starting
Q13 = 1: Comparator operation starting
SNZAD
1
0
1
0
0
0
0
1
1
1
2
8
7
1
1
V22 = 0: (ADF) = 1 ?
(ADF) ← 0
V22 = 1: SNZAD = NOP
NOP
POF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
2
1
1
1
1
(PC) ← (PC) + 1
RAM back-up
EPOF
SNZP
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
1
1
1
0
0
5
0
B
3
1
1
1
1
POF instruction valid
(P) = 1 ?
DWDT
WRST
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
0
0
0
2
2
9
C
1
1
1
1
Stop of watchdog timer function enabled
A 0
(WDF1) = 1 ?,
(WDF1) ← 0
SRST
RUPT
SUPT
SVDE**
0
0
0
1
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
2
0
5
5
9
1
8
9
3
1
1
1
1
1
1
1
1
System reset
(UPTF) ← 0
(UPTF) ← 1
Voltage drop detection circuit valid at RAM
back-up
Note: The SVDE instruction can be used only in the H version.
Rev.1.02 2006.12.22 page 128 of 140
REJ03B0148-0102
4508 Group
Skip condition
Datailed description
–
–
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the high-order 4 bits (AD7–AD4) of comparator register to reg-
ister B, and the low-order 4 bits (AD3–AD0) of comparator register to register A.
(Q13: bit 3 of A/D control register Q1)
–
–
–
–
Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A.
“0” is stored to the least significant bit (A0) of register A.
In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.
(Q13 = bit 3 of A/D control register Q1)
–
–
–
–
–
–
Transfers the contents of A/D control register Q1 to register A.
Transfers the contents of register A to A/D control register Q1.
Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
V22 = 0: (ADF) = 1
–
When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping,
clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction.
When V22 = 1 : This instruction is equivalent to the NOP instruction. (V22: bit 2 of interrupt control register V2)
–
–
–
–
No operation; Adds 1 to program counter value, and others remain unchanged.
Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction.
Operations of all functions are stopped.
–
–
–
Makes the immediate after POF instruction valid by executing the EPOF instruction.
(P) = 1
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0.”
–
–
–
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
(WDF1) = 1
Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1.” When the
WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when executing the
WRST instruction immediately after the DWDT instruction.
–
–
–
–
–
–
–
–
System reset occurs.
Clears (0) to the high-order bit reference enable flag UPTF.
Sets (1) to the high-order bit reference enable flag UPTF.
Validates the voltage drop detection circuit at RAM back-up (only for the H version).
Rev.1.02 2006.12.22 page 129 of 140
REJ03B0148-0102
4508 Group
INSTRUCTION CODE TABLE
D9–D4 000000000001000010000011000100000101
Hex.
010000 011000
010111 011111
000110
06
001100
0C
000111001000001001001010001011
07 08 09
001101001110 001111
00
01
02
03
04
05
0A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0B
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0D 0E 0F 10–17 18–1F
D3–D0
notation
SZB
0
A
0
LA TABP TABP
16
LA TABP TABP
17
LA TABP TABP
18
LA TABP TABP
19
LA TABP TABP
20
LA TABP TABP
21
LA TABP TABP
22
LA TABP TABP
23
LA TABP TABP
24
LA TABP TABP
25
LA TABP TABP
10 10 26
LA TABP TABP
11 11 27
LA TABP TABP
12 12 28
LA TABP TABP
13 13 29
LA TABP TABP
14 14 30
LA TABP TABP
15 15 31
0000
0
NOP BLA
SRST CLD
BMLA
–
TASP
TAD
TAX
TAZ
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
0
0
SZB
1
A
1
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
–
–
1
1
SZB
2
A
2
POF
–
–
–
2
2
SZB
3
A
3
SNZP INY
–
–
3
3
A
4
SZD
SEAn
SEAM
–
DI
EI
RD
SD
–
–
RT TAV1
RTS TAV2
4
4
A
5
–
5
5
A
6
RC
–
RTI
–
–
6
6
A
7
SC DEY
–
SNZ0
–
–
7
7
LZ
0
A
8
–
–
–
AND
OR
RUPT
SUPT
–
8
8
LZ
1
A
9
TDA
TABE
–
9
9
LZ
2
A
10
AM TEAB
AMC
TYA CMA
RAR
TBA TAB
TAY
SNZI0
–
LZ
3
A
11
–
EPOF
RB
0
SB
0
A
12
–
–
RB
1
SB
1
A
13
–
–
–
RB
2
SB
2
A
14
–
TV2A
TV1A
RB
3
SB
3
A
15
SZC
–
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representa-
tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is
shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
The second word
BL
10 0aaa aaaa
10 0aaa aaaa
10 0p00 pppp
10 0p00 pppp
00 0111 nnnn
00 0010 1011
BML
BLA
BMLA
SEA
SZD
Rev.1.02 2006.12.22 page 130 of 140
REJ03B0148-0102
4508 Group
INSTRUCTION CODE TABLE (continued)
110000
111111
101100
2C
D9–D4 100000100001100010100011100100100101100110 100111101000101001101010101011
101101101110 101111
Hex.
20
–
21
–
22
23
24
–
25
TAW6 IAP0 TAB1 SNZT1
IAP1 TAB2 SNZT2
26
27
28
29
2A
2B
2D 2E 2F 30–3F
D3–D0
0000
notation
TMA TAM XAM XAMI XAMD
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
0
OP0A T1AB
OP1A T2AB
–
–
WRST
0
0
0
0
0
TMA TAM XAM XAMI XAMD
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
–
–
–
–
–
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1
1
1
1
TMA
2
TAM XAM XAMI XAMD
2
TJ1A TW5A OP2A
–
TAJ1 TAMR IAP2
–
–
T1HAB
SVDE*
T2HAB
T2R2L
–
–
2
2
2
TMA
3
TAM XAM XAMI XAMD
3
–
TW6A
–
–
–
–
–
–
–
TAI1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
3
3
TMA
4
TAM XAM XAMI XAMD
4
TQ1A TK1A
–
TAQ1
–
–
–
–
–
4
4
4
TMA
5
TAM XAM XAMI XAMD
5
–
TK2A
TPSAB
–
–
–
–
TABPS
–
–
–
5
5
5
TMA TAM XAM XAMI XAMD
–
TMRA
–
–
TAK0
TAPU0
–
–
–
–
6
6
6
6
6
TMA TAM XAM XAMI XAMD
–
–
TI1A
SNZAD
–
T1R1L
7
7
7
7
7
TMA
8
TAM XAM XAMI XAMD
8
–
–
–
TFR0ATSIAB
TABSI SNZSI
–
–
8
8
8
TMA
9
TAM XAM XAMI XAMD
9
TRGA
TL1A
–
TFR1ATADAB TALA TAK1
TABAD
–
–
–
–
–
–
–
–
–
9
9
9
TMA
10
TAM XAM XAMI XAMD
10 10 10 10
TAM XAM XAMI XAMD
11 11 11 11
TAM XAM XAMI XAMD
12 12 12 12
TFR2A
–
–
–
–
–
–
TAL1 TAK2
–
–
–
–
–
–
–
TPAA
TMA
11
TK0A TFR3A
TAW1
–
CRCK
DWDT
–
–
–
–
–
–
TMA
12
–
–
–
–
–
–
TAW2
–
–
TMA TAM XAM XAMI XAMD
13
TMA TAM XAM XAMI XAMD
–
TPU0A
TPU1A
TPU2A
–
–
13
13
13
13
TW1A
TW2A
TAPU1
SST
ADST
14
14
TAM XAM XAMI XAMD
15 15 15 15
14
14
14
TMA
15
TAW5 TAPU2
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-
order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of
each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
The second word
• * can be used only in the H version.
BL
10 0aaa aaaa
10 0aaa aaaa
10 0p00 pppp
10 0p00 pppp
00 0111 nnnn
00 0010 1011
BML
BLA
BMLA
SEA
SZD
Rev.1.02 2006.12.22 page 131 of 140
REJ03B0148-0102
4508 Group
Electrical characteristics
Absolute maximum ratings
Parameter
Symbol
VDD
Conditions
Ratings
–0.3 to 6.5
Unit
V
Supply voltage
–
–
Input voltage P0, P1, P2, D0–D3,
RESET, XIN
–0.3 to VDD+0.3
VI
V
Input voltage INT, CNTR0, CNTR1, SIN, SCK
Input voltage AIN0, AIN1, AIN4, AIN5
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
VI
–
V
V
V
VI
–
Output voltage P0, P1, P2, D
RESET
0–D3,
VO
Output transistors in cut-off state
–0.3 to VDD+0.3
–0.3 to VDD+0.3
300
Output voltage CNTR0, CNTR1, SOUT, SCK
Output voltage XOUT
V
V
VO
Output transistors in cut-off state
VO
–
mW
°C
°C
Power dissipation
Pd
Ta = 25 °C
–20 to 85
Operating temperature range
Storage temperature range
Topr
Tstg
–
–
–40 to 125
Rev.1.02 2006.12.22 page 132 of 140
REJ03B0148-0102
4508 Group
Recommended operating conditions 1
(Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Typ.
Symbol
VDD
Parameter
Supply voltage
Conditions
Unit
V
Max.
5.5
5.5
5.5
5.5
5.5
Min.
4
f(STCK) ≤ 6 MHz
f(STCK) ≤ 4.4 MHz
f(STCK) ≤ 2.2 MHz
f(STCK) ≤ 1.1 MHz
f(STCK) ≤ 4.4 MHz
(with a ceramic resonator)
2.7
2.0
1.8
2.7
V
V
VDD
VDD
Supply voltage
(with RC oscillation)
Supply voltage
5.5
5.5
1.8
1.6
(with an on-chip oscillator)
RAM back-up voltage
Supply voltage
V
V
V
VRAM
VSS
VIH
(at RAM back-up)
0
VDD
VDD
VDD
VDD
0.2VDD
0.3VDD
0.3VDD
0.15VDD
–20
–10
–10
–5
“H” level input voltage
P0, P1, P2, D0–D3
0.8VDD
XIN
0.7VDD
RESET
0.85VDD
INT, CNTR0, CNTR1, SIN, SCK
P0, P1, P2, D0–D3
XIN
0.85VDD
V
VIL
“L” level input voltage
0
0
0
0
RESET
INT, CNTR0, CNTR1, SIN, SCK
P0, P1, P2, D0–D3
CNTR0, CNTR1, SOUT, SCK
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
mA
mA
mA
IOH(peak) “H” level peak output current
IOH(avg) “H” level average output current P0, P1, P2, D0–D3
(Note)
CNTR0, CNTR1, SOUT, SCK
24
IOL(peak) “L” level peak output current
P0, P1
12
CNTR0, CNTR1, SOUT, SCK
P2, RESET
10
4.0
40
D0, D1
D2, D3
30
24
12
12
mA
IOL(avg)
“L” level average output current P0, P1
6.0
CNTR0, CNTR1, SOUT, SCK
P2, RESET
5.0
2.0
30
D0, D1
D2, D3
15
15
7.0
–40
–40
60
mA
mA
ΣIOH(avg) “H” level total average current
ΣIOL(avg) “L” level total average current
P0, P1, CNTR0, CNTR1, SOUT, SCK
P2, D0–D3
P0, P1, CNTR0, CNTR1, SOUT, SCK
P2, D0–D3, RESET
60
Notes 1: The average output current (IOH, IOL) is the average value during 100 ms.
Rev.1.02 2006.12.22 page 133 of 140
REJ03B0148-0102
4508 Group
Recommended operating conditions 2
(Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Typ.
Symbol
f(XIN)
Parameter
Unit
Conditions
VDD = 4.0 V to 5.5 V
Min.
Max.
6
MHz
Oscillation frequency
Through mode
(with a ceramic resonator)
4.4
2.2
1.1
6
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
Internal frequency divided
by 2
4.4
2.2
6
Internal frequency divided
by 4, 8
4.4
4.4
VDD = 2.7 V to 5.5 V
MHz
MHz
f(XIN)
f(XIN)
Oscillation frequency
(with RC oscillation) (Note 1)
Oscillation frequency
Through mode
VDD = 4.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.0 V to 5.5 V
VDD = 1.8 V to 5.5 V
4.8
3.2
(with a ceramic oscillation selected,
external clock input)
1.6
0.8
Internal frequency divided
by 2
4.8
3.2
1.6
Internal frequency divided
by 4, 8
4.8
3.2
CNTR0, CNTR1
CNTR0, CNTR1
Hz
s
f(CNTR) Timer external input frequency
tw(CNTR) Timer external input period
(“H” and “L” pulse width)
f(STCK)/6
3/f(STCK)
3/f(STCK)
Hz
s
f(SCK)
Serial interface external input period
SCK
SCK
f(STCK)/6
100
tw(SCK) Serial interface external input period
(“H” and “L” pulse width)
VDD = 0 → 1.8 V
µs
TPON
Power-on reset circuit
valid supply voltage rising time (Note 2)
Notes 1: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
2: If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest distance, and input “L” level
to RESET pin until the value of supply voltage reaches the minimum operating voltage.
When ceramic resonator is used
f(STCK)
When RC oscillation is used
f(STCK)
When external clock is used
f(STCK)
[MHz]
[MHz]
[MHz]
6
4.8
4.4
4.4
3.2
2.2
1.1
1.6
0.8
Recommended
operating condition
Recommended
operating condition
Recommended
operating condition
2.7
4
2.7
4
5.5
2
1.8
2
5.5
1.8
2.7
5.5
V
DD
V
DD
VDD
[V]
[V]
[V]
System clock (STCK) operating condition map
Rev.1.02 2006.12.22 page 134 of 140
REJ03B0148-0102
4508 Group
Electrical characteristics 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Symbol
VOH
Parameter
“H” level output voltage
Test conditions
IOH = –10 mA
Unit
V
Min.
3.0
4.1
2.1
2.4
Typ. Max.
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
IOH = –3.0 mA
IOH = –5.0 mA
IOH = –1.0 mA
IOL = 12 mA
IOL = 4.0 mA
IOL = 6.0 mA
IOL = 2.0 mA
IOL = 5.0 mA
IOL = 1.0 mA
IOL = 2.0 mA
IOL = 30 mA
IOL = 10 mA
IOL = 15 mA
IOL = 5.0 mA
IOL = 15 mA
IOL = 5.0 mA
IOL = 9.0 mA
IOL = 3.0 mA
P0, P1, P2, D0–D3
CNTR0, CNTR1, SOUT, SCK
VOL
“L” level output voltage
P0, P1
2.0
0.9
0.9
0.6
2.0
0.6
0.9
2.0
0.9
2.0
0.9
2.0
0.9
1.4
0.9
2.0
V
CNTR0, CNTR1, SOUT, SCK
VOL
VOL
“L” level output voltage
V
V
P2, RESET
VDD = 3.0 V
VDD = 5.0 V
“L” level output voltage
D0, D1
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VI = VDD
V
VOL
IIH
“L” level output voltage
D2, D3
µA
µA
“H” level input current
P0, P1, P2, D0–D3
RESET, INT
CNTR0, CNTR1, SIN, SCK
“L” level input current
P0, P1, P2, D0–D3
RESET, INT
VI = 0 V P0, P1, P2, D2, D3 No pull-up
IIL
–2.0
CNTR0, CNTR1, SIN, SCK
Pull-up resistor value
P0, P1, P2, D2, D3, RESET
VI = 0 V
VDD = 5.0 V
VDD = 3.0 V
60
120
1.0
0.4
0.2
0.2
500
250
120
kΩ
V
RPU
30
50
125
250
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 1.8 V
VT+ – VT– Hysteresis RESET
VT+ – VT–
V
Hysteresis INT, CNTR0, CNTR1
SIN, SCK
f(RING)
On-chip oscillator clock frequency
200
100
30
700
400
200
±17
±17
kHz
VDD = 5.0 V 10 %, Ta = center 25 °C
%
∆ f(XIN)
Oscillation frequency error
(Note 1)
(at RC oscillation, error value of external VDD = 3.0 V 10 %, Ta = center 25 °C
R, C not included)
Notes 1: When the RC oscillation is used, use a 33 pF capacitor externally.
Rev.1.02 2006.12.22 page 135 of 140
REJ03B0148-0102
4508 Group
Electrical characteristics 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
f(STCK) = f(XIN)/8
Unit
mA
Min.
Typ. Max.
VDD = 5.0 V
1.2
1.3
1.6
2.2
0.9
1
IDD
Supply current
2.4
2.6
3.2
4.4
1.8
2
at active mode
f(XIN) = 6.0 MHz
f(RING) = stop
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
(with a ceramic resonator)
(Notes 1, 2)
VDD = 5.0 V
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
mA
mA
µA
µA
µA
f(XIN) = 4.0 MHz
f(RING) = stop
1.2
1.6
0.2
0.25
0.3
0.4
50
2.4
3.2
0.4
0.5
0.6
0.8
100
120
160
240
20
VDD = 3.0 V
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
f(XIN) = 2.0 MHz
f(RING) = stop
VDD = 5.0 V
f(STCK) = f(RING)/8
f(STCK) = f(RING)/4
f(STCK) = f(RING)/2
f(STCK) = f(RING)
f(STCK) = f(RING)/8
f(STCK) = f(RING)/4
f(STCK) = f(RING)/2
f(STCK) = f(RING)
at active mode
f(XIN) = stop
60
(with an on-chip oscillator)
(Notes 1, 2)
f(RING) = operating
80
120
10
VDD = 3.0 V
f(XIN) = stop
13
26
f(RING) = opertaing
19
38
31
62
Ta = 25 °C
VDD = 5.0 V
VDD = 3.0 V
0.1
3
at RAM back-up mode
(POF instruction execution)
(Note 3)
10
6
Notes 1: When the A/D converter is used, the A/D operation current (IADD) is included.
2: In the M34508G4H, the voltage drop detection circuit operation current (IRST) is added.
3: In the M34508G4H, when the SVDE instruction is executed, the voltage drop detection circuit operation current (IRST) is added.
Rev.1.02 2006.12.22 page 136 of 140
REJ03B0148-0102
4508 Group
A/D converter recommended operating conditions
(Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
VDD
Parameter
Supply voltage
Conditions
Unit
V
Max.
5.5
Min.
2.0
2.7
0
Ta = 0 °C to 50 °C
Ta = –20 °C to 85 °C
5.5
VIA
Analog input voltage
V
VDD
334
123
61.2
15.3
kHz
f(ADCK) A/D clock frequency (Note)
VDD = 4.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.2 V to 5.5 V
VDD = 2.0 V to 5.5 V
0.8
0.8
0.8
0.8
Note: Definition of A/D conversion clock (ADCK)
MR3, MR2
System clock (STCK)
Division circuit
Divided by 8
Divided by 4
11
10
01
00
Instruction clock (INSTCK)
Internal clock
generating circuit
(divided by 3)
A/D clock
generating circuit
(divided by 6)
A/D conversion
clock (ADCK)
On-chip oscillator
MR0
Divided by 2
1
Ceramic resonance
X
IN
Multi-
plexer
0
RC oscillation
f(ADCK)
[kHz]
334
123
61.2
A/D clock
recommended
operating condition
15.3
0.8
2
2.2 2.7
4
5.5
VDD
[V]
A/D clock (ADCK) operating condition map
Rev.1.02 2006.12.22 page 137 of 140
REJ03B0148-0102
4508 Group
A/D converter characteristcs
(Ta = –20 °C to 85 °C, unless otherwise noted)
Limits
Typ.
Unit
Symbol
Parameter
Resolution
Test conditions
Max.
10
Min.
–
–
bits
Ta = 0 °C to 50 °C, 2.2 V ≤ VDD < 2.7 V
Ta = –20 °C to 85 °C, 2.7 V ≤ VDD ≤ 5.5 V
Ta = 0 °C to 50 °C, 2.2 V ≤ VDD < 2.7 V
Ta = –20 °C to 85 °C, 2.7 V ≤ VDD ≤ 5.5 V
VDD = 2.56 V
LSB
Linearity error
±4.0
±2.0
±0.9
±0.9
15
LSB
mV
–
Differential non-linearity error
Zero transition voltage
V0T
7.5
7.5
0
0
VDD = 3.075 V
15
VDD = 5.12 V
20
10
0
mV
VDD = 2.56 V
VFST
Full-scale transition voltage
2567.5
3079.5
5120
±8.0
2560
3072
5110
2552.5
3064.5
5100
VDD = 3.075 V
VDD = 5.12 V
LSB
µA
Ta = 0 °C to 50 °C, 2.0 V ≤ VDD < 2.2 V
–
Absolute accuracy
(Quantization error excluded)
A/D operating current (Note 1)
VDD = 5.0 V
IADD
TCONV
900
300
31
85
169
676
8
300
100
VDD = 3.0 V
µs
f(ADCK) = 334 kHz
f(ADCK) = 123 kHz
f(ADCK) = 61.2 kHz
f(ADCK) = 15.3 kHz
A/D conversion time
bits
mV
–
–
Comparator resolution
VDD = 2.56 V
Comparator error (Note 2)
15
15
20
4
VDD = 3.072 V
VDD = 5.12 V
µs
f(ADCK) = 334 kHz
f(ADCK) = 123 kHz
f(ADCK) = 61.2 kHz
f(ADCK) = 15.3 kHz
–
Comparator comparison time
11
22
88
Notes 1: When the A/D converter is used, the IADD is included to IDD.
2: As for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison
voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref
VDD
Vref =
✕ n
256
n = Value of register AD (n = 0 to 255)
Rev.1.02 2006.12.22 page 138 of 140
REJ03B0148-0102
4508 Group
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
V
Min.
Max.
–
VRST
Detection voltage
Ta = 25 °C
2.6
2.7
0.1
-20 °C ≤ Ta < 0 °C
0 °C ≤ Ta < 50 °C
50 °C ≤ Ta ≤ 85 °C
Ta = 25 °C
2.5
2.2
2
3.1
3
(reset occurs) (Note 2)
2.7
+
VRST
Detection voltage
V
-20 °C ≤ Ta < 0 °C
0 °C ≤ Ta < 50 °C
50 °C ≤ Ta ≤ 85 °C
(reset release) (Note 3)
2.6
2.3
2.1
3.2
3.1
2.8
+
VRST
VRST
IRST
–
Detection voltage hysteresis
Operation current (Note 4)
Detection time (Note 5)
V
–
VDD = 5 V
VDD = 3 V
50
30
100
60
µA
ms
–
TRST
VDD → (VRST – 0.1 V)
0.2
1.2
Notes 1: The voltage drop detection circuit is equipped with only the M34508G4H.
–
2: The detection voltage (VRST ) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
+
3: The detection voltage (VRST ) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs.
4: In the M34508G4H, IRST is added to IDD (supply current).
5: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST– – 0.1 V].
Basic timing diagram
Machine cycle
Mi
Mi+1
Pin name
STCK
Parameter
System clock
D0
–D
3
Port output
P0
P1
P2
0
0
0
–P0
–P1
, P2
3
3
1
D –D3
0
Port input
P0
P1
P2
0
0
0
–P0
–P1
, P2
3
3
1
Interrupt input
INT
Rev.1.02 2006.12.22 page 139 of 140
REJ03B0148-0102
4508 Group
Package outline
JEITA Package Code
RENESAS Code
Previous Code
20P2N-A
MASS[Typ.]
0.3g
P-SOP20-5.3x12.6-1.27
PRSP0020DA-A
20
11
F
NOTE)
1.
DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
2.
1
10
Index mark
*2
A2
A1
D
Dimension in Millimeters
Reference
Symbol
Min
12.5
5.2
Nom
12.6
5.3
Max
12.7
5.4
D
E
A2
A1
A
1.8
*3
bp
0
0.1
0.2
2.1
e
y
Detail F
bp
c
0.35
0.18
0.4
0.2
0.5
0.25
0
°
8°
HE
e
7.5
7.8
8.1
1.42
0.1
1.12
1.27
y
L
0.4
0.6
0.8
JEITA Package Code
RENESAS Code
PLSP0020JB-A
Previous Code
20P2F-A
MASS[Typ.]
0.1g
P-LSSOP20-4.4x6.5-0.65
11
20
NOTE)
F
1.
DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
2.
1
10
Index mark
A2
A1
Dimension in Millimeters
Reference
Symbol
*2
D
Min
6.4
4.3
Nom
6.5
Max
6.6
D
E
4.4
4.5
A2
A
1.15
1.45
0.2
A1
bp
c
0
0.1
*3
bp
e
0.17
0.13
0.22
0.15
0.32
0.2
Detail F
y
0
°
10°
HE
e
6.2
6.4
6.6
0.77
0.10
0.7
0.53
0.65
y
L
0.3
0.5
Rev.1.02 2006.12.22 page 140 of 140
REJ03B0148-0102
4508 Group Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Mar. 25, 2005
1.01 Aug. 12, 2005
First edition issued
–
1
Information about the PLSP0020JB-A package products.
“PLSP0020JB-A (20P2F-A)” added to PIN CONFIGURATION.
ROM Code Protect Address added.
17
52
57
58
Table 20: Some description about Port P1 added.
Fig.52 revised.
Fig.54 revised.
“DATA REQUIRED FOR QzROM WRITING ORDERS” added.
Notes On ROM Code Protect added.
62
130
A/D converter characteristics:
Linearity error, Differential non-linearity error and Absolute accuracy
→ Parameters and Test conditions revised.
-
+
131
132
2
Voltage drop detection circuit characteristics: VRST , VRST → Test conditions revised.
PLSP0020JB-A package added.
1.02 Dec. 22, 2006
Block diagram: “Power-on reset circuit” added.
Description (Note 4) about SCK pin revised.
TIMER: Description revised and Structure of Timer 2 in Table 9 revised.
Fig.23: INSTCK (wrong) → INTSNC (correct)
(2) Prescaler: PRS → RPS
5, 63
26
28
30
(3) Timer 3 → Timer 1
43
53
58
SERIAL I/O: Table 14: Note revised.
Fig. 46: Notes revised.
Table 23: Changes referring ahead and note 5 added.
59 to 61 QzROM Writing Mode added.
63
LIST OF PRECAUTIONS: Mulfunction revised.
68 to 71 NOTES ON NOISE added.
77
Description of Port output structure control register FR2 and FR3 revised.
103
107
117
134
Instruction code of TAL1 revised. Description of TALA revised.
TC1A eliminated.
Detailed description of TEAB revised.
f(SCK): Serial interface external input frequency →
Serial interface external input period
135
137
139
→
∆ f(XIN): Ta = around 25 °C → center 25 °C
Figure title revised, “When ceramic resonator is used” deleted.
Note 4: (power current) → (supply current)
Pages 80–82, 94, 95, 115, 122–129:
Description of SNZ0, SNZT1, SNZT2, SNZAD, SNZSI and WRST instructions revised.
(1/1)
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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