M37481E8FP [RENESAS]
8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES; 8位单片机740系列/ 7470系列
| 型号： | M37481E8FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES |
| 文件： | 总337页 (文件大小：2721K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no ces whatsoever have been
made to the contents of the document, and these changes do not cony alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business opof high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 7470 SERIES
7480 Group
7481 Group
User’s M
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable, but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi
Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility r any damage,
or infringement of any third-party’s rights, originating in e of any
product data, diagrams, charts or circuit application es contained in
these materials.
All information contained in these materials, g product data,
diagrams and charts, represent informatioducts at the time of
publication of these materials, and are to change by Mitsubishi
Electric Corporation without notice doduct improvements or other
reasons. It is therefore recommet customers contact Mitsubishi
Electric Corporation or an authMitsubishi Semiconductor product
distributor for the latest prormation before purchasing a product
listed herein.
Mitsubishi Electric Con semiconductors are not designed or
manufactured for device or system that is used under
circumstances h human life is potentially at stake. Please contact
Mitsubishi Eorporation or an authorized Mitsubishi Semiconductor
product distrr when considering the use of a product contained herein
for any specific purposes, such as apparatus or systems for transportation,
vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export
control restrictions, they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.
Preface
This user’s manual of the Mitsubishi CMOS 8-bit
microcomputer 7480 Group and 7481 Group describes
the hardware specifications and applications in detail.
For software information, refer to SERIES 740
<SOFTWARE> USER’S MANUAL, and for
development support tools (assemblers, debuggers,
etc.) refer to the mattached to each tool, as
well as data book MENT SUPPORT TOOLS
FOR MICROCRS.
BEFORE USING THIS USER’S MANUAL
1. Manual Contents
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
●
●
●
CHAPTER 1 – HARDWARE
This chapter describes the features of the microcomputers, the operation of their peripherals, and
their electrical characteristics.
CHAPTER 2 – APPLICATIONS
This chapter describes usage of peripheral functions and application examples of the microcomputers,
focusing on the settings of the related registers.
CHAPTER 3 – APPENDICES
This chapter describes all the control register configurations, and the ask ROM confirmation forms
(mask ROM version), the ROM programming confirmation forms (oPROM version), and the
mark specification forms to be submitted at the ordering.
2. Register Configurations
An example of control register configurations of the 7480 G7481 Group and the description of
symbols used in them are explained below.
Contents immediately after seased from reset (Note 1)
Bit
Bit attributes (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUMB16
]
0 0
R
O
W
0
b
0
1
Nam
Function
At reset
0
Fix these
0
0
O
O
0
2
O
Sttion bit
0 : Zero page
1 : 1 page
timer L count
selection bit
0 : f(XIN)/8
1 : f(XIN)/16
O
O
5
0
×
Undefined
Undefined
t implemented. Writing to this bit is disabled.
This bit is undefined at reading.
Undefined
×
Undefined
Not implemented. Writing to this bit is disabled.
This bit is undefined at reading.
Clock division
ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (medium-speed mode)
O
O
6
7
0
Undefined
×
Undefined
Not implemented. Writing to this bit is disabled.
This bit is undefined at reading.
Note: In the products whose RAM size is 192 bytes or less, set this bit to ‘0’.
indicates the bit which is not implemented.
Notes 1: Contents after system is released from reset
0: ‘0’ after system is released from reset
1: ‘1’ after system is released from reset
undefined: undefined after system is released from reset
2: Bit attributes
R (Read)
W (Write)
O: Write enabled
O: Read enabled
×: Read disabled
×: Write disabled
Undefined: Undefined at reading
0: ‘0’ at reading
0: Fixed to ‘0’
: This bit can be set to ‘0’ by software, but cannot be set to ‘1’.
1: ‘1’ at reading
Table of contents
Table of Contents
CHAPTER 1 HARDWARE
1.1 Product Summary ................................................................................................................. 1-2
1.2 Group Expansion .................................................................................................................. 1-3
1.3 Performance Overviews ....................................................................................................... 1-6
1.4 Pinouts .....................................................................................................................................1-8
1.5 Pin Descriptions .................................................................................................................. 1-10
1.6 Functional Block Diagrams.......................................................................................... 1-12
1.7 Central Processing Unit (CPU) ........................................................................ 1-15
1.7.1 Accumulator (A) ........................................................................................... 1-16
1.7.2 Index Register X (X) ................................................................................... 1-16
1.7.3 Index Register Y (Y) ................................................................................... 1-16
1.7.4 Stack Pointer (S) ......................................................................................... 1-16
1.7.5 Program Counter (PC) ................................................................................ 1-18
1.7.6 Processor Status Register (PS) ................................................................. 1-18
1.8 Access Area ......................................................................................................... 1-20
1.8.1 Zero Page (Addresses hrough ‘00FF16’) .................................................. 1-21
1.8.2 Special Page (Addre0016’ through ‘FFFF16’)............................................. 1-21
1.9 Memory Maps....................................................................................................... 1-22
1.10 Input/Output ....................................................................................................... 1-26
1.10.1 Block s .......................................................................................................... 1-26
1.10.2 Resociated with I/O Pins ......................................................................... 1-30
1.10.3 I/..................................................................................................................... 1-35
1.10.4 Termation of Unused Pins..................................................................................... 1-38
1.10.5 Notes on Usage ......................................................................................................... 1-39
1.11 Interrupts ............................................................................................................................ 1-41
1.11.1 Block Diagram ............................................................................................................ 1-42
1.11.2 Registers Associated with Interrupt Control ........................................................... 1-43
1.11.3 Interrupt Sources ....................................................................................................... 1-47
1.11.4 Interrupt Sequence .................................................................................................... 1-49
1.11.5 Interrupt Control ......................................................................................................... 1-53
1.11.6 Setting of Interrupts................................................................................................... 1-54
1.11.7 Notes on Usage ......................................................................................................... 1-56
7480 Group and 7481 Group User’s Manual
i
Table of contents
CHAPTER 3 APPENDICES
3.1 Control Registers .................................................................................................................. 3-2
3.2 Mask ROM Confirmation Forms....................................................................................... 3-20
3.3 ROM Programming Confirmation Forms........................................................................ 3-40
3.4 Mark Specification Forms ................................................................................................. 3-48
3.5 Package Outlines ................................................................................................................ 3-52
3.6 Machine instructions .......................................................................................................... 3-54
3.7 List of Instruction Codes .................................................................................................. 3-64
3.8 SFR Memory Map ...................................................................................................... 3-65
3.9 Pinouts .................................................................................................................. 3-66
7480 Group and 7481 Group User’s Manual
v
List of Figures
List of Figures
CHAPTER 1 HARDWARE
Figure 1.2.1 ROM/RAM Expansion Plan of 7480 Group and 7481 Group (As of September 1997) ............. 1-4
Figure 1.4.1 Pinout of 7480 Group (top view)........................................................................... 1-8
Figure 1.4.2 Pinout of 7481 Group (top view)........................................................................... 1-9
Figure 1.6.1 M37480Mx/E8-XXXSP/FP and M37480MxT/E8T-XXXSP/FP Functional Block Diagram ......... 1-12
Figure 1.6.2 M37481Mx/E8-XXXSP, M37481MxT/E8T-XXXSP and M37481E8SS Functional Block Diagram .. 1-13
Figure 1.6.3 M37481Mx/E8-XXXFP, M37481MxT/E8T-XXXFP Functional Block Diagram ...............................1-14
Figure 1.7.1 CPU Internal Registers ......................................................................................... 1-15
Figure 1.7.2 Operation for Pushing onto and Pulling from Stack ......................................... 1-17
Figure 1.8.1 Access Area ........................................................................................................... 1-20
Figure 1.9.1 Memory Maps of 7480 Group and 7481 Group ................................................ 1-23
Figure 1.9.2 Memory Map of SFR Area .............................................................................. 1-24
Figure 1.9.3 Memory Map of Interrupt Vector Area.................................................. 1-25
Figure 1.10.1 Block Diagrams of Port Pins P0i and P10–............................................... 1-27
Figure 1.10.2 Block Diagram of Port Pins P14–P17 ........................................................... 1-28
Figure 1.10.3 Block Diagrams of Port Pins P2i to P........................................................... 1-29
Figure 1.10.4 Memory Map of Registers Associa/O Pins ......................................1-30
Figure 1.10.5 Port Pi Registers (i = 0 to 5) ............................................................ 1-31
Figure 1.10.6 Port Pi Direction Registers (i , 5) ...................................................... 1-32
Figure 1.10.7 Port P0 Pull-up Control Re.................................................................. 1-33
Figure 1.10.8 Port P1 Pull-up Control ....................................................................... 1-33
Figure 1.10.9 Port P4P5 Input Conter ..................................................................... 1-34
Figure 1.10.10 Write and Read rt Pin ...................................................................... 1-35
Figure 1.10.11 Port P4 and P.................................................................................... 1-37
Figure 1.11.1 Block Diagrarrupt Inputs and Key-On Wakeup Circuit ...................1-42
Figure 1.11.2 Memory Mgisters Associated with Interrupt Control ........................1-43
Figure 1.11.3 Edge Plection Register....................................................................... 1-44
Figure 1.11.4 Interest Register 1 ............................................................................. 1-45
Figure 1.11.5 Inequest Register 2 ............................................................................. 1-45
Figure 1.11.6 Control Register 1 ............................................................................... 1-46
Figure 1.11.upt Control Register 2 ............................................................................... 1-46
Figure 1.11.8 Oeration When Interrupt Request is Accepted.............................................. 1-50
Figure 1.11.9 Processing Time from Interrupt Generation until Execution of Interrupt Service Routine.... 1-51
Figure 1.11.10 Timing at Interrupt Acceptance ....................................................................... 1-51
Figure 1.11.11 Interrupt Control Diagram................................................................................. 1-53
Figure 1.11.12 Setting of Interrupts (1) .................................................................................... 1-54
Figure 1.11.13 Setting of Interrupts (2) .................................................................................... 1-55
7480 Group and 7481 Group User’s Manual
i
List of Figures
Figure 1.12.1 Block Diagram of Timer X and Timer Y .......................................................... 1-58
Figure 1.12.2 Memory Map of Registers Associated with Timer X and Timer Y ...............1-59
Figure 1.12.3 Timer X ................................................................................................................. 1-60
Figure 1.12.4 Timer Y ................................................................................................................. 1-61
Figure 1.12.5 Timer X Mode Register ...................................................................................... 1-62
Figure 1.12.6 Timer Y Mode Register ...................................................................................... 1-63
Figure 1.12.7 Timer XY Control Register ............................................................................... 1-63
Figure 1.12.8 Operation Example in Timer Mode and Event Count Mode .........................1-67
Figure 1.12.9 Setting of Timer Mode and Event Count Mode (1) ........................................ 1-68
Figure 1.12.10 Setting of Timer Mode and Event Count Mode (2) ......................................1-69
Figure 1.12.11 Operation Example in Pulse Output Mode .................................................... 1-71
Figure 1.12.12 Setting of Pulse Output Mode (1) ................................................................... 1-72
Figure 1.12.13 Setting of Pulse Output Mode (2) ................................................................... 1-73
Figure 1.12.14 Operation Example in Pulse Period Measurement Mode ............................1-75
Figure 1.12.15 Setting of Pulse Period Measurement Mode ................................................. 1-76
Figure 1.12.16 Operation Example in Pulse Width MeasuremenMode .............................1-78
Figure 1.12.17 Setting of Pulse Width Measurement Mode ....................................... 1-79
Figure 1.12.18 Operation Example in Programmable Wavneration Mode ...........1-81
Figure 1.12.19 Setting of Programmable Waveform GeMode (1)..........................1-82
Figure 1.12.20 Setting of Programmable Waveform on Mode (2) ........................1-83
Figure 1.12.21 Operation Example in Programmahot Output Mode ...................1-85
Figure 1.12.22 Setting of Programmable One-Sut Mode (1) ..................................1-86
Figure 1.12.23 Setting of Programmable Onutput Mode (2) ..................................1-87
Figure 1.12.24 Operation Example in PW................................................................ 1-89
Figure 1.12.25 Setting of PWM Mode (..................................................................... 1-90
Figure 1.12.26 Setting of PWM Mod.......................................................................... 1-91
Figure 1.12.27 Operation in Timemer Y at Writes................................................... 1-92
Figure 1.12.28 Operation in TiTimer Y at Reads................................................... 1-93
Figure 1.13.1 Block Diagram r 1 and Timer 2 ........................................................... 1-95
Figure 1.13.2 Memory Misters Associated with Timer 1 and Timer 2 ................1-95
Figure 1.13.3 Timer 1 ................................................................................................. 1-96
Figure 1.13.4 Timer ...................................................................................................... 1-96
Figure 1.13.5 Timde Register....................................................................................... 1-97
Figure 1.13.6 Mode Register....................................................................................... 1-97
Figure 1.13.ions in Timer Mode ............................................................................... 1-100
Figure 1.13.8 ing of Timer Mode ...................................................................................... 1-101
Figure 1.13.9 Operations in Programmable Waveform Generation Mode .........................1-103
Figure 1.13.10 Setting of Programmable Waveform Generation Mode (1)........................1-104
Figure 1.13.11 Setting of Programmable Waveform Generation Mode (2)........................1-105
Figure 1.13.12 Operations in Timer 1 and Timer 2 at Reads.............................................1-106
7480 Group and 7481 Group User’s Manual
ii
List of Figures
Figure 1.14.1 Memory Map of Registers Associated with Serial I/O..................................1-107
Figure 1.14.2 Transmit/Receive Buffer Register .................................................................... 1-108
Figure 1.14.3 Serial I/O Status Register ................................................................................ 1-109
Figure 1.14.4 Serial I/O Control Register............................................................................... 1-111
Figure 1.14.5 UART Control Register ..................................................................................... 1-112
Figure 1.14.6 Baud Rate Generator........................................................................................ 1-113
Figure 1.14.7 Bus Collision Detection Control Register ....................................................... 1-113
Figure 1.14.8 Block Diagram of Clock Synchronous Serial I/O ..........................................1-116
Figure 1.14.9 Transmit Operation of Clock Synchronous Serial I/O ..................................1-118
Figure 1.14.10 Transmit Timing of Clock Synchronous Serial I/O......................................1-118
Figure 1.14.11 Receive Operation of Clock Synchronous Serial I/O .................................1-120
Figure 1.14.12 Receive Timing of Clock Synchronous Serial I/O.......................................1-120
Figure 1.14.13 Setting of Clock Synchronous Serial I/O (1) ...............................................1-121
Figure 1.14.14 Setting of Clock Synchronous Serial I/O (2) ...............................................1-122
Figure 1.14.15 Data Transfer Formats in UART ................................................................... 1-128
Figure 1.14.16 Block Diagram of UART ................................................................................ 1-129
Figure 1.14.17 Transmit Operation of UART .............................................................. 1-131
Figure 1.14.18 Transmit Timing example in UART ............................................... 1-131
Figure 1.14.19 Receive Operation of UART .......................................................... 1-133
Figure 1.14.20 Receive Timing Example in UART ................................................ 1-133
Figure 1.14.21 Setting of UART (1) ........................................................................ 1-134
Figure 1.14.22 Setting of UART (2) ........................................................................ 1-135
Figure 1.14.23 Contention bus system comms ...................................................... 1-138
Figure 1.14.24 Block Diagram of Bus Arbterrupt ..................................................1-138
Figure 1.14.25 Timing of Bus Collision n ................................................................. 1-139
Figure 1.14.26 Setting of Bus Arbitrrrupt ............................................................... 1-140
Figure 1.15.1 Block Diagram of Aerter..................................................................... 1-141
Figure 1.15.2 Memory Map of Associated with A-D Converter .........................1-142
Figure 1.15.3 A-D Control R...................................................................................... 1-142
Figure 1.15.4 A-D Conveister .................................................................................. 1-143
Figure 1.15.5 Change oersion Register and Comparison Voltage during A-D Conversion..... 1-145
Figure 1.15.6 SettinConversion ............................................................................... 1-146
Figure 1.15.7 Intivalent circuit of analog input circuit ..........................................1-148
Figure 1.16.1 gram of Watchdog Timer ................................................................. 1-149
Figure 1.16.y Map of Registers Associated with Watchdog Timer ......................1-149
Figure 1.16.3 chdog Timer H ............................................................................................ 1-150
Figure 1.16.4 CPU Mode Register .......................................................................................... 1-150
Figure 1.16.5 Internal Processing Sequence during Reset by Watchdog Timer ............. 1-152
Figure 1.16.6 Setting of Watchdog Timer .............................................................................. 1-153
Figure 1.17.1 Internal Processing Sequence after Reset Release .....................................1-155
Figure 1.17.2 Internal State at Reset ..................................................................................... 1-156
Figure 1.18.1 Block Diagram of Clock Generator ................................................................. 1-158
Figure 1.18.2 Memory Map of Register Associated with Oscillation Circuit ......................1-159
Figure 1.18.3 CPU Mode Register .......................................................................................... 1-159
Figure 1.18.4 Oscillator Start-Up Stabilization Time at Power On .....................................1-161
Figure 1.19.1 Transitions from Power Saving Modes........................................................... 1-163
Figure 1.19.2 Memory Map of Registers Associated with Power Saving ..........................1-164
Figure 1.19.3 STP Instruction Operation Control Register ..................................................1-164
Figure 1.19.4 Edge Polarity Selection Register..................................................................... 1-165
Figure 1.19.5 Operation at Recovery from Stop Mode by Reset Input .............................1-166
Figure 1.19.6 Operation Example at Recovery from Stop Mode by INT0 Interrupt......... 1-167
Figure 1.19.7 Setting of Valid/Invalid of STP and WIT Instructions ...................................1-169
7480 Group and 7481 Group User’s Manual
iii
List of Figures
Figure 1.20.1 Pinout in EPROM Mode of 7480 Group ........................................................ 1-172
Figure 1.20.2 Pinout in EPROM Mode of 7481 Group (1) ..................................................1-173
Figure 1.20.3 Pinout in EPROM Mode of 7481 Group (2) ..................................................1-174
Figure 1.20.4 Programming and Verification of One Time PROM Version .......................1-178
Figure 1.21.1 Timing Diagram ................................................................................................. 1-190
Figure 1.21.2 Measurement Circuit of Typical Power Source Current Characteristics ... 1-190
Figure 1.21.3 VCC–ICC Characteristics (at System Operating in High-Speed Mode) ...... 1-191
Figure 1.21.4 VCC–ICC Characteristics (at System Operating in Medium-Speed Mode). 1-191
Figure 1.21.5 VCC–ICC Characteristics (in Wait Mode) ........................................................ 1-192
Figure 1.21.6 VCC–ICC Characteristic (in Stop Mode) .......................................................... 1-192
Figure 1.21.7 f(XIN)–ICC Characteristics (at System Operating in High-Speed Mode) .... 1-193
Figure 1.21.8 f(XIN)–ICC Characteristics (at System Operating in Medium-Speed Mode)1-193
Figure 1.21.9 Measurement Circuits of Typical Port Characteristics..................................1-194
Figure 1.21.10 VOH–IOH Characteristics on P-Channel Side of Programmable I/O Port (CMOS Output) 1-194
Figure 1.21.11 VOL–IOL Characteristics on N-Channel Side of Programmable I/O Port (CMOS Output) 1-195
Figure 1.21.12 VIL–IIL Characteristics of Pull-up Transistor of Programmae I/O Port (CMOS Output) 1-195
Figure 1.21.13 Typical Characteristics of A-D Conversion (1) ..................................1-197
Figure 1.21.14 Typical Characteristics of A-D Conversion ..................................1-198
CHAPTER 2 APPLICATIONS
Figure 2.1.1 External Circuit for Output Ports ........................................................... 2-2
Figure 2.1.2 Simplified External Circuit Example by l Shift Port and Noise Margin..................2-3
Figure 2.2.1 Setting Example of Division R................................................................ 2-4
Figure 2.2.2 Control Procedure Example ms Processing ............................................ 2-5
Figure 2.2.3 Peripheral Circuit Examp......................................................................... 2-6
Figure 2.2.4 Method of Measuring ow Rate................................................................ 2-6
Figure 2.2.5 Control Procedure of Measuring Water Flow Rate............................. 2-7
Figure 2.2.6 Peripheral Circuie ..................................................................................... 2-8
Figure 2.2.7 Setting Examision Ratio......................................................................... 2-8
Figure 2.2.8 Control Proxample of Buzzer Output .................................................... 2-9
Figure 2.2.9 PeripherExample ................................................................................... 2-10
Figure 2.2.10 Phal Procedure Example ................................................................... 2-11
Figure 2.2.11 PCircuit Example................................................................................. 2-12
Figure 2.2.12 nication Format Example....................................................................... 2-12
Figure 2.2.13 munications Control Procedure Example.................................................. 2-13
Figure 2.2.14 Pripheral Circuit Example................................................................................. 2-14
Figure 2.2.15 Operation Timing Example ................................................................................. 2-14
Figure 2.2.16 Control Procedure Example of Motorcycle Engine ......................................... 2-15
Figure 2.2.17 Peripheral Circuit Example................................................................................. 2-16
Figure 2.2.18 Operation Timing Example ................................................................................. 2-16
Figure 2.2.19 Phase Control Procedure Example ................................................................... 2-17
Figure 2.2.20 Peripheral Circuit Example................................................................................. 2-18
Figure 2.2.21 Control Procedure Example of Analog Voltage Output ..................................2-19
7480 Group and 7481 Group User’s Manual
iv
List of Figures
Figure 2.3.1 Connection Example ............................................................................................. 2-20
Figure 2.3.2 Setting Example of Synchronous Clock ............................................................. 2-20
Figure 2.3.3 Timing of Interrupt Control ................................................................................... 2-21
Figure 2.3.4 Control Procedure Example of Serial I/O Transmit .......................................... 2-21
Figure 2.3.5 Connection Example ............................................................................................. 2-22
Figure 2.3.6 Setting Example of Synchronous Clock ............................................................. 2-22
Figure 2.3.7 Communication Format ......................................................................................... 2-22
Figure 2.3.8 Control Procedure Example of Serial I/O Receive ........................................... 2-23
Figure 2.3.9 Connection Example ............................................................................................. 2-24
Figure 2.3.10 Setting Example of Synchronous Clock ........................................................... 2-24
Figure 2.3.11 Communication Format Example of Simplified SAE J1850 ...........................2-25
Figure 2.3.12 Communication Timing Example ....................................................................... 2-26
Figure 2.3.13 Control Procedure Example (1) of LAN Communications..............................2-27
Figure 2.3.14 Control Procedure Example (2) of LAN Communications..............................2-28
Figure 2.4.1 Example of Determining A-D Conversion Values.............................................. 2-30
Figure 2.4.2 Control Procedure Example of Determining A-D Cnversion Values.............2-31
Figure 2.5.1 Reset Circuit Examples ............................................................................. 2-32
Figure 2.6.1 Oscillation Circuit Example with Ceramic Res.................................... 2-33
Figure 2.6.2 External Clock Circuit Example ........................................................... 2-33
Figure 2.7.1 Connection Example ............................................................................. 2-34
Figure 2.7.2 Operation Example in Key-Input Wai................................................. 2-34
Figure 2.7.3 Control Procedure Example of Pog in Key-Input Waiting State.... 2-35
Figure 2.7.4 Connection Example ............................................................................. 2-36
Figure 2.7.5 Operation Example in Serial ive Waiting State..................................2-36
Figure 2.7.6 Control Procedure Examper-Saving ................................................... 2-37
Figure 2.8.1 Wiring for RESET Pin ........................................................................... 2-38
Figure 2.8.2 Wiring for Clock I/O .............................................................................. 2-39
Figure 2.8.3 Wiring for VPP PiTime PROM and EPROM Version .......................2-39
Figure 2.8.4 Bypass Capacis VSS Line and VCC Line ............................................ 2-40
Figure 2.8.5 Bypass Caposs VSS Line and VREF Line .......................................... 2-40
Figure 2.8.6 Analog Siand Resistor and Capacitor ............................................... 2-40
Figure 2.8.7 Wiring e Current Signal Line ................................................................ 2-41
Figure 2.8.8 Wirinal Line Where Potential Levels Change Frequently.................2-41
Figure 2.8.9 Vns on Underside of Oscillator............................................................ 2-41
Figure 2.8.1For I/O Ports ........................................................................................... 2-42
Figure 2.8.11 chdog Timer by Software ............................................................................ 2-43
Figure 2.9.1 Initialization of Flags in PS .................................................................................. 2-44
Figure 2.9.2 Stack Memory Contents after PHP Instruction Execution................................2-44
Figure 2.9.3 PLP Instruction Execution .................................................................................... 2-44
Figure 2.9.4 Execution of Decimal Operation .......................................................................... 2-45
Figure 2.11.1 Application Circuit to Hot-Water Supply Equipment ....................................... 2-48
Figure 2.11.2 Application Circuit to Motorcycle Single-Cylinder Engine ..............................2-49
7480 Group and 7481 Group User’s Manual
v
List of Figures
CHAPTER 3 APPENDICES
Figure 3.1.1 Port Pi Registers (i = 0 to 5) ................................................................................ 3-2
Figure 3.1.2 Port Pi Direction Registers (i = 0, 1, 4, 5).......................................................... 3-2
Figure 3.1.3 Port P0 Pull-up Control Register........................................................................... 3-3
Figure 3.1.4 Port P1 Pull-up Control Register........................................................................... 3-3
Figure 3.1.5 Port P4P5 Input Control Register ......................................................................... 3-4
Figure 3.1.6 Edge Polarity Selection Register ........................................................................... 3-5
Figure 3.1.7 A-D Control Register............................................................................................... 3-6
Figure 3.1.8 A-D Conversion Register ........................................................................................ 3-6
Figure 3.1.9 STP Instruction Operation Control Register......................................................... 3-7
Figure 3.1.10 Transmit/Receive Buffer Register ........................................................................ 3-8
Figure 3.1.11 Serial I/O Status Register .................................................................................... 3-8
Figure 3.1.12 Serial I/O Control Register................................................................................... 3-9
Figure 3.1.13 UART Control Register ......................................................................................... 3-9
Figure 3.1.14 Baud Rate Generator.......................................................................................... 3-10
Figure 3.1.15 Bus Collision Detection Control Register ................................................ 3-10
Figure 3.1.16 Watchdog Timer H .............................................................................. 3-11
Figure 3.1.17 Timer X ................................................................................................. 3-12
Figure 3.1.18 Timer Y ................................................................................................. 3-13
Figure 3.1.19 Timer 1 ................................................................................................. 3-13
Figure 3.1.20 Timer 2 ................................................................................................. 3-14
Figure 3.1.21 Timer X Mode Register ...................................................................... 3-14
Figure 3.1.22 Timer Y Mode Register ...................................................................... 3-15
Figure 3.1.23 Timer XY Control Regist.................................................................... 3-15
Figure 3.1.24 Timer 1 Mode Registe......................................................................... 3-16
Figure 3.1.25 Timer 2 Mode Regi.............................................................................. 3-16
Figure 3.1.26 CPU Mode Regis.................................................................................. 3-17
Figure 3.1.27 Interrupt Requter 1 ............................................................................. 3-18
Figure 3.1.28 Interrupt Register 2 ............................................................................. 3-18
Figure 3.1.29 Interrupt Register 1 ............................................................................... 3-19
Figure 3.1.30 Interrul Register 2 ............................................................................... 3-19
Figure 3.8.1 SFR Map ................................................................................................. 3-65
Figure 3.9.1 Pi480 Group (top view)......................................................................... 3-66
Figure 3.9.2 f 7481 Group (top view)......................................................................... 3-67
7480 Group and 7481 Group User’s Manual
vi
List of Tables
List of Tables
CHAPTER 1 HARDWARE
Table 1.2.1 Supported Products of 7480 Group and 7481 Group.......................................... 1-5
Table 1.3.1 Performance Overview of 7480 Group .................................................................. 1-6
Table 1.3.2 Performance Overview of 7481 Group .................................................................. 1-7
Table 1.7.1 Push and Pull Instructions for Accumulator and Processor Status Register. 1-16
Table 1.7.2 Instructions to Set Flags of Processor Status Register to ‘1’ or ‘0’................1-19
Table 1.9.1 RAM Area ................................................................................................................ 1-22
Table 1.9.2 ROM Area................................................................................................................ 1-22
Table 1.10.1 Termination of Unused Pins................................................................................ 1-38
Table 1.11.1 Interrupt Sources .................................................................................................. 1-41
Table 1.11.2 Interrupt Sources Available for CPU’s Return from Stop/Wait Mode ............1-52
Table 1.12.1 Relation between Timer Count Periods and Values Set to r X and Timer Y ................. 1-65
Table 1.13.1 Relation between Timer Count Periods and Values Set and Timer 2 .................. 1-99
Table 1.14.1 Clearing Error Flags ........................................................................... 1-110
Table 1.14.2 Example of Baud Rates ..................................................................... 1-127
Table 1.14.3 Setting of UART Control Register .................................................... 1-128
Table 1.14.4 Function of UART Transfer Data Bi.................................................. 1-129
Table 1.19.1 States of Microcomputer in PowModes .........................................1-162
Table 1.20.1 Supported Built-in PROM Veructs in 7480 Group and 7481 Group
(As of September 1997) .................................................................... 1-171
Table 1.20.2 Pin Functions in EPROM .................................................................... 1-172
Table 1.20.3 Pin Descriptions (1)............................................................................ 1-175
Table 1.20.4 Pin Descriptions (2.............................................................................. 1-176
Table 1.20.5 I/O Signals in Eode ............................................................................ 1-177
Table 1.21.1 Absolute Maxtings of 7480 Group ....................................................1-180
Table 1.21.2 Recommenating Conditions of 7480 Group (1) ..............................1-180
Table 1.21.3 Recommperating Conditions of 7480 Group (2) ..............................1-181
Table 1.21.4 Electracteristics of 7480 Group (1)...................................................1-182
Table 1.21.5 Eleharacteristics of 7480 Group (2)...................................................1-183
Table 1.21.6 ersion Characteristics of 7480 Group .............................................1-184
Table 1.21.7 te Maximum Ratings of 7481 Group ....................................................1-185
Table 1.21.8 Rommended Operating Conditions of 7481 Group (1) ..............................1-185
Table 1.21.9 Recommended Operating Conditions of 7481 Group (2) ..............................1-186
Table 1.21.10 Electrical Characteristics of 7481 Group (1).................................................1-187
Table 1.21.11 Electrical Characteristics of 7481 Group (2).................................................1-188
Table 1.21.12 A-D Conversion Characteristics of 7481 Group ...........................................1-189
Table 1.21.13 Necessary Conditions for Timing and Switching Characteristics .............. 1-190
CHAPTER 2 APPLICATIONS
Table 2.10.1 Functions added to the 7480 Group and 7481 Group .................................... 2-46
Table 2.10.2 Functions Revised from 7477 Group and 7478 Group ...................................2-47
7480 Group and 7481 Group User’s Manual
i
CHAPTER 1
HARDWARE
1.ct Summary
oup Expansion
Performance Overviews
.4 Pinouts
1.5 Pin Descriptions
1.6 Functional Block Diagrams
1.7 Central Processing Unit (CPU)
1.8 Access Area
1.9 Memory Maps
1.10 Input/Output Pins
1.11 Interrupts
1.12 Timer X and Timer Y
1.13 Timer 1 and Timer 2
1.14 Serial I/O
1.15 A-D Converter
1.16 Watchdog Timer
1.17 Reset
1.18 Oscillation Circuit
1.19 Power Saving Function
1.20 Built-in PROM Version
1.21 Electrical Characteristics
HARDWARE
1.1 Product Summary
1.1 Product Summary
The 7480 Group and 7481 Group are 8-bit microcomputers fabricated using Mitsubishi’s silicon gate CMOS
process. They have a simple instruction set with ROM, RAM, and input/output (I/O) interface that are located
in the same memory area.
These microcomputers contain a serial I/O, an A-D converter, and a watchdog timer on a single chip, so
that they are most suitable for control use in automotive controls, office machines, and home appliances.
The 7480 Group and 7481 Group offer products with various types and sizes of built-in memories, as well
as several choice of packages.
7480 Group and 7481 Group User's Manual
1-2
HARDWARE
1.2 Group Expansion
1.2 Group Expansion
The 7480 Group and 7481 Group are included in the 7470 series microcomputers, based on the M37470M2-
XXXSP.
The 7470 series is classified as follows:
7470 series
7470 Group
7471 Group
7477 Group
7478 Group
7480 Group
7481 Group
Figure 1.2.1 shows the ROM/RAM expansion plan for the 7480 Group and 7481 Group.
Since these products are different only in the type and size of built-in memory, and the number of ports,
the most suitable product for user’s system can be easily selected.
The following products are supported in the 7480 Group and 7481 Group in addition to the mask ROM
version.
(1) One Time PROM Version
This is a programmable microcomputer with built-in programM (PROM) that can be written
to only one time.
For details, refer to Section 1.20 Built-in PROM Vers
(2) Built-in EPROM Version (with Window)
This is a programmable microcomputer with a rent window on top of its package. Built-in
EPROM can be written and erased.
For details, refer to Section 1.20 Built-iVersion.
Table 1.2.1 lists the products currently sin the 7480 Group and 7481 Group.
7480 Group and 7481 Group User's Manual
1-3
HARDWARE
1.2 Group Expansion
ROM size
(bytes)
M37480M8T-XXXSP/FP
M37480E8T-XXXSP/FP
M37481M8T-XXXSP/FP
M37481E8T-XXXSP/FP
M37481E8SS
16 K
12 K
8 K
M37480M8-XXXSP/FP
M37480E8-XXXSP/FP
M37481M8-XXXSP/FP
M37481E8-XXXSP/FP
M37480M4-XXXSP/FP
M37480M4T-XXXSP/FP
M37481M4-XXXSP/FP
M37481M4T-XXXSP/FP
M37480M2T-XXXSP/FP
M37481M2T-XXXSP/FP
4 K
RAM size
(bytes)
0
128
25
384
448
Note: Regarding the products being devlanned, the development
schedule may be reviewed. Regoducts being planned, the
development of them may be
: Under development
: Under planning
Figure 1.2.1 ROM/RAM Expansio7480 Group and 7481 Group (As of September 1997)
7480 Group and 7481 Group User's Manual
1-4
HARDWARE
1.2 Group Expansion
Table 1.2.1 Supported Products of 7480 Group and 7481 Group
(As of September 1997)
Remarks
ROM
RAM
Product
I/O Ports
Package
(bytes) (bytes)
M37480M2T-XXXSP
M37480M2T-XXXFP
M37480M4-XXXSP
M37480M4-XXXFP
M37480M4T-XXXSP
M37480M4T-XXXFP
M37480M8-XXXSP
M37480M8-XXXFP
M37480M8T-XXXSP
M37480M8T-XXXFP
M37480E8SP
32P4B
Mask ROM version (Note)
4096
8192
128
256
32P2W-A
32P4B
Mask ROM version
32P2W-A
32P4B
Mask ROM version (Note)
Mask ROM version
32P2W-A
32P4B
I/O ports: 18
Input ports: 8
32P2W-A
(Including 4 analog 32P4B
Mask ROM version (Note)
input pins.)
32P2W-A
32P4B
One ime PROM version
16384
448
M37480E8FP
32P2W-A (Sin blank)
32P4B
M37480E8-XXXSP
M37480E8-XXXFP
M37480E8T-XXXSP
M37480E8T-XXXFP
M37481M2T-XXXSP
M37481M2T-XXXFP
M37481M4-XXXSP
M37481M4-XXXFP
M37481M4T-XXXSP
M37481M4T-XXXFP
M37481M8-XXXSP
M37481M8-XXXFP
M37481M8T-XXXSP
M37481M8T-XXXFP
M37481E8SP
ime PROM version
32P2W
32P
One Time PROM version (Note)
Mask ROM version (Note)
Mask ROM version
3
4096
8192
128
256
6N-A
2P4B
44P6N-A
42P4B
Mask ROM version (Note)
Mask ROM version
44P6N-A
42P4B
s: 24
44P6N-A
42P4B
t ports: 12
ncluding 8 analog
input pins.)
Mask ROM version (Note)
44P6N-A
42P4B
One Time PROM version
16
48
M37481E8FP
44P6N-A (Shipped in blank)
42P4B
M37481E8-XXXSP
M37481E8-XXXFP
M37481E8T-XXXSP
M37481E8T-XXXFP
M37481E8SS
One Time PROM version
44P6N-A
42P4B
One Time PROM version (Note)
44P6N-A
42S1B-A
Built-in EPROM version
Note: Extended Operating Temperature Range Version.
7480 Group and 7481 Group User's Manual
1-5
HARDWARE
1.3 Performance Overviews
1.3 Performance Overviews
Tables 1.3.1 and 1.3.2 list the performance overviews of the 7480 Group and 7481 Group, respectively.
Table 1.3.1 Performance Overview of 7480 Group
Items
Performance
71 (69 basic instructions of 740 Family and 2 Multiply and
Number of Basic Instructions
Divide instructions)
0.5 µs (the minimum instructions at f(XIN) = 8 MHz)
Instruction Execution Time
Clock Input Oscillation Frequency
M37480M2
8 MHz (Max.)
4096 bytes
ROM
M37480M4
8192 bytes
M37480M8/E8
16384 bytes
Memory
Size
M37480M2
128 bytes
RAM
M37480M4
256 bytes
M37480M8/E8
448 bytes
P0
8 bits
I/O
P1
8 bits
Input/
Output
Ports
P4
2 bits
P2
4 bits
Input
P3
4 bits
Input/Output Voltage
5 V
Input/Output
–5 mA (P0, P1: CMOS 3-State Buffer)
4: N-Channel open-drain)
× 1
Output Current
Characteristics
Serial I/O
Timers
bit timer × 2
8-bit timer × 2
M37480M2
64 levels (Max.)
M37480M4
96 levels (Max.)
Subroutine Nesting
M37480
192 levels (Max.)
5 external, 8 internal, and 1 software interrupt sources
4-channel analog inputs
(alternative function of Port 2 pins)
Built-in circuit with a feedback resistor; a ceramic resonator external
Built-in circuit
Interrupt Sources
A-D Converter
(Successive Comparison Conversion)
Clock Generator
Watchdog Timer
2.7 V to 4.5 V (f(XIN) = (2.2 VCC–2) MHz)
4.5 V to 5.5 V (f(XIN) = 8 MHz)
35 mW (typical value at f(XIN) = 8 MHz)
–20 °C to 85 °C (–40 °C to 85 °C for Extended Operating
Temperature Range Version)
CMOS Silicon Gate
Power Supply
Power Dissipation
Operating Temperature Range
Device Structure
M37480Mx/E8-XXXSP
32-Pin Shrink Plastic DIP
32-Pin Plastic SOP
M37480MxT/E8T-XXXSP
M37480Mx/E8-XXXFP
M37480MxT/E8T-XXXFP
Package
7480 Group and 7481 Group User's Manual
1-6
HARDWARE
1.3 Performance Overviews
Table 1.3.2 Performance Overview of 7481 Group
Performance
Items
71 (69 basic instructions of 740 Family and 2 Multiply and
Number of Basic Instructions
Divide instructions)
0.5 µs (the minimum instructions at f(XIN) = 8 MHz)
Instruction Execution Time
Clock Input Oscillation Frequency
M37481M2
8 MHz (Max.)
4096 bytes
ROM
M37481M4
8192 bytes
M37481M8/E8
16384 bytes
Memory
Size
M37481M2
128 bytes
RAM
M37481M4
256 bytes
M37481M8/E8
448 bytes
P0
8 bits
P1
8 bits
I/O
Input/
Output
Ports
P4
4 bits
P5
4 bits
P2
8 bits
Input
P3
4 bits
Input/Output Voltage
5 V
Input/Output
–5 mA to P0, P1: CMOS 3-State Buffer)
10 mA N-Channel open-drain)
8 b
Output Current
Characteristics
Serial I/O
Timers
er × 2
mer × 2
M37481M2
levels (Max.)
M37481M4
96 levels (Max.)
Subroutine Nesting
M37481M8/E8
192 levels (Max.)
5 external, 8 internal, and 1 software interrupt sources
8-channel analog inputs
(alternative function of Port 2 pins)
Built-in circuit with a feedback resistor; a ceramic resonator external
Built-in circuit
Interrupt Sources
A-D Converter
(Successive Comparison Conv
Clock Generator
Watchdog Timer
2.7 V to 4.5 V (f(XIN) = (2.2 VCC–2) MHz)
4.5 V to 5.5 V (f(XIN) = 8 MHz)
35 mW (typical value at f(XIN) = 8 MHz)
–20 °C to 85 °C (–40 °C to 85 °C for Extended Operating
Temperature Range Version)
CMOS Silicon Gate
Power Supply
Power Dissipation
Operating Temperature Range
Device Structure
M37481Mx/E8-XXXSP
42-Pin Shrink Plastic DIP
42-Pin Shrink Ceramic DIP
44-Pin Plastic QFP
M37481MxT/E8T-XXXSP
M37481E8SS
Package
M37481Mx/E8-XXXFP
M37481MxT/E8T-XXXFP
7480 Group and 7481 Group User's Manual
1-7
HARDWARE
1.4 Pinouts
1.4 Pinouts
Figures 1.4.1 and 1.4.2 show the pinouts of the 7480 Group and 7481 Group, respectively. For the pinouts
of the built-in PROM versions used in the EPROM mode, refer to Section 1.20.1 EPROM mode.
Pinout (top view)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P3
P3
7
6
5
4
3
2
1
0
1
0
3
2
P1
P1
P1
P1
7
/SRDY
1
2
6
/SCLK
5
/TX
D
3
4
/RX
D
4
P1
3
/T
1
0
1
0
5
P1
2/T
6
P1
P1
7
8
P2
3/IN
2/IN
1/IN
0
/IN
3
2
1
0
/CNTR
1
0
9
P2
P2
P2
/CNTR
10
11
12
13
14
V
REF
IN
OUT
SS
P3
1
/INT
1
0
X
P3
0
/INT
X
RESET
15
16
V
V
CC
Outline 32P4B✽1
32
31
26
25
24
23
22
21
20
19
18
17
P0
P0
P0
P0
P4
P4
P3
P3
4
3
2
1
0
1
0
3
2
P1
7
/SRDY
/SCLK
1
2
P1
6
P1
5
/TX
D
3
P1
4
/RX
D
4
P1
3
/T
1
0
1
0
5
P1
2/T
6
P1
P1
7
8
P2
3/IN
2/IN
1/IN
3
2
/CNTR
1
0
P2
P2
P2
/CNTR
13
14
15
16
T
SS
P3
1
/INT
1
0
P3
0
/INT
RESET
V
V
CC
Outline 32P2W-A✽2
✽ 1: The M37480M2T-XXXSP, M37480M4-XXXSP and M37480M4T-XXXSP are also included in the 32P4B packages,
respectively. All of these products are pin-compatible.
2: The M37480M2T-XXXFP, M37480M4-XXXFP and M37480M4T-XXXFP are also included in the 32P2W-A packages,
respectively. All of these products are pin-compatible.
Note:
The only differences between the 32P4B package product and the 32P2W-A package product are package outline and
absolute maximum ratings.
Figure 1.4.1 Pinout of 7480 Group (top view)
7480 Group and 7481 Group User's Manual
1-8
HARDWARE
1.4 Pinouts
Pinout (top view)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
P52
P53
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
P07
P06
4
5
P05
P04
6
P03
7
P02
8
P01
9
P10
P00
10
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P43
11
12
13
14
15
16
17
18
19
20
21
P42
P41/CNTR1
P40/CNTR0
P33
P32
P31/INT1
P30/INT0
RESET
P51
XIN
XOUT
P50
VSS
VCC
✽1
Outline 42P4B
42S1B-A (M37481E8SS)
P04
22
21
20
19
P30/INT0
RESET
P51
34
35
36
37
38
39
40
43
44
P05
P06
P07
P52
VSS
P50
VCC
MXXFP
T-XXXFP
E8-XXXFP
81E8T-XXXFP
18
17
16
15
14
13
12
VSS
AVSS
P53
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
XOUT
XIN
VREF
P20/IN0
Outline 44P6N-A ✽2
✽ 1: The M37481M2T-XXXSP, M37481M4-XXXSP and M37481M4T-XXXSP are also included in the 42P4B packages,
respectively. All of these products are pin-compatible.
2: The M37481M2T-XXXFP, M37481M4-XXXFP and M37481M4T-XXXFP are also included in the 44P6N-A packages,
respectively. All of these products are pin-compatible.
Note:
The only differences between the 42P4B package product and the 44P6N-A package product are package outline,
absolute maximum ratings and the fact that the 44P6N-A package product has the AVss pin.
Figure 1.4.2 Pinout of 7481 Group (top view)
7480 Group and 7481 Group User's Manual
1-9
HARDWARE
1.5 Pin Descriptions
1.5 Pin Descriptions
Tables 1.5.1 and 1.5.2 list the pin descriptions.
For pin functions in the EPROM mode of the built-in PROM version, refer to Section 1.20.2 Pin Descriptions.
Table 1.5.1 Pin Descriptions (1)
Input/
Pin
Name
Function
Output
VCC, VSS Power source
• Apply the following voltage to the VCC pin:
2.7 V to 4.5 V (at f(XIN) = (2.2 VCC–2) MHz), or
4.5 V to 5.5 V (at f(XIN) = 8 MHz).
• Apply 0 V to the VSS pin.
• Ground level input pin for the A-D converter
• Apply the same voltage as for the VSS pin to the AVSS
pin.
AVSS
VREF
Analog power source
Note: This pin is dedicated 4P6N-A package products
in the 7481 Grou
• Reference voltage for A-D converter
• Apply the folloage to the VREF pin:
2 V to VCC VCC = 2.7 V to 4.0 V, or
0.5 VCC VCC V when VCC = 4.0 V to 5.5 V.
Note: using A-D converter, connect VREF pin to
Reference voltage input
Input
• put pin
RESET
XIN
Reset input
Clock input
Clock output
Input
m Reset: Holding the LOW level for 2 µs or more
ces CPU into reset state.
I/O pins for clock generator
• A ceramic resonator is connected between pins XIN and
XOUT.
• When an external clock is used, it is input to XIN pin, and
leave XOUT pin open.
XOUT
Output
• A feedback resistor is built in between pins XIN and XOUT.
7480 Group and 7481 Group User's Manual
1-10
HARDWARE
1.5 Pin Descriptions
Table 1.5.2 Pin Descriptions (2)
Input/
Output
I/O
Pin
Name
I/O port P0
Function
P00–P07
• 8-bit I/O port pins
• The output structure is CMOS output.
• When an input port is selected, a pull-up transistor can
be connectable by the bit.
• In input mode, a key-on wake up function is provided.
• 8-bit I/O port pins
I/O
P10–P17
I/O port P1
• The output structure is CMOS output.
• When an input port is selected, a pull-up transistor can
be connected by the 4 bits.
• P12 and P13 serve the alternative functions of the timer
output pins T0 and T1.
• P14, P15, P16, and P17 he alternative functions of
the serial I/O pins RxDCLK and SRDY, respectively.
• 8-bit input port pi
Input
P20–P27
Input port P2
• P20–P27 serve rnative functions of the analog
input pins I
Note: The 7has only four pins of P20–P23 (IN0–IN3).
• 4-bit pins
Input
I/O
P30–P33
P40–P43
Input port P3
I/O port P4
• P3serve the alternative functions of the external
input pins INT0 and INT1.
I/O port pins
e output structure is N-channel open-drain outputs with
built-in clamping diodes.
• P40 and P41 serve the alternative functions of the timer
I/O pins CNTR0 and CNTR1.
Note: The 7480 Group has only two pins of P40 and P41.
• 4-bit I/O port pins
I/O
P50–P53
I/O port P5
• The output structure is N-channel open-drain outputs with
built-in clamping diodes.
Note: The 7480 Group is not provided with port P5.
7480 Group and 7481 Group User's Manual
1-11
HARDWARE
1.6 Functional Block Diagrams
1.6 Functional Block Diagrams
Figures 1.6.1, 1.6.2 and 1.6.3 show the functional block diagrams of the 7480 Group and 7481 Group.
Figure 1.6.1 M37480Mx/E8-XXXSP/FP and M37480MxT/E8T-XXXSP/FP Functional Block Diagram
7480 Group and 7481 Group User's Manual
1-12
HARDWARE
1.6 Functional Block Diagrams
Figure 1.6.2 M37481Mx/E8-XXXSP, M37481MxT/E8T-XXXSP and M37481E8SS Functional Block Diagram
7480 Group and 7481 Group User's Manual
1-13
HARDWARE
1.6 Functional Block Diagrams
Figure 1.6.3 M37481Mx/E8-XXXFP, M37481MxT/E8T-XXXFP Functional Block Diagram
7480 Group and 7481 Group User's Manual
1-14
HARDWARE
1.7 Central Processing Unit (CPU)
1.7 Central Processing Unit (CPU)
The 7480 Group and 7481 Group have the CPU common to the 740 family.
For the description of the instructions, refer to the following:
• Section 3.6 Machine Instructions
• 740 FAMILY CPU CORE BASIC FUNCTIONS: ADDRESSING MODE in data book SINGLE CHIP 8-BIT
MICROCOMPUTERS
• SERIES 740 <SOFTWARE> USER’S MANUAL
The instructions which characterize the group are as follows:
1. FST and SLW instructions are excluded.
2. MUL and DIV instructions are available.
3. WIT instruction is available (Note).
4. STP instruction is available (Note).
Note: For the above instructions, refer to Section 1.19 Power Saving Function.
The CPU has the six registers (CPU internal registers).
Figure 1.7.1 shows the CPU internal registers.
7
7
0
A
X
ulator
Index register X
7
0
0
S
Index register Y
Stack pointer
7
7
0
0
15
8
PCL
Program counter
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Figure 1.7.1 CPU Internal Registers
7480 Group and 7481 Group User's Manual
1-15
HARDWARE
1.7 Central Processing Unit (CPU)
States of the CPU internal registers immediately after system is released from reset are as follows:
• The interrupt disable flag (I) of the processor status register (PS) is set to ‘1’.
• The high-order 8 bits (PCH) of the program counter contain the contents of address ‘FFFF16’, and the low-
order 8 bits (PCL) contain the contents of address ‘FFFE16’.
Since the contents of the CPU internal registers not mentioned above are undefined immediately after
system is released from reset, it is necessary to initialize these registers by software.
1.7.1 Accumulator (A)
The accumulator is an 8-bit register. Data manipulations, such as arithmetic or logical operation and
transfers, are performed using this register.
1.7.2 Index Register X (X)
Index register X is an 8-bit register that performs addressing in the index addressing mode.
1.7.3 Index Register Y (Y)
Index register Y is an 8-bit register that performs addressing for certain inns in the index addressing
mode.
1.7.4 Stack Pointer (S)
The stack pointer is an 8-bit register. It indicates the start adhe stack area where the contents
of registers pushed at subroutine call or interrupt are store
The low-order 8 bits in the stack are addressed by thpointer, and the high-order 8 bits are
addressed by the content of the stack page selection this bit is ‘0’, the high-order 8 bits indicate
‘0016’, and when ‘1’, they indicate ‘0116’.
For the 7480 Group and 7481 Group, the staselection bit is assigned to bit 2 of the CPU mode
register (address 00FB16). Set this bit to ‘ssary, because it is cleared to ‘0’ at reset.
Note: In the 7480 Group and 7481 Groupr, the product with RAM whose memory size is 192 bytes
or less does not have RAM on Therefore, clear this bit to ‘0’.
Figure 1.7.2 shows the operation ing onto and pulling from the stack. Push the contents of
necessary registers other than tcribed here onto stack by software.
Table 1.7.1 lists the push antructions for the accumulator and the processor status register.
Initialize the stack pointtware because it is undefined immediately after system is released from
reset.
Table 1.7.1 Push and Pull Instructions for Accumulator and Processor Status Register
Push Instructions
Pull Instructions
Accumulator
PHA
PHP
PLA
PLP
Processor Status Register
7480 Group and 7481 Group User's Manual
1-16
HARDWARE
1.7 Central Processing Unit (CPU)
Routine being executed
•
•
•
•
•
•
•
When an interrupt is accepted
Interrupt request (Note)
M(S)←(PC
(S)←(S) – 1
M(S)←(PC
H)
Push the return
address onto stack
L
)
•
•
•
•
•
•
•
(S)←(S) – 1
M(S)←(PS)
(S)←(S) – 1
Push the contents of
processor status
register onto stack
Execute JSR
When a subroutine is called
g: ‘0’ → ‘1’
etch the jump
vector
Interrupt se
rout
M(S)←(PC
(S)←(S) – 1
M(S)←(PC
H)
Push the
return address
onto stack
L
)
•
•
•
•
•
•
•
(S)←(S) – 1
cute RTI
Subroutine
Pull the contents of
processor status
register from stack
(S)←(S) + 1
(PS)←M(S)
(S)←(S) + 1
(PC
(S)←(S) + 1
(PC )←M(S)
L)←M(S)
Pull the return
address from stack
Execute RTS
(S)←(S) + 1
H
(PC
(S)←(S) +
(PC
L)←M(S)
Pull the return
address from
stack
H
: Operation performed by software
: Operation automatically performed by hardware
Note: Condition for acceptance of an interrupt
•
•
•
Interrupt disable flag is ‘0’ (enabled state)
Interrupt enable bit is ‘1’ (enabled state)
Figure 1.7.2 Operation for Pushing onto and Pulling from Stack
7480 Group and 7481 Group User's Manual
1-17
HARDWARE
1.7 Central Processing Unit (CPU)
1.7.5 Program Counter (PC)
The program counter is a 16-bit counter consisting of the high-order 8 bits (PCH) and the low-order 8 bits
(PCL). The program counter indicates the address of the program memory to be next fetched.
At reset, the high-order 8 bits (PCH) of the program counter contain the contents of address ‘FFFF16’, and
the low-order 8 bits (PCL) contain the contents of address ‘FFFE16’.
1.7.6 Processor Status Register (PS)
The processor status register is an 8-bit register. This register consists of 5 flags which hold the states
immediately after arithmetic or logical operation, and 3 flags which determine the CPU operation.
C, Z, V, and N flags are used to test the branch instructions. However, Z, V, and N flags are invalid in the
decimal mode.
Each flag of the processor status register is described below. Also, Table 1.7.2 lists the instructions that
set these flags to ‘1’ or ‘0’.
(1) Carry Flag C (bit 0)
This flag holds a carry or a borrow from the arithmetic logic unit after folowing an arithmetic or logical
operation. Also, the shift and rotate instructions can affect the conf this flag.
The Carry flag is set to ‘1’ by using the SEC instruction and to ‘0’ by using the CLC
instruction.
(2) Zero Flag Z (bit 1)
This flag is ‘1’ when the result of an arithmetic, logicafer operation is ‘0’, otherwise it is ‘0’.
The Zero flag is invalid in the decimal mode.
There is no instruction that can affect the conteflag.
(3) Interrupt Disable Flag I (bit 2)
This flag disables all interrupts except tinstruction interrupt. When it is set to ‘1’, interrupt
is disabled. When an interrupt is acce flag automatically goes to ‘1’.
This flag is set to ‘1’ by using the ruction and cleared to ‘0’ by using the CLI instruction.
Note: This flag is set to ‘1’ (intabled) at reset.
(4) Decimal Mode Flag D (b
This flag determines whdition and subtraction are performed in the binary or decimal mode.
When this flag is ‘0’, binary operation is performed; On the other hand, when it is ‘1’, an 8-
bit word is handlecimal number of two digits. Decimal adjust is automatically performed in
the decimal operatioowever, the decimal operation can be performed only at the ADC and SBC
instructions.
This flag is set to ‘1’ by using the SED instruction and cleared to ‘0’ by using the CLD instruction.
Note: This flag is undefined at reset; then it is necessary to initialize this flag because it directly
affects the result of arithmetic operation.
7480 Group and 7481 Group User's Manual
1-18
HARDWARE
1.7 Central Processing Unit (CPU)
(5) Break Flag B (bit 4)
This flag recognizes whether an interrupt occurs by using the BRK instruction. The contents of
processor status register are pushed onto the stack when the following occurs;
• the contents of this flag is set to ‘1’ when an interrupt occurs by using the BRK instruction, or
• this flag is set to ‘0’ by the all other interrupts.
There is no instruction that can affect the content of this flag.
(6) Index X Mode Flag T (bit 5)
When this flag is ‘0’, operation is performed between the accumulator and memories. When this flag
is ‘1’, operation is directly done between memories without using the accumulator. This flag is set
to ‘1’ by using the SET instruction and cleared to ‘0’ by using the CLT instruction.
Note: This flag is undefined at reset; it is therefore necessary to initialize this flag because it directly
affects the result of operation.
(7) Overflow Flag V (bit 6)
This flag is used in adding or subtracting an 8-bit word as signed binary digits. When the result of
addition or subtraction exceeds the range of +127 to -128, this set to ‘1’. When the BIT
instruction is executed, the content of bit 6 of the activated meritten to the flag.
This flag is cleared to ‘0’ by using the CLV instruction. Howevis no instruction that can set
this flag to ‘1’.
In the decimal mode, this flag is invalid.
(8) Negative Flag N (bit 7)
When the result of arithmetic, logical or transfer is negative (bit 7 is ‘1’), this flag is set to
‘1’. When the BIT instruction is executed, the of bit 7 of the activated memory is written to
the flag.
There is no instruction that can directly e content of this flag.
In the decimal mode, this flag is inv
Table 1.7.2 Instructions to Set Flags essor Status Register to ‘1’ or ‘0’
C Flag
Z
Flag
D Flag
V Flag
–
N Flag
–
B Flag
T Flag
Instructions to Set
Flags to ‘1’
SEC
SEI
SED
–
SET
Instructions to Set
Flags to ‘0’
C
–
CLI
CLD
CLV
–
–
CLT
7480 Group and 7481 Group User's Manual
1-19
HARDWARE
1.8 Access Area
1.8 Access Area
For the 7480 Group and 7481 Group, all ROM, RAM and I/O and various control registers are located in
the same access area. Therefore, data transfer, arithmetic and logical operations can be accomplished by
the same instructions without identifying between memory and I/O interface.
The program counter consists of 16 bits and can access the 64K-byte area of addresses ‘000016’ through
‘FFFF16’.
The area of the least significant 256 bytes (addresses ‘000016’ through ‘00FF16’) is called the ‘zero page’.
Frequently accessed memory such as an internal RAM, I/O ports, timers, etc are located in this area.
Furthermore, the area of the most significant 256 bytes (addresses ‘FF0016’ through ‘FFFF16’) is called the
‘special page’. An internal ROM and interrupt vectors are located in this area.
Both the zero page and the special page can be accessed with two bytes, using the specific mode for each
page.
Figure 1.8.1 shows the outline of the access area.
000016
RAM
ro page
00C016
00FF16
SFR area
RAM
ROM
Special page
Interrupt vector area
FFFF16
Figure 1.8.1 Access Area
7480 Group and 7481 Group User's Manual
1-20
HARDWARE
1.8 Access Area
1.8.1 Zero Page (Addresses ‘000016’ through ‘00FF16’)
The area of 256 bytes from addresses ‘000016’ through ‘00FF16’ is called the zero page. The internal RAM
and the special function registers (SFR) are located in this area.
The addressing modes shown in Table 1.8.1 are used to specify memory or registers in this area. In the
mode listed, the zero page addressing mode can be used to access this area by shorter instruction cycles.
1.8.2 Special Page (Addresses ‘FF0016’ through ‘FFFF16’)
The area of 256 bytes from addresses ‘FF0016’ through ‘FFFF16’ is called the special page. The internal
ROM and the interrupt vector area are located in this area.
The addressing modes shown in Table 1.8.1 are used to specify memory or subroutines in this area. In
the mode listed, the special page addressing mode can be used to jump to this area by shorter instruction
cycles.
Ordinary, frequently used subroutines are located in this area.
Table 1.8.1 Addressing Mode Accessible to Each Area
Addressing Mode
Reference to Zero Page Reference to Special PReference to Other Areas
(Required Bytes)
Zero Page (2)
O
O
O
O
O
O
O
O
O
O
–
–
–
–
–
Zero Page Indirect (2)
Zero Page X (2)
Zero Page Y (2)
Zero Page Bit (2)
Zero Page Bit Relative (3)
Absolute (3)
–
–
–
–
–
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
–
Absolute X (3)
Absolute Y (3)
Relative (2)
Indirect (3)
Indirect X (2)
Indirect Y (2)
Special Page (2)
7480 Group and 7481 Group User's Manual
1-21
HARDWARE
1.9 Memory Maps
1.9 Memory Maps
Figure 1.9.1 shows the memory maps of the 7480 Group and 7481 Group.
Memories and I/Os located in the access area are described below.
●
●
●
RAM
The internal RAM is located in the area listed in Table 1.9.1. Internal RAM is used for data storage,
the stack area used subroutine call or interrupt generation.
To prevent the contents of RAM from being destroyed, take the depth of subroutine nesting and the
level of interrupt into consideration when using RAM as the stack area.
Special Function Registers (SFR) (Addresses ‘00C016’ through ‘00FF16’)
Special function registers (SFR) are assigned to addresses ‘00C016’ through ‘00FF16’. Various control
registers for the I/O ports, the timers, the serial I/O, the A-D converter, and the interrupts are located
in the SFR area.
Figure 1.9.2 shows the memory map of the SFR area.
ROM
The internal ROM is located in the area listed in Table 1.9.2. ROM is used to store data
tables and programs. In the 7480 Group and 7481 Group, a‘FFE416’ through ‘FFFF16’ of
the ROM area are assigned to the vector area where the dresses after system is released
from reset and interrupt generation are stored.
Figure 1.9.3 shows the memory map of the interruparea.
Table 1.9.1 RAM Area
Product
Range orea
RAM Size
128 × 8 bits
256 × 8 bits
448 × 8 bits
M3748xM2
Addresses ‘000016’ through ‘0
M3748xM4
Addresses ‘000016’ through Addresses ‘010016’ through ‘013F16’
Addresses ‘000016’ throu6’, Addresses ‘010016’ through ‘01FF16’
M3748xM8/E8
Table 1.9.2 ROM Area
Product
M3748xM2
M3748xM4
M3748xM8
M3748xE8
Memory
Mask RO
Range of ROM Area
Addresses ‘F00016’ through ‘FFFF16’
Addresses ‘E00016’ through ‘FFFF16’
ROM Size
4K × 8 bits
8K × 8 bits
Mask R
Mask ROM
PROM
Addresses ‘C00016’ through ‘FFFF16’
16K × 8 bits
7480 Group and 7481 Group User's Manual
1-22
HARDWARE
1.9 Memory Maps
M37480M2
M37481M2
M37480M4
M37481M4
M37480M8/E8
M37481M8/E8
000016
000016
000016
RAM
RAM
RAM
(128 bytes)
(192 bytes)
(192 bytes)
007F16
008016
00BF16
00C016
Zero page
Not used
00BF16
00C016
00FF16
010016
00BF
00C01166
SFR area
SFR area
SFR area
00FF16
010016
00FF16
RAM
RAM
(64 bytes)
(256 bytes)
013F16
01FF16
C00016
Not used
Not used
Noed
E00016
F00016
FF0016
ROM
(4096 bytes)
ROM
(16384 bytes)
FF001
FF0016
Special
page
FFE416
FFFF16
F
FFE416
FFFF16
Interrupt vector area
rupt vector area
Interrupt vector area
Figure 1.9.1 Memory Maps oroup and 7481 Group
7480 Group and 7481 Group User's Manual
1-23
HARDWARE
1.9 Memory Maps
Port P0 register (P0)
Transmit/receive buffer register (TB/RB)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
00C016
00C116
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
Port P0 direction register (P0D)
00C216 Port P1 register (P1)
Port P1 direction register (P1D)
00C316
00C416
00C516
00C616
00C716
00C816
Port P2 register (P2)
Bus collision detection control register (BUSARBCON)
Port P3 register (P3)
Port P4 register (P4)
00C916 Port P4 direction register (P4D)
00CA16 Port P5 register (P5)
(Note)
00CB16 Port P5 direction register (P5D)
00CC16
00CD16
00CE16
00CF16
00EF16 Watchdog timer H (WDTH)
00F016 Timer X low-order
Port P0 pull-up control register (P0PCON)
Port P1 pull-up control register (P1PCON)
Port P4P5 input control register (P4P5CON)
00D016
00D116
00D216
00D316
Timer X high-or
00F216 Timer Y low-
00F116
Timer Y YH)
Timer
00F316
00F416
00D416 Edge polarity selection register (EG)
00D516
00D616
00D716
00D816
00F516 Tim
00F616 de register (TXM)
00F71
00
6
mode register (TYM)
XY control register (TXYCON)
mer 1 mode register (T1M)
Timer 2 mode register (T2M)
CPU mode register (CPUM)
A-D control register (ADCON)
00D916
00DA16 A-D conversion register (AD)
00DB16
00DC16
00DD16
FC16 Interrupt request register 1 (IREQ1)
00FD16
00FE16 Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Interrupt request register 2 (IREQ2)
00DE16
00DF16
STP instruction operation control register (STPCO
00FF16
Note: These registers are not allocated in the 7480 Group.
Figure 1.9.2 Memory MR Area
7480 Group and 7481 Group User's Manual
1-24
HARDWARE
1.9 Memory Maps
FFE416
FFE516
FFE616
FFE716
FFE816
FFE916
FFEA16
FFEB16
FFEC16
FFED16
FFEE16
FFEF16
FFF016
FFF116
FFF216
FFF316
FFF416
FFF516
FFF616
FFF716
FFF816
FFF916
FFFA16
FFFB16
FFFC16
FFFD16
FFFE16
FFFF16
BRK instruction interrupt
A-D conversion completion interrupt
Bus arbitration interrupt
Serial I/O transmit interrupt
Serial I/O receive interrupt
Timer 2 interrupt
Timer 1 interrupt
Timer Y interrupt
Timer X interrupt
CNTR
1
0
interrupt
interrupt
CNTR
INT1 interrupt or key-on w
INT0
i
Note: Refer to Secerrupts for each interrupt overview.
Figure 1.9.3 Memory Map of Interor Area
7480 Group and 7481 Group User's Manual
1-25
HARDWARE
1.10 Input/Output Pins
1.10 Input/Output Pins
The Input/Output (I/O) pins of the 7480 Group and 7481 Group are classified as follows:
• I/O port pins (P00–P07, P10–P17, P40–P43, and P50–P53)
• Input port pins (P20–P27 and P30–P33)
• Reset input pin (RESET)
• Clock input and output pins (XIN and XOUT)
• A-D conversion reference voltage input pin (VREF)
• Power source pins (VCC, VSS, and AVSS)
Notes 1: The 7480 Group does not have port pins P24–P27, P42, P43, and P50–P53.
2: The AVSS pin is dedicated to the 44P6N-A package products in the 7481 Group.
For the functions of each pin, refer to Section 1.5 Pin Descriptions.
1.10.1 Block Diagrams
Figures 1.10.1, 1.10.2, and 1.10.3 show the block diagrams of the I/O annput port pins.
7480 Group and 7481 Group User's Manual
1-26
HARDWARE
1.10 Input/Output Pins
● Port P0
Pull-up control
register
Tr1
Direction register
Port latch
Data bus
Port pins P0i (i = 0 to 7)
Interrupt control circuit
Tr1: Pull-up transistor
● Ports P10–P13
Pull-up control
register
Data bus
Tr3
Tr4
Timer 2 operation
mode bit
Direction register
Port latch
Port P13 pin
Data bus
T1
Timer 1 op
mod
Direction register
Port latch
Port P1
2
pin
pin
pin
Data bus
T0
ion register
Port latch
Data bus
Port P11
Tr5
Direction register
Port latch
Port P1
0
Data bus
Tr2 to Tr5: Pull-up transistor
Figure 1.10.1 Block Diagrams of Port Pins P0i and P10–P13
7480 Group and 7481 Group User's Manual
1-27
HARDWARE
1.10 Input/Output Pins
● Ports P14–P17
Serial I/O enable bit
Serial I/O mode selection bit
S
RDY output enable bit
Tr6
Direction register
Port latch
Port P1
7
pin
Data bus
S
RDY
Serial I/O synchronous clock
selection bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O enable bit
Tr7
Direction register
Port latch
Port P1
6
pin
pin
pin
Data bus
S
CLK output
Serial I/O enable bit
Transmit enable bit
Tr8
Direction register
Port latch
Port P1
5
Data bus
xD
Seriit
e bit
Tr9
Direction register
Port latch
Port P1
4
Data bus
RxD
Pull-up control
register
Data bus
Tr6 to Tr9: Pull-up transistor
Figure 1.10.2 Block Diagram of Port Pins P14–P17
7480 Group and 7481 Group User's Manual
1-28
HARDWARE
1.10 Input/Output Pins
● Port P2
Port pins P2
i
(i = 0 to 7 for 7481 Group,
i = 0 to 3 for 7480 Group)
Data bus
Multi-
plexer
A-D conversion circuit
● Port P3
Data bus
Port pins P3
i
(i = 0 to 3)
INT0, INT1
● Ports P40 and P41
‘001’
‘100’
‘101’
‘110’
Timer X, Y operating
mode bits
Port pins P40 and P41
Direction register
Port latch
Data bus
Timer out
CNTR0, CNTR1 input
● Ports P42, P43, and P5
Port pins P42, P43, and P5i (i=0 to 3)
Dection register
Port latch
Data bus
Port P4P5 input control register
• For the 7480 Group, set this register to ‘0016’.
• For the 7481 Group, set the bit corresponding to the port
set to the input mode to ‘1’.
Figure 1.10.3 Block Diagrams of Port Pins P2i to P5i
7480 Group and 7481 Group User's Manual
1-29
HARDWARE
1.10 Input/Output Pins
1.10.2 Registers Associated with I/O Pins
Figure 1.10.4 shows the memory map of the registers associated with I/O pins.
Port P0 register (P0)
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
Port P0 direction register (P0D)
Port P1 register (P1)
Port P1 direction register (P1D)
Port P2 register (P2)
Port P3 register (P3)
Port P4 register (P4)
Port P4 direction register (P4D)
Port P5 register (P5)
te)
Port P5 direction register (P5D)
Port P0 pull-up control register (P
00D016
00D116
00D216
Port P1 pull-up control registN)
Port P4P5 input control re5CON)
Note: These not allocated in the 7480 Group.
Figure 1.10.4 Memory Map of Ressociated with I/O Pins
7480 Group and 7481 Group User's Manual
1-30
HARDWARE
1.10 Input/Output Pins
(1) Port Pi Registers (i = 0 to 5)
Each port register can read the states of the port pins and specify the output levels of them.
Pin used for input (Ports P0 to P5)
• A read: When reading from port register corresponding to each port, the input value (state of the
pin) is read; the contents of port latch is not read.
• A write: When writing to port register corresponding to each port, data is written only into the port
latch; the state of the pin is unaffected.
Pin used for output (Ports P0, P1, P4, and P5)
• A read: When reading from port register corresponding to each port, the written value into the port
latch is read; the state of the pin is not read. Therefore, even if the output voltage is
affected by the external load etc., the last output value can correctly be read.
• A write: When writing to port register corresponding to each port, data written into a bit of the port
register can be output to the external circuit through the output transistor.
Note: The 7480 Group does not have port P5 and, consequently, provided with the port P5
register.
Figure 1.10.5 shows the port Pi registers (i = 0 to 5).
Port Pi (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi, i=0 to 00C016,00C216,00C416,00C616,00C816,00CA16]
At reset
R
W
b
Function
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
O
O
O
O
O
O
0
1
s input ports (Ports P0 to P5)
ng, input level of pin is read.
ting, writing to port latch is performed and
pin state is not affected.
hen used as output ports (Ports P0, P1, P4, P5)
• At reading, the last written value into the port latch is
read.
O
O
O
O
O
O
6
• At writing, the written value is output externally through
a transistor.
O
O
O
O
7
Note: • In the 74oup, port P2 has only bits 0 to 3. The other bits are not implemented. (undefined at reading).
• Port P3 has only bits 0 to 3. The other bits are not implemented (‘0’ at reading).
• In the 7480 Group, port P4 has only bits 0 and 1. In the 7481 Group, port P4 has only bits 0 to 3.
The other bits are not implemented. (bits 4 to 7: ‘0’ at reading, bits 2 and 3 in the 7480 Group: undefined).
• The 7480 Group does not have port P5. In the 7481 Group, port P5 has only bits 0 to 3.
The other bits are not implemented. (‘0’ at reading).
Figure 1.10.5 Port Pi Registers (i = 0 to 5)
7480 Group and 7481 Group User's Manual
1-31
HARDWARE
1.10 Input/Output Pins
(2) Port Pi Direction Registers (i = 0, 1, 4, 5)
These registers switch the input and output of the programmable I/O port pins P00–P07, P10–P17,
P40–P43, and P50–P53.
Note: The 7480 Group does not have port P5 and, consequently, is not provided with the port P5
direction register.
Figure 1.10.6 shows the port Pi direction registers (i = 0, 1, 4, 5).
Port Pi direction register (i=0,1,4,5)
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD, i=0,1,4,5) [Addresses 00C116,00C316,00C916,00CB16
]
R
O
W
O
b
0
Name
reset
Function
0 : Input mode
Port Pi direction register (Note)
1 : Output mode
0 : Input mode
1 : Output mode
0
1
2
3
4
5
6
7
O
O
O
O
O
O
0 : Input mode
1 : Output m
0 : Inpu
1 : O
0
0
0
O
O
O
O
ode
t mode
utput mode
0
0
O
O
O
O
0 : Input mode
1 : Output mode
0 : Input mode
1 : Output mode
Note: • In the 7480 Group, port P4 direction ly bits 0 and 1. In the 7481 Group, port P4 direction register
has only bits 0 to 3. The other bitmented (bits 4 to 7: ‘0’ at reading, bits 2 and 3 in the 7480 Group:
undefined).
• The 7480 Group does not hection register. In the 7481 Group, port P5 has only bits 0 to 3.
The other bits are not impt reading).
Figure 1.10.6 Port Pi DirRegisters (i = 0, 1, 4, 5)
7480 Group and 7481 Group User's Manual
1-32
HARDWARE
1.10 Input/Output Pins
(3) Port Pi Pull-up Control Registers (i = 0, 1)
When any pin of ports P0 and P1 is used for input, the corresponding bit of the port Pi pull-up control
register controls the pull-up of the pin.
Pull-up control is performed by the ON/OFF switch of a pull-up transistor. Pull-up control is valid only
when the pin is used for input and invalid when used for output or serial I/O.
Note: Port P1 controls the pull-up of high- or low-order four bits at one time. Even if only port P10
pin is pulled high, for example, port pins P11–P13 are also pulled high simultaneously.
Figures 1.10.7 and 1.10.8 show the port P0 and the port P1 pull-up control registers.
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 pull-up control register (P0PCON) [Address 00D016
]
R
O
W
O
b
0
Name
Function
No pull-up
set
P0
0
pull-up control bit
0 : P0
1 : P0
0
0
Pull-up
0 : P0
1 : P0
1
1
No pul
Pull
1
2
P0
1
2
pull-up control bit
pull-up control bit
0
0
O
O
O
O
O
O
P0
0 : P0
1 : P
3
P03
pull-up control bit
0
l-up
up
0
4
No pull-up
Pull-up
O
O
O
O
4
5
P0
4
5
pull-up control bi
pull-up co
0
0
P0
0 : P0
1 : P0
5
5
No pull-up
Pull-up
6
7
P0
6
pu
ntrol bit
0
0
0 : P0
1 : P0
6
6
No pull-up
Pull-up
O
O
O
O
0 : P0
1 : P0
7
7
No pull-up
Pull-up
control is valid when the corresponding port is set to the input mode.
Figure 1.10.7 Port P0 Pull-ol Register
Port P1 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P1 pull-up control register (P1PCON) [Address 00D116]
Name
Function
R
O
W
O
b
0
At reset
0
P13–P10 pull-up
control bit
0 : P10–P13 No pull-up
1 : P10–P13 Pull-up
1
0 : P14–P17 No pull-up
1 : P14–P17 Pull-up
0
O
O
P17–P14 pull-up
control bit
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
×
×
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
2
3
Not implemented.
Writing to these bits is disabled.
These bits are undefined at reading.
×
×
×
4
5
6
×
7
Note: Pull-up control is valid only when the corresponding port is set to the input mode.
When port pins P15–P17 are used as serial I/O pins, pull-up control of
the corresponding port pins is invalid.
Figure 1.10.8 Port P1 Pull-up Control Register
7480 Group and 7481 Group User's Manual
1-33
HARDWARE
1.10 Input/Output Pins
(4) Port P4P5 Input Control Register
When port pins P42, P43, and P50–P53 of the 7481 Group are used as input ports, set the corresponding
bits of the port P4P5 input control register to ‘1’.
Note: The 7480 Group does not have port pins P42, P43, and P50–P53; therefore, set the port P4P5
input control register to ‘0016’.
Figure 1.10.9 shows the port P4P5 input control register.
Port P4P5 input control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P4P5 input control register (P4P5CON) [Address 00D216
]
0 0 0 0 0 0
b
0
Name
Function
, P4 are used as
At ret
R
O
W
O
P4
2
, P4
3
input control bit When the P4
2
3
the input port, set this bit to ‘1’.
1
2
P5 input control bit
Not implemented.
Writing to these bits is disabled.
These bits are ‘0’ at reading.
When the P5 is used as th
port, set this bit to ‘1’.
0
O
O
×
×
×
0
0
3
4
5
0
0
0
0
0
0
0
0
×
×
×
6
7
0
Note: 7480 Group does not ha2, P43 and P5, so set this register to ‘0016’.
Figure 1.10.9 Port P4P5 Input Control Re
7480 Group and 7481 Group User's Manual
1-34
HARDWARE
1.10 Input/Output Pins
1.10.3 I/O Ports
(1) Writes to and Reads from I/O Port Pins
Pin used for input (Ports P0 to P5)
• A read: When reading from port register corresponding to each port, the input value (state of the
pin) is read; the contents of port latch is not read.
• A write: When writing to port register corresponding to each port, data is written only into the port
latch; the state of the pin is unaffected.
Pin used for output (Ports P0, P1, P4, and P5)
• A read: When reading from port register corresponding to each port, the written value into the port
latch is read; the state of the pin is not read. Therefore, even if the output voltage is
affected by the external load etc., the last output value can correctly be read.
• A write: When writing to port register corresponding to each port, data written into a bit of the port
register can be output to the external circuit through the ouput transistor.
Figure 1.10.10 shows a write and a read of an I/O port pin.
Pins used for input
Pins utput
• By reading from port register, input level of pin
can be read.
• Bom port register, port latch can be read.
to port register, output value can be set.
• By writing to port register, writing to port latch is
performed.
‘H’ level output
Port direction
register
Port direction
register
(Note)
(‘0’)
(‘1’)
Port register
(When Writing)
Port register
(When Writing)
‘L’ level output
Port register
(When Reading)
Port register
(When Reading)
Note: The P-channel transistor and the N-channel transistor are in a cut-off state.
Figure 1.10.10 Write and Read of I/O Port Pin
7480 Group and 7481 Group User's Manual
1-35
HARDWARE
1.10 Input/Output Pins
(2) Switching of Programmable I/O Port Pins
Any pin of the programmable I/O ports P0, P1, P4, and P5 can be switched from input to output or
from output to input with the corresponding bit of their port direction registers.
• The pin is set to the input mode when the corresponding bit is ‘0’.
• The pin is set to the output mode when the corresponding bit is ‘1’.
Notes 1: In the 7480 Group, port P4 contains pins P40 and P41 only, while in the 7481 Group, port
P4 contains pins P40–P43. In addition, the 7480 Group does not have port P5, while the
7481 Group has port P5, consisting of P50–P53.
2: After system is released from reset, all of the programmable I/O port pins are set to the
input mode. (The corresponding direction registers are cleared to all ‘0’.)
3: When any of port pins P42, P43, and P50–P53 is used as an input port pin, clear the
corresponding bit of the port P4 and P5 direction registers to ‘0’. In addition, set the
corresponding input control bit of the port P4P5 input control register to ‘1’.
The 7480 Group does not have port pins P42, P43, and P50–P53; therefore, set the port
P4P5 input control register to ‘0016’.
(3) Pull-up Control
When any pin of ports P0 and P1 is used as an input port pinup can be controlled with the
corresponding bit of the port P0 and P1 pull-up control re
• A port pin is not pulled high when the corresponding
• A port pin is pulled high when the corresponding b
Pull-up control is performed by the ON/OFF switll-up transistor. Pull-up control is valid only
when the pin is used for input and invalid wfor output or serial I/O.
Note: Port P0 controls the pull-up by thne time. Port P1, however, controls the pull-up of
the high- or low-order four bitime. Even if only port P10 pin is pulled high, for
example, port pins P11–P1pulled high simultaneously.
7480 Group and 7481 Group User's Manual
1-36
HARDWARE
1.10 Input/Output Pins
(4) Level Shift Ports
Every pin of ports P4 and P5 acts as an N-channel open-drain output and is provided with a built-
in clamping diode.
When voltage VI is applied to a pin through a resistor as shown in Figure 1.10.11, and the current
I flowing in a clamping diode is 1 mA or less, the condition VI > VCC can be maintained.
VI
I
Port P4
Port P5
7480 Group
7481 Group
Figure 1.10.11 Port P4 and P5 Circuit
Notes 1: In the 7480 Group, port P4 contains pind P41 only, while in the 7481 Group, port
P4 contains pins P40–P43. In additio80 Group does not have port P5, while the
7481 Group has port P5, consisti–P53.
2: Total Input Current
It is required to keep the curng to the clamping diodes of port P4 or P5 equal to
or less than 1.0 mA a pint which is too large for the microcomputer can handle
will raise the voltage oer source pin. To protect the device, use an appropriate
power circuit to stabpower source voltage within specifications.
3: Maximum Input V
If the input sige to port P4 or P5 exceeds VCC + 0.3 V, a delay time of 2 µs/V
or more is nimmediately after the input waveform exceeds the above voltage.
Delay timcalculated by the following expression in CR integrating circuits.
1
d
dv
t
≥ 2 × 10– 6 [s/V]
2
0.6 × VIN
1: Delay time t = C × R
2: VIN = maximum amplitude difference of input voltage
4: Clamping diodes used in the 7480 Group and 7481 Group differ from the normal switching
diodes. These clamping diodes are used only for the DC signal level shifts. Therefore,
sudden stress, such as a rush current must not be applied directly to the diodes.
(5) Ports with Built-in Schmidt Trigger Circuits
A Schmidt trigger circuit is built into every pin of ports P3, P4, and P5 of the 7481 Group.
When any of port pins P42, P43, and P50–P53 is used as an input port pin, clear the corresponding
bit of the port P4 and P5 direction registers to ‘0’. In addition, set the corresponding input control bit
of the port P4P5 input control register to ‘1’.
Note: The 7480 Group does not have pins P42, P43, and P50–P53; therefore, set the port P4P5 input
control register to ‘0016’.
7480 Group and 7481 Group User's Manual
1-37
HARDWARE
1.10 Input/Output Pins
1.10.4 Termination of Unused Pins
Table 1.10.1 lists the termination of unused pins.
Table 1.10.1 Termination of Unused Pins
Termination
Pull-up to VCC through Pull-down to VSS through Connect to Connect to
Port
Open
a resistor (Note 1)
a resistor (Note 1)
VCC
VSS
P0
O (Note 4)
×
×
O (Note 3)
P10–P13
P15, P17
P14, P16
P2 (Note 8)
P3
O (Note 2)
O (Note 4)
O (Note 6)
O (Note 6)
×
×
O (Note 3)
O (Note 6)
O (Note 6)
O (Note 5)
O (Note 2)
×
O (Note 6) O (Note 6)
O (Note 6) O (Note 6)
P4, P5
O (Note 7)
×
×
O (Note 3)
O (Note 5)
(Note 8)
AVSS (Note 9)
VREF
×
×
×
O
×
O
×
×
×
×
×
×
×
XOUT
O
Notes 1: Do not connect several pins of programmable I/O poer to VCC or VSS through a resistor.
2: Every pin that is allowed to be open when unusepecial circuit structure which prevents
currents from flowing into the circuit unless thread signal is performed internally, even
if an intermediate level input is applied to
3: When these pins are pulled high, set tsponding bits of port direction registers, port
registers and port P4P5 input control o that each pin is in the input mode or output is
HIGH.
4: When these pins are pulled lowcorresponding bits of port direction registers, pull-up
control registers, port registet each pin can be set to the input mode without pull-up
transistor or in the output i
5: Set these pins to the oe and keep them open.
However, these I/O pithe input mode until the pins are switched to the output mode by
software after the muter is released from reset. Therefore, the power source current may
increase depende input level of each pin.
Since their porn registers might be switched into the input mode by program runaway or
noise, periodicallet the port direction registers to the output mode by software.
6: A short wire can be used to directly connect any unused pin to the VCC or VSS pin without a
resistor, but a long wire must connect it through a resistor. Since the P33 pin of the built-in PROM
version has the alternative function of the VPP pin, connect the P33 pin to VCC or VSS with the
shortest wire through a resistor (about 5 kΩ), in series.
7: When these pins are pulled low, set the corresponding bits of port direction registers, port
registers and port P4P5 input control register so that each pin is in the input mode or output is
LOW.
8: The 7480 Group does not have port pins P24–P27, P42, P43, and P50–P53.
9: The AVSS pin is dedicated to the 44P6N-A package products in the 7481 Group.
7480 Group and 7481 Group User's Manual
1-38
HARDWARE
1.10 Input/Output Pins
1.10.5 Notes on Usage
Pay attention to the following notes when the I/O ports are used.
(1) Rewriting to Port Register of I/O Port
1
Rewriting to the port register of an I/O port with a bit manipulation instruction may affect the values
of the bits not specified.
1: ‘Bit manipulation instructions’: the CLB and SEB instructions
REASON: The bit manipulation instructions are read-modify-write instructions. These instructions
read and write data by the byte. Therefore when these instructions are executed for any
one bit of the port register of an I/O port, the following processing is performed to all of
the bits of the register:
• For bits that are set to the input mode, the states of the corresponding pins are read
into the CPU, and after the bit manipulation, the bits of the port register are rewritten.
• For bits that are set to the output mode, the values of the port latches are read into the
CPU, and after the bit manipulation, the bits of the pister are rewritten.
Pay attention also to the following:
• Even if a port pin set to the output mode is to the input mode, output data is
retained in the port register.
• When the state of a port pin and the cthe corresponding bit of the port register
are different, the content of the bit ort register set to the input mode may be
affected even if this bit is not spy a bit manipulation instruction.
(2) Pull-up Control of Ports P0 and P1
When any of pins P15–P17 is userial I/O pin, the pull-up control of the pin is invalid. (The
pin cannot be pulled high.)
For details, refer to FigurBlock Diagram of Port Pins P14–P17.
When any pin of porP1 is used as an output port pin, the pull-up control of the pin is
invalid. (The pin cpulled high.)
For details, refee 1.10.1 Block Diagrams of Port Pins P0i and P10–P13 and Figure1.10.2
Block Diagram rt Pins P14–P17.
Port P1 controls pull-up the high- or low-order four bits at one time. Even if only port P10 pin is
pulled high, for example, port pins P11–P13 are pulled high simultaneously.
7480 Group and 7481 Group User's Manual
1-39
HARDWARE
1.10 Input/Output Pins
(3) Transition to Standby State (Note)
At the transition to the standby state, do not leave the input levels of input port pins and I/O port pins
undefined (especially pins P14, P16, P3, P4, and P5). In an N-channel open-drain I/O pin, when the
corresponding bit of the port register is ‘1’, its transistor remains in an off state even if the pin is set
to output mode with the port direction register. As a result, the pin goes to a high impedance state,
causing the level of the pin to be undefined depending on the external circuit. In such a case, a
through current flows to the gate of the input stage, so that the power source current may increase.
Note: The standby state means the following:
The stop mode by an execution of the STP instruction
The wait mode by an execution of the WIT instruction.
Actual Example
Pull a pin high (connect to VCC) or low (connect to VSS) through a resistor.
Choose a resistor taking the following into consideration:
• External circuit condition
• Variation of output levels at normal operation
Also, take account of the variation of current when pull-up transiorts P0 and P1 are used.
(4) Usage of Pins P12, P13, P40, and P41 as Normal Outpu
Pins P12 and P13 have the alternative functions of the 8-output pins T0 and T1 respectively.
Pins P40 and P41 also have the alternative functionit timer I/O pins CNTR0 and CNTR1
respectively. When the operating mode bits of the nding timer are set to any mode related
to output (Note), these pins cannot operate as utput pins. Refer to Figure 1.10.1 Block
Diagrams of Port Pins P0i and P10–P13 an1.10.3 Block Diagrams of Port Pins P2i to
P5i.
Note: Modes related to output:
For 8-bit timers (timer 1 an):
• Programmable wavefration mode
For 16-bit timers (timeimer Y):
• Pulse output m
• Programmabrm generation mode
• Programmshot output mode
• PWM m
(5) Usage of Port Pins P42, P43, and P50–P53 as Input Ports
When any of port pins P42, P43, and P50–P53 of the 7481 Group are used as an input port pin, clear
the corresponding bit of the port P4 and P5 direction registers to ‘0’, and set the corresponding input
control bit of the port P4P5 input control register to ‘1’.
7480 Group and 7481 Group User's Manual
1-40
HARDWARE
1.11 Interrupts
1.11 Interrupts
The interrupt function is used to suspend the routine being executed by any interrupt source and to execute
another routine. An interrupt is used in the following cases:
• When processing of a higher priority than the routine being executed is requested.
• When processing is requested to be performed according to a special timing.
Table 1.11.1 lists the interrupt sources available in the 7480 Group and 7481 Group.
Table 1.11.1 Interrupt Sources
Priority
Vector Address
Interrupt Source
Reset (Note 1)
Comments
Non-maskable (Note 2)
High-order
Low-order
FFFE16
Order
FFFF16
FFFD16
1
2
FFFC16
INT0
External interrupt (Polarity programmable)
External interrupt (Polarity programmable)
External interrupt
INT1
FFFB16
FFFA16
3
Key-on Wakeup
CNTR0
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE5
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC1
FFE
F
6
416
External interr(Polarity programmable)
External inolarity programmable)
Internal
4
5
CNTR1
6
Timer X
7
Timer Y
Interupt
8
Timer 1
Inerrupt
9
Timer 2
interrupt
10
11
12
13
14
Serial I/O Receive
Serial I/O Transmit
Bus arbitration
A-D conversion complete
BRK instruction
nal interrupt
nternal interrupt
Internal interrupt
Internal interrupt
Non-maskable software interrupt
Notes 1: Reset is included in the above tell, because it performs the same operation as interrupts.
2: ‘Non-maskable interrupt’:
this is the interrupt not haorresponding interrupt request bit and interrupt enable bit. This
interrupt request is accgardless of the state of the interrupt disable flag.
7480 Group and 7481 Group User's Manual
1-41
HARDWARE
1.11 Interrupts
1.11.1 Block Diagram
Figure 1.11.1 shows the block diagram of the interrupt inputs and the key-on wakeup circuit.
P40/CNTR0
Port P4
0
data read circuit
‘0’
CNTR
CNTR
0
interrupt request signal
0
1
edge selection bit
edge selection bit
‘1’
P41/CNTR1
Port P4
CNTR
1
data read circuit
‘0’
CNTR
1
interrupt request signal
‘1’
‘1’
‘1’
P3
P3
0
1
/INT
0
1
Port P3
0 data read circuit
‘0’
INT
INT interrupt request signal
0
0
1
edge selection bit
edge selection bit
/INT
Port Pread circuit
‘0’
INT
‘0’
I
sour
bit at S
request signal
INT
1
‘1’
CPU stop state signal
Pull-up control register
Port direction register
P07
Pull-up control
register
Port direction
register
P0
P0
1
0
Port P0 data read circuit
Pull-up
regi
P
Figure 1.11.1 Block Diagram of Interrupt Inputs and Key-On Wakeup Circuit
7480 Group and 7481 Group User's Manual
1-42
HARDWARE
1.11 Interrupts
1.11.2 Registers Associated with Interrupt Control
Figure 1.11.2 shows the memory map of the registers associated with interrupt control.
Edge polarity selection register (EG)
00D416
00FC16
00FD16
00FE16
00FF16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Figure 1.11.2 Memory Map of Registers Associated with Interrul
7480 Group and 7481 Group User's Manual
1-43
HARDWARE
1.11 Interrupts
(1) Edge Polarity Selection Register
The edge polarity selection register consists of the bits that select the polarity of the valid edge of
the INT and CNTR pins, as well as the bit that selects the valid/invalid of the key-on wakeup.
Figure 1.11.3 shows the edge polarity selection register.
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0
Edge polarity selection register (EG) [Address 00D416]
b
Function
Name
R
O
W
O
At reset
0
0
INT0 edge
selection bit
0 : Falling edge
1 : Rising edge
1
2
0
O
O
O
O
INT1 edge
selection bit
0 : Falling edge
1 : Rising edge
0: In event count mode, rising edge counted.
: In pulse output mode, operation started
at HIGH level output.
CNTR0 edge
selection bit
:
In pulse period measurement mode, a perio
from falling edge until falling edge meas
: In pulse width measurement m
HIGH-level period measured
: In programmable one-sho
one-shot HIGH pulse
operation started at put.
: Interrupt request idetecting
falling edge.
1: In event couedge counted.
: In pulse oeration started
at LOW
3
0
CNTR1 edge
selection bit
O
O
:
In pulment mode, a period
frol rising edge measured.
: measurement mode,
eriod measured.
mmable one-shot output mode,
ot LOW pulse generated after
ation started at HIGH level output.
terrupt request is generated by detecting
rising edge.
Undefined
ted. Writing to this bit is disabled.
ndefined at reading.
Undefined
×
4
O
O
0
ource
ection bit at 1 : P00–P07 LOW level
TP or WIT (for key-on wake-up)
0 : P31/INT1
Undefined
Undefined
6
7
Undefined
Undefined
×
×
Not implemented. Writing to these bits are disabled.
These bits are undefined at reading.
Note: When setting bits 0 to 3, the interrupt request bit may be set to ‘1’.
After setting the following, enable the interrupt.
➀Disable interrupts
➁Set the edge polarity selection register
➂ Set the interrupt request bit to ‘0’
Figure 1.11.3 Edge Polarity Selection Register
7480 Group and 7481 Group User's Manual
1-44
HARDWARE
1.11 Interrupts
(2) Interrupt Request Register 1 and Interrupt Request Register 2
Interrupt request registers 1 and 2 consist of the bits that indicate whether or not there is an interrupt
request.
Figures 1.11.4 and 1.11.5 show the interrupt request registers 1 and 2.
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16
]
R
O
W
b
0
Name
Function
At reset
0
Timer X interrupt request bit 0 : No interrupt request
1 : Interrupt request
1
2
Timer Y interrupt request bit 0 : No interrupt request
1 : Interrupt request
0
0
O
O
Timer 1 interrupt request bit 0 : No interrupt request
1 : Interrupt request
3
Timer 2 interrupt request bit 0 : No interrupt request
1 : Interrupt request
O
4
5
Serial I/O receive
interrupt request bit
0 : No interrupt r
1 : Interrupt re
0
0
O
O
O
O
Serial I/O transmit
interrupt request bit
0 : No int
1 : Inte
6
7
Bus arbitration interrupt
request bit
0 : quest
quest
0
0
A-D conversion completierrupt request
interrupt request bit rrupt request
: The bit can be set to , but cannot be set to ‘1’.
Figure 1.11.4 Interrupt Request Regist
Interrupt request r
b7 b6 b5 b4 b
Interrupt request register 2 (IREQ2) [Address 00FD16
]
R
W
b
0
Name
Function
At reset
0
O
INT
INT
0
1
interrupt request bit
0 : No interrupt request
1 : Interrupt request
0
0
0
O
O
1
2
interrupt request bit
0 : No interrupt request
1 : Interrupt request
CNTR
CNTR
0
1
interrupt request bit 0 : No interrupt request
1 : Interrupt request
3
interrupt request bit 0 : No interrupt request
1 : Interrupt request
O
Undefined
Undefined
Undefined
Undefined
×
×
×
×
Undefined
Undefined
Undefined
Undefined
4
5
6
Not implemented.
Writing to these bits is disabled.
These bits are undefined at reading.
7
: The bit can be set to ‘0’ by software, but cannot be set to ‘1’.
Figure 1.11.5 Interrupt Request Register 2
7480 Group and 7481 Group User's Manual
1-45
HARDWARE
1.11 Interrupts
(3) Interrupt Control Register 1 and Interrupt Control Register 2
Interrupt control registers 1 and 2 consist of the bits that control the acceptance of interrupts.
Figures 1.11.6 and 1.11.7 show the interrupt control registers 1 and 2.
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 00FE16
]
R
O
W
O
b
0
Name
Function
At reset
0
Timer X interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
1
2
Timer Y interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
0
0
O
O
O
O
Timer 1 interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
3
Timer 2 interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
O
O
O
O
4
5
Serial I/O receive
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabl
0
0
O
O
Serial I/O transmit
interrupt enable bit
0 : Interrupt d
1 : Interrup
6
7
Bus arbitration interrupt
enable bit
0 : Int
1 : ed
0
0
O
O
O
O
A-D conversion completion isabled
interrupt enable bit t enabled
Figure 1.11.6 Interrupt Control Register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b
t control register 2 (ICON2) [Address 00FF16
]
R
O
W
O
At reset
0
b
0
Name
Function
INT
0
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
1
2
3
0 : Interrupt disabled
1 : Interrupt enabled
O
O
INT
1
interrupt enable bit
CNTR
0
1
interrupt enable bit 0 : Interrupt disabled
O
O
O
O
1 : Interrupt enabled
CNTR
interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
Undefined
Undefined
Undefined
Undefined
×
×
×
×
Undefined
Undefined
Undefined
Undefined
4
5
Not implemented.
Writing to these bits are disabled.
These bits are undefined at reading.
6
7
Figure 1.11.7 Interrupt Control Register 2
7480 Group and 7481 Group User's Manual
1-46
HARDWARE
1.11 Interrupts
1.11.3 Interrupt Sources
In the 7480 Group and 7481 Group, the interrupt requests can be generated by 14 sources (5 external,
8 internal, and 1 software).
The interrupts are vectored interrupts whose priority levels are fixed, and each interrupt has its own priority
level. When two or more interrupt requests are generated at the same sampling time, which is a timing to
test the generation of interrupt requests, the interrupt with a higher priority is acceptable.
For the priority levels of interrupts, refer to Table 1.11.1 Interrupt Sources.
Each interrupt source is described below.
(1) INT0 and INT1 Interrupts
When a rising edge or a falling edge of the input signal to the INT0 or INT1 pin is detected, an
interrupt request is generated.
The edge polarity to be detected can be selected by the INT0 edge selection bit or the INT1 edge
selection bit of the edge polarity selection register.
The request bit, the enable bit, and the interrupt vector of the INT1 nterrupt have the alternative
functions of those of the key-on wakeup interrupt respectively. When NT1 interrupt is used, clear
the INT1 source selection bit at the STP/WIT of the edge polarion register to ‘0’.
• State after system is released from reset
After system is released from reset, the INT0 edge set, INT1 edge selection bit and the
INT1 source selection bit at the STP/WIT of the edy selection register are all cleared to
‘0’.
In such conditions, though an interrupt request ted by detecting a falling edge of the INT0
or INT1 pin, the interrupt request cannot be because the corresponding interrupt enable
bit is ‘0’ and the interrupt disable flag is
Notes 1: The INT0 and INT1 pins hlternative functions of input port pins P30 and P31,
respectively. When these used as input port pins, valid edges can still be detected
because the 7480 Gro481 Group does not have the function to switch the INT pins
to input port pins. e, when these pins are used as input port pins, clear all the
corresponding innable bits to ‘0’ (disabled).
2: Keep the triginput to the INT pins 250 ns or more.
(2) Key-On Wakeup
When the INT1 sourelection bit at the STP/WIT of the edge polarity selection register is ‘1’ and
the LOW level is applied to any pin of port P0 which is used as input in the stop/wait mode at the
execution of STP/WIT, a key-on wakeup interrupt request is generated. In other states than the stop/
wait mode, the key-on wakeup interrupt is invalid.
The request bit, the enable bit, and the interrupt vector of the key-on wakeup interrupt have the
alternative functions of those of the INT1 interrupt respectively. When the key-on wakeup interrupt
is used, set the INT1 source selection bit at the STP/WIT of the edge polarity selection register to
‘1’.
Note: When the key-on wakeup interrupt is used, execute the STP/WIT instruction after all inputs to
port P0 are held HIGH. If the LOW level is applied to any input pin of port P0, an execution
of the STP/WIT instruction generates an interrupt request instantly.
7480 Group and 7481 Group User's Manual
1-47
HARDWARE
1.11 Interrupts
(3) CNTR0 and CNTR1 Interrupts
When a rising edge or a falling edge of the input signal to the CNTR0 or the CNTR1 pin is detected,
an interrupt request is generated. The edge polarity to be detected can be selected by the CNTR0
edge selection bit or the CNTR1 edge selection bit of the edge polarity selection register.
• State after system is released from reset
After system is released from reset, the port pins with the alternative functions of CNTR pins are
placed in the input mode, and their edge selection bits are held all ‘0’ also. In such conditions,
though an interrupt request is generated by detecting a falling edge of the CNTR0 or CNTR1 pin,
the interrupt request cannot be accepted because the corresponding interrupt enable bit is ‘0’ and
the interrupt disable flag is ‘1’.
Note: The CNTR0 and CNTR1 pins have the alternative functions of I/O port pins P40 and P41,
respectively. When these pins are used as input port pins, valid edges can still be detected
because the 7480 Group and 7481 Group does not have the function to switch the CNTR pins
to input port pins. Therefore, when these pins are used as nput port pins, clear all the
corresponding interrupt enable bits to ‘0’ (disabled).
(4) Timer X, Timer Y, Timer 1, and Timer 2 Interrupts
At an underflow in each timer, the corresponding interrupt is generated.
For timer X and timer Y, refer to Section 1.12 Timer X er Y, and for timer 1 and timer 2,
refer to Section 1.13 Timer 1 and Timer 2.
(5) Serial I/O Receive Interrupt, Serial I/O Transupt, and Bus Arbitration Interrupt
• Serial I/O receive interrupt
During serial I/O reception, a serial I/O rterrupt request is generated when the received
data stored completely in the receive ster is transferred to the receive buffer register.
• Serial I/O transmit interrupt
During serial I/O transmission, /O transmit interrupt request is generated when the transmit
buffer register is emptied osmit shift operation is complete.
• Bus arbitration interru
In the bus collision n enable state during the serial I/O communication, the mismatch of
levels between er pin TxD and receiver pin RxD generates a bus arbitration interrupt
request.
The bus collision detection can be enabled by setting the bus collision detection enable bit of the
bus collision detection control register.
For serial I/O, refer to Section 1.14 Serial I/O.
(6) A-D Conversion Complete Interrupt
When A-D conversion is completed, an A-D conversion complete interrupt request is generated.
For A-D conversion, refer to Section 1.15 A-D Converter.
(7) BRK Instruction Interrupt
The BRK instruction interrupt is a non-maskable software interrupt. Program branches to the jump
address stored in the vector address when the BRK instruction is executed.
For the BRK instruction, refer to the section of the BRK instruction in SERIES 740 <SOFTWARE>
USER’S MANUAL.
7480 Group and 7481 Group User's Manual
1-48
HARDWARE
1.11 Interrupts
1.11.4 Interrupt Sequence
Interrupt sequence is described below.
Generation of Interrupt Requests
When an interrupt request other than the BRK instruction interrupt is generated, the interrupt request bit
of the corresponding interrupt request register is set to ‘1’. At this time, the interrupt request is accepted
when both the following conditions are satisfied:
• The interrupt enable bit of the corresponding interrupt control register is ‘1’.
• The interrupt disable flag of the processor status register is ‘0’.
When the BRK instruction interrupt request is generated, the break flag of the processor status register
is set to ‘1’, causing the interrupt request to be accepted unconditionally.
For interrupt sources, refer to Section 1.11.3 Interrupt Sources. Also for interrupt control, refer to
Section 1.11.5 Interrupt Control.
Acceptance of Interrupt Request
When an interrupt request is accepted, the following operations are d:
[1] Upon the completion of the instruction being executed, the g is temporarily suspended.
[2] The contents of the program counter and the processoregister are pushed onto the stack in
the following order:
➀ High-order 8 bits of the program counter
➁ Low-order 8 bits of the program counter
➂ Processor status register
[3] The jump address (the start address rrupt service routine) stored in the vector address of
the accepted interrupt is set in the ounter, and the interrupt service routine is executed. At
this time, the interrupt disable flag i’, and multiple interrupts are disabled. Also, the corresponding
interrupt request bit is cleared r any interrupt other than the BRK instruction interrupt.
[4] When the RTI instruction, , the last instruction of the interrupt service routine, is executed, the
contents of the prograr and the processor status register pushed onto the stack are pulled
to the correspondinr in the following order:
➀ Processor status ster
➁ Low-order 8 bits of program counter
➂ High-order 8 bits of program counter
[5] The program temporarily suspended by the acceptance of the interrupt request is resumed at the
address indicated by the program counter.
Note: When the BRK instruction is executed, 2 is added to the contents of program counter, and then
the contents of the program counter are pushed onto the stack. As a result, upon return from the
BRK instruction interrupt service routine, the one byte subsequent to the BRK instruction is not
executed. Therefore, at programming, it is necessary to insert the NOP instruction immediately
after the BRK instruction.
7480 Group and 7481 Group User's Manual
1-49
HARDWARE
1.11 Interrupts
Figure 1.11.8 shows an operation when an interrupt request is accepted.
Routine being executed
: Operation performed by software
: Operation automatically performed by hardware
•
• • • • •
Processing at accepting interrupt
Interrupt
request is
generated
1
M(S)←(PCH)
(S)←(S)–1
M(S)←(PCL)
(S)←(S)–1
M(S)←(PS)
Contents of program counter
are pushed onto stack
3
•
• • • • •
Contents of processor status
register are pushed ono stack
(S)←(S)–1
2
Interrupt disab
Fetch the juored
into vect
Interrupt service
routine
RTI instruction execu
(S)←(
(
1
)←M(S)
(S)←(S)+1
(PCH)←M(S)
ontents of processor status
register are pulled from stack
Contents of program counter
are pulled from stack
2
3
1
Immediately after interrupt
request is accepted
Immediately before interrupt
service routine is executed
Immediately after system returns
from interrupt service routine
S
S
XXS–3
S
XXS
XXS
PCL
PCH
PCL
PCH
PCL
PCH
XXPCL
XXPCH
XXPCL
XXPCH
Jump address
(from vector address)
b7
b0
b7
b0
b7
b0
PS
0
PS
PS
0
Note
Note
Note
1
Interrupt disable flag
Break flag
Interrupt disable flag
Break flag
Interrupt disable flag
Break flag
Stack area
Stack area
Stack area
(S)=XXS–3
XXS
0
Note
(PS)
(PCL)
XXPCL
XXPCH
(S)=XXS
(PCH)
(S)=XXS
Note: In the case of the BRK instruction interrupt, b4 of PS is set to ‘1’.
Figure 1.11.8 Operation When Interrupt Request is Accepted
7480 Group and 7481 Group User's Manual
1-50
HARDWARE
1.11 Interrupts
Processing Before Interrupt Service Routine
When an interrupt request is accepted, the interrupt service routine is started after the following are
performed.
➀ the instruction being executed at the generation of the interrupt request is completed
➁ the pipeline postprocessing
➂ the pushing onto the stack, and vector fetch
Figure 1.11.9 shows the processing time from the interrupt generation until the execution of an interrupt
service routine, and Figure 1.11.10 shows a timing at interrupt acceptance.
Interrupt service routine starts
Interrupt request is generated
Main routine
Waiting time for
pipeline
postprocessing
Push onto stack
Vector fetch
Interrupt service
roe
0 to 16 cycles (Note)
2 cycles
5 cycle
7 to 23 cycles
(At internal system clock φ = 4 MHz, 1.75 µs to
Note: At the DIV instruction executed.
Figure 1.11.9 Processing Time from Interrupt Geuntil Execution of Interrupt Service Routine
Waiting time for
onto stack
pipeline
postprocessing
Vector fetch
Interrupt service routine starts
φ
SYNC
R/W
Address bus
Data bus
PC
S, SPS S-1, SPS S-2, SPS
B
L
B
H
AL, AH
Not used
PS
A
L
AH
PCH
PCL
SYNC:
CPU operation code fetch cycle
(This is an internal signal which cannot be examined from the external.)
Vector address of each interrupt
Jump address of each interrupt
B
A
L
L
, B
H
:
:
, AH
SPS:
‘0016’ or ‘0116
’
(when the stack page selection bit is ‘0’, SPS is ‘0016’, and when the bit is ‘1’, SPS is ‘0116’)
Figure 1.11.10 Timing at Interrupt Acceptance
7480 Group and 7481 Group User's Manual
1-51
HARDWARE
1.11 Interrupts
Return from Stop/Wait Mode
When an interrupt request is accepted in the stop/wait mode, the CPU terminates these modes and
returns to the normal mode.
Table 1.11.2 lists the interrupt sources available for CPU’s return from the stop/wait mode.
Table 1.11.2 Interrupt Sources Available for CPU’s Return from Stop/Wait Mode (O:Available,
×:Not available)
Interrupt Source
Reset (Note 1)
Return from Stop Mode
Return from Wait Mode
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
×
INT0
O
INT1
O
Key-on Wakeup
CNTR0
O
O
CNTR1
O
Timer X
O (Note 2)
Timer Y
O (Note 2)
Timer 1
×
Timer 2
×
Serial I/O Receive
Serial I/O Transmit
Bus Arbitration
A-D Conversion Complete
BRK Instruction
O (Note 3)
O (Note 3)
O (Note 3)
×
×
Notes 1: Reset is included in the above table, as wse it performs the same operation as interrupts.
2: Available in the event count mode on
3: Available only when the external clocr the clock divided by 16) is used as the synchronous
clock.
For details, refer to Section 1.19 Pving Function.
7480 Group and 7481 Group User's Manual
1-52
HARDWARE
1.11 Interrupts
1.11.5 Interrupt Control
Figure 1.11.11 shows an interrupt control diagram.
Interrupt request bit
Interrupt enable bit
Interrupt acceptance
Interrupt disable flag
BRK instruction
Reset
Figure 1.11.11 Interrupt Control Diagram
Only when all of the following conditions are satisfied, interrupts other than the BRK instruction interrupt
are accepted:
• Corresponding interrupt request bit is ‘1’ (interrupt requested).
• Corresponding interrupt enable bit is ‘1’ (interrupt enabled).
• Interrupt disable flag is ‘0’ (interrupt enabled).
The priority level of each interrupt is specified by hardware. Howeessing of various priorities can
be performed under software control by using the above bits
For the interrupt priority levels, refer to Table 1.11.1 Interrces.
Interrupt Request Bits
The interrupt request bits indicate whether or not thnterrupt requests. When an interrupt request
is generated, an interrupt request bit is set to ‘1orms the external that the interrupt request is
generated. After the interrupt is accepted, the request bit is automatically cleared to ‘0’.
The interrupt request bits can be cleared to oftware, but they cannot be set to ‘1’.
Interrupt Enable Bits
The interrupt enable bits control the nce of interrupt requests as follows:
• When an interrupt enable bit is acceptance of the corresponding interrupt request is disabled.
• When an interrupt enable bie acceptance of the corresponding interrupt request is enabled.
Interrupt Disable Flag
This flag is located in thcessor status register. The flag controls the acceptance of the interrupt
requests other than the BRK instruction interrupt as follows:
• When the interrupt disable flag is ‘0’, the acceptance of interrupt request is enabled.
• When the interrupt disable flag is ‘1’, the acceptance of interrupt request is disabled.
When the program branches to the interrupt service routine, this flag is automatically set to ‘1’ and disables
multiple interrupts. When multiple interrupts are used, clear this flag to ‘0’ at the start of the interrupt
service routine.
7480 Group and 7481 Group User's Manual
1-53
HARDWARE
1.11 Interrupts
1.11.6 Setting of Interrupts
Figures 1.11.12 and 1.11.13 show the setting of interrupts.
Procedure 1 Setting interrupt disable flag to ‘1’ to disable the acceptance of other interrupts during setting.
b7
b0
Processor status register (PS)
Interrupt disabled
1
Procedure 2 Setting using interrupt enable bit to ‘0’ (disabled)
b7
b0
Interrupt control register 1 (ICON1) [Address 00FE16]
When timer X interrupt is set, timer X interrupt is disabled.
0 0 0 0 0 0 0 0
When timer Y interrupt is set, timer Y interrupt is disabled.
When timer 1 interrupt is set, timer 1 interrupt is disabled.
When timer 2 interrupt is set, timer 2 interrupt is disabled.
When serial I/O receive interrupt is set, serial I/O receive inter.
When serial I/O transmit interrupt is set, serial I/O transmit abled.
When bus arbitration interrupt is set, bus arbitration inted.
When A-D conversion completion interrupt is set, Acompletion interrupt is disabled.
b7
b0
0 0 0 0
Interrupt control register 2 (ICON2) [Add
When INT0 interrupt is set, INT0 interrup
When INT1 interrupt is set, INT1 inter.
When CNTR0 interrupt is set, CNdisabled.
When CNTR1 interrupt is set, pt is disabled.
Procedure 3 Setting each interrupt
• When INT interrupt, CNTR interrupt n wakeup interrupt are used
1. Selection of edge polarity select
b7
b0
Edlection register (EG) [Address 00D416]
arity selection
polarity selection
0: Falling edge
edge polarity selection
1: Rising edge
TR1 edge polarity selection
INT1 source at STP and WIT selection
0 : P31/INT1
1 : P00–P07 LOW level (Key-on wakeup)
2. When CNTR interrupt and key-on wakeup interrupt are used, using port is set to input mode.
3. When key-on wakeup interrupt is used, using port pins are pulled high.
• When timer interrupt is used
1. Stop of timer count
2. Setting of each mode
3. Setting of timer (except pulse period measurement mode and pulse width measurement mode)
• When serial I/O receive interrupt, serial I/O transmit interrupt or bus arbitration interrupt are used
1. Setting of registers related to serial I/O
2. Setting of baud rate generator (only when internal clock is selected as synchronous clock)
Note: For details, refer to setting of each function.
Figure 1.11.12 Setting of Interrupts (1)
7480 Group and 7481 Group User's Manual
1-54
HARDWARE
1.11 Interrupts
Procedure 4 Setting using interrupt request bit to ‘0’ (no interrupt request)
b7
b0
Interrupt request register 1 (IREQ1) [Address 00FC16
]
0
0
0
0
0
0
0
0
When timer X interrupt is set, there is no timer X interrupt request.
When timer Y interrupt is set, there is no timer Y interrupt request.
When timer 1 interrupt is set, there is no timer 1 interrupt request.
When timer 2 interrupt is set, there is no timer 2 interrupt request.
When serial I/O receive interrupt is set, there is no serial I/O receive interrupt request.
When serial I/O transmit interrupt is set, there is no serial I/O transmit interrupt request.
When bus arbitration interrupt is set, there is no bus arbitration interrupt request.
When A-D conversion completion interrupt is set, there is no A-D conversion completion interrupt request.
b7
b0
Interrupt request register 2 (IREQ2) [Address 00FD16
]
0
0
0
0
When INT
0
1
interrupt is set, there is no INT
interrupt is set, there is no INT
0
1
interrupt request.
interrupt request.
When INT
When CNTR
0
interrupt is set, there is no CNTR
0
interrupt request.
interrupt request.
When CNTR
1
interrupt is set, there is no CNTR
1
Procedure 5 Using interrupt enable bit to ‘1’ (enabled)
b7
b0
Interrupt control register 1 (ICON1) [Address 00
When timer X interrupt is set, timer X interrupt is
1
1
1
1
1
1
1 1
When timer Y interrupt is set, timer Y interrup
When timer 1 interrupt is set, timer 1 inter.
When timer 2 interrupt is set, timer 2 iled.
When serial I/O receive interrupt ireceive interrupt is enabled.
When serial I/O transmit interrl I/O transmit interrupt is enabled.
When bus arbitration interrrbitration interrupt is enabled.
When A-D conversion rrupt is set, A-D conversion completion interrupt is enabled.
b7
b0
Interrupt contrICON2) [Address 00FF16
]
1
1 1 1
When INT
0
INT
0
1
interrupt is enabled.
interrupt is enabled.
When IN
set, INT
Whe
upt is set, CNTR
0
interrupt is enabled.
interrupt is enabled.
W
terrupt is set, CNTR
1
Procedure 6 Setting b2 when the interrupt disable flag is set to ‘1’ in procedure 1.
b7
rocessor status register (PS)
Interrupt enabled
0
Procedure 7 Operate the function associated with each interrupt
• When key-on wakeup interrupt is used:
System is set to enter the stop mode/wait mode with the STP/WIT instruction.
• When timer interrupt is used:
Timer count start
• When serial I/O receive interrupt, serial I/O transmit interrupt and bus arbitration interrupt are used:
Data is written to the transmit buffer register and transmit/receive start.
• When A-D conversion completion interrupt is used:
Setting A-D control register (A-D conversion start)
Note: For details, refer to setting of each function.
Figure 1.11.13 Setting of Interrupts (2)
7480 Group and 7481 Group User's Manual
1-55
HARDWARE
1.11 Interrupts
1.11.7 Notes on Usage
Pay attention to the following notes when an interrupt is used.
(1) For All Interrupts
Before the execution of an interrupt, set the corresponding interrupt request bit and interrupt enable
bit in the following order:
➀ Clear the interrupt request bit to ‘0’ (no interrupt request).
➁ Set the corresponding interrupt enable bit to ‘1’ (interrupt enabled).
The interrupt request bits can be changed by software, but retain the values immediately after a
rewrite instruction is executed. Therefore, the following operations must be performed after one or
more instructions at the completion of a rewrite instruction:
• Execute the BBC or BBS instruction after an interrupt request bit is changed.
• Set an interrupt enable bit to ‘1’ after an interrupt request bit is changed.
(2) For the INT and CNTR Interrupts
When edge selection bits of the edge polarity selection register arinterrupt request bits may
become ‘1’. Therefore, set edge selection bits in the following :
➀ Clear interrupt enable bit to ‘0’ (interrupt disabled).
➁ Set edge selection bit.
➂ Clear interrupt request bit to ‘0’ (no interrupt request
➃ Execute one or more instructions (NOP etc.).
➄ Set interrupt enable bit to ‘1’ (interrupt enabled
The INT0, INT1, CNTR0, and CNTR1 pins haernative functions of input port pins P30, P31,
I/O port pins P40, and P41, respectively. se pins are used as input port pins, valid edges
can still be detected because the 7480 d 7481 Group does not have the function to switch
the INT and CNTR pins to input port erefore, when these pins are used as input port pins,
clear all the corresponding interrubits of the INT and CNTR interrupts to ‘0’ (disabled).
Keep the trigger width input T pins 250 ns or more.
(3) For the Key-On Wakeupt
When the key-on warrupt is used, execute the STP/WIT instruction after all inputs to port
P0 are held HIGH
In states other than the stop/wait mode, the key-on wakeup interrupt is invalid.
(4) For the BRK instruction interrupt
When the BRK instruction is executed, 2 is added to the contents of program counter, and then the
contents of the program counter are pushed onto the stack. As a result, upon return from the BRK
instruction interrupt service routine, the one byte subsequent to the BRK instruction is not executed.
Therefore, at programming, it is necessary to insert the NOP instruction immediately after the BRK
instruction.
When there are two or more interrupt sources of which interrupt request bits and interrupt enable bits
are ‘1’, but the interrupt disable flag is ‘1’ (that is, in the interrupt disabled state), the execution of
the BRK instruction starts execution of the interrupt service routine at the vector address with the
highest priority level in these sources.
7480 Group and 7481 Group User's Manual
1-56
HARDWARE
1.12 Timer X and Timer Y
1.12 Timer X and Timer Y
The 7480 Group and 7481 Group have two 16-bit timers with 16-bit latches.
• Timer X
• Timer Y
Timer X or timer Y can select the following operation modes by the timer X or Y operation mode bits and
the timer X or Y count source selection bits of the timer X mode register (address 00F616) or the timer Y
mode register (address 00F716):
• Timer mode
• Event count mode
• Pulse output mode
• Pulse period measurement mode
• Pulse width measurement mode
• Programmable waveform generation mode
• Programmable one-shot output mode
• PWM mode
For details, refer to the section of each mode.
1.12.1 Block Diagram
Figure 1.12.1 shows the block diagram of timer X and timer
7480 Group and 7481 Group User's Manual
1-57
HARDWARE
1.12 Timer X and Timer Y
Programmable
one-shot
output mode
INT
0
‘1’
CNTR
0
Data bus
edge selection bit
‘1’
‘0’
edge selection bit
Programmable one-shot
output circuit
P30/INT0
‘0’
PWM mode
PWM generation circuit
Programmable
one-shot
INT
0
interrupt request
output mode
PWM mode
Programmable waveform
generation mode
Output level latch
D
T
Q
Pulse output mode
CNTR
0
Pulse output mode
‘001’
‘100’
‘0’
S
Q
edge selection bit
‘101’
‘110’
T
Q
‘1’
Timer X
operating mode bits
Port P4
0
latch
Timer X (low-order) latch Timer X (high-order) latch
Timer X (low-order) Timer X (high-order)
Port P4
direction register
0
Timer X
interrupt request
Pulse width measurement mode
Pulse period measurement mode
CNTR
0
Edge dete
edge selection bit
‘1’
CNTR
0
interrupt request
Timer X cou
selec
P40/CNTR0
f(XIN)/2
f(XIN)/8
f(XIN)/16
‘0’
Programmable waveform generation mode
Timer X trigger selection bit
Timer X stop control bit
‘1’
Programmable
one-shot
D
T
Q
INT
1
output mode
edge selection bit
CNTR
1
‘1’
edge selection bit
Progrhot
t
P31/INT1
‘0’
PWM mode
‘0’
Programmable
one-shot
output mode
PWM mode
ation circuit
INT
1
Programmable waveform
generation mode
interrupt request
Output level latch
T
Q
Pulse output mode
CNTR
edge selection bit
1
‘001’
‘100’
‘101’
Pulse output mode
‘0’
S
Q
T
Q
‘1’
‘110’
Timer Y
operating mode bits
Port P4
latch
1
Timer Y (low-order) latch Timer Y (high-order) latch
Timer Y (low-order) Timer Y (high-order)
Port P4
direction register
1
Timer Y
interrupt request
Pulse width measurement mode
Pulse period measurement mode
CNTR
1
Edge detection circuit
edge selection bit
‘1’
CNTR
1
Timer Y count source
selection bits
interrupt request
P41/CNTR1
f(XIN)/2
f(XIN)/8
‘0’
f(XIN)/16
Programmable waveform generation mode
Timer Y trigger selection bit
‘0’
‘1’
Timer Y stop control bit
D
T
Q
Figure 1.12.1 Block Diagram of Timer X and Timer Y
7480 Group and 7481 Group User's Manual
1-58
HARDWARE
1.12 Timer X and Timer Y
1.12.2 Registers Associated with Timer X and Timer Y
Figure 1.12.2 shows the memory map of the registers associated with timer X and timer Y.
00F016
00F116
00F216
00F316
Timer X low-order (TXL)
Timer X high-order (TXH)
Timer Y low-order (TYL)
Timer Y high-order (TYH)
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer XY control register (TXYCON)
00F616
00F716
00F816
Figure 1.12.2 Memory Map of Registers Associated with Timd Timer Y
7480 Group and 7481 Group User's Manual
1-59
HARDWARE
1.12 Timer X and Timer Y
(1) Timer X and Timer Y
These are the 16-bit registers that count the count sources.
• When the timer X or Y write control bit of the timer X or Y mode register is;
‘0’: data is written to the timer and the timer latch (Note), and
‘1’: data is written to the timer latch only.
• In the pulse width measurement mode or the pulse period measurement mode, a read from the
timer receives the contents of the timer latch.
In the other modes, it receives the contents of the timer.
Note: The timer latches are the registers that hold the initial values automatically reloaded to the
timers when they underflow, and they hold the measured values of pulse periods or widths.
The timer latches cannot directly be read.
Figures 1.12.3 and 1.12.4 show the timer X and timer Y.
Timer X (Timer X latch)
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (high-order) (TXH) [Address 00F116]
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (low-odress 00F016]
n
b
0
At reset
R
O
W
r count value of
indicated.
1
1
O
O
1
1
1
O
O
O
Note 1
5
6
7
1
1
1
O
O
Function
At reset
b
R
W
1
1
O
O
O
0
1
2
3
The high-order count value of
timer X is indicated.
1
1
1
O
O
Note 1
4
5
O
O
O
1
1
1
6
7
Notes 1: Do not write to these bits in pulse period measurement mode or pulse width measurement mode.
2: When b3 of timer X mode register is ‘0’, writing to latch and timer is simultaneously
performed. When b3 is ‘1’, writing to only latch is performed.
3: When reading/writing from/to timer X, read/write from/to both high-order and low-order
bytes. At reading, read the high-order byte and the low-order byte in this order.
At writing, write the low-order byte and the high-order byte in this order.
Figure 1.12.3 Timer X
7480 Group and 7481 Group User's Manual
1-60
HARDWARE
1.12 Timer X and Timer Y
Timer Y (Timer Y latch)
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y (high-order) (TYH) [Address 00F316
b7 b6 b5 b4 b3 b2 b1 b0
]
Timer Y (low-order) (TYL) [Address 00F216
]
Function
At reset
b
R
O
W
0
1
2
The low-order count value of
timer Y is indicated.
1
1
O
O
O
1
1
1
3
4
5
Note 1
O
O
1
1
1
6
7
O
O
Function
b
R
O
W
0
1
2
The high-order count
timer Y is indicated
1
O
O
1
1
1
3
4
5
O
O
Note 1
1
1
1
O
O
O
6
Notes 1: Do not write to these bits in pulse pment mode or pulse width measurement mode.
2: When b3 of timer Y mode registto latch and timer is simultaneously
performed. When b3 is ‘1’, wrih is performed.
3: When reading/writing from//write from/to both high-order and low-order bytes.
At reading, read the highthe low-order byte in this order.
At writing, write the lod the high-order byte in this order.
Figure 1.12.4 Timer Y
7480 Group and 7481 Group User's Manual
1-61
HARDWARE
1.12 Timer X and Timer Y
(2) Timer X Mode Register, Timer Y Mode Register, and Timer XY Control Register
These registers consist of the bits controlling the operations of timer X and timer Y.
Figures 1.12.5, 1.12.6, and 1.12.7 show the timer X mode register, timer Y mode register, and timer
XY control register respectively.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register (TXM) [Address 00F616
]
b
0
Name
Function
At reset
0
R
O
W
O
b2 b1 b0
Timer X operating mode bits
0 0 0 : Timer • event count mode
0 0 1 : Pulse output mode
0 1 0 : Pulse period measurement mode
0 1 1 : Pulse width measurement mode
1 0 0 : Programmable waveform
generation mode
1 0 1 : Programmable one-shot output
mode
1 1 0 : PWM mode
1
0
O
O
O
O
2
3
0
1 1 1 : Not available
0 : Writing to both latch
1 : Writing to latch on
O
O
O
O
O
O
Timer X write control bit
Output level latch
0 : LOW output f
1 : HIGH outp
pin
4
5
0
0
Timer X trigger selection bit
0 : Timer X mmable
wavmode
1 : T(input signal of INT
0
start in programmable
neration mode
(XIN)/2
: f(XIN)/8
1 0 : f(XIN)/16
6
7
Timer X count source
selection bits
0
0
O
O
O
O
1 1 : Input from CNTR0 pin
Figure 1.12.5 Timer X Mode R
7480 Group and 7481 Group User's Manual
1-62
HARDWARE
1.12 Timer X and Timer Y
Timer Y mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y mode register (TYM) [Address 00F716
]
Function
b
0
Name
At reset
0
R
O
W
O
b2 b1 b0
0 0 0 : Timer • event count mode
0 0 1 : Pulse output mode
0 1 0 : Pulse period measurement mode
0 1 1 : Pulse width measurement mode
1 0 0 : Programmable waveform
generation mode
1 0 1 : Programmable one-shot
output mode
1 1 0 : PWM mode
Timer Y operating mode bits
1
0
O
O
O
O
2
3
0
0
1 1 1 : Not available
Timer Y write control bit 0 : Writing to both latch and timer
1 : Writing to latch only
O
O
O
O
O
O
0 : LOW output from CNTR
1 : HIGH output from CNTR
1
pin
pi
4
5
Output level latch
0
0
1
Timer Y trigger selection bit 0 : Timer Y free run in program
waveform generation mo
1 : Trigger occurrence (in
pin) and timer Y stle
waveform gene
b7 b6
6
7
Timer Y count source
0
0
O
O
O
O
0 0 : f(X
selection bits
0 1 :
1 0
CNTR1 pin
Figure 1.12.6 Timer Y Mode Register
Timer XY control register
b7 b6 b5 b4 b3 b2 b1 b
Y control register (TXYCON) [Address 00F816]
0 0 0 0 0 0
R
W
b
At reset
1
Name
Function
O
O
0
Timer X stop control bit
0 : Count operation
1 : Count stop
1
Timer Y stop control bit
0 : Count operation
1 : Count stop
1
O
O
×
×
×
×
×
×
Not implemented.
Writing to these bits is disabled.
These bits are ‘0’ at reading.
0
0
2
3
0
0
0
4
5
6
0
0
0
0
0
7
0
0
Figure 1.12.7 Timer XY Control Register
7480 Group and 7481 Group User's Manual
1-63
HARDWARE
1.12 Timer X and Timer Y
1.12.3 Basic Operations of Timer X and Timer Y
Basic operations of timer X and timer Y are described below.
For details, refer to (1) Operations of each mode.
Count Sources
Timer X or timer Y can select the following count sources with the timer X or Y count source selection bits
of the timer X or Y mode register:
• f(XIN)/2
• f(XIN)/8
• f(XIN)/16
• CNTR0 or CNTR1 pin input (in event count mode only).
Note: In the event count mode, the inverted signal of input to a CNTR pin is used as the count source when
a CNTR edge selection bit of the edge polarity selection register is ‘1’.
Writes to and Reads from Timers
Write to and read from each timer two bytes together in the following orde:
• Write: ➀ low-order byte ➁ high-order byte
• Read: ➀ high-order byte ➁ low-order byte
Note: When a read from and a write into the same timer are exering an interrupt service routine
etc., the normal operation cannot be performed.
Writes to timers
When ‘TL (000016 through FFFF16)’ is written er, the following different operations are
performed depending on the state of the timY write control bit of the timer X or Y mode
register:
• In the ‘0’ state of the timer X or Y trol bit, the ‘TL’ is set in both the timer latch and the
timer.
Notes 1: A write to an operatinauses the contents of the timer to be affected, so that the
time from the last uuntil the next underflow is undefined.
2: A write to the lobyte of an operating timer allows the timer to continue counting
down until the te to the high-order byte.
• In the ‘1’ state oer X or Y write control bit, the ‘TL’ is set in the timer latch only.
Notes 1: A write to opped timer causes the contents of the timer not to be affected and allows
the timer to count down from the value prior to the write. Therefore, the time from the start
of count down until the first underflow is undefined.
2: If a write and an underflow occur at approximately the same time in an operating timer, the
reloaded value may be undefined.
Reads from timers
The contents of a timer can be read by a read operation; however, the contents of the timer latch
(measured value) are read in the pulse period measurement mode or the pulse width measurement
mode.
Note: When the high-order byte of an operating timer is read, the low-order byte is set in the latch
for reading. Therefore, the read value of the low-order byte retains the value at the time the
high-order byte is being read.
7480 Group and 7481 Group User's Manual
1-64
HARDWARE
1.12 Timer X and Timer Y
Count Operation
The count operation (start/stop) of timer X or timer Y is controlled by the timer X or Y stop control bit of
the timer XY control register as follows:
• When the timer X or Y stop control bit is set to ‘0’, the timer starts counting.
• When the timer X or Y stop control bit is set to ‘1’, the timer stops counting.
In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count
source.
The timer X or Y stop control bit is recognized during the HIGH time of the count source. When the count
has stopped, the count source cannot be accepted.
In the PWM mode, the high- and the low-order bytes of timer X or Y counts down each as an 8-bit timer.
Reloading Timers
When a timer reaches ‘000016’ in the count operation, an underflow occurs at the subsequent rising edge
of the count source, and the contents of the timer latch are reloaded to the timer.
In the pulse period measurement mode or the pulse width measurement mode, when a timer reaches
‘000016’, an underflow occurs and a timer wraps around to ‘FFFF16’ at the ubsequent rising edge of the
count source.
In the PWM mode, the high- and the low-order byte of a timer count h as an 8-bit timer. When
either the high- or the low-order byte of the timer becomes ‘0116’, aow occurs at the subsequent
rising edge of the count source, and the contents of the timer leloaded to the timer.
Timer Interrupt
At an underflow, the timer X or Y interrupt request bit ot request register 1 is set to ‘1’; then a
timer interrupt request is generated.
Table 1.12.1 lists the relation between timer cods and values set to timer X and timer Y.
Table 1.12.1 Relation between Timer Couds and Values Set to Timer X and Timer Y
Clock Input
f(XIN) = 4 MHz
f(XIz
Oscillation Frequency
Count Source
(Cycle Time)
f(XIN)/16
f(XIN)/8
f(XIN)/16
f(XIN)/2
f(XIN)/2
(0.25 µs)
s)
(2 µs)
(0.5 µs)
(2 µs)
(4 µs)
High- LoLow- High- Low- High- Low- High- Low- High- Low-
order der order order order order order order order order order
0F16
1F16
4E16
3F16
1F16
0316
E716
0116
F316
0716 CF16 0116
F316
E716
0016
0116
F916
F316
E116
C316
D316
A716
1 ms
2 ms
0716 CF16 0316
E716 0F16
C316 2716
8716 4E16
A716
9F16
0F16
1F16
0316
0916
1316
6116
1316
2716
8716
0F16
0916
1316
6116
C316 0416
5 ms
10 ms
50 ms
100 ms
9C16 3F16
–
8716
A716
0916
3016
6116
–
–
C316 4F16
–
–
C316 4F16
C316 4F16
7480 Group and 7481 Group User's Manual
1-65
HARDWARE
1.12 Timer X and Timer Y
1.12.4 Timer Mode and Event Count Mode
(1) Operations in Timer Mode and Event Count Mode
Operations in the timer mode and the event count mode are explained with Figure 1.12.8.
Count Sources
In the timer mode and the event count mode, timer X or timer Y can select the following count
sources with the timer X or Y count source selection bits:
• f(XIN)/2
• f(XIN)/8
timer mode
• f(XIN)/16
• CNTR0 pin input (Timer X used)
• CNTR1 pin input (Timer Y used)
event count mode
Notes 1: In the event count mode, the inverted signal of input to a CNTR pin is used as the count
source when a CNTR edge selection bit of the edge polarity selection register is ‘1’.
2: In the event count mode, keep the frequency of the CNin input used as the count
source f(XIN)/4 or less.
Writes to and Reads from Timers
When ‘TL (000016 through FFFF16)’ is written to a tifollowing different operations are
performed depending on the state of the timer X or ontrol bit:
• In the ‘0’ state of the timer X or Y write contr‘TL’ is set in both the timer latch and the
timer ( ➀ in Figure 1.12.8).
• In the ‘1’ state of the timer X or Y write bit, the ‘TL’ is set in the timer latch only.
Also, the contents of the timer can y a read operation.
Count Operation
• When the timer X or Y stobit of the timer XY control register is cleared to ‘0’, the timer
starts counting (➁ in Fi.8).
• When the timer X or ntrol bit is set to ‘1’, the timer stops counting (➂ in Figure 1.12.8).
In the count operationtents of each timer are decremented by 1 at every rising edge of the
count source (➃ i1.12.8).
Reloading Timers
When a timer reaches ‘000016’ in the count operation, an underflow occurs at the subsequent rising
edge of the count source, and the contents of the timer latch are reloaded to the timer (➄ in Figure
1.12.8).
Timer Interrupt
At an underflow, the timer X or Y interrupt request bit is set to ‘1’; then a timer interrupt request is
generated (➅ in Figure 1.12.8).
7480 Group and 7481 Group User's Manual
1-66
HARDWARE
1.12 Timer X and Timer Y
Count source
(Note 2)
‘0’ is
‘1’ is
‘0’ is
written
written
written
Timer X stop
control bit
Count start
Count start
Writing to timer
X (Note 1)
Count stop
3
2
4
RL
RL
UF
RL
TL
1
5
000016
UF
UF
Time
T
6
Timer X interrupt
request bit
A
A
A
TL
RL
UF
T
: Setting value to timer X
: Contents of timer latch is reloaded
: Underflow
: Count period
1
T(s) =
×
(Setting value to
Count source frequency
: Clearing by writing ‘0’ to interrupt request bit or accepting intst
A
Notes 1: In this case, timer X write control bit is ‘0’ (writing to er latch simultaneously).
2: In event count mode,
• when CNTR edge selection bit is ‘0’, CNTR pin d as the count source.
• when CNTR edge selection bit is ‘1’, the invpin input is used as the count source.
Figure 1.12.8 Operation Example in Timeand Event Count Mode
7480 Group and 7481 Group User's Manual
1-67
HARDWARE
1.12 Timer X and Timer Y
(2) Setting of Timer Mode and Event Count Mode
Figures 1.12.9 and 1.12.10 show the setting of the timer mode and the event count mode.
Procedure 1 Stop of timer count
b7
b0
Timer XY control register (TXYCON) [Address 00F816
]
1 1
Timer X count stop (when timer X is used)
Timer Y count stop (when timer Y is used)
Procedure 2 Setting CNTR pin input in event counter mode
1. Setting port pin which has the alternative function of CNTR pin to input mode
b7
b0
Port P4 direction register (P4D) [Address 00C916
]
0 0
Port P40 input mode (when timer X is used)
Port P41 input mode (when timer Y is used)
(Note 1)
Notes 1: In the 7480 Group, its are not implemented.
b3 b2
: ‘Nnted’.
2. Setting edge porality selection register
b7
b0
Edge porality selection register (EG) [Address
CNTR0 edge porality selection (when timer X is
CNTR1 edge porality selection (when timer
0: CNTR pin input is used as the count
1: The inverted CNTR pin input is ust source.
Procedure 3 Setting timer mode register
• when timer X is used
b7
b0
Timer X mode r[Address 00F616
Timer • event
]
0 0 0
Timer X w
0: Wnd timer simultaneously
1y latch
source selection
2
N)/8
in timer mode
(XIN)/16
1: CNTR0 pin input
in event count mode
• when timer Y is used
b7
b0
Timer Y mode register (TYM) [Address 00F716
Timer • event count mode
]
0 0 0
Timer Y write control
0: Writing to latch and timer simultaneously
1: Writing to only latch
Timer Y count source selection
00: f(XIN)/2
in timer mode
01: f(XIN)/8
10: f(XIN)/16
11: CNTR1 pin input
in event count mode
Figure 1.12.9 Setting of Timer Mode and Event Count Mode (1)
7480 Group and 7481 Group User's Manual
1-68
HARDWARE
1.12 Timer X and Timer Y
Procedure 4 Setting timer (Note 2)
• when timer X is used
Timer X low-order (TXL) [Address 00F016
]
Timer X high-order (TXH) [Address 00F116
Timer X count value is set
]
]
• when timer Y is used
Timer Y low-order (TYL) [Address 00F216
]
Timer Y high-order (TYH) [Address 00F316
Timer Y count value is set
Notes 2: When wer, set the low-order byte
and hyte in this order.
Procedure 5 Start of timer count
b7
b0
Timer XY control register (TXYCON) [Ad6
]
0 0
Timer X count start (when timer X is used
Timer Y count start (when timer Y is us
Figure 1.12.10 Setting of Timer Modvent Count Mode (2)
7480 Group and 7481 Group User's Manual
1-69
HARDWARE
1.12 Timer X and Timer Y
1.12.5 Pulse Output Mode
(1) Operations in Pulse Output Mode
Operations in the pulse output mode are explained with Figure 1.12.11.
Count Sources
In the pulse output mode, timer X or timer Y can select the following count sources with the timer
X or Y count source selection bits:
• f(XIN)/2
• f(XIN)/8
• f(XIN)/16
Writes to and Reads from Timers
When ‘TL (000016 through FFFF16)’ is written to a timer, the following different operations are
performed depending on the state of the timer X or Y write control bit:
• In the ‘0’ state of the timer X or Y write control bit, the ‘TL’ is soth the timer latch and the
timer ( ➀ in Figure 1.12.11).
• In the ‘1’ state of the timer X or Y write control bit, the ‘Tn the timer latch only.
Also, the contents of the timer can be read by a read .
Count Operation
• When the timer X or Y stop control bit is cl‘0’, the timer starts counting (➁ in Figure
1.12.11).
• When the timer X or Y stop control bit is ’, the timer stops counting (➂ in Figure 1.12.11).
In the count operation, the contents of r are decremented by 1 at every rising edge of the
count source (➃ in Figure 1.12.11).
Reloading Timers
When a timer reaches ‘0000count operation, an underflow occurs at the subsequent rising
edge of the count source, contents of the timer latch are reloaded to the timer (➄ in Figure
1.12.11).
Timer Interrupt
At an underflow, ther X or Y interrupt request bit is set to ‘1’; then a timer interrupt request is
generated (➅ in Figure 1.12.11).
Pulse Output
At every underflows, polarity-inverted pulses are output from the following pins (➆ in Figure 1.12.11):
• CNTR0 pin (Timer X used)
• CNTR1 pin (Timer Y used)
When the timer X or Y write control bit is ‘0’, the CNTR pin output is initialized to the following levels
by a write to the timer:
• HIGH when the CNTR edge selection bit is ‘0’ (➇ in Figure 1.12.11).
• LOW when the CNTR edge selection bit is ‘1’.
Notes 1: When the timer X or Y write control bit is ‘1’, the CNTR pin output level cannot be initialized
by a write to the timer.
2: In the pulse output mode, the output level of a CNTR pin is inverted when the CNTR edge
selection bit is switched (➈ in Figure 1.12.11).
7480 Group and 7481 Group User's Manual
1-70
HARDWARE
1.12 Timer X and Timer Y
Count source
‘0’ is
‘1’ is
‘0’ is
written
written
written
Timer X stop
control bit
Count start
Count start
Writing to timer
Writing to timer
X (Note 1)
X (Note 2)
2
Count stop
3
RL
UF
4
RL
RL
UF
RL
UF
TL
1
5
000016
UF
Time
A
6
Timer X interrupt
request bit
A
A
A
‘1’ is
written
CNTR
0 edge
selection bit
Initialized when
writing to timer X
7
8
CNTR0 pin output
H
Undefined
TL
RL
UF
H
: Setting value to timer X
: Contents of timer latch is reloaded
: Underflow
: Pulse width
1
H(s) =
×
(Setimer X + 1)
Count source frequency
A
: Clearing by writing ‘0’ to interrupt request ing interrupt request
Notes 1: In this case, timer X write control ng to timer and timer latch simultaneously).
2: In this case, timer X write contrriting to only timer latch).
Figure 1.12.11 Operation En Pulse Output Mode
7480 Group and 7481 Group User's Manual
1-71
HARDWARE
1.12 Timer X and Timer Y
(2) Setting of Pulse Output Mode
Figures 1.12.12 and 1.12.13 show the setting of the pulse output mode.
Procedure 1 Stop of timer count
b7
b0
Timer XY control register (TXYCON) [Address 00F816
]
1 1
Timer X count stop (when timer X is used)
Timer Y count stop (when timer Y is used)
Procedure 2 Setting CNTR pin output
1. Setting port pin which has the alternative function of CNTR pin to output mode (Note 1)
b7
b0
Port P4 direction register (P4D) [Address 00C916
]
1 1
Port P4
0
output mode (when timer X is used)
output mode (when timer Y is used)
(Note 2)
Port P4
1
Notes 1: Pay attention ttput level of CNTR pin.
2: In the 7480 e bits are not implemented.
b3 b2
2. Setting edge polarity selection register
plemented’.
b7
b0
Edge polarity selection register (EG) [Addre
CNTR
0
edge polarity selection (when timer X
edge polarity selection (when tim
CNTR
1
0: When setting operation mode, HIGfrom CNTR pin is started.
1: When setting operation mode, Lut from CNTR pin is started.
Procedure 3 Setting timer mode register
• when timer X is used
b7
b0
Timer X mode M) [Address 00F616
Pulse outp
]
0 0 1
Timer X
0: and timer simultaneously
nly latch
nt source selection
N)/2
XIN)/8
: f(XIN)/16
11: Not available
• when timer Y is used
b7
b0
Timer Y mode register (TYM) [Address 00F716
Pulse output mode
]
0 0 1
Timer Y write control
0: Writing to latch and timer simultaneously
1: Writing to only latch
Timer Y count source selection
00: f(XIN)/2
01: f(XIN)/8
10: f(XIN)/16
11: Not available
Figure 1.12.12 Setting of Pulse Output Mode (1)
7480 Group and 7481 Group User's Manual
1-72
HARDWARE
1.12 Timer X and Timer Y
Procedure 4 Setting timer (Note 3)
• when timer X is used
Timer X low-order (TXL) [Address 00F016
]
Timer X high-order (TXH) [Address 00F116
Timer X count value is set
]
]
• when timer Y is used
Notes 3: • When writing to timer, set the low-order
byte and high-order byte in this order.
• When setting count value to timer, CNTR
pin is initialized to the contents of the
CNTR edge selection bit.
Timer Y low-order (TYL) [Address 00F216
]
Timer Y high-order (TYH) [Address 00F316
Timer Y count value is set
Procedure 5 Start of timer count
b7
b0
Timer XY control register (TXYCON) [Address 00F816
0 0
Timer X count start (when timer X is used)
Timer Y count start (when timer Y is used)
Figure 1.12.13 Setting of Pulse Output Mode
7480 Group and 7481 Group User's Manual
1-73
HARDWARE
1.12 Timer X and Timer Y
1.12.6 Pulse Period Measurement Mode
(1) Operations in Pulse Period Measurement Mode
Operations in the pulse period measurement mode are explained with Figure 1.12.14.
Count Sources
In the pulse period measurement mode, timer X or timer Y can select the following count sources
with the timer X or Y count source selection bits:
• f(XIN)/2
• f(XIN)/8
• f(XIN)/16
Writes to and Reads from Timers
In the pulse period measurement mode, do not write to timers.
When a timer is read, the read value is the contents of the timer latch (measured value of the last
pulse period).
Count Operation
• When the timer X or Y stop control bit is cleared to ‘0’, tstarts counting ( ➀ in Figure
1.12.14).
• When the timer X or Y stop control bit is set to ‘1’, tstops counting.
In the count operation, the contents of each timer are ented by 1 at every rising edge of the
count source (➁ in Figure 1.12.14).
Reloading Timers
When a timer reaches ‘000016’ in the counon, an underflow occurs at the subsequent rising
edge of the count source and a timer und to ‘FFFF16’ (➂ in Figure 1.12.14).
When the valid edge of a CNTR pidetected in the count operation, the timer goes to
‘FFFF16’ (➃ in Figure 1.12.14).
Timer Interrupt
At an underflow, the timer terrupt request bit of interrupt request register 1 is set to ‘1’; then
a timer interrupt requerated (➄ in Figure 1.12.14).
CNTR Interrupt
When the valid eda CNTR pin input is detected, the CNTR interrupt request bit of interrupt
request register 2 is set to ‘1’, and the CNTR interrupt request is generated (➅ in Figure 1.12.14).
The measured value of the pulse period must be read at this time.
Pulse Period Measurement
When any one of the following valid edges are detected, the complement on one of the contents of
the timer is written to the timer latch (➆ in Figure 1.12.14). The contents of the timer latch are
retained until the measurement of the next pulse period is complete.
• Valid edge of a CNTR0 pin input (Timer X used)
• Valid edge of a CNTR1 pin input (Timer Y used)
The measurement type of pulse period is selected by a CNTR edge selection bit of the edge polarity
selection register as follows:
• The period from a falling edge of a CNTR pin input until the next falling edge when the CNTR edge
selection bit is ‘0’ (➇ in Figure 1.12.14).
• The period from a rising edge of a CNTR pin input until the next rising edge when the CNTR edge
selection bit is ‘1’.
7480 Group and 7481 Group User's Manual
1-74
HARDWARE
1.12 Timer X and Timer Y
• When the period from falling edge until the next falling edge is measured (Note)
CNTR
0
pin input
6
8
T
CNTR
0
interrupt
A
A
A
A
A
request bit
Count source
‘0’ is
written
Timer X stop
control bit
Count start
1
RL
UF
RL
RL
RL
RL
UF
RL
2
FFFF16
000016
3
5
4
Time
7
7
7
Timer X interrupt
request bit
A
A
RL : ‘FFFF16’ is reloaded
UF : Underflow
T : Pulse period
n: The number of timer interrupt
request generation during measuring.
1
T(s) =
×
{(Contench + 1) +65536 × n}
Count source frequency
: Clearing by writing ‘0’ to interrupt request bit or arupt request
A
Note: In this case, CNTR0 edge selection bit is ‘0’ is valid).
Figure 1.12.14 Operation Example Period Measurement Mode
7480 Group and 7481 Group User's Manual
1-75
HARDWARE
1.12 Timer X and Timer Y
(2) Setting of Pulse Period Measurement Mode
Figure 1.12.15 shows the setting of the pulse period measurement mode.
Procedure 1 Stop of timer count
b7
b0
Timer XY control register (TXYCON) [Address 00F816
]
1 1
Timer X count stop (when timer X is used)
Timer Y count stop (when timer Y is used)
Procedure 2 Setting CNTR pin input
1. Setting port pin which has the alternative function of CNTR pin to input mode
b7
b0
Port P4 direction register (P4D) [Address 00C916
]
0 0
Port P4
0
input mode (when timer X is used)
input mode (when timer Y is used)
(Note)
Port P4
1
Note: In the 7480 Grous are not implemented.
b3 b2
plemented’.
2. Setting edge polarity selection register
b7
b0
Edge polarity selection register (EG) [A16
]
CNTR
0
edge polarity selection (when ti
edge polarity selection (wheed)
CNTR
1
0: CNTR pin input from falling tted
1: CNTR pin input from risinunted
Procedure 3 Setting timer mode register
• when timer X is used
b7
b0
Timer X moXM) [Address 00F616
Pulse peent mode
]
0 1 0
Timce selection
16
available
• when timer Y is u
b7
Timer Y mode register (TYM) [Address 00F716
Pulse period measurement mode
]
0
Timer Y count source selection
00: f(XIN)/2
01: f(XIN)/8
10: f(XIN)/16
11: Not available
Procedure 4 Start of timer count
b7
b0
Timer XY control register (TXYCON) [Address 00F816
]
0 0
Timer X count start (when timer X is used)
Timer Y count start (when timer Y is used)
Figure 1.12.15 Setting of Pulse Period Measurement Mode
7480 Group and 7481 Group User's Manual
1-76
HARDWARE
1.12 Timer X and Timer Y
1.12.7 Pulse Width Measurement Mode
(1) Operations in Pulse Width Measurement Mode
Operations in the pulse width measurement mode are explained with Figure 1.12.16.
Count Sources
In the pulse width measurement mode, timer X or timer Y can select the following count sources with
the timer X or Y count source selection bits:
• f(XIN)/2
• f(XIN)/8
• f(XIN)/16
Writes to and Reads from timers
In the pulse width measurement mode, do not write to timers.
When a timer is read, the read value is the contents of the timer latch (measured value of the last
pulse width).
Count Operation
• When the timer X or Y stop control bit is cleared to ‘0’, tstarts counting ( ➀ in Figure
1.12.16).
• When the timer X or Y stop control bit is set to ‘1’, tstops counting.
In the count operation, the contents of each timer are nted by 1 at every rising edge of the
count source (➁ in Figure 1.12.16).
Reloading Timers
When a timer reaches ‘000016’ in the counon, an underflow occurs at the subsequent rising
edge of the count source and a timer und to ‘FFFF16’ (➂ in Figure 1.12.16).
When the valid edge of a CNTR pidetected in the count operation, the timer goes to
‘FFFF16’ (➃ in Figure 1.12.16).
Timer Interrupt
At an underflow, the timenterrupt request bit is set to ‘1’; then a timer interrupt request is
generated (➄ in Figure .
CNTR Interrupt
When the valid eda CNTR pin input is detected, the CNTR interrupt request bit of interrupt
request register 2 is set to ‘1’, and the CNTR interrupt request is generated (➅ in Figure 1.12.16).
The measured value of the pulse width must be read at this time.
Pulse Width Measurement
When any one of the following valid edges are detected, the complement on one of the contents of
the timer is written to the timer latch (➆ in Figure 1.12.16). The contents of the timer latch are
retained until the measurement of the next pulse width is complete.
• Valid edge of a CNTR0 pin input (Timer X used)
• Valid edge of a CNTR1 pin input (Timer Y used)
The measurement type of pulse width is selected by a CNTR edge selection bit as follows:
• HIGH-level period from a rising edge of a CNTR pin input until the next falling edge when the CNTR
edge selection bit is ‘0’ (➇ in Figure 1.12.16).
• LOW-level period from a falling edge of a CNTR pin input until the next rising edge when the CNTR
edge selection bit is ‘1’.
7480 Group and 7481 Group User's Manual
1-77
HARDWARE
1.12 Timer X and Timer Y
• When HIGH-level period is measured (Note)
CNTR
0
pin input
6
8
H
A
A
A
CNTR
0
interrupt
request bit
Count source
‘0’ is
written
Timer X stop
control bit
Count start
1
4
RL
UF
RL
RL
RL
RL
UF
RL
2
FFFF16
000016
3
5
Time
7
7
A
A
Timer X interrupt
request bit
RL
UF
H
: ‘FFFF16’ is reloaded
: Underflow
: Pulse width
n: The number of timer interrupt
1
request generation during measuring.
H(s) = Count source frequency × {(Contents +1) + 65536 × n}
: Clearing by writing ‘0’ to interrupt request bit or accept request
A
Note: In this case, CNTR0 edge selection bit is ‘0’ (favalid).
Figure 1.12.16 Operation Example Width Measurement Mode
7480 Group and 7481 Group User's Manual
1-78
HARDWARE
1.12 Timer X and Timer Y
(2) Setting of Pulse Width Measurement Mode
Figure 1.12.17 shows the setting of the pulse width measurement mode.
Procedure 1 Stop of timer count
b7
b0
Timer XY control register (TXYCON) [Address 00F816
]
1 1
Timer X count stop (when timer X is used)
Timer Y count stop (when timer Y is used)
Procedure 2 Setting CNTR pin input
1. Setting port pin which has the alternative function of CNTR pin to input mode
b7
b0
Port P4 direction register (P4D) [Address 00C916
]
0 0
Port P4
0
input mode (when timer X is used)
input mode (when timer Y is used)
(Note)
Port P4
1
Note: In the 7480 Gbits are not implemented.
b
implemented’.
2. Setting edge polarity selection register
b7
b0
Edge polarity selection register (EGD416
]
CNTR
CNTR
0
edge polarity selection (wheed)
edge polarity selection (used)
1
0: CNTR pin input from risinGH-level period) is counted
1: CNTR pin input from fLOW-level period) is counted
Procedure 3 Setting timer mode register
• when timer X is used
b7
b0
Timer X r (TXM) [Address 00F616
Pulsement mode
]
0 1 1
ource selection
)/8
IN)/16
Not available
• when timer Y is u
b7
Timer Y mode register (TYM) [Address 00F716
Pulse width measurement mode
]
0 1
Timer Y count source selection
00: f(XIN)/2
01: f(XIN)/8
10: f(XIN)/16
11: Not available
Procedure 4 Start of timer count
b7
b0
Timer XY control register (TXYCON) [Address 00F816
]
0 0
Timer X count start (when timer X is used)
Timer Y count start (when timer Y is used)
Figure 1.12.17 Setting of Pulse Width Measurement Mode
7480 Group and 7481 Group User's Manual
1-79
HARDWARE
1.12 Timer X and Timer Y
1.12.8 Programmable Waveform Generation Mode
(1) Operations in Programmable Waveform Generation Mode
Operations in the programmable waveform generation mode are explained with Figure 1.12.18.
Count Sources
In the programmable waveform generation mode, timer X or timer Y can select the following count
sources with the timer X or Y count source selection bits:
• f(XIN)/2
• f(XIN)/8
• f(XIN)/16
Writes to and Reads from Timers
When ‘TL (000016 through FFFF16)’ is written to a timer, the following different operations are
performed depending on the state of the timer X or Y write control bit:
• In the ‘0’ state of the timer X or Y write control bit, the ‘TL’ is seth the timer latch and the
timer ( ➀ in Figure 1.12.18).
• In the ‘1’ state of the timer X or Y write control bit, the ‘TL’ is timer latch only (➁ in Figure
1.12.18).
Also, the contents of the timer can be read by a reaon.
Count Operation
In the programmable waveform generation e following starting point of a timer can be
selected with the timer X or Y trigger seleof the timer X or Y mode register:
• When a valid edge of an INT0 pin inpected (Timer X used).
• When a valid edge of an INT1 pin etected (Timer Y used).
Clearing the timer X or Y stop it to ‘0’ brings the following results:
• When the timer X or Y trigtion bit is cleared to ‘0’, the timer starts counting.
• When the timer X or Y trection bit is set to ‘1’, the timer starts counting as soon as the
valid edge of an INT is detected (➂ in Figure 1.12.18).
When the timer X oontrol bit is set to ‘1’, the timer stops counting.
Note: Keep the trths input to the INT pins 250 ns or more.
In the count operatihe contents of each timer are decremented by 1 at every rising edge of the
count source (➃ in Figure 1.12.18).
Reloading Timers
When a timer reaches ‘000016’ in the count operation, an underflow occurs at the subsequent rising
edge of the count source, and the contents of the timer latch are reloaded to the timer (➄ in Figure
1.12.18).
Timer Interrupt
At an underflow, the timer X or Y interrupt request bit is set to ‘1’; then a timer interrupt request is
generated (➅ in Figure 1.12.18).
7480 Group and 7481 Group User's Manual
1-80
HARDWARE
1.12 Timer X and Timer Y
Generation of Programmable Waveform
When an underflow occurs in a timer, the contents of the output level latches of the timer X or Y
mode register are output from the following pins (➆ in Figure 1.12.18):
• CNTR0 pin (Timer X used)
• CNTR1 pin (Timer Y used)
When the timer X or Y operation mode bits of the timer X or Y mode register, which are set to other
modes, are switched to the programmable waveform generation mode, the CNTR pin outputs are
initialized to LOW (➇ in Figure 1.12.18).
INT0 pin input
(Note 4)
INT0
A
A
A
interrupt request bit
Count source
‘0’ is
written
Timer X stop
control bit
Count start
Change of timer X
(Note 3)
Writing to timer
X(Note 1)
Change of timer X
(Note 2)
3
(Note 2)
4
RL
RL
2
TL
1
5
UF
RL
UF
RL
UF
000016
UF
Time
Timer X interrupt
request bit
A
A
A
A
A
‘1’ is
‘0’ is
‘1’ is
‘0’ is
‘1’ is
written
written
written
written
written
Output level latch
Unde
Initializesetting
timer X oode bits
7
CNTR0 pin output
H
Undefined
TL : Setting value to timer X
RL : Contents of timer latch is reloaded
UF : Underflow
H : Pulse width
1
H(s) =
×
(Setting value to timer X+1)
Count source frequency
: Clearing by writing ‘0’ to interrupt request bit or accepting interrupt request
A
Notes 1: In this case, timer X write control bit is ‘0’ (writing to timer and timer latch simultaneously).
2: In this case, timer X write control bit is ‘1’ (writing to only timer latch).
3: In this case, timer X trigger selection bit is ‘1’ (trigger occurs, at the same time, timer X is activated ).
4: In this case, INT0 edge selection bit is ‘1’ (rising edge is valid).
Figure 1.12.18 Operation Example in Programmable Waveform Generation Mode
7480 Group and 7481 Group User's Manual
1-81
HARDWARE
1.12 Timer X and Timer Y
(2) Setting of Programmable Waveform Generation Mode
Figures 1.12.19 and 1.12.20 show the setting of the programmable waveform generation mode.
Procedure 1 Stop of timer count
b7
b0
Timer XY control register (TXYCON) [Address 00F816
]
1 1
Timer X count stop (when timer X is used)
Timer Y count stop (when timer Y is used)
Procedure 2 Setting INT pin input and CNTR pin output
1. Setting port pin which has the alternative function of the CNTR pin to output mode (Note 1)
b7
b0
Port P4 direction register (P4D) [Address 00C916
]
1 1
Port P4
0
output mode (when timer X is used)
output mode (when timer Y is used)
(Note 2)
Port P4
1
Notes 1: Pay attention to the outt level of CNTR pin.
2: In the 7480 Group, ts are not implemented.
b3 b2
: ‘Nnted’.
2. Setting INT edge selection bit when timer is activated by the trigger of INT p
b7
b0
Edge polarity selection register (EG) [Addres
INT
INT
0
edge polarity selection (when timer X is u
edge polarity selection (when timer Y
1
0: Timer is activated by detecting the fNT pin input
1: Timer is activated by detecting thf INT pin input
Procedure 3 Setting timer mode register
• when timer X is used
b7
b0
Timer X mode reg[Address 00F616
]
1 0 0
Programmable eration mode (Note 3)
Timer X wr
0: Wrid timer simultaneously
1: atch
Oh
er selection
X free run
gger occurrence (input signal of INT0 pin) and timer X start
er X count source selection
00: f(XIN)/2
01: f(XIN)/8
10: f(XIN)/16
11: Not available
Notes 3: The CNTR pin output is initialized to LOW when the operation mode
bits set to other modes are set to the programmable waveform
generation mode.
Figure 1.12.19 Setting of Programmable Waveform Generation Mode (1)
7480 Group and 7481 Group User's Manual
1-82
HARDWARE
1.12 Timer X and Timer Y
• when timer Y is used
b7
b0
Timer Y mode register (TYM) [Address 00F716
]
1 0 0
Programmable waveform generation mode (Note 3)
Timer Y write control
0: Writing to latch and timer simultaneously
1: Writing to only latch
Output level latch
Timer Y trigger selection
0: Timer Y free run
1: Trigger occurrence (input signal of INT1 pin) and timer Y start
Timer Y count source selection
00: f(XIN)/2
01: f(XIN)/8
10: f(XIN)/16
11: Not available
Procedure 4 Setting timer (Note 4)
• when timer X is used
Timer X low-order (TXL) [Address 00F016
]
Timer X high-order (TXH) [Address 00F116
Timer X count value is set
]
• when timer Y is used
Timer Y low-order (TYL) [Address 0
Timer Y high-order (TYH) [Add
Timer Y count value is s
Notes 4: When writing to timer, set the low-order byte
and high-order byte in this order.
Procedure 5 Start of timer count (Note
b7
b0
Timer gister (TXYCON) [Address 00F816
]
0 0
Timt (when timer X is used)
Ttart (when timer Y is used)
Notes 5: When bit 5 of timer mode register is ‘1’,
timer count does not start at this time.
Trigger (input signal of INT pin) occurs,
at the same time, timer count starts.
Notes 6: Keep the trigger width input to INT pin 250 ns
or more.
Figure 1.12.20 Setting of Programmable Waveform Generation Mode (2)
7480 Group and 7481 Group User's Manual
1-83
HARDWARE
1.12 Timer X and Timer Y
1.12.9 Programmable One-Shot Output Mode
(1) Operations in Programmable One-Shot Output Mode
Operations in the programmable one-shot output mode is explained with Figure 1.12.21.
Count Sources
In the programmable one-shot output mode, timer X or timer Y can select the following count sources
with the timer X or Y count source selection bits:
• f(XIN)/2
• f(XIN)/8
• f(XIN)/16
Writes to and Reads from Timers
When ‘TL (000016 through FFFF16)’ is written to a timer, the following different operations are
performed depending on the state of the timer X or Y write control bit:
• In the ‘0’ state of the timer X or Y write control bit, the ‘TL’ is seth the timer latch and the
timer ( ➀ in Figure 1.12.21).
• In the ‘1’ state of the timer X or Y write control bit, the ‘TLn the timer latch only.
Also, the contents of the timer can be read by a read
Count Operation
• When the timer X or Y stop control bit is cle0’, the timer starts counting (➁ in Figure
1.12.21).
• When the timer X or Y stop control bit i1’, the timer stops counting.
In the count operation, the contents of er are decremented by 1 at every rising edge of the
count source (➂ in Figure 1.12.21).
Reloading Timers
When a timer reaches ‘0000count operation, an underflow occurs at the subsequent rising
edge of the count source, ontents of the timer latch are reloaded to the timer (➃ in Figure
1.12.21).
When the valid edge pin input is detected, the contents of the timer latch are also reloaded
(➄ in Figure 1.12.
Timer Interrupt
At an underflow, the timer X or Y interrupt request bit is set to ‘1’; then a timer interrupt request is
generated (➅ in Figure 1.12.21).
Generation of Programmable One-Shot Pulse
• When timer X is used, a one-shot pulse is output from the CNTR0 pin when the valid edge of an
INT0 pin input is detected (➆ in Figure 1.12.21).
• When timer Y is used, a one-shot pulse is output from the CNTR1 pin when the valid edge of an
INT1 pin input is detected.
7480 Group and 7481 Group User's Manual
1-84
HARDWARE
1.12 Timer X and Timer Y
When the timer X or Y operation mode bits of the timer X or Y mode register are set to the
programmable one-shot output mode, the CNTR pin outputs are initialized to the content of the CNTR
edge selection bit (➇ in Figure 1.12.21).
The CNTR pin output remains at the inverted level of the content of the CNTR edge selection bit for
the period from the rising edge 1 of the count source immediately after the valid edge of an INT pin
input is detected until the subsequent an underflow (➈ in Figure 1.12.21).
Notes 1: Keep the trigger widths input to the INT pins 250 ns or more.
2: In the programmable one-shot output mode, the output level of a CNTR pin is inverted
when the CNTR edge selection bit is switched (➉ in Figure 1.12.21).
1: One cycle or less of the rising edge of the count source, after the valid edge of an INT pin input
is detected.
INT
0
pin input
(Note 2)
INT
0
A
interrupt request bit
Count source
‘0’ is
written
Timer X stop control bit
Count start
Writing to timer X
(Note 1)
2
3
RL
UF
RL
UF
RL
RL
RL
UF
TL
5
6
1
000016
Time
A
A
A
Timer X interrupt request bit
‘0’ is
written
CNTR
0
edge selection bit
Initialized to the contents of CNTR
0 edge selection bit
when setting timer X operation mode bits
10
8
7
CNTR0 pin output
H
9
Undefined
TL
RL
UF
H
: Setting value to timer X
: Contents of timer latch is reloaded
: Underflow
: Pulse width
1
H(s) =
×
(Setting value to timer X + 1)
Count source frequency
: Clearing by writing ‘0’ to interrupt request bit or accepting interrupt request
A
Notes 1: In this case, timer X write control bit is ‘0’ (writing to timer and timer latch simultaneously).
2: In this case, INT edge selection bit is ‘1’ (rising edge is valid).
0
Figure 1.12.21 Operation Example in Programmable One-Shot Output Mode
7480 Group and 7481 Group User's Manual
1-85
HARDWARE
1.12 Timer X and Timer Y
(2) Setting of Programmable One-Shot Output Mode
Figures 1.12.22 and 1.12.23 show the setting of the programmable one-shot output mode.
Procedure 1 Stop of timer count
b7
b0
Timer XY control register (TXYCON) [Address 00F816
]
1 1
Timer X count stop (when timer X is used)
Timer Y count stop (when timer Y is used)
Procedure 2 Setting INT pin input and CNTR pin output
1. Setting port pin which has the alternative function of the CNTR pin to output mode (Note 1)
b7
b0
Port P4 direction register (P4D) [Address 00C916
]
1 1
Port P4
0
output mode (when timer X is used)
output mode (when timer Y is used)
(Note 2)
Port P4
1
Notes 1: Pay attention tt level of CNTR pin.
2: In the 7480 se bits are not implemented.
b3
implemented’.
2. Setting INT edge selection bit and CNTR edge selection bit
b7
b0
Edge polarity selection register (EG0D416
]
INT
INT
0
edge polarity selection (when )
edge polarity selection (whsed)
1
0: Falling edge of INT pin in
1: Rising edge of INT pin
CNTR
0
edge polarity stimer X is used)
CNTR
1
edge polariten timer Y is used)
0: HIGH level frs output after the maximum 1 cycle of
count soudetection of INT pin input.
1: LOW lepin is output after the maximum 1 cycle of
count igger detection of INT pin input.
Procedure 3 Setting timer mode
• when timer X is used
b7
b0
X mode register (TXM) [Address 00F616
]
1 0 1
Pogrammable one-shot output mode (Note 3)
Timer X write control
0: Writing to latch and timer simultaneously
1: Writing to only latch
Timer X count source selection
00: f(XIN)/2
01: f(XIN)/8
10: f(XIN)/16
11: Not available
Notes 3: When setting operation mode, CNTR pin output is
initialized to the contents of the CNTR edge selection bit.
Figure 1.12.22 Setting of Programmable One-Shot Output Mode (1)
7480 Group and 7481 Group User's Manual
1-86
HARDWARE
1.12 Timer X and Timer Y
• when timer Y is used
b7
b0
Timer Y mode register (TYM) [Address 00F716
]
1 0 1
Programmable one-shot output mode (Note 3)
Timer Y write control
0: Writing to latch and timer simultaneously
1: Writing to only latch
Timer Y count source selection
00: f(XIN)/2
01: f(XIN)/8
10: f(XIN)/16
11: Not available
Procedure 4 Setting timer (Note 4)
• when timer X is used
Timer X low-order (TXL) [Address 00F016
]
Timer X high-order (TXH) [Address 00F116
Timer X count value is set
]
• when timer Y is used
Timer Y low-order (TYL) [Address 00
Timer Y high-order (TYH) [Addre
Timer Y count value is set
Notes 4: When writing to timer, set the low-order byte
and high-order byte in this order.
Procedure 5 Start of timer count
b7
b0
Timer Xster (TXYCON) [Address 00F816
]
0 0
Timer when timer X is used)
Timt (when timer Y is used)
Notes 5: Keep the trigger width input to INT pin 250 ns
or more.
Figure 1.12.23 Setting of Programmable One-Shot Output Mode (2)
7480 Group and 7481 Group User's Manual
1-87
HARDWARE
1.12 Timer X and Timer Y
1.12.10 PWM Mode
(1) Operations in PWM Mode
Operations in the PWM mode are explained with Figure 1.12.24.
Count Sources
In the PWM mode, timer X or timer Y can select the following count sources with the timer X or Y
count source selection bits:
• f(XIN)/2
• f(XIN)/8
• f(XIN)/16
Writes to and Reads from Timers
When ‘TL (000016 through FFFF16)’ is written to a timer, the following different operations are
performed depending on the state of the timer X or Y write control bit:
• In the ‘0’ state of the timer X or Y write control bit, the ‘TL’ is seth the timer latch and the
timer ( ➀ in Figure 1.12.24).
• In the ‘1’ state of the timer X or Y write control bit, the ‘TLn the timer latch only.
Also, the contents of the timer can be read by a read
Count Operation
In the PWM mode, the high- and the low-order timer counts down each as an 8-bit timer.
• When the timer X or Y stop control bit is cl0’ in the HIGH state of the PWM output, only
the high-order byte of the timer starts cown (➁ in Figure1.12.24), while in the LOW state
of the PWM output, only the low-order e timer starts counting down (➂ in Figure 1.12.24).
• When the stop control bit is set to the high- and the low-order byte stop counting down
(➃ in Figure 1.12.24).
In the count operation, the conte high- or the low-order byte of the timer are decremented
by 1 at every rising edge of t source (➄ in Figure 1.12.24).
When either the high- or tder byte of an operating timer becomes ‘0116’, it stops counting.
At the same time, the ts counting (➅ in Figure 1.12.24).
Reloading Timer
When either the higr the low-order byte of an operating timer becomes ‘0116’, an underflow
occurs at the subsequent rising edge of the count source, and the contents of the timer latch is
reloaded to the timer (➅ in Figure 1.12.24).
Timer Interrupt
At an rising edge of the PWM output waveform, the timer X or Y interrupt request bit is set to ‘1’;
then a timer interrupt request is generated (➆ in Figure 1.12.24).
PWM Output
• When timer X is used, the PWM waveform is output from the CNTR0 pin.
• When timer Y is used, the PWM waveform is output from the CNTR1 pin.
7480 Group and 7481 Group User's Manual
1-88
HARDWARE
1.12 Timer X and Timer Y
When the timer X or Y write control bit is ‘0’, the CNTR pin output is initialized to HIGH by a write
to the timer (➇ in Figure 1.12.24). When it is ‘1’, however, the CNTR pin output level cannot be
initialized by a write to the timer. In the PWM mode, when the low-order byte of the timer becomes
‘0116’ in the LOW level of the PWM output (➈ in Figure 1.12.24), or when the high-order byte
becomes ‘0116’ in the HIGH level of the PWM output (➉ in Figure 1.12.24), an underflow occurs in
each timer at the subsequent rising edge of the count source and the output level of the CNTR pin
is inverted.
When ‘TLL (0016 through FF16)’ is written to the low-order byte of the timer and ‘TLH (0016 through
FF16)’ to the high-order byte, the duty cycle of the PWM waveform output from the CNTR pin is
expressed by ‘TLH/(TLH + TLL)’.
Notes 1: • All of the PWM outputs are HIGH when TLL = 0016 and TLH ≠ 0016.
• All of the PWM outputs are LOW when TLH = 0016.
2: When at least one of TLL and TLH is ‘0016’, no timer interrupt request can be generated.
3: Even when value ‘0016’ is written to a timer, the timer continues counting down. Therefore,
the contents of the timer are undefined.
Count source
n
‘0’ is written
‘0’ is written
Timer X stop
control bit
Count start
Writing to timer X
(high-order) (Note)
Count start
2
3
Count stop
5
UF
RL
RL
UF
4
RL
TLH
1
0116
0016
U
UF
Time
Time
Writing to timer X
(low-order) (Note)
RL
UF
RL
UF
RL
UF
TLL
1
0116
0016
7
Timer X interrupt
request bit
A
A
A
Initialized to HIGH when
writing to timer X (Note)
9
10
HH
HL
8
CNTR0 pin output
T
Undefined
TL
TL
H
: Setting value to timer X (high-order)
: Setting value to timer X (low-order)
RL: Contents of timer latch is reloaded
UF: Underflow
L
T : PWM period T(s)=H
H
H
+ H
: Pulse width (HIGH-period)
(s) =
L
H
1
× Setting value to timer X (high-order)
× Setting value to timer X (low-order)
HH
Count source frequency
H
L
: Pulse width (LOW-period)
1
H
L
(s) =
Count source frequency
A
: Clearing by writing ‘0’ to interrupt request bit or accepting interrupt request
Note: In this case, timer X write control bit is ‘0’ (writing to timer and timer latch simultaneously).
Figure 1.12.24 Operation Example in PWM Mode
7480 Group and 7481 Group User's Manual
1-89
HARDWARE
1.12 Timer X and Timer Y
(2) Setting of PWM Mode
Figures 1.12.25 and 1.12.26 show the setting of the PWM mode.
Procedure 1 Stop of timer count
b7
b0
Timer XY control register (TXYCON) [Address 00F816
]
1 1
Timer X count stop (when timer X is used)
Timer Y count stop (when timer Y is used)
Procedure 2 Setting CNTR pin output (Setting the port pin which has the alternative function of CNTR pin to
output mode) (Note 1)
b7
b0
Port P4 direction register (P4D) [Address 00C916
]
1 1
Port P4
0
output mode (when timer X is used)
output mode (when timer Y is used)
(Note 2)
Port P4
1
Notes 1: Pay attention to tevel of CNTR pin.
2: In the 7480 Grbits are not implemented.
b3 b2
plemented’.
Procedure 3 Setting timer mode register
• when timer X is used
b7
b0
Timer X mode register (TXM) [Ad6
]
1 1 0
PWM mode (Note 3)
Timer X write control
0: Writing to latch and tiusly
1: Writing to only latc
Timer X count sour
00: f(XIN)/2
01: f(XIN)/8
10: f(XIN)/
11: Not
• when timer Y is used
b7
b0
ode register (TYM) [Address 00F716
]
1 1 0
mode (Note 3)
er Y write control
0: Writing to latch and timer simultaneously
1: Writing to only latch
Timer Y count source selection
00: f(XIN)/2
01: f(XIN)/8
10: f(XIN)/16
11: Not available
Notes 3: When setting operation mode, CNTR pin output is
initialized to HIGH.
Figure 1.12.25 Setting of PWM Mode (1)
7480 Group and 7481 Group User's Manual
1-90
HARDWARE
1.12 Timer X and Timer Y
Procedure 4 Setting timer (Note 4)
• when timer X is used
Timer X low-order (TXL) [Address 00F016
]
Timer X low-order count value (LOW level output interval) is set
Timer X high-order (TXH) [Address 00F116
]
Timer X high-order count value (HIGH level output interval) is set
• when timer Y is used
Timer Y low-order (TYL) [Address 00F216
]
Timer Y low-order count value (LOW level output interval) is set
Timer Y high-order (TYH) [Address 00F316
]
Timer Y high-order count value (HIGH level output interval) iet
Notes 4: When wer, set the low-order byte
and hte in this order.
Procedure 5 Start of timer count
b7
b0
Timer XY control register (TXYCON) [Ad
]
0 0
Timer X count start (when timer X is used)
Timer Y count start (when timer Y is use
Figure 1.12.26 Setting of PWM Mode (2)
7480 Group and 7481 Group User's Manual
1-91
HARDWARE
1.12 Timer X and Timer Y
1.12.11 Notes on Usage
Pay attention to the following notes when timer X or Y is used.
(1) In All Modes
Write to and Read from Timers
Write to and read from each timer two bytes together in the following order:
• Write: ➀ low-order byte → ➁ high-order byte
• Read: ➀ high-order byte → ➁ low-order byte
When a read from and a write into the same timer are executed during an interrupt service routine
etc., the normal operation cannot be performed.
In the pulse period measurement mode and the pulse width measurement mode, do not write to
timers.
Writes to Timers
When the timer X or Y write control bit is ‘0’:
• A write to an operating timer causes the contents of the timer to be ffected, so that the time from
the last underflow until the next underflow is undefined in this c
• A write to the low-order byte of an operating timer allows the tintinue counting down until
the next write to the high-order byte. Therefore, the time uubsequent underflow may be
undefined.
Figure 1.12.27 shows an operation in timer X or timer s.
• Example: Writing ‘020016’ into timer
Count source
0016
FF16
FE16
FD16
Contents of timer (low-order)
Contents of timer (high-order)
Undefin
defined value
0216
‘0016’ is written to the ‘0216’ is written to the
low-order of timer high-order of timer
Note: In this case, the write control bit is ‘0’.
Figure 1.12.27 Operation imer X or Timer Y at Writes
When the timer X or Y write control bit is ‘1’:
• A write to a stopped timer causes the contents of the timer not to be affected and allows the timer
to count down from the value prior to this write. Therefore, the time from the start of count down
until the first underflow is undefined.
• If a write and an underflow occur at approximately the same time in an operating timer, the reloaded
value may be undefined.
7480 Group and 7481 Group User's Manual
1-92
HARDWARE
1.12 Timer X and Timer Y
Reads from Timers
• When the high-order byte of an operating timer is read, the low-order byte is set in the latch for
reading. Therefore, the read value of the low-order byte retains the value at the time the high-order
byte is being read.
• In the count operation, the contents of each timer are decremented by 1 at every rising edge of
the count source, while the contents of each timer are transferred to the latch for reading by falling
edge, so that the read value of the timer may be different from its real value.
Figure 1.12.28 shows an operation in timer X or timer Y at reads.
Count source
010116
010016
00FF16
00FE16
00FD16
Contents of timer
010216
010016
00FF16
00FE16
010116
Read value of timer
High-order of timer is read (Read value: ‘0116’)
In this case, the low-order read value ‘0116’ is
written to latch for reading.
Low-order of timer is rvalue: ‘0116’)
Figure 1.12.28 Operation in Timer X or Timer Y at Reads
(2) In Event Count Mode
The inverted signal of input to a CNTR pin is used ount source when a CNTR edge selection
bit of the edge polarity selection register is ‘1
Keep the frequency of the CNTR pin inps the count source f(XIN)/4 or less.
(3) In Pulse Output Mode
When the timer X or Y write cont0’, the CNTR pin output is initialized to the following levels
by a write to the timer:
• HIGH when the CNTR edion bit is ‘0’.
• LOW when the CNTR ection bit is ‘1’.
When the timer X te control bit, however, is ‘1’, the CNTR pin output level cannot be
initialized by a write timer.
The output level of a CNTR pin is inverted when the CNTR edge polarity selection bit is switched.
(4) In Pulse Period Measurement Mode and Pulse Width Measurement Mode
Do not write to timers in these modes; otherwise the last measured value in the timer latch will be
changed by this write.
When a timer is read, the read value is the contents of the timer latch (the last measured value).
(5) In Programmable Waveform Generation Mode
When the timer X or Y operation mode bits, which are set to other modes, are switched to the
programmable waveform generation mode, the CNTR pin outputs are initialized to LOW.
When the timer X or Y trigger selection bit is ‘1’, keep the trigger widths input to the INT pins 250ns
or more.
7480 Group and 7481 Group User's Manual
1-93
HARDWARE
1.12 Timer X and Timer Y
(6) In Programmable One-Shot Output Mode
When the timer X or Y operation mode bits are set to the programmable one-shot output mode, the
CNTR pin outputs are initialized to the content of the CNTR edge selection bit.
The output level of a CNTR pin is inverted when the CNTR edge selection bit is switched.
Keep the trigger widths input to the INT pins 250 ns or more.
(7) In PWM Mode
When the timer X or Y write control bit is ‘0’, the CNTR pin output is initialized to HIGH by a write
to the timer. When the write control bit is ‘1’, the CNTR pin output level cannot be initialized by a
write to the timer.
All of the PWM outputs are HIGH when TLL = 0016 and TLH ≠ 0016.
All of the PWM outputs are LOW when TLH = 0016.
When at least one of TLL and TLH is ‘0016’, no timer interrupt an be generated.
Even when value ‘0016’ is written to a timer, the timer ccounting down. Therefore, the
contents of the timer are undefined.
(8) I/O Port Pins P40 and P41 with the Alternative Fof Timer I/O Pins CNTR0 and CNTR1
Port pins P40 and P41 have the alternative fun16-bit timer I/O pins CNTR0 and CNTR1
respectively. If the timer X or Y operation mthe corresponding timer is set to any mode
related to output (Note), these pins cannot the normal function as output port pins. Refer to
Figure 1.10.3 Block Diagrams of Port i to P5i in Section 1.10. Input/Output Pins.
Note: Modes related to output:
• Pulse output mode
• Programmable waveeration mode
• Programmable onutput mode
• PWM mode
(9) Edge Polarity Seegister
When the edge polaselection bit of edge polarity selection register is set, the interrupt request
bit may be set to ‘1’.
Refer to Section 1.11.7 (2) in 1.11 Interrupts.
7480 Group and 7481 Group User's Manual
1-94
HARDWARE
1.13 Timer 1 and Timer 2
1.13 Timer 1 and Timer 2
The 7480 Group and 7481 Group have two 8-bit timers with 8-bit latches:
• Timer 1
• Timer 2
Timer 1 or timer 2 can select the following operation modes by the timer 1 or 2 operation mode bit of the
timer 1 mode register (address 00F916) or the timer 2 mode register (address 00FA16):
• Timer mode
• Programmable waveform generation mode
For details, refer to the section of each mode.
1.13.1 Block Diagram
Figure 1.13.1 shows the block diagram of timer 1 and timer 2.
Data bus
8
Timer count source
selection bits
‘00’
T
Timer interrupt
request bit
Timer stop
f(XIN)/8
f(XIN)/64
‘01’
‘10’
‘11’
control bit
f(XIN)/128
f(XIN)/256
T
el
8
T
0, T1
output
Q
D
Timer mode register
8
Data bus
Figure 1.13.1 Block Diaf Timer 1 and Timer 2
1.13.2 Registers Associated with Timer 1 and Timer 2
Figure 1.13.2 shows the memory map of the registers associated with timer 1 and timer 2.
Timer 1 (T1)
Timer 2 (T2)
00F416
00F516
Timer 1 mode register (T1M)
Timer 2 mode register (T2M)
00F916
00FA16
Figure 1.13.2 Memory Map of Registers Associated with Timer 1 and Timer 2
7480 Group and 7481 Group User's Manual
1-95
HARDWARE
1.13 Timer 1 and Timer 2
(1) Timer 1 and Timer 2
These are the 8-bit registers that count the pulses of count sources.
• When a timer is written, the written data is set to the timer and the timer latch (Note).
• When a timer is read, the read value is the contents of the timer.
Note: The timer latches are the registers that hold the initial values automatically reloaded to the
timers when they underflow. Actually, the value decremented by 1 from the contents of the
timer latch is reloaded to the timer.
Figures 1.13.3 and 1.13.4 show the timer 1 and timer 2.
Timer 1 (Timer 1 latch)
b7 b6 b5 b4 b3 b2 b1 b0
Timer1 (T1) [Address 00F416
b
]
R
O
O
W
O
O
Function
set
The timer 1 count value is indicated.
1
1
1
0
1
O
O
O
O
2
3
4
1
1
1
O
O
O
O
5
6
7
O
O
O
O
1
1
Figure 1.13.3 Timer 1
Timer 2 (Timer 2 latch)
b7 b6 b5 b4 b3 b2 b1
(T2) [Address 00F516
]
Function
R
O
O
W
O
O
At reset
b
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
The timer 2 count value is indicated.
1
2
O
O
O
O
3
4
5
O
O
O
O
O
O
6
7
O
O
Figure 1.13.4 Timer 2
7480 Group and 7481 Group User's Manual
1-96
HARDWARE
1.13 Timer 1 and Timer 2
(2) Timer 1 Mode Register and Timer 2 Mode Register
These registers consist of the bits controlling the operation of timer 1 and timer 2.
Figures 1.13.5 and 1.13.6 show the timer 1 and 2 mode registers.
Timer 1 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 mode register (T1M) [Address 00F916
]
0
0 0
b
0
Name
Function
At reset
0
R
O
W
O
Timer 1 stop control bit 0 : Count operation
1 : Count stop
O
O
1
0
Timer 1 operation
mode bit
0 : Timer mode
1 : Programmable waveform generation mode
×
×
O
0
0
0
0
2
3
4
Not implemented. Writing to these bits is disabled.
These bits are ‘0’ at reading.
O
Output level latch
0 : LOW output from T
1 : HIGH output from T
0
pin
pin
0
0
0
×
O
O
5
6
Not implemented. Writing to this bit is disabled.
This bit is ‘0’ at reading.
b7 b6
O
O
Timer 1 count source
0 0 : f(XIN)/8
selection bits
0 1 : f(XIN)/64
1 0 : f(XIN)/
1 1 : f(X
7
0
Figure 1.13.5 Timer 1 Mode Register
Timer 2 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Tgister (T2M) [Address 00FA16
]
0
0 0
R
O
W
O
Name
Function
At reset
0
Timer 2 stop control bit 0 : Count operation
1 : Count stop
O
O
1
0
Timer 2 operation
mode bit
0 : Timer mode
1 : Programmable waveform generation mode
0
0
×
×
O
2
3
4
Not implemented. Writing to these bits is disabled.
These bits are ‘0’ at reading.
0
0
0
O
Output level latch
0 : LOW output from T
1
pin
pin
1 : HIGH output from T
1
0
5
0
×
Not implemented. Writing to this bit is disabled.
This bit is ‘0’ at reading.
b7 b6
0 0 : f(XIN)/8
0 1 : f(XIN)/64
1 0 : f(XIN)/128
1 1 : f(XIN)/256
O
O
O
Timer 2 count source
selection bits
6
7
0
0
O
Figure 1.13.6 Timer 2 Mode Register
7480 Group and 7481 Group User's Manual
1-97
HARDWARE
1.13 Timer 1 and Timer 2
1.13.3 Basic Operations of Timer 1 and Timer 2
Basic operations of timer 1 and timer 2 are described below.
For details, refer to (1) Operations of each mode.
Count Sources
Timer 1 and timer 2 can select the following count sources with the timer 1 or 2 count source select bits
of the timer 1 or 2 mode register:
• f(XIN)/8
• f(XIN)/64
• f(XIN)/128
• f(XIN)/256
Writes to Timers
When ‘TL(0016 through FF16)’ is written to a timer, ‘TL’ is set in both the timer and the timer latch.
Note: A write to an operating timer causes the contents of the timer to be afected, so that the period from
the last underflow until the next underflow is undefined.
Reads from Timers
The contents of the timer can be read by a read operation.
Count Operations
The count operation (start/stop) of timer 1 or timer 2 is d by the timer 1 or 2 stop control bit of
the timer 1 or 2 mode register as follows:
• When the timer 1 or 2 stop control bit is set to ‘mer starts counting.
• When the timer 1 or 2 stop control bit is set ttimer stops counting.
In the count operation, the contents of each tidecremented by 1 at every rising edge of the count
source.
The timer 1 or 2 stop control bit is recogring the HIGH time of the count source. When the count
has stopped, the count source cannopted.
Reloading Timers
When a timer reaches ‘FF16’ unt operation, an underflow occurs at the subsequent rising edge of
the count source, and the remented by 1 from the contents of the timer latch is reloaded to the
timer.
Timer Interrupt
At an underflow, the timer 1 or 2 interrupt request bit of interrupt request register 1 is set to ‘1’; then a
timer interrupt request is generated.
Table 1.13.1 lists the relation between timer count periods and values set to timer 1 and timer 2.
7480 Group and 7481 Group User's Manual
1-98
HARDWARE
1.13 Timer 1 and Timer 2
Table 1.13.1 Relation between Timer Count Periods and Values Set to Timer 1 and Timer 2
Clock Input
Oscillation Frequency
Count Source
(Count Period)
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN)/8
(1µs)
6316
C716
—
f(XIN)/64 f(XIN)/128 f(XIN)/256
f(XIN)/8
(2µs)
3116
6316
F916
—
f(XIN)/64
(16µs)
—
f(XIN)/128
(8µs)
—
(16µs)
—
(32µs)
—
(32µs)
—
100 µs
200 µs
500 µs
1 ms
1816
—
—
—
—
—
—
—
—
—
—
7C16
F916
—
—
—
—
—
—
7C16
F916
—
—
7C16
F916
—
2 ms
—
7C16
—
7C16
4 ms
1.13.4 Timer Mode
(1) Operations in Timer Mode
The operations in the timer mode is explained with Figure 1.13.7
Count Sources
In the timer mode, timer 1 or timer 2 can select the follnt sources with the timer 1 or 2
count source selection bits of the timer 1 or 2 mode r
• f(XIN)/8
• f(XIN)/64
• f(XIN)/128
• f(XIN)/256
7480 Group and 7481 Group User's Manual
1-99
HARDWARE
1.13 Timer 1 and Timer 2
Writes to and Reads from Timer
When ‘TL (0016 through FF16)’ is written to a timer, ‘TL’ is set in both the timer and the timer latch
( ➀ in Figure 1.13.7).
Also, the contents of the timer can be read by a read operation.
Count Operation
• When the timer 1 or 2 stop control bit is cleared to ‘0’, the timer starts counting (➁ in Figure 1.13.7).
• When the timer 1 or 2 stop control bit is set to ‘1’, the timer stops counting (➂ in Figure 1.13.7).
In the count operation, the contents of each timer are decremented by 1 at every rising edge of the
count source (➃ in Figure 1.13.7).
Reloading Timers
When a timer reaches ‘FF16’ in the count operation, an underflow occurs at the subsequent rising
edge of the count source, and the value decremented by 1 from the contents of the timer latch is
reloaded to the timer. (➄ in Figure 1.13.7).
Timer Interrupt
At an underflow, the timer 1 or 2 interrupt request bit is set to ‘timer interrupt request is
generated (➅ in Figure 1.13.7).
Count source
‘0’ is
‘0’ is
written
written
Timer 1 stop
control bit
Count start
2
Count start
Count stop
Writing to timer 1
Writing to timer 1
RL
4
3
TL
TL–1
RL
RL
UF
1
0016
FF16
UF
UF
UF
Time
T
6
Timer 1 interrupt
request bit
A
A
A
A
TL: Setting value to timer 1
RL: The value which is the timer latch decremented by 1 is reloaded
UF: Underflow
1
× (Setting value to timer 1 +1)
T(s) =
T: Count period
Count source frequency
: Clearing by writing ‘0’ to interrupt request bit or accepting interrupt request
A
Figure 1.13.7 Operations in Timer Mode
7480 Group and 7481 Group User's Manual
1-100
HARDWARE
1.13 Timer 1 and Timer 2
(2) Setting of Timer Mode
Figure 1.13.8 shows the setting of the timer mode.
Procedure 1 Stop of timer count
• when timer 1 is used
b7
b0
1
Timer 1 mode register (T1M) [Address 00F916
Timer 1 count is stopped.
]
• when timer 2 is used
b7
b0
1
Timer 2 mode register (T2M) [Address 00FA16
Timer 2 count is stopped.
]
Procedure 2 Setting timer mode register
• when timer 1 is used
b7
b0
Timer 1 mode register (T1M) [Address 00F916
Timer mode
]
0 1
Timer 1 count source selection
00: f(XIN)/8
01: f(XIN)/64
10: f(XIN)/128
11: f(XIN)/256
• when timer 2 is used
b7
b0
Timer 2 mode register (T2M) [Addr
Timer mode
0 1
Timer 2 count source selection
00: f(XIN)/8
01: f(XIN)/64
10: f(XIN)/128
11: f(XIN)/256
Note : Procedure n be set simultaneously because the described register is the same.
Procedure 3 Setting timer
• when timer 1 is used
1) [Address 00F416
1 count value is set
]
• when timer 2 is used
Timer 2 (T2) [Address 00F516
Timer 2 count value is set
]
Procedure 4 Start of timer count
• when timer 1 is used
b7
b0
0 0
Timer 1 mode register (T1M) [Address 00F916
Timer 1 count is started
]
• when timer 2 is used
b7
b0
0 0
Timer 2 mode register (T2M) [Address 00FA16
Timer 2 count is started
]
Figure 1.13.8 Setting of Timer Mode
7480 Group and 7481 Group User's Manual
1-101
HARDWARE
1.13 Timer 1 and Timer 2
1.13.5 Programmable Waveform Generation Mode
(1) Operations in Programmable Waveform Generation Mode
Operations in the programmable waveform generation mode is explained with Figure 1.13.9.
Count Sources
In the programmable waveform generation mode, timer 1 or timer 2 can select the following count
sources with the timer 1 or 2 count source selection bits:
• f(XIN)/8
• f(XIN)/64
• f(XIN)/128
• f(XIN)/256
Writes to and Reads from Timers
When ‘TL(0016 through FF16)’ is written to a timer, ‘TL’ is set in both the timer and the timer latch
( ➀ in Figure 1.13.9).
Also, the contents of the timer can be read by a read operation.
Count Operation
• When the timer 1 or 2 stop control bit is cleared to ‘0’, the rts counting (➁ in Figure 1.13.9).
• When the timer 1 or 2 stop control bit is set to ‘1’, thops counting (➂ in Figure 1.13.9).
In the count operation, the contents of each timer are nted by 1 at every rising edge of the
count source (➃ in Figure 1.13.9).
Reloading timers
When a timer reaches ‘FF16’ in the count n, an underflow occurs at the subsequent rising
edge of the count source, and the valuented by 1 from the contents of the timer latch is
reloaded to the timer. (➄ in Figure 1
Timer interrupt
At an underflow, the timer 1 rrupt request bit is set to ‘1’; then a timer interrupt request is
generated (➅ in Figure 1.
Generation of Proge Waveform
When an underfls in a timer, the contents of the output level latch are output from the
following pins (➆ in ure 1.13.9):
• T0 pin (Timer 1 used)
• T1 pin (Timer 2 used)
The output level of the T0 or T1 pin remains undefined until the first underflow occurs in this mode
(➇ in Figure 1.13.9).
7480 Group and 7481 Group User's Manual
1-102
HARDWARE
1.13 Timer 1 and Timer 2
Count source
‘0’ is
‘1’ is
‘0’ is
written
written
written
Timer 1 stop
control bit
Count start
2
Count start
Writing TL
Writing TL to timer 1
to timer 1
Writing TL to timer 1
RL
TL'
TL' – 1
4
Count stop
3
RL
UF
RL
UF
RL
TL
TL – 1
1
5
6
0016
FF16
UF
UF
Time
A
A
A
A
Timer 1 interrupt
request bit
‘1’ is
‘0’ is
‘1’ is
‘0’ is
‘1’ is
written
written
written
written
written
Output level latch
Undefined
8
7
T0 pin output
H
Undefined
: Clearing by writing ‘0’ to interrupt request bg interrupt request
A
TL: Setting value to timer 1
RL: The value which is the timer latch by 1 is reloaded
UF: Underflow
H: Pulse width
× (Setting value to timer 1 +1)
H(s) =
Count scy
Figure 1.13.9 Operations in mable Waveform Generation Mode
7480 Group and 7481 Group User's Manual
1-103
HARDWARE
1.13 Timer 1 and Timer 2
(2) Setting of Programmable Waveform Generation Mode
Figures 1.13.10 and 1.13.11 show the setting of the programmable waveform generation mode.
Procedure 1 Stop of timer count
• when timer 1 is used
b7
b0
1
Timer 1 mode register (T1M) [Address 00F916
]
Timer 1 count is stopped.
• when timer 2 is used
b7
b0
1
Timer 2 mode register (T2M) [Address 00FA16
Timer 2 count is stopped.
]
Procedure 2 Setting port which is also used as T pin to output mode (Note 1)
b0
b7
Port P1 direction register (P1D) [Address 00C316
]
0 0
Port P1
2
3
output mode (when timer 1 is used)
output mode (when timer 2 is used)
Port P1
Notes 1: Pn to the output level of T pin.
Procedure 3 Setting timer mode register
• when timer 1 is used
b7
b0
Timer 1 mode register (T100F916
]
1 1
Programmable waveform de
Output level latch
Timer 1 count sour
00: f(XIN)/8
01: f(XIN)/64
10: f(XIN)/
11: f(X
• when timer 2 is used
b7
b0
mode register (T2M) [Address 00FA16
]
1 1
ammable waveform generation mode
tput level latch
Timer 2 count source selection
00: f(XIN)/8
01: f(XIN)/64
10: f(XIN)/128
11: f(XIN)/256
Notes 2 : Procedure 1 and 3 can be set simultaneously
because the described register is the same.
Figure 1.13.10 Setting of Programmable Waveform Generation Mode (1)
7480 Group and 7481 Group User's Manual
1-104
HARDWARE
1.13 Timer 1 and Timer 2
Procedure 4 Setting timer
• when timer 1 is used
Timer 1 (T1) [Address 00F416
Timer 1 count value is set
]
]
• when timer 2 is used
Timer 2 (T2) [Address 00F516
Timer 2 count value is set
Procedure 5 Start of timer count
• when timer 1 is used
b7
b0
1 0
Timer 1 mode register (T1M) [Address 0916
Timer 1 count is started
]
• when timer 2 is used
b7
b0
1 0
Timer 2 mode register (T2M) FA16
Timer 2 count is started
]
Figure 1.13.11 Setting of Programmable Waveforation Mode (2)
7480 Group and 7481 Group User's Manual
1-105
HARDWARE
1.13 Timer 1 and Timer 2
1.13.6 Notes on Usage
Pay attention to the following notes when timer 1 or timer 2 is used.
(1) In All Modes
A write to an operating timer causes the contents of the timer to be affected, so that the period from
the last underflow until the next underflow is undefined.
In the count operation, the contents of each timer are decremented by 1 at every rising edge of the
count source, while the contents of each timer are transferred to the latch for reading at the falling
edge, so that the read value of the timer may be different from its real value by +1.
Figure 1.13.12 shows an operation in timer 1 and timer 2 at reads.
• when ‘7F16’ is written to timer
Count source
FF16
Contents of timer
Timer read value
0116
0016
7D16
7C16
0216
0116
0016
7E16
7D16
Timer
interrupt request bit
learing by writing ‘0’ to interrupt request bit or
accepting interrupt request
Figure 1.13.12 Operations in Timer 1 an2 at Reads
(2) I/O Port Pins P12 and P13 witernative Functions of Timer Output Pins T0 and T1
Port pins P12 and P13 have native functions of timer output pins T0 and T1 respectively. If
the timer operation mode corresponding timer (1 or 2) is set to the programmable waveform
generation mode, thesnnot perform the normal function as output port pins. Refer to Figure
1.10.1 Block Diagrort Pins P0i and P10–P13 in Section 1.10 Input/Output pins.
Therefore, set the onding timer (1 or 2) operation mode bit to the timer mode when these pins
are used as normal Iport pins.
7480 Group and 7481 Group User's Manual
1-106
HARDWARE
1.14 Serial I/O
(1) Transmit Buffer Register and Receive Buffer Register
The transmit buffer register and the receive buffer register are located at the same address. These
registers are written transmit data and read receive data when clock synchronous or clock asynchronous
serial I/O is used.
Clock Synchronous Serial I/O
A write to the transmit buffer register (Note) starts the following operations:
• When the BRG output/4 is selected as the synchronous clock, communication is started.
• When an external clock is selected as the synchronous clock and the SRDY output is in the enable
state, the level of the SRDY signal changes from HIGH to LOW, and the completion of the communication
preparation is signaled to the external.
Clock Asynchronous Serial I/O (UART)
A write to the transmit buffer register (Note) starts data transmission.
Note: During transmission, data is written to the transmit buffer regiser.
During reception, dummy data is written to the transmit buffer rewhen the clock synchronous
serial I/O is selected.
Figure 1.14.2 shows the transmit/receive buffer register.
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer B) [Address 00E016
]
b
At reset
unction
R
W
0
1
Undefined
Undefined
In tran
Transferred to the transmit shift register
bit data.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
2
n:
Note
ta is stored completely in the receive shift
er, the receive data is transferred to this register.
7
Note: In transmission, this register is a write-only register.
In reception, this register is a read-only register.
Figure 1.14.2 Transmit/Receive Buffer Register
7480 Group and 7481 Group User's Manual
1-108
HARDWARE
1.14 Serial I/O
(2) Serial I/O Status Register
This register consists of the flags that indicate the serial I/O transmit/receive status.
Figure 1.14.3 shows the serial I/O status register.
Serial I/O status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O status register (SIOSTS) [Address 00E116
]
1
b
Name
Function
0 : Buffer full
At reset
0
R
O
W
×
0
Transmit buffer empty flag
(TBE)
1 : Buffer empty
1
0
×
×
0 : Buffer empty
1 : Buffer full
O
O
Receive buffer full flag
(RBF)
0 : Transmit shift in progress
1 : Transmit shift completed
2
3
4
5
0
0
0
Transmit shift completion
flag (TSC)
×
×
×
O
O
0 : No error
1 : Overrun error
Overrun error flag
(OE)
0 : No error
1 : Parity error
Parity error flag
(PE)
0 : No error
1 : Framing
O
Framing error flag
(FE)
×
×
6
7
Summing error flag
(SE)
0 : OE
1 : O1
0
1
O
1
This bit is fixed to ‘1’.
Note: b4 and b5 are valid only i
Figure 1.14.3 Serial I/O Status Register
Each flag of the serial I/O status rdescribed below.
Transmit Buffer Empty Flag it 0)
This flag indicates the stattransmit buffer register.
• When the data written nsmit buffer register is transferred to the transmit shift register, this
flag is set to ‘1’.
• When transmit dtten to the transmit buffer register, this flag is cleared to ‘0’.
This flag is valid h clock synchronous serial I/O and UART.
Receive Buffer Full Flag (RBF: bit 1)
This flag indicates the status of the receive buffer register.
• When receive data is stored completely in the receive shift register and transferred to the receive
buffer register, this flag is set to ‘1’.
• When the transferred data is read from the receive buffer register, this flag is cleared to ‘0’.
This flag is valid in both clock synchronous serial I/O and UART.
Transmit Shift Completion Flag (TSC: bit 2)
This flag indicates the status of the transmit shift operation.
• When the data in the transmit buffer register is transferred to the transmit shift register, and shift
operation is started by the synchronous clock (the start bit of the transmit data is transmitted), this
flag is cleared to ‘0’.
• When the shift operation is completed (the transmission of the last bit of the transmit data is
completed), this flag is set to ‘1’.
This flag is valid in both clock synchronous serial I/O and UART.
7480 Group and 7481 Group User's Manual
1-109
HARDWARE
1.14 Serial I/O
Overrun Error Flag (OE: bit 3)
This flag indicates the status of reading receive data.
• When the next receive data is stored completely in the receive shift register before the receive data
stored in the receive buffer register is read through, this flag is set to ‘1’.
• This flag is cleared to ‘0’ by any operations listed in Table 1.14.1.
This flag is valid in both clock synchronous serial I/O and UART.
Parity Error Flag (PE: bit 4)
This flag indicates the result of checking even or odd parity by hardware in UART.
• This flag is set to ‘1’ when the parity of the receive data differs from the predetermined parity.
• This flag is cleared to ‘0’ by any operation listed in Table 1.14.1.
This flag is valid only at parity enable in UART.
Framing Error Flag (FE: bit 5)
This flag indicates faults of frame synchronization in UART.
• When the stop bit of receive data is not received at the specified timng, this flag is set to ‘1’. Only
the first stop bit is tested and the second stop bit is not tested.
• This flag is cleared to ‘0’ by any operation listed in Table 1.1
This flag is valid only in UART.
Summing Error Flag (SE: bit 6)
This flag indicates faults of serial I/O.
• When the overrun error, parity error or framing urs, this flag is set to ‘1’.
• This flag is cleared to ‘0’ by any operation lisble 1.14.1.
This flag is valid in both clock synchronol I/O and UART.
[Clearing Error Flag]
Error flags (bits 3 to 6) of the serial s register are cleared to ‘0’ by any operation listed in
Table 1.14.1.
Table 1.14.1 Clearing Error Flags
Set Seriable Bit
Set Receive Enable Bit
Dummy Data is Written to
Clearing Method
Error Flag
’
to ‘0’
O
Serial I/O Status Register
Overrun Error Flag
Parity Error Flag
Framing Error Flag
Summing Error Flag
O
×
×
×
O
O
O
O
O
O
O
7480 Group and 7481 Group User's Manual
1-110
HARDWARE
1.14 Serial I/O
(3) Serial I/O Control Register
This register controls the selection of a transmit/receive mode, a synchronous clock, serial I/O pin
functions, etc. of serial I/O.
Figure 1.14.4 shows the serial I/O control register.
Serial I/O control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address 00E216
]
b
0
Name
Function
At reset
0
R
O
W
O
BRG count source
selection bit (CSS)
0 : f(XIN)/4
1 : f(XIN)/16
Serial I/O synchronous
clock selection bit (SCS)
0
O
1
O
when clock synchronous serial I/O is selected
0 : BRG output/4
1 : External clock input
when UART is selected
0 : BRG output/16
1 : External clock input
O
O
2
3
S
RDY output enable bit
0 : P1
1 : SRDY output p
7
pin
0
0
O
O
(SRDY)
0 : Interrupt ocit
buffer is
1 : Interransmit shift
oped.
Transmit interrupt source
selection bit (TIC)
O
O
O
O
4
5
6
7
Transmit enable bit
(TE)
0 bled
nabled
0
0
0
Receive enable bit
(RE)
ve disabled
eive enabled
O
O
Serial I/O mode se
(SIOM)
Asynchronous serial I/O (UART)
1 : Clock synchronous serial I/O
O
O
Serial I
(SIO
0 : Serial I/O disabled
1 : Serial I/O enabled
0
Figure 1.14.4 Serial I/O Control R
7480 Group and 7481 Group User's Manual
1-111
HARDWARE
1.14 Serial I/O
(4) UART Control Register
This register controls the data transmission formats in clock asynchronous serial I/O (UART).
This register is valid only when UART is selected.
Figure 1.14.5 shows the UART control register.
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1
UART control register (UARTCON) [Address 00E316
]
b
0
Name
Function
At reset
0
R
O
W
O
0 : 8 bits
1 : 7 bits
Character length selection bit
(CHAS)
Parity enable bit
(PARE)
0 : Parity disabled
1 : Parity enabled
O
O
1
2
3
0
0
O
O
O
Parity selection bit
(PARS)
0 : Even parity
1 : Odd parity
Stop bit length selection bit
(STPS)
O
1
0 : 1 stop bit
1 : 2 stop bits
These bits are fixed to ‘1’.
×
×
×
×
4
5
1
1
1
1
1
1
6
7
1
Figure 1.14.5 UART Control Register
7480 Group and 7481 Group User's Manual
1-112
HARDWARE
1.14 Serial I/O
(5) Baud Rate Generator (BRG)
The baud rate generator is an 8-bit counter with an auto-reload register, used only for serial I/O.
When the serial I/O synchronous clock selection bit of the serial I/O control register is ‘0’, setting
value ‘n’ (any number of 0016 to FF16) to the baud rate generator outputs a signal of the BRG count
source (Note 1) divided by ‘n + 1’ as the BRG output (Note 2) .
Notes 1: • f(XIN)/4: when the BRG count source selection bit of the serial I/O control register is ‘0’.
• f(XIN)/16: when the BRG count source selection bit is ‘1’.
2: • BRG output/4 is used for the synchronous clock in clock synchronous serial I/O.
• BRG output/16 is used for the synchronous clock in clock asynchronous serial I/O.
Figure 1.14.6 shows the baud rate generator.
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address 00E416
]
R
W
Function
b
At reset
O
O
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
1
2
• 8-bit timer for baud rate generation
• Valid only when BRG output diviis selected
as synchronous clock.
O
O
O
O
O
O
O
O
3
4
5
O
O
O
6
7
O
O
O
Figure 1.14.6 Baud Rate Generator
(6) Bus Collision Detection Cegister
This register consists of ontrolling the valid/invalid of the bus collision detection.
Figure 1.14.7 shows tllision detection control register.
Bus collision detction control register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
Bus collision detection control register (BUSARBCON) [Address 00E516
]
R
O
W
O
b
0
Name
Function
At reset
0
0 : Collision detection invalid
1 : Collision detection valid
Bus collision detection enable bit
0
0
0
0
0
×
×
×
×
×
×
×
1
2
3
Not implemented.
Writing to these bits is disabled.
These bits are ‘0’ at reading.
0
0
0
4
5
6
0
0
0
0
0
7
0
Figure 1.14.7 Bus Collision Detection Control Register
7480 Group and 7481 Group User's Manual
1-113
HARDWARE
1.14 Serial I/O
1.14.2 Clock Synchronous Serial I/O
In clock synchronous serial I/O, the transmit operation of the transmitter (Note 1) and the receive operation
of the receiver (Note 2) are performed simultaneously, synchronizing with the synchronous clock used for
transferring, which is generated by the clock control circuit.
Notes 1: Synchronized with falling edges of the synchronous clock, data is transmitted from the TxD pin
of the transmitter by the bit.
2: Synchronized with rising edges of the synchronous clock, data is received from the RxD pin of
the receiver by the bit.
Clock synchronous serial I/O is selected by setting the serial I/O mode selection bit of the serial I/O control
register to ‘1’.
Data Communication
• Half-duplex communication: one of the two communicating microcomputers operates only as a transmitter
and the other only as a receiver at a time or vice versa.
• Full-duplex communication: both of the two communicating microcompoperate simultaneously as
transmitter and receiver.
Synchronous Clock
A synchronous clock is selected by the serial I/O synchronous lection bit of the serial I/O control
register as follows:
• 0: BRG output/4
• 1: External clock input to the SCLK pin
For the BRG output, refer to (5) Baud Rate GeBRG) in Section 1.14.1.
When a clock synchronous serial I/O comon is carried out between two microcomputers, the
synchronous clock is normally selected s:
• Microcomputer 1 clears the serial Ironous clock selection bit to ‘0’, and 8 synchronous clock
pulses, generated by writing to tit buffer register, are output from the SCLK pin.
• Microcomputer 2 selects the eck and inputs the pulses outputted from microcomputer 1 to the
SCLK pin. This is the synchock.
Note: When an externaselected as the synchronous clock:
Perform the followiperations while the SCLK pin input is HIGH during data transmission:
• Write ‘1’ to the transmit enable bit
• Write transmit data to the transmit buffer register
The shift operations of the transmit shift register and the receive shift register are performed while
the synchronous clock is being input to the serial I/O circuit. Stop the synchronous clock with 8
cycles when an external clock is selected as the synchronous clock. The synchronous clock automatically
stops after 8 synchronous clock pulses generated when the BRG output/4 is selected as the synchronous
clock.
7480 Group and 7481 Group User's Manual
1-114
HARDWARE
1.14 Serial I/O
Data Transfer Rate (Baud Rate)
In clock synchronous serial I/O, the data transfer rate (baud rate), which is the frequency of the synchronous
clock, is calculated by the following formulas:
• When the serial I/O synchronous clock selection bit is ‘0’.
(BRG output/4 is selected as the synchronous clock)
f(XIN)
Baud rate [bps] =
Division ratio (Note 1) × (BRG setting value (Note 2) + 1) × 4
Notes 1: BRG count source selection bit of the serial I/O control register is as follows:
• ‘0’: Division ratio is 4
• ‘1’: Division ratio is 16.
2: The value written to the baud rate generator (0016 to FF16).
• When the serial I/O synchronous clock selection bit is ‘1’
(an external clock input is selected as the synchronous clock):
Baud rate [bps] = the external clock input frequency from thn
Output of SRDY Signal
In clock synchronous serial I/O, the output level of the changes from HIGH to LOW by writing
to the transmit buffer register when the SRDY output it of serial I/O control register is ‘1’. The
completion of the serial I/O communication preparatialed to the external by the SRDY output. Also,
the SRDY pin returns to the HIGH state at the fiedge of the synchronous clock.
Note: Set the transmit enable bit to ‘1’ as he receive enable bit and the SRDY output enable bit
of the serial I/O control register weceiver outputs the SRDY signal while the external clock
is selected as the synchronous
Starting of Transmission and n
• When the BRG output/4 is as the synchronous clock:
Transmitting and receivwhen a write to the transmit buffer register occurs.
Normally, communicaarted after the completion of communication preparation of the target unit
is recognized with the Y signal.
• When the external clock is selected as the synchronous clock:
Transmitting and receiving starts when input to the external clock starts.
When data is written to the transmit buffer register, the output level of the SRDY pin changes from HIGH
to LOW and informs the target unit of the completion of communication preparation.
7480 Group and 7481 Group User's Manual
1-115
HARDWARE
1.14 Serial I/O
(1) Block Diagram of Clock Synchronous Serial I/O
Figure 1.14.8 shows the block diagram of a clock synchronous serial I/O.
Data bus
Address 00E216
Serial I/O control register
Receive buffer full flag (RBF)
P1
6
P14
Address 00E016
Receive buffer register
Receive interrupt request (RI)
RxD
Receive shift register
Receive enable bit
(RE)
Clock control circuit
S
CLK
Serial I/O enable bit (SIOE)
BRG count source
Serial I/O synchronous clock
selection bit
selection bit (CSS)
Division ratio 1/(n + 1)
Baud rate generator
Address 00E416
Clock control
XIN
1/4
1/4
1/4
RDY output enable bit
(SRDY)
S
Falling edge
detection
F/F
S
RDY
Transmit enable bit
(TE)
Transmit shift register
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O status register
Address 00E116
TxD
Transmit inter
selection
Transmit buffer register
Address 00E01
P17
P15
Da
Figure 1.14.8 Block Diagram k Synchronous Serial I/O
7480 Group and 7481 Group User's Manual
1-116
HARDWARE
1.14 Serial I/O
(2) Operations of Clock Synchronous Serial I/O Transmission
Transmit Operation
➀ When transmit data is written to the transmit buffer register (Note 1), the transmit buffer empty flag
of the serial I/O status register is cleared to ‘0’.
➁ The transmit data written to the transmit buffer register is transferred to the transmit shift register.
When the data transfer to the transmit shift register is completed, the transmit buffer empty flag
goes to ‘1’ (Note 2).
In this instance, when the BRG output/4 is selected as the synchronous clock, 8 synchronous clock
pulses are generated.
➂ Synchronized with a falling edge of the synchronous clock, the least significant bit (LSB) of the
transmit data transferred to the transmit shift register is output from the TxD pin. At this time, the
contents of the transmit shift register are shifted to the low-order direction by one bit, and the
transmit shift completion flag is cleared to ‘0’.
➃ By repeating the shift operation of ‘Transmit Operation ➂’ 8 times, 8-bit transmit data is output from
the TxD pin by the bit from the LSB.
➄ When 8 bits of the transmit data are output by the 8 shift operations, the transmit shift completion
flag is set to ‘1’ (Note 3).
Notes 1: When the external clock is selected as the synchrock, write the transmit data to
the transmit buffer register during the HIGH statsynchronous clock.
2: When the transmit buffer empty flag is ‘1’, thansmit data can be written to the
transmit buffer register.
3: The supply of the synchronous clock pulsransmit shift register stops automatically
upon transmit completion when the Bt/4 is selected as the synchronous clock.
However, when the next transmit dtten to the transmit buffer register during the
‘0’ state of the transmit shift colag, the supply of the synchronous clock pulse
continues, and data is succesnsmitted.
When the external clock is as the synchronous clock, shift operation continues as
long as the external clog input. Therefore, it is necessary to stop the external
clock after transmissipleted.
Serial I/O Transmit Inter
In the following cases, I/O transmit interrupt request bit of interrupt request register 1 is
set to ‘1’: then the inequest is generated.
• When the transmpt source selection bit is ‘0’, and the data written to the transmit buffer
register is transfeo the transmit shift register (‘Transmit Operation ➁’).
• When the transmit interrupt source selection bit is ‘1’, and the shift operation of the transmit shift
register is completed (‘Transmit Operation ➄’).
Figure 1.14.9 shows the transmit operation of clock synchronous serial I/O. The numbers in the figure
corresponds to those of the above-mentioned ‘Transmit Operation’.
Figure 1.14.10 shows a transmit timing of clock synchronous serial I/O.
7480 Group and 7481 Group User's Manual
1-117
HARDWARE
1.14 Serial I/O
1
3
Synchronous clock
Data bus
Writing transmit data
Transmit buffer register
b0
Address 00E016
D7 D6 D5 D4 D3 D2 D1
D0
P15/TxD
Transmit shift register
1
Serial I/O status register
Address 00E116
1
Serial I/O status register
Address 00E116
0
b0
0
b2
Transmit buffer empty flag
Transmit shift completion flag
4
5
2
Synchronous clock
Transmit buffer register
Transferring transmit data
Transmit shift register
Address 00E016
b0
D7 D6 D5 D4 D3 D2 D1
P15/TxD
Transmit shift register
0
Serial I/O status register
Address 00E116
Synchronous clock
1
b0
P15/TxD
Transmit buffer empty flag
Transmit
0
Serial Ier
E116
1
b2
Transmit shift completion flag
Figure 1.14.9 Transmit Operation of Clock Synchrrial I/O
Synchronous clock
D1
D2
D3
D4
D5
D6
D7
TxD pin
Transmit buffer register
write signal
S
RDY pin
Transmit buffer empty flag
Transmit shift completion flag
(Note 1)
(Note 2)
Serial I/O transmit
interrupt request bit
A
A
Clearing by writing ‘0’ to the serial I/O transmit interrupt request bit or
accepting a serial I/O transmit interrupt request.
A :
Notes 1: When the transmit interrupt source selection bit is ‘0’ (transmit buffer is emptied).
2: When the transmit interrupt source selection bit is ‘1’ (transmit shift operation is completed).
Figure 1.14.10 Transmit Timing of Clock Synchronous Serial I/O
7480 Group and 7481 Group User's Manual
1-118
HARDWARE
1.14 Serial I/O
(3) Operations of Clock Synchronous Serial I/O Reception
Receive Operation
➀ Synchronized with a rising edge of the synchronous clock, a transmitted bit data is received on
the RxD pin, which is stored in the most significant bit (MSB) of the receive shift register.
➁ The contents of the receive shift register are shifted to the low-order direction by one bit every time
a bit data is received, and the next bit data is stored in the MSB. 8-bit data is fully stored in the
receive shift register by repeating this shift operation 8 times.
➂ The completely received 8-bit data stored in the receive shift register is transferred to the receive
buffer register. When the data transfer to the receive buffer register is completed, the receive
buffer full flag of the serial I/O status register is set to ‘1’ (Note).
Note: If the next data is stored completely word in the receive shift register before the data transferred
from the receive shift register to the receive buffer register is read through, the overrun error
is generated. At this time, the overrun error flag and the summing error flag of the serial I/O
status register are set to ‘1’. For the handling in this case, refer to ‘ Handling when overrun
error is generated’ in (5) Notes on Usage of Clock Synchronous Serial I/O.
When the receive buffer register is read, the receive buffer g is cleared to ‘0’.
Serial I/O Receive Interrupt
When the data stored completely in the receive shift regiansferred to the receive buffer
register (‘Receive Operation ➂’), the serial I/O receivt request bit of interrupt request
register 1 is set to ‘1’; then the interrupt request is g.
Figure 1.14.11 shows the receive operation of nchronous serial I/O. The numbers in the
figure corresponds to those of the above-meeceive Operation’.
Figure 1.14.12 shows a receive timing of chronous serial I/O.
7480 Group and 7481 Group User's Manual
1-119
HARDWARE
1.14 Serial I/O
1
3
Synchronous clock
Synchronous clock
b0
Receive shift register
D1
D
D
0
D7
D6
D5
D4
D3
D2
0
P1
4
/RxD
/RxD
Transferring receive data
16 Receive buffer register
Receive shift register
Address 00E0
2
Synchronous clock
0
1
b0
Receive shift register
Serial I/O status register
Address 00E116
D3 D2
D1
D0
P14
b1
Receive buffer full flag
Figure 1.14.11 Receive Operation of Clock Synchronous Ser
Synchronous clock
RxD pin
D0
2
D3
D4
D5
D6
D7
ceive shift register
Transmit buffer register
write signal
SRDY pin
Receive buffer read signal
Receive buffer full flag
Serial I/O receive interrupt
request bit
A
A
: Clearing by writing ‘0’ to the serial I/O receive interrupt request bit or
accepting a serial I/O receive interrupt request.
Figure 1.14.12 Receive Timing of Clock Synchronous Serial I/O
7480 Group and 7481 Group User's Manual
1-120
HARDWARE
1.14 Serial I/O
(4) Setting of Clock Synchronous Serial I/O
Figures 1.14.13 and 1.14.14 show the setting of clock synchronous serial I/O.
Procedure 1 Stop and initialization of serial I/O operation
b7
b0
Serial I/O control register (SIOCON) [Address 00E216
]
0 0
Transmit operation stop and initialized
Receive operation stop and initialized
Procedure 2 Disabling serial I/O transmit/receive interrupt
b7
b0
Interrupt control register 1 (ICON1) [Address 00FE16
]
0 0
Serial I/O receive interrupt disabled
Serial I/O transmit interrupt disabled
Procedure 3 Setting baud rate generator when BRG output/4 is selechronous clock
Baud rate generator (BRG) [Address 00
Baud rate value is set
Procedure 4 Setting serial I/O control register
b7
b0
Serial I/O control regis) [Address 00E216
]
1 1
BRG count sourc
(valid only whut/4 is selected as synchronous clock)
0: f(XIN)/4
1: f(XIN)/1
Serial ous clock selection
0:
ck input
ut enable selection
SRDY pin is operated as normal I/O pin
17/SRDY pin is operated as SRDY pin (Note 1)
ransmit interrupt source selection (valid only when transmitting)
0: when transmit buffer is empty
1: when transmit shift operation is completed
Transmit enable selection
0: transmit disabled
1: transmit enabled (Note 2)
Receive enable selection
0: receive disabled
1: receive enabled
Clock synchronous serial I/O selected
Serial I/O enabled (P14–P17 are operated as serial I/O pin)
Notes 1: When the following conditions are satisfied, set the transmit enable bit
in addition to the receive enable bit and SRDY output enable bit to ‘1’.
• Half-duplex communication is performed
• External clock is selected as synchronous clock for receive side
• SRDY output is performed.
2: Keep SCLK pin input HIGH when writing transmit enable bit to ‘1’
to select the external clock input as the synchronous clock.
Figure 1.14.13 Setting of Clock Synchronous Serial I/O (1)
7480 Group and 7481 Group User's Manual
1-121
HARDWARE
1.14 Serial I/O
Procedure 5 Setting interrupt when serial I/O transmit/receive interrupt is used (Note 3)
1. ‘0’ is set to serial I/O transmit/receive interrupt request bit
b7
b0
0 0
Interrupt request register 1 (IREQ1) [Address 00FC16]
Serial I/O receive interrupt request bit (when receiving)
Serial I/O transmit interrupt request bit (when transmitting)
2. Serial I/O transmit/receive interrupt is enabled
b7
b0
1 1
Interrupt control register 1 (ICON1) [Address 00FE16
Serial I/O receive interrupt enabled (when receiving)
]
Serial I/O transmit interrupt enabled (when transmitting)
Notes 3: Refer to Handling when overrun error is generated in
(5) Notes on Usage of Clock Synchronous Serial I/O.
Procedure 6 Start of data transmit/receive
Transmit buffer register (TB) [Address 00E016
]
Writing transmit data when transmitting (Note 4)
Writing dummy data when receiving half-duplex on
Notes 4: Keep SCLK pin input HIGH g transmit data to transmit buffer register
to select the external clothe synchronous clock.
Figure 1.14.14 Setting of Clock Synchronl I/O (2)
7480 Group and 7481 Group User's Manual
1-122
HARDWARE
1.14 Serial I/O
(5) Notes on Usage of Clock Synchronous Serial I/O
Pay attention to the following notes when clock synchronous serial I/O is selected.
Selecting External Clock as Synchronous Clock
Perform the following operations while the SCLK pin input is HIGH during transmission:
• Write ‘1’ to the transmit enable bit
• Write transmit data to the transmit buffer register
The shift operations of the transmit shift register and the receive shift register are performed while
the synchronous clock is being input to the serial I/O circuit. Stop the synchronous clock with 8
cycles.
Keep the HIGH- and the LOW- width (TWH and TWL) of the pulses used as the external clock
source TWH, TWL [s] ≥ (8/f(XIN) [Hz]). For example, use a frequency of 500 kHz or less (50% duty
cycle) as the external clock source when f(XIN) = 8 MHz.
Set the transmit enable bit to ‘1’ as well as the receive enable bihe SRDY output enable bit
of the serial I/O control register when the receiver outputs thignal.
Handling Recovering from Errors Generated
Handling when overrun error is generated
If the next data is stored completely word in the ret register before the data transferred
from the receive shift register to the receive buer is read through, the overrun error is
generated. At this time, the overrun error flag summing error flag of the serial I/O status
register are set to ‘1’. The contents of the hift register are not transferred to the receive
buffer register, so that the contents of te buffer register remain unaffected. As a result,
if the contents of the receive buffer re read, the data of the receive shift register is not
transferred to the receive buffer red becomes invalid.
When the overrun error occurs, cverrun error flag to ‘0’ by any of the following operations,
and perform receive preparat.
• Clear the serial I/O enathe serial I/O control register to ‘0’. (In this case, only the
overrun error flag retu.)
• Clear the receive eof the serial I/O control register to ‘0’.
• Write dummy dae serial I/O status register.
Referring to TransShift Completion Flag
The transmit shift completion flag changes from ‘1’ to ‘0’ with a delay of 0.5 to 1.5 clocks of the
synchronous clock. Therefore, pay attention to this delay when data transmission is controlled, by
referring to the transmit shift completion flag after the transmit data is written to the transmit buffer
register.
7480 Group and 7481 Group User's Manual
1-123
HARDWARE
1.14 Serial I/O
Stopping Transmission/Reception of Clock Synchronous Serial I/O
In order to stop the transmit operation in half-duplex transmission, clear the transmit enable bit of
the serial I/O control register to ‘0’. As a result, the following stop and initialization of transmit
operation are performed:
• To stop and initialize the clock supplied to the transmit shift register
• To clear the transmit shift register (Only when ‘0’ is written to the transmit enable bit while the
SCLK pin input is HIGH, selecting an external clock as the synchronous clock.)
• To clear the transmit buffer empty flag and transmit shift completion flag
REASON: Neither stopping transmit operation nor initializing the transmitter circuit is performed
even when the serial I/O enable bit is cleared to ‘0’ (serial I/O disabled), and internal
transmit operation continues. (Because serial I/O pins TxD, RxD, SCLK, and SRDY
function as I/O port pins, transmit data cannot be output to the external.)
In order to stop the receive operation in half-duplex transmission, clear the receive enable bit or
the serial I/O enable bit of the serial I/O control register to ‘0’. As a result, the following stop and
initialization of the receive operation are performed:
• To stop and initialize the clock supplied to the receive shift
• To clear the receive shift register
• To clear every error flag
• To clear the receive buffer full flag
In order to stop the transmit and receive operaull-duplex transmission, clear both the
transmit enable bit and the receive enable bit erial I/O control register to ‘0’ at the same
time. (To stop only one of the transmit or operation cannot be done in the full-duplex
communication of clock synchronous se
REASON: In clock synchronous sehe same clock is used for transmission and reception.
Therefore, transmissiception cannot be synchronized when either transmit or
receive operation d, causing displacement of bit positions.
Re-setting Serial I/O Conister
Re-set the serial I/O coster according to the following sequence:
➀ Clear both the tranreceive enable bits of the serial I/O control register to ‘0’ to stop and
initialize transmceive operations.
➁ Set bits 0 to 3 aof the serial I/O control register.
➂ Set the transmit enable bit or receive enable bit to ‘1’.
(Procedures ➁ and ➂ can be performed simultaneously with the LDM instruction.)
7480 Group and 7481 Group User's Manual
1-124
HARDWARE
1.14 Serial I/O
Using Serial I/O Transmit Interrupt and Serial I/O Receive Interrupt
Set the associated registers in the following sequence to use serial I/O transmit interrupt.
➀ Clear the serial I/O transmit interrupt enable bit of interrupt control register 1 to ‘0’.
➁ Set the serial I/O control register.
➂ Execute one or more instructions such as NOP.
➃ Clear the serial I/O transmit interrupt request bit of interrupt request register 1 to ‘0’.
➄ Set the serial I/O transmit interrupt enable bit of interrupt control register 1 to ‘1’.
REASONS 1: If normal port pins are switched to serial I/O pins with the serial I/O control register,
the serial I/O transmit interrupt request bit may become ‘1’.
2: If the transmit enable bit of the serial I/O control register is set to ‘1’, the transmit
buffer empty flag and the transmit shift completion flag are ‘1’. As a result, the serial
I/O transmit interrupt request bit becomes ‘1’ regardless of the state of the transmit
interrupt source selection bit of the serial I/O control register, and the interrupt
request is generated.
Set the associated registers in the following sequence to use sO receive interrupt.
➀ Clear the serial I/O receive interrupt enable bit of interrupt egister 1 to ‘0’.
➁ Set the serial I/O control register.
➂ Execute one or more instructions, such as NOP.
➃ Clear the serial I/O receive interrupt request bit of request register 1 to ‘0’.
➄ Set the serial I/O receive interrupt enable bit of control register 1 to ‘1’.
REASON: If normal port pins are switched to pins with the serial I/O control register, the
serial I/O receive interrupt requay become ‘1’.
7480 Group and 7481 Group User's Manual
1-125
HARDWARE
1.14 Serial I/O
1.14.3 Clock Asynchronous Serial I/O (UART)
In clock asynchronous serial I/O (UART), the transmit operation of the transmitter and the receive operation
of the receiver are performed simultaneously, synchronizing with the synchronous clock used for transferring,
which is generated by the clock control circuit.
In UART, the transmitter and the receiver have the same transmit/receive baud rate and the same data
transfer format.
UART is selected by clearing the serial I/O mode selection bit of the serial I/O control register to ‘0’.
Data Communication
• Half-duplex communication: one of the two communicating microcomputers operates only as a transmitter
and the other only as a receiver at a time or vice versa.
• Full-duplex communication: both of the two communicating microcomputers operate simultaneously as
transmitter and receiver.
Synchronous Clock
A synchronous clock is selected by the serial I/O synchronous clock selebit of the serial I/O control
register as follows:
• 0: BRG output /16
• 1: External clock/16 input to the SCLK pin
For the BRG output, refer to (5) Baud Rate Generator in 1.14.1.
Notes 1: In UART, the P16/SCLK pin can be used as 16 when the BRG output/16 is selected as
the synchronous clock, since the SCLK pused to output the synchronous clock to the
external.
2: When the external clock/16 is selecsynchronous clock, keep the HIGH- and the LOW-
width (TWH and TWL) of the pulsas the external clock source TWH, TWL [s] ≥ (2/f(XIN)
[Hz]). For example, use a fre2 MHz or less (50% duty cycle) as the external clock
source when f(XIN) = 8 MH
7480 Group and 7481 Group User's Manual
1-126
HARDWARE
1.14 Serial I/O
Data Transfer Rate (Baud Rate)
In UART, the baud rate, which is the frequency of the synchronous clock, is calculated by the following
formulas.
• When the serial I/O synchronous clock selection bit is ‘0’:.
(BRG output/16 is selected as the synchronous clock.)
f(XIN)
Baud rate [bps] =
Division ratio (Note 1) × (BRG setting value (Note 2) + 1) × 16
Notes 1: BRG count source selection bit of the serial I/O control register is as follows:
• ‘0’: Division ratio is 4
• ‘1’: Division ratio is 16.
2: The value written to the baud rate generator (0016 to FF16).
• When the serial I/O synchronous clock selection bit is ‘1’
(the external clock/16 input is selected as the synchronous clock):
External clock input frequency from the SCLK p
Baud rate [bps] =
16
Table 1.14.2 lists an example of baud rates.
Table 1.14.2 Example of Baud Rates
f(XIN) = 3.9936 MHz
Baud Rate
[bps]
f(XIN) = 7.9872 MHz
Count Source
BRG Setting
103 (6
51
)
C16)
(1916)
12 (0C16)
7 (0716)
Count Source
BRG Setting Value
51 (3316)
f(XIN)/16
f(XIN)/16
f(XIN)/16
f(XIN)/16
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/
f(XIN)/
f(XIN)/16
f(XIN)/16
f(XIN)/16
f(XIN)/4
300
25 (1916)
600
1200
12 (0C16)
2400
25 (1916)
4800
f(XIN)/4
12 (0C16)
9600
15600
31200
41600
3 (0316)
2 (0216)
7480 Group and 7481 Group User's Manual
1-127
HARDWARE
1.14 Serial I/O
Data Transfer Formats
In UART, the data transfer formats shown in Figure 1.14.15 can be selected with the UART control register.
LSB
D0
MSB
D7
ST
ST
ST
ST
ST
ST
ST
ST
D1
D1
D1
D1
D1
D1
D1
D1
D2
D2
D2
D2
D2
D2
D2
D2
D3
D3
D3
D3
D3
D3
D3
D3
D4
D4
D4
D4
D4
D4
D4
D4
D5
D5
D5
D5
D5
D5
D5
D6
D6
D6
D6
SP
• 1ST – 8DATA – 1SP
LSB
D0
MSB
D7
SP SP
• 1ST – 8DATA – 2SP
LSB
D0
MSB
D7
PA
SP
• 1ST – 8DATA – 1PA – 1SP
• 1ST – 8DATA – 1PA – 2SP
• 1ST – 7DATA – 1SP
LSB
D0
MSB
D7
PA SP SP
LSB
D0
MSB
D6
SP
LSB
D0
MSB
D6
SP SP
• 1ST – 7DATA – 2SP
LSB
D0
MSB
D
PA
P
• 1ST – 7DATA – 1PA – 1SP
• 1ST – 7DATA – 1PA – 2SP
LSB
D0
SP SP
ST: Start bit
Di(i = 0 to 7): Data bit
PA: Parity bit
SP: Stop bit
Figure 1.14.15 Data Transfer Formats in UART
Table 1.14.3 lists the setting of the UART coster, and Table 1.14.4 lists the function of the UART
data transfer bits.
Table 1.14.3 Setting of UART Contter
UART Control Register
Transfer Data Format
3 (Note 1)
b2 (Note 2)
b1 (Note 3)
b0 (Note 4)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1ST—8DATA—1SP
—
1ST—7DATA—1SP
0: Even parity
1: Odd parity
1ST—8DATA—1PA—1SP
1ST—7DATA—1PA—1SP
1ST—8DATA—2SP
—
1ST—7DATA—2SP
0: Even parity
1: Odd parity
1ST—8DATA—1PA—2SP
1ST—7DATA—1PA—2SP
Notes 1: Stop bit length selection bit
2: Parity selection bit
3: Parity enable bit
4: Character length selection bit
7480 Group and 7481 Group User's Manual
1-128
HARDWARE
1.14 Serial I/O
Table 1.14.4 Function of UART Transfer Data Bits
Name
Function
Start Bit
(ST)
Indicates the start of data transmission. The LOW signal of one-bit wide is added to the
head of the transmit data.
Data Bits
(DATA)
Parity Bit
(PA)
The transmit data written into UART transmit buffer register.
Data ‘0’ represents LOW, and ‘1’ the HIGH signal.
Added to the end of the data bits to enhance the reliability of communications. The number
of ‘1’ in transmit/receive data including parity bit keeps even or odd according to the setting
value of parity selection bit.
Added to the end of the data bits (or after the parity bit if parity is valid) and indicates the
transmission is completed. The HIGH signal of one or two bits wide is output as stop bit.
Stop Bit(s)
(SP)
(1) Block Diagram of UART
Figure 1.14.16 shows the block diagram of UART.
Data bus
P1
4
Address 00E216
control register
Receive enable bit
RxD
(RE)
Address
Receive buffer regis
Overrun error
flag(OE)
ST detection
ve buffer full flag (RBF)
eive interrupt request (RI)
7 bits
8 bits
Receive shift r
Address 00E316
UART control register
Character length
selection bit (CHAS)
on
1/16
Parity error flag (
Framing err
Clock contr
Serial I/O enable bit(SIOE)
Serial I/O synchronous clock selectio
Serial I/O synchronous clock
selection bit (SCS)
S
CLK
IN
BRG count
Division ratio 1/(n + 1)
Baud rate generator
Address 00E416
ST/SP/PA generation 1/16
selection
1/4
X
1/4
Transmit
(TE)
Transmit shift register
Transmit shift completion flag (TSC)
TxD
Transmit interrupt source
selection bit (TIC)
aracter length
ction bit (CHAS)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Transmit buffer register
P16
P15
Address 00E016
Serial I/O status register
Address 00E116
Data bus
Figure 1.14.16 Block Diagram of UART
7480 Group and 7481 Group User's Manual
1-129
HARDWARE
1.14 Serial I/O
(2) Operations of UART Transmission
Transmit Operation
➀ When transmit data is written to the transmit buffer register, the transmit buffer empty flag of the
serial I/O status register is cleared to ‘0’.
➁ The transmit data written to the transmit buffer register is transferred to the transmit shift register.
When the data transfer to the transmit shift register is completed, the transmit buffer empty flag
goes to ‘1’ (Note 1).
➂ Synchronized with a falling edge of the synchronous clock, the start bit (the LOW level) is output
from the TxD pin.
➃ Synchronized with the next falling edge of the synchronous clock, the least significant bit (LSB)
of the transmit data transferred to the transmit shift register is output from the TxD pin. At this time,
the contents of the transmit shift register are shifted to the low-order direction by one bit, and the
serial I/O transmit shift completion flag is cleared to ‘0’.
➄ By repeating the shift operation of ‘Transmit Operation ➃’ ‘n’ times (‘n’: the number of bits set by
the character length selection bit of the UART control register), the transmit data is output from
the TxD pin by the bit from the LSB.
➅ After the transmit data is output, the parity bit, and then the stop he HIGH level), are output
from the TxD pin synchronized with falling edges of the synchrock. The parity bit and the
stop bit are generated and output automatically, according tting of the parity enable bit,
the parity selection bit, and the stop bit length selection e UART control register.
When the last stop bit of the transfer format is outputsmit shift completion flag is set to
‘1’ at the next rising edge of the synchronous cloc).
Notes 1: When the transmit buffer empty flag next transmit data can be written to the
transmit buffer register.
2: The supply of the synchronous clto the transmit shift register stops automatically
upon transmit completion wheG output/16 is selected as the synchronous clock.
However, when the next trata is written to the transmit buffer register during the
‘0’ state of the transmit pletion flag, the supply of the synchronous clock pulse
continues, and data is ively transmitted.
Serial I/O Transmit Interr
In the following cases, I/O transmit interrupt request bit of interrupt request register 1 is
set to ‘1’; then the inquest is generated:
• When the transmpt source selection bit is ‘0’, and the data written to the transmit buffer
register is transfeo the transmit shift register (‘Transmit Operation ➁’).
• When the transmit interrupt source selection bit is ‘1’, and the shift operation of the transmit shift
register is completed (‘Transmit Operation ➅’).
Figure 1.14.17 shows the transmit operation of UART, and Figure 1.14.18 shows a transmit timing
example in UART.
7480 Group and 7481 Group User's Manual
1-130
HARDWARE
1.14 Serial I/O
1
4
Synchronous clock
Data bus
Writing transmit data
16 Transmit buffer register
b0
Address 00E0
D7 D6 D5 D4 D3 D2 D1
D0
P15/TxD
Transmit shift register
1
Serial I/O status register
Address 00E116
1
Serial I/O status register
Address 00E116
0
b0
0
b2
Transmit buffer empty flag
Transmit shift completion flag
2
5
Synchronous clock
16 Transmit buffer register
Address 00E0
b0
Transferring transmit data
Transmit shift register
D7 D6 D5 D4 D3 D2 D1
P15/TxD
Transmit shift register
0
Serial I/O status register
Address 00E116
Synchronous clock
6
1
b0
Transmit buffer empty flag
P15/TxD
0
3
Synchronous clock
Serial I/er
E116
b0
1
b2
D7 D6 D5 D4 D3 D2 D1
D0 ST
P15/TxD
Transmit shift register
Transmit shift completion flag
Figure 1.14.17 Transmit Operation of UART
• Example of 1ST-8DATA-1SP
Synchronous clock
ST
D
0
D
1
D
2
D
6
D
7
SP
TxD pi
Transmit buffer register
write signal
Transmit buffer empty flag
Transmit shift completion flag
(Note 1)
(Note 2)
Serial I/O transmit
interrupt request bit
A
A
: Clearing by writing ‘0’ to the serial I/O transmit interrupt request bit or
accepting a serial I/O transmit interrupt request.
A
Notes 1: When the transmit interrupt source selection bit is ‘0’ (transmit buffer is emptied).
2: When the transmit interrupt source selection bit is ‘1’ (transmit shift operation is completed).
Figure 1.14.18 Transmit Timing example in UART
7480 Group and 7481 Group User's Manual
1-131
HARDWARE
1.14 Serial I/O
(3) Operations of UART Reception
Receive Operation
➀ When a falling edge of the RxD pin input is detected, this input level to the RxD pin is identified
according to the subsequent rising edge of the synchronous clock as follows:
• As the start bit when the level is LOW.
• As noise when the level is HIGH. In this case, the CPU suspends the receive operation and
enters the waiting state for the next start bit.
➁ Synchronized with the rising edge of the synchronous clock, transmitted data is received on the
RxD pin by the bit and stored in the most significant bit (MSB) of the receive shift register. Every
time a data bit is received, the contents of the receive shift register are shifted by one bit to the
low-order direction.
➂ The receive shift operation of ‘Receive Operation ➁’ is performed ‘n’ times (‘n’: the number of bits
set by the character length selection bit of the UART control register), and the received data is
stored completely in the receive shift register (Note 1).
➃ The received data stored completely in the receive shift register is transferred to the receive buffer
register.
➄ The parity bit and the stop bit are input to the RxD pin synchrd with rising edges of the
synchronous clock. When the last stop bit (the HIGH level) ithe RxD pin, the receive
buffer full flag of the serial I/O status register is set to ‘1’ bsequent falling edge of the
synchronous clock (Note 2).
At this time, error flags are checked.
Notes 1: When the character length selection bit its wide), the MSB of the receive buffer
register becomes ‘0’.
2: If the next data is stored completely ceive shift register before the data transferred
from the receive shift register to ive buffer register is read through (the receive
buffer full flag is ‘1’), the overrs generated. At this time, the overrun error flag and
the summing error flag of t/O status register is set to ‘1’. Refer to (5) Notes on
Usage of UART.
When the receive bufer is read, the receive buffer full flag is cleared to ‘0’.
Serial I/O Receive Interru
When the receive buffer goes to ‘1’ (‘Receive Operation ➄’), the serial I/O receive interrupt
request bit of interrut register 1 is set to ‘1’; then the interrupt request is generated.
Figure 1.14.19 shoe receive operation of UART and Figure 1.14.20 shows a receive timing
example in UART.
7480 Group and 7481 Group User's Manual
1-132
HARDWARE
1.14 Serial I/O
1
5
Synchronous clock
RxD (Noise)
Synchronous clock
RxD (SP)
HIGH is identified as noise.
Stop bit detected
LOW is identified as a start bit.
0 0 0 0
0
RxD (ST)
Serial I/O status register
Address 00E116
1
b6 b5 b4 b3
b1
Synchronous clock
2
3
4
Receive buffer full flag
b0
D0
P14/RxD
Receive shift register
Synchronous clock
b0
D3 D2
D1
D0
P14/RxD
Receive shift register
• • •
: b3
b4
Overrun error fto ‘1’ when overrun error occurs.
Parity error t to ‘1’ when parity error occurs.
Framing E); set to ‘1’ when framing error occurs.
Sumag (SE); set to ‘1’ when OE U PE U FE = 1.
• • •
• • •
• • •
b5
Synchronous clock
b6
Receive shift register
Address 00E016
D7 D6 D5 D4 D3 D2
D1
D0
Receive data transfer
Receive buffer register
Figure 1.14.19 Receive Operation of UART
• Example of 1ST-7DATA-1P
Synchronous clock
PA
ST
D0
D1
D2
D6
SP
RxD
Test whether a start bit or not
Reading to the receive shift register
Receive buffer register
read signal
Receive buffer full flag
Serial I/O receive interrupt
request bit
A
: Clearing by writing ‘0’ to the serial I/O receive interrupt request bit or
accepting a serial I/O receive interrupt request.
A
Figure 1.14.20 Receive Timing Example in UART
7480 Group and 7481 Group User's Manual
1-133
HARDWARE
1.14 Serial I/O
(4) Setting of UART
Figures 1.14.21 and 1.14.22 show the setting of UART.
Procedure 1 Stop of serial I/O operation and initialization
b7
b0
Serial I/O control register (SIOCON) [Address 00E216]
0 0
Transmission operation stop and initialized
Receive operation stop and initialized
Procedure 2 Disabling serial I/O transmit/receive interrupt
b7
b0
Interrupt control register 1 (ICON1) [Address 00FE16]
0 0
Serial I/O receive interrupt disabled
Serial I/O transmit interrupt disabled
Procedure 3 Setting baud rate generator when BRG output/16 is selechronous clock
Baud rate generator (BRG) [Address 00E
Baud rate value is set
Procedure 4 Setting serial I/O control register
b7
b0
Serial I/O control reON) [Address 00E216]
0
1
X
BRG count sour
(valid only wput/16 is selected as synchronous clock)
0: f(XIN)/4
1: f(XIN)/
Serianous clock selection
06 (Note 1)
ock input/16
invalid when UART is selected.
mit interrupt source selection (valid only when transmitting)
when transmit buffer is empty
1: when transmit shift operation is completed
Transmit enable selection
0: transmit disabled
1: transmit enabled
Receive enable selection
0: receive disabled
1: receive enabled
Clock asynchronous serial I/O (UART) selected
Serial I/O enabled (P14–P16 are operated as serial I/O pin)
Notes 1: When BRG output/16 is selected as the synchronous clock,
P16/SCLK pin can be used as port pin P16 because the synchronous clock
is not output externally from SCLK pin.
Figure 1.14.21 Setting of UART (1)
7480 Group and 7481 Group User's Manual
1-134
HARDWARE
1.14 Serial I/O
Procedure 5 Setting UART control register
b7
b0
UART control register (UARTCON) [Address 00E316
]
Character length selection
0: 8 bits
1: 7 bits
Parity enable selection
0: Parity disabled
1: Parity enabled
Parity selection (valid only when parity enabled)
0: Even parity
1: Odd parity
Stop bit length selection
0: 1 stop bit
1: 2 stop bits
Procedure 6 Setting interrupt when serial I/O transmit/receive ined (Note 2)
1. ‘0’ is set to serial I/O transmit/receive interrupt request bit
b7
b0
Interrupt request register 1 (IRs 00FC16
]
0 0
Serial I/O receive interrupt when receiving)
Serial I/O transmit interbit (when transmitting)
2. Serial I/O transmit/receive interrupt is enab
b7
b0
Interrupt co1 (ICON1) [Address 00FE16
]
1 1
Serial Iterrupt enabled (when receiving)
Seriit interrupt enabled (when transmitting)
Notes 2: Refer to al I/O Transmit Interrupt and Serial I/O Receive Interrupt
in (5) Usage of UART.
Procedure 7 Start data transmit when transmitting
Transmit buffer register (TB) [Address 00E016
Writing transmit data
]
Figure 1.14.22 Setting of UART (2)
7480 Group and 7481 Group User's Manual
1-135
HARDWARE
1.14 Serial I/O
(5) Notes on Usage of UART
Pay attention to the following notes when UART is selected.
Selecting BRG output/16 as Synchronous Clock
Since the SCLK pin is not used to output the synchronous clock to the external, the P16/SCLK pin can
be used as normal port pin P16.
Selecting External Clock/16 Input as Synchronous Clock
Keep the HIGH- and the LOW- width (TWH and TWL) of the pulses used as the external clock source
TWH, TWL [s] ≥ (2/f(XIN) [Hz]). For example, use a frequency of 2 MHz or less (50% duty cycle) as
the external clock source when f(XIN) = 8 MHz.
Handling Recovering from Errors Generated
Handling when parity error or framing error is generated
When the parity error or the framing error occurs, the flag corresponding to each error and the
summing error flag of the serial I/O status register are set to ‘1’. To cear these flags to ‘0’, perform
either of the following operations.
• Clear the receive enable bit of the serial I/O control registe
• Write dummy data to the serial I/O status register.
Handling when overrun error is generated
If the next data is stored completely in the receive ster before the data transferred from
the receive shift register to the receive buffer regisd through, the overrun error is generated.
At this time, the overrun error flag and the suror flag of the serial I/O status register are
set to ‘1’. The contents of the receive sher are not transferred to the receive buffer
register, so that the contents of the recr register remain unaffected. As a result, if the
contents of the receive buffer register ahe data of the receive shift register is not transferred
to the receive buffer register and invalid.
When the overrun error occurs, coverrun error flag to ‘0’ by any of the following operations
and perform receive preparat.
• Clear the serial I/O enathe serial I/O control register to ‘0’. (In this case, only the
overrun error flag retu.)
• Clear the receive eof the serial I/O control register to ‘0’.
• Write dummy dae serial I/O status register.
Referring to TransShift Completion Flag
The transmit shift completion flag changes from ‘1’ to ‘0’ with a delay of 0.5 to 1.5 clocks of the
synchronous clock. Therefore, pay attention to this delay when data transmission is controlled, by
referring to the transmit shift completion flag after the transmit data is written to the transmit buffer
register.
7480 Group and 7481 Group User's Manual
1-136
HARDWARE
1.14 Serial I/O
Stopping Transmission/Reception of UART
In order to stop the transmit operation of UART, clear the transmit enable bit of the serial I/O
control register to ‘0’. As a result, the following stop and initialization of transmit operation are
performed:
• To stop and initialize the clock supplied to the transmit shift register
• To clear the transmit shift register.
• To clear the transmit buffer empty flag and transmit shift completion flag
In order to stop the receive operation of UART, clear the receive enable bit or the serial I/O enable
bit of the serial I/O control register to ‘0’. As a result, the following stop and initialization of the
receive operation are performed:
• To stop and initialize the clock supplied to the receive shift register
• To clear the receive shift register
• To clear every error flag
• To clear the receive buffer full flag
Re-setting Serial I/O Control Register
Re-set the serial I/O control register according to the following seqstop and initialize transmit
and receive operations:
➀ Clear both of the transmit and receive enable bits of th/O control register to ‘0’.
➁ Set bits 0 to 3 and 6 of the serial I/O control registe
➂ Set both the transmit and receive enable bits to ‘1
(Procedures ➁ and ➂ can be performed simultaneh the LDM instruction.)
Using Serial I/O Transmit Interrupt and SeReceive Interrupt
Set the associated registers in the follouence to use serial I/O transmit interrupt.
➀ Clear the serial I/O transmit interre bit of interrupt control register 1 to ‘0’.
➁ Set the serial I/O control registe
➂ Execute one or more instructas NOP.
➃ Clear the serial I/O transmpt request bit of interrupt request register 1 to ‘0’.
➄ Set the serial I/O transpt enable bit of interrupt control register 1 to ‘1’.
REASONS 1: If normns are switched to serial I/O pins with the serial I/O control register,
the transmit interrupt request bit may become ‘1’.
2: If mit enable bit of the serial I/O control register is set to ‘1’, the transmit
buffmpty flag and the transmit shift completion flag are ‘1’. As a result, the serial
I/O transmit interrupt request bit becomes ‘1’ regardless of the state of the transmit
interrupt source selection bit of the serial I/O control register, and the interrupt
request is generated.
Set the associated registers in the following sequence to use serial I/O receive interrupt.
➀ Clear the serial I/O receive interrupt enable bit of interrupt control register 1 to ‘0’.
➁ Set the serial I/O control register.
➂ Execute one or more instructions, such as NOP.
➃ Clear the serial I/O receive interrupt request bit of interrupt request register 1 to ‘0’.
➄ Set the serial I/O receive interrupt enable bit of interrupt control register 1 to ‘1’.
REASON: If normal port pins are switched to serial I/O pins with the serial I/O control register, the
serial I/O receive interrupt request bit may become ‘1’.
7480 Group and 7481 Group User's Manual
1-137
HARDWARE
1.14 Serial I/O
1.14.4 Bus Arbitration
LAN data bus
In the serial I/O communications of the contention
bus system shown in Figure 1.14.23, transmit data
may not correctly be sent on the transmission line
because of bus collision.
In the 7480 Group and 7481 Group, if the comparison
of the level of serial I/O transmit pin TxD with that
of serial I/O receive pin RxD results in a mismatch,
the bus arbitration interrupt request is generated.
This indicates that the bus collision occurred.
When the bus collision detection enable bit of the
bus collision detection control register is set to ‘1’,
bus collision detection can be performed. In addition,
bus collision detection is valid when any of the
following conditions is selected:
Interface
Driver/
Receiver
TxD
RxD
7480 Group
7481Group
Figure 1.14.23 Contention bus system communications
Serial I/O mode
• Clock synchronous serial I/O
• Clock asynchronous serial I/O (UART)
Synchronous clock
• BRG output divided
• External clock (or external clock/16)
(1) Block Diagram
Figure 1.14.24 shows the block diagram of the ation interrupt.
TxD pin
RxD pin
D
Q
Bus arbitration interrupt request
Synchronous clock
Bus collision detection enable bit
Transmit enable bit
Figure 1.14.24 Block Diagram of Bus Arbitration Interrupt
7480 Group and 7481 Group User's Manual
1-138
HARDWARE
1.14 Serial I/O
(2) Operations of Bus Arbitration
Operations of bus arbitration in the serial I/O communications are described below.
Bus Collision Detection
The level of serial I/O transmit pin TxD is compared with that of serial I/O receive pin RxD, synchronized
with rising edges of the synchronous clock which is used in serial I/O communications.
• The level of 8-bit transmit data is referred for comparison in clock synchronous serial I/O.
• The levels of all transmitted bits, from the start to the stop bits, are referred for comparison in
UART.
Bus Arbitration Interrupt
When a mismatch results from the comparison of the level of the TxD pin with that of the RxD pin
in bus collision detection, the bus arbitration interrupt request bit of interrupt request register 1 is set
to ‘1’; then the interrupt request is generated.
Figure 1.14.25 shows a timing of bus collision detection.
Synchronous clock
TxD pin
RxD pin
Bus arbitration interrupt
request bit
A
Bus arbitration
A
by writing ‘0’ to the bus arbitration interrupt request bit or
ting a bus arbitration interrupt request.
Figure 1.14.25 Timing oollision Detection
7480 Group and 7481 Group User's Manual
1-139
HARDWARE
1.14 Serial I/O
(3) Setting of Bus Arbitration Interrupt
Figure 1.14.26 shows the setting of bus arbitration interrupt.
Procedure 1 Disabling of the acceptance of the interrupts associated serial I/O
b7
b0
Interrupt control register 1 (ICON1) [Address 00FE16
]
0 0 0
Serial I/O receive interrupt disabled
Serial I/O transmit interrupt disabled
Bus arbitration interrupt disabled
Procedure 2 Setting serial I/O full-duplex communication
1. Set Baud Rate Generator when the divided BRG output/4 or 16 is selected as the synchronous clock.
2. Set Serial I/O Control Register (in full-duplex communication).
3. Set UART Control Register (in UART).
Procedure 3 Setting bus collision detection control register
b7
b0
Bus collision detection control register (BUSAddress 00E516
Bus collision detect enabled
]
1
Procedure 4 Setting the using interrupt request bit to ‘
b7
b0
Interrupt request regist[Address 00FC16
]
0 0 0
There is no serial I/O pt request
There is no serial terrupt request
There is no bterrupt request
Procedure 5 Enabling the acche using interrupts
b7
b0
control register 1 (ICON1) [Address 00FE16
]
1 1 1
I/O receive interrupt enabled
rial I/O transmit interrupt enabled
Bus arbitration interrupt enabled
Procedure 6 Writing transmit data into transmit buffer register
Figure 1.14.26 Setting of Bus Arbitration Interrupt
7480 Group and 7481 Group User's Manual
1-140
HARDWARE
1.15 A-D Converter
1.15 A-D Converter
The 7480 Group and 7481 Group have a built-in A-D converter with:
• analog input pins...................... 8 channels (alternative functions of port P2) (Note), and
• conversion system.................... 8-bit successive comparison.
When the A-D converter is not used, power dissipation can be reduced by clearing the VREF connection
selection bit of the A-D control register to ‘0’ and switching off VREF.
Note: In the 7480 Group, 4-channel analog input pins are implemented.
1.15.1 Block Diagram of A-D Converter
Figure 1.15.1 shows the block diagram of the A-D converter.
Data bus
b4
b0
A-D control registe
(Address 00D91
A-D conversion
completion interrupt
request
ol circuit
P20
P21
P22
/IN
/IN
/IN
0
1
2
A-D conversion
register
Com
(Address 00DA16
)
P23
P24
P25
P26
P27
/IN
/IN
/IN
/IN
/IN
3
4
5
6
7
Switch tree
(Note 2)
Ladder resistor
V
SS
(Note 1)
VREF
Notes 1: AVSS for the 44P6N package of the 7481 Group.
2: Port pins P2 /IN –P2 /IN are not implemented in the 7480 Group.
4
4
7
7
Figure 1.15.1 Block Diagram of A-D Converter
7480 Group and 7481 Group User's Manual
1-141
HARDWARE
1.15 A-D Converter
1.15.2 Registers Associated with A-D Converter
Figure 1.15.2 shows the memory map of the registers associated with the A-D converter.
A-D control register (ADCON)
A-D conversion register (AD)
00D916
00DA16
Figure 1.15.2 Memory Map of Registers Associated with A-D Converter
(1) A-D Control Register
The A-D control register consists of the bits controlling the A-D converter.
Figure 1.15.3 shows the A-D control register.
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register (ADCON) [Address 00D9
b
0
Name
on
At reset
0
R
O
W
O
Analog input pin selection bits
P2
: P2
0 0 : P2
1 0 1 : P2
1 1 0 : P2
1 1 1 : P2
1
2
3
4
5
6
7
N
0
1
2
3
4
5
6
7
/IN
/IN
/IN
/IN
/IN
/IN
/IN
O
O
O
O
1
2
0
0
(Note)
3
mpletion bit
0 : Conversion in progress
1 : Conversion completed
1
0
O
O
0 : Disconnect between VREF pin and
ladder resistor
ection selection bit
O
1 : Connect between VREF pin and
ladder resistor
Undefined
Undefined
Undefined
Undefined
×
×
×
Not implemented.
Writing to these bits is disabled.
These bits are undefined at reading.
Undefined
Undefined
6
7
: The bit can be set to ‘0’ by software, but cannot be set to ‘1’.
Note: Do not perform setting in the 7480 Group.
Figure 1.15.3 A-D Control Register
7480 Group and 7481 Group User's Manual
1-142
HARDWARE
1.15 A-D Converter
(2) A-D Conversion Register
This is a read-only register in which an A-D conversion result is stored.
Figure 1.15.4 shows the A-D conversion register.
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address 00DA16]
R
W
At reset
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
defined
b
0
Function
Read-only register to store the A-D conversion result.
×
×
×
×
×
×
×
×
O
O
O
1
2
O
O
3
4
5
O
6
7
O
O
Figure 1.15.4 A-D Conversion Register
7480 Group and 7481 Group User's Manual
1-143
HARDWARE
1.15 A-D Converter
1.15.3 Operations of A-D Converter
The A-D conversion system of the 7480 Group and 7481 Group is successive comparison conversion. The
comparison result of internally generated comparison voltage Vref with input voltage VIN from an analog
input pin is stored in the A-D conversion register.
The operations of the A-D converter are described below.
Start of A-D Conversion
When the A-D conversion completion bit of the A-D control register is cleared to ‘0’, A-D conversion is
started.
A-D Conversion
➀
The A-D conversion register goes to ‘0016’.
➁
Analog input voltage VIN is compared with comparison voltage Vref 8 times. The contents of the A-D
conversion register are determined by the bit from the MSB, each time a comparison is performed.
Comparison voltage Vref is determined by the following formula depending on the contents of the A-
D conversion register and reference voltage VREF, which is input fre VREF pin.
Expression of comparison voltage Vref
Vref =
0 ........................................when n = 0
VREF
256
× (n – 0.5) ...........when n = 1
VREF: Referencinput from the VREF pin
: The cof the A-D conversion register
n
The first comparison (determination of bit conversion register)
Bit 7 of the A-D conversion register is sand comparison voltage Vref obtained by the above
formula is input to the comparator. Vrared with VIN, and bit 7 of the A-D conversion register
is determined, depending on the rhe comparison as follows:
• Bit 7 remains ‘1’ (retention) if IN.
• Bit 7 is converted to ‘0’ if .
Comparison from the se (determination of bits 6 to 0 of A-D conversion register)
Every bit of bits 6 to A-D conversion register is successively determined as bit 7 is done
in the first time. (bit to be determined is set to ‘1’, and the value of the bit is determined
by the comparison rt of VIN with Vref.)
Figure 1.15.5 shows the change of the A-D conversion register and the comparison voltage during
A-D conversion.
➂
A-D conversion is completed when comparison voltage Vref is compared with analog input voltage VIN
8 times and all bits of the A-D conversion register are determined. At this time, the A-D conversion
completion bit of the A-D control register becomes ‘1’.
7480 Group and 7481 Group User's Manual
1-144
HARDWARE
1.15 A-D Converter
The contents of A-D conversion register
Comparison voltage (Vref) [V]
At A-D conversion start
0 0 0 0 0 0 0 0
0
V
V
V
REF
2
V
REF
512
At the first comparison start
At the second comparison start
At the third comparison start
–
±
±
1
0 0 0 0 0 0 0
REF
2
V
REF
4
V
REF
512
–
±
1 1
0 0 0 0 0 0
REF
2
V
V
REF
4
VREF
V
REF
512
–
–
1 2 1 0 0 0 0 0
8
.....
V
REF
2
REF
4
VREF
±
±
±
At the eighth comparison start
8
1 2 3 4 5 6 7 1
.......
V
REF
V
REF
512
256
At A-D conversion completed
(at the eighth conversion completed)
1 2
4 5 6 7 8
3
The digital value corresponding to
analog input voltage
: The determined value obtai-th (m=1 to 8) comparison result
m
Figure 1.15.5 Change of A-D Conversion Register and ison Voltage during A-D Conversion
A-D conversion interrupt
When A-D conversion is completed, the A-D convmpletion interrupt request bit of interrupt request
register 1 is set to ‘1’; then an A-D conversiotion interrupt request is generated.
Reads from A-D conversion register
When A-D conversion is completed, thnversion register is read to obtain the A-D conversion result.
The completion of A-D conversion cknowledged by any of the following conditions:
• The A-D conversion completio’.
• The A-D conversion complerupt request bit is ‘1’.
• The branch to A-D converletion interrupt service routine occurs (when A-D conversion completion
interrupt enabled).
Note: Do not read from the A-D conversion register during A-D conversion operation.
A-D conversion time
A-D conversion ends in 50 cycles after its start. Because the A-D converter uses the clock input divided
by 2, f(XIN)/2, as the operating clock, A-D conversion time is fundamentally obtained by the following
formula:
2
A-D conversion time =
× conversion cycles (50 cycles)
f(XIN)
(12.5 µs at f(XIN) = 8 MHz)
7480 Group and 7481 Group User's Manual
1-145
HARDWARE
1.15 A-D Converter
1.15.4 Setting of A-D Conversion
Figure 1.15.6 shows the setting of A-D conversion.
Procedure 1 Disabling acceptance of A-D conversion completion interrupt
b7
b0
0
Interrupt control register 1 (ICON1) [Address 00FE16]
A-D conversion completion interrupt acceptance disabled
Procedure 2 Setting A-D control register
b7
b0
A-D control register (ADCON) [Address 00D916]
1
Analog input pin selection
000: P20/IN0
001: P21/IN1
010: P22/IN2
011: P23/IN3
100: P24/IN4
101: P25/IN5
110: P26/IN6
111: P27/IN7
(Note 1)
VREF and ladder resistor connected
Procedure 3 Setting A-D conversion completion interrupt req‘0’
b7
b0
0
Interrupt request register 1 (IRss 00FC16]
There is no A-D conversion crupt request.
Procedure 4 Enabling acceptance of interrD conversion interrupt is used
b7
b0
1
Interrupt co1 (ICON1) [Address 00FE16]
A-D cmpletion interrupt acceptance enabled
Procedure 5 Start of A-D (Note 2)
b7
0
ontrol register (ADCON) [Address 00D916]
A-D conversion start
Notes 1: Do not set these bits in the 7480 Group.
2: Start A-D conversion after the following:
➀the ladder resistor is connected to VREF pin
➁VREF stabilization time elapses 1.0 µs or more.
Figure 1.15.6 Setting of A-D Conversion
7480 Group and 7481 Group User's Manual
1-146
HARDWARE
1.15 A-D Converter
1.15.5 Notes on Usage
Pay attention to the following notes when the A-D converter is used.
The comparator consists of a capacitive coupling circuit, so that low clock input frequencies cause
electric charge to be lost.
• Use 1 MHz or more of f(XIN) during A-D conversion is performed.
• Do not execute the STP instruction during A-D conversion.
Voltages to be applied to the reference voltage input pin are as follows:
• VREF = 2 to VCC [V] when VCC = 2.7 V to 4.0 V
• VREF = 0.5 VCC to VCC [V] when VCC = 4.0 V to 5.5 V
When the A-D converter is not used, connect VREF pin to the VCC pin.
Apply the same voltage as to the VSS pin to analog power source voltage input pin AVSS. (The AVSS
pin is dedicated to the 44P6N-A package in the 7481 Group.)
Even when A-D conversion is started, the A-D conversion completion interrquest bit is not automatically
cleared to ‘0’.
Clear this bit to ‘0’ before A-D conversion starts.
A-D conversion resumes when ‘0’ is written into the A-D ccompletion bit of the A-D control
register during A-D conversion.
To start A-D conversion, set the VREF connection n bit of the A-D control register to ‘1’ to
connect ladder resistor and the VREF. A-D convethen be started, after the VREF stabilization
time elapses 1.0 µs or more.
7480 Group and 7481 Group User's Manual
1-147
HARDWARE
1.15 A-D Converter
Figure 1.15.7 shows the internal equivalent circuit of analog input circuit. In order to perform the A-D
conversion correctly, complete the charge to the internal capacitor by the specified time. The maximum
output impedance of analog input source to complete the charge to the internal capacitor by this
specified time is shown below.
About 10 kΩ (at f(XIN) = 8 MHz)
When the maximum value of output impedance is over the above value, take countermeasures, for
example, connect a capacitor (0.1 µF to 1 µF) between analog input pins and VSS.
V
CC
(Note 2)
(Note 2)
R(about 6 Ω)
P2i/INi pin
(i=0 to 7)
(Note 1)
C1 = 10pF ± 50%
C2 (about 3 pF)
SW1(Note 3)
SW2
Amplifier
V
SS
VSS
Reference voltage circuit
istor
V
RE
V
REF
V
SS
Notes 1: In the 7480 Group, i = 0 to 3.
2: This is a parasitic diode of output transistor.
3: SW1 is turned on only when analog input pin is selected.
Figure 1.15.7 Internal eqcircuit of analog input circuit
7480 Group and 7481 Group User's Manual
1-148
HARDWARE
1.16 Watchdog Timer
1.16 Watchdog Timer
If a program cannot run a normal loop by a runaway, etc., the watchdog timer provides the means of
returning the CPU to the reset state.
In the 7480 Group and 7481 Group, invalidating the STP and WIT instructions causes a runaway to be
detected more effectively. For the selection of the valid/invalid of the STP and WIT instructions, refer to
Section 1.19 Power Saving Function.
The watchdog timer is comprised of 7-bit watchdog timer L and 8-bit watchdog timer H (address 00FE16).
1.16.1 Block Diagram of Watchdog Timer
Figure 1.16.1 shows the block diagram of the watchdog timer.
Data bus
‘7F16’ is set when writing to ‘FF16’ is set when writing to
watchdog timer H
watchdog timer H
1/8
‘0’
‘1’
Watchdog timer L
(7 bits)
g timer H
8 bits)
XIN
1/16
bit 7
Watchdog timer L count
source selection bit
Internal reset
cuit
RESET
Figure 1.16.1 Block Diagram of Watchdog Ti
1.16.2 Registers Associated with Watcher
Figure 1.16.2 shows the memory map gisters associated with the watchdog timer.
tchdog timer H (WDTH)
0
CPU mode register (CPUM)
00FB16
Figure 1.16.2 Memory Map of Registers Associated with Watchdog Timer
7480 Group and 7481 Group User's Manual
1-149
HARDWARE
1.16 Watchdog Timer
(1) Watchdog Timer H
Watchdog timer H indicates the high-order 8 bits of the count value of the watchdog timer.
Figure 1.16.3 shows the watchdog timer H.
Watchdog timer H
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer H (WDTH) [Address 00EF16
]
At reset
R
O
O
W
b
Function
The high-order count value of watchdog timer is indicated.
0
1
1
1
2
O
O
1
1
3
4
5
Note
O
O
O
6
7
O
The following value is set by writing arbitrary dat
Note:
• watchdog timer L ← ‘7F16
’
• watchdog timer H ← ‘FF16
’
Figure 1.16.3 Watchdog Timer H
(2) CPU Mode Register
This register consists of the bits that select a ge and an internal clock, as well as the bit that
selects a count source of the watchdog
Figure 1.16.4 shows the CPU mode r
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
de register (CPUM) [Address 00FB16
]
0
R
O
W
0
b
0
1
Name
Function
At reset
0
Fix these bits to ‘0’
0
0
O
O
0
2
O
Stack page selection bit
0 : Zero page
(Note)
1 : 1 page
Watchdog timer L count
source selection bit
0 : f(XIN)/8
1 : f(XIN)/16
O
O
3
4
5
0
×
Undefined
Undefined
Not implemented. Writing to this bit is disabled.
This bit is undefined at reading.
Undefined
×
Undefined
Not implemented. Writing to this bit is disabled.
This bit is undefined at reading.
Clock division
ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (medium-speed mode)
O
O
6
7
0
Undefined
×
Undefined
Not implemented. Writing to this bit is disabled.
This bit is undefined at reading.
Note: In the products whose RAM size is 192 bytes or less, set this bit to ‘0’.
Figure 1.16.4 CPU Mode Register
7480 Group and 7481 Group User's Manual
1-150
HARDWARE
1.16 Watchdog Timer
1.16.3 Operations of Watchdog Timer
The operations of the watchdog timer are described below.
Count Source
The watchdog timer can select the following count sources using watchdog timer L count source selection
bit of the CPU mode register:
• f(XIN)/8 when the bit is ‘0’
• f(XIN)/16 when the bit is ‘1’
Internal Operation
➀ When the write instructions (Note 1) are executed to watchdog timer H, the following values are placed
in watchdog timers H and L, regardless of the written value:
• ‘FF16’ into watchdog timer H
• ‘7F16’ into watchdog timer L
The watchdog timer starts counting by writing to watchdog timer H, and every time the count source is
input, the watchdog timer is decremented by 1.
➁ When bit 7 of watchdog timer H becomes ‘0’ by a down count (Note 2), ternal reset signal changes
from HIGH to LOW and the CPU enters the reset state. As a result, thstate of the microcomputer
is set as shown in Figure 1.17.2 Internal State at Reset in Sectieset. Timer 1 goes to ‘FF16’
to generate the wait time for the system releasing from reshen the watchdog timer starts
counting, using f(XIN)/8 as the count source.
➂ When an underflow occurs in timer 1, the internal reset sigsed to the HIGH state and the system
is released from reset. The program is executed at ths stored in the reset vector area.
Notes 1: Write instructions which generate write sch as STA, LDM, and CLB.
2: The time from writing data into watchdH to placing ‘0’ in bit 7 is 16384 (400016) cycles
of the count source.
Examples
At f(XIN) = 8 MHz :
• 16.384 ms; when the freqthe count source is f(XIN)/8
• 32.768 ms; when the frof the count source is f(XIN)/16
Figure 1.16.5 shows the interssing sequence during reset by the watchdog timer.
7480 Group and 7481 Group User's Manual
1-151
HARDWARE
1.16 Watchdog Timer
XIN pin
Internal clock φ
2048 cycles of XIN pin input signal
Internal reset signal
Address bus
Data bus
FFFE16 FFFF16
AL,AH
AL
AH
SYNC pin
Bit 7 of Watchdog Timer H
changes from ‘1’ to ‘0’.
Internal Clock φ :
Basic clock frequency of CPU, f(XIN)/2 (high-speed mode) aftreleased from reset.
AH, AL :
Jump addresses stored in reset vector area.
SYNC :
:
CPU opcode fetch cycle (it cannot be examined externais an internal signal).
Undefined
Figure 1.16.5 Internal Processing Sequence during RWatchdog Timer
Countermeasures with Watchdog Timer against y
Watchdog timer H is written to with the main ro, to keep bit 7 from going to ‘0.’ (keep it at ‘1’).
In case of a program runaway by noise, watcr H is not written to, so that bit 7 becomes ‘0’ and
the CPU returns to the reset state.
Operations in Stop and Wait Mode
• When the STP instruction is exeenter the stop mode, the f(XIN) stops, causing the watchdog
timer to stop counting. When tode is terminated, the watchdog timer starts counting in response
to the restarting of f(XIN) o
• When the WIT instruction ed to enter the wait mode, CPU stops operating, whereas the watchdog
timer continues countse the oscillation of f(XIN) does not stop.
Note: The watchdog timer continues counting even during the oscillator start-up stabilization time (2048
cycles of the XIN pin input signal) after the stop mode is terminated, and the wait mode. Write to
watchdog timer in order to prevent bit 7 of watchdog timer H from going to ‘0’.
In the 7480 Group and 7481 Group, the valid/invalid of the STP and WIT instructions can be selected.
Invalidating these instructions causes a runaway to be detected more effectively when the watchdog timer
is used.
For details on the setting of the valid/invalid of the stop and wait modes and the STP and WIT instructions,
refer to Section 1.19 Power Saving Function.
7480 Group and 7481 Group User's Manual
1-152
HARDWARE
1.16 Watchdog Timer
1.16.4 Setting of Watchdog Timer
Figure 1.16.6 shows the setting of the watchdog timer.
Procedure 1 Selecting watchdog timer L count source
b7
b0
CPU mode register (CPUM) [Address 00FB16
]
0 0
Watchdog timer L count soure selection
0: f(XIN)/8
1: f(XIN)/16
Procedure 2 Writing to watchdog timer H (Note 1)
Watchdog timer H (WDTH) [Address 00EF16
Arbitrary data (Note 2)
]
FF16
Notes 1: Writing to watchdog timer H starts counting.
2: The following values are set regardless of writte
• Watchdog Timer L ← ‘7F16
’
• Watchdog Timer H ← ‘FF16
’
Note: Internal reset occurs if bit 7 of watchdog timer ’. Therefore, write to watchdog timer H
in the main routine in order to prevent bit 7 omer H from going to ‘0’.
Since the timer counts for the start-up sta(2048 cycles of the XIN pin input signal),
bit 7 of watchdog timer H must not be ‘period.
Figure 1.16.6 Setting of Watchdog Timer
1.16.5 Notes on Usage
Pay attention to the following notes when hdog timer is used.
Write to watchdog timer in the maiin order to prevent bit 7 of watchdog timer H from going to
‘0’.
The watchdog timer contining even during the oscillator start-up stabilization time (2048 cycles
of the XIN pin input signe stop mode is terminated, and the wait mode. Write to watchdog timer
in order to prevent bitchdog timer H from going to ‘0’.
Do not operate the watchdog timer during system evaluation.
7480 Group and 7481 Group User's Manual
1-153
HARDWARE
1.17 Reset
1.17 Reset
When the LOW level is applied to the RESET pin for 2 µs or more, the internal reset signal becomes LOW,
and the CPU enters the reset state. Subsequently, when the HIGH level is applied to the RESET pin, the
internal reset signal becomes HIGH, and the system is released from reset after the oscillator start-up
stabilization time (Note) elapses. The program is resumed at the jump address stored in the reset vector
area after the system is released from reset.
In the 7480 Group and 7481 Group, even when bit 7 of watchdog timer H changes from ‘1’ to ‘0’, the internal
reset signal changes from HIGH to LOW, causing the CPU to enter the reset state. For details of the
watchdog timer, refer to Section 1.16 Watchdog Timer.
Note: 2048 cycles of the XIN pin input signal (counted by timer 1).
For an example of reset circuits, refer to Section 2.5 Reset.
7480 Group and 7481 Group User's Manual
1-154
HARDWARE
1.17 Reset
1.17.1 Reset Operations
The reset operations are described below.
➀ When the power source voltage is within specifications (Note) and clock input oscillation frequency f(XIN)
is stabled, the internal reset signal changes from HIGH to LOW by applying the LOW level to the RESET
pin for 2 µs or more, causing the CPU to enter the reset state.
➁ Then the HIGH level is applied to the RESET pin, so that the internal state of the microcomputer is set,
as shown in Figure 1.17.2 Internal State at Reset. Timer 1 goes to ‘FF16’ to generate the f(XIN)
oscillator start-up stabilization time and then starts counting, using f(XIN)/8 as the count source.
➂ When an underflow occurs in timer 1, the internal reset signal becomes HIGH and the system is released
from reset. The program is resumed at the address stored in the reset vector area.
Note: • 2.7 V to 4.5 V at f(XIN) = (2.2 VCC–2) MHz
• 4.5 V to 5.5 V at f(XIN) = 8 MHz
Figure 1.17.1 shows the internal processing sequence after reset release.
VCC
XIN pin
φ
Internal clock
2 µs or more
RESET
2048 cycles of XIN ignal
Internal reset
Address bus
FFFE16 FFFF16
AL,AH
Data bus
SYNC pin
AL
AH
Internal clock
,
SYN
φ
ock frequency of CPU = f(XIN)/2
addressesstored in reset vector area
PU opcode fetch cycle
A
H
(it cannot be examined externally because it is an internal signal)
: Undefined
Figure 1.17.1 Internal Processing Sequence after Reset Release
7480 Group and 7481 Group User's Manual
1-155
HARDWARE
1.17 Reset
1.17.2 Internal State at Reset
Figure 1.17.2 shows the internal state at reset.
Address
Contents of register
b7
b0
(1) Port P0 direction register (P0D)
(2) Port P1 direction register (P1D)
(3) Port P4 direction register (P4D)
(4) Port P5 direction register (P5D)
00C116
00C316
00C916
00CB16
00D016
00D116
00D216
00D416
00D916
0016
0016
0 0 0 0
0 0 0 0
Port P0 pull-up control register (P0PCON)
Port P1 pull-up control register (P1PCON)
Port P4P5 input control register (P4P5CON)
(5)
(6)
(7)
0016
0 0
0016
(8) Edge polarity selection register (EG)
(9) A-D control register (ADCON)
(10) STP instruction operation control register (STPCON)
(11) Serial I/O status register (SIOSTS)
(12) Serial I/O control register (SIOCON)
(13) UART control register (UARTCON)
(14) Bus collision detection control register (BUSARBCON)
(15) Watchdog timer H (WDTH)
0
0 0 0 0
0 0 0
00DE16 0 0
00E116 1 0 0
00E2
16
01 1 0 0 0 0
16
00F016
00F116
00F216
00F316
00F416
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
0016
FF16
(16) Timer X low-order (TXL)
FF16
(17) Timer X high-order (TXH)
FF16
(18) Timer Y low-order (TYL)
FF16
(19) Timer Y high-order (TYH)
FF16
(20) Timer 1 (T1)
FF16
(21) Timer X mode register (
(22) Timer Y mode regis
(23) Timer XY contrXYCON)
(24) Timer 1 mT1M)
(25) Timer 2 mter (T2M)
(26) CPU mode register (CPUM)
0016
0016
0 0 0 0 0 0
0016
1 1
0016
0
0 0 0 0
(27) Interrupt request register 1 (IREQ1)
(28) Interrupt request register 2 (IREQ2)
(29) Interrupt control register 1 (ICON1)
(30) Interrupt control register 2 (ICON2)
0016
0 0 0
0
0016
0 0 0 0
(31) Program counter (PC
H)
Contents of FFFF16
Contents of FFFE16
(PC
L
)
(32) Processor status register (PS)
: Read back as undefined at reset.
1
Note: Since the contents of the registers and RAM not mentioned above are undefined at reset,
initialize them by software.
There are bits not implemented for some products.
For these bits, refer to each register.
Figure 1.17.2 Internal State at Reset
7480 Group and 7481 Group User's Manual
1-156
HARDWARE
1.17 Reset
1.17.3 Notes on Usage
Pay attention to the following notes when reset is used.
Internal clock φ becomes f(XIN)/2 (high-speed mode) when the system is released from reset.
Timer 1 and timer 2 are counting when the system is released from reset.
Apply 0.32 V or less to the RESET pin at the time that power source voltage passes 2.7V, at power on.
When the STP instruction is executed in normal operations, I/O port pins retain the states immediately
before internal clock φ stops. If the CPU is then forced to the reset state from the stop mode, the I/O
pins go to the input mode with the high-impedance state.
7480 Group and 7481 Group User's Manual
1-157
HARDWARE
1.18 Oscillation Circuit
1.18 Oscillation Circuit
The 7480 Group and 7481 Group are equipped with a built-in clock generator providing the clock necessary
for operation of the microcomputer. An oscillation circuit is constructed by connecting a ceramic resonator
between the XIN and XOUT pins (Note 1). Also, an external clock can be supplied to the clock generator (Note
2).
The built-in feedback resistor connected between the XIN and XOUT pins allows the user to omit an external
resistor.
Notes 1: For an example of an oscillation circuit using a ceramic resonator, refer to Section 2.6 Oscillation
Circuit. Consult the manufacturer of the resonator for the oscillator start-up stabilization time.
2: Also, for an external clock circuit, refer to Section 2.6 Oscillation Circuit. Use a 50% duty cycle
pulse signal as the external clock input to the XIN pin. At this time, leave the XOUT pin open.
1.18.1 Block Diagram of Clock Generator
The clock generator controls the oscillation circuit. The generated clock (internal clock φ) is supplied to the
CPU and the peripherals.
Figure 1.18.1 shows the block diagram of the clock generator.
X
OUT
X
IN
1/2
1/4
mer 1
Clock dividing rbit
φ
Internal clock
1/4
Q
S
R
Q
Q
S
S
R
Reset
STP instruction
T
tion
STP
instruction
R
Reset
Interrupt disable flag
Interrupt request
Figure 1.18.1 Block Diagram of Clock Generator
7480 Group and 7481 Group User's Manual
1-158
HARDWARE
1.18 Oscillation Circuit
1.18.2 Register Associated with Oscillation Circuit
Figure 1.18.2 shows the memory map of the register associated with the oscillation circuit.
CPU mode register (CPUM)
00FB16
Figure 1.18.2 Memory Map of Register Associated with Oscillation Circuit
The CPU mode register consists of the bits that select a stack page and an internal clock, as well as the
bit that selects a count source of the watchdog timer.
Figure 1.18.3 shows the CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address 00
0 0
R
O
W
0
b
0
1
Name
ction
At reset
Fix these bits to ‘0’.
0
0
0
O
O
0
2
O
Stack page sel
: Zero page
(Note)
1 : 1 page
Watchdot
sourc
0 : f(XIN)/8
1 : f(XIN)/16
O
O
3
4
0
×
Undefined
Undefined
d. Writing to this bit is disabled.
defined at reading.
Undefined
×
Undefined
emented. Writing to this bit is disabled.
it is undefined at reading.
lock division
ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (medium-speed mode)
O
O
7
0
Undefined
×
Undefined
Not implemented. Writing to this bit is disabled.
This bit is undefined at reading.
Note: In the products whose RAM size is 192 bytes or less, set this bit to ‘0’.
Figure 1.18.3 CPU Mode Register
7480 Group and 7481 Group User's Manual
1-159
HARDWARE
1.18 Oscillation Circuit
1.18.3 Oscillation Operations
(1) Oscillation Operations
The following clocks can be selected as internal clock φ by the clock division ratio selection bit of
the CPU mode register.
• XIN pin input divided by 2 (high-speed mode) when the bit is ‘0’.
• XIN pin input divided by 8 (medium-speed mode) when the bit is ‘1’.
Note: The oscillation circuit is held in the high-speed mode after the system is released from reset.
(2) Oscillation in Stop Mode
When the STP instruction is executed to enter the stop mode, internal clock φ stops in the HIGH
state, and the oscillation of f(XIN) stops, as well. At this time, timer 1 goes to ‘FF16’, and f(XIN)/8 is
selected as the count source.
CPU returns from stop mode by reset or accepting an external interrupt request (Note 1). In this time,
internal clock φ is not supplied to the CPU until an underflow occurs in timer 1, though the oscillation
of f(XIN) and internal clock φ are started. The reason is that oscillart-up stabilization time is
required when an external resonator is used.
Note: Activate timer 1 and disable the acceptance of a tterrupt request before the STP
instruction is executed.
Notes 1: For interrupt sources that can be used to om the stop mode, refer to Table 1.11.2
Interrupt Sources Available for CPUn from Stop/Wait Mode.
For details of the stop mode, refer to Sec.2 Stop Mode.
(3) Oscillation in Wait Mode
When the WIT instruction is executer the wait mode, only internal clock φ stops in the HIGH
state.
When the CPU returns from mode by reset or accepting an interrupt request (Note 2), the
supply of internal clock φ U is resumed. Since f(XIN) continues oscillation during the wait
mode, instructions can ted immediately after the CPU returns from the wait mode.
Notes 2: For interces that can be used to return from the wait mode, refer to Table 1.11.2
Interrupt ces Available for CPU’s Return from Stop/Wait Mode.
For details of the wait mode, refer to Section 1.19.3 Wait Mode.
7480 Group and 7481 Group User's Manual
1-160
HARDWARE
1.18 Oscillation Circuit
1.18.4 Oscillator Start-Up Stabilization Time
Oscillation is unstable immediately after oscillation is started in the oscillation circuit which uses a ceramic
resonator. Necessary time for stabilizing oscillation is called an oscillator start-up stabilization time.
The oscillator start-up stabilization time necessitated varies with the structure of the oscillation circuit used.
Consult the manufacturer of the resonator for the oscillator start-up stabilization time.
(1) Oscillator Start-Up Stabilization Time at Power On
The oscillator start-up stabilizing time of 2048 cycles of the XIN pin input signal is automatically
generated after the system is released from reset by timer 1 in the 7480 Group and 7481 Group
(Note).
Note: Timer 1 goes to ‘FF16’ to select f(XIN)/8 as the count source.
Figure 1.18.4 shows an oscillator start-up stabilization time at power on.
2.7 V (Note)
V
CC
2 µs or more
RESET pin
XIN
Oscillator station time
2048 cyin input signal
Internal reset
Internal reset released
Note: At f(XIN) = (2.2 VCC
Apply 0.32 V or lSET pin at the time that power source voltage passes 2.7 V.
Figure 1.18.4 Oscillator Startilization Time at Power On
(2) Oscillator Start-Uzation Time after Stop Mode
Oscillation stops in op mode. When the CPU returns from the stop mode by reset or accepting
an interrupt request, the oscillator start-up stabilization time of 2048 cycles of the input signal to the
XIN pin is automatically generated by timer 1, as occurs at power on.
1.18.5 Notes on Usage
Pay attention to the following notes when an oscillation circuit is used.
The oscillation circuit is held in the high-speed mode after the system is released from reset.
When a ceramic resonator is connected between the XIN and XOUT pins, consult the manufacturer of the
resonator for the oscillator start-up stabilization time.
When an external clock is input to the XIN pin, use a 50% duty cycle pulse signal as the external clock
input to the XIN pin. At this time, leave the XOUT pin open.
Activate timer 1 and disable the acceptance of a timer 1 interrupt request before the STP instruction is
executed.
7480 Group and 7481 Group User's Manual
1-161
HARDWARE
1.19 Power Saving Function
1.19 Power Saving Function
The 7480 Group and 7481 Group are provided with the function to halt the CPU operation and make it stand
by in the following two power saving modes by software:
• Stop mode with the STP instruction
• Wait mode with the WIT instruction
Also, the valid/invalid of the STP and WIT instructions can be selected with the STP instruction operation
control register.
Table 1.19.1 lists the states of the microcomputer in the power saving modes.
Figure 1.19.1 shows the transitions from the power saving modes.
Table 1.19.1 States of Microcomputer in Power Saving Modes
Stop Mode
Stopped
Wait Mode
Operating
Clock f(XIN)
Internal Clock φ
CPU
Suspended at the HIGH level Suspended at the HIGH level
Stopped
Stopped
Retains the state at
instruction exec
etains the state at WIT
instruction execution
I/O Ports
Event Count Mode
Opera
topped
Operating
(external clock as count source)
Other Modes
Operating
Operating
Timers
(divided main clock as count source)
Divided BRG output as synchronous
clock
Serial I/O
RAM
External clock or its 1/16 a
synchronous clock
Retains the state at STP
instruction execution
Retains the state at WIT
instruction execution
Used to generate oscillator
start-up stabilization time
Retains the state at STP
instruction execution
Registers associatemer 1
Other registe
Retains the state at WIT
SFR
instruction execution
Retains the state at STP
instruction execution
Retains the state at WIT
CPU Internal Registers
instruction execution
(Note)
Note: The CPU internal registers are composed of the following six registers:
• Accumulator
• Index register X
• Index register Y
• Stack pointer
• Program counter
• Processor status register
7480 Group and 7481 Group User's Manual
1-162
HARDWARE
1.19 Power Saving Function
Stop mode
Wait mode
Interrupt request
accepted
Interrupt request
accepted
Reset input
Reset input
Only RAM retained
and other registers
are in the reset state
RAM and the registers
except timer 1 retained
RAM and the registers
retained
Oscillator start-up
Oscillator start-up
No oscillator start-up stabilization time
stabilization time
2048 cycles of XIN pin
input signal
stabilization time
2048 cycles of XIN pin
input signal
System is released from reset
Interrupt service
routine executed
Program executed at
the address stored in
reset vector areas
The next address following
STP or WIT instruction
(program execution continued)
Figure 1.19.1 Transitions from Power Saving Mode
7480 Group and 7481 Group User's Manual
1-163
HARDWARE
1.19 Power Saving Function
1.19.1 Registers Associated with Power Saving
Figure 1.19.2 shows the memory map of the registers associated with power saving.
Edge polarity selection register (EG)
00D416
00DE16
STP instruction operation control register (STPCON)
Figure 1.19.2 Memory Map of Registers Associated with Power Saving
(1) STP Instruction Operation Control Register
The STP instruction operation control register has only one bit thts the valid/invalid of the
STP and the WIT instruction.
Figure 1.19.3 shows the STP instruction operation control re
STP instruction operation control register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
STP instruction operation (STPCON) [Address 00DE16]
b
R
O
W
O
Function
At reset
1
Na
STP and lid
select
0 : STP/WIT instruction valid
1 : STP/WIT instruction invalid
0
×
×
1
0
0
0
0
Nd.
se bits is disabled.
are ‘0’ at reading.
2
×
×
×
0
0
0
0
0
0
7
×
×
0
0
0
0
e: The STP and WIT instructions are invalid after the system is released from reset. When
using these instructions, set STP and WIT valid/invalid selection bit of the STP instruction
operation control register to ‘1’, then set this bit to ‘0’. (Writing twice successively)
When not using the STP and WIT instructions, set this bit to ‘1’ either once or twice.
Figure 1.19.3 STP Instruction Operation Control Register
7480 Group and 7481 Group User's Manual
1-164
HARDWARE
1.19 Power Saving Function
(2) Edge Polarity Selection Register
The edge polarity selection register consists of the bits that select the polarity of the valid edge of
INT and CNTR pins, as well as the bit that selects the valid/invalid of key-on wakeup.
Figure 1.19.4 shows the edge polarity selection register.
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0
Edge polarity selection register (EG) [Address 00D416
]
b
Function
Name
edge
R
O
W
O
At reset
0
0
INT
0
0 : Falling edge
1 : Rising edge
selection bit
1
2
0
0
O
O
O
O
INT
selection bit
1
edge
0 : Falling edge
1 : Rising edge
0: In event count mode, rising edge counte
: In pulse output mode, operation starte
at HIGH level output.
CNTR edge
selection bit
0
:
In pulse period measurement mode, a
from falling edge until falling edge m
: In pulse width measuremen
HIGH-level period measu
: In programmable one-de,
one-shot HIGH pufter
operation started output.
: Interrupt requeby detecting
falling edge
1: In event cling edge counted.
: In pulsoperation started
at Lt.
3
0
CNTR
selection bit
1
edge
O
O
:
In surement mode, a period
until rising edge measured.
dth measurement mode,
el period measured.
grammable one-shot output mode,
-shot LOW pulse generated after
peration started at HIGH level output.
: Interrupt request is generated by detecting
rising edge.
Undefined
mented. Writing to this bit is disabled.
is undefined at reading.
Undefined
×
O
O
0
T
selection bit at 1 : P0
STP or WIT
1
source
0 : P3
1
/INT
1
0
–P0
7
LOW level
(for key-on wake-up)
Undefined
Undefined
6
7
Undefined
Undefined
×
×
Not implemented. Writing to these bits are disabled.
These bits are undefined at reading.
Note: When setting bits 0 to 3, the interrupt request bit may be set to ‘1’.
After setting the following, enable the interrupt.
➀Disable interrupts
➁Set the edge polarity selection register
➂ Set the interrupt request bit to ‘0’
Figure 1.19.4 Edge Polarity Selection Register
7480 Group and 7481 Group User's Manual
1-165
HARDWARE
1.19 Power Saving Function
1.19.2 Stop Mode
(1) Operations in Stop Mode
State in Stop Mode
When the STP instruction is valid, its execution causes the CPU to enter the stop mode. In this
mode, the CPU operation is halted because internal clock φ stops in the HIGH state. In addition, the
operation of the peripherals stops as well, because the oscillation of f(XIN) stops. As a result, power
dissipation can be reduced.
Timer 1 goes to ‘FF16’ to generate the oscillator start-up stabilization time necessary for terminating
the stop mode, and a frequency of f(XIN)/8 is selected as the count source.
Note: Timers continue counting in the event count mode, as done the serial I/O does when the
external clock (or its 1/16) is selected as the synchronous clock.
For the operations in the stop mode, refer to Table 1.19.1 States of Microcomputer in Power
Saving Modes.
The stop mode is terminated by reset or accepting an interrupt reqand the CPU returns to the
normal mode.
The operation at recovery from the stop mode by reset or aan interrupt request is described
below.
Recovery from Stop Mode by Reset Input
➀ By applying the LOW level to the RESET pin or more in the stop mode, the CPU enters
the reset state and is brought out of the e, causing the XIN oscillation to resume.
➁ When the RESET pin is restored to thevel, the oscillator start-up stabilization time is
generated by timer 1.
➂ After the oscillator start-up stabilie elapses, internal clock φ is supplied to the CPU.
➃ The program is executed at thstored in the reset vector area.
Figure 1.19.5 shows the oprecovery from the stop mode by reset input.
φ
Note: 2 cycles of internal clock
STP inson
executed
Stop mode is terminated
by reset input
Stop mode
V
CC
2 µs
or more
RESET
STP instruction execution cycle (Note)
Undefined
X
IN pin
XIN pin : High-impedance state Oscillation start-up stabilization time
Internal reset
2048 cycles of XIN pin input signal
Figure 1.19.5 Operation at Recovery from Stop Mode by Reset Input
For details of reset, refer to Section 1.17 Reset.
7480 Group and 7481 Group User's Manual
1-166
HARDWARE
1.19 Power Saving Function
Recovery from Stop Mode by Interrupt
➀ The stop mode is terminated and the XIN oscillation is resumed when an interrupt request is
generated and its interrupt is acceptable in the stop mode.
➁ Next, the oscillator start-up stabilization time is generated by timer 1. After the oscillator start-up
stabilization time elapses, internal clock φ is resumed and supplied to the CPU.
➂ The interrupt request used to terminate the stop mode is accepted and the interrupt service routine
is executed.
➃ After the interrupt service routine is completed, the program is executed at the instruction following
the STP instruction.
Note: The state of timer 1 is affected by recovering from the stop mode.
The interrupt sources used for recovery from the stop mode are as follows:
• INT0, INT1
• CNTR0, CNTR1
• Serial I/O (only when external clock (or its 1/16) is selected as the synchronous clock)
• Timer X and timer Y (only in event count mode)
• Key inputs (in key-on wakeup)
Figure 1.19.6 shows an operation example at recovery frop mode by the INT0 interrupt.
• INT
0
interrupt is used for recovery from st(rising edge detected)
STP instruction
executed
INT0 interrupt
request accepted
Stop ated
b
STP instruction execution
cycle (Note 1)
Oscillation start-up stabilization time
2048 cycles of XIN pin input signal
Stop
XIN
High-impedance state
INT
0
pin input
FF16
RL
Counting down
Contents of timer 1
0016
UF
INT0 interrupt
request bit
Peripheral device
Operating
Operating
Operating
Stop (Note 2)
CPU
Stop
Operating
RL : Reload
UF : Underflow
φ
Notes 1: 2 cycles of internal clock
2: Timer operates in event count mode.
Serial I/O operates when the external clock input (or its 1/16) is
used as the synchronous clock.
Figure 1.19.6 Operation Example at Recovery from Stop Mode by INT0 Interrupt
7480 Group and 7481 Group User's Manual
1-167
HARDWARE
1.19 Power Saving Function
(2) Transition to Stop Mode
The transition from the normal mode to the stop mode is described below.
Recovery from Stop Mode by Reset Input
Execute the STP instruction while the STP instruction is valid.
Recovery from Stop Mode by Accepting Interrupt Request
Execute the STP instruction while the STP instruction is valid after the following sequence is completed:
• Set the interrupt that is used to terminate the stop mode.
• Clear the timer 1 interrupt enable bit to ‘0’ (disabled).
• Clear the timer 1 stop control bit to ‘0’ (count operation).
For the setting of the valid/invalid of the STP instruction, refer to Section 1.19.4 Setting of Valid/
Invalid of STP and WIT Instructions.
1.19.3 Wait Mode
(1) Operations in Wait Mode
State in Wait Mode
When the WIT instruction is valid, its execution causes thenter the wait mode. In this mode,
internal clock φ stops, though f(XIN) continues oscilla result, the CPU is halted but the
peripherals continue to operate.
For the operations in the wait mode, refer to 9.1 States of Microcomputer at Power
Saving Modes.
The wait mode is terminated by reset or aan interrupt request, and the CPU returns to the
normal mode.
The operation at recovery from the e by reset or accepting an interrupt request is described
below.
Recovery from Wait Modset Input
➀ By applying the LOW the RESET pin for 2 µs or more in the wait mode, the CPU enters
the reset state anght out of the wait mode.
➁ When the RESrestored to the HIGH level, the oscillator start-up stabilization time is
generated by time
➂ After the oscillator start-up stabilization time elapses, internal clock φ is supplied to the CPU.
➃ The program is executed at the address stored in the reset vector area.
For details of reset, refer to Section 1.17 Reset.
Recovery from Wait Mode by Interrupt
➀ The wait mode is terminated, when an interrupt request is generated and its interrupt is acceptable
in the wait mode.
➁ Next, internal clock φ is resumed and supplied to the CPU.
➂ The interrupt request used to terminate the wait mode is accepted and the interrupt service routine
is executed.
➃ After the interrupt service routine is completed, the program is executed at the instruction following
the WIT instruction.
All interrupt sources except the BRK instruction interrupt, are available for recovering from the wait
mode.
7480 Group and 7481 Group User's Manual
1-168
HARDWARE
1.19 Power Saving Function
(2) Transition to Wait Mode
The transition from the normal mode to the wait mode is described below.
Recovery from Wait Mode by Reset Input
Execute the WIT instruction while the WIT instruction is valid.
Recovery from Wait Mode by Accepting Interrupt Request
Execute the WIT instruction while the WIT instruction is valid after the interrupt for terminating the
wait mode is set.
For the setting of the valid/invalid of the WIT instruction, refer to Section 1.19.4 Setting of Valid/
Invalid of STP and WIT Instructions.
1.19.4 Setting of Valid/Invalid of STP and WIT Instructions
In the 7480 Group and 7481 Group, the valid/invalid of the STP and WIT instructions can be selected with
the STP instruction operation control register. The STP and the WIT instruction are invalid after the system
is released from reset to prevent the program from a runaway.
Writing twice successively to the STP instruction operation control rekes the STP and the WIT
instruction valid, while non-successive writing to the register (for a single write) makes these
instructions invalid. As the STP and the WIT instruction remain ter the system is released from
reset, successive writing is used to prevent the clock oscillstopping due to erroneous data
written during a program runaway.
Figure 1.19.7 shows the setting of valid/invalid of the d WIT instructions.
Procedure 1 Setting interrupt disable flag or status register to ‘1’ (interrupt disabled)
Procedure 2 Setting STP instration control register (twice successive writing) (Note 1)
1. A write of ‘1’
b7
P instruction operation control register (STPCON) [Address 00DE16
STP and WIT instructions invalid
]
2. Selection of valid/invalid of STP and WIT instructions (Note 2)
b7
b0
STP instruction operation control register (STPCON) [Address 00DE16
]
STP and WIT valid/Invalid selection
0: Valid
1: Invalid
Notes 1: A single write to the STP instruction operation control register makes the STP
and WIT instructions invalid.
2: If invalidating the STP and WIT instructions, the second write can be omitted.
Procedure 3 Clearing interrupt disable flag of processor status register to ‘0’ (interrupt enabled)
when using interrupts.
Figure 1.19.7 Setting of Valid/Invalid of STP and WIT Instructions
7480 Group and 7481 Group User's Manual
1-169
HARDWARE
1.19 Power Saving Function
1.19.5 Notes on Usage
Pay attention to the following notes when the power saving function is used.
(1) Setting of Valid/Invalid of STP and WIT Instructions
To make the STP and the WIT instruction valid, write twice successively to the STP instruction
operation control register while interrupts are disabled.
REASON: Execution of an interrupt service routine may cause this register not to be successively
written.
(2) In Stop Mode
After the CPU is brought out of the stop mode, timer 1 operates in the following conditions. Re-set
timer 1 if necessary.
• Contents of the timer 1 latch: ‘FF16’
• Count source: f(XIN)/8
Since the A-D converter stops in the stop mode, execute the STP ction after A-D conversion
is completed.
In the stop mode, timer X and timer Y continue counting e event count mode.
Serial I/O operates only when an external clock (or is selected as the synchronous clock
in the stop mode.
7480 Group and 7481 Group User's Manual
1-170
HARDWARE
1.20 Built-in PROM Version
1.20 Built-in PROM Version
A microcomputer with built-in PROM (PROM) is called a built-in programmable ROM version (built-in PROM
version), in contrast to a mask ROM version.
The 7480 Group and 7481 Group offer the following two versions of this type.
• One Time PROM version
The one time PROM are programmable only once. Erasing and reprogramming are not possible.
• Built-in EPROM version (with a transparent window)
The microcomputer has a built-in erasable PROM (EPROM) with a transparent window in top of the
package. The built-in EPROM are programmable, erasable and reprogrammable.
The built-in PROM version has the EPROM mode to program into the built-in PROM, in addition to the
operation modes of the mask ROM version.
For details, refer to Sections 1.3 Performance Overviews, 1.4 Pinouts, and 1.6 Functional Block Diagrams.
The 7480 Group and 7481 Group support the built-in PROM version produlisted in Table 1.20.1.
Table 1.20.1 Supported Built-in PROM Version Products in 7480 d 7481 Group
(As of September 1997)
PROM
(bytes)
RAM
I/O Port
Product
Pa
Remarks
(bytes)
M37480E8SP
One Time PROM Version
I/O ports: 18
M37480E8FP
2W-A (shipped in blank)
2P4B
Input ports:
(Including
input
M37480E8-XXXSP
M37480E8-XXXFP
M37480E8T-XXXSP
M37480E8T-XXXFP
M37481E8SP
One Time PROM Version
32P2W-A
32P4B
One Time PROM Version (Extended
32P2W-A operating temperature range version)
16384
448
42P4B
One Time PROM Version
M37481E8FP
44P6N-A (shipped in blank)
42P4B
ports: 24
M37481E8-XXXSP
M37481E8-XXXFP
M37481E8T-XXXSP
M37481E8T-XXXFP
M37481E8SS
nput ports: 12
(Including 8 analog
input pins.)
One Time PROM Version
44P6N-A
42P4B
One Time PROM Version (Extended
44P6N-A operating temperature range version)
42S1B-A Built-in EPROM Version
7480 Group and 7481 Group User's Manual
1-171
HARDWARE
1.20 Built-in PROM Version
1.20.1 EPROM Mode
The built-in PROM version has the EPROM mode in addition to the operation modes of the mask ROM
version. The EPROM mode is the mode used to program into and read from the built-in PROM. Programming,
reading and erasing of the built-in PROM can be performed by the same operation as in the M5M27C256K.
Table 1.20.2 lists the pin functions in the EPROM mode, and Figures 1.20.1 to 1.20.3 show the pinouts.
Table 1.20.2 Pin Functions in EPROM Mode
Built-in PROM version
VCC
M5M27C256K
VCC
P33
VPP
VSS
VSS
P11–P17,
P20–P23,
P30, P31,
P40, P41
P00–P07
VREF
Pin name
A0–A14
D0–D7
CE
OE
P32
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P3
P3
7
6
5
4
3
2
1
0
1
0
3
2
P1
7
/SRDY
1
2
D
7
6
A
A
10
9
8
D
P1
P1
6/SCLK
A
5
/TXD
D
5
4
D
A
A
A
7
6
5
P1
4
/RXD
P1
P1
3
/T
D3
D2
D1
D0
7
A
4
8
A
3
/IN
1/IN
0
/IN
3
2
1
0
/CNTR
1
0
9
A
A
14
13
P2
P2
/CNTR
10
11
12
13
14
A
A
A
2
1
V
PP
0
OE
V
REF
IN
OUT
SS
A
A
12
11
P3
1
0
/INT
1
0
CE
X
P3
/INT
X
RESET
15
16
VSS
V
V
CC
V
CC
VSS
Outline 32P4B
32P2W-A (Note)
: PROM pin (Same functions as M5M27C256K)
The only differences between the 32P4B package product and the 32P2W-A package product are
package shape and the absolute maximum ratings.
Note:
Figure 1.20.1 Pinout in EPROM Mode of 7480 Group
7480 Group and 7481 Group User's Manual
1-172
HARDWARE
1.20 Built-in PROM Version
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P52
P5
3
1
2
3
D
D
D
7
6
5
4
P07
P06
P05
P04
P03
P02
P01
P00
A
10
P17/SRDY
P1
6
/SCLK
A
A
A
9
8
7
6
P1
5
/TXD
4
P14
/RXD
5
D
D
D
P1
P1
3
/T
1
0
1
0
6
A
A
A
3
2
2/T
7
5
4
P1
P1
8
D
1
0
9
D
P2
7/IN
6/IN
5/IN
4/IN
7
6
5
4
10
11
12
13
14
15
16
P4
3
2
P2
P2
P2
P4
A
14
13
P41
P40
P33
P32
/CNTR
1
0
/CNTR
A
P2
P2
P2
P2
3
2
1
0
/IN
/IN
/IN
/IN
3
2
1
0
VPP
A
A
A
A
3
2
1
OE
A
P3
P3
1
/INT
1
0
0/INT
17
18
19
20
21
0
V
REF
IN
OUT
SS
RESET
CE
X
P51
VSS
X
P50
VCC
V
VSS
VCC
Outline 42P4B (Note)
42S1B-A (M37481E
: PROM pin (Same functions as M5M27C256K)
Note: The only differences between the 42P4B package pro44P6N-A package product are
package shape, the absolute maximum ratings and the 44P6N-A package product has
the AVSS pin.
Figure 1.20.2 Pinout in EPROM M481 Group (1)
7480 Group and 7481 Group User's Manual
1-173
HARDWARE
1.20 Built-in PROM Version
P0
4
22
21
20
19
P3
RESET
0/INT0
34
35
D
4
5
A
11
P0
P0
P0
5
D
P5
P5
1
0
6
7
36
37
38
39
D
6
7
V
SS
D
P52
V
CC
VCC
18
17
16
15
14
M37481E8-XXXFP
M37481E8T-XXXFP
VSS
V
SS
V
SS
VSS
AVSS
P53
40
41
P1
P1
P1
P1
7
/SRDY
X
OUT
IN
A10
A
A
A
9
6
/SCLK
X
42
43
44
5
/TX
D
13
12
8
7
CE
4
/RXD
A
0
ON-A (Note)
: PROM pin (Same functi27C256K)
Note: The only differences betP4B package product and the 44P6N-A package product are
package shape, the amum ratings and the fact that the 44P6N-A package product has
the AVSS pin.
Figure 1.20.3 Pinout in EPROM Mode of 7481 Group (2)
7480 Group and 7481 Group User's Manual
1-174
HARDWARE
1.20 Built-in PROM Version
1.20.2 Pin Descriptions
Tables 1.20.3 and 1.20.4 list pin descriptions in the Ordinary and EPROM modes.
Table 1.20.3 Pin Descriptions (1)
Input/
Pin
Name
Mode
Function
Output
VCC,
Ordinary/
EPROM
Power source
• Apply the following voltage to the VCC pin:
2.7 V to 4.5 V (at f(XIN) = (2.2 VCC–2) MHz), or
4.5 V to 5.5 V (at f(XIN) = 8 MHz).
• Apply 0 V to the VSS pin.
VSS
AVSS
Ordinary/
EPROM
Analog
• Ground level input pin for the A-D converter
• Apply the same voltage as for the VSS pin to the AVSS
pin.
power source
Note: This pin is dedicated to the 44P6N-A package products
in the 7481 Group.
VREF
Ordinary
Reference
Input
• Reference voltage inpA-D converter
• Apply the following to the VREF pin:
2 V to VCC whe2.7 V to 4.0 V, or
0.5 VCC to VVCC = 4.0 V to 5.5 V.
Note: Wheg A-D converter, connect VREF pin to
V
voltage input
• CE
Mode input
Reset input
Input
Input
EPROM
• ut pin
RESET Ordinary
EPROM
m Reset: Holding the LOW level for 2 µs or more
es CPU into reset state.
Connect it to VSS pin.
Reset input
Clock input
I
• I/O pins for clock generator
XIN
Ordinary/
EPROM
• A ceramic resonator is connected between pins XIN and
XOUT.
• When an external clock is used, it is input to XIN pin, and
leave XOUT pin open.
XOUT
Ordinary/
EPROM
Cloc
Output
• A feedback resistor is built in between pins XIN and XOUT.
7480 Group and 7481 Group User's Manual
1-175
HARDWARE
1.20 Built-in PROM Version
Table 1.20.4 Pin Descriptions (2)
Input/
Output
I/O
Pin
Name
Function
Mode
P00–P07
I/O port P0
• 8-bit I/O port pins
Ordinary
• The output structure is CMOS output.
• When an input port is selected, a pull-up transistor can
be connectable by the bit.
• In input mode, a key-on wake up function is provided.
• Data (D0–D7) I/O pins
I/O
I/O
Data I/O
D0–D7
EPROM
Ordinary
P10–P17
I/O port P1
• 8-bit I/O port pins
• The output structure is CMOS output.
• When an input port is selected, a pull-up transistor can
be connected by the 4 bits.
• P12 and P13 serve the ive functions of the timer
output pins T0 and T
• P14, P15, P16, anve the alternative functions of
the serial I/O pixD, SCLK and SRDY, respectively.
• P11–P17 arress (A4–A10) input pins.
• Leave P
Input
Input
Address input
A4–A10
EPROM
Ordinary
• 8-bit pins
P20–P27
P30–P33
Input port P2
• P2erve the alternative functions of the analog
s IN0–IN7.
he 7480 Group has only four pins of P20–P23 (IN0–IN3).
Inp
20–P23 are the address (A0–A3) input pins.
Leave P24–P27 open.
Address input
A0–A3
EPROM
Ordinary
• 4-bit input port pins
Input port P3
• P30 and P31 serve the alternative functions of the external
interrupt input pins INT0 and INT1.
Input
I/O
• P30, P31 are the address (A11, A12) input pins.
• P32 pin is the OE input pin.
Addt
A11
EPROM
Ordinary
• P33 pin is the VPP input pin used to apply VPP when
programming and program verifying.
Mode input
VPP input
• 4-bit I/O port pins
P40–P43
I/O port P4
• The output structure is N-channel open-drain outputs with
built-in clamping diodes.
• P40 and P41 serve the alternative functions of the timer
I/O pins CNTR0 and CNTR1.
Note: The 7480 Group has only two pins of P40 and P41.
• P40, P41 are the address (A13, A14) input pins.
• Leave P42, P43 open.
Input
I/O
Address input
A13, A14
EPROM
Ordinary
• 4-bit I/O port pins
P50–P53
I/O port P5
• The output structure is N-channel open-drain outputs with
built-in clamping diodes.
Note: The 7480 Group is not provided with port P5.
• Leave port P5 open.
Input
Input port P5
EPROM
7480 Group and 7481 Group User's Manual
1-176
HARDWARE
1.20 Built-in PROM Version
1.20.3 Reading, Programming and Erasing of Built-in PROM
The built-in PROM version can be used in the EPROM mode by setting the RESET pin to LOW. Reading,
programming, and erasing of the built-in PROM in the EPROM mode are described below.
Also, Table 1.20.5 lists the I/O signals in the EPROM mode.
(1) Reading from Built-in PROM
• 0 V is applied to the RESET pin, and 5 V to the VCC pin.
• Address signals (A0–A14) are input, and the OE and the CE pins are set to LOW. Then, the contents
of PROM are placed on data I/O pins (D0–D7).
• The CE or the OE pins are set to HIGH. Then, data I/O pins (D0–D7) float.
(2) Programming into Built-in PROM
• 0 V is applied to the RESET pin, and 5 V to the VCC pin.
• The OE pin is set to HIGH and VPP is applied to the VPP pin. Then, the CPU enters the program
mode.
• Addresses are set to address input pins (A0–A14), and the 8-bit datto be programmed is placed
in parallel, on data I/O pins (D0–D7).
• Setting the CE pin to LOW starts programming.
Specify addresses 400016 through 7FFF16 when programmthe PROM programmer.
Also, set all addresses 000016 through 3FFF16 to ‘FF16’ ogramming into addresses 000016
through 7FFF16.
(3) Erasing
• Only the built-in EPROM version with a wi7481E8SS) is erasable.
• The EPROM can be erased when exposaviolet light with a wavelength of 2537 Å.
• Integrated dose necessary for erasurimum of 15 W•s/cm2.
Table 1.20.5 I/O Signals in EPROM Mo
Pin name
RESET
0 V
CE
VPP
VCC
VCC
D0–D7
Mode
IL
VIH
VIH
VIL
VIH
VIL
VIH
VCC
VCC
VPP
VPP
VPP
Output
Floating
Input
Read
Output disable
Write
Output
Floating
Write-verify
Write disable
Note: VIL represents the LOW input voltage, and VIH, the HIGH input voltage.
7480 Group and 7481 Group User's Manual
1-177
HARDWARE
1.20 Built-in PROM Version
1.20.4 Notes on Usage
Pay attention to the following notes when the built-in PROM version is used.
(1) All Products of Built-in PROM Version Products
Programming into Built-in PROM
• A high voltage is used to program into the PROM. Be careful not to apply an overvoltage to pins,
especially when power is turned on.
• The use of a dedicated programming adapter (Note) is recommended when the PROM programming
is performed, so that general-purpose PROM programmers are available for programming.
Reading from Built-in PROM
The use of a dedicated programming adapter (Note) is recommended when the PROM contents are
read, so that general-purpose PROM programmers are available fding.
Note: Refer to Data Book DEVELOPMENT SUPPORT TOOMICROCOMPUTERS for the
dedicated programming adapter.
(2) One Time PROM Version
The one time PROM version (a blank product) is tested nor screened since Mitsubishi’s
assembly process. To improve reliability after png, it is suggested that these products are
used only after programming and verification, g to the procedure shown in Figure 1.20.4, is
completed.
Programming with PROM Programmer
Screening
(at 150°C for 40
(Note 1)
Notes 1: Exposure to a high temperature of be within 100 hours.
The M37480E8SP/FP, M37481E8SP/FP and M37481E8SS
are not available for automotive controls because they are not
extended operating temperature versions, which are used in
automotive controls. The M37481E8SS is for the program-evaluation
only. It cannot be as the final product as well as in automotive
controls.
Verifying with POM
Programmer
2: Implementation evaluation will reject those damaged by
surge during handling.
(Note 2)
Function check in target device
Figure 1.20.4 Programming and Verification of One Time PROM Version
7480 Group and 7481 Group User's Manual
1-178
HARDWARE
1.20 Built-in PROM Version
(3) Built-in EPROM Version
The built-in EPROM version can be used for program development only. Use them only for program
development and implementation evaluation.
Sunlight and fluorescent light include light that may erase the information programmed in the built-
in PROM. When using the EPROM version in the read mode, be sure to cover the transparent glass
portion with a seal.
This seal to cover the transparent glass portion is prepared by Mitsubishi. Be careful not to bring
the seal into contact with the microcomputer lead wires when covering the portion with the seal
because this seal is made of metal (aluminum).
Before erasing data, clean the transparent glass. If any finger stain or seal adhesive is stuck to the
transparent glass, this prevents ultraviolet rays from passing, thereby affecting the erase characteristic
adversely.
7480 Group and 7481 Group User's Manual
1-179
HARDWARE
1.21 Electrical Characteristics
1.21 Electrical Characteristics
1.21.1 Electrical Characteristics
(1) Electrical Characteristics of 7480 Group
For the 7480 Group, Table 1.21.1 lists the absolute maximum ratings, and Tables 1.21.2 and 1.21.3
list the recommended operating conditions. Also, Tables 1.21.4 and 1.21.5 list the electrical characteristics,
and Table 1.21.6 lists the A-D conversion characteristics.
Table 1.21.1 Absolute Maximum Ratings of 7480 Group
Symbol
VCC
VI
Parameter
Power source voltage
Input voltage
Conditions
Ratings
Unit
V
All voltages are measured based on –0.3 to 7
VSS.
–0.3 to VCC+0.3
V
VO
Output voltage
Output transistors are in the cut-off state. –0.3 to VCC+0.3
V
Pd
Power dissipation
Ta = 25°C
10 (Note 1)
mW
°C
°C
Topr
Tstg
Operating temperature range
Storage temperature range
85 (Note 2)
to 150 (Note 3)
Notes 1: 500 mW for 32P2W-A package.
2: –40 °C to 85 °C for extended operating temperature sion.
3: –65 °C to 150 °C for extended operating temperatversion.
Table 1.21.2 Recommended Operating Conditions ooup (1) (Note 1)
Limits
Symbol
VCC
Parameter
Unit
Min.
4.5
Max.
5.5
Typ.
V
V
f(XIN) =
f(XICC–2.0) MHz
5
3
0
Power source voltage
Power source voltage
2.7
4.5
VSS
VIH
VIH
V
HIGH input voltage P00–P017
HIGH input voltage P20
0.8VCC
VCC
VCC
V
0.7VCC
V
HIGH input voltage
0.8VCC
VCC
V
VCC = 4.5 V to 5.5V
VCC = 2.7 V to 4.5V
VIH
P30–P33, P40, P42)
0.9VCC
VCC
V
HIGH input voltRESET
LOW input voltage 00–P07, P10–P17
LOW input voltage P20–P23
0.8VCC
VCC
V
VIH
VIL
VIL
0
0
0
0
0
0
0.2VCC
0.25VCC
0.4VCC
0.3VCC
0.16VCC
0.12VCC
1
V
V
LOW input voltage
VCC = 4.5 V to 5.5V
VCC = 2.7 V to 4.5V
V
VIL
P30–P33, P40, P41
V
LOW input voltage XIN
LOW input voltage RESET
V
VIL
VIL
II
V
Input current P40, P41 (Note 2) VI > VCC
mA
Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –20 °C to 85 °C (Ta = –40 ° C to 85 °C for extended
operating temperature range version), unless otherwise noted.
For the clamping diodes of port P4, refer to (4) Level Shift Ports in Section 1.10.3 I/O Ports.
2: When voltage is applied through a resistor, current I of 1 mA or less maintains VI > VCC.
For this circuit, refer to Figure 1.10.11 Port P4 and P5 Circuit.
7480 Group and 7481 Group User's Manual
1-180
HARDWARE
1.21 Electrical Characteristics
Table 1.21.3 Recommended Operating Conditions of 7480 Group (2) (Note 1)
Limits
Min. Typ.
Symbol
Parameter
Unit
Max.
–30
–30
60
IOH(sum) HIGH output sum current P00–P07
IOH(sum) HIGH output sum current P10–P17
IOL(sum) LOW output sum current P00–P07, P40, P41
mA
mA
mA
mA
mA
mA
mA
60
IOL(sum)
IOH(peak)
LOW output sum current P10–P17
–10
20
HIGH output peak current P00–P07, P10–P17
IOL(peak) LOW output peak current P00–P07, P10–P17, P40, P41
–5
IOH(avg) HIGH output average current P00–P07, P10–P17 (Note 2)
LOW output average current
IOL(avg)
10
mA
P00–P07, P10–P17, P40, P41 (Note 2)
f(XIN) = 8 MHz
2
1
Timer input frequency CNTR0 (P40)
MHz
MHz
kHz
f(CNTR)
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MH
CNTR1 (P41) (Note 3)
Serial I/O
500
250
2
when selecting clock
synchronous serial I/O
when selecting
UART
clock input frequency
SCLK (P16)
kHz
f(SCLK)
MHz
MHz
MHz
MHz
1
(Note 3)
8
Clock input oscillation VCC = 4.5V to 5.5V
frequency (Note 3)
VCC = 2.7V to 4.5V
f(XIN)
2.2VCC–2.0
Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –85 °C (Ta = –40 ° C to 85 °C for extended
operating temperature range version), unlwise noted.
For the clamping diodes of port P4, refLevel Shift Ports in Section 1.10.3 I/O Ports.
2: Output average currents IOH(avg) an) are average values for a period of 100 ms.
3: The frequency is the value at a 5cycle.
4: Connect a bypass capacitor of c.1 µF between VCC and VSS, and one of capacity 0.01µF
between VREF and VSS.
7480 Group and 7481 Group User's Manual
1-181
HARDWARE
1.21 Electrical Characteristics
Table 1.21.4 Electrical Characteristics of 7480 Group (1) (Note 1)
Limits
Typ.
Parameter
Unit
Symbol
VOH
Test conditions
Min.
Max.
HIGH output voltage
P00–P07, P10–P17
3
2
V
V
VCC = 5 V, IOH = –5 mA
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
VCC = 5 V
LOW output voltage
2
1
V
VOL
P00–P07, P10–P17, P40, P41
Hysteresis P00–P07 (Note 2),
P30–P33, P40, P41
V
0.5
0.3
0.5
0.3
0.5
0.3
V
VT+–VT–
VT+–VT–
VT+–VT–
IIH
V
VCC = 3 V
V
VCC = 5 V
Hysteresis RESET
V
VCC = 3 V
VCC = 5 V
V
Hysteresis
when used as
VCC = 3 V
VCC = 5 V
VCC = 3 V
V
P14/RxD, P16/SCLK
HIGH input current
P00–P07, P10–P17
HIGH input current
P30–P33, P40, P41
HIGH input current
P20–P23
RxD, SCLK
5
3
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
µA
µA
µA
µA
µA
µA
VI = VCC,
No pull-up transistor
VI = VCC = 5 V
VI = VCC = 3 V
VI = VCC, when not
selecting analog input
VI = VCC, when XI
is stopped
5
IIH
3
V
3 V
= 5 V
CC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
5
IIH
3
HIGH input current
XIN, RESET
5
IIH
3
–5
–3
–1.0
–0.35
–5
–3
–5
–3
–5
–3
VI = 0 V,
LOW input current
P00–P07, P10–P17
No pull-uor
VI = 0 3),
Pulistor used
IIL
–0.5
–0.25
–0.08
–0.18
LOW input current
P30–P33, P40, P41
LOW input current
P20–P23
IIL
IIL
IIL
V
= 0 V, when not
selecting analog input
VI = 0 V, when XIN
is stopped
LOW input curre
XIN, RESET
Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –20 °C to 85°C (Ta = –40 °C to 85°C for extended
operating temperature range version), unless otherwise noted.
2: The limits when the key-on wakeup function of port P0 is used
3: When represented with electric resistance, the corresponding values are as follows:
• VCC = 5 V: 5 kΩ (Min.), 10 kΩ (Typ.), and 20 kΩ (Max.)
• VCC = 3 V: 8.6 kΩ (Min.), 16.7 kΩ (Typ.), and 37.5 kΩ (Max.)
7480 Group and 7481 Group User's Manual
1-182
HARDWARE
1.21 Electrical Characteristics
Table 1.21.5 Electrical Characteristics of 7480 Group (2) (Note)
Limits
Unit
Symbol
Parameter
Test conditions
No A-D
Min.
Typ.
Max.
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.5
7
High-speed mode,
f(XIN) = 4 MHz,
VCC = 5 V
conversion
During A-D
conversion
No A-D
4
1.8
2
8
3.6
4
High-speed mode,
f(XIN) = 4 MHz,
VCC = 3 V
conversion
During A-D
conversion
No A-D
7
14
15
3.5
4
High-speed mode,
f(XIN) = 8 MHz,
VCC = 5 V
conversion
During A-D
conversion
No A-D
7.5
1.75
2
Medium-speed mode,
f(XIN) = 4 MHz,
VCC = 5 V
conve
D
on
-D
Medium-speed mo
f(XIN) = 4 M
VCC = 3
0.9
1
1.8
2
nversion
During A-D
conversion
No A-D
ICC
Power source current
Memode,
8 MHz,
= 5 V
7
3.5
3.75
conversion
During A-D
conversion
VCC = 5 V
VCC = 3 V
7.5
igh-speed mode,
f(XIN) = 4 MHz
High-speed mode,
f(XIN) = 8 MHz
Medium-speed mode,
f(XIN) = 4 MHz
Medium-speed mode,
f(XIN) = 8 MHz
mA
mA
2
1
1
0.5
mA
VCC = 5 V
4
2
mA
mA
VCC = 5 V
VCC = 3 V
1.8
0.9
0.9
0.45
mA
VCC = 5 V
Ta = 25 °C
Ta = 85 °C
3.6
1
1.8
0.1
1
µA
f(XIN) = 0 MHz,
VCC = 5 V
µA
10
At clock stop
VRAM
RAM back-up voltage
V
2.0
Note: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –20 °C to 85°C (Ta = –40 °C to 85°C for extended
operating temperature range version), unless otherwise noted.
7480 Group and 7481 Group User's Manual
1-183
HARDWARE
1.21 Electrical Characteristics
Table 1.21.6 A-D Conversion Characteristics of 7480 Group (Note)
Limits
Typ.
Unit
bits
Symbol
Test conditions
Parameter
Max.
8
Min.
–
–
Resolution
Absolute accuracy
LSB
±2
VCC = VREF = 5.0 V
(except quantification error)
µs
µs
V
VCC = 2.7V to 4.5V, f(XIN) = 4MHZ
VCC = 4.5V to 5.5V, f(XIN) = 8MHZ
VCC = 2.7 V to 4.0V
25
12.5
VCC
VCC
100
TCONV
VVREF
Conversion time
2
0.5 VCC
12
Reference voltage
VCC = 4.0 V to 5.5 V
V
kΩ
V
RLADDER
VIA
35
Ladder resistor
0
VREF
416
Analog input voltage
Reference power input current
VREF = 5.0 V
µA
IVREF
50
143
Note: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –20 °C to 85°C (Ta = –40 °C to 85°C for extended
operating temperature range version), unless otherwise noted.
7480 Group and 7481 Group User's Manual
1-184
HARDWARE
1.21 Electrical Characteristics
(2) Electrical Characteristics of 7481 Group
For the 7481 Group, Table 1.21.7 lists the absolute maximum ratings, and Tables 1.21.8 and 1.21.9
list the recommended operating conditions. Also, Tables 1.21.10 and 1.21.11 list the electrical
characteristics, and Table 1.21.12 lists the A-D conversion characteristics.
Table 1.21.7 Absolute Maximum Ratings of 7481 Group
Symbol
VCC
VI
Parameter
Power source voltage
Input voltage
Conditions
Ratings
Unit
V
All voltages are measured based on –0.3 to 7
VSS.
–0.3 to VCC+0.3
V
VO
Output voltage
Output transistors are in the cut-off state. –0.3 to VCC+0.3
V
Pd
Power dissipation
Ta = 25°C
1000 (Note 1)
mW
°C
°C
Topr
Tstg
Operating temperature range
Storage temperature range
–20 to 85 (Note 2)
–40 to 150 (Note 3)
Notes 1: 500 mW for 44P6N-A package.
2: –40 °C to 85 °C for extended operating temperature range versio
3: –65 °C to 150 °C for extended operating temperature range v
Table 1.21.8 Recommended Operating Conditions of 7481 Groute 1)
Limits
Symbol
VCC
Parameter
Unit
Min.
4.5
Max.
5.5
Typ.
V
V
f(XIN) = 8
5
3
0
Power source voltage
Power source voltage
2.7
4.5
f(XIN) = 2.0) MHz
VSS
VIH
VIH
V
HIGH input voltage P00–P07, P10–P17
HIGH input voltage P20–P27
HIGH input voltage
0.8VCC
VCC
VCC
V
0.7VCC
V
0.8VCC
VCC
V
= 4.5 V to 5.5V
VCC = 2.7 V to 4.5V
VIH
P30–P33, P40–P43, P50–P53
0.9VCC
VCC
V
HIGH input voltage XIN, R
0.8VCC
VCC
V
VIH
VIL
VIL
LOW input voltage P000–P17
LOW input voltage
LOW input voltag
0
0
0
0
0
0
0.2VCC
0.25VCC
0.4VCC
0.3VCC
0.16VCC
0.12VCC
1
V
V
VCC = 4.5 V to 5.5V
VCC = 2.7 V to 4.5V
V
VIL
P30–P33, P40–P0–P53 (Note 2
LOW input voltage XIN
)
V
V
VIL
VIL
II
LOW input voltage RESET
V
Input current P40–P43, P50–P53 (Note 2) VI > VCC
mA
Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –20 °C to 85 °C (Ta = –40 ° C to 85 °C for extended
operating temperature range version), unless otherwise noted.
For the clamping diodes of port P4, refer to (4) Level Shift Ports in Section 1.10.3 I/O Ports.
2: When voltage is applied through a resistor, current I of 1 mA or less maintains VI > VCC.
For this circuit, refer to Figure 1.10.11 Port P4/P5 Circuitry.
7480 Group and 7481 Group User's Manual
1-185
HARDWARE
1.21 Electrical Characteristics
Table 1.21.9 Recommended Operating Conditions of 7481 Group (2) (Note 1)
Limits
Min. Typ.
Symbol
Parameter
Unit
Max.
–30
–30
60
IOH(sum) HIGH output sum current P00–P07
mA
mA
mA
mA
mA
mA
mA
IOH(sum) HIGH output sum current P10–P17
IOL(sum) LOW output sum current P00–P07, P40–P43, P50–P52
IOL(sum) LOW output sum current P10–P17, P53
60
–10
20
IOH(peak)
HIGH output peak current P00–P07, P10–P17
IOL(peak) LOW output peak current P00–P07, P10–P17, P40–P43, P50–P53
–5
IOH(avg) HIGH output average current P00–P07, P10–P17 (Note 2)
LOW output average current
IOL(avg)
10
mA
P00–P07, P10–P17, P40–P43, P50–P53 (Note 2)
f(XIN) = 8 MHz
2
1
Timer input frequency CNTR0 (P40)
MHz
MHz
kHz
f(CNTR)
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MH
CNTR1 (P41) (Note 3)
Serial I/O
500
250
2
when selecting clock
synchronous serial I/O
when selecting
UART
clock input frequency
SCLK (P16)
kHz
f(SCLK)
MHz
MHz
MHz
MHz
1
(Note 3)
8
Clock input oscillation VCC = 4.5V to 5.5V
frequency (Note 3)
VCC = 2.7V to 4.5V
f(XIN)
2.2VCC–2.0
Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –85 °C (Ta = –40 ° C to 85 °C for extended
operating temperature range version), unlwise noted.
For the clamping diodes of port P4, reLevel Shift Ports in Section 1.10.3 I/O Ports.
2: Output average currents IOH(avg) ang) are average values for a period of 100 ms.
3: The frequency is the value at a 5cycle.
4: Connect a bypass capacitor of c.1 µF between VCC and VSS, and one of capacity 0.01µF
between VREF and VSS.
7480 Group and 7481 Group User's Manual
1-186
HARDWARE
1.21 Electrical Characteristics
Table 1.21.10 Electrical Characteristics of 7481 Group (1) (Note 1)
Limits
Typ.
Parameter
Unit
Test conditions
Symbol
VOH
Min.
Max.
HIGH output voltage
3
2
V
V
VCC = 5 V, IOH = –5 mA
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
VCC = 5 V
P00–P07, P10–P17
LOW output voltage P00–P07,
P10–P17, P40–P43, P50–P53
Hysteresis P00–P07 (Note 2),
P30–P33, P40–P43, P50–P53
2
1
V
VOL
V
0.5
0.3
0.5
0.3
0.5
0.3
V
VT+–VT–
VT+–VT–
VT+–VT–
IIH
V
VCC = 3 V
V
VCC = 5 V
Hysteresis RESET
V
VCC = 3 V
Hysteresis
VCC = 5 V
V
when used as
P14/RxD, P16/SCLK
HIGH input current
P00–P07, P10–P17
HIGH input current
P30–P33, P40–P43, P50–P53
HIGH input current
P20–P27
VCC = 3 V
VCC = 5 V
VCC = 3 V
V
RxD, SCLK
5
3
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
µA
µA
µA
µA
µA
µA
VI = VCC,
No pull-up transistor
VI = VCC = 5 V
VI = VCC = 3 V
VI = VCC, when not
selecting analog input
VI = VCC, when XI
is stopped
5
IIH
3
V
3 V
= 5 V
CC = 3 V
VCC = 5 V
VCC = 3 V
5
IIH
3
HIGH input current
XIN, RESET
5
IIH
3
–5
–3
–1.0
–0.35
–5
–3
–5
–3
–5
–3
VI = 0 V,
LOW input current
P00–P07, P10–P17
No pull-uor
VI = 0 3),
Pulistor used
IIL
–0.5
VCC = 5 V –0.25
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
–0.18
–0.08
LOW input current
P30–P33, P40–P43, P50–P
LOW input current
P20–P27
IIL
IIL
IIL
V
= 0 V, when not
selecting analog input
VI = 0 V, when XIN
is stopped
LOW input curre
XIN, RESET
Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –20 °C to 85°C (Ta = –40 °C to 85°C for extended
operating temperature range version), unless otherwise noted.
2: The limits when the key-on wakeup function of port P0 is used
3: When represented with electric resistance, the corresponding values are as follows:
• VCC = 5 V: 5 kΩ (Min.), 10 kΩ (Typ.), and 20 kΩ (Max.)
• VCC = 3 V: 8.6 kΩ (Min.), 16.7 kΩ (Typ.), and 37.5 kΩ (Max.)
7480 Group and 7481 Group User's Manual
1-187
HARDWARE
1.21 Electrical Characteristics
Table 1.21.11 Electrical Characteristics of 7481 Group (2) (Note)
Limits
Typ.
Symbol
Parameter
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test conditions
No A-D
Min.
Max.
7
3.5
4
High-speed mode
f(XIN) = 4 MHz
VCC = 5 V
conversion
During A-D
conversion
No A-D
8
3.6
4
1.8
2
High-speed mode
f(XIN) = 4 MHz
VCC = 3 V
conversion
During A-D
conversion
No A-D
7
14
15
3.5
4
High-speed mode
f(XIN) = 8 MHz
VCC = 5 V
conversion
During A-D
conversion
No A-D
7.5
1.75
2
Medium-speed mode
f(XIN) = 4 MHz
VCC = 5 V
conve
D
on
-D
Medium-speed mo
f(XIN) = 4 M
VCC = 3
0.9
1
1.8
2
nversion
During A-D
conversion
No A-D
ICC
Power source current
Memode
8 MHz
= 5 V
7
3.5
3.75
conversion
During A-D
conversion
VCC = 5 V
VCC = 3 V
7.5
igh-speed mode
f(XIN) = 4 MHz
High-speed mode
f(XIN) = 8 MHz
Medium-speed mode
f(XIN) = 4 MHz
Medium-speed mode
f(XIN) = 8 MHz
mA
mA
2
1
1
0.5
mA
VCC = 5 V
4
2
mA
mA
VCC = 5 V
VCC = 3 V
1.8
0.9
0.9
0.45
mA
VCC = 5 V
Ta = 25 °C
Ta = 85 °C
3.6
1
1.8
0.1
1
µA
f(XIN) = 0 MHz
VCC = 5 V
µA
10
At clock stop
VRAM
RAM back-up voltage
V
2.0
Note: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –20 °C to 85°C (Ta = –40 °C to 85°C for extended
operating temperature range version), unless otherwise noted.
7480 Group and 7481 Group User's Manual
1-188
HARDWARE
1.21 Electrical Characteristics
Table 1.21.12 A-D Conversion Characteristics of 7481 Group (Note)
Limits
Typ.
Unit
bits
Symbol
Test conditions
Parameter
Min.
Max.
8
–
–
Resolution
Absolute accuracy
LSB
VCC = VREF = 5.0 V
±2
(except quantification error)
µs
µs
V
VCC = 2.7V to 4.5V, f(XIN) = 4MHZ
VCC = 4.5V to 5.5V, f(XIN) = 8MHZ
VCC = 2.7 V to 4.0V
25
12.5
VCC
VCC
100
TCONV
VVREF
Conversion time
2
0.5 VCC
12
Reference voltage
VCC = 4.0 V to 5.5 V
V
kΩ
V
RLADDER
VIA
35
Ladder resistor
0
VREF
416
Analog input voltage
µA
IVREF
50
143
Reference power input current VREF = 5.0 V
Note: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –20 °C to 85°C (Ta = –40 °C to 85°C for extended
temperature range version), unless otherwise noted.
7480 Group and 7481 Group User's Manual
1-189
HARDWARE
1.21 Electrical Characteristics
1.21.2 Necessary Conditions for Timing and Switching Characteristics
Table 1.21.13 lists the necessary conditions for timing and the switching characteristics of the 7480 Group
and 7481 Group, and Figure 1.21.1 shows the timing diagram.
Table 1.21.13 Necessary Conditions for Timing and Switching Characteristics (Note)
Limits
Unit
Symbol
Parameter
Min.
2000
880
880
160
80
Typ.
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC(SCLK)
Serial I/O clock input cycle time
Serial I/O clock input HIGH pulse width
Serial I/O clock input LOW pulse width
Serial I/O input set-up time
tWH(SCLK)
tWL(SCLK)
tSU(RxD–SCLK)
th(SCLK–RxD)
td(SCLK–TxD)
tC(SCLK)
Serial I/O input hold time
Serial I/O output delay time
100
Serial I/O clock input cycle time
Serial I/O clock input HIGH pulse width
Serial I/O clock input LOW pulse width
500
0
tWH(SCLK)
tWL(SCLK)
Note: Values at VCC = 4.5 V to 5.5 V, VSS = 0 V, Ta = –40 °C to d f(XIN) = 8 MHz
tc(SCLK)
t
WL(SCLK
)
(SCLK)
0.8VCC
0.8VCC
S
CLK
0.2VCC
0.2VCC
D-S
tsu(R
X
th(SCLK-RXD)
0.8V
0.8VCC
0.2VCC
RXD
td(SCLK-T
XD
TXD
Figure 1.21.1 Timing Diagram
1.21.3 Typical Characteristics of Power Source Current
The typical characteristics of the power source current
described in this section are based on a limited
number of samples in the 7480 Group and 7481
Group. ‘Typical values’ are not guaranteed.
For the limits, refer to section 1.21.1 Electrical
Characteristics.
7480 Group
7481 Group
ICC
V
CC
VSS
A
Figure 1.21.2 shows a measurement circuit of typical
power source current characteristics.
XIN
XOUT
0 to 5.5V
Figure 1.21.2 Measurement Circuit of Typical Power
Source Current Characteristics
7480 Group and 7481 Group User's Manual
1-190
HARDWARE
1.21 Electrical Characteristics
(1) VCC–ICC Characteristics
Figures 1.21.3 to 1.21.6 show the VCC–ICC characteristics of the 7480 Group and 7481 Group.
Conditions: System operates at 25°C, f(XIN) = 8 MHz (with
a ceramic resonator) in High-speed mode
10.0
9.0
During A-D conversion
8.0
7.0
6.0
No A-D n
5.0
4.0
3.0
2.0
1.0
0.0
2.0
3.0
.0
5.0
6.0
7.0
Power source voltage VCC [V]
Figure 1.21.3 VCC–ICC Charactat System Operating in High-Speed Mode)
Conditions: System operates at 25°C, f(XIN) = 8 MHz (with
a ceramic resonator) in Medium-speed mode
5.0
4.0
During A-D conversion
3.0
No A-D conversion
2.0
1.0
0.0
2.0
3.0
4.0
5.0
6.0
7.0
Power source voltage VCC [V]
Figure 1.21.4 VCC–ICC Characteristics (at System Operating in Medium-Speed Mode)
7480 Group and 7481 Group User's Manual
1-191
HARDWARE
1.21 Electrical Characteristics
Conditions: 25°C, f(XIN) = 8 MHz (with a ceramic resonator)
in wait mode
0.3
0.2
0.1
0.0
High-speed mode
Medium-speed mode
2.0
3.0
4.0
5.0
6.0
7.0
Power source voltage VCC [V]
Figure 1.21.5 VCC–ICC Characteristics (in Wait Mode)
tions: 25°C, f(XIN) = 0 MHz
in stop mode
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2.0
3.0
4.0
5.0
6.0
7.0
Power source voltage VCC [V]
Figure 1.21.6 VCC–ICC Characteristic (in Stop Mode)
7480 Group and 7481 Group User's Manual
1-192
HARDWARE
1.21 Electrical Characteristics
(2) f(XIN)–ICC Characteristics
Figures 1.21.7 and 1.21.8 show the f(XIN)-ICC characteristics of the 7480 Group and 7481 Group.
Conditions: System operates at 25 °C,
with a ceramic resonator
in High-speed mode
6.0
5.0
4.0
3.0
2.0
V (During A-D conversion)
V (No A-D conversion)
= 3 V (During A-D conversion)
C = 3 V (No A-D conversion)
1.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Clock input oscillation frequency f(XIN) [M
Figure 1.21.7 f(XIN)–ICC Characteristics (at System ng in High-Speed Mode)
Conditioperates at 25 °C,
ceramic resonator
medium-speed mode
3.0
2.0
1.0
: VCC = 5 V (During A-D conversion)
: VCC = 5 V (No A-D conversion)
: VCC = 3 V (During A-D conversion)
: VCC = 3 V (No A-D conversion)
0.0
0.0
8.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Clock input oscillation frequency f(XIN) [MHz]
Figure 1.21.8 f(XIN)–ICC Characteristics (at System Operating in Medium-Speed Mode)
7480 Group and 7481 Group User's Manual
1-193
HARDWARE
1.21 Electrical Characteristics
1.21.4 Typical Characteristics of Ports
The typical characteristics of the ports described in this section are based on limited numbers of samples
in the 7480 Group and 7481 Group. ‘Typical values’ are not guaranteed. For the limits, refer to Section
1.21.1 Electrical Characteristics.
Figure 1.21.9 shows measurement circuits of typical port characteristics. Figures 1.21.10 through 1.21.12
show the typical characteristics of ports of the 7480 Group and 7481 Group.
1
2
3
I
OH
–
V
OH characteristics
I
OL
–
V
OL characteristics
IIL– VIL characteristics
measurement circuit
measurement circuit
measurement circuit
7480 Group
7481 Group
7480 Group
7481 Group
7480 Group
7481 Group
V
CC
V
CC
VCC
0 V to VCC
0 V to VCC
V
CC
V
CC
VCC
A
A
I
OL
P00
P00
P00
I
OH
A
V
SS
V
SS
VSS
0 V to VCC
Figure 1.21.9 Measurement Circuits of Typical Port Cistics
Condition : 25 °C
–60.0
–50.0
–40.0
V
CC = 5V
–30.0
–20.0
–10.0
0.0
V
CC = 3V
0.0
1.0
2.0
3.0
4.0
5.0
HIGH output voltage VOH [V]
Figure 1.21.10 VOH–IOH Characteristics on P-Channel Side of Programmable I/O Port (CMOS Output)
7480 Group and 7481 Group User's Manual
1-194
HARDWARE
1.21 Electrical Characteristics
Condition : 25 °C
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
V
CC = 5V
V
CC = 3V
0.0
1.0
2.0
3.0
5.0
LOW output voltage VOL [V]
Figure 1.21.11 VOL–IOL Characteristics on N-Channel Sidrammable I/O Port (CMOS Output)
Condition : 25 °C
–0.6
–0.5
–0.4
V
CC = 5V
–0.3
–0.2
–0.1
0.0
VCC = 3V
0.0
1.0
2.0
3.0
4.0
5.0
LOW input voltage VIL [V]
Figure 1.21.12 VIL–IIL Characteristics of Pull-up Transistor of Programmable I/O Port (CMOS Output)
7480 Group and 7481 Group User's Manual
1-195
HARDWARE
1.21 Electrical Characteristics
1.21.5 Typical Characteristics of A-D Conversion
Figures 1.21.13 and 1.21.14 show typical characteristics of A-D conversion of the 7480 Group and 7481
Group in different measurement conditions.
The bottom line in each graph shows an absolute accuracy error (ERROR), indicating offset from the ideal
value at the point where an output code changes.
For example, a ‘3F16→4016’ change in an output code ideally takes place at the point where IN0 = 1270mV,
in Figure 1.21.13.
However, 1270–1 = 1269 mV is obtained as the measured changing point, because the absolute accuracy
error is –1 mV.
The top line in each graph represents the width of input voltages that have the same output code in 1-LSB
WIDTH.
For example, ‘21–20 = 1 mV (0.05 LSB)’ is obtained as the differential non-linear error because the
measurement value of the width of input voltages whose output codes are ‘3F16’, is 21 mV.
7480 Group and 7481 Group User's Manual
1-196
HARDWARE
1.21 Electrical Characteristics
Figure 1.21.13 Typical Characteristics onversion (1)
7480 Group and 7481 Group User's Manual
1-197
HARDWARE
1.21 Electrical Characteristics
Figure 1.21.14 Typical Characteristics onversion (2)
7480 Group and 7481 Group User's Manual
1-198
CHAPTER 2
APPLICATIONS
2.Output Pins
er X and Timer Y
Serial I/O
.4 A-D Converter
2.5 Reset
2.6 Oscillation Circuit
2.7 Power-Saving Function
2.8 Countermeasures against Noise
2.9 Notes on Programming
2.10 Differences between 7480 and 7481
Group, and 7477 and 7478 Group
2.11 Application Circuit Examples
APPLICATIONS
2.1 Input/Output Pins
2.1 Input/Output Pins
(1) External Circuit Example for Output Ports
POINT: The following currents and voltages must be within specifications in the recommended operating
conditions when external circuits for I/O ports are designed.
For Input Ports
Input voltage
Input current
For Output Ports
Output sum currents
Output peak current
Output average current
For the recommended operating conditions, refer to Section 11 Electrical Characteristics.
Note: When a key matrix is used for multi-key inputs, take acce total current which results
from multiple inputs and is input to one port.
Figure 2.1.1 shows an external circuitry for output por
V
CC=5 V
output sum current
OL0 + IOL1 + IOL2 = 36 mA < 60 mA
I
(Note 1)
Note 1)
P0
0
• LOW output peak current
OL0 = IOL1 = IOL2 = 12 mA < 20 mA
I
OL0=12 mA
R0=250 Ω
R1=25
R2
I
P0
1
I
OL1=12 mA
• LOW output average current (in a period of 100 ms) (Note 2)
12 mA × 10 ms × 5
= 6 mA < 10 mA
100 ms
P0
2
I
OL2=12 mA
7480 Group
7481 Group
Shaded areas: Maximum ratings
Notes 1: LED (VF = 2 V) used.
2: Turn-on timing of LEDs connected to port pins P00, P01 and P02 (50% duty cycle).
10 ms
10 ms
Turned on for 10 ms, five times in a 100-ms period.
Figure 2.1.1 External Circuit for Output Ports
7480 Group and 7481 Group User's Manual
2-2
APPLICATIONS
2.1 Input/Output Pins
(2) Simplifying External Circuit Example by Using Level Shift Port and Noise Margin
POINT: Ports P4 and P5 have N-channel open-drain outputs. Built-in clamping diodes allow voltages
VCC or more to be applied to port pins when the current for a pin is 1 mA or less.
Voltages VIL = 0.4 VCC and VIH = 0.8 VCC can be applied to ports P3, P4, and P5 (at VCC
= 4.5 V 5.5 V).
Figure 2.1.2 shows a simplified external circuit example by using a level shift port and noise margin.
The former hardware
12 V power source (VCC
)
5 V power source
V
I
SW
7480 Group
7481 Group
Hardware using
level shift port
12 V power
SW
Port
V
IL
7480 Group
7481 Group
Ground voltage level
Max. 1.0 V
V
IL = SW ground voltage level (Max.) + V
F (Max.)
= 1.0 [V] + 1.0 [V]
= 2.0 [V] (Max.) ≤ 0.4 VCC
Figure 2.1.2 Simplified External Circuit Example by Using Level Shift Port and Noise Margin
7480 Group and 7481 Group User's Manual
2-3
APPLICATIONS
2.2 Timer X and Timer Y
2.2 Timer X and Timer Y
2.2.1 Application Example of Timer Mode
Generation of period of 100 ms (100-ms Periodic Processing)
POINT: The clock is divided by timer X, and the CPU performs periodic processing with a timer X
interrupt service routine generated every 100 ms.
SPECIFICATIONS: Clock: f(XIN) = 8 MHz
A timer X interrupt is generated every 100 ms using the timer mode of timer X.
Periodic processing is performed every 100 ms with timer X interrupt service
routine.
Figure 2.2.1 shows a setting example of the division ratio.
Figure 2.2.2 shows a control procedure example of 100-ms process.
Fixed division ratio
1/16
Timer X
00-ms periodic processing with
timer X interrupt service routine
1
f(XIN) = 8 MHz
1/50000
Figure 2.2.1 Setting Example of Division Ratio
7480 Group and 7481 Group User's Manual
2-4
APPLICATIONS
2.2 Timer X and Timer Y
RESET (Note 1)
Initialize
SEI
Set timer X mode register
b7
b0
× ×
TXM(Address 00F616
)
1
0
0 0 0
0
Timer • event count mode
Writing to latch and timer simultaneously
Timer X count source: f(XIN)/16
Timer X ← C34F16 (Note 2)
Timer X interrupt request bit ← 0
Timer X interrupt enable bit ← 1
Set Timer XY control register
b7
b0
0
TXYCON(Address 00F816
Timer X count started
)
CLI
errupt generated every 100 ms
mer X interrupt service routine
100-ms periodic processing
RTI
Processing
Notes 1: State after system is released from reset
• Timer X stop control bit = 1 (count stopped)
2: • C34F16 = 50000 – 1
• Write in order of low-order to high-order byte.
Figure 2.2.2 Control Procere Example of 100-ms Processing
7480 Group and 7481 Group User's Manual
2-5
APPLICATIONS
2.2 Timer X and Timer Y
2.2.2 Application Example of Event Count Mode
Measurement of Water Flow Rate
POINT: Pulses generated corresponding to the water flow rate are counted for a fixed period (100
ms), and the water flow rate during this period is calculated.
SPECIFICATIONS: Clock: f(XIN) = 8 MHz
Pulses generated corresponding to the water flow rate are input to the CNTR1
pin and counted using the event count mode of timer Y.
The contents of timer Y are read in the timer X interrupt service routine generated
after 100 ms from the start of counting pulses, and the water flow rate during
100 ms is calculated.
Figure 2.2.3 shows a peripheral circuit example.
Figure 2.2.4 shows the method of measuring water flow rate.
Figure 2.2.5 shows the control procedure example of measuring wow rate.
For the setting example of division ratio from timer X, refer to 2.1.
7480 Group
7481 Group
Water flow rate sensor
Water flow
P41/CNTR1
Blades rotate in proportion to
Thater flow,
water flow and generate pulses. e pulse period.
Figure 2.2.3 Peripheral Circuit
100 ms
Timer X interrupt request bit
CNTR1 input
Timer Y counting (Note).
Timer X, timer Y
start counting.
Timer X interrupt service routine
• Timer X, timer Y stop counting.
• Timer Y is read out.
Note: Counting rising edges.
• Flow rate during 100 ms = (FFFF16 – read value of timer Y) × flow rate per pulse
Figure 2.2.4 Method of Measuring Water Flow Rate
7480 Group and 7481 Group User's Manual
2-6
APPLICATIONS
2.2 Timer X and Timer Y
Flow rate measuring routine
Timer X interrupt enable bit ← 0
Timer Y interrupt enable bit ← 0
Set timer XY control register
b7
b0
1 1
TXYCON(Address 00F816
Timer X count stop
)
Timer Y count stop
Port P4
1
(alternative function of CNTR
1) is set to input.
CNTR
1 edge selection bit ← 0
(counting rising edges)
Set timer X mode register
b7
1
b0
0
0
0 0 0
× ×
TXM(Address 00F616
)
Timer • event count mode
Writing to latch and timer simultaneously
Timer X count source: f(XIN)/16
Set timer Y mode register
b7
1
b0
0
× ×
TYM(Address 00F716
)
1
0 0 0
Timer • event count mode
Writing to latch and timer simultaneously
Timer Y count source: CNTR1 pin input
Timer Y ← FFFF16 (Note 1)
Timer X← C34F16 (Note 2)
Timer X interrupt service routine
Timer X interrupt request bit ← 0
Timer Y interrupt request bit ← 0
Timer X interrupt enable bit ← 1
Set timer XY control register
b7
b0
1
1
Set timer XY control register
TXYCON(Address 00F816
)
b7
b0
Timer X count stop
Timer Y count stop
0 0
TXYCON(Addres
Timer X count
Timer Y cou
Timer Y is read out (Note 3).
RTI
Note 1: • Initial value.
• Write to timer Y in order of low-order to high-order byte.
2: • C34F16 = 50000 – 1.
• Write to timer X in order of low-order to high-order byte.
3: • (FFFF16 – the read value of Timer Y) = the number of CNTR
edges detected during 100 ms.
1
• Read from timer Y in order of high-order to low-order byte.
Figure 2.2.5 Control Procedure Example of Measuring Water Flow Rate
7480 Group and 7481 Group User's Manual
2-7
APPLICATIONS
2.2 Timer X and Timer Y
2.2.3 Application Example of Pulse Output Mode
Piezoelectric Buzzer Output
POINT: The pulse output mode of a 16-bit timer is used for buzzer output.
SPECIFICATIONS: Clock: f(XIN) = 8 MHz
4 kHz pulses are output from the CNTR0 pin using the pulse output mode of
timer X.
CNTR0 pin output level is fixed to HIGH while the buzzer output is stopped.
Figure 2.2.6 shows a peripheral circuit example.
Figure 2.2.7 shows a setting example of the division ratio.
Figure 2.2.8 shows a control procedure example of buzzer output.
7480 Group
7481 Group
Outputs HIGe buzzer output is stopped.
CNTR
0
pin
P40/CNTR0
Buzzer
output
µs 125 µs
t the division ratio to make the timer X
underflow period 125 µs.
Figure 2.2.6 Peripheral Circuit Example
Fixed division
X
1/125
125 µs
250 µs
CNTR0 pin outputs 4-kHz pulses.
f(XIN)=8MHz
1/8
1/2
Pulse output mode inverts the
output level of the CNTR pin.
0
Figure 2.2.7 Setting ExDivision Ratio
7480 Group and 7481 Group User's Manual
2-8
APPLICATIONS
2.2 Timer X and Timer Y
RESET(Note 1)
Initialize
SEI
Port P4
Port P4
0
(alternative function of CNTR0) ← HIGH
0
(alternative function of CNTR
0) is set to output.
CNTR edge selection bit ← 0 (Note 2)
0
Set timer X mode register
b7
0
b0
1
×
×
0
1
0 0
TXM(Address 00F616
Pulse output mode
)
Writing to latch and timer simultaneously
Timer X count source : f(XIN)/8
Timer X ← 007C16(Note 3)
CLI
Processing
Buzzer output processing
Buzzer output requested ?
N
N
Y
Timer X count operating ?
Timer X count stopped ?
Y
Y
Set timer XY control register
b7
b0
1
TXYCON(Address 00F816
Timer X count stop
)
Set timer XY control regist
b7
b0
0
ress 00F816
ount start
)
Timer X ← 007C16 (Note3)
Processing
Notes 1: State after system is released from reset
• Timer X stop control bit = 1 (count stop)
2: In pulse output mode, the output level of CNTR0 pin is initialized to
HIGH by writing to timer X (writing to latch and timer simultaneously).
3: • 007C16 = 125–1
• Write to timer X in order of low-order to high-order byte.
• The output level of CNTR
0 pin is initialized by writing to timer X
(writing to latch and timer simultaneously).
Figure 2.2.8 Control Procedure Example of Buzzer Output
7480 Group and 7481 Group User's Manual
2-9
APPLICATIONS
2.2 Timer X and Timer Y
2.2.4 Application Example of Pulse Period Measurement Mode
Phase Control of Load (Measuring Period of Feedback Signal)
POINT: The period of the feedback signal input from the load is measured using the pulse period
measurement mode of a 16-bit timer.
SPECIFICATIONS: Clock: f(XIN) = 8 MHz
Phase control signal is output to the load and controls the load’s phase.
The period of the feedback signal input to the CNTR0 pin from the load is
measured using the pulse period measurement mode of timer X.
• Count source: f(XIN)/16
The period of the feedback signal is analyzed to adjust the phase control signal
input to the load.
For the output of the phase control signal, refer to Section 2.2.7 Applicatin Example of Programmable
One-shot Output Mode.
Figure 2.2.9 shows a peripheral circuit example.
Figure 2.2.10 shows a phase control procedure example.
p
roup
Feedback signal
/CNTR0
Load
Phanal
Port
VAC
Figure 2.2.9 Peripheral Cxample
7480 Group and 7481 Group User's Manual
2-10
APPLICATIONS
2.2 Timer X and Timer Y
RESET(Note 1)
Initialize
SEI
Port P4
0
(alternative function of CNTR0) is set to input.
CNTR0 edge selection bit ← 0
(measuring a period from rising until the next rising edge)
Set timer X mode register
b7
b0
× ×
×
0
1 0
1 0
TXM(Address 00F616
)
Pulse period measurement mode
Timer X count source: f(XIN)/16
CNTR
0
interrupt request bit ← 0
interrupt enable bit ← 1
CNTR
0
Set timer XY control register
b7
b0
0
TXYCON(Address 00F816
Timer X count start
)
CLI
When detecting rising edge input to CNTR
CNTR interrupt service routine
0 pin
0
Processing
Phase control processing
• Period of feedback signal anal
• Phase control signal adjust
Timer X is read out (Note 2).
Process
END
Notes 1: State after system is released from reset
• Timer X stop control bit = 1 (count stop)
• Timer X interrupt enable bit = 0 (disabled)
2: Read from timer X in order of high-order to low-order byte.
Figure 2.2.10 Phase Control Procedure Example
7480 Group and 7481 Group User's Manual
2-11
APPLICATIONS
2.2 Timer X and Timer Y
2.2.5 Application Example of Pulse Width Measurement Mode
Communications between Two Microcomputers (Reception)
POINT: 8-bit data is received by measuring each bit’s HIGH-level width input to the CNTR pin and
identifying each bit data.
SPECIFICATIONS: Clock: f(XIN) = 8 MHz
The HIGH-level width of CNTR0 pin input is measured using the pulse width
measurement mode of timer X.
• Count source: f(XIN)/8
The start, stop bits and each bit data of 8-bit receive data are identified by the
measured values of the HIGH-level widths.
Figure 2.2.11 shows a peripheral circuit example.
Figure 2.2.12 shows a communication format example.
Figure 2.2.13 shows a communication control procedure example.
Group
81 Group
(Receiver)
Microcomputer (transmitter)
Data
P40/CNTR0
Figure 2.2.11 Peripheral Circuit Exa
8-bit data
Start
Stop
pulse
pulse
D1
=1
D2
=0
D7=1
0.35 ms
0.35 ms
0.15 ms
0.75 ms
0.55 ms
0.1ms
0.05 ms
Longest communication time ≈ 4.6 ms
Shortest communication time ≈ 3.0 ms
Data pulse‘0’: HIGH level output for 0.15 ms
Data pulse‘1’: HIGH level output for 0.35 ms
Start pulse: HIGH level output for 0.55 ms
Stop pulse: HIGH level output for 0.75 ms
(The LOW levels are output for 0.05 ms or more before
and after each pulse.)
Figure 2.2.12 Communication Format Example
7480 Group and 7481 Group User's Manual
2-12
APPLICATIONS
2.2 Timer X and Timer Y
RESET(Note 1)
Initialize
SEI
Port P4
0
(alternative function of CNTR0) is set to input.
CNTR
0
edge selection bit ← 0(HIGH width measured)
Set timer X mode register
b7
b0
× × ×
0
1
0 1
1
TXM(Address 00F616
)
Pulse width measurement mode
Timer X count source: f(XIN)/8
Timer X interrupt service routine processing
Timer X interrupt request bit ← 0
CNTR interrupt request bit ← 0
0
Error-recovery
Timer X interrupt enable bit ← 1
CNTR interrupt enable bit ← 1
0
Set timer XY control register
b7
b0
0
TXYCON(Address 00F816
Timer X count start
)
: Carry Flag
TA : RAM for received data (1 byte)
ORK : RAM for receiving data (2 bytes)
COUNT : RAM for counting data (1 byte)
CLI
RTI
1: After system is released from reset
• Timer X stop control bit = 1 (count stopped)
• CNTR
• Pin P4
0
edge selection bit = 0 (HIGH pulse width measured)
/CNTR : input mode
0
0
2: Read from timer X in order of high-order to low-order byte.
3: 100 to 199 (Data pulse ‘0’)
CNTR0 interrupt service routine
4: 300 to 399 (Data pulse ‘1’)
5: 500 to 599 (Start pulse)
6: 700 to 799 (Stop pulse)
Timer X is read out
Read value fr
006416 throug
012C16 through018F16 (Note 4)
01F416 through 025716 (Note 5)
02BC16 through 031F16 (Note 6)
Others
C←0
C←1
rWORK←0016
rCOUNT←0016
N
rCOUNT = 8 ?
ROR rWORK
Y
rDATA←rWORK
b7
b0
Processing against
error generation
C
rWORK(Internal RAM)
rCOUNT←rCOUNT +1
RTI
Figure 2.2.13 Communications Control Procedure Example
7480 Group and 7481 Group User's Manual
2-13
APPLICATIONS
2.2 Timer X and Timer Y
2.2.6 Application Example of Programmable Waveform Generation Mode
Control of Motorcycle Single-Cylinder Engine
POINT: A trigger input to the INT pin automatically starts a timer counting. This allows the CNTR pin
output to be changed with a more accurate timing than counting is started in an INT interrupt
service routine.
SPECIFICATIONS: Clock: f(XIN) = 8 MHz
A rise-to-rise period of a crank angle signal input to the CNTR0 pin is measured
using the pulse period measurement mode of timer X to determine the correction
value of timer Y.
The trigger of the crank angle signal input to the INT1 pin makes timer Y
activated. Then, the control signal of the igniter is output from the CNTR1 pin
using the programmable waveform generation mode.
For the pulse period measurement of the crank angle signal, refeection 2.2.4 Application
Example of Pulse Period Measurement Mode.
Figure 2.2.14 shows a peripheral circuit example.
Figure 2.2.15 shows an operation timing example.
Figure 2.2.16 shows a control procedure example of mengine.
80 Group
7481 Group
Motorcycle single-cylinder engine
Phase c
Igniter
P41/CNTR1
Crank angle input
P40/CNTR0
P31/INT1
Figure 2.2.14 Peripheral Circule
vated
Timer Y activated
Timer Y activated
INT
1
pin input
pin input
CNTR
0
(Crank angle signal)
T
TL0 set 1
TL1set 2
Count stop 5
Initial value set 6
RL
UF
RL
RL
UF
RL
RL
UF
RL
UF
RL
Initial
value
000016
UF
UF
UF
3
4
Timer Y
output
level latch
CNTR
1 pin output
(Igniter control signal)
: Measured with pulse period measurement mode of timer X
: The written value to timer Y to correct HIGH output time of
the CNTR1 pin (determined by measured value T).
: The written value to timer Y to output LOW time of the CNTR
(determined by measured value T).
T
TL0
: Underflow
: Reload
UF
RL
1 pin
TL1
Figure 2.2.15 Operation Timing Example
7480 Group and 7481 Group User's Manual
2-14
APPLICATIONS
2.2 Timer X and Timer Y
INT1 Interrupt service routine
RESET(Note 1)
Initialize
SEI
Change timer Y (Note 3) ➀
RTI
Port P40 (alternative function of CNTR0) is set to input.
Port P41 (alternative function of CNTR1) is set to output.
Timer Y interrupt service routine
INT1 edge selection bit ← (rising edge detected)
CNTR0 edge selection bit ← (rise-to-rise period detected)
After INT1 edge detected,
first timer Y interrupt occurs?
N
Set timer X mode register
b7
b0
TXM(Address 00F616)
× ×
×
0
Y
1 0
Change timer Y (Note 3) ➁
Pulse period measurement mode
Timer X count source selected
Change timer Y output level latch ➂
b7
b0
Set timer Y mode register (Note 2)
1
0 1 1 0
(Address 00F716)
level latch
b7
b0
1
1 0 1 0
0
TYM (Address 00F716)
Programmable waveform
generation mode
edge detected,
timer Y interrupt occurs?
N
Writing to latch and timer simultaneously
Output level latch
Timer Y activated by input signal
to INT1 pin
Timer Y count source selected
Y
timer Y output level latch ➃
b0
Timer Y ← Initial value (Note 3)
1
1 1 1 0
0
TYM (Address 00F716)
Output level latch
Control timer Y writing
b7
b0
1
1 1 1 0
0
TYM (Address 00F716)
Writing to latch only
After INT1 edge detected,
third timer Y interrupt occurs?
N
Set timer XY control register
Y
b7
b0
0
0
TXYCON (Addres
Stop timer Y counting ➄
b7
b0
Timer X count
TXYCON (Address 00F816)
Timer Y count stop
1
0
Timer Y co4)
Control timer Y writing
b7
b0
Timer Y interr← 0
INT1 interrbit ← 0
Timer Y interrupt enable bit ← 1
INT1 interrupt enable bit ← 1
1
1 0 1 0
0
TYM (Address 00F716)
Writing to latch and timer
simultaneously
Timer Y ← Initial value (Note 3) ➅
Control timer Y writing
CLI
b7
b0
1
1 1 1 0
0
TYM (Address 00F716)
Writing to latch only
Start Timer Y counting
Processing
b7
b0
TXYCON (Address 00F816)
0
0
Timer Y count start (Note 4)
Notes 1: State after system is released from reset
• Timer X and Y stop control bits = 0 (count stopped)
• Timer Y and INT1 interrupt enable bits = 0 (disabled)
2: The output level of CNTR1 pin is initialized to LOW.
3: Write to timer Y in order of low-order to high-order byte.
4: In this time, timer Y remains still stopped.
RTI
Figure 2.2.16 Control Procedure Example of Motorcycle Engine
7480 Group and 7481 Group User's Manual
2-15
APPLICATIONS
2.2 Timer X and Timer Y
2.2.7 Application Example of Programmable One-Shot Output Mode
Phase Control of Load (Output of Phase Control Signals)
POINT: The phase control signal to the load is output using the programmable one-shot output mode
of a 16-bit timer.
SPECIFICATIONS: Clock: f(XIN) = 8 MHz
The phase control signal to the load is output from the CNTR1 pin using the
programmable one-shot output mode of timer Y.
• Count source: f(XIN)/16
• Rising edges of the signal input to the INT1 pin from the trigger detection
circuit are detected.
• A triac is turned on at the HIGH level.
The period of the feedback signal input from the load is measured, analyzed,
and used to adjust the phase control signal.
For the measurement of the period of the feedback signal, rection 2.2.4 Application
Example of Pulse Period Measurement Mode.
Figure 2.2.17 shows a peripheral circuit example.
Figure 2.2.18 shows an operation timing example.
Figure 2.2.19 shows a phase control procedure exam
7480 Group
7481 Group
signal
Port
Load
Phase control signal
P4
1
/CNTR
1
Trigger detection
circuit
P3
1
/INT
1
Figure 2.2.17 Peripheral it Example
VAC power supply
INT1
pin input
Writing to latch in
timer Y interrupt
service routine
RL
RL
RL RL
RL RL
RL
UF
RL
RL
UF
RL
RL
UF
RL
000016
UF
UF
UF
CNTR
1
pin output
Figure 2.2.18 Operation Timing Example
7480 Group and 7481 Group User's Manual
2-16
APPLICATIONS
2.2 Timer X and Timer Y
RESET(Note 1)
INT1 interrupt service routine
Initialize
SEI
Change timer Y (Note 3)
Port P4
1
(alternative function of CNTR1) ← LOW
RTI
Port P4
1
(alternative function of CNTR1) is set to output.
INT
CNTR
1
edge selection bit ← 1 (rising edge detected)
edge selection bit ← 0 (Note 2)
1
Set timer Y mode register
b7
b0
× ×
1 0
1 1 0 1
TYM(Address 00F716
)
Programmable one-shot output mode
Writing to latch only
Timer Y count source : f(XIN)/16
Timer Y ← Initial value (Note 3)
Set timer XY control register
b7
b0
TXYCON(Address 00F816
Timer Y count start
)
0
INT
1
interrupt request bit ← 0
interrupt enable bit ← 1
CLI
INT
1
Proces
Phase control pr
• Period of feeeasured
• Measured d
(determY setting value)
Processing
Notes 1: State after system is released from reset
• Timer Y stop control bit = 0 (count stop)
• Timer Y interrupt enable bit = 0 (disabled)
2: HIGH level one-shot pulse is output.
3: Write to timer Y in order of low-order to high-order byte.
Figure 2.2.19 Phase Control Procedure Example
7480 Group and 7481 Group User's Manual
2-17
APPLICATIONS
2.2 Timer X and Timer Y
2.2.8 Application Example of PWM Mode
Output of Analog Voltage
POINT: Analog voltage is output using the PWM waveform.
SPECIFICATIONS: Clock: f(XIN) = 8 MHz
PWM waveforms are output from the CNTR0 pin using the PWM mode of timer
X.
• Count source: f(XIN)/16
• The duty cycle of PWM waveforms is determined depending on analog voltage
output.
PWM waveforms are converted into the analog voltage using the external circuit
to the CNTR0 pin.
Figure 2.2.20 shows a peripheral circuit example.
Figure 2.2.21 shows a control procedure example of analog voltagput.
7480 Group
7481 Group
HH
HL
V
CC
VCC
VSS
H
H
P40
/CNTR
0
VCC ×
HH+HL
VSS
Figure 2.2.20 Peripheral Circuit Ex
7480 Group and 7481 Group User's Manual
2-18
APPLICATIONS
2.2 Timer X and Timer Y
Analog voltage output routine
Set timer XY control register
b7
b0
1
TXYCON(Address 00F816)
Timer X count stop
Set port P40 (alternative function of CNTR0) (Note).
Port P40 (alternative function of CNTR0) is set to output.
Set Timer X Mode Register
b7
b0
× ×
0 1 1 0
TXM(Address 00F616)
PWM mode
Writing to latch and timer simultaneously
Timer X count source selected
Set Timer X low-order byte (LOW width)
Set Timer X high-order byte (HIGH width)
Set Timer XY Control Register
b7
b0
0
TXYCON(Address 00F816)
Timer X count start
END
Note: The output analog voltage is initir VCC).
• The same potential as VSS to P40/CNTR0 pin is set to ‘0’.
• The same potential as VC: P40/CNTR0 pin is set to ‘1’.
Figure 2.2.21 Control Procedure Examnalog Voltage Output
7480 Group and 7481 Group User's Manual
2-19
APPLICATIONS
2.3 Serial I/O
2.3 Serial I/O
2.3.1 Application Example of Clock Synchronous Serial I/O Transmission
Successive Transmission
POINT: Successive transmission is performed by generating a serial I/O transmit interrupt when the
transmit buffer register is emptied, as well as by generating a serial I/O transmit interrupt
request when serial I/O transmission is initialized to ‘enable’ by using the serial I/O control
register (Note).
Note: Refer to Using Serial I/O Transmit Interrupt and Serial I/O Receive Interrupt of (5)
Notes on Usage of Clock Synchronous Serial I/O in Section 1.14.2 Clock
Synchronous Serial I/O.
SPECIFICATIONS: Clock: f(XIN) = 7.9872 MHz
5-byte successive transmission using clock ous serial I/O
• Baud rate: 2400 bps
• Synchronous clock: a frequency of 2.btained from dividing f(XIN) is
output from the SCLK pin.
• The completion of communicatiation at the receiver is recognized
using port pin P17 as the SRinput pin.
Figure 2.3.1 shows a connections example.
Figure 2.3.2 shows a setting example of th
synchronous clock.
P15/TxD
P16/SCLK
P17/SRDY
RxD
SCLK
SRDY
Figure 2.3.3 shows the timing of int
control. Figure 2.3.4 shows a control p
example of serial I/O transmit.
Microcomputer
(Receiver)
7480 Group
7481 Group
Figure 2.3.1 Connection Example
BRG count source
selection bit
‘0’
Baud rate
generator
f(XIN) = 7.9872 MHz
1/4
Clock
generator
Synchronous clock
2.4 kHz
1/52
1/4
‘1’
BRG
output
1/4
Baud rate : 2400bps
Figure 2.3.2 Setting Example of Synchronous Clock
7480 Group and 7481 Group User's Manual
2-20
APPLICATIONS
2.3 Serial I/O
1st byte transmitted 3rd byte transmitted
5th byte transmitted
1st byte transmitted
2nd byte transmitted
Setting of serial I/O
control register
2nd byte transmitted 4th byte transmitted
Serial I/O transmUitndefined
interrupt request bit
A
B
A
B A
B A
B A
B
A
B A
Write ‘0’
Write ‘1’
Write ‘1’
Serial I/O transmit
interrupt enable bit
Execute CLI
instruction
Transmission requested
5-byte transmission completed
Transmission requested
Interrupt disable flag
: Processed within serial I/O transmit interrupt service routine.
: Cleared by the acceptance of serial I/O transmit interrupt request.
System is released from reset.
A
B
: Interrupt request generated with transmitter buffer register emptied.
Figure 2.3.3 Timing of Interrupt Control
RESET(Note 1)
Serial I/O transmit interrrvice routine
Initialize
SEI
N
OW ?
Port P17 is set to input.
Baud rate generator ← 3316 (Note 2)
Set serial I/O control register (Note 3)
Y
er register ← BUFF_p(Note 4)
added to pointer p for BUFF.
b7
b0
p ← p + 1
1
1 0 1 0 0 0
1
SIOCON (Address 00E216)
BRG count source: f(XIN)/16
Synchronous clock:
BRG output divided by 4
N
p ≥ 5 ?
SRDY output disabled
Transmit interrupt so
Y
Serial I/O transmit interrupt enable bit ← 0
Transmission buffer re
Transmit enabl
Receive disa
Clock synl I/O
Serial I/
RTI
Transmit processing
5-byte transmission data is stored
to buffer area (BUFF)
Pcessing
BUFF_0 ← Transmission data 0
BUFF_1 ←
Transmission data 1
• • •
BUFF_4 ← Transmission data 4 (1st byte)
Y
Transmission requested ?
N
Initialize pointer p for BUFF
p ← 0
Serial I/O transmit interrupt enable bit ← 1
Processing
Serial I/O transmit interrupt
BUFF: 5-byte buffer area
BUFF_0 to BUFF_4
Notes 1: State after system is released from reset
• Serial I/O transmit interrupt enable bit = 0
• Serial I/O receive interrupt enable bit = 0
2: 3316 = 52–1
3: In this time, serial I/O transmit interrupt request bit is 1.
4: Transmit/receive is started by writing to transmit buffer register.
Figure 2.3.4 Control Procedure Example of Serial I/O Transmit
7480 Group and 7481 Group User's Manual
2-21
APPLICATIONS
2.3 Serial I/O
2.3.2 Application Example of Clock Asynchronous Serial I/O (UART) Reception
Processing of Received Data Bytes as a Packet
POINT: RAM area is secured by adding the several bytes to the maximum number of bytes necessary
for data processing, and the received data is stored in increasing order of address in the
interrupt service routine. If the data overflows the RAM area, the overflow data is stored at
the start address of the RAM.
When the received data whose byte number satisfies the requirement of data processing is
stored completely in the buffer area, the data processing is performed in the main routine.
As a result, the received data can be stored without losing any bits of data in process even
when the subsequent received data is stored completely during the data processing.
SPECIFICATIONS: Clock: f(XIN) = 7.9872 MHz
UART reception
• Baud rate : 9600 bps
• Synchronous clock : f(XIN) is divided into 9z
• Communication format: 1ST-8DATA-1SP
Processing received data as a packet
The head data of every packet consiscode characteristic for the head
data and the code indicating the nbytes of the packet.
Figure 2.3.5 shows a connection example.
Figure 2.3.6 shows the setting example of the
synchronous clock.
TxD
Figure 2.3.7 shows a communication form
Figure 2.3.8 shows a control procedure ex
of serial I/O receive.
P14/RxD
Microcomputer
(Transmitter)
7480 Group
7481 Group
(Receiver)
Figure 2.3.5 Connection Example
BRG count source
Baud rate
generator
selection bit
‘0’
f(XIN) = 7.9872 MHz
4
Clock
generator
Synchronous clock
9.6 kHz
1/13
1/16
BRG output
‘1’
1/4
Baud rate : 9600bps
Figure 2.3.6 Setting Example of Synchronous Clock
Transmit data (1ST-8DATA-1SP)
LSB
Start bit
Data bit (i = 0 to 7)
Stop bit
ST:
Di:
SP:
N:
MSB
ST
D0
D
1
D
6
D7
SP
The number of bytes of the packet
1st byte
(n – 1)th byte
Head data
: Consists of the code characteristic for the head data
and the code indicating the number of bytes of
the packet.
1 packet (N bytes)
Figure 2.3.7 Communication Format
7480 Group and 7481 Group User's Manual
2-22
APPLICATIONS
2.3 Serial I/O
RESET (Note 1)
Initialize
RAM area
SEI
BUFF_0
BUFF_1
Pointer for writing to BUFF (pw) ← 0016
Pointer for reading from BUFF (pr) ← 0016
Write receive data in serial I/O
receive interrupt service routine
BUFF_pw
BUFF_pr
Baud rate generator ← 0C16 (Note 2)
Set serial I/O control register
b7
b0
Head data of the packet
N-byte buffer area
1 0 1
0
0 0
× ×
SIOCON (Address 00E216
)
BRG count source : f(XIN)/4
Synchronous clock : BRG output divided by 16
Transmit disabled
BUFF_(N–2)
BUFF_(N–1)
Receive enabled
Clock asynchronous serial I/O
Serial I/O enabled
Set UART control eegister
b7 b0
0
0 0
UARTCON (Address 00E316
×
)
Serial I/O recervice routine
Character length bit : 8 bits
Parity disabled
Stop bit length : 1 bit
ceive buffer register
UFF_pw ← Read data
Serial I/O receive interrupt request bit ← 0
Serial I/O receive interrupt enable bit ← 1
CLI
N
Processing head data received?
Y
Analyze the number of bytes of the packet
Processing
i ← 0016
pr = pw
N
pr ≠ pw and i = the num
of the packet ?
i ← i + 1
• The contents of pr annumbers of bytes
packet is stored in anotin order not to
destroy them.
pr ← pr + 1
• Processing for 1 packet data from BUFF_pr
N
pr ≥ N?
i ← 0016
Y
pr ← 0016
pr = pw
Processing
RTI
Notes 1: Processing after system is released from reset.
•Serial I/O receive interrupt enable bit = 0 (disabled)
2: 0C16 = 13–1
Figure 2.3.8 Control Procedure Example of Serial I/O Receive
7480 Group and 7481 Group User's Manual
2-23
APPLICATIONS
2.3 Serial I/O
2.3.3 Application Example of Bus Arbitration Interrupt
LAN Communications in Contention Bus System
POINT: In LAN communications with the contention bus system, the malfunction of transmission due
to bus collision is detected with a bus arbitration interrupt.
SPECIFICATIONS: Clock: f(XIN) = 7.9872 MHz
LAN communication format: Simplified SAE J1850 (PWM system)
The CNTR0 pin is connected to the RxD pin, and SOF is detected with the
rising edge of a CNTR0 pin input
Data is transmitted and received by clock synchronous serial I/O communications.
• Baud rate: 41600 bps
• Synchronous clock: f(XIN) is divided into 41.6 kHz
• Bus collision detected
The HIGH level has priority on LAN communicaion line at bus collision
Figure 2.3.9 shows a connection example.
Figure 2.3.10 shows a setting example of the synchronous c
Figure 2.3.11 shows a communication format example of E J1850.
Figure 2.3.12 shows a communication timing example.
Figures 2.3.13 and 2.3.14 show control procedure ex
Unit B
Unit C
nit D
LAN communication Line (+)
LAN communication Line (–)
Unit A
• Conflicts between unit A and unit B
H
Unit A
TxD pin output
L
P1
P1
/CNTR
5
/TxD
IN
–
H
L
Unit B
TxD pin output
4
/RxD
P4
0
0
ver
H
L
LAN communication line
(RxD pin input)
7480 Group
7481 Group
Bus collision
detected in unit B
Figure 2.3.9 Connection Example
BRG count source
selection bit
Baud rate
generator
f(XIN)=7.9872MHz
1/4
Clock
generator
‘0’
Synchronous clock
41.6 kHz
1/3
1/4
BRG output
‘1’
1/4
Baud rate : 41600bps
Figure 2.3.10 Setting Example of Synchronous Clock
7480 Group and 7481 Group User's Manual
2-24
APPLICATIONS
2.3 Serial I/O
1 frame
Max. 7 bytes
Data area
1 byte
Priority code
1 byte
1 byte
1 byte
1 byte
RSP code
SOF
Target ID
Source ID
CRC code
EOD
EOF
IFS
Transmit/Receive
Data Name
Function
Transmission/Reception
SOF
(Start of Frame)
Indicates the head of
the frame
• Fixed format of 6 time.
• Transmitter transmits ‘001111002’ with serial transmission.
• Receiver detects data with CNTR0 interrupt and recognizes with
pulse width measurement mode of timer X.
4 time
2 time
H
L
When transmitting
Priority
Code
Code for priority
control in multi-unit
transmission
• 1 bit represented by 3 time (1 byte represented bytes).
• Both transmitter and receiver communicate wI/O.
• Priority code: ‘0016’ (high priority) through riority).
3 time
3 time
me
H
L
H
L
Target ID
ID number of
target unit
When transmitting ‘0’
When
Data
Transmit data 1
b7
b0
mit
Source ID
Data Area
CRC Code
ID number of
transmit unit
D5
1
0
0
D6
1
0 D7
1
ata
enerated
1 byte
Transmit data 2
b7
b7
b0
Transmit data
D7 D6 D5 D0
1
D3
1
0
D4
1
0
Transmit data 3
0 D1 0 D2
Code for error
detection
b7
b0
0 D0
1
1
transmit
RSP Code
Receiver transmits
self-address if data
correctly received
error detection
Transmit data 1
Transmit data 2
Transmit data 3
L
D7
D6
D5
D4
D3
D2
D1
D0
EOD
(End of Data)
• Fixed format of 3 time.
• Both transmitter and receiver generate a wait time with timer 1.
Indicatf
data
3 time
EOF
(End of Frame)
Indicates he end of
frame
H
L
IFS
(Inter-Frame
Separation)
Indicates the
separation between
frames
• Fixed format of 6 time.
• Both transmitter and receiver generate a wait time with timer 1.
6 time
H
L
Figure 2.3.11 Communication Format Example of Simplified SAE J1850
7480 Group and 7481 Group User's Manual
2-25
APPLICATIONS
2.3 Serial I/O
• When unit A, unit B, and unit C start transmitting simultaneously
Priority code
‘01××××××2’
SOF
Target ID
0
1
H
L
Unit A
TxD pin output
Writing ‘0011110016’ to
transmit buffer register
for SOF transmission
Bus collision detected
Transmit processing
completed
Successive writing dummy
Receive processing completed
after recognizing that target ID
is not source ID of unit A.
data ‘0016’ to transmit buffer
register for reception of target
ID to CRC code
Receive processing start
Target ID
Priority code
‘00××××××2’
‘1×××××××2’
EOD RSP code EOF
IFS
SOF
0
0
1
H
Unit B
TxD pin output
L
Writing ‘0011110016’ to
transmit buffer register
for SOF transmission
Bus collision detected
Transmit processing
completed
Successive writing dummy
data ‘0016’ to transmit buffer
register for reception of source
ID to CRC code after
recognizing that target ID is
source ID of unit B.
Receive
processing
completed
Whrect reception is
ccode, writing
nsmit buffer register
.
Receive processing start
Target ID
data
code
Priority code
‘00××××××2’
‘0×××××××
(Transmit to
EOD RSP code EOF
IFS
SOF
0
0
0
H
Unit C
TxD pin output
L
Writing ‘0011110016’ to
transmit buffer register
for SOF transmission
Transmit
processing
completed
Successive writing 3 times
dummy data ‘0016’ to
transmit buffer register
for reception of RSP code
Units other than units A, B and C
start receive processing at the
Source ID
transmit data
CRC code
rising edge of CNTR0 pin
EOD RSP code EOF
IFS
SOF
y code
Target ID
0
LAN
H
communication line
(RxD pin input)
L
Receive processing completed
after recognizing that target ID is not
source ID of units other than unit B.
Communication
completed
Units other than units A, B and C
write successively dummy data ‘0016
’
to transmit buffer register
for reception of priority code to CRC code
Figure 2.3.12 Communication Timing Example
7480 Group and 7481 Group User's Manual
2-26
APPLICATIONS
2.3 Serial I/O
Transmit service routine
RESET(Note 1)
Initialize
SEI
When transmit is started
• Transmit data generated
(1 byte represented by 3 bytes)
• Bus arbitration interrupt request bit ← 0
• Bus arbitration interrupt enable bit ← 1
• CNTR0 interrupt enable bit ← 0
Port P40 (alternative function of CNTR0 pin) is set to input.
CNTR0 edge selection bit ← 1
• SOF transmission (writing to transmit buffer register)
(Rising edge active)
When EOD is output, waiting time is generated
(Note 3)
After EOD waiting time elapses, RSP code is received
(writing dummy data to transmit buffer register)
After receiving RSP code, EOF and IFS are output and
waiting time is generated (Note 3)
After EOF/IFS waiting time elapses
(when transmit completed)
Baud rate generator ← 0216 (Note 2)
Set serial I/O control register (Note 3)
b7
1
b0
1
SIOCON (Address 00E216)
1 1 1 0 0 0
• Bus arbitration interrupt enable bit ← 0
• CNTR0 interrupt request bit ← 0
• CNTR0 interrupt enable bit ← 1
BRG count source: f(XIN)/16
Synchronous clock:
BRG output divided by 4
SRDY output disabled
Transmit interrupt source:
Transmission buffer register is empty.
Transmit enabled
END
Receive enabled
Clock synchronous serial I/O
Receive
Serial I/O enabled
After SOF pleted
• CNTRle bit ← 0
Wheto CRC code, and RSP code
ar
Bus collision detection enable bit ← 1
data is converted to 1-byte data.
cessing is completed after recognizing
ived target ID is not self ID.
EOD is detected, EOD waiting time is
erated (Note 3)
Serial I/O transmit interrupt request bit ← 0
Serial I/O receive interrupt request bit ← 0
CNTR0 interrupt request bit ← 0
hen the correct reception is checked by CRC code
after EOD waiting time elapses, RSP code is
transmitted (writing to transmit buffer register)
After transmitting RSP code, EOF and IFS
waiting time is generated (Note 3)
After EOF/IFS wait time elapses
Serial I/O transmit interrupt enable bit ← 1
Serial I/O receive interrupt enable bit ← 1
CNTR0 interrupt enable bit ← 1
CLI
(when receive completed)
• CNTR0 interrupt request bit ← 0
• CNTR0 interrupt enable bit ← 1
Proce
END
Y
Y
During transreception ?
N
During transmitting
During receiving
Transmit service routine
Receive service routine
Transmission requested ?
N
Notes 1: State after system is released from reset
• Bus arbitration interrupt enable bit = 0
2: 0216 = 3–1
Processing
3: Waiting time is generated by timer 1.
4: Write ‘0016’ as dummy data to transmit buffer register.
Figure 2.3.13 Control Procedure Example (1) of LAN Communications
7480 Group and 7481 Group User's Manual
2-27
APPLICATIONS
2.3 Serial I/O
Serial I/O transmit interrupt service routine
Serial I/O receive interrupt service routine
When transmitting
Write the following transmit data to transmit buffer
register by the byte at one interrupt processing
1. Priority code
2. Target ID
3. Source ID
4. Data
When transmitting
Transmit data is received
When RSP code is received
When receiving
Read receive buffer register
1. Priority code
5. CRC code
2. Target ID
3. Source ID
4. Data
5. CRC code
Level of RxD pin is checked every 3-byte reception
• HIGH level: next data is received
• LOW level: EOD is detected
In the interrupt processing after writing transmit data
to transmit buffer register is completed, change
transmit interrupt source to ‘when transmit shift
operation is completed’, and the interrupt source is
back to the state before changing at the next interrupt
processing.
When receiving
Write dummy data to transmit buffer register
RTI
RTI
Bus arbitration interrupt service routine
CNTR0 interrupt (when receiving)
When rtected
• CNtion bit ← 0
(tected)
measured with timer X
edge is detected
edge selection bit ← 1
When SOF collision occurs, transmit processing is
stopped and receive processing is started from
priority code.
When priority code collision occurs,
transmit processing is stopped and receive
processing is started from target ID.
g edge detected)
When data collision occurs, communication error on
communication line is detected, transmit processing i
stopped, and processing against error such as re-
transmission is performed.
W width is measured with timer X
SOF LOW width waiting time is generated with
timer 1 (acceptance of timer 1 interrupt request
is enabled)
Reception is completed when SOF is not received
correctly.
Bus arbitration interrupt enable bit ← 0
RTI
RTI
Timer 1 interrupt e routine
When SOF is received
• Write dummy data to transmit buffer register for
generating synchronous clock
• Acceptance of timer 1 interrupt request is disabled
Processing for EOD, EOF and IFS waiting time elapse
RTI
Note: Write ‘0016’ as dummy data to transmit buffer register.
Figure 2.3.14 Control Procedure Example (2) of LAN Communications
7480 Group and 7481 Group User's Manual
2-28
APPLICATIONS
2.4 A-D Converter
2.4 A-D Converter
2.4.1 Determination of A-D Conversion Values
In A-D conversion, it is recommended to determine conversion values using several samplings to improve
the accuracy of A-D conversion. Methods for sampling and determining A-D conversion values are described
below.
Sampling Methods
EXAMPLES: ➀ Sampling 2n times
➁ Running sampling 2n times
➂ Sampling (2n + 2) times
Notes 1: ‘n’ is a positive integer according to the specifications.
Determining Methods
EXAMPLES: ➀ The sum of the sampling result is divided by the of times of the sampling.
➁ Except the minimum and the maximum value, of the sampling (or running
sampling) results of (2n + 2) times is divide
➂ The average value calculated by ➀ or ➁ d unless the difference between
the previous and the newest value is ‘re.
Notes 2: ‘m’ and ‘n’ are positive integding to the specifications.
A method derived from these examples of samd determining is explained in Section 2.4.2
Application Example of A-D Converter.
7480 Group and 7481 Group User's Manual
2-29
APPLICATIONS
2.4 A-D Converter
2.4.2 Application Example of A-D Converter
POINT: To improve the accuracy of A-D conversion, A-D conversion values are determined by
Sampling Methods ➁ and ➂, and Determining Methods ➁ and ➂ of Section 2.4.1
Determination of A-D Conversion Values.
SPECIFICATIONS: After the running sampling has been taken 6 times, the sum of the sampling
results, except the minimum and maximum values, is divided by 4.
When the difference between the new average value and the previous updated
value is less than 5, the value is updated to the new value, when 5 or more,
the value is not updated.
Figure 2.4.1 shows the example of determining A-D conversion values.
Figure 2.4.2 shows the control procedure example of determining of A-D conversion values.
-D conversion result
(n+1)th
sampling
(n-3)th
sampling
n-th
sampling
(n-7)th
(n-6)th
sampling sampling
(n-4)th
sampling
)th
ampling
(n-5)th
sampling
Sampling point
A-D conversion result
A816
A716
A916
A816
A
M
A816
AB16
Maximum
Time
value
A916 + A816 + A716 + A816
4
Ave
= A816
Figure 2.4.1 Example of Determininnversion Values
7480 Group and 7481 Group User's Manual
2-30
APPLICATIONS
2.4 A-D Converter
A-D conversion routine
A-D conversion completion interrupt request bit ← ‘0’
Set A-D conversion control register
b7
b0
1
1 0 0 0
ADCON (Address 00D916
Analog input pin : P2 /IN
)
0
0
Connect between VREF pin
and ladder resistor
V
REF stabilizing wait time
Set A-D conversion control register
b7
b0
1
0 0 0 0 ADCON (Address 00D916
)
A-D conversion start
N
A-D conversion completed ? (Note)
Y
Average of 4-time samplings, which the maximum
value and the minimum value are excluded from
6-time samplings, is calculated.
The difference from previous
determined value is less than
Y
Update of determi
(The last calculated aveomes
the determ
ND
Note: Tn of A-D conversion is examined by the following.
ersion completion bit of A-D conversion control register is ‘1’.
nversion completion interrupt request bit of interrupt request register 1 is ‘1’.
ch to A-D conversion completion interrupt service routine is performed.
hen A-D conversion completion interrupt is enabled)
Figure 2.4.2 Control Procedure Example of Determining A-D Conversion Values
7480 Group and 7481 Group User's Manual
2-31
APPLICATIONS
2.5 Reset
2.5 Reset
Figure 2.5.1 shows reset circuit examples.
7480 Group
7481 Group
7480 Group
7481 Group
RESET
RESET
VCC
VCC
Power source voltage detection circuit
RESET, VCC pin number
32pin
42pin
44pin
21
RESET pin
VCC pin
18
25
22
17
18
Figure 2.5.1 Reset Circuit Examples
7480 Group and 7481 Group User's Manual
2-32
APPLICATIONS
2.6 Oscillation Circuit
2.6 Oscillation Circuit
2.6.1 Oscillation Circuit with Ceramic Resonator
An oscillation circuit can be formed by connecting
a ceramic resonator between the XIN and XOUT pins.
Figure 2.6.1 shows an oscillation circuit example
with a ceramic resonator.
7480 Group
7481 Group
Note: Set oscillation circuit parameters, such as Rd,
CIN, and COUT, to the values recommended
by the manufacturer of the resonator.
XIN
X
OUT
Rd
CIN
COUT
XIN, XOUT pin number
32pin
pin
19
44pin
14
XIN pin
X
OUT pin
20
15
F6.1 Oscillation Circuit Example with
Ceramic Resonator
2.6.2 External Clock Input to XIN
An external clock input to the XIN pin can be
to the built-in clock generator.
Figure 2.6.2 shows the external clock ciple.
7480 Group
7481 Group
Notes 1: Leave the XOUT pin open external
clock is input to the
XIN
XOUT
2: Use a 50% duty ce signal as the
external clock he XIN pin.
Open
External clock
VCC
VSS
Duty cycle 50%
X
IN, XOUT pin number
32pin
42pin
19
44pin
14
X
IN pin
14
15
XOUT pin
20
15
Figure 2.6.2 External Clock Circuit Example
7480 Group and 7481 Group User's Manual
2-33
APPLICATIONS
2.7 Power-Saving Function
2.7 Power-Saving Function
2.7.1 Application Example of Stop Mode
Power-Saving in Key-Input Waiting State
POINT: When the CPU has no key input for the specified period in its key-input waiting state, the
CPU enters the stop mode and reduces power dissipation by halting itself and its peripherals.
Any key input, thereafter, generates a key-on wakeup interrupt request, and the CPU returns
to the normal mode by accepting the request.
SPECIFICATIONS: Port pin P00 is used as a key-input pin.
When having no key input for the specified period, the CPU executes the STP
instruction to enter the stop mode.
Any key input generates a key-on wakeup interrupt request in the stop mode,
and the CPU returns to the normal mode by apting the request.
Figure 2.7.1 shows a connection example.
Figure 2.7.2 shows an operation example in the key-input wte.
Figure 2.7.3 shows a control procedure example of powein key-input waiting state.
P00
Key input
7480 Group
7481 Group
Figure 2.7.1 Connection Ex
Key-on wakeup interrupt
service routine executed
STP instruction
Key-on wakeup interrupt
request generated
executed
Key-input waiting state
after the specified period
STP instruction
execution cycle
Oscillator start-up stabilizing time
2048 count of XIN pin input signal
Stop mode state
Undefined
XIN
X
IN pin : High-impedance state
Internal clock φ
Key input
Port P
0
Figure 2.7.2 Operation Example in Key-Input Waiting State
7480 Group and 7481 Group User's Manual
2-34
APPLICATIONS
2.7 Power-Saving Function
RESET(Note)
Initialize
SEI
Port P00 is set to input.
Port P00 is pulled high.
Set edge polarity selection register
b7
b0
1
EG (Address 00D416)
Key-on wakeup
Set STP instruction operation control register
(Writing 2 times)
1st writing
b7
b0
1
STPCON (Address 00DE16)
Writing ‘1’
2nd writing
b7
b0
0
STPCON (Address 00DE16)
STP/WIT instruction valid
ssing
CLI
Y
Key input ?
N
Specified period elapsed ?
Y
Key-on wakeup interrupt request bit ← 0
Key-on wakeup interrupt enable bit ← 1
Other interrupt enable bits ← 0
STP instruction execution
Stop mode
Key input
System to normal mode after the
oscillation p stabilization time elapsed.
Key-on wakeup interrupt service routine
Processing
The interrupt enable bit and timer 1 are
returned to the state before the STP
instruction is executed.
RTI
Processing
Note: State after system is released from reset
• STP/WIT instructions invalid.
Figure 2.7.3 Control Procedure Example of Power-Saving in Key-Input Waiting State
7480 Group and 7481 Group User's Manual
2-35
APPLICATIONS
2.7 Power-Saving Function
2.7.2 Application Example of Wait Mode
Power-Saving in Serial I/O Receive Waiting State
POINT: When serial I/O reception is not started in serial I/O receive enabled state, the CPU enters
the wait mode and reduces power dissipation by halting itself. Then, when a serial I/O
receive interrupt or a timer X interrupt is accepted after the specified period, and the CPU
returns to the normal mode and terminates the communications.
SPECIFICATIONS: Clock synchronous serial I/O reception
• Synchronous clock: external clock input
• SRDY signal output
When serial I/O reception is not started in serial I/O receive enabled state, the
CPU executes the WIT instruction to enter the wait mode.
The CPU returns to the normal mode and terminates communications by either
of the acceptance of the following interrupt sources:
• Serial I/O receive interrupt
• Timer X interrupt: receive wait time is cothe timer mode
Figure 2.7.4 shows a connection example.
Figure 2.7.5 shows an operation example in the serial Ie waiting state.
Figure 2.7.6 shows a control procedure of power-sav
TxD
P1
4
/RxD
/SCLK
SCLK
P16
P17/SRDY
Port
7480 Group
7481 Group
Microc
Figure 2.7.4 Connection ple
WIT instruction
executed
Serial I/O receive interrupt or
timer X interrupt service routine executed
WIT instruction
execution cycle
Serial I/O receive
ready completed
Wait mode state
XIN
φ
Internal clock
Figure 2.7.5 Operation Example in Serial I/O Receive Waiting State
7480 Group and 7481 Group User's Manual
2-36
APPLICATIONS
2.7 Power-Saving Function
RESET(Note 1)
Initialize
SEI
Set serial I/O control register
b7
1
b0
×
1 1
×
1 1
0
SIOCON (Address 00E216
)
Synchronous clock:
External clock input
S
RDY output
Transmission disabled
Reception enabled
Clock synchronous serial I/O
Serial I/O enabled
Set timer X mode register
b7
b0
×
× × ×
0
0 0
0
TXM (Address00F616
)
Timer • event count mode
Writing to latch and timer
simultaneously
Timer X count source selected
Set STP instruction operation control register
(Wring 2 times)
Processing
1st writing
b7
b0
1
eception wait time count value (Note 2)
STPCON (Address 00DE16
Writing ‘1’
)
2nd writing
b7
Serial I/O receive interrupt request bit ← 0
Timer X interrupt request bit ← 0
b0
0
STPCON (Address 00DE1
STP/WIT instruction vali
Serial I/O receive interrupt enable bit ← 1
Timer X interrupt enable bit ← 1
Other interrupt enable bits ← 0
CLI
Timer X count stop bit ← 0
Receive buffer register ← Dummy data
WIT instruction executed
Wait mode
Reception is
completed or reception
waiting time elapses.
System is o normal mode after the
oscillation sstabilization time elapsed.
Serial I/O receive interrupt service routine or
timer X interrupt service routine
Processing
RTI
The interrupt enable bit is returned to the state
before the WIT instruction is executed.
Serial I/O disabled
Timer X count stop
Notes 1: State after system is released from reset
• STP/WIT instructions invalid.
Processing
2: Write in order of low-order to high-order byte.
Figure 2.7.6 Control Procedure Example of Power-Saving
7480 Group and 7481 Group User's Manual
2-37
APPLICATIONS
2.8 Countermeasures against Noise
2.8 Countermeasures against Noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual
use.
2.8.1 Shortest Wiring Length
The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Wiring for RESET Pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
REASON
The reset works to initialize a microcomputer.
The width of a pulse input into the RESET pin is determined by thg necessary conditions. If
noise having a shorter pulse width than the standard is input to ET pin, the microcomputer
is released from reset before the internal state of the microcis completely initialized. This
may cause a program runaway.
Noise
Reset
circuit
Reset
circuit
RESET
RESET
V
SS
V
VSS
V
SS
0 Group
481 Group
7480 Group
7481 Group
N.G.
O.K.
Figure 2.8.1 Wiring for in
7480 Group and 7481 Group User's Manual
2-38
APPLICATIONS
2.8 Countermeasures against Noise
(2) Wiring for Clock I/O Pins
• Make the length of wiring which is connected
to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm)
across the grounding lead of a capacitor
which is connected to an oscillator and the
VSS pin of a microcomputer as short as
possible.
Noise
7480 Group
7481 Group
X
X
V
IN
OUT
SS
• Separate the VSS pattern only for oscillation
from other VSS patterns.
N.G.
REASON
A microcomputer’s operation synchronizes with
a clock generated by the oscillator (circuit). If
noise enters clock I/O pins, clock waveforms
may be deformed. This may cause a
malfunction or program runaway.
7480 Group
7481 Group
Also, if a potential difference is caused by the
noise between the VSS level of a microcomputer
and the VSS level of an oscillator, the correct
clock will not be input in the microcomputer.
X
X
V
IN
OUT
SS
O.K.
(3) Wiring for VPP Pin of One Time PROM
Version and EPROM Version
2.8.2 Wiring for Clock I/O Pins
(In the 7480 Group and 7481 Group, the VPP
pin is also used as the P33 pin)
Connect an approximately 5 kΩ resist
the VPP pin the shortest possible in
7480 Group
7481 Group
Note: Even when a circuit whican
approximately 5 kΩ resed in
t h e M a s k R O M o n , t h e
microcomputer oorrectly.
Approximately
5kΩ
P33/VPP
REASON
The VPP pin of the Time PROM and the
EPROM version is the power source input pin
for the built-in PROM. When programming in
the built-in PROM, the impedance of the VPP
pin is low to allow the electric current for writing
flow into the PROM. Because of this, noise
can enter easily. If noise enters the VPP pin,
abnormal instruction codes or data are read
from the built-in PROM, which may cause a
program runaway.
Figure 2.8.3 Wiring for VPP Pin of One Time PROM
and EPROM Version
7480 Group and 7481 Group User's Manual
2-39
APPLICATIONS
2.8 Countermeasures against Noise
2.8.2 Connection of Bypass Capacitor across VSS
Line and VCC Line
Connect an approximately 0.1 µF bypass capacitor
across the VSS line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin
and the VCC pin at equal length.
VCC
V
CC
• Connect a bypass capacitor across the VSS pin
and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal
lines for VSS line and VCC line.
V
SS
V
SS
• Connect the power source line to VSS pin and
VCC pin through a bypass capacitor.
N.G.
O.K.
Figure 2.8.4 Bypass Capacitor across VSS Line and
VCC Line
2.8.3 Connection of Bypass Capacitor across VSS
Line and VREF Line
Connect an approximately 0.01 µF bypass capacitor
across the VSS line and the VREF line as follows:
• Connect a bypass capacitor across the VSS pin
and the VREF pin at equal length.
VREF
V
• Connect a bypass capacitor across the VSS pin
and the VREF pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal
lines for VSS line and VREF line.
2.8.4 Wiring to Analog Input Pins
VSS
VSS
• Connect an approximately 100 Ω to 1 kΩ resis
to an analog signal line which is connected
analog input pin in series. Besides, con
resistor to the microcomputer as close ae.
• Connect an approximately 0.1 to 1 citor
across the VSS pin and the anut pin.
Besides, connect the capacitoSS pin as
close as possible. Also, conneacitor across
the analog input pin anS pin at equal
length.
N.G.
O.K.
Figure 2.8.5 Bypass Capacitor across VSS Line and
VREF Line
Noise
REASON
(Note)
Signals which is input in an analog input pin (such
as an A-D converter input pin) are usually output
signals from sensor. The sensor which detects a
change of event is installed far from the printed
circuit board with a microcomputer, the wiring to an
analog input pin is longer necessarily. This long
wiring functions as an antenna which feeds noise
into the microcomputer, which causes noise to an
analog input pin.
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
If a capacitor between an analog input pin and the
VSS pin is grounded at a position far away from the
VSS pin, noise on the GND line may enter a
microcomputer through the capacitor.
Note:The resistor is used for dividing
resistance with a thermistor.
Figure 2.8.6 Analog Signal Line and Resistor and
Capacitor
7480 Group and 7481 Group User's Manual
2-40
APPLICATIONS
2.8 Countermeasures against Noise
2.8.5 Consideration for Oscillator
7480 Group
7481 Group
Take care to prevent an oscillator that generates
clocks for a microcomputer operation from being
affected by other signals.
Mutual inductance
M
(1) Keeping Oscillator Away from Large Current
Signal Lines
X
X
IN
Large
current
OUT
Install a microcomputer (and especially an
oscillator) as far as possible from signal lines
where a current larger than the tolerance of
current value flows.
V
SS
GND
Figure 2.8.7 Wiring for Large Current Signal Line
REASON
In the system using a microcomputer, there
are signal lines for controlling motors, LEDs,
and thermal heads or others. When a large
current flows through those signal lines, strong
noise occurs because of mutual inductance.
7480 Group
7481Group
CNTR
Do not c
X
IN
OUT
SS
(2) Keeping Oscillator Away from Signal Lines
Where Potential Levels Change Frequently
Install an oscillator and a connecting pattern
of an oscillator away from signal lines where
potential levels change frequently. Also, do
not cross such signal lines over the clock lines
or the signal lines which are sensitive to nois
X
V
2.8.8 Wiring to Signal Line Where Potential
Levels Change Frequently
REASON
An example of VSS patterns on the
7480 Group
Signal lines where potential level
frequently (such as the CNTR pmay
affect other lines at signal rising edge.
If such lines cross over a e, clock
waveforms may be defoich causes
a microcomputer failurgram runaway.
underside of a printed circuit board
7481 Group
Oscillator wiring
pattern example
XIN
X
OUT
V
SS
(3) Oscillator Protectising VSS Pattern
As for a two-sided printed circuit board, print
a VSS pattern on the underside (soldering side)
of the position (on the component side) where
an oscillator is mounted.
Separate the VSS line for oscillation from other VSS lines
Figure 2.8.9 VSS Patterns on Underside of Oscillator
Connect the VSS pattern to the microcomputer
VSS pin with the shortest possible wiring.
Besides, separate this VSS pattern from other
VSS patterns.
7480 Group and 7481 Group User's Manual
2-41
APPLICATIONS
2.8 Countermeasures against Noise
2.8.6 Setup for I/O Ports
Setup I/O ports using hardware and software as
follows:
Noise
Noise
O.K.
N.G.
Data bus
<Hardware>
Direction register
• Connect a resistor of 100 Ω or more to an I/O
port in series.
Port latch
<Software>
I/O port
pins
• As for an input port, read data several times by
a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may
reverse because of noise, rewrite data to its port
latch at fixed periods.
Figure 2.8.10 Setup For I/O Ports
• Rewrite data to direction registers, and if necessary,
pull-up control registers and port P4P5 input control
register at fixed periods.
7480 Group and 7481 Group User's Manual
2-42
APPLICATIONS
2.8 Countermeasures against Noise
2.8.7 Providing of Watchdog Timer Function by
Software
If a microcomputer runs away because of noise or
others, it can be detected by a software watchdog
timer and the microcomputer can be reset to normal
operation. This is equal to or more effective than
program runaway detection by a hardware watchdog
timer. The following shows an example of a watchdog
timer provided by software.
Interrupt service routine
(SWDT) ← (SWDT)—1
Interrupt processing
Main routine
(SWDT)← N
CLI
In the following example, to reset a microcomputer
to normal operation, the main routine detects errors
of the interrupt service routine and the interrupt service
routine detects errors of the main routine.
This example assumes that interrupt processing is
repeated multiple times in a single main routine
processing.
Main processing
>0
(SWDT)
≤0?
RTI
≠
N
≤0
(SWDT)
=N?
Return
=N
Interrupt service
routine erro
Main routine
errors
<Main Routine>
• Assigns a single byte of RAM to a software
watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the
main routine. The initial value N should satisfy
the following condition:
Figure 2.8hdog Timer by Software
N+1 ≥ (Counts of interrupt processing executed ain routine)
As the main routine execution cycle may chuse of an interrupt processing or others, the initial
value N should have a margin.
• Watches the operation of the interrue routine by comparing the SWDT contents with counts of
interrupt processing count after value N has been set.
• Detects that the interrupt servichas failed and determines to branch to the program initialization
routine for recovery proceshe following cases:
If the SWDT contents dnge after interrupt processing
<Interrupt Service Rou
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the initial value
N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization routine
for recovery when the contents of the SWDT reach 0 or less by continuative decrement without initializing
to the initial value N.
7480 Group and 7481 Group User's Manual
2-43
APPLICATIONS
2.9 Notes on Programming
2.9 Notes on Programming
2.9.1 Notes on Processor Status Register
Initialization of Processor Status Register
After system is released from reset, the
contents of processor status register (PS) are
undefined except for the I flag which is ‘1’.
Therefore, flags which affect program execution
must be initialized after system is released
from reset.
Reset
Flags of processor status register
(PS) initializing
Main program
In particular, it is essential to initialize the T
and D flags because they have an important
effect on calculations.
Figure 2.9.1 Initialization of Flags in PS
How to Refer Processor Status Register
To refer the contents of the processor status
register (PS), execute the PHP instruction once
then read the contents of (S + 1). If necessary,
execute the PLP instruction to return the PS
to its original status.
k area
S
Pushed PS
The NOP instruction should be executed after
every PLP instruction.
re 2.9.2 Stack Memory Contents after PHP
Instruction Execution
PLP instruction
NOP instruction
Figure 2.9.3 PLP Instruction Execution
7480 Group and 7481 Group User's Manual
2-44
APPLICATIONS
2.9 Notes on Programming
2.9.2 Notes Concerning Decimal Operation
Execution of Decimal Calculations
The ADC and SBC are the only instructions
which will yield proper decimal results in
decimal mode. To calculate in decimal notation,
set the decimal mode flag (D) to ‘1’ with the
SED instruction. After executing the ADC or
SBC instruction, execute another instruction
before executing the SEC, CLC, SED or CLD
instruction.
Set D flag to ‘1’
ADC,SBC instruction
NOP instruction
SEC,CLC,CLD instruction
Figure 2.9.4 Execution of Decimal Operation
Note on Flags in Decimal Mode
When decimal mode is selected, the values of three of the flags in thtatus register (the N, V, and
Z flags) are invalid after the ADC or SBC instruction is executed
The carry flag (C) is set to ‘1’ if a carry is generated as a resucalculation, or is cleared to
‘0’ if a borrow is generated. To determine whether a calculgenerated a carry, the C flag
must be initialized to ‘1’ before each calculation.
2.9.3 Notes on JMP Instruction
When using the JMP instruction in indirect addressing o not specify the last address on a page
as an indirect address.
Pages are sectioned every 256 addresses from a.
For other notes, refer to each secti
7480 Group and 7481 Group User's Manual
2-45
APPLICATIONS
2.10 Differences between 7480 and 7481 Group, and 7477 and 7478 Group
2.10 Differences between 7480 and 7481 Group, and 7477 and 7478 Group
The 7480 Group and 7481 Group have almost the same functions as the 7477 Group and 7478 Group.
However, take the following differences into consideration when using the former to replace the latter.
2.10.1 Functions Added to 7480 Group and 7481 Group
Table 2.10.1 lists the functions added to the 7480 Group and 7481 Group.
Table 2.10.1 Functions added to the 7480 Group and 7481 Group
Description
Added Function
Bus Arbitration
• In serial I/O communication of the bus-contention system, the
level of the TxD pin is compared with that of the RxD pin.
When there is a mismatch, a bus arbitration interrupt is generated
to detect bus collision.
• The valid/invalid of the STP and IT instructions is selectable
by writing 2 times to the STP ioperation control register.
• Watchdog timer returns prthe reset state if a runaway
occurs.
STP and WIT Instruction
Watchdog Timer
• Each pin of ports Phas a built-in clamping diode, by
which voltages ore can be applied.
Built-in Clamping Diode
Note: In the up, port P5 is not implemented.
7480 Group and 7481 Group User's Manual
2-46
APPLICATIONS
2.10 Differences between 7480 and 7481 Group, and 7477 and 478 Group
2.10.2 Functions Revised from 7477 Group and 7478 Group
The functions of 7480 Group and 7481 Group whose specifications are revised from those of the 7477
Group and 7478 Group are listed in Table 2.10.2.
Table 2.10.2 Functions Revised from 7477 Group and 7478 Group
7477 Group and 7478 Group
M3747xM4 ..................................... 192 bytes
M3747xM8/E8 ............................... 384 bytes
• I/O port
7480 Group and 7481 Group
M3748xM4 ........................................ 256 bytes
M3748xM8/E8 .................................. 448 bytes
• I/O port
RAM Sizes
Port P4
• CMOS outputs
• N-channel open-drain outputs
• Built-in clamping diodes
• In input mode, pull-up transistors
connectable.
• In input mode, P40–P43, P50–P53 pins have
schmidt circuits.
Port P5
• Input port
• Pull-up transistors connectable
• P50, P51 serve as input pins for clock
generator.
Note: The 7480 Group does not have P42,
P43, an50–P53 pins.
The oup and 7481 Group do
ne clock generator for timers.
Note: The 7477 Group does not have port
P5.
CNTR Pins
Timer
CNTR0 and CNTR1 pins have the alternative Cd CNTR1 pins have the alternative
functions of P32 and P33.
Four 8-bit timers
s of P40 and P41.
8-bit timers
wo 16-bit timers
Noise Margin
VIL: 0.25 VCC (Max.)
VIH: 0.7 VCC (Min.)
On port P3, P4, and P5 only.
VIL: 0.4 VCC (Max.)
VIH: 0.8 VCC (Min.)
(at VCC = 4.5 V to 5.5 V)
To connect/not to connect between VREF and
ladder resistors is selectable with a VREF-off
circuit.
A-D Converter
Package
No VREF-off circuit
The M3747XXFP and M37478MxT/ The M37481Mx/E8-XXXFP and M37481MxT/
E8T-XXXged in 56P6N-A packages. E8T-XXXFP are packaged in 44P6N-A
packages.
7480 Group and 7481 Group User's Manual
2-47
APPLICATIONS
2.11 Application Circuit Examples
2.11 Application Circuit Examples
Figures 2.11.1 and 2.11.2 show two examples of application circuits using the 7480 Group and 7481 Group.
Port
Port
Electromagnetic
valve 1
Igniter
Port
Port
Port
Frame detection
Electromagnetic
valve 2
Port
IN
Mode setting
Water heater
oportion
alve
PWM output
P4
0
1
/CNTR
0
Thermistor 1
Thermistor 2
IN
IN
IN
Feedba
Port
Fan motor
PWM
P4
/CNTR
1
VR
For adjust
k
Water volume
sensor
Port
Remote controller 1
Remote controller 2
Remote controller 3
Driver
Port
Figure 2.11.1 Application Circuit to Hot-Water Supply Equipment
7480 Group and 7481 Group User's Manual
2-48
APPLICATIONS
2.11 Application Circuit Examples
Key code
reception
amplifier
Programmable
waveform
P30/INT0
Engine control signal
output
Period
measurement
Igniter
P41/CNTR1
Port
Crank input
P40/CNTR0
P31/INT1
Electron carburetor
Sensor input
Throttle open degree
IN
Negative pressure sensor
Key input
Port
Port
ort
Ignition input
(For immobilizer)
Figure 2.11.2 Application to Motorcycle Single-Cylinder Engine
7480 Group and 7481 Group User's Manual
2-49
APPLICATIONS
2.11 Application Circuit Examples
This page left intentionally.
7480 Group and 7481 Group User's Manual
2-50
CHAPTER 3
APPENDICES
3.ol Registers
sk ROM Confirmation Forms
ROM Programming Confirmation Forms
.4 Mark Specification Forms
3.5 Package Outlines
3.6 Machine Instructions
3.7 List of Instruction Codes
3.8 SFR Memory Map
3.9 Pinouts
APPENDICES
3.1 Control Registers
3.1 Control Registers
Port Pi (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi, i=0 to 5) [Addresses 00C016,00C216,00C416,00C616,00C816,00CA16
]
At reset
R
W
b
Function
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
ndefined
O
O
O
O
O
O
0
1
2
3
When used as input ports (Ports P0 to P5)
• At reading, input level of pin is read.
• At writing, writing to port latch is performed and
the pin state is not affected.
When used as output ports (Ports P0, P1, P4, P5)
• At reading, the last written value into the port latch is
read.
O
O
O
O
O
O
4
5
6
• At writing, the written value is output externally through
a transistor.
O
O
O
O
7
Note: • In the 7480 Group, port P2 has only bits 0 to 3. The other bits are not implementedat reading).
• Port P3 has only bits 0 to 3. The other bits are not implemented (‘0’ at reading).
• In the 7480 Group, port P4 has only bits 0 and 1. In the 7481 Group, port P4 o 3.
The other bits are not implemented. (bits 4 to 7: ‘0’ at reading, bits 2 and 3 iup: undefined).
• The 7480 Group does not have port P5. In the 7481 Group, port P5 has
The other bits are not implemented. (‘0’ at reading).
Figure 3.1.1 Port Pi Registers (i = 0 to 5)
Port Pi direction register (i=0,1,4,5)
b7 b6 b5 b4 b3 b2 b1 b0
Port ister (PiD, i=0,1,4,5) [Addresses 00C116,00C316,00C916,00CB16]
R
O
W
O
Name
At reset
0
Function
0 : Input mode
rt Pi direction register (Note)
1 : Output mode
0 : Input mode
1 : Output mode
0
0
1
2
3
4
5
6
7
O
O
O
O
O
O
0 : Input mode
1 : Output mode
0 : Input mode
1 : Output mode
0
0
0
O
O
O
O
0 : Input mode
1 : Output mode
0 : Input mode
1 : Output mode
0
0
O
O
O
O
0 : Input mode
1 : Output mode
0 : Input mode
1 : Output mode
Note: • In the 7480 Group, port P4 direction register has only bits 0 and 1. In the 7481 Group, port P4 direction register
has only bits 0 to 3. The other bits are not implemented (bits 4 to 7: ‘0’ at reading, bits 2 and 3 in the 7480 Group:
undefined).
• The 7480 Group does not have port P5 direction register. In the 7481 Group, port P5 has only bits 0 to 3.
The other bits are not implemented (‘0’ at reading).
Figure 3.1.2 Port Pi Direction Registers (i = 0, 1, 4, 5)
7480 Group and 7481 Group User's Manual
3-2
APPENDICES
3.1 Control Registers
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 pull-up control register (P0PCON) [Address 00D016
]
R
O
W
O
b
0
Name
Function
No pull-up
At reset
0
P0
0
pull-up control bit
0 : P0
1 : P0
0
0
Pull-up
0 : P0
1 : P0
1
1
No pull-up
Pull-up
1
2
P0
1
2
pull-up control bit
pull-up control bit
0
0
O
O
O
O
O
O
P0
0 : P0
1 : P0
2
2
No pull-up
Pull-up
3
P03
pull-up control bit
0
0 : P0
1 : P0
3
3
No pull-up
Pull-up
0 : P0
1 : P0
4
4
No pull-up
Pull-up
O
O
O
O
4
5
P0
4
5
pull-up control bit
pull-up control bit
0
0
P0
0 : P0
1 : P0
5
5
No pull-up
Pull-up
6
7
P0
6
7
pull-up control bit
pull-up control bit
0
0
0 : P0
1 : P0
6
6
No pull-up
Pull-up
O
O
O
O
0 : P0
1 : P0
7
7
No pu
Pu
P0
Note: Pull-up control is valid when the cort is set to the input mode.
Figure 3.1.3 Port P0 Pull-up Control Register
Port P1 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pol register (P1PCON) [Address 00D116
]
Name
Function
R
O
W
At reset
0
O
3
–P1
0
pull-up
0 : P1
1 : P1
0
0
–P1
–P1
3
3
No pull-up
Pull-up
control bit
1
0 : P1
1 : P1
4
4
–P1
–P1
7
7
No pull-up
Pull-up
0
O
O
P17–P14 pull-up
control bit
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
×
×
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
2
3
Not implemented.
Writing to these bits is disabled.
These bits are undefined at reading.
×
×
×
4
5
6
×
7
Note: Pull-up control is valid only when the corresponding port is set to the input mode.
When port pins P1 –P1 are used as serial I/O pins, pull-up control of
the corresponding port pins is invalid.
5
7
Figure 3.1.4 Port P1 Pull-up Control Register
7480 Group and 7481 Group User's Manual
3-3
APPENDICES
3.1 Control Registers
Port P4P5 input control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P4P5 input control register (P4P5CON) [Address 00D216
]
0 0 0 0 0 0
b
0
Name
Function
, P4 are used as
At reset
0
R
O
W
O
P4
2
, P4
3
input control bit When the P4
2
3
the input port, set this bit to ‘1’.
1
2
P5 input control bit
Not implemented.
Writing to these bits is disabled.
These bits are ‘0’ at reading.
When the P5 is used as the input
port, set this bit to ‘1’.
0
0
O
O
×
×
×
0
0
3
4
5
0
0
0
0
0
0
0
0
×
×
×
6
7
0
Note: 7480 Group does not have port pins P42, P43 and P5, so set bits 0 and 1 to ‘0’.
Figure 3.1.5 Port P4P5 Input Control Register
7480 Group and 7481 Group User's Manual
3-4
APPENDICES
3.1 Control Registers
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0
Edge polarity selection register (EG) [Address 00D416]
b
Function
Name
R
O
W
O
At reset
0
0
INT0 edge
selection bit
0 : Falling edge
1 : Rising edge
1
2
0
0
O
O
O
O
INT1 edge
selection bit
0 : Falling edge
1 : Rising edge
0: In event count mode, rising edge counted.
: In pulse output mode, operation started
at HIGH level output.
CNTR0 edge
selection bit
:
In pulse period measurement mode, a period
from falling edge until falling edge measured.
: In pulse width measurement mode,
HIGH-level period measured.
: In programmable one-shot output mode,
one-shot HIGH pulse generated after
operation started at LOW level output.
: Interrupt request is generated by det
falling edge.
1: In event count mode, falling ed
: In pulse output mode, operat
at LOW level output.
3
0
CNTR1 edge
selection bit
O
O
:
In pulse period measuremen
from rising edge until risi.
: In pulse width meae,
LOW-level perio
: In programmutput mode,
one-shot erated after
operatioGH level output.
: Interrenerated by detecting
risi
Undefined
Not implementedbit is disabled.
This bit is undg.
Undefined
×
4
5
O
O
0
INT1 sour
selecti00–P07 LOW level
STP (for key-on wake-up)
NT1
Undefined
Undefined
6
Undefined
Undefined
×
×
nted. Writing to these bits are disabled.
are undefined at reading.
setting bits 0 to 3, the interrupt request bit may be set to ‘1’.
r setting the following, enable the interrupt.
➀Disable interrupts
➁Set the edge polarity selection register
➂ Set the interrupt request bit to ‘0’
Figure 3.1.6 Edge Polarity Selection Register
7480 Group and 7481 Group User's Manual
3-5
APPENDICES
3.1 Control Registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register (ADCON) [Address 00D916]
b
0
Name
Function
At reset
0
R
O
W
O
b2 b1 b0
Analog input pin selection bits
0 0 0 : P20/IN0
0 0 1 : P21/IN1
0 1 0 : P22/IN2
0 1 1 : P23/IN3
1 0 0 : P24/IN4
1 0 1 : P25/IN5
1 1 0 : P26/IN6
1 1 1 : P27/IN7
O
O
O
O
1
2
0
0
(Note)
3
4
A-D conversion completion bit
0 : Conversion in progress
1 : Conversion completed
1
0
O
O
0 : Disconnect between VREF pin
ladder resistor
VREF connection selection bit
O
1 : Connect between VREF p
ladder resistor
Undefined
Undefined
Undefined
5
ndefined
×
×
×
Not implemented.
Writing to these bits is disabled.
These bits are undefined at reading.
Undefined
Undefined
6
7
: The bit can be set to ‘0’ by software, buto ‘1’.
Note: Do not perform setting in the 748
Figure 3.1.7 A-D Control Register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D cter (AD) [Address 00DA16]
R
W
At reset
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Function
ad-only register to store the A-D conversion result.
×
×
×
×
×
×
×
×
O
O
O
O
O
3
4
5
O
6
7
O
O
Figure 3.1.8 A-D Conversion Register
7480 Group and 7481 Group User's Manual
3-6
APPENDICES
3.1 Control Registers
STP instruction operation control register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
STP instruction operation control register (STPCON) [Address 00DE16
]
b
0
R
O
W
O
Function
At reset
1
Name
STP and WIT valid/invalid
selection bit (Note)
0 : STP/WIT instruction valid
1 : STP/WIT instruction invalid
×
×
1
0
0
0
0
Not implemented.
Writing to these bits is disabled.
These bits are ‘0’ at reading.
2
3
4
×
×
×
0
0
0
0
0
0
5
6
7
×
×
0
0
0
0
Note: The STP and WIT instructions are invalid after the system ireset. When
using these instructions, set STP and WIT valid/invalid she STP instruction
operation control register to ‘1’, then set this bit to ‘0’. uccessively)
When not using the STP and WIT instructions, set her once or twice.
Figure 3.1.9 STP Instruction Operation Control Regi
7480 Group and 7481 Group User's Manual
3-7
APPENDICES
3.1 Control Registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address 00E016
]
b
At reset
Function
R
W
0
1
Undefined
Undefined
In transmission:
Transmit data is transferred to the transmit shift register
by writing transmit data.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
2
3
In reception:
Note
When data is stored completely in the receive shift
register, the receive data is transferred to this register.
4
5
6
7
Note: In transmission, this register is a write-only register.
In reception, this register is a read-only register.
Figure 3.1.10 Transmit/Receive Buffer Register
Serial I/O status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O status register (SIOSTS) 16
]
1
b
Name
Function
At reset
0
R
O
W
×
0
Buffer full
1 : Buffer empty
Transmit buffer e
(TBE)
1
0
×
×
0 : Buffer empty
1 : Buffer full
O
O
Receive
(RBF)
0 : Transmit shift in progress
1 : Transmit shift completed
2
5
0
0
0
0
Tmpletion
×
×
×
O
O
0 : No error
1 : Overrun error
error flag
0 : No error
1 : Parity error
rity error flag
(PE)
0 : No error
1 : Framing error
O
Framing error flag
(FE)
×
×
6
7
Summing error flag
(SE)
0 : OE U PE U FE=0
1 : OE U PE U FE=1
0
1
O
1
This bit is fixed to ‘1’.
Note: b4 and b5 are valid only in UART
Figure 3.1.11 Serial I/O Status Register
7480 Group and 7481 Group User's Manual
3-8
APPENDICES
3.1 Control Registers
Serial I/O control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address 00E216
]
b
0
Name
Function
At reset
0
R
O
W
O
BRG count source
selection bit (CSS)
0 : f(XIN)/4
1 : f(XIN)/16
Serial I/O synchronous
clock selection bit (SCS)
0
O
1
O
when clock synchronous serial I/O is selected
0 : BRG output/4
1 : External clock input
when UART is selected
0 : BRG output/16
1 : External clock input/16
O
O
2
3
S
RDY output enable bit
0 : P1
1 : SRDY output pin
7
pin
0
0
O
O
(SRDY)
0 : Interrupt occurs when transmit
buffer is empty.
1 : Interrupt occurs when transmit ft
operation is completed.
Transmit interrupt source
selection bit (TIC)
O
O
O
O
4
5
6
7
Transmit enable bit
(TE)
0 : Transmit disabled
1 : Transmit enabled
0
0
Receive enable bit
(RE)
0 : Receive disa
1 : Receive e
O
O
Serial I/O mode selection bit
(SIOM)
0 : Async(UART)
1 : Clos serial I/O
O
O
Serial I/O enable bit
(SIOE)
0 abled
enabled
0
Figure 3.1.12 Serial I/O Control Register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1
l register (UARTCON) [Address 00E316
]
Name
Function
At reset
0
R
O
W
O
0
0 : 8 bits
1 : 7 bits
Character length selection bit
(CHAS)
Parity enable bit
(PARE)
0 : Parity disabled
1 : Parity enabled
O
O
1
2
3
0
0
0
O
O
O
Parity selection bit
(PARS)
0 : Even parity
1 : Odd parity
Stop bit length selection bit
(STPS)
O
1
0 : 1 stop bit
1 : 2 stop bits
These bits are fixed to ‘1’.
×
×
×
×
4
5
1
1
1
1
1
1
6
7
1
Figure 3.1.13 UART Control Register
7480 Group and 7481 Group User's Manual
3-9
APPENDICES
3.1 Control Registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address 00E416
]
R
W
Function
b
At reset
O
O
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
1
2
• 8-bit timer for baud rate generation of serial I/O.
• Valid only when BRG output divided by 4 or 16 is selected
as synchronous clock.
O
O
O
O
O
O
O
O
3
4
5
O
O
O
6
7
O
O
O
Figure 3.1.14 Baud Rate Generator
Bus collision detection control register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
Bus collision detection control register (BUddress 00E516
]
R
O
W
O
b
0
Name
nction
At reset
0
on detection invalid
ision detection valid
Bus collision detection enabl
0
0
0
0
0
×
×
×
×
×
×
×
1
2
3
Not implemented
Writing to thesed.
These bits ag.
0
0
0
4
5
6
0
0
0
0
0
0
Figure 3.1.15 Bus Collision Control Register
7480 Group and 7481 Group User's Manual
3-10
APPENDICES
3.1 Control Registers
Watchdog timer H
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer H (WDTH) [Address 00EF16
]
At reset
R
O
O
W
b
Function
The high-order count value of watchdog timer is indicated.
0
1
1
1
2
O
O
1
1
1
3
4
5
Note
O
O
O
1
1
1
6
7
O
The following value is set by writing arbitrary data.
Note:
• watchdog timer L ← ‘7F16
’
• watchdog timer H ← ‘FF16
’
Figure 3.1.16 Watchdog Timer H
7480 Group and 7481 Group User's Manual
3-11
APPENDICES
3.1 Control Registers
Timer X (Timer X latch)
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (high-order) (TXH) [Address 00F116
b7 b6 b5 b4 b3 b2 b1 b0
]
Timer X (low-order) (TXL) [Address 00F016
]
Function
b
0
1
At reset
R
O
W
The low-order count value of
timer X is indicated.
1
1
O
O
2
3
4
1
1
1
O
O
O
Note 1
5
6
7
1
1
1
O
O
Function
At reset
b
R
W
1
1
O
O
O
0
1
2
3
The high-ordef
timer X is i
1
1
1
O
O
Note 1
4
O
O
O
1
1
1
Notes 1: Do not write to these bits in pulurement mode or pulse width measurement mode.
2: When b3 of timer X mode reing to latch and timer is simultaneously
performed. When b3 is ‘1’latch is performed.
3: When reading/writing fread/write from/to both high-order and low-order
bytes. At reading, reer byte and the low-order byte in this order.
At writing, write the and the high-order byte in this order.
Figure 3.1.17 Timer X
7480 Group and 7481 Group User's Manual
3-12
APPENDICES
3.1 Control Registers
Timer Y (Timer Y latch)
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y (high-order) (TYH) [Address 00F316
b7 b6 b5 b4 b3 b2 b1 b0
]
Timer Y (low-order) (TYL) [Address 00F216
]
Function
At reset
b
R
O
W
0
1
2
The low-order count value of
timer Y is indicated.
1
1
O
O
O
1
1
1
3
4
5
Note 1
O
O
1
1
1
6
7
O
O
Function
b
O
W
0
1
2
The high-order count value
timer Y is indicated.
O
O
1
1
1
3
4
5
O
O
Note 1
1
1
1
O
O
O
6
7
Notes 1: Do not write to these bits in pulse period mode or pulse width measurement mode.
2: When b3 of timer Y mode register is ‘0ch and timer is simultaneously
performed. When b3 is ‘1’, writing terformed.
3: When reading/writing from/to timfrom/to both high-order and low-order bytes.
At reading, read the high-ordeow-order byte in this order.
At writing, write the low-ordhigh-order byte in this order.
Figure 3.1.18 Timer Y
Timer 1 (Timer
b7 b6 b5 b4 bb0
Timer1 (T1) [Address 00F416
b
]
R
O
O
W
O
O
Function
At reset
The timer 1 count value is indicated.
1
1
1
0
1
O
O
O
O
2
3
4
1
1
1
O
O
O
O
5
6
7
O
O
O
O
1
1
Figure 3.1.19 Timer 1
7480 Group and 7481 Group User's Manual
3-13
APPENDICES
3.1 Control Registers
Timer 2 (Timer 2 latch)
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address 00F516
]
Function
R
O
O
W
O
O
At reset
b
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
The timer 2 count value is indicated.
1
2
O
O
O
O
3
4
5
O
O
O
O
O
O
6
7
O
O
Figure 3.1.20 Timer 2
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register (TXM) [Address 00F
b
0
Name
ion
At reset
0
R
O
W
Timer X operating mode bits
O
event count mode
output mode
lse period measurement mode
Pulse width measurement mode
: Programmable waveform
generation mode
1 0 1 : Programmable one-shot output
mode
1 1 0 : PWM mode
1
0
O
O
O
2
3
0
0
O
1 1 1 : Not available
0 : Writing to both latch and timer
1 : Writing to latch only
O
O
O
O
O
O
control bit
ut level latch
0 : LOW output from CNTR
1 : HIGH output from CNTR
0
pin
pin
0
0
0
Timer X trigger selection bit
0 : Timer X free run in programmable
waveform generation mode
1 : Trigger occurrence (input signal of INT
0
pin) and timer X start in programmable
waveform generation mode
b7 b6
0 0 : f(XIN)/2
0 1 : f(XIN)/8
1 0 : f(XIN)/16
6
7
Timer X count source
selection bits
0
0
O
O
O
O
1 1 : Input from CNTR0 pin
Figure 3.1.21 Timer X Mode Register
7480 Group and 7481 Group User's Manual
3-14
APPENDICES
3.1 Control Registers
Timer Y mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y mode register (TYM) [Address 00F716
]
Function
b
0
Name
At reset
0
R
O
W
O
b2 b1 b0
0 0 0 : Timer • event count mode
0 0 1 : Pulse output mode
0 1 0 : Pulse period measurement mode
0 1 1 : Pulse width measurement mode
1 0 0 : Programmable waveform
generation mode
1 0 1 : Programmable one-shot
output mode
1 1 0 : PWM mode
Timer Y operating mode bits
1
0
O
O
O
O
2
3
0
0
1 1 1 : Not available
Timer Y write control bit 0 : Writing to both latch and timer
1 : Writing to latch only
O
O
O
O
O
O
0 : LOW output from CNTR
1 : HIGH output from CNTR
1
pin
pin
4
5
Output level latch
0
0
1
Timer Y trigger selection bit 0 : Timer Y free run in programma
waveform generation mode
1 : Trigger occurrence (inpu
pin) and timer Y start
waveform generat
b7 b6
6
7
Timer Y count source
0
0
O
O
O
O
0 0 : f(XIN)
selection bits
0 1 : f(X
1 0 :
1 NTR1 pin
Figure 3.1.22 Timer Y Mode Register
Timer XY control register
b7 b6 b5 b4 b3 b2 b1 b0
ol register (TXYCON) [Address 00F816]
0 0 0 0 0 0
R
O
W
O
At reset
1
Name
Function
Timer X stop control bit
0 : Count operation
1 : Count stop
1
Timer Y stop control bit
0 : Count operation
1 : Count stop
1
O
O
×
×
×
×
×
×
Not implemented.
Writing to these bits is disabled.
These bits are ‘0’ at reading.
0
0
2
3
0
0
0
4
5
6
0
0
0
0
0
7
0
0
Figure 3.1.23 Timer XY Control Register
7480 Group and 7481 Group User's Manual
3-15
APPENDICES
3.1 Control Registers
Timer 1 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 mode register (T1M) [Address 00F916]
0
0 0
b
0
Name
Function
At reset
0
R
O
W
O
Timer 1 stop control bit 0 : Count operation
1 : Count stop
O
O
1
0
Timer 1 operation
mode bit
0 : Timer mode
1 : Programmable waveform generation mode
×
×
O
0
0
0
0
2
3
4
Not implemented. Writing to these bits is disabled.
These bits are ‘0’ at reading.
O
Output level latch
0 : LOW output from T0 pin
1 : HIGH output from T0 pin
0
0
0
0
×
O
O
5
6
Not implemented. Writing to this bit is disabled.
This bit is ‘0’ at reading.
b7 b6
O
O
Timer 1 count source
0 0 : f(XIN)/8
selection bits
0 1 : f(XIN)/64
1 0 : f(XIN)/128
1 1 : f(XIN)/256
7
Figure 3.1.24 Timer 1 Mode Register
Timer 2 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 mode register 00FA16
]
0
0 0
R
O
W
O
b
0
N
Function
At reset
0
Timebit 0 : Count operation
1 : Count stop
O
O
1
0
ation
0 : Timer mode
1 : Programmable waveform generation mode
0
0
×
×
O
mplemented. Writing to these bits is disabled.
ese bits are ‘0’ at reading.
0
0
0
O
Output level latch
0 : LOW output from T
1
pin
pin
1 : HIGH output from T
1
0
5
0
×
Not implemented. Writing to this bit is disabled.
This bit is ‘0’ at reading.
b7 b6
0 0 : f(XIN)/8
0 1 : f(XIN)/64
1 0 : f(XIN)/128
1 1 : f(XIN)/256
O
O
O
Timer 2 count source
selection bits
6
7
0
0
O
Figure 3.1.25 Timer 2 Mode Register
7480 Group and 7481 Group User's Manual
3-16
APPENDICES
3.1 Control Registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address 00FB16
]
0 0
R
O
W
0
b
0
1
Name
Function
At reset
Fix these bits to ‘0’.
0
0
0
O
O
0
2
O
Stack page selection bit
0 : Zero page
(Note)
1 : 1 page
Watchdog timer L count
source selection bit
0 : f(XIN)/8
1 : f(XIN)/16
O
O
3
4
5
0
×
Undefined
Undefined
Not implemented. Writing to this bit is disabled.
This bit is undefined at reading.
Undefined
×
Undefined
Not implemented. Writing to this bit is disabled.
This bit is undefined at reading.
Clock division
ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (medium-speed mod
O
O
6
7
0
Undefined
×
fined
Not implemented. Writing to this bit is disabled.
This bit is undefined at reading.
Note: In the products whose RAM size is 192 bytehis bit to ‘0’.
Figure 3.1.26 CPU Mode Register
7480 Group and 7481 Group User's Manual
3-17
APPENDICES
3.1 Control Registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16
]
R
O
W
b
0
Name
Function
At reset
0
Timer X interrupt request bit 0 : No interrupt request
1 : Interrupt request
1
2
Timer Y interrupt request bit 0 : No interrupt request
1 : Interrupt request
0
0
O
O
Timer 1 interrupt request bit 0 : No interrupt request
1 : Interrupt request
3
Timer 2 interrupt request bit 0 : No interrupt request
1 : Interrupt request
0
O
4
5
Serial I/O receive
interrupt request bit
0 : No interrupt request
1 : Interrupt request
0
0
O
O
O
O
Serial I/O transmit
interrupt request bit
0 : No interrupt request
1 : Interrupt request
6
7
Bus arbitration interrupt
request bit
0 : No interrupt req
1 : Interrupt requ
0
0
A-D conversion completion 0 : No interr
interrupt request bit 1 : Interr
: The bit can be set to ‘0’ by software, et to ‘1’.
Figure 3.1.27 Interrupt Request Register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt r 2 (IREQ2) [Address 00FD16]
R
W
ame
Function
At reset
0
O
nterrupt request bit
0 : No interrupt request
1 : Interrupt request
0
0
0
O
O
2
INT1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
CNTR0 interrupt request bit 0 : No interrupt request
1 : Interrupt request
3
CNTR1 interrupt request bit 0 : No interrupt request
1 : Interrupt request
O
Undefined
Undefined
Undefined
Undefined
×
×
×
×
Undefined
Undefined
Undefined
Undefined
4
5
6
Not implemented.
Writing to these bits is disabled.
These bits are undefined at reading.
7
: The bit can be set to ‘0’ by software, but cannot be set to ‘1’.
Figure 3.1.28 Interrupt Request Register 2
7480 Group and 7481 Group User's Manual
3-18
APPENDICES
3.1 Control Registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 00FE16
]
R
O
W
O
b
0
Name
Function
At reset
0
Timer X interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
1
2
Timer Y interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
0
0
O
O
O
O
Timer 1 interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
3
Timer 2 interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
0
O
O
O
O
4
5
Serial I/O receive
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
O
O
Serial I/O transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6
7
Bus arbitration interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
O
O
O
O
A-D conversion completion 0 : Interrupt dis
interrupt enable bit 1 : Interrupt
Figure 3.1.29 Interrupt Control Register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt conCON2) [Address 00FF16
]
R
O
W
O
At reset
0
b
e
Function
upt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
2
3
0 : Interrupt disabled
1 : Interrupt enabled
O
O
T
1
interrupt enable bit
CNTR
0
1
interrupt enable bit 0 : Interrupt disabled
O
O
O
O
1 : Interrupt enabled
CNTR
interrupt enable bit 0 : Interrupt disabled
1 : Interrupt enabled
Undefined
Undefined
Undefined
Undefined
×
×
×
×
Undefined
Undefined
Undefined
Undefined
4
5
Not implemented.
Writing to these bits are disabled.
These bits are undefined at reading.
6
7
Figure 3.1.30 Interrupt Control Register 2
7480 Group and 7481 Group User's Manual
3-19
APPENDICES
3.2 Mask ROM Confirmation Forms
3.2 Mask ROM Confirmation Forms
Mask ROM number
Date:
GZZ-SH09-84B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M2T-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idenwe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the PROMs.
Microcomputer name :
M37480M2T-XX
M37480M2T-XXXFP
Checksum code foROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27512
EPROM address
000016
EPRO
EPROM address
0
000016
Area for ASCII
codes of the name
of the product
for ASCII
des of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37480M2T–’
‘M37480M2T-’
‘M37480M2T–’
000F16
001016
016
000F16
001016
2FFF16
300016
6FFF16
700016
EFFF16
F00016
ROM (4K)
ROM (4K)
ROM (4K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480M2T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480M2T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘M’ = 4D16
‘2’ = 3216
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-20
APPENDICES
3.2 Mask ROM Confirmation Forms
Mask ROM number
GZZ-SH09-84B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M2T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37480M2T–’
✽= $8000
.BYTE ‘M37480M2T–’
✽= $0000
.BYTE ‘M37480M2T–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the masonfirmation, the ROM processing
is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the pacordered fill out the appropriate mark
specification form (32P4B for M37480M2T-XXXSP, 32P2W-A for M-XXXFP) and attach to the mask ROM
confirmation form.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-21
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-85B<56A0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M4-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idenwe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the PROMs.
Microcomputer name :
M37480M4-XXXS
M37480M4-XXXFP
Checksum code for OM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27512
EPROM address
000016
EPRO
EPROM address
0
000016
Area for ASCII
codes of the name
of the product
or ASCII
es of the name
f the product
‘M37480M4-’
Area for ASCII
codes of the name
of the product
‘M37480M4–’
‘M37480M4–’
000F16
001016
16
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480M4–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480M4–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-22
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-85B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M4-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37480M4–’
✽= $8000
.BYTE ‘M37480M4–’
✽= $0000
.BYTE ‘M37480M4–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the packordered fill out the appropriate mark
specification form (32P4B for M37480M4-XXXSP, 32P2W-A for MXXFP) and attach to the mask ROM
confirmation form.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-23
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-86B<56A0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M4T-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idenwe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the PROMs.
Microcomputer name :
M37480M4T-XXX
M37480M4T-XXXFP
Checksum code for OM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27512
EPROM address
000016
EPRO
EPROM address
0
000016
Area for ASCII
codes of the name
of the product
or ASCII
es of the name
f the product
Area for ASCII
codes of the name
of the product
‘M37480M4T–’
‘M37480M4T-’
‘M37480M4T–’
000F16
001016
16
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480M4T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480M4T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-24
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-86B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M4T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37480M4T–’
✽= $8000
.BYTE ‘M37480M4T–’
✽= $0000
.BYTE ‘M37480M4T–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the packordered fill out the appropriate mark
specification form (32P4B for M37480M4T-XXXSP, 32P2W-A for MXXXFP) and attach to the mask ROM
confirmation form.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-25
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-87B<56A0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M8-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idenwe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the PROMs.
Microcomputer name :
M37480M8-XXXS
M37480M8-XXXFP
Checksum code for OM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
EPRO
0
Area for ASCII
codes of the name
of the product
or ASCII
es of the name
f the product
‘M37480M8–’
‘M37480M8–’
000F16
001016
16
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480M8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480M8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘M’ = 4D16
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-26
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-87B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M8-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37480M8-’
✽= $0000
.BYTE ‘M37480M8-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the packordered fill out the appropriate mark
specification form (32P4B for M37480M8-XXXSP, 32P2W-A for MXXFP) and attach to the mask ROM
confirmation form.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-27
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-88B<56A0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M8T-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idenwe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the PROMs.
Microcomputer name :
M37480M8T-XXX
M37480M8T-XXXFP
Checksum code for OM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
EPRO
0
Area for ASCII
codes of the name
of the product
or ASCII
es of the name
f the product
‘M37480M8T–’
‘M37480M8T–’
000F16
001016
16
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480M8T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480M8T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘M’ = 4D16
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-28
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-88B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M8T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37480M8T-’
✽= $0000
.BYTE ‘M37480M8T-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the packordered fill out the appropriate mark
specification form (32P4B for M37480M8T-XXXSP, 32P2W-A for MXXXFP) and attach to the mask ROM
confirmation form.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-29
APPENDICES
3.2 Mask ROM Confirmation Forms
Mask ROM number
Date:
GZZ-SH09-78B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M2T-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idenwe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the PROMs.
Microcomputer name :
M37481M2T-XX
M37481M2T-XXXFP
Checksum code foROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27512
EPROM address
000016
EPRO
EPROM address
0
000016
Area for ASCII
codes of the name
of the product
for ASCII
des of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37481M2T–’
‘M37481M2T-’
‘M37481M2T–’
000F16
001016
016
000F16
001016
2FFF16
300016
6FFF16
700016
EFFF16
F00016
ROM (4K)
ROM (4K)
ROM (4K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481M2T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481M2T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘M’ = 4D16
‘2’ = 3216
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-30
APPENDICES
3.2 Mask ROM Confirmation Forms
Mask ROM number
GZZ-SH09-78B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M2T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37481M2T–’
✽= $8000
.BYTE ‘M37481M2T–’
✽= $0000
.BYTE ‘M37481M2T–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the masonfirmation, the ROM processing
is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the pacordered fill out the appropriate mark
specification form (42P4B for M37481M2T-XXXSP, 44P6N-A for M-XXXFP) and attach to the mask ROM
confirmation form.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-31
APPENDICES
3.2 Mask ROM Confirmation Forms
Mask ROM number
Date:
GZZ-SH09-79B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M4-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idenwe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the PROMs.
Microcomputer name :
M37481M4-XXX
M37481M4-XXXFP
Checksum code foROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27512
EPROM address
000016
EPRO
EPROM address
000016
Area for ASCII
codes of the name
of the product
for ASCII
des of the name
of the product
‘M37481M4-’
Area for ASCII
codes of the name
of the product
‘M37481M4–’
‘M37481M4–’
000F16
001016
6
016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481M4–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481M4–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-32
APPENDICES
3.2 Mask ROM Confirmation Forms
Mask ROM number
GZZ-SH09-79B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M4-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37481M4–’
✽= $8000
.BYTE ‘M37481M4–’
✽= $0000
.BYTE ‘M37481M4–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the masonfirmation, the ROM processing
is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the pacordered fill out the appropriate mark
specification form (42P4B for M37481M4-XXXSP, 44P6N-A for MXXXFP) and attach to the mask ROM
confirmation form.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-33
APPENDICES
3.2 Mask ROM Confirmation Forms
Mask ROM number
Date:
GZZ-SH09-80B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M4T-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idenwe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the PROMs.
Microcomputer name :
M37481M4T-XX
M37481M4T-XXXFP
Checksum code foROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27512
EPROM address
000016
EPRO
EPROM address
0
000016
Area for ASCII
codes of the name
of the product
for ASCII
des of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37481M4T–’
‘M37481M4T-’
‘M37481M4T–’
000F16
001016
016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481M4T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481M4T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-34
APPENDICES
3.2 Mask ROM Confirmation Forms
Mask ROM number
GZZ-SH09-80B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M4T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37481M4T–’
✽= $8000
.BYTE ‘M37481M4T–’
✽= $0000
.BYTE ‘M37481M4T–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the masonfirmation, the ROM processing
is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the pacordered fill out the appropriate mark
specification form (42P4B for M37481M4T-XXXSP, 44P6N-A for M-XXXFP) and attach to the mask ROM
confirmation form.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-35
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-81B<56A0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M8-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idenwe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the PROMs.
Microcomputer name :
M37481M8-XXXS
M37481M8-XXXFP
Checksum code for OM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
EPRO
0
Area for ASCII
codes of the name
of the product
or ASCII
es of the name
f the product
‘M37481M8–’
‘M37481M8–’
000F16
001016
16
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481M8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481M8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘M’ = 4D16
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-36
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-81B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M8-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37481M8-’
✽= $0000
.BYTE ‘M37481M8-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the packordered fill out the appropriate mark
specification form (42P4B for M37481M8-XXXSP, 44P6N-A for MXXFP) and attach to the mask ROM
confirmation form.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-37
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-82B<56A0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M8T-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idenwe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the PROMs.
Microcomputer name :
M37481M8T-XXX
M37481M8T-XXXFP
Checksum code for OM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
EPRO
0
Area for ASCII
codes of the name
of the product
or ASCII
es of the name
f the product
‘M37481M8T–’
‘M37481M8T–’
000F16
001016
16
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481M8T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481M8T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘M’ = 4D16
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-38
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-82B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M8T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37481M8T-’
✽= $0000
.BYTE ‘M37481M8T-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the packordered fill out the appropriate mark
specification form (42P4B for M37481M8T-XXXSP, 44P6N-A for M3XXXFP) and attach to the mask ROM
confirmation form.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-39
APPENDICES
3.3 ROM Programming Confirmation Forms
3.3 ROM Programming Confirmation Forms
GZZ-SH09-91B<56A0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480E8-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idewe will produce ROM programming based on
this data. We shall assume the responsibility for errors only if ata on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data itted EPROMs.
Microcomputer name :
M37480E8-XXXS
M37480E8-XXXFP
Checksum code foOM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
EPRO
0
Area for ASCII
for ASCII
des of the name
of the product
‘M37480E8–’
codes of the name
of the product
‘M37480E8–’
000F16
001016
016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480E8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480E8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘E’ = 4516
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-40
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-91B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480E8-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37480E8-’
✽= $0000
.BYTE ‘M37480E8-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM processing is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the packadered. Please submit the shrink DIP
package Mark Specification Form (only for built-in One Time PROM uter) for the M37480E8-XXXSP or the
32P2W-A Mark Specification Form for the M37480E8-XXXFP.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-41
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-92B<56A0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480E8T-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idewe will produce ROM programming based on
this data. We shall assume the responsibility for errors only if ata on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data itted EPROMs.
Microcomputer name :
M37480E8T-XXX
M37480E8T-XXXFP
Checksum code foOM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
EPRO
0
Area for ASCII
codes of the name
of the product
for ASCII
des of the name
of the product
‘M37480E8T–’
‘M37480E8T–’
000F16
001016
016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480E8T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480E8T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘E’ = 4516
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-42
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-92B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480E8T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37480E8T-’
✽= $0000
.BYTE ‘M37480E8T-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM processing is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the packadered. Please submit the shrink DIP
package Mark Specification Form (only for built-in One Time PROM ter) for the M37480E8T-XXXSP or the
32P2W-A Mark Specification Form for the M37480E8T-XXXFP.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-43
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-89B<56A0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481E8-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idewe will produce ROM programming based on
this data. We shall assume the responsibility for errors only if ata on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data itted EPROMs.
Microcomputer name :
M37481E8-XXXS
M37481E8-XXXFP
Checksum code foOM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
EPRO
0
Area for ASCII
for ASCII
des of the name
of the product
‘M37481E8–’
codes of the name
of the product
‘M37481E8–’
000F16
001016
016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481E8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481E8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘E’ = 4516
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-44
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-89B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481E8-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37481E8-’
✽= $0000
.BYTE ‘M37481E8-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM processing is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the packadered. Please submit the shrink DIP
package Mark Specification Form (only for built-in One Time PROM uter) for the M37481E8-XXXSP or the
44P6N-A Mark Specification Form for the M37481E8-XXXFP.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-45
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-90B<56A0>
ROM number
Date:
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481E8T-XXXSP/FP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈1. Confirmation
Specify the name of the product being ordered and the type of EPROd.
Three EPROMs are required for each pattern (Check @ in the appr).
If at least two of the three sets of EPROMs submitted contain idewe will produce ROM programming based on
this data. We shall assume the responsibility for errors only if ata on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data itted EPROMs.
Microcomputer name :
M37481E8T-XXX
M37481E8T-XXXFP
Checksum code foOM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
EPRO
0
Area for ASCII
codes of the name
of the product
for ASCII
des of the name
of the product
‘M37481E8T–’
‘M37481E8T–’
000F16
001016
016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481E8T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481E8T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘E’ = 4516
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
7480 Group and 7481 Group User's Manual
3-46
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-90B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481E8T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37481E8T-’
✽= $0000
.BYTE ‘M37481E8T-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM processing is disabled. Write the data correctly.
❈2. Mark specification
Mark specification must be submitted using the correct form for the packadered. Please submit the shrink DIP
package Mark Specification Form (only for built-in One Time PROM ter) for the M37481E8T-XXXSP or the
44P6N-A Mark Specification Form for the M37481E8T-XXXFP.
❈3. Comments
7480 Group and 7481 Group User's Manual
3-47
APPENDICES
3.4 Mark Specification Forms
3.4 Mark Specification Forms
32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM
7480 Group and 7481 Group User's Manual
3-48
APPENDICES
3.4 Mark Specification Forms
32P2W (32-PIN SOP) MARK SPECIFICATION FORM
7480 Group and 7481 Group User's Manual
3-49
APPENDICES
3.4 Mark Specification Forms
42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM
7480 Group and 7481 Group User's Manual
3-50
APPENDICES
3.4 Mark Specification Forms
44P6N (44-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special
mark (if needed).
A. Standard Mitsubishi Mark
Mitsubishi lot
Mitsubishi IC catalog name
number (6-digit)
B. Customer’s Parts Number + Mitsubishi Catalog Name
Customer’s
Note : Thize of characters are standard
pe.
Mcatalog name and Mitsubishi lot number
Note4 : If the Mitsubishi logo
the box below.
is not required, check
Mitsubishi logo is not required.
Note1 : The mark field should be wrned.
2 : The fonts and size of are standard
Mitsubishi type.
3 : Customer’s parts ne up to 7 characters :
Only 0 ~ 9, A ~
&, ©, (period), and
•
,
(comma) ar
Note1 : If the special mark is to be printed, indicate the
desired layout of the mark in the left figure. The
layout will be duplicated as close as possible.
Mitsubishi lot number (6-digit ) and mask ROM
number (3-digit) are always marked.
C. Special Mark Required
2 : If the customer’s trade mark logo must be used
in the special mark, check the box below.
Please submit a clean original of the logo.
For the new special character fonts a clean font
original (ideally logo drawing) must be submit-
ted.
Special logo required
The standard Mitsubishi font is used for all characters ex-
cept for a logo.
7480 Group and 7481 Group User's Manual
3-51
APPENDICES
3.5 Package Outlines
3.5 Package Outlines
32P2W–A
32P4B
7480 Group and 7481 Group User's Manual
3-52
APPENDICES
3.5 Package Outlines
42P4B
44P6N–A
7480 Group and 7481 Group User's Manual
3-53
APPENDICES
3.6 Machine Instructions
3.6 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
OP
69
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP
#
n
# OP
2
#
n
# OP
65
#
2
OP
n
#
ADC
(Note 1)
(Note 5)
When T = 0
Adds the carry, accumulator and memory con-
tents. The results are entered into the
accumulator.
2
3
←
A
A + M + C
When T = 1
Adds the contents of the memory in the ad-
dress indicated by index register X, the
contents of the memory specified by the ad-
dressing mode and the carry. The results are
entered into the memory at the address indi-
cated by index register X.
←
M(X)
M(X) + M + C
AND
(Note 1)
When T = 0
“AND’s” the accumulator and memory con-
tents.
29
2
2
25
3
2
V
←
A
A
M
The results are entered into the accumulator.
“AND’s” the contents of the memory of the ad-
dress indicated by index register X and the
contents of the memory specified by the ad-
dressing mode. The results are entered into
the memory at the address indicated by index
register X.
When T = 1
V
←
M(X)
M(X)
M
7
0
ASL
Shifts the contents of accumulator or contents
of memory one bit to the left. The low order bit
of the accumulator or memory is cleared and
the high order bit is shifted into the carry flag.
1
06
5
2
←
←
0
C
BBC
(Note 4)
Ab or Mb = 0?
Ab or Mb = 1?
C = 0?
Branches when the contents of the bit speci-
fied in the accumulator or memory is “0”.
13
+
4
2
2
17
+
5
5
3
3
20i
20i
BBS
(Note 4)
Branches when the contents of the bit sp
fied in the accumulator or memory is “1”
03
+
4
07
+
20i
20i
BCC
(Note 4)
Branches when the contents of c
“0”.
BCS
(Note 4)
C = 1?
Branches when the conteag is
“1”.
BEQ
(Note 4)
Z = 1?
V
Branches when the o flag is “1”.
BIT
A
M
“AND’s” thaccumulator and
memory. are not entered any-
where.
24
3
2
BMI
(Note 4)
N = 1?
Z = 0?
N = 0?
Brhe contents of negative flag is
BNE
(Note 4)
when the contents of zero flag is “0”.
BPL
(Note 4)
Branches when the contents of negative flag is
“0”.
←
BRA
BRK
PC
PC ± offset
Jumps to address specified by adding offset to
the program counter.
←
B
1
Executes a software interrupt.
00
7
1
←
M(S)
PCH
←
S
S – 1
←
PCL
S – 1
M(S)
←
S
←
PS
S – 1
M(S)
←
S
←
←
PCL
PCH
ADL
ADH
7480 Group and 7481 Group User's Manual
3-54
APPENDICES
3.6 Machine Instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
ABS, X
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
n
4
#
2
n
#
OP
6D
n
4
#
3
OP
n
5
#
OP
79
n
5
#
3
OP
#
n
#
OP
61
n
6
#
OP
71
n
6
#
OP
#
OP
#
N
N
V
V
75
35
16
7D
3D
1E
3
3
3
2
2
•
4
2
2D
4
3
5
39
5
3
21
6
2
31
6
2
N
•
•
•
•
•
Z
•
6
2
0E
6
3
7
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90
B0
F0
2
2
2
2
2
2
•
•
•
2C
4
3
M7 M6
Z
30
D0
10
80
2
2
2
4
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
7480 Group and 7481 Group User's Manual
3-55
APPENDICES
3.6 Machine Instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n #
OP
#
n
# OP
#
n
# OP
#
BVC
(Note 4)
V = 0?
Branches when the contents of overflow flag is
“0”.
BVS
(Note 4)
V = 1?
Branches when the contents of overflow flag is
“1”.
←
CLB
CLC
CLD
CLI
Ab or Mb
0
Clears the contents of the bit specified in the
accumulator or memory to “0”.
1B
+
2
1
1F
+
5
2
20i
20i
←
←
C
D
0
0
Clears the contents of the carry flag to “0”.
18
2
2
2
2
2
1
1
1
1
1
Clears the contents of decimal mode flag to D8
“0”.
←
I
0
Clears the contents of interrupt disable flag to 58
“0”.
←
←
CLT
CLV
T
V
0
0
Clears the contents of index X mode flag to 12
“0”.
Clears the contents of overflow flag to “0”.
B8
CMP
(Note 3)
When T = 0
A – M
Compares the contents of accumulator and
memory.
2
C5
3
2
When T = 1
M(X) – M
Compares the contents of the memory speci-
fied by the addressing mode with the content
of the address indicated by index register
__
←
COM
CPX
CPY
DEC
DEX
DEY
DIV
M
M
Forms a one’s complement of the co
memory, and stores it into memory
44
E4
C4
C6
5
3
3
5
2
2
2
2
X – M
Y – M
Compares the contents of indnd
memory.
E0
C0
2
2
2
Compares the contentter Y and
memory.
2
←
←
A
M
A – 1 or
M – 1
Decrements ththe accumulator
or memory b
1A
2
1
←
←
←
X
Y
A
X – 1
Decrements of index register X CA
by 1.
2
2
1
1
Y – 1
he contents of index register Y 88
(M(zz + X + 1),
s the 16-bit data that is the contents of
z + x + 1) for high byte and the contents of
M (zz + x) for low byte by the accumulator.
Stores the quotient in the accumulator and the
1’s complement of the remainder on the stack.
M(zz + X)) / A
M(S)
of Remainder
←
←
1’s complememt
S
S – 1
EOR
(Note 1)
When T = 0
“Exclusive-ORs” the contents of accumulator
and memory. The results are stored in the ac-
cumulator.
49
2
2
45
3
2
–
←
A
A V M
When T = 1
“Exclusive-ORs” the contents of the memory
specified by the addressing mode and the
contents of the memory at the address indi-
cated by index register X. The results are
stored into the memory at the address indi-
cated by index register X.
–
M(X) V M
←
M(X)
←
←
INC
INX
INY
A
M
A + 1 or
M + 1
Increments the contents of accumulator or
memory by 1.
3A
2
1
E6
5
2
←
←
X
Y
X + 1
Y + 1
Increments the contents of index register X by E8
1.
2
2
1
1
Increments the contents of index register Y by C8
1.
7480 Group and 7481 Group User's Manual
3-56
APPENDICES
3.6 Machine Instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
V
•
5
4
B
•
3
D
•
2
I
1
Z
•
0
C
•
OP
n
#
n
#
OP
#
OP
n
#
OP
#
n
#
#
#
OP
50
#
2
OP
#
N
•
T
•
2
•
70
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
0
•
•
•
•
•
0
•
•
•
•
•
D5
4
CD
4
3
DD
5
3
D9
5
3
C1
6
2
D
N
•
•
2
•
Z
C
N
N
N
N
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
Z
Z
Z
Z
•
•
C
C
•
EC
CC
CE
4
4
6
3
3
3
D6
6
DE
7
3
2
•
•
E2 16
2
2
•
55
4
4D
4
3
5D
5
3
59
5
3
41
6
2
51
6
2
N
•
•
•
•
•
Z
•
F6
6
EE
6
3
FE
7
3
N
N
N
•
•
•
•
•
•
•
•
•
•
•
•
2
•
•
•
Z
Z
Z
•
•
•
7480 Group and 7481 Group User's Manual
3-57
APPENDICES
3.6 Machine Instructions
Addressing mode
Symbol
JMP
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP #
OP
#
n
# OP
#
n
# OP
#
n
If addressing mode is ABS
Jumps to the specified address.
←
←
PCL
PCH
ADL
ADH
If addressing mode is IND
←
←
PCL
M (ADH, ADL)
PC
H
M (AD , AD + 1)
H
L
If addressing mode is ZP, IND
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
←
PCH
S – 1
JSR
M(S)
After storing contents of program counter in
stack, and jumps to the specified address.
←
S
←
PCL
S – 1
M(S)
←
S
After executing the above,
if addressing mode is ABS,
←
←
PCL
PCH
ADL
ADH
if addressing mode is SP,
←
←
PCL
PCH
ADL
FF
If addressing mode is ZP, IND,
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
LDA
(Note 2)
When T = 0
Load accumulator with contents of memory.
2
2
A5
3
2
←
A
M
When T = 1
Load memory indicated by index register
with contents of memory specified by the
dressing mode.
←
nn
M
M(X)
M
←
←
←
7
LDM
LDX
LDY
LSR
M
X
Y
Load memory with immediate value
3C
A6
A4
46
4
3
3
5
3
2
2
2
Load index register X s of
memory.
A2
A0
2
2
2
M
Load index regisontents of
memory.
2
0
Shift the comulator or memory
to the righ
4A
2
1
→
→
0
C
The low ccumulator or memory is
storebit is cleared.
←
S – 1
MUL
NOP
M(S) · A
A ✕ M(zz + X)
accumulator with the contents of
cified by the zero page X address-
and stores the high byte of the result
stack and the low byte in the accumula-
←
S
←
PC
PC + 1
No operation.
EA
2
1
ORA
(Note 1)
When T = 0
“Logical OR’s” the contents of memory and ac-
cumulator. The result is stored in the
accumulator.
09
2
2
05
3
2
←
A
A V M
When T = 1
“Logical OR’s” the contents of memory indi-
cated by index register X and contents of
memory specified by the addressing mode.
The result is stored in the memory specified by
index register X.
←
M(X)
M(X) V M
7480 Group and 7481 Group User's Manual
3-58
APPENDICES
3.6 Machine Instructions
Addressing mode
Processor status register
ZP, X
OP n
ZP, Y
OP n
ABS
ABS, X
OP n
ABS, Y
IND
n
ZP, IND
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
#
#
OP
4C
n
3
#
3
#
OP
n
#
OP
6C
#
3
OP
B2
n
4
#
2
#
#
OP
#
OP
#
N
•
V
•
T
•
B
•
D
•
I
Z
•
C
•
5
•
20
6
3
02
7
2
22
5
2
•
•
•
•
•
•
•
•
B5
4
2
AD
4
3
A1
N
•
•
•
•
•
Z
•
BD
5
3
B9
5
3
6
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
B6
4
2
AE
AC
4E
4
4
6
3
3
3
BE
5
3
N
N
0
Z
Z
Z
B4
56
4
6
2
2
•
BC
5E
5
7
3
3
C
62 15
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
15
4
2
0D
4
3
1D
5
3
19
5
3
01
6
2
11
6
2
N
Z
7480 Group and 7481 Group User's Manual
3-59
APPENDICES
3.6 Machine Instructions
Addressing mode
Symbol
PHA
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n #
OP
#
1
n
# OP
#
n
# OP
#
←
M(S)
A
Saves the contents of the accumulator in 48
memory at the address indicated by the stack
pointer and decrements the contents of stack
pointer by 1.
3
←
S
S – 1
←
S – 1
PHP
PLA
PLP
ROL
ROR
M(S)
PS
Saves the contents of the processor status 08
register in memory at the address indicated by
the stack pointer and decrements the contents
of the stack pointer by 1.
3
4
4
1
1
1
←
S
←
←
S
A
S + 1
M(S)
Increments the contents of the stack pointer 68
by 1 and restores the accumulator from the
memory at the address indicated by the stack
pointer.
←
S
S + 1
Increments the contents of stack pointer by 1 28
and restores the processor status register
from the memory at the address indicated by
the stack pointer.
←
PS
M(S)
7
←
0
Shifts the contents of the memory or accumu-
lator to the left by one bit. The high order bit is
shifted into the carry flag and the carry flag is
shifted into the low order bit.
6A
2
1
1
26
66
82
5
5
8
2
2
2
←
←
C
Shifts the contents of the memory or accumu-
lator to the right by one bit. The low order bit is
shifted into the carry flag and the carry flag i
shifted into the high order bit.
7
0
→
→
C
RRF
RTI
7
→
0
→
Rotates the contents of memory to th
4 bits.
←
S
S + 1
M(S)
S + 1
M(S)
S + 1
Returns from an interrupt rmain 40
routine.
6
6
1
1
←
PS
←
PCL
←
PCH
S
←
S
←
M(S)
←
PCL
←
RTS
S
S + 1
M(S)
S + 1
Returns fre to the main routine. 60
←
S
←
PCH
M(S)
SBC
(Note 1)
(Note 5)
When T = 0
the contents of memory and
ent of carry flag from the contents of
ulator. The results are stored into the
mulator.
E9
2
2
E5
3
2
_
←
A
A – M – C
When T = 1
_
←
M(X)
M(X) – M – C
Subtracts contents of complement of carry flag
and contents of the memory indicated by the
addressing mode from the memory at the ad-
dress indicated by index register X. The
results are stored into the memory of the ad-
dress indicated by index register X.
←
SEB
SEC
SED
SEI
Ab or Mb
1
Sets the specified bit in the accumulator or
memory to “1”.
0B
+
2
1
0F
+
5
2
20i
20i
←
←
C
D
1
1
Sets the contents of the carry flag to “1”.
38
2
2
2
2
1
1
1
1
Sets the contents of the decimal mode flag to F8
“1”.
←
I
1
Sets the contents of the interrupt disable flag 78
to “1”.
←
SET
T
1
Sets the contents of the index X mode flag to 32
“1”.
7480 Group and 7481 Group User's Manual
3-60
APPENDICES
3.6 Machine Instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
n
#
n
#
OP
#
OP
n
#
OP
#
n
#
#
#
OP
#
OP
#
N
•
V
•
T
•
B
•
D
•
I
Z
•
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
Z
(Value saved in stack)
36
76
6
6
2
2
2E
6E
6
6
3
3
3E
7E
7
7
3
3
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
•
C
C
•
(Value saved in stack)
•
•
•
•
•
•
•
•
•
•
•
•
N
V
Z
C
F5
4
2
ED
4
3
FD
3
E1
6
2
F1
6
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
1
•
•
•
1
•
•
1
•
•
7480 Group and 7481 Group User's Manual
3-61
APPENDICES
3.6 Machine Instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP #
OP
#
1
n
# OP
#
n
# OP
85
#
2
n
←
STA
STP
STX
STY
TAX
TAY
TST
TSX
TXA
TXS
TYA
WIT
M
A
Stores the contents of accumulator in memory.
Stops the oscillator.
4
42
2
←
←
←
←
M
M
X
X
Y
Stores the contents of index register X in
memory.
86
84
4
4
2
2
Stores the contents of index register Y in
memory.
A
Transfers the contents of the accumulator to AA
index register X.
2
2
1
1
Y
A
Transfers the contents of the accumulator to A8
index register Y.
M = 0?
Tests whether the contents of memory are “0”
or not.
64
3
2
←
←
←
←
X
A
S
A
S
X
X
Y
Transfers the contents of the stack pointer to BA
index register X.
2
2
2
1
1
1
Transfers the contents of index register X to 8A
the accumulator.
Transfers the contents of index register X t
the stack pointer.
Transfers the contents of index regi
the accumulator.
Stops the internal clock.
C2
Notes 1 : The number of cycles “n” is increased by 3 when T i
2 : The number of cycles “n” is increased by 2 when
3 : The number of cycles “n” is increased by 1 whe
4 : The number of cycles “n” is increased by 2 whas occurred.
5 : N, V, and Z flags are invalid in decimal op
7480 Group and 7481 Group User's Manual
3-62
APPENDICES
3.6 Machine Instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP n
ABS
ABS, X
OP
9D
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
4
3
2
1
0
C
•
OP
95
n
5
#
2
#
2
OP
8D
n
5
#
3
n
#
OP
99
n
#
3
OP
#
n
#
OP
81
n
7
#
OP
91
n
7
#
OP
#
OP
#
N
•
V
•
T
•
B
•
D
•
I
Z
•
6
3
6
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
96
5
8E
8C
5
5
3
3
94
5
2
•
•
N
N
N
N
N
•
Z
Z
Z
Z
Z
•
N
•
Z
•
Symbol
Contents
Symbol
Contents
IMP
Implied addressing mode
+
Addition
IMM
A
Immediate addressing mode
Accumulator or Accumulatmode
–
Subtraction
Logical OR
Logical AND
V
V
–
V
–
BIT, A
Accumulator bit relatmode
Logical exclusive OR
Negation
ZP
BIT, ZP
Zero page addr
Zero page bessing mode
←
X
Shows direction of data flow
Index register X
Y
Index register Y
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Zero page X addng mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
S
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
PC
PS
PCH
PCL
ADH
ADL
FF
nn
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
M
Memory specified by address designation of any ad-
dressing mode
Memory of address indicated by contents of index
register X
M(X)
M(S)
Memory of address indicated by contents of stack
Z
Zero flag
pointer
I
D
B
Interrupt disable flag
Decimal mode flag
Break flag
M(ADH, ADL)
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-or-
der bits.
T
V
N
X-modified arithmetic mode flag
Overflow flag
Negative flag
M(00, ADL)
Contents of address indicated by zero page ADL
1 bit of accumulator
1 bit of memory
Opcode
Number of cycles
Ab
Mb
OP
n
#
Number of bytes
7480 Group and 7481 Group User's Manual
3-63
APPENDICES
3.7 List of Instruction Codes
3.7 List of Instruction Codes
D3 – D0
0000 0001 0010 0011 0100 0101
0110 0111 1000 1001
1010 1011 1100 1101
1110 1111
Hexadecimal
notati on
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
D7 – D4
ORA
JSR
BBS
ORA
ZP
ASL
ZP
BBS
0, ZP
ORA
IMM
ASL
A
SEB
0, A
ORA
ABS
ASL
ABS 0, ZP
SEB
BRK
—
—
PHP
CLC
PLP
SEC
PHA
CLI
—
—
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IND, X ZP, IND 0, A
ORA
IND, Y
BBC
0, A
ORA
ZP, X
ASL
ZP, X 0, ZP
BBC
ORA
ABS, Y
DEC
A
CLB
0, A
ORA
ABS, X
ASL
ABS, X 0, ZP
CLB
BPL
JSR
CLT
AND
JSR
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
AND
ABS
ROL
ABS 1, ZP
SEB
ABS IND, X SP
AND
IND, Y
BBC
1, A
AND
ZP, X
ROL
ZP, X 1, ZP
BBC
AND
ABS, Y
INC
A
CLB
1, A
LDM AND
ZP ABS, X
ROL
ABS, X 1, ZP
CLB
BMI
RTI
SET
STP
—
EOR
IND, X
BBS COM EOR
2, A
LSR
ZP
BBS
2, ZP
EOR
IM
B JMP
, A
EOR
ABS
LSR
ABS 2, ZP
SEB
ZP
ZP
ABS
EOR
IND, Y
BBC
2, A
EOR
ZP, X
LSR
ZP, X 2, ZP
BBC
CLB
2, A
EOR
ABS, X
LSR
ABS, X 2, ZP
CLB
BVC
RTS
BVS
BRA
—
—
—
ADC
MUL
BBS TST
ADC
ZP
ROR
ZP
BBS
3, Z
ROR
MM
SEB JMP
3, A
ADC
ABS
ROR
ABS 3, ZP
SEB
I
IND, X ZP, X 3, A
ZP
A
IND
ADC
IND, Y
BBC
3, A
ADC
ZP, X
ROR
ZP,
ADC
ABS, Y
CLB
3, A
ADC
ABS, X
ROR
ABS, X 3, ZP
CLB
—
—
—
—
STA
IND, X ZP
RRF
BBS STY
4, A
STA
Z
S
, ZP
SEB STY
4, A
STA
ABS
STX
ABS 4, ZP
SEB
DEY
TYA
TAY
CLV
INY
—
TXA
TXS
TAX
TSX
DEX
—
ZP
ABS
STA
—
BBC
STY
P, Y 4, ZP
BBC
STA
ABS, Y
CLB
4, A
STA
ABS, X
CLB
—
BCC
LDY
—
IND, Y
4, A ZP,
4, ZP
LDA
LDX
BBS
5,
A
ZP
LDX
ZP
BBS
5, ZP
LDA
IMM
SEB LDY
5, A
LDA
LDX
SEB
IMM IND, X IMM
ABS
ABS ABS 5, ZP
LDA JMP
IND, Y ZP, P, X ZP, X
Y
LDA
LDX
ZP, Y 5, ZP
BBC
LDA
ABS, Y
CLB
LDY
LDA
LDX
CLB
5, ZP
BCS
5, A ABS, X ABS, X ABS, Y
CPY CMP
S CPY
6, A
CMP DEC
ZP
BBS
6, ZP
CMP
IMM
SEB CPY
6, A
CMP DEC
ABS ABS
SEB
6, ZP
IMM
IND
ZP
ZP
ABS
I
BBC
6, A
CMP
ZP, X
DEC
ZP, X 6, ZP
BBC
CMP
ABS, Y
CLB
6, A
CMP DEC
ABS, X ABS, X
CLB
6, ZP
BNE
—
—
CLD
INX
—
CPX SBC
IMM IND, X ZP, X 7, A
DIV
BBS CPX
SBC
ZP
INC
ZP
BBS
7, ZP
SBC
IMM
SEB CPX
7, A
SBC
INC
SEB
NOP
—
ZP
ABS
ABS ABS 7, ZP
SBC
IND, Y
BBC
7, A
SBC
ZP, X
INC
ZP, X 7, ZP
BBC
SBC
ABS, Y
CLB
7, A
SBC
ABS, X ABS, X
INC
CLB
7, ZP
BEQ
—
—
SED
—
3-byte instruction
2-byte instruction
1-byte instruction
7480 Group and 7481 Group User's Manual
3-64
APPENDICES
3.8 SFR Memory Map
3.8 SFR Memory Map
Figure 3.8.1 shows the SFR memory map.
Port P0 register (P0)
Transmit/receive buffer register (TB/RB)
00C016
00C116
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA
00
16
Port P0 direction register (P0D)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIOCON)
UART control register (UARTCON)
Baud rate gener (BRG)
00C216 Port P1 register (P1)
Port P1 direction register (P1D)
00C316
00C416
00C516
00C616
00C716
00C816
Port P2 register (P2)
Bus collision dol register (BUSARBCON)
Port P3 register (P3)
Port P4 register (P4)
00C916 Port P4 direction register (P4D)
00CA16 Port P5 register (P5)
(Note)
00CB16 Port P5 direction register (P5D)
00CC16
00CD16
00CE16
00CF16
EF16 Watchdog timer H (WDTH)
00F016 Timer X low-order (TXL)
Port P0 pull-up control register (P0PCON)
Port P1 pull-up control register (P1PCON
Port P4P5 input control register (P4P
00D016
00D116
00D216
00D316
Timer X high-order (TXH)
00F216 Timer Y low-order (TYL)
00F116
Timer Y high-order (TYH)
Timer 1 (T1)
00F316
00F416
00D416 Edge polarity selection register
00D516
00D616
00D716
00D816
00F516 Timer 2 (T2)
00F616 Timer X mode register (TXM)
00F716
00F816
00F916
00FA16
00FB16
Timer Y mode register (TYM)
Timer XY control register (TXYCON)
Timer 1 mode register (T1M)
Timer 2 mode register (T2M)
CPU mode register (CPUM)
A-D control regN)
00D916
00DA16 A-D conversioAD)
00DB16
00DC16
00DD16
00FC16 Interrupt request register 1 (IREQ1)
00FD16
00FE16 Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Interrupt request register 2 (IREQ2)
00DE16
00DF16
STP instruction operation control register (STPCON)
00FF16
Note: These registers are not allocated in the 7480 Group.
Figure 3.8.1 SFR Memory Map
7480 Group and 7481 Group User's Manual
3-65
APPENDICES
3.9 Pinouts
3.9 Pinouts
Figures 3.9.1 and 3.9.2 show the pinouts of the 7480 Group and 7481 Group.
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P3
P3
7
6
5
4
3
2
1
0
1
0
3
2
P1
P1
P1
P1
7
/SRDY
1
2
6
/SCLK
5
/TX
D
3
4
/RX
D
4
P1
3
/T
1
0
1
0
5
P1
2/T
6
P1
P1
7
8
P2
3/IN
2/IN
1/IN
0
/IN
3
2
1
0
/CNTR
1
0
9
P2
P2
P2
/CNTR
10
11
12
13
14
V
REF
IN
OUT
SS
P3
1
/INT
1
0
X
P3
0
/INT
X
RESE
15
16
V
V
C
Outline 32P4B✽1
9
28
27
26
25
24
23
22
21
20
19
18
17
P0
P0
P0
P0
P0
P0
P0
P4
P4
P3
P3
6
5
4
3
2
1
0
1
0
3
2
P1
7
/SRDY
/SCLK
1
2
P1
6
P1
5
/TX
D
3
P1
4
/RX
D
4
P1
3
/T
1
0
1
5
P1
2/T
P1
P1
P2
0
/CNTR
1
0
P2
/CNTR
0
11
12
13
14
15
16
V
REF
IN
OUT
SS
P3
1
/INT
1
0
X
P3
0
/INT
X
RESET
V
V
CC
Outline 32P2W-A✽2
✽ 1: The M37480M2T-XXXSP, M37480M4-XXXSP and M37480M4T-XXXSP are also included in the 32P4B packages,
respectively. All of these products are pin-compatible.
2: The M37480M2T-XXXFP, M37480M4-XXXFP and M37480M4T-XXXFP are also included in the 32P2W-A packages,
respectively. All of these products are pin-compatible.
Note:
The only differences between the 32P4B package product and the 32P2W-A package product are package outline and
absolute maximum ratings.
Figure 3.9.1 Pinout of 7480 Group (top view)
7480 Group and 7481 Group User's Manual
3-66
APPENDICES
3.9 Pinouts
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
P52
P53
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
P13/T1
P12/T0
P11
P07
P06
4
5
P05
P04
6
P03
7
P02
8
P01
9
P10
P00
10
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
P43
11
12
13
14
15
16
17
18
19
20
21
P42
P41/CNTR1
P40/CNTR0
P33
P32
P31/INT1
P30/INT0
RESET
P51
XIN
XOUT
P
VSS
✽1
Outline 42P4B
42S1B-A S)
P04
22
21
20
19
P30/INT0
RESET
P51
34
39
40
41
42
43
44
P05
P06
P0
VS
P50
VCC
M37481M8-XXXFP
M37481M8T-XXXFP
M37481E8-XXXFP
M37481E8T-XXXFP
18
17
16
15
14
13
12
VSS
AVSS
P53
P17/SRDY
P16/SCLK
P15/TXD
P14/RXD
XOUT
XIN
VREF
P20/IN0
Outline 44P6N-A ✽2
✽ 1: The M37481M2T-XXXSP, M37481M4-XXXSP and M37481M4T-XXXSP are also included in the 42P4B packages,
respectively. All of these products are pin-compatible.
2: The M37481M2T-XXXFP, M37481M4-XXXFP and M37481M4T-XXXFP are also included in the 44P6N-A packages,
respectively. All of these products are pin-compatible.
Note:
The only differences between the 42P4B package product and the 44P6N-A package product are package outline,
absolute maximum ratings and the fact that the 44P6N-A package product has the AVss pin.
Figure 3.9.2 Pinout of 7481 Group (top view)
7480 Group and 7481 Group User's Manual
3-67
APPENDICES
3.9 Pinouts
This page left intentionally.
7480 Group and 7481 Group User's Manual
3-68
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
7480 Group
7481 Group
Nov. First Edition 1997
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1996 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
7480 Group
7481 Group
Printed in Japan (ROD)
New publication, effective Nov. 1997.
© 1997 MITSUBISHI ELECTRIC CORPORATION
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
7480 GROUP AND 7481 GROUP USER'S MANUAL
Rev.
Rev.
Revision Description
No.
date
1.0 First Edition
971130
(1/1)
A
GRADE
MESC TECHNICAL NEWS
No.M740-14-9712
Additional information of 7480/7481 Group (Rev.A)
The following errors exist in the 7480 Group and 7481 Group User’s Manual.
Please refer to the corrected information as shown below.
Corrected information of 7480 Group and 7481 Group User’s Manual (Rev.A)
Page
1-192
Error
Correct
Figure 1.21.5
Conditions: 25°C, f(XIN)=8 MHz (with a ceramic onator) in wait mode
3.0
High-speed mode
2.0
1.0
0.0
Medium-speed mode
2
3.0
4.0
5.0
6.0
7.0
Power source voltage VCC [V]
: Corrected points
2-24
LAN comnication format: Simplified SAE LAN communication format: Simplified SAE*
Section 2.3.3
SPECIFICATIONS
J1850 (PWM system)
J1850 (PWM system)
*SAE: Society of Automotive Engineers
(1/1)
相关型号：
©2020 ICPDF网 联系我们和版权申明