M38039G6HKP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38039G6HKP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总92页 (文件大小：1607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0166-0110
Rev.1.10
Nov 14, 2005
DESCRIPTION
• Power source voltage
[In high-speed mode]
The 3803 group (Spec.H QzROM version) is the 8-bit
microcomputer based on the 740 family core technology.
The 3803 group (Spec.H QzROM version) is designed for
household products, office automation equipment, and
controlling systems that require analog signal processing,
including the serial interface functions, 8/16-bit timer, A/D
converter and D/A converter.
At 16.8 MHz oscillation frequency.................... 4.5 to 5.5 V
At 12.5 MHz oscillation frequency.................... 4.0 to 5.5 V
At 8.4 MHz oscillation frequency...................... 2.7 to 5.5 V
At 4.2 MHz oscillation frequency...................... 2.2 to 5.5 V
At 2.1 MHz oscillation frequency...................... 2.0 to 5.5 V
[In middle-speed mode]
At 16.8 MHz oscillation frequency.................... 4.5 to 5.5 V
At 12.5 MHz oscillation frequency.................... 2.7 to 5.5 V
At 8.4 MHz oscillation frequency...................... 2.2 to 5.5 V
At 6.3 MHz oscillation frequency...................... 1.8 to 5.5 V
[In low-speed mode]
FEATURES
• Basic machine-language instructions ................................. 71
• Minimum instruction execution time .......................... 0.24 µs
(at 16.8 MHz oscillation frequency)
• Memory size
At 32 kHz oscillation frequency......................... 1.8 to 5.5 V
• Power dissipation
QzROM .................................................... 16 K to 48 K bytes
RAM ..................................................................... 2048 bytes
• Programmable input/output ports ....................................... 56
• Software pull-up resistors............................................ Built-in
• Interrupts .............................................. 21 sources, 16 vectors
(external 8, internal 12, software 1)
In high-speed mode ........................................... 40 mW (typ.)
(at 16.8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ............................................ 45 µW (typ.)
(at 32 kHz oscillation frequency, at 3 V power source voltage)
• Operating temperature range ............................. −20 to 85 °C
• Packages
SP............................. PRDP0064BA-A (64-pin 750 mil SDIP)
HP.................... PLQP0064KB-A (64-pin 10 × 10 mm LQFP)
KP....................PLQP0064GA-A (64-pin 14 × 14 mm LQFP)
• Timers ...................................................................... 16-bit × 1
8-bit × 4
(with 8-bit prescaler)
• Serial interface.........8-bit × 2 (UART or Clock-synchronized)
8-bit × 1 (Clock-synchronized)
• PWM ....................................... 8-bit × 1 (with 8-bit prescaler)
• A/D converter ........................................ 10-bit × 16 channels
(8-bit reading enabled)
APPLICATION
Household products, Consumer electronics, etc.
• D/A converter ............................................ 8-bit × 2 channels
• Watchdog timer ....................................................... 16-bit × 1
• LED direct drive port..............................................................8
• Clock generating circuit ............................. Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
Rev.1.10 Nov 14, 2005 Page 1 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Currently support products are listed below.
Table 1
Support products
QzROM size (bytes)
ROM size for User in ( ) (bytes)
RAMsize
Product name
Package
Remarks
M38039G4H-XXXHP
M38039G4H-XXXKP
M38039G6H-XXXHP
M38039G6H-XXXKP
M38039G8H-XXXHP
M38039G8H-XXXKP
M38039GCH-XXXHP
M38039GCH-XXXKP
M38039G4HSP
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PRDP0064BA-A
PLQP0064KB-A
PLQP0064GA-A
PRDP0064BA-A
PLQP0064KB-A
PLQP0064GA-A
PRDP0064BA-A
PLQP0064KB-A
PLQP0064GA-A
PRDP0064BA-A
PLQP0064KB-A
PLQP0064GA-A
16384
(16254)
24576
(24446)
QzROM version
(Programmed shipment) (1)
32768
(32638)
49152
(49022)
16384
(16254)
M38039G4HHP
2048
M38039G4HKP
M38039G6HSP
24576
(24446)
M38039G6HHP
M38039G6HKP
QzROM version
(blank) (2)
M38039G8HSP
32768
(32638)
M38039G8HHP
M38039G8HKP
M38039GCHSP
M38039GCHHP
M38039GCHKP
NOTES:
49152
(49022)
1. This means a shipment of which User ROM has been programmed.
2. The user ROM area of a blank product is blank.
Rev.1.10 Nov 14, 2005 Page 2 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
PIN CONFIGURATION (TOP VIEW)
49
32
P37/SRDY3
P20(LED0)
P21(LED1)
P22(LED2)
50
31
30
29
28
27
26
P36/SCLK3
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P35/TXD3
P34/RXD3
P33
P23(LED3)
P24(LED4)
P32
P25(LED5)
P26(LED6)
P31/DA2
P30/DA1
VCC
25
24
23
22
21
20
19
18
17
P27(LED7)
VSS
M38039GXH-XXXHP/KP
M38039GXHHP/KP
XOUT
VREF
AVSS
XIN
P67/AN7
P66/AN6
P40/INT40/XCOUT
P41/INT00/XCIN
RESET
P65/AN5
P64/AN4
P63/AN3
CNVSS
P42/INT1
Package type: PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
Fig 1. 3803 group (Spec.H QzROM version) pin configuration (PLQP0064KB-A/PLQP0064GA-A)
Table 2 List of package (Spec.H QzROM version) (PLQP0064KB-A/PLQP0064GA-A)
QzROM size (bytes)
ROM size for User in ( )
RAM size
(bytes)
Package
Product name
Remarks
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
M38039G4H-XXXHP
M38039G4HHP
QzROM version (Programmed shipment)
QzROM version (blank)(2)
16384 (16254)
24576 (24446)
32768 (32638)
49152 (49022)
16384 (16254)
24576 (24446)
32768 (32638)
49152 (49022)
M38039G6H-XXXHP
M38039G6HHP
QzROM version (Programmed shipment)
QzROM version (blank)(2)
PLQP0064KB-A
2048
M38039G8H-XXXHP
M38039G8HHP
QzROM version (Programmed shipment)
QzROM version (blank)(2)
M38039GCH-XXXHP
M38039GCHHP
QzROM version (Programmed shipment)
QzROM version (blank)(2)
M38039G4H-XXXKP
M38039G4HKP
QzROM version (Programmed shipment)
QzROM version (blank)(2)
M38039G6H-XXXKP
M38039G6HKP
QzROM version (Programmed shipment)
QzROM version (blank)(2)
PLQP0064GA-A
NOTES:
2048
M38039G8H-XXXKP
M38039G8HKP
QzROM version (Programmed shipment)
QzROM version (blank)(2)
M38039GCH-XXXKP
M38039GCHKP
QzROM version (Programmed shipment)
QzROM version (blank)(2)
1. This means a shipment of which User ROM has been programmed.
2. The user ROM area of a blank product is blank.
Rev.1.10 Nov 14, 2005 Page 3 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
PIN CONFIGURATION (TOP VIEW)
1
2
64
63
62
61
60
59
58
VCC
P30/DA1
P31/DA2
P32
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
3
4
5
P33
P34/RXD3
6
7
P35/TXD3
P36/SCLK3
P64/AN4
P63/AN3
8
57
56
55
54
53
52
51
50
49
48
P37/SRDY3
P00/AN8
P01/AN9
9
P62/AN2
10
P61/AN1
11
12
13
14
15
16
17
18
19
20
21
22
P60/AN0
P02/AN10
P03/AN11
P04/AN12
P57/INT3
P56/PWM
P55/CNTR1
P54/CNTR0
P53/SRDY2
P52/SCLK2
P05/AN13
P06/AN14
P07/AN15
P10/INT41
P11/INT01
47
46
45
P51/SOUT2
P50/SIN2
P12
P13
P47/SRDY1/CNTR2
P46/SCLK1
44
43
P14
P15
P45/TXD1
42
23
24
25
26
P44/RXD1
P43/INT2
P42/INT1
CNVSS
P16
P17
41
40
39
P20(LED0)
P21(LED1)
27
28
29
30
38
37
36
35
34
33
RESET
P22(LED2)
P23(LED3)
P24(LED4)
P41/INT00/XCIN
P40/INT40/XCOUT
XIN
P25(LED5)
P26(LED6)
P27(LED7)
31
32
XOUT
VSS
Package type: PRDP0064BA-A (64P4B)
Fig 2. 3803 group (Spec.H QzROM version) pin configuration (PRDP0064BA-A)
Table 3 List of package (Spec.H QzROM version) (PRDP0064BA-A)
QzROM size (bytes)
ROM size for User in ( )
RAM size
(bytes)
Package
Product name
M38039G4HSP
Remarks
16384 (16254)
24576 (24446)
32768 (32638)
49152 (49022)
M38039G6HSP
M38039G8HSP
M38039GCHSP
QzROM version (blank)(1)
PRDP0064BA-A
NOTES:
2048
1. The user ROM area of a blank product is blank.
Rev.1.10 Nov 14, 2005 Page 4 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Fig 3. Functional block diagram
Rev.1.10 Nov 14, 2005 Page 5 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
PIN DESCRIPTION
Table 4
Pin description
Pin
Name
Functions
Function except a port function
VCC, VSS
CNVSS
Power source
CNVSS input
• Apply voltage of 1.8 V − 5.5 V to VCC, and 0 V to VSS.
• This pin controls the operation mode of the chip and is shared with the VPP pin which is the
power source input pin for programming the built-in QzROM.
• Normally connected to VSS.
VREF
AVSS
Reference
voltage
• Reference voltage input pin for A/D and D/A converters.
Analog power
source
• Analog power source input pin for A/D and D/A converters.
• Connect to VSS.
RESET
XIN
Reset input
Clock input
• Reset input pin for active “L”.
• Input and output pins for the clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin
open.
XOUT
Clock output
P00/AN8−
P07/AN15
I/O port P0
I/O port P1
• 8-bit CMOS I/O port.
• A/D converter input pin
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
P10/INT41
P11/INT01
• Interrupt input pin
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
• P20 − P27 (8 bits) are enabled to output large current for
LED drive.
P12−P17
P20-P27
I/O port P2
I/O port P3
P30/DA1
• 8-bit CMOS I/O port.
• D/A converter input pin
• Serial I/O3 function pin
P31/DA2
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
• P30, P31, P34 − P37 are CMOS 3-state output structure.
• P32, P33 are N-channel open-drain output structure.
• Pull-up control of P30, P31, P34 − P37 is enabled in a bit unit.
P32, P33
P34/RXD3
P35/TXD3
P36/SCLK3
P37/SRDY3
P40/INT40/XCOUT
P41/INT00/XCIN
I/O port P4
• 8-bit CMOS I/O port.
• Interrupt input pin
• Sub-clock generating I/O pin
(resonator connected)
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
P42/INT1
P43/INT2
• Interrupt input pin
P44/RXD1
P45/TXD1
P46/SCLK1
• Serial I/O1 function pin
P47/SRDY1/CNTR2
• Serial I/O1, timer Z function pin
• Serial I/O2 function pin
P50/SIN2
I/O port P5
P51/SOUT2
P52/SCLK2
P53/SRDY2
P54/CNTR0
P55/CNTR1
P56/PWM
P57/INT3
• Timer X function pin
• Timer Y function pin
• PWM output pin
• Interrupt input pin
• A/D converter input pin
P60/AN0−
I/O port P6
P67/AN7
Rev.1.10 Nov 14, 2005 Page 6 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
PART NUMBERING
Product name
H−
XXX SP
M3803 9
G
C
Package type
SP : PRDP0064BA-A
HP : PLQP0064KB-A
KP : PLQP0064GA-A
ROM number
Omitted in blank version.
−: standard
“−” is omitted in the shipped in blank version.
H−: Partial specification changed version.
QzROM size
9: 36864 bytes
A: 40960 bytes
B: 45056 bytes
C: 49152 bytes
D: 53248 bytes
E: 57344 bytes
F: 61440 bytes
1: 4096 bytes
2: 8192 bytes
3: 12288 bytes
4: 16384 bytes
5: 20480 bytes
6: 24576 bytes
7: 28672 bytes
8: 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved areas ;
they cannot be used as a user’s ROM area.
Memory type
G: QzROM version
RAM size
0: 192 bytes
1: 256 bytes
2: 384 bytes
3: 512 bytes
4: 640 bytes
5: 768 bytes
6: 896 bytes
7: 1024 bytes
8: 1536 bytes
9: 2048 bytes
Fig 4. Part numbering
Rev.1.10 Nov 14, 2005 Page 7 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
GROUP EXPANSION
Memory Size
• QzROM size................................................16 K to 48 K bytes
• RAM size..................................................................2048 bytes
Renesas Technology expands the 3803 group (Spec.H QzROM
version) as follows.
Packages
Memory Type
• PRDP0064BA-A ..................64-pin shrink plastic-molded DIP
• PLQP0064KB-A ...............0.5 mm-pitch plastic molded LQFP
• PLQP0064GA-A ...............0.8 mm-pitch plastic molded LQFP
Support for QzROM version.
Memory Expansion Plan
As of Sep. 2005
ROM size (bytes)
Under development
48K
32K
24K
16K
M38039GCH
Under development
M38039G8H
Under development
M38039G6H
Under development
M38039G4H
640
1024
1536
2048
RAM size (bytes)
Notes 1: Products under development: the development schedule and specification may be revised without notice.
Fig 5. Memory expansion plan
Rev.1.10 Nov 14, 2005 Page 8 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
GROUP DESCRIPTION
The QzROM version of 3803 group (Spec.H) is under development. The mask ROM version and the flash memory version are mass
production. Currently support products are listed below.
Table 5
Support products (mask ROM version and flash memory version of Spec.H)
ROM/flash memory size
RAMsize
Product name
(bytes)
Package
Remarks
(bytes)
ROM size for User in ( )
M38034M4H-XXXSP
M38034M4H-XXXFP
M38034M4H-XXXHP
M38034M4H-XXXKP
M38037M6H-XXXSP
M38037M6H-XXXFP
M38037M6H-XXXHP
M38037M6H-XXXKP
M38037M8H-XXXSP
M38037M8H-XXXFP
M38037M8H-XXXHP
M38037M8H-XXXKP
M38039MCH-XXXSP
M38039MCH-XXXFP
M38039MCH-XXXHP
M38039MCH-XXXKP
M38039MFH-XXXSP
M38039MFH-XXXFP
M38039MFH-XXXHP
M38039MFH-XXXKP
M38039MFH-XXXWG
M38039FFHSP
PRDP0064BA-A (64P4B)
PRQP0064GA-A (64P6N-A)
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
PRDP0064BA-A (64P4B)
PRQP0064GA-A (64P6N-A)
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
PRDP0064BA-A (64P4B)
PRQP0064GA-A (64P6N-A)
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
PRDP0064BA-A (64P4B)
PRQP0064GA-A (64P6N-A)
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
PRDP0064BA-A (64P4B)
PRQP0064GA-A (64P6N-A)
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
PTLG0064JA-A (64F0G)
PRDP0064BA-A (64P4B)
PRQP0064GA-A (64P6N-A)
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
PTLG0064JA-A (64F0G)
PRDP0064BA-A (64P4B)
PRQP0064GA-A (64P6N-A)
PLQP0064KB-A (64P6Q-A)
16384
(16254)
640
24576
(24446)
1024
1024
2048
32768
(32638)
Mask ROM version
49152
(49022)
61440
(61310)
2048
2048
M38039FFHFP
Flash memory version
(VCC=2.7−5.5V)
M38039FFHHP
M38039FFHKP
61440
M38039FFHWG
M38039FFSP
Flash memory version
(VCC=4.0−5.5V)
M38039FFFP
M38039FFHP
Rev.1.10 Nov 14, 2005 Page 9 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and
interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0”, the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure.7.
Store registers other than those described in Figure.6 with
program when the user needs them during interrupts or
subroutine calls (see Table 6).
CENTRAL PROCESSING UNIT (CPU)
The 3803 group (Spec.H QzROM version) uses the standard 740
Family instruction set. Refer to the table of 740 Family
addressing modes and machine instructions or the 740 Family
Software Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc. are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y
and specifies the real address.
b7
b0
A
Accumulator
b7
b0
X
Index Register X
b7
b0
Y
Index Register Y
b0
b7
S
Stack Pointer
b15
b7
b7
b0
PCH
PCL
Program Counter
b0
N V T B D I Z C
Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig 6. 740 Family CPU register structure
Rev.1.10 Nov 14, 2005 Page 10 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
On-going Routine
Interrupt request
(Note)
M(S)←(PCH)
Push Return Address
on Stack
(S)←(S) − 1
M(S)←(PCL)
Execute JSR
Push Return
Address
on Stack
M(S)←(PCH)
(S)←(S) − 1
M(S)←(PCL)
(S)←(S) − 1
Subroutine
(S)←(S) − 1
M(S)←(PS)
(S)←(S) − 1
Push Contents of
Processor
Status Register on Stack
Interrupt
Service Routine
I Flag is Set from
“0” to “1”
Fetch the Jump
Vector
Execute RTI
(S)←(S) + 1
(PS)←M(S)
(S)←(S) + 1
(PCL)←M(S)
(S)←(S) + 1
(PCH)←M(S)
Execute RTS
POP Contents of
Processor Status Register
from Stack
(S)←(S) + 1
POP Return
Address from
Stack
(PCL)←M(S)
(S)←(S) + 1
(PCH)←M(S)
POP Return
Address from Stack
Note : Condition for acceptance of an interrupt → Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig 7. Register push and pop at interrupt generation and subroutine call
Table 6
Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
Rev.1.10 Nov 14, 2005 Page 11 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
[Processor status register (PS)]
Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the
processor status register is always “0”. When the BRK
instruction is used to generate an interrupt, the processor
status register is pushed onto the stack with the break flag set
to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an
arithmetic operation and 3 flags which decide MCU operation.
Branch operations can be performed by testing the Carry (C)
flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.
In decimal mode, the Z, V, N flags are not valid.
Bit 5: Index X mode flag (T)
Bit 0: Carry flag (C)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”,
direct arithmetic operations and direct data transfers are
enabled between memory locations.
The C flag contains a carry or borrow generated by the
arithmetic logic unit (ALU) immediately after an arithmetic
operation. It can also be changed by a shift or rotate
instruction.
Bit 6: Overflow flag (V)
Bit 1: Zero flag (Z)
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds +127 to −
128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instruction is stored
in the overflow flag.
The Z flag is set if the result of an immediate arithmetic
operation or a data transfer is “0”, and cleared if the result is
anything other than “0”.
Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or
data transfer is negative. When the BIT instruction is
executed, bit 7 of the memory location operated on by the
BIT instruction is stored in the negative flag.
Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it
is “1”.
Decimal correction is automatic in decimal mode. Only the
ADC and SBC instructions can execute decimal arithmetic.
Table 7
Set and clear instructions of each bit of processor status register
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
−
N flag
Set instruction
−
−
−
−
−
−
Clear instruction
CLI
CLV
Rev.1.10 Nov 14, 2005 Page 12 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, the
internal system clock control bits, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM: address 003B16)
1
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
Main clock (XIN-XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0
0
1
1
0
1
0
1
: φ = f(XIN)/2 (high-speed mode)
: φ = f(XIN)/8 (middle-speed mode)
: φ = f(XCIN)/2 (low-speed mode)
: Not available
Fig 8. Structure of CPU mode register
Rev.1.10 Nov 14, 2005 Page 13 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
MISRG
• Middle-speed mode automatic switch by program
The middle-speed mode can also be automatically switched
by program while operating in low-speed mode. By setting
the middle-speed automatic switch start bit (bit 3) of MISRG
(address 001016) to “1” in the condition that the middle-
speed mode automatic switch set bit is “1” while operating in
low-speed mode, the MCU will automatically switch to
middle-speed mode. In this case, the oscillation stabilizing
time of the main clock can be selected by the middle-speed
automatic switch wait time set bit (bit 2) of MISRG (address
001016).
(1) Bit 0 of address 001016: Oscillation stabilizing time
set after STP instruction released bit
When the MCU stops the clock oscillation by the STP
instruction and the STP instruction has been released by an
external interrupt source, usually, the fixed values of Timer 1
and Prescaler 12 (Timer 1 = 0116, Prescaler 12 = FF16) are
automatically reloaded in order for the oscillation to
stabilize. The user can inhibit the automatic setting by setting
“1” to bit 0 of MISRG (address 001016).
However, by setting this bit to “1”, the previous values, set
just before the STP instruction was executed, will remain in
Timer 1 and Prescaler 12. Therefore, you will need to set an
appropriate value to each register, in accordance with the
oscillation stabilizing time, before executing the STP
instruction.
Figure.9 shows the structure of MISRG.
(2) Bits 1, 2, 3 of address 001016: Middle-speed Mode
Automatic Switch Function
In order to switch the clock mode of an MCU which has a
sub-clock, the following procedure is necessary:
set CPU mode register (003B16) --> start main clock
oscillation --> wait for oscillation stabilization --> switch to
middle-speed mode (or high-speed mode).
However, the 3803 group (Spec.H QzROM version) has the
built-in function which automatically switches from low to
middle-speed mode by program.
b7
b0
MISRG
MISRG: address 001016)
Oscillation stabilizing time set after STP instruction
released bit
0 : Automatically set “0116” to Timer 1, “FF16” to
Prescaler 12
1 : Automatically set disabled
Middle-speed mode automatic switch set bit
0 : Not set automatically
1 : Automatic switching enabled (Note)
Middle-speed mode automatic switch wait time set bit
0 : 4.5 to 5.5 machine cycles
1 : 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0 : Invalid
1 : Automatic switch start (Note)
Not used (return “0” when read)
(Do not write “1” to this bit)
Note : When automatic switch to middle-speed mode from low-speed mode occurs,
the values of CPU mode register (3B16) change.
Fig 9. Structure of MISRG
Rev.1.10 Nov 14, 2005 Page 14 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
MEMORY
• ROM Code Protect Address (address FFDB16)
Address FFDB16, which is the reserved ROM area of QzROM, is
the ROM code protect address. “0016” or “FE16” is written into
this address when selecting the protect bit write by using a serial
programmer or selecting protect enabled for writing shipment by
Renesas Technology corp.. When “0016” or “FE16” is set to the
ROM code protect address, the protect function is enabled, so
that reading or writing from/to QzROM is disabled by a serial
programmer.
• Special Function Register (SFR) Area
The Special Function Register area in the zero page contains
control registers such as I/O ports and timers.
• RAM
The RAM is used for data storage and for stack area of
subroutine calls and interrupts.
As for the QzROM product in blank, the ROM code is protected
by selecting the protect bit write at ROM writing with a serial
programmer.
• ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs. In
the QzROM version, 1 byte of address FFDB16 is also a reserved
area.
The protect can be performed, dividing twice. The protect area 1
is from the beginning address of ROM to address “EFFF16”. As
for the QzROM product shipped after writing, “0016” (protect
enabled to all area), “FE16” (protect enabled to the protect area 1)
or “FF16” (protect disabled) is written into the ROM code protect
address when Renesas Technology corp. performs writing.
The writing of “0016”, “FE16” or “FF16” can be selected as ROM
option setup (“MASK option” written in the mask file converter)
when ordering.
• Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
• Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
<Notes>
Since the contents of RAM are undefined at reset, be sure to set
an initial value before use.
• Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
RAM area
User ROM area
Address
XXXX16
RAM size
(bytes)
000016
SFR area
192
256
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
384
010016
RAM
512
640
XXXX16
768
Reserved area
896
083F16
1024
1536
2048
084016
Not used
0FDF16
0FE016
SFR area
0FFF16
100016
ROM area
Not used
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
YYYY16
Reserved ROM area
(128 bytes)
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
ZZZZ16
Protect area 1
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
EFFF16
F00016
ROM
FF0016
FFDB16
Reserved ROM area
(ROM code protect address)
Special page
FFDC16
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig 10. Memory map diagram
Rev.1.10 Nov 14, 2005 Page 15 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Port P0 (P0)
Prescaler 12 (PRE12)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Port P0 direction register (P0D)
Port P1 (P1)
Timer 1 (T1)
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Timer Y (TY)
Port P3 direction register (P3D)
Port P4 (P4)
Timer Z low-order (TZL)
Timer Z high-order (TZH)
Timer Z mode register (TZM)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
MISRG
Baud rate generator 3 (BRG3)
Transmit/Receive buffer register 3 (TB3/RB3)
Serial I/O3 status register (SIO3STS)
Serial I/O3 control register (SIO3CON)
UART3 control register (UART3CON)
AD/DA control register (ADCON)
AD conversion register 1 (AD1)
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
DA1 conversion register (DA1)
Reserved *
DA2 conversion register (DA2)
Transmit/Receive buffer register 1 (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
Baud rate generator (BRG1)
Serial I/O2 control register (SIO2CON)
Watchdog timer control register (WDTCON)
Serial I/O2 register (SIO2)
AD conversion register 2 (AD2)
Interrupt source selection register (INTSEL)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Reserved *
Port P0 pull-up control register (PULL0)
Port P1 pull-up control register (PULL1)
Port P2 pull-up control register (PULL2)
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
Port P5 pull-up control register (PULL5)
Port P6 pull-up control register (PULL6)
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
*Reserved area: Do not write any data to these addresses, because these
areas are reserved.
Fig 11. Memory map of special function register (SFR)
Rev.1.10 Nov 14, 2005 Page 16 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
I/O PORTS
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
By setting the port P0 pull-up control register (address 0FF016)
to the port P6 pull-up control register (address 0FF616) ports can
control pull-up with a program. However, the contents of these
registers do not affect ports programmed as the output ports.
The I/O ports have direction registers which determine the
input/output direction of each individual pin. Each bit in a
direction register corresponds to one pin, and each pin can be set
to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
Table 8
I/O port function
Name
Pin
Input/
Output
I/O Structure
Non-Port Function
Related SFRs
Ref.
No.
P00/AN8−P07/AN15
Port P0 Input/output, CMOScompatible A/D converter input
AD/DA control register
(1)
individual
bits
input level
CMOS 3-state
output
P1
P11
0
/INT41
Port P1
External interrupt input
Interrupt edge selection register (2)
/INT01
P12−P17
P20/LED0−P27/LED7 Port P2
(3)
P30/DA1
P31/DA2
Port P3
D/A converter output
AD/DA control register
(4)
(5)
P32, P33
CMOScompatible
input level
N-channel
open-drain output
P34/RXD3
P35/TXD3
P36/SCLK3
P37/SRDY3
CMOScompatible Serial I/O3 function I/O
Serial I/O3 control register
UART3 control register
(6)
(7)
(8)
(9)
input level
CMOS 3-state
output
P40/INT40/XCOUT
P41/INT00/XCIN
Port P4
External interrupt input
External interrupt input
Serial I/O1 function I/O
Interrupt edge selection register (10)
Sub-clock generating circuit CPU mode register
(11)
P42/INT1
P43/INT2
Interrupt edge selection register (2)
P44/RXD1
P45/TXD1
P46/SCLK1
Serial I/O1 control register
UART1 control register
(6)
(7)
(8)
P47/SRDY1/CNTR2
Serial I/O1 function I/O
Timer Z function I/O
Serial I/O1 control register
Timer Z mode register
(12)
P50/SIN2
Port P5
Serial I/O2 function I/O
Serial I/O2 control register
(13)
(14)
(15)
(16)
P51/SOUT2
P52/SCLK2
P53/SRDY2
P54/CNTR0
P55/CNTR1
Timer X, Y function I/O
Timer XY mode register
PWM control register
(17)
P56/PWM
PWM output
(18)
P57/INT3
External interrupt input
A/D converter input
Interrupt edge selection register (2)
AD/DA control register (1)
P60/AN0−P67/AN7
Port P6
NOTES:
1. Refer to the applicable sections how to use double-function ports as function I/O ports.
2. Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
Rev.1.10 Nov 14, 2005 Page 17 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
(1) Ports P0, P6
(2) Ports P10, P11, P42, P43, P57
Pull-up control bit
Pull-up control bit
Direction
register
Direction
register
Port latch
Port latch
Data bus
Data bus
A/D converter input
Interrupt input
Analog input pin
selection bit
(3) Ports P12 to P17, P2
(4) Ports P30, P31
Pull-up control bit
Pull-up control bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
D/A converter output
DA1 output enable bit (P30)
DA2 output enable bit (P31)
(5) Ports P32, P33
(6) Ports P34, P44
Pull-up control bit
Serial I/O enable bit
Receive enable bit
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
Serial I/O input
(7) Ports P35, P45
(8) Ports P36, P46
Pull-up control bit
Serial I/O synchronous clock
selection bit
Pull-up control bit
Serial I/O enable bit
Transmit enable bit
P-channel
Serial I/O enable bit
Serial I/O mode selection bit
output
disable bit
Serial I/O enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O output
Serial I/O clock output
Serial I/O external clock input
Fig 12. Port block diagram (1)
Rev.1.10 Nov 14, 2005 Page 18 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
(9) Port P37
(10) Port P40
Pull-up control bit
Pull-up control bit
Serial I/O3 mode selection bit
Port XC switch bit
Serial I/O3 enable bit
SRDY3 output enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
INT40 Interrupt input
Serial I/O3 ready output
Port XC
switch bit
(11) Port P41
(12) Port P47
Pull-up control bit
Timer Z operating
mode bits
Pull-up control bit
Port XC switch bit
Bit 2
Bit 1
Bit 0
Direction
register
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Data bus
Port latch
SRDY1 output enable bit
Direction
register
INT00 Interrupt input
Data bus
Port latch
Port XC
switch bit
Sub-clock generating circuit input
Timer output
Serial I/O1 ready output
CNTR2 interrupt input
(13) Port P50
(14) Port P51
Pull-up control bit
Pull-up control bit
P-channel
output
disable bit
Serial I/O2 transmit completion signal
Serial I/O2 port selection bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 input
Serial I/O2 output
Fig 13. Port block diagram (2)
Rev.1.10 Nov 14, 2005 Page 19 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
(15) Port P52
(16) Port P53
Pull-up control bit
Pull-up control bit
Serial I/O2 synchronous clock
selection bit
SRDY2 output enable bit
Serial I/O2 port selection bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2 external clock input
(17) Ports P54, P55
(18) Port P56
Pull-up control bit
Pull-up control bit
PWM function enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Pulse output mode
Timer output
PWM output
CNTR Interrupt input
Fig 14. Port block diagram (3)
Rev.1.10 Nov 14, 2005 Page 20 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
Port P0 pull-up control register
(PULL0: address 0FF016)
P00 pull-up control bit
0: No pull-up
1: Pull-up
P01 pull-up control bit
0: No pull-up
1: Pull-up
P02 pull-up control bit
0: No pull-up
1: Pull-up
P03 pull-up control bit
0: No pull-up
1: Pull-up
P04 pull-up control bit
0: No pull-up
1: Pull-up
P05 pull-up control bit
0: No pull-up
1: Pull-up
P06 pull-up control bit
0: No pull-up
1: Pull-up
P07 pull-up control bit
0: No pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
1: Pull-up
b7
b0
Port P1 pull-up control register
(PULL1: address 0FF116)
P10 pull-up control bit
0: No pull-up
1: Pull-up
P11 pull-up control bit
0: No pull-up
1: Pull-up
P12 pull-up control bit
0: No pull-up
1: Pull-up
P13 pull-up control bit
0: No pull-up
1: Pull-up
P14 pull-up control bit
0: No pull-up
1: Pull-up
P15 pull-up control bit
0: No pull-up
1: Pull-up
P16 pull-up control bit
0: No pull-up
1: Pull-up
P17 pull-up control bit
0: No pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
1: Pull-up
Fig 15. Structure of port pull-up control register (1)
Rev.1.10 Nov 14, 2005 Page 21 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
Port P2 pull-up control register
(PULL2: address 0FF216)
P20 pull-up control bit
0: No pull-up
1: Pull-up
P21 pull-up control bit
0: No pull-up
1: Pull-up
P22 pull-up control bit
0: No pull-up
1: Pull-up
P23 pull-up control bit
0: No pull-up
1: Pull-up
P24 pull-up control bit
0: No pull-up
1: Pull-up
P25 pull-up control bit
0: No pull-up
1: Pull-up
P26 pull-up control bit
0: No pull-up
1: Pull-up
P27 pull-up control bit
0: No pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
1: Pull-up
b7
b0
Port P3 pull-up control register
(PULL3: address 0FF316)
P30 pull-up control bit
0: No pull-up
1: Pull-up
P31 pull-up control bit
0: No pull-up
1: Pull-up
Not used
(return “0” when read)
P34 pull-up control bit
0: No pull-up
1: Pull-up
P35 pull-up control bit
0: No pull-up
1: Pull-up
P36 pull-up control bit
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
P37 pull-up control bit
0: No pull-up
1: Pull-up
Fig 16. Structure of port pull-up control register (2)
Rev.1.10 Nov 14, 2005 Page 22 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
Port P4 pull-up control register
(PULL4: address 0FF416)
P40 pull-up control bit
0: No pull-up
1: Pull-up
P41 pull-up control bit
0: No pull-up
1: Pull-up
P42 pull-up control bit
0: No pull-up
1: Pull-up
P43 pull-up control bit
0: No pull-up
1: Pull-up
P44 pull-up control bit
0: No pull-up
1: Pull-up
P45 pull-up control bit
0: No pull-up
1: Pull-up
P46 pull-up control bit
0: No pull-up
1: Pull-up
P47 pull-up control bit
0: No pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
1: Pull-up
b7
b0
Port P5 pull-up control register
(PULL5: address 0FF516)
P50 pull-up control bit
0: No pull-up
1: Pull-up
P51 pull-up control bit
0: No pull-up
1: Pull-up
P52 pull-up control bit
0: No pull-up
1: Pull-up
P53 pull-up control bit
0: No pull-up
1: Pull-up
P54 pull-up control bit
0: No pull-up
1: Pull-up
P55 pull-up control bit
0: No pull-up
1: Pull-up
P56 pull-up control bit
0: No pull-up
1: Pull-up
P57 pull-up control bit
0: No pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
1: Pull-up
Fig 17. Structure of port pull-up control register (3)
Rev.1.10 Nov 14, 2005 Page 23 of 91
REJ03B0166-0110
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Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
Port P6 pull-up control register
(PULL6: address 0FF616)
P60 pull-up control bit
0: No pull-up
1: Pull-up
P61 pull-up control bit
0: No pull-up
1: Pull-up
P62 pull-up control bit
0: No pull-up
1: Pull-up
P63 pull-up control bit
0: No pull-up
1: Pull-up
P64 pull-up control bit
0: No pull-up
1: Pull-up
P65 pull-up control bit
0: No pull-up
1: Pull-up
P66 pull-up control bit
0: No pull-up
1: Pull-up
P67 pull-up control bit
0: No pull-up
Note: Pull-up control is valid when the corresponding
bit of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be
set to the port of which pull-up is selected.
1: Pull-up
Fig 18. Structure of port pull-up control register (4)
Rev.1.10 Nov 14, 2005 Page 24 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
INTERRUPTS
<Notes>
When setting the followings, the interrupt request bit may be set
to “1”.
The 3803 group (Spec.H QzROM version)’s interrupts are a type
of vector and occur by 16 sources among 21 sources: eight
external, twelve internal, and one software.
• When setting external interrupt active edge
Related register: Interrupt edge selection register
(address 003A16)
Timer XY mode register (address 002316)
Timer Z mode register (address 002A16)
• When switching interrupt sources of an interrupt vector
address where two or more interrupt sources are allocated
Related register: Interrupt source selection register
(address 003916)
• Interrupt Control
Each interrupt is controlled by an interrupt request bit, an
interrupt enable bit, and the interrupt disable flag except for the
software interrupt set by the BRK instruction. An interrupt
occurs if the corresponding interrupt request and enable bits are
“1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The reset and the BRK instruction cannot be disabled with any
flag or bit. The I (interrupt disable) flag disables all interrupts
except the reset and the BRK instruction interrupt.
When several interrupt requests occur at the same time, the
interrupts are received according to priority.
When not requiring for the interrupt occurrence synchronized
with these setting, take the following sequence.
(1) Set the corresponding interrupt enable bit to “0” (disabled).
(2) Set the interrupt edge select bit (the active edge switch bit)
or the interrupt source select bit.
(3) Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
• Interrupt Operation
By acceptance of an interrupt, the following operations are
automatically performed:
1. The contents of the program counter and the processor sta-
tus register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding inter-
rupt request bit is cleared.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
• Interrupt Source Selection
Which of each combination of the following interrupt sources
can be selected by the interrupt source selection register (address
003916).
1. INT0 or Timer Z
2. CNTR1 or Serial I/O3 reception
3. Serial I/O2 or Timer Z
4. INT4 or CNTR2
5. A/D converter or serial I/O3 transmission
• External Interrupt Pin Selection
The occurrence sources of the external interrupt INT0 and INT4
can be selected from either input from INT00 and INT40 pin, or
input from INT01 and INT41 pin by the INT0, INT4 interrupt
switch bit of interrupt edge selection register (bit 6 of address
003A16).
Rev.1.10 Nov 14, 2005 Page 25 of 91
REJ03B0166-0110
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Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Table 9
Interrupt vector addresses and priority
Vector
Interrupt Request Generating
Conditions
Addresses(1)
Interrupt Source
Priority
Remarks
High Low
Reset(2)
INT0
1
2
FFFD16 FFFC16 At reset
Non-maskable
FFFB16 FFFA16 At detection of either rising or falling
edge of INT0 input
External interrupt
(active edge selectable)
Timer Z
INT1
At timer Z underflow
3
4
5
FFF916 FFF816 At detection of either rising or falling
edge of INT1 input
External interrupt
(active edge selectable)
Serial I/O1 reception
FFF716 FFF616 At completion of serial I/O1 data
reception
Valid when serial I/O1 is selected
Serial I/O1
transmission
FFF516 FFF416 At completion of serial I/O1
transmission shift or when
Valid when serial I/O1 is selected
transmission buffer is empty
Timer X
Timer Y
Timer 1
Timer 2
CNTR0
6
7
FFF316 FFF216 At timer X underflow
FFF116 FFF016 At timer Y underflow
FFEF16 FFEE16 At timer 1 underflow
FFED16 FFEC16 At timer 2 underflow
8
STP release timer underflow
9
10
FFEB16 FFEA16 At detection of either rising or falling
edge of CNTR0 input
External interrupt
(active edge selectable)
CNTR1
11
12
FFE916 FFE816 At detection of either rising or falling
edge of CNTR1 input
External interrupt
(active edge selectable)
Serial I/O3 reception
Serial I/O2
At completion of serial I/O3 data
reception
Valid when serial I/O3 is selected
Valid when serial I/O2 is selected
FFE716 FFE616 At completion of serial I/O2 data
transmission or reception
Timer Z
INT2
At timer Z underflow
13
14
15
FFE516 FFE416 At detection of either rising or falling
edge of INT2 input
External interrupt
(active edge selectable)
INT3
FFE316 FFE216 At detection of either rising or falling
edge of INT3 input
External interrupt
(active edge selectable)
INT4
FFE116 FFE016 At detection of either rising or falling
edge of INT4 input
External interrupt
(active edge selectable)
CNTR2
A/D converter
At detection of either rising or falling
edge of CNTR2 input
External interrupt
(active edge selectable)
16
17
FFDF16 FFDE16 At completion of A/D conversion
Serial I/O3
transmission
At completion of serial I/O3
transmission shift or when
transmission buffer is empty
Valid when serial I/O3 is selected
Non-maskable software interrupt
BRK instruction
NOTES:
FFDD16 FFDC16 At BRK instruction execution
1. Vector addresses contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
Rev.1.10 Nov 14, 2005 Page 26 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig 19. Interrupt control
Rev.1.10 Nov 14, 2005 Page 27 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
Not used (returns “0” when read)
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit
INT4 interrupt edge selection bit
INT0, INT4 interrupt switch bit
0 : INT00, INT40 interrupt
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
1 : INT01, INT41 interrupt
Not used (returns “0” when read)
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16)
Interrupt request register 1
(IREQ1 : address 003C16)
INT0/Timer Z interrupt request bit
INT1 interrupt request bit
Serial I/O1 receive interrupt request bit
CNTR0 interrupt request bit
CNTR1/Serial I/O3 receive interrupt
request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O2/Timer Z interrupt request bit
INT2 interrupt request bit
INT3 interrupt request bit
INT4/CNTR2 interrupt request bit
AD converter/Serial I/O3 transmit
interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt control register 1
Interrupt control register 2
b7
b0
b7
b0
(ICON2 : address 003F16)
(ICON1 : address 003E16)
INT0/Timer Z interrupt enable bit
INT1 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
CNTR0 interrupt enable bit
CNTR1/Serial I/O3 receive interrupt
enable bit
Serial I/O2/Timer Z interrupt enable bit
INT2 interrupt enable bit
INT3 interrupt enable bit
INT4/CNTR2 interrupt enable bit
AD converter/Serial I/O3 transmit
interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
b7
b0
Interrupt source selection register
(INTSEL : address 003916)
INT0/Timer Z interrupt source selection bit
0 : INT0 interrupt
1 : Timer Z interrupt
Serial I/O2/Timer Z interrupt source selection bit
0 : Serial I/O2 interrupt
(Do not write “1” to these bits simultaneously.)
1 : Timer Z interrupt
Not used (Do not write “1” to these bits.)
INT4/CNTR2 interrupt source selection bit
0 : INT4 interrupt
1 : CNTR2 interrupt
Not used (Do not write “1” to this bit.)
CNTR1/Serial I/O3 receive interrupt source selection bit
0 : CNTR1 interrupt
1 : Serial I/O3 receive interrupt
AD converter/Serial I/O3 transmit interrupt source selection bit
0 : A/D converter interrupt
1 : Serial I/O3 transmit interrupt
Fig 20. Structure of interrupt-related registers
Rev.1.10 Nov 14, 2005 Page 28 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
TIMERS
• Timer X and Timer Y
The timer X and timer Y can each select one of four operating
modes by setting the timer XY mode register (address 002316).
• 8-bit Timers
The 3803 group (Spec.H QzROM version) has four 8-bit timers:
timer 1, timer 2, timer X, and timer Y.
The timer 1 and timer 2 use one prescaler in common, and the
timer X and timer Y use each prescaler. Those are 8-bit
prescalers. Each of the timers and prescalers has a timer latch or
a prescaler latch.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down-counters. When the timer reaches “0016”, an
underflow occurs at the next count pulse and the contents of the
corresponding timer latch are reloaded into the timer and the
count is continued. When the timer underflows, the interrupt
request bit corresponding to that timer is set to “1”.
(1) Timer mode
• Mode selection
This mode can be selected by setting “00” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the timer XY mode register (address
002316).
• Explanation of operation
The timer count operation is started by setting “0” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 002316).
When the timer reaches “0016”, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
• Timer divider
The divider count source is switched by the main clock division
ratio selection bits of CPU mode register (bits 7 and 6 at address
003B16). When these bits are “00” (high-speed mode) or “01”
(middle-speed mode), XIN is selected. When these bits are “10”
(low-speed mode), XCIN is selected.
(2) Pulse Output Mode
• Mode selection
This mode can be selected by setting “01” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the timer XY mode register (address
002316).
• Prescaler 12
The prescaler 12 counts the output of the timer divider. The count
source is selected by the timer 12, X count source selection
register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512, 1/1024 of f(XIN) or f(XCIN).
• Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR0/CNTR1 pin. Regardless of the timer counting or
not the output of CNTR0/CNTR1 pin is initialized to the level of
specified by their active edge switch bits when writing to the
timer. When the CNTR0 active edge switch bit (bit 2) and the
CNTR1 active edge switch bit (bit 6) of the timer XY mode
register (address 002316) is “0”, the output starts with “H” level.
When it is “1”, the output starts with “L” level.
• Timer 1 and Timer 2
The timer 1 and timer 2 counts the output of prescaler 12 and
periodically set the interrupt request bit.
• Prescaler X and prescaler Y
The prescaler X and prescaler Y count the output of the timer
divider or f(XCIN). The count source is selected by the timer 12,
X count source selection register (address 000E16) and the timer
Y, Z count source selection register (address 000F16) among 1/2,
1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of
f(XIN) or f(XCIN); and f(XCIN).
Switching the CNTR0 or CNTR1 active edge switch bit will
reverse the output level of the corresponding CNTR0 or CNTR1
pin.
• Precautions
Set the double-function port of CNTR0/CNTR1 pin and port
P54/P55 to output in this mode.
(3) Event Counter Mode
• Mode selection
This mode can be selected by setting “10” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the timer XY mode register (address
002316).
• Explanation of operation
The operation is the same as the timer mode’s except that the
timer counts signals input from the CNTR0 or CNTR1 pin. The
valid edge for the count operation depends on the CNTR0 active
edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6)
of the timer XY mode register (address 002316). When it is “0”,
the rising edge is valid. When it is “1”, the falling edge is valid.
• Precautions
Set the double-function port of CNTR0/CNTR1 pin and port
P54/P55 to input in this mode.
Rev.1.10 Nov 14, 2005 Page 29 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
(4) Pulse Width Measurement Mode
• Mode selection
This mode can be selected by setting “11” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the timer XY mode register (address
002316).
• Explanation of operation
When the CNTR0 active edge switch bit (bit 2) or the CNTR1
active edge switch bit (bit 6) of the timer XY mode register
(address 002316) is “1”, the timer counts during the term of one
falling edge of CNTR0/CNTR1 pin input until the next rising
edge of input (“L” term). When it is “0”, the timer counts during
the term of one rising edge input until the next falling edge input
(“H” term).
• Precautions
Set the double-function port of CNTR0/CNTR1 pin and port
P54/P55 to input in this mode.
The count operation can be stopped by setting “1” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 002316). The interrupt request
bit is set to “1” each time the timer underflows.
• Precautions when switching count source
When switching the count source by the timer 12, X and Y count
source selection bits, the value of timer count is altered in
inconsiderable amount owing to generating of thin pulses on the
count input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
Rev.1.10 Nov 14, 2005 Page 30 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
XIN
“00”
“11”
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
Divider
Count source
selection bit
“10”
XCIN
Data bus
Main clock
division ratio
selection bits
Timer X latch (8)
Prescaler X latch (8)
f(XCIN)
Pulse width
measurement
mode
Timer mode
Pulse output mode
To timer X interrupt
Prescaler X (8)
Timer X count stop bit
Timer X (8)
request bit
CNTR0 active
Event
counter
mode
edge switch bit
P54/CNTR0
“0”
To CNTR0 interrupt
request bit
“1”
CNTR0 active
edge switch bit
“1”
“0”
Q
Q
T
Toggle flip-flop
R
Port P54
latch
Timer X latch write pulse
Pulse output mode
Port P54
direction register
Pulse output mode
Data bus
Count source selection bit
Clock for timer Y
f(XCIN)
Prescaler Y latch (8)
Timer Y latch (8)
Pulse width
measurement
mode
Timer mode
Pulse output mode
To timer Y interrupt
Prescaler Y (8)
Timer Y count stop bit
Timer Y (8)
request bit
CNTR1 active
Event
counter
mode
edge switch bit
P55/CNTR1
“0”
To CNTR1 interrupt
request bit
“1”
CNTR1 active
edge switch bit
“1”
“0”
Q
Q
T
Toggle flip-flop
R
Port P55
latch
Timer Y latch write pulse
Pulse output mode
Port P55
direction register
Pulse output mode
Data bus
Prescaler 12 latch (8)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
To timer 2 interrupt
Timer 2 (8)
Clock for timer 12
request bit
To timer 1 interrupt
request bit
Fig 21. Block diagram of timer X, timer Y, timer 1, and timer 2
Rev.1.10 Nov 14, 2005 Page 31 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
Timer XY mode register
(TM : address 002316)
Timer X operating mode bits
b1 b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge switch bit
0: Interrupt at falling edge
Count at rising edge in event counter mode
1: Interrupt at rising edge
Count at falling edge in event counter mode
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bits
b5 b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge switch bit
0: Interrupt at falling edge
Count at rising edge in event counter mode
1: Interrupt at rising edge
Count at falling edge in event counter mode
Timer Y count stop bit
0: Count start
1: Count stop
Fig 22. Structure of timer XY mode register
Rev.1.10 Nov 14, 2005 Page 32 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
Timer 12, X count source selection register
(T12XCSS : address 000E16)
Timer 12 count source selection bits
b3 b2 b1 b0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0 : f(XIN)/2 or f(XCIN)/2
1 : f(XIN)/4 or f(XCIN)/4
0 : f(XIN)/8 or f(XCIN)/8
1 : f(XIN)/16 or f(XCIN)/16
0 : f(XIN)/32 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/64
0 : f(XIN)/128 or f(XCIN)/128
1 : f(XIN)/256 or f(XCIN)/256
0 : f(XIN)/512 or f(XCIN)/512
1 : f(XIN)/1024 or f(XCIN)/1024
1 0 1 0 :
1 0 1 1 :
1 1 0 0 :
1 1 0 1 :
1 1 1 0 :
1 1 1 1 :
Not used
Timer X count source selection bits
b7 b6 b5 b4
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0 : f(XIN)/2 or f(XCIN)/2
1 : f(XIN)/4 or f(XCIN)/4
0 : f(XIN)/8 or f(XCIN)/8
1 : f(XIN)/16 or f(XCIN)/16
0 : f(XIN)/32 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/64
0 : f(XIN)/128 or f(XCIN)/128
1 : f(XIN)/256 or f(XCIN)/256
0 : f(XIN)/512 or f(XCIN)/512
1 : f(XIN)/1024 or f(XCIN)/1024
0 : f(XCIN)
1 0 1 1 :
1 1 0 0 :
1 1 0 1 :
1 1 1 0 :
1 1 1 1 :
Not used
b7
b0
Timer Y, Z count source selection register
(TYZCSS : address 000F16)
Timer Y count source selection bits
b3 b2 b1 b0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0 : f(XIN)/2 or f(XCIN)/2
1 : f(XIN)/4 or f(XCIN)/4
0 : f(XIN)/8 or f(XCIN)/8
1 : f(XIN)/16 or f(XCIN)/16
0 : f(XIN)/32 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/64
0 : f(XIN)/128 or f(XCIN)/128
1 : f(XIN)/256 or f(XCIN)/256
0 : f(XIN)/512 or f(XCIN)/512
1 : f(XIN)/1024 or f(XCIN)/1024
0 : f(XCIN)
1 0 1 1 :
1 1 0 0 :
1 1 0 1 :
1 1 1 0 :
1 1 1 1 :
Not used
Timer Z count source selection bits
b7 b6 b5 b4
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0 : f(XIN)/2 or f(XCIN)/2
1 : f(XIN)/4 or f(XCIN)/4
0 : f(XIN)/8 or f(XCIN)/8
1 : f(XIN)/16 or f(XCIN)/16
0 : f(XIN)/32 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/64
0 : f(XIN)/128 or f(XCIN)/128
1 : f(XIN)/256 or f(XCIN)/256
0 : f(XIN)/512 or f(XCIN)/512
1 : f(XIN)/1024 or f(XCIN)/1024
0 : f(XCIN)
1 0 1 1 :
1 1 0 0 :
1 1 0 1 :
1 1 1 0 :
1 1 1 1 :
Not used
Fig 23. Structure of timer 12, X and timer Y, Z count source selection registers
Rev.1.10 Nov 14, 2005 Page 33 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
• 16-bit Timer
(2) Event counter mode
The timer Z is a 16-bit timer. When the timer reaches “000016”,
an underflow occurs at the next count pulse and the
corresponding timer latch is reloaded into the timer and the count
is continued. When the timer underflows, the interrupt request bit
corresponding to the timer Z is set to “1”.
• Mode selection
This mode can be selected by setting “000” to the timer Z
operating mode bits (bits 2 to 0) and setting “1” to the
timer/event counter mode switch bit (bit 7) of the timer Z mode
register (address 002A16).
When reading/writing to the timer Z, perform reading/writing to
both the high-order byte and the low-order byte. When reading
the timer Z, read from the high-order byte first, followed by the
low-order byte. Do not perform the writing to the timer Z
between read operation of the high-order byte and read operation
of the low-order byte. When writing to the timer Z, write to the
low-order byte first, followed by the high-order byte. Do not
perform the reading to the timer Z between write operation of the
low-order byte and write operation of the high-order byte.
The timer Z can select the count source by the timer Z count
source selection bits of timer Y, Z count source selection register
(bits 7 to 4 at address 000F16).
The valid edge for the count operation depends on the CNTR2
active edge switch bit (bit 5) of the timer Z mode register
(address 002A16). When it is “0”, the rising edge is valid. When
it is “1”, the falling edge is valid.
• Interrupt
The interrupt at an underflow is the same as the timer mode’s.
• Explanation of operation
The operation is the same as the timer mode’s.
Set the double-function port of CNTR2 pin and port P47 to input
in this mode.
Figure.26 shows the timing chart of the timer/event counter
mode.
Timer Z can select one of seven operating modes by setting the
timer Z mode register (address 002A16).
(1) Timer mode
(3) Pulse output mode
• Mode selection
• Mode selection
This mode can be selected by setting “000” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A16).
This mode can be selected by setting “001” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A16).
• Count source selection
• Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be
selected as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the
count source.
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be
selected as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the
count source.
• Interrupt
• Interrupt
When an underflow occurs, the INT0/timer Z interrupt request bit
(bit 0) of the interrupt request register 1 (address 003C16) is set to
“1”.
The interrupt at an underflow is the same as the timer mode’s.
• Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5)
of the timer Z mode register (address 002A16) is “0”, the output
starts with “H” level. When it is “1”, the output starts with “L”
level.
• Explanation of operation
During timer stop, usually write data to a latch and a timer at the
same time to set the timer value.
The timer count operation is started by setting “0” to the timer Z
count stop bit (bit 6) of the timer Z mode register (address
002A16).
When the timer reaches “000016”, an underflow occurs at the
next count pulse and the contents of timer latch are reloaded into
the timer and the count is continued.
When writing data to the timer during operation, the data is
written only into the latch. Then the new latch value is reloaded
into the timer at the next underflow.
• Precautions
The double-function port of CNTR2 pin and port P47 is
automatically set to the timer pulse output port in this mode.
The output from CNTR2 pin is initialized to the level depending
on CNTR2 active edge switch bit by writing to the timer.
When the value of the CNTR2 active edge switch bit is changed,
the output level of CNTR2 pin is inverted.
Figure.27 shows the timing chart of the pulse output mode.
Rev.1.10 Nov 14, 2005 Page 34 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
(4) Pulse period measurement mode
(5) Pulse width measurement mode
• Mode selection
• Mode selection
This mode can be selected by setting “010” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A16).
This mode can be selected by setting “011” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A16).
• Count source selection
• Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be
selected as the count source.
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be
selected as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the
count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the
count source.
• Interrupt
• Interrupt
The interrupt at an underflow is the same as the timer mode’s.
When the pulse period measurement is completed, the
INT4/CNTR2 interrupt request bit (bit 5) of the interrupt request
register 2 (address 003D16) is set to “1”.
The interrupt at an underflow is the same as the timer mode’s.
When the pulse widths measurement is completed, the
INT4/CNTR2 interrupt request bit (bit 5) of the interrupt request
register 2 (address 003D16) is set to “1”.
• Explanation of operation
• Explanation of operation
The cycle of the pulse which is input from the CNTR2 pin is
measured. When the CNTR2 active edge switch bit (bit 5) of the
timer Z mode register (address 002A16) is “0”, the timer counts
during the term from one falling edge of CNTR2 pin input to the
next falling edge. When it is “1”, the timer counts during the
term from one rising edge input to the next rising edge input.
When the valid edge of measurement completion/start is
detected, the 1’s complement of the timer value is written to the
timer latch and “FFFF16” is set to the timer.
Furthermore when the timer underflows, the timer Z interrupt
request occurs and “FFFF16” is set to the timer. When reading the
timer Z, the value of the timer latch (measured value) is read.
The measured value is retained until the next measurement
completion.
The pulse width which is input from the CNTR2 pin is measured.
When the CNTR2 active edge switch bit (bit 5) of the timer Z
mode register (address 002A16) is “0”, the timer counts during
the term from one rising edge input to the next falling edge input
(“H” term). When it is “1”, the timer counts during the term from
one falling edge of CNTR2 pin input to the next rising edge of
input (“L” term).
When the valid edge of measurement completion is detected, the
1’s complement of the timer value is written to the timer latch.
When the valid edge of measurement completion/start is
detected, “FFFF16” is set to the timer.
When the timer Z underflows, the timer Z interrupt occurs and
“FFFF16” is set to the timer Z. When reading the timer Z, the
value of the timer latch (measured value) is read. The measured
value is retained until the next measurement completion.
• Precautions
• Precautions
Set the double-function port of CNTR2 pin and port P47 to input
in this mode.
A read-out of timer value is impossible in this mode. The timer
can be written to only during timer stop (no measurement of
pulse period).
Since the timer latch in this mode is specialized for the read-out
of measured values, do not perform any write operation during
measurement.
“FFFF16” is set to the timer when the timer underflows or when
the valid edge of measurement start/completion is detected.
Consequently, the timer value at start of pulse period
measurement depends on the timer value just before
measurement start.
Set the double-function port of CNTR2 pin and port P47 to input
in this mode.
A read-out of timer value is impossible in this mode. The timer
can be written to only during timer stop (no measurement of
pulse widths).
Since the timer latch in this mode is specialized for the read-out
of measured values, do not perform any write operation during
measurement.
“FFFF16” is set to the timer when the timer underflows or when
the valid edge of measurement start/completion is detected.
Consequently, the timer value at start of pulse width
measurement depends on the timer value just before
measurement start.
Figure.28 shows the timing chart of the pulse period
measurement mode.
Figure.29 shows the timing chart of the pulse width measurement
mode.
Rev.1.10 Nov 14, 2005 Page 35 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
(6) Programmable waveform generating mode
2. “L” one-shot pulse; Bit 5 of timer Z mode register = “1”
The output level of the CNTR2 pin is initialized to “H” at
mode selection. When trigger generation (input signal to
INT1 pin) is detected, “L” is output from the CNTR2 pin.
When an underflow occurs, “H” is output. The “L” one-shot
pulse width is set by the setting value to the timer Z low-
order and high-order. When trigger generating is detected
during timer count stop, although “L” is output from the
CNTR2 pin, “L” output state continues because an under-
flow does not occur.
• Mode selection
This mode can be selected by setting “100” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A16).
• Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be
selected as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the
count source.
• Precautions
Set the double-function port of INT1 pin and port P42 to input in
this mode.
The double-function port of CNTR2 pin and port P47 is
automatically set to the programmable one-shot generating port
in this mode.
• Interrupt
The interrupt at an underflow is the same as the timer mode’s.
This mode cannot be used in low-speed mode.
If the value of the CNTR2 active edge switch bit is changed
during one-shot generating enabled or generating one-shot pulse,
then the output level from CNTR2 pin changes.
Figure.31 shows the timing chart of the programmable one-shot
generating mode.
• Explanation of operation
The operation is the same as the timer mode’s. Moreover the
timer outputs the data set in the output level latch (bit 4) of the
timer Z mode register (address 002A16) from the CNTR2 pin
each time the timer underflows.
Changing the value of the output level latch and the timer latch
after an underflow makes it possible to output an optional
waveform from the CNTR2 pin.
<Notes regarding all modes>
• Timer Z write control
Which write control can be selected by the timer Z write control
bit (bit 3) of the timer Z mode register (address 002A16), writing
data to both the latch and the timer at the same time or writing
data only to the latch.
When the operation “writing data only to the latch” is selected,
the value is set to the timer latch by writing data to the address of
timer Z and the timer is updated at next underflow. After reset
release, the operation “writing data to both the latch and the timer
at the same time” is selected, and the value is set to both the latch
and the timer at the same time by writing data to the address of
timer Z.
• Precautions
The double-function port of CNTR2 pin and port P47 is
automatically set to the programmable waveform generating port
in this mode.
Figure.30 shows the timing chart of the programmable waveform
generating mode.
(7) Programmable one-shot generating mode
• Mode selection
This mode can be selected by setting “101” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A16).
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
• Timer Z read control
• Count source selection
A read-out of timer value is impossible in pulse period
measurement mode and pulse width measurement mode. In the
other modes, a read-out of timer value is possible regardless of
count operating or stopped.
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be
selected as the count source.
However, a read-out of timer latch value is impossible.
• Interrupt
The interrupt at an underflow is the same as the timer mode’s.
The trigger to generate one-shot pulse can be selected by the INT1
active edge selection bit (bit 1) of the interrupt edge selection
register (address 003A16). When it is “0”, the falling edge active is
selected; when it is “1”, the rising edge active is selected.
When the valid edge of the INT1 pin is detected, the INT1
interrupt request bit (bit 1) of the interrupt request register 1
(address 003C16) is set to “1”.
• Switch of interrupt active edge of CNTR2 and INT1
Each interrupt active edge depends on setting of the CNTR2
active edge switch bit and the INT1 active edge selection bit.
• Switch of count source
When switching the count source by the timer Z count source
selection bits, the value of timer count is altered in
inconsiderable amount owing to generating of thin pulses on the
count input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
• Explanation of operation
1. “H” one-shot pulse; Bit 5 of timer Z mode register = “0”
The output level of the CNTR2 pin is initialized to “L” at
mode selection. When trigger generation (input signal to
INT1 pin) is detected, “H” is output from the CNTR2 pin.
When an underflow occurs, “L” is output. The “H” one-shot
pulse width is set by the setting value to the timer Z register
low-order and high-order. When trigger generating is
detected during timer count stop, although “H” is output
from the CNTR2 pin, “H” output state continues because an
underflow does not occur.
• Usage of CNTR2 pin as normal I/O port P47
To use the CNTR2 pin as normal I/O port P47, set timer Z
operating mode bits (b2, b1, b0) of timer Z mode register
(address 002A16) to “000”.
Rev.1.10 Nov 14, 2005 Page 36 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
CNTR2 active edge
switch bit
Data bus
Programmable one-shot
“1”
generating mode
P42/INT1
Programmable one-shot
generating circuit
Programmable one-shot
generating mode
“0”
To INT1 interrupt
request bit
Programmable waveform
generating mode
D
T
Output level latch
Q
Pulse output mode
CNTR2 active edge switch bit
“0”
S
Q
Q
T
Pulse output mode
“1”
“001”
“100”
“101”
Timer Z operating
mode bits
Timer Z low-order latch Timer Z high-order latch
Timer Z low-order Timer Z high-order
To timer Z interrupt
request bit
Port P47
latch
Port P47
direction register
Pulse period measurement mode
Pulse width measurement mode
Edge detection circuit
To CNTR2 interrupt
request bit
“1”
“1”
f(XCIN)
P47/CNTR2
“0”
CNTR2 active edge
switch bit
“0”
Timer Z count stop bit
Timer/Event
counter mode
switch bit
XIN
Count source
selection bit
Divider
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
XCIN
Fig 24. Block diagram of timer Z
Rev.1.10 Nov 14, 2005 Page 37 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
Timer Z mode register
(TZM : address 002A16)
Timer Z operating mode bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Timer/Event counter mode
1 : Pulse output mode
0 : Pulse period measurement mode
1 : Pulse width measurement mode
0 : Programmable waveform generating mode
1 : Programmable one-shot generating mode
0 : Not available
1 : Not available
Timer Z write control bit
0 : Writing data to both latch and timer simultaneously
1 : Writing data only to latch
Output level latch
0 : “L” output
1 : “H” output
CNTR2 active edge switch bit
0 : •Event counter mode: Count at rising edge
•Pulse output mode: Start outputting “H”
•Pulse period measurement mode: Measurement between two falling edges
•Pulse width measurement mode: Measurement of “H” term
•Programmable one-shot generating mode: After start outputting “L”,
“H” one-shot pulse generated
•Interrupt at falling edge
1 : •Event counter mode: Count at falling edge
•Pulse output mode: Start outputting “L”
•Pulse period measurement mode: Measurement between two rising edges
•Pulse width measurement mode: Measurement of “L” term
•Programmable one-shot generating mode: After start outputting “H”,
“L” one-shot pulse generated
•Interrupt at rising edge
Timer Z count stop bit
0 : Count start
1 : Count stop
Timer/Event counter mode switch bit (Note)
0 : Timer mode
1 : Event counter mode
Note: When selecting the modes except the timer/event counter mode, set “0” to this bit.
Fig 25. Structure of timer Z mode register
Rev.1.10 Nov 14, 2005 Page 38 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
FFFF16
TL
000016
TR
TR
TR
TL : Value set to timer latch
TR : Timer interrupt request
Fig 26. Timing chart of timer/event counter mode
FFFF16
TL
000016
TR
TR
TR
TR
Waveform output
from CNTR2 pin
CNTR2
CNTR2
TL : Value set to timer latch
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
(CNTR2 active edge switch bit = “0”; Falling edge active)
Fig 27. Timing chart of pulse output mode
Rev.1.10 Nov 14, 2005 Page 39 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
000016
T3
T2
T1
FFFF16
TR
FFFF16 + T1
TR
T2
T3
FFFF16
Signal input from
CNTR2 pin
CNTR2 CNTR2
CNTR2
CNTR2
CNTR2 of rising edge active
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
Fig 28. Timing chart of pulse period measurement mode (Measuring term between two rising edges)
000016
T3
T2
T1
FFFF16
TR
FFFF16 + T2
T3
T1
Signal input from
CNTR2 pin
CNTR2
CNTR2
CNTR2
CNTR2 interrupt of rising edge active; Measurement of “L” width
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
Fig 29. Timing chart of pulse width measurement mode (Measuring “L” term)
Rev.1.10 Nov 14, 2005 Page 40 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
FFFF16
T3
L
T2
T1
000016
Signal output from
CNTR2 pin
L
T3
T1
T2
TR
TR
CNTR2
TR
TR
CNTR2
L : Timer initial value
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
(CNTR2 active edge switch bit = “0”; Falling edge active)
Fig 30. Timing chart of programmable waveform generating mode
FFFF16
L
TR
TR
TR
Signal input from
INT1 pin
Signal output from
CNTR2 pin
L
L
L
CNTR2
CNTR2
L : One-shot pulse width
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
(CNTR2 active edge switch bit = “0”; Falling edge active)
Fig 31. Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating)
Rev.1.10 Nov 14, 2005 Page 41 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
SERIAL INTERFACE
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control
register (bit 6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
• Serial I/O1
Serial I/O1 can be used as either clock synchronous or
asynchronous (UART) serial I/O. A dedicated timer is also
provided for baud rate generation.
Data bus
Serial I/O1 control register
Address 001A16
Address 001816
Receive buffer register 1
Receive buffer full flag (RBF)
Receive shift register 1
Receive interrupt request (RI)
P44/RXD1
Shift clock
Clock control circuit
P46/SCLK1
Serial I/O1 synchronous clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN)
Baud rate generator 1
Address 001C16
1/4
(f(XCIN) in low-speed mode)
1/4
Falling-edge detector
Clock control circuit
F/F
P47/SRDY1
P45/TXD1
Shift clock
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit shift register 1
Transmit interrupt request (TI)
Transmit buffer register 1
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig 32. Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Serial output TXD1
Serial input RXD1
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register 1 (address 001816)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output
continuously from the TXD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Fig 33. Operation of clock synchronous serial I/O1
Rev.1.10 Nov 14, 2005 Page 42 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
(2) Asynchronous Serial I/O (UART) Mode
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in a memory. Since the
shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer register, and receive data is
read from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
Data bus
Serial I/O1 control register
Address 001A16
Address 001816
Receive buffer register 1
OE
Character length selection bit
Receive buffer full flag (RBF)
Receive interrupt request (RI)
ST detector
P44/RXD1
7 bits
8 bits
Receive shift register 1
1/16
UART1 control register
Address 001B16
SP detector
PE FE
Clock control circuit
Serial I/O1 synchronous clock selection bit
P46/SCLK1
Frequency division ratio 1/(n+1)
Baud rate generator
BRG count source selection bit
1/4
f(XIN)
(f(XCIN) in low-speed mode)
Address 001C16
ST/SP/PA generator
1/16
Transmit shift
completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
P45/TXD1
Transmit shift register 1
Character length selection bit
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Transmit buffer register 1
Address 001816
Address 001916
Data bus
Fig 34. Block diagram of UART serial I/O1
Transmit or
receive clock
Transmit buffer
write signal
TBE=0
TBE=0
TSC=0
TBE=1
TBE=1
TSC=1*
ST
D0
D1
SP
ST
D0
D1
SP
Serial output
TXD1
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer
read signal
RBF=0
RBF=1
SP
RBF=1
SP
Serial input
RXD1
ST
D0
D1
ST
D0
D1
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.
Fig 35. Operation of UART serial I/O1
Rev.1.10 Nov 14, 2005 Page 43 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
[Transmit Buffer Register 1/Receive Buffer Register 1
(TB1/RB1)] 001816
The transmit buffer register 1 and the receive buffer register 1 are
located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits,
the MSB of data stored in the receive buffer is “0”.
[Serial I/O1 Status Register (SIO1STS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the
receive buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer
register, and the receive buffer full flag is set. A write to the
serial I/O1 status register clears all the error flags OE, PE, FE,
and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1
enable bit SIOE (bit 7 of the serial I/O1 control register) also
clears all the status flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1
control register has been set to “1”, the transmit shift completion
flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O1 Control Register (SIO1CON)] 001A16
The serial I/O1 control register consists of eight control bits for
the serial I/O1 function.
[UART1 Control Register (UART1CON)] 001B16
The UART control register consists of four control bits (bits 0 to
3) which are valid when asynchronous serial I/O is selected and
set the data format of an data transfer, and one bit (bit 4) which is
always valid and sets the output structure of the P45/TXD1 pin.
[Baud Rate Generator 1 (BRG1)] 001C16
The baud rate generator determines the baud rate for serial
transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate
generator.
Rev.1.10 Nov 14, 2005 Page 44 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
b7
b0
Serial I/O1 status register
Serial I/O1 control register
(SIO1STS : address 001916)
(SIO1CON : address 001A16)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O1 is selected, external clock input divided by 16
when UART is selected.
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
SRDY1 output enable bit (SRDY)
0: P47 pin operates as normal I/O pin
1: P47 pin operates as SRDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
0: Transmit disabled
1: Framing error
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P44 to P47 operate as normal I/O pins)
1: Serial I/O1 enabled
(pins P44 to P47 operate as serial I/O1 pins)
b7
b0
UART1 control register
(UART1CON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD1 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig 36. Structure of serial I/O1 control registers
Rev.1.10 Nov 14, 2005 Page 45 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
<Notes concerning serial I/O1>
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
• Note
• Note
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial
I/O1 enable bit to “0”.
Clear the serial I/O1 enable bit and the transmit enable bit to
“0” (serial I/O and transmit disabled).
• Reason
• Reason
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O1 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD1, RXD1, SCLK1, and
SRDY1 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD1 pin and an
operation failure occurs.
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O1 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD1, RXD1, SCLK1, and
SRDY1 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD1 pin and an
operation failure occurs.
1.2 Stop of receive operation
• Note
2.2 Stop of receive operation
• Note
Clear the receive enable bit to “0” (receive disabled), or clear
the serial I/O1 enable bit to “0” (serial I/O disabled).
Clear the receive enable bit to “0” (receive disabled).
2.3 Stop of transmit/receive operation
• Note 1 (only transmission operation is stopped)
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial
I/O1 enable bit to “0”.
1.3 Stop of transmit/receive operation
• Note
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when data is transmitted and received in the clock
synchronous serial I/O mode, any one of data transmission and
reception cannot be stopped.)
• Reason
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O1 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD1, RXD1, SCLK1, and
SRDY1 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD1 pin and an
operation failure occurs.
• Reason
In the clock synchronous serial I/O mode, the same clock is
used for transmission and reception. If any one of transmission
and reception is disabled, a bit error occurs because
transmission and reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also
operates for data reception. Accordingly, the transmission
circuit does not stop by clearing only the transmit enable bit to
“0” (transmit disabled). Also, the transmission circuit is not
initialized by clearing the serial I/O1 enable bit to “0” (serial
I/O disabled) (refer to 1.1).
• Note 2 (only receive operation is stopped)
Clear the receive enable bit to “0” (receive disabled).
Rev.1.10 Nov 14, 2005 Page 46 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
3. SRDY1 output of reception side
• Note
7. Transmit interrupt request when transmit enable bit is set
• Note
When signals are output from the SRDY1 pin on the reception
side by using an external clock in the clock synchronous serial
I/O mode, set all of the receive enable bit, the SRDY1 output
enable bit, and the transmit enable bit to “1” (transmit
enabled).
When using the transmit interrupt, take the following
sequence.
1. Set the serial I/O1 transmit interrupt enable bit to “0” (dis-
abled).
2. Set the transmit enable bit to “1”.
3. Set the serial I/O1 transmit interrupt request bit to “0” after
1 or more instruction has executed.
4. Set the serial I/O1 transmit interrupt enable bit to “1”
(enabled).
4. Setting serial I/O1 control register again
• Note
Set the serial I/O1 control register again after the transmission
and the reception circuits are reset by clearing both the
transmit enable bit and the receive enable bit to “0”.
• Reason
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and the transmit shift register shift completion flag
are also set to “1”. Therefore, regardless of selecting which
timing for the generating of transmit interrupts, the interrupt
request is generated and the transmit interrupt request bit is set
at this point.
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of
the serial I/O1 control register
Can be set with the
LDM instruction at
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
the same time
5.Data transmission control with referring to transmit shift
register completion flag
• Note
After the transmit data is written to the transmit buffer register,
the transmit shift register completion flag changes from “1” to
“0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after
writing the data to the transmit buffer register, note the delay.
6. Transmission control when external clock is selected
• Note
When an external clock is used as the synchronous clock for
data transmission, set the transmit enable bit to “1” at “H” of
the SCLK1 input level. Also, write data to the transmit buffer
register at “H” of the SCLK1 input level.
Rev.1.10 Nov 14, 2005 Page 47 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
• Serial I/O2
The serial I/O2 function can be used only for clock synchronous
serial I/O.
b7
b0
For clock synchronous serial I/O2, the transmitter and the
receiver must use the same clock. If the internal clock is used,
transfer is started by a write signal to the serial I/O2 register
(address 001F16).
Serial I/O2 control register
(SIO2CON : address 001D16)
Internal synchronous clock selection bits
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
0: f(XIN)/128 f(XCIN)/128 in low-speed mode)
1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
[Serial I/O2 Control Register (SIO2CON)] 001D16
The serial I/O2 control register contains eight bits which control
various serial I/O2 functions.
Serial I/O2 port selection bit
0: I/O port
1: SOUT2, SCLK2 signal output
SRDY2 output enable bit
0: I/O port
1: SRDY2 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P51/SOUT2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Fig 37. Structure of Serial I/O2 control register
Internal synchronous
clock selection bits
1/8
1/16
1/32
1/64
Data bus
f(XIN)
(f(XCIN) in low-speed mode)
1/128
1/256
P53 latch
Serial I/O2 synchronous
clock selection bit
“0”
“1”
P53/SRDY2
SRDY2 Synchronization
circuit
“1”
SRDY2 output enable bit
“0”
External clock
P52 latch
“0”
P52/SCLK2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
“1”
Serial I/O2 port selection bit
P51 latch
“0”
P51/SOUT2
P50/SIN2
“1”
Serial I/O2 port selection bit
Serial I/O2 register (8)
Address 001F16
Fig 38. Block diagram of serial I/O2
Rev.1.10 Nov 14, 2005 Page 48 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output SOUT2
Serial I/O2 input SIN2
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or (f(XCIN) in low-speed mode, can be selected by
setting bits 0 to 2 of the serial I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion.
Fig 39. Timing of serial I/O2
Rev.1.10 Nov 14, 2005 Page 49 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
• Serial I/O3
(1) Clock Synchronous Serial I/O Mode
Serial I/O3 can be used as either clock synchronous or
asynchronous (UART) serial I/O3. A dedicated timer is also
provided for baud rate generation.
Clock synchronous serial I/O3 mode can be selected by setting
the serial I/O3 mode selection bit of the serial I/O3 control
register (bit 6 of address 003216) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Data bus
Serial I/O3 control register
Address 003216
Address 003016
Receive buffer register 3
Receive buffer full flag (RBF)
Receive shift register 3
Receive interrupt request (RI)
P34/RXD3
Shift clock
Clock control circuit
P36/SCLK3
Serial I/O3 synchronous clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN)
Baud rate generator 3
Address 002F16
1/4
(f(XCIN) in low-speed mode)
1/4
Falling-edge detector
Clock control circuit
F/F
P37/SRDY3
P35/TXD3
Shift clock
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit shift register 3
Transmit interrupt request (TI)
Transmit buffer register 3
Transmit buffer empty flag (TBE)
Serial I/O3 status register
Address 003116
Address 003016
Data bus
Fig 40. Block diagram of clock synchronous serial I/O3
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Serial output TXD3
Serial input RXD3
Receive enable signal SRDY3
Write pulse to receive/transmit
buffer register (address 003016)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output
continuously from the TXD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Fig 41. Operation of clock synchronous serial I/O3
Rev.1.10 Nov 14, 2005 Page 50 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
(2) Asynchronous Serial I/O (UART) Mode
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in a memory. Since the
shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer register, and receive data is
read from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O3 mode selection bit (b6) of the serial I/O3
control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
Data bus
Serial I/O3 control register
Address 003216
Address 003016
Receive buffer register 3
OE
Character length selection bit
Receive buffer full flag (RBF)
Receive interrupt request (RI)
ST detector
P34/RXD3
7 bits
8 bits
Receive shift register 3
1/16
UART3 control register
Address 003316
SP detector
PE FE
Clock control circuit
Serial I/O3 synchronous clock selection bit
P36/SCLK3
Frequency division ratio 1/(n+1)
Baud rate generator 3
Address 002F16
BRG count source selection bit
1/4
f(XIN)
(f(XCIN) in low-speed mode)
ST/SP/PA generator
1/16
Transmit shift
completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
P35/TXD3
Transmit shift register 3
Character length selection bit
Transmit buffer empty flag (TBE)
Serial I/O3 status register
Transmit buffer register 3
Address 003016
Address 003116
Data bus
Fig 42. Block diagram of UART serial I/O3
Transmit or
receive clock
Transmit buffer
write signal
TBE=0
TBE=0
TSC=0
TBE=1
TBE=1
TSC=1*
Serial output
TXD3
ST
D0
D1
SP
ST
D0
D1
SP
1 start bit
* Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer
read signal
RBF=0
RBF=1
SP
RBF=1
SP
Serial input
RXD3
ST
D0
D1
ST
D0
D1
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O3 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.
Fig 43. Operation of UART serial I/O3
Rev.1.10 Nov 14, 2005 Page 51 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
[Transmit Buffer Register 3/Receive Buffer Register 3
(TB3/RB3)] 003016
The transmit buffer register 3 and the receive buffer register 3 are
located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits,
the MSB of data stored in the receive buffer is “0”.
[Serial I/O3 Status Register (SIO3STS)] 003116
The read-only serial I/O3 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O3
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the
receive buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer
register, and the receive buffer full flag is set. A write to the
serial I/O3 status register clears all the error flags OE, PE, FE,
and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O3
enable bit SIOE (bit 7 of the serial I/O3 control register) also
clears all the status flags, including the error flags.
Bits 0 to 6 of the serial I/O3 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O3
control register has been set to “1”, the transmit shift completion
flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O3 Control Register (SIO3CON)] 003216
The serial I/O3 control register consists of eight control bits for
the serial I/O3 function.
[UART3 Control Register (UART3CON)] 003316
The UART control register consists of four control bits (bits 0 to
3) which are valid when asynchronous serial I/O is selected and
set the data format of an data transfer, and one bit (bit 4) which is
always valid and sets the output structure of the P35/TXD3 pin.
[Baud Rate Generator 3 (BRG3)] 002F16
The baud rate generator determines the baud rate for serial
transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate
generator.
Rev.1.10 Nov 14, 2005 Page 52 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
b7
b0
Serial I/O3 status register
Serial I/O3 control register
(SIO3STS : address 003116)
(SIO3CON : address 003216)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Serial I/O3 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O3 is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O3 is selected, external clock input divided by 16
when UART is selected.
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
SRDY3 output enable bit (SRDY)
0: P37 pin operates as normal I/O pin
1: P37 pin operates as SRDY3 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
0: Transmit disabled
1: Framing error
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
Serial I/O3 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O3 enable bit (SIOE)
0: Serial I/O3 disabled
(pins P34 to P37 operate as normal I/O pins)
1: Serial I/O3 enabled
(pins P34 to P37 operate as serial I/O3 pins)
b7
b0
UART3 control register
(UART3CON : address 003316)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P35/TXD3 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig 44. Structure of serial I/O3 control registers
Rev.1.10 Nov 14, 2005 Page 53 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
<Notes concerning serial I/O3>
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
• Note
• Note
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial
I/O3 enable bit to “0”.
Clear the serial I/O3 enable bit and the transmit enable bit to
“0” (serial I/O and transmit disabled).
• Reason
• Reason
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O3 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD3, RXD3, SCLK3, and
SRDY3 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O3 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD3 pin and an
operation failure occurs.
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O3 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD3, RXD3, SCLK3, and
SRDY3 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O3 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD3 pin and an
operation failure occurs.
1.2 Stop of receive operation
• Note
2.2 Stop of receive operation
• Note
Clear the receive enable bit to “0” (receive disabled), or clear
the serial I/O3 enable bit to “0” (serial I/O disabled).
Clear the receive enable bit to “0” (receive disabled).
2.3 Stop of transmit/receive operation
• Note 1 (only transmission operation is stopped)
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial
I/O3 enable bit to “0”.
1.3 Stop of transmit/receive operation
• Note
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when data is transmitted and received in the clock
synchronous serial I/O mode, any one of data transmission and
reception cannot be stopped.)
• Reason
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O3 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins TXD3, RXD3, SCLK3, and
SRDY3 function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O3 enable bit is set to “1” at this time, the
data during internally shifting is output to the TXD3 pin and an
operation failure occurs.
• Reason
In the clock synchronous serial I/O mode, the same clock is
used for transmission and reception. If any one of transmission
and reception is disabled, a bit error occurs because
transmission and reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also
operates for data reception. Accordingly, the transmission
circuit does not stop by clearing only the transmit enable bit to
“0” (transmit disabled). Also, the transmission circuit is not
initialized by clearing the serial I/O3 enable bit to “0” (serial
I/O disabled) (refer to 1.1).
• Note 2 (only receive operation is stopped)
Clear the receive enable bit to “0” (receive disabled).
Rev.1.10 Nov 14, 2005 Page 54 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
3. SRDY3 output of reception side
• Note
7. Transmit interrupt request when transmit enable bit is set
• Note
When signals are output from the SRDY3 pin on the reception
side by using an external clock in the clock synchronous serial
I/O mode, set all of the receive enable bit, the SRDY3 output
enable bit, and the transmit enable bit to “1” (transmit
enabled).
When using the transmit interrupt, take the following
sequence.
1. Set the serial I/O3 transmit interrupt enable bit to “0” (dis-
abled).
2. Set the transmit enable bit to “1”.
3. Set the serial I/O3 transmit interrupt request bit to “0” after
1 or more instruction has executed.
4. Set the serial I/O3 transmit interrupt enable bit to “1”
(enabled).
4. Setting serial I/O3 control register again
• Note
Set the serial I/O3 control register again after the transmission
and the reception circuits are reset by clearing both the
transmit enable bit and the receive enable bit to “0”.
• Reason
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and the transmit shift register shift completion flag
are also set to “1”. Therefore, regardless of selecting which
timing for the generating of transmit interrupts, the interrupt
request is generated and the transmit interrupt request bit is set
at this point.
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of
the serial I/O3 control register
Can be set with the
LDM instruction at
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
the same time
5.Data transmission control with referring to transmit shift
register completion flag
• Note
After the transmit data is written to the transmit buffer register,
the transmit shift register completion flag changes from “1” to
“0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after
writing the data to the transmit buffer register, note the delay.
6. Transmission control when external clock is selected
• Note
When an external clock is used as the synchronous clock for
data transmission, set the transmit enable bit to “1” at “H” of
the SCLK3 input level. Also, write data to the transmit buffer
register at “H” of the SCLK input level.
Rev.1.10 Nov 14, 2005 Page 55 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
PULSE WIDTH MODULATION (PWM)
• PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set
to “1”, operation starts by initializing the PWM output circuit,
and pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
The 3803 group (Spec.H QzROM version) has PWM functions
with an 8-bit resolution, based on a signal that is the clock input
XIN or that clock input divided by 2 or the clock input XCIN or
that clock input divided by 2 in low-speed mode.
• Data Setting
The PWM output pin also functions as port P56. Set the PWM
period by the PWM prescaler, and set the “H” term of output
pulse by the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255):
PWM period = 255 × (n+1) / f(XIN)
31.875 × m × (n+1)
µs
255
= 31.875 × (n+1) µs
PWM output
(when f(XIN) = 8 MHz, count source selection bit = “0”)
Output pulse “H” term = PWM period × m / 255
= 0.125 × (n+1) × m µs
T = [31.875 × (n+1)] µs
(when f(XIN) = 8 MHz, count source selection bit = “0”)
m : Contents of PWM register
n : Contents of PWM prescaler
T : PWM period
(when f(XIN) = 8 MHz, count source selection bit = “0”)
Fig 45. Timing of PWM period
Data bus
PWM
prescaler pre-latch
PWM
register pre-latch
Transfer control circuit
PWM
prescaler latch
PWM
register latch
Count source
selection bit
Port P56
“0”
PWM prescaler
PWM register
XIN
(XCIN at low-
speed mode)
“1”
1/2
Port P56 latch
PWM function enable bit
Fig 46. Block diagram of PWM function
Rev.1.10 Nov 14, 2005 Page 56 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
b7
b0
PWM control register
(PWMCON: address 002B16)
PWM function enable bit
0 : PWM disabled
1 : PWM enabled
Count source selection bit
0 : f(XIN) (f(XCIN) at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Not used
(return “0” when read)
Fig 47. Structure of PWM control register
B
T
C
T2
=
A
B
C
PWM output
T
T
T2
PWM register
write signal
(Changes “H” term from “A” to “ B”.)
PWM prescaler
write signal
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed,
the PWM output will change from the next period after the change.
Fig 48. PWM output timing when PWM register or PWM prescaler is changed
<Notes>
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L” level output is as follows:
n + 1
2×f(XIN)
(Count source selection bit = 0, where n is the value set in the prescaler)
(Count source selection bit = 1, where n is the value set in the prescaler)
-----------------------
sec
n + 1
f(XIN)
---------------
sec
Rev.1.10 Nov 14, 2005 Page 57 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
A/D CONVERTER
• Channel Selector
The channel selector selects one of ports P67/AN7 to P60/AN0 or
P07/AN15 to P00/AN8, and inputs the voltage to the comparator.
[AD Conversion Register 1, 2 (AD1, AD2)] 003516,
003816
The AD conversion register is a read-only register that stores the
result of an A/D conversion. When reading this register during an
A/D conversion, the previous conversion result is read.
• Comparator and Control Circuit
The comparator and control circuit compares an analog input
voltage with the comparison voltage, and then stores the result in
the AD conversion registers 1, 2. When an A/D conversion is
completed, the control circuit sets the AD conversion completion
bit and the AD interrupt request bit to “1”.
Note that because the comparator consists of a capacitor
coupling, set f(XIN) to 500 kHz or more during an A/D
conversion.
Bit 7 of the AD conversion register 2 is the conversion mode
selection bit. When this bit is set to “0”, the A/D converter
becomes the 10-bit A/D mode. When this bit is set to “1”, that
becomes the 8-bit A/D mode. The conversion result of the 8-bit
A/D mode is stored in the AD conversion register 1. As for 10-bit
A/D mode, not only 10-bit reading but also only high-order 8-bit
reading of conversion result can be performed by selecting the
reading procedure of the AD conversion registers 1, 2 after A/D
conversion is completed (in Figure.50).
As for 10-bit A/D mode, the 8-bit reading inclined to MSB is
performed when reading the AD converter register 1 after A/D
conversion is started; and when the AD converter register 1 is
read after reading the AD converter register 2, the 8-bit reading
inclined to LSB is performed.
b7
b0
AD/DA control register
(ADCON : address 003416)
Analog input pin selection bits 1
b2 b1 b0
0 0 0: P60/AN0 or P00/AN8
0 0 1: P61/AN1 or P01/AN9
0 1 0: P62/AN2 or P02/AN10
0 1 1: P63/AN3 or P03/AN11
1 0 0: P64/AN4 or P04/AN12
1 0 1: P65/AN5 or P05/AN13
1 1 0: P66/AN6 or P06/AN14
1 1 1: P67/AN7 or P07/AN15
[AD/DA Control Register (ADCON)] 003416
The AD/DA control register controls the A/D conversion
process. Bits 0 to 2 and bit 4 select a specific analog input pin.
Bit 3 signals the completion of an A/D conversion. The value of
this bit remains at “0” during an A/D conversion, and changes to
“1” when an A/D conversion ends. Writing “0” to this bit starts
the A/D conversion.
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
• Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024, and that outputs the comparison
voltage in the 10-bit A/D mode (256 division in 8-bit A/D mode).
The A/D converter successively compares the comparison
voltage Vref in each mode, dividing the VREF voltage (see
below), with the input voltage.
Analog input pin selection bit 2
0: AN0 to AN7 side
1: AN8 to AN15 side
Not used (returns “0” when read)
DA1 output enable bit
0: DA1 output disabled
1: DA1 output enabled
• 10-bit A/D mode (10-bit reading)
DA2 output enable bit
0: DA2 output disabled
1: DA2 output enabled
VREF
1024
-------------
Vref =
× n (n = 0 − 1023)
• 10-bit A/D mode (8-bit reading)
Fig 49. Structure of AD/DA control register
VREF
256
-------------
Vref =
× n (n = 0 − 255)
• 8-bit A/D mode
8-bit reading
(Read only address 003516)
VREF
256
-------------
Vref =
× n (n − 0.5) (n = 1 − 255)
b7
b0
=0
(n = 0)
AD conversion register 1
(AD1: address 003516)
b9 b8 b7 b6 b5 b4 b3 b2
10-bit reading
(Read address 003816 before 003516)
b7
b0
AD conversion register 2
(AD2: address 003816)
0
b9 b8
b7
b0
AD conversion register 1
(AD1: address 003516)
b7 b6 b5 b4 b3 b2 b1 b0
Note : Bits 2 to 6 of address 003816 become “0” at reading.
Fig 50. Structure of 10-bit A/D mode reading
Rev.1.10 Nov 14, 2005 Page 58 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Data bus
b7
b0
AD/DA control register
(Address 003416)
4
P60/AN0
P61/AN1
P62/AN2
P63/AN3
A/D converter interrupt request
A/D control circuit
AD conversion register 2
AD conversion register 1
(Address 003816)
(Address 003516)
Comparator
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P00/AN8
P01/AN9
P02/AN10
P03/AN11
P04/AN12
P05/AN13
P06/AN14
P07/AN15
10
Resistor ladder
VREF AVSS
Fig 51. Block diagram of A/D converter
Rev.1.10 Nov 14, 2005 Page 59 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
D/A CONVERTER
The 3803 group (Spec.H QzROM version) has two internal D/A
converters (DA1 and DA2) with 8-bit resolution.
The D/A conversion is performed by setting the value in each
DA conversion register. The result of D/A conversion is output
from the DA1 or DA2 pin by setting the DA output enable bit to
“1”.
When using the D/A converter, the corresponding port direction
register bit (P30/DA1 or P31/DA2) must be set to “0” (input
status).
The output analog voltage V is determined by the value n
(decimal notation) in the DA conversion register as follows:
DA1 conversion register (8)
DA1 output enable bit
R-2R resistor ladder
P30/DA1
V = VREF× n/256 (n = 0 to 255)
Where VREF is the reference voltage.
At reset, the DA conversion registers are cleared to “0016”, and
the DA output enable bits are cleared to “0”, and the P30/DA1
and P31/DA2 pins become high impedance.
DA2 conversion register (8)
The DA output does not have buffers. Accordingly, connect an
external buffer when driving a low-impedance load.
DA2 output enable bit
P31/DA2
R-2R resistor ladder
Fig 52. Block diagram of D/A converter
DA1 output enable bit
“0”
R
R
R
R
R
R
R
2R
P30/DA1
“1”
2R
2R
2R
2R
2R
2R
2R
2R
MSB
“0”
LSB
DA1 conversion register
“1”
AVSS
VREF
Fig 53. Equivalent connection circuit of D/A converter (DA1)
Rev.1.10 Nov 14, 2005 Page 60 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
WATCHDOG TIMER
• Bit 6 of Watchdog Timer Control Register
• When bit 6 of the watchdog timer control register is “0”, the
MCU enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer restarts
counting(Note.). When executing the WIT instruction, the
watchdog timer does not stop.
• When bit 6 is “1”, execution of STP instruction causes an
internal reset. When this bit is set to “1” once, it cannot be
rewritten to “0” by program. Bit 6 is “0” at reset.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example,
because of a software run-away). The watchdog timer consists of
an 8-bit watchdog timer L and an 8-bit watchdog timer H.
• Watchdog Timer Initial Value
Watchdog timer L is set to “FF16” and watchdog timer H is set to
“FF16” by writing to the watchdog timer control register (address
001E16) or at a reset. Any write instruction that causes a write
signal can be used, such as the STA, LDM, CLB, etc. Data can
only be written to bits 6 and 7 of the watchdog timer control
register. Regardless of the value written to bits 0 to 5, the above-
mentioned value will be set to each timer.
The following shows the period between the write execution to
the watchdog timer control register and the underflow of
watchdog timer H.
Bit 7 of the watchdog timer control register is “0”:
when XCIN = 32.768 kHz; 32 s
• Watchdog Timer Operations
when XIN = 16 MHz; 65.536 ms
The watchdog timer stops at reset and starts to count down by
writing to the watchdog timer control register (address 001E16).
An internal reset occurs at an underflow of the watchdog timer
H. The reset is released after waiting for a reset release time and
the program is processed from the reset vector address.
Accordingly, programming is usually performed so that writing
to the watchdog timer control register may be started before an
underflow. If writing to the watchdog timer control register is not
performed once, the watchdog timer does not function.
Bit 7 of the watchdog timer control register is “1”:
when XCIN = 32.768 kHz; 125 ms
when XIN = 16 MHz; 256 µs
Note. The watchdog timer continues to count even while waiting for a
stop release. Therefore, make sure that watchdog timer H does not
underflow during this period.
“FF16” is set when
watchdog timer
Data bus
control register is
written to.
XCIN
“FF16” is set when
watchdog timer
control register is
written to.
“0”
“10”
Watchdog timer L (8)
Main clock division
ratio selection bits (Note)
Watchdog timer H (8)
“1”
1/16
“00”
“01”
Watchdog timer H count
source selection bit
XIN
STP instruction function selection bit
STP instruction
Reset
Internal reset
circuit
RESET
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig 54. Block diagram of Watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 001E16)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction function selection bit
0: Entering stop mode by execution of STP instruction
1: Internal reset by execution of STP instruction
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig 55. Structure of Watchdog timer control register
Rev.1.10 Nov 14, 2005 Page 61 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 16 cycles or more of XIN. Then the RESET pin is
returned to an “H” level (the power source voltage should be
between 1.8 V and 5.5 V, and the oscillation should be stable),
reset is released. After the reset is completed, the program starts
from the address contained in address FFFD16 (high-order byte)
and address FFFC16 (low-order byte). Make sure that the reset
input voltage is less than 0.29 V for VCC of 1.8 V.
1.8 V
VCC
0 V
RESET
VCC
RESET
0 V
0.29 V or less
RESET
VCC
Power source voltage
detection circuit
Example at VCC = 5 V
Fig 56. Reset circuit example
XIN
φ
RESET
Internal
reset
Address
?
?
?
?
FFFC
FFFD
ADH,L
Reset address from the
vector table.
Data
?
?
?
?
ADL
ADH
SYNC
XIN : 10.5 to 18.5 clock cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig 57. Reset sequence
Rev.1.10 Nov 14, 2005 Page 62 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Address
Address
Register contents
0016
Register contents
FF16
(1)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
Port P0 (P0)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
002816
002916
002A16
002B16
002C16
002D16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
(PS)
Timer Z (low-order) (TZL)
0016
0016
0016
0016
FF16
(2)
Port P0 direction register (P0D)
Port P1 (P1)
Timer Z (high-order) (TZH)
0016
(3)
Timer Z mode register (TZM)
0016
(4)
Port P1 direction register (P1D)
Port P2 (P2)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
(5)
0016
0016
0016
0016
0016
0016
0016
0016
0016
(6)
Port P2 direction register (P2D)
Port P3 (P3)
PWM register (PWM)
(7)
Baud rate generator 3 (BRG3)
(8)
Port P3 direction register (P3D)
Port P4 (P4)
Transmit/Receive buffer register 3 (TB3/RB3)
Serial I/O3 status register (SIO3STS)
Serial I/O3 control register (SIO3CON)
UART3 control register (UART3CON)
AD/DA control register (ADCON)
AD conversion register 1 (AD1)
DA1 conversion register (DA1)
1
0
0
0
0
0
0
0
(9)
0016
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
Port P4 direction register (P4D)
Port P5 (P5)
1
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
Port P5 direction register (P5D)
Port P6 (P6)
X X X X X X X X
0016
0016
Port P6 direction register (P6D)
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
MISRG
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DA2 conversion register (DA2)
0
0
0
1
0
0
0
0
0
0
X X
AD conversion register 2 (AD2)
Interrupt source selection register (INTSEL)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
0016
0016
0016
X X X X X X
X
1
X
0
Transmit/Receive buffer register 1 (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
Baud rate generator 1 (BRG1)
Serial I/O2 control register (SIO2CON)
Watchdog timer control register (WDTCON)
Serial I/O2 register (SIO2)
Prescaler 12 (PRE12)
0
1
0
0
0
0
0
0
0
0
0016
0016
0016
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Port P0 pull-up control register (PULL0)
Port P1 pull-up control register (PULL1)
Port P2 pull-up control register (PULL2)
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
Port P5 pull-up control register (PULL5)
Port P6 pull-up control register (PULL6)
Processor status register
1
1
1
0 0
0
0
0
0016
0016
0016
0016
0016
X X X X X X X X
0016
0
0 1 1 1 1 1 1
X X X X X X X X
FF16
Timer 1 (T1)
0116
FF16
0016
FF16
0016
0016
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
0016
0016
FF16
FF16
FF16
Timer X (TX)
X X X X X
1
X
X
Prescaler Y (PREY)
(PCH)
FFFD16 contents
FFFC16 contents
Program counter
Timer Y (TY)
(PCL)
Note : X: Not fixed.
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Fig 58. Internal status at reset
Rev.1.10 Nov 14, 2005 Page 63 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
CLOCK GENERATING CIRCUIT
Oscillation Control
(1) Stop mode
The 3803 group (Spec.H QzROM version) has two built-in
oscillation circuits: main clock XIN-XOUT oscillation circuit and
sub clock XCIN-XCOUT oscillation circuit. An oscillation circuit
can be formed by connecting a resonator between XIN and XOUT
(XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No external
resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip.(An external feed-back resistor may be
needed depending on conditions.) However, an external feed-
back resistor is needed between XCIN and XCOUT.
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. When the
oscillation stabilizing time set after STP instruction released bit
(bit 0 of address 001016) is “0”, the prescaler 12 is set to “FF16”
and timer 1 is set to “0116”. When the oscillation stabilizing time
set after STP instruction released bit is “1”, set the sufficient time
for oscillation of used oscillator to stabilize since nothing is set to
the prescaler 12 and timer 1.
After STP instruction is released, the input of the prescaler 12 is
connected to count source which had set at executing the STP
instruction, and the output of the prescaler 12 is connected to
timer 1. Oscillator restarts when an external interrupt is received,
but the internal clock φ is not supplied to the CPU (remains at
“H”) until timer 1 underflows. The internal clock φ is supplied
for the first time, when timer 1 underflows. This ensures time for
the clock oscillation using the ceramic resonators to be
stabilized. When the oscillator is restarted by reset, apply “L”
level to the RESET pin until the oscillation is stable since a wait
time will not be generated.
Immediately after power on, only the XIN oscillation circuit
starts oscillating, and XCIN and XCOUT pins function as I/O ports.
• Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After
reset is released, this mode is selected.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
(2) Wait mode
The internal clock φ is half the frequency of XCIN.
(4) Low power dissipation mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ
restarts at reset or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
The low power consumption operation can be realized by
stopping the main clock XIN in low-speed mode. To stop the
main clock, set bit 5 of the CPU mode register to “1”. When the
main clock XIN is restarted (by setting the main clock stop bit to
“0”), set sufficient time for oscillation to stabilize.
The sub-clock XCIN-XCOUT oscillating circuit can not directly
input clocks that are generated externally. Accordingly, make
sure to cause an external resonator to oscillate.
To ensure that the interrupts will be received to release the STP
or WIT state, their interrupt enable bits must be set to “1” before
executing of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP
instruction.
<Notes>
• If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient
time is required for the sub clock to stabilize, especially
immediately after power on and at returning from stop mode.
When switching the mode between middle/high-speed and
low-speed, set the frequency on condition that f(XIN) >
3×f(XCIN).
• When using the quartz-crystal oscillator of high frequency,
such as 16 MHz etc., it may be necessary to select a specific
oscillator with the specification demanded.
• When using the oscillation stabilizing time set after STP
instruction released bit set to “1”, evaluate time to stabilize
oscillation of the used oscillator and set the value to the timer 1
and prescaler 12.
Rev.1.10 Nov 14, 2005 Page 64 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
XCIN XCOUT
XIN
XOUT
Rd (Note)
Rf
Rd
COUT
CCOUT
CIN
CCIN
Notes :Insert a damping resistor if required.
The resistance will vary depending on the oscillator
and the oscillation drive capacity setting.
Use the value recommended by the maker of the
oscillator.
Also, if the oscillator manufacturer's data sheet
specifies to add a feedback resistor externally to
the chip though a feedback resistor exists on-chip,
insert a feedback resistor between XIN and XOUT
following the instruction.
Fig 59. Ceramic resonator circuit
XCIN
XCOUT
XIN
XOUT
Open
Open
External oscillation
circuit
External oscillation
circuit
VCC
VSS
VCC
VSS
Fig 60. External clock input circuit
Rev.1.10 Nov 14, 2005 Page 65 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
XCOUT
XCIN
“0”
“1”
Port XC
switch bit
XIN
XOUT
Main clock division ratio
selection bits (Note 1)
(Note 4)
Divider
Low-speed
mode
Timer 1
Prescaler 12
1/4
1/2
Reset or
STP instruction
(Note 2)
High-speed or
middle-speed mode
(Note 3)
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Reset
Q
S
R
S
R
Q
Q
S
R
STP
instruction
STP
instruction
WIT
instruction
Reset
Interrupt disable flag l
Interrupt request
Notes1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port XC switch bit (b4) to “1”.
2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the STP instruction is
supplied as the count source at executing STP instruction.
3: When bit 0 of MISRG is “0”, timer 1 is set “0116” and prescaler 12 is set “FF16” automatically. When bit 0 of MISRG is “1” , set the
appropriate value to them in accordance with oscillation stabilizing time required by the using oscillator because nothing is
automatically set into timer 1 and prescaler 12.
4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.
Fig 61. System clock generating circuit block diagram (Single-chip mode)
Rev.1.10 Nov 14, 2005 Page 66 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Reset
Middle-speed mode
(f(φ) = 1 MHz)
CM7=0
High-speed mode
(f(φ) = 4 MHz)
CM7=0
CM6
“1”←→”0”
CM6=1
CM5=0 (8 MHz oscillating)
CM4=0 (32 kHz stopped)
CM6=0
CM5=0 (8 MHz oscillating)
CM4=0 (32 kHz stopped)
Middle-speed mode
(f(φ) = 1 MHz)
CM7=0
CM6=1
CM5=0 (8 MHz oscillating)
CM4=1 (32 kHz oscillating)
High-speed mode
(f(φ) = 4 MHz)
CM7=0
CM6=0
CM5=0 (8 MHz oscillating)
CM4=1 (32 kHz oscillating)
CM6
“1”←→”0”
Low-speed mode
(f(φ) = 16 kHz)
CM7=1
CM6=0
CM5=0 (8 MHz oscillating)
CM4=1 (32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN-XOUT) stop bit
0 : Operating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
0 0 : φ = f(XIN)/2 (High-speed mode)
0 1 : φ = f(XIN)/8 (Middle-speed mode)
1 0 : φ = f(XCIN)/2 (Low-speed mode)
1 1 : Not available
Low-speed mode
(f(φ) = 16 kHz)
CM7=1
CM6=0
CM5=1 (8 MHz stopped)
CM4=1 (32 kHz oscillating)
Notes1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the
wait mode is ended.
3: Timer operates in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-
speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode.
6: Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/
high-speed mode.
7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig 62. State transitions of system clock
Rev.1.10 Nov 14, 2005 Page 67 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
NOTES ON PROGRAMMING
Processor Status Register
A/D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) in the middle/high-speed mode
is at least on 500 kHz during an A/D conversion.
Do not execute the STP instruction during an A/D conversion.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”.
After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
D/A Converter
The accuracy of the D/A converter becomes rapidly poor under
the VCC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0
V is recommended. When a D/A converter is not used, set all
values of DAi conversion registers (i=1, 2) to “0016”.
Interrupts
The contents of the interrupt request bits do not change
immediately after they have been written. After writing to an
interrupt request register, execute at least one instruction before
performing a BBC or BBS instruction.
Instruction Execution Time
The instruction execution time is obtained by multiplying the
period of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After
executing an ADC or SBC instruction, execute at least one
instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
The period of the internal clock φ is double of the XIN period in
high-speed mode.
Reserved Area, Reserved Bit
Timers
Do not write any data to the reserved area in the SFR area and the
special page. (Do not change the contents after reset.)
If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
CPU Mode Register
Multiplication and Division Instructions
Be sure to fix bit 3 of the CPU mode register (address 003B16) to
“1”.
• The index X mode (T) and the decimal mode (D) flags do not
affect the MUL and DIV instruction.
• The execution of these instructions does not change the
contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is
“1”
• The instruction with the addressing mode which uses the value
of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction
register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.)
to a direction register.
Use instructions such as LDM and STA, etc., to set the port
direction registers.
Serial Interface
In clock synchronous serial I/O, if the receive side is using an
external clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O1 continues to output the final bit from the TXD pin
after transmission is completed. SOUT2 pin for serial I/O2 goes to
high impedance after transfer is completed.
When in serial I/Os 1 and 3 (clock-synchronous mode) or in
serial I/O2, an external clock is used as synchronous clock, write
transmission data to the transmit buffer register or serial I/O2
register, during transfer clock is “H”.
Rev.1.10 Nov 14, 2005 Page 68 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
NOTES ON USAGE
Termination of Unused Pins.
Be sure to perform the termination of unused pins.
The shortest
(Note)
Handling of Power Source Pins
CNVSS/VPP
In order to avoid a latch-up occurrence, connect a capacitor
suitable for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin), and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the
pins to be connected, a ceramic capacitor of 0.01 µF−0.1 µF is
recommended.
Approx. 5kΩ
VSS
(Note)
The shortest
Note. Shows the microcomputer’s pin.
Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less
than the recommended operating conditions and design a system
not to cause errors to the system by this unstable operation.
Fig 63. Wiring for the CNVSS/VPP
Notes On QzROM Writing Orders
When ordering the QzROM product shipped after writing,
submit the mask file (extension: .msk) which is made by the
mask file converter MM.
Be sure to set the ROM option (“MASK option” written in the
mask file converter) setup when making the mask file by using
the mask file converter MM.
Electric Characteristic Differences Between Flash
Memory, Mask ROM and QzROM Version MCUs
Notes On ROM Code Protect
(QzROM product shipped after writing)
There are differences in the manufacturing processes and the
mask pattern among flash memory, mask ROM, and QzROM
version MCUs due to the differences of the ROM type. Even
when the ROM type is the same, when the memory size is
different, the manufacturing processes and the mask pattern
differ. For these reasons, the oscillation circuit constants and the
characteristics such as a characteristic value, operation margin,
noise immunity, and noise radiation within the limits of electrical
characteristics may differ.
When manufacturing an application system, please perform
sufficient evaluations in each product. Especially, when
switching a product (example: change from the mask ROM
version to QzROM version), please perform sufficient
evaluations by the switching product in the stage before mass-
producing an application system.
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the ROM option setup data in
the mask file which is submitted at ordering.
Renesas Technology corp. uses the ROM option setup data at the
ROM code protect address (address FFDB16) when writing to the
QzROM. Consequently, the actual written value might differ
from the ordered value as the contents of the ROM code protect
address.
The ROM option setup data in the mask file is “0016” for protect
enabled, “FE16” (protect enabled to the protect area 1 only) or
“FF16” for protect disabled. Therefore, the contents of the ROM
code protect address of the QzROM product shipped after
writing are “0016”, “FE16” or “FF16”.
Note that the mask file which has nothing at the ROM option
data or has the data other than “0016”, “FE16” and “FF16” can not
be accepted.
Product Shipped in Blank
As for the product shipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approx.0.1 %
may occur. Moreover, please note the contact of cables and
foreign bodies on a socket, etc. because a writing environment
may cause some writing errors.
DATA REQUIRED FOR QzROM WRITING ORDERS
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark
specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
QzROM Version
Connect the CNVSS/VPP pin the shortest possible to the GND
pattern which is supplied to the VSS pin of the microcomputer.
In addition connecting an approximately 5 kΩ resistor in series to
the GND could improve noise immunity. In this case as well as
the above mention, connect the pin the shortest possible to the
GND pattern which is supplied to the VSS pin of the
microcomputer.
• Reason
The CNVSS/VPP pin is the power source input pin for the built-in
QzROM. When programming in the QzROM, the impedance of
the VPP pin is low to allow the electric current for writing to flow
into the built-in QzROM. Because of this, noise can enter easily.
If noise enters the VPP pin, abnormal instruction codes or data
are read from the QzROM, which may cause a program runaway.
Rev.1.10 Nov 14, 2005 Page 69 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
ELECTRICAL CHARACTERISTICS
Absolute maximum ratings
Table 10 Absolute maximum ratings
Symbol
VCC
Parameter
Conditions
Ratings
−0.3 to 6.5
Unit
V
Power source voltages
All voltages are based on VSS.
When an input voltage is
measured, output transistors
are cut off.
VI
Input voltage
P00-P07, P10-P17, P20-P27,
P30, P31, P34-P37, P40-P47,
P50-P57, P60-P67, VREF
−0.3 to VCC + 0.3
V
VI
VI
Input voltage
Input voltage
P32, P33
RESET, XIN
CNVSS
−0.3 to 5.8
V
V
−0.3 to VCC + 0.3
VI
Input voltage
−0.3 to VCC + 0.3
−0.3 to VCC + 0.3
V
V
VO
Output voltage
P00-P07, P10-P17, P20-P27,
P30, P31, P34-P37, P40-P47,
P50-P57, P60-P67, XOUT
VO
Output voltage
P32, P33
−0.3 to 5.8
1000(1)
V
mW
°C
Pd
Power dissipation
Ta=25 °C
Topr
Operating temperature
Storage temperature
−20 to 85
−65 to 125
Tstg
°C
NOTES:
1. This value is 300 mW except SP package.
Rev.1.10 Nov 14, 2005 Page 70 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Recommended operating conditions
Table 11 Recommended operating conditions (1)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VCC
Parameter
Conditions
Unit
Min.
2.2
2.0
2.2
2.7
4.0
4.5
1.8
2.2
2.7
4.5
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Max.
When start oscillating(2)
Power source
voltage(1)
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
V
V
High-speed mode
f(XIN) ≤ 2.1 MHz
f(φ) = f(XIN)/2
f(XIN) ≤ 4.2 MHz
f(XIN) ≤ 8.4 MHz
f(XIN) ≤ 12.5 MHz
f(XIN) ≤ 16.8 MHz
Middle-speed mode f(XIN) ≤ 6.3 MHz
V
f(φ) = f(XIN)/8
f(XIN) ≤ 8.4 MHz
f(XIN) ≤ 12.5 MHz
f(XIN) ≤ 16.8 MHz
VSS
VIH
Power source voltage
V
V
“H” input voltage
P00-P07, P10-P17,
P20-P27, P30, P31,
P34-P37, P40-P47,
P50-P57, P60-P67
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
0.85 VCC
0.8 VCC
VCC
VCC
VIH
VIH
“H” input voltage
P32, P33
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
0.85 VCC
0.8 VCC
0.85 VCC
0.8 VCC
5.5
5.5
V
V
“H” input voltage
RESET, XIN, XCIN,
CNVSS
VCC
VCC
VIL
VIL
“L” input voltage
P00-P07, P10-P17,
P20-P27, P30-P37,
P40-P47, P50-P57,
P60-P67
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
0
0
0.16 VCC
0.2 VCC
V
V
“L” input voltage
RESET, CNVSS
1.8 ≤ VCC < 2.7 V
2.7 ≤ VCC ≤ 5.5 V
1.8 ≤ VCC ≤ 5.5 V
0
0
0
0.16 VCC
0.2 VCC
VIL
“L” input voltage
XIN, XCIN
0.16 VCC
V
f(XIN)
Main clock input
oscillation
frequency(3)
High-speed mode
f(φ) = f(XIN)/2
2.0 ≤ VCC < 2.2 V
2.2 ≤ VCC < 2.7 V
2.7 ≤ VCC < 4.0 V
4.0 ≤ VCC < 4.5 V
4.5 ≤ VCC ≤ 5.5 V
MHz
(20 × VCC – 36) × 1.05
-----------------------------------------------------------
2
MHz
MHz
MHz
(24 × VCC – 40.8) × 1.05
----------------------------------------------------------------
3
(9 × VCC – 0.3) × 1.05
---------------------------------------------------------
3
(24 × VCC – 60) × 1.05
-----------------------------------------------------------
3
16.8
MHz
MHz
Middle-speed mode 1.8 ≤ VCC < 2.2 V
f(φ) = f(XIN)/8
(15 × VCC – 9) × 1.05
-------------------------------------------------------
3
2.2 ≤ VCC < 2.7 V
2.7 ≤ VCC < 4.5 V
4.5 ≤ VCC ≤ 5.5 V
MHz
MHz
(24 × VCC – 28.8) × 1.05
----------------------------------------------------------------
3
(15 × VCC + 39) × 1.1
--------------------------------------------------------
7
16.8
50
MHz
kHz
Sub-clock input oscillation frequency(3, 4)
f(XCIN)
32.768
NOTES:
1. When using A/D converter, see A/D converter recommended operating conditions.
2. The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating
temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation.
3. When the oscillation frequency has a duty cycle of 50%.
4. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Rev.1.10 Nov 14, 2005 Page 71 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Table 12 Recommended operating conditions (2)
(VCC = 1.8 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
Typ.
Max.
−80
−80
80
“H” total peak output current(1)
“H” total peak output current(1)
“L” total peak output current(1)
“L” total peak output current(1)
“L” total peak output current(1)
“H” total average output current(1)
“H” total average output current(1)
“L” total average output current(1)
“L” total average output current(1)
“L” total average output current(1)
“H” peak output current(2)
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
P00-P07, P10-P17, P20-P27, P30, P31, P34-P37
P40-P47, P50-P57, P60-P67
P00-P07, P10-P17, P30-P37
P20-P27
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
80
P40-P47, P50-P57, P60-P67
P00-P07, P10-P17, P20-P27, P30, P31, P34-P37
P40-P47, P50-P57, P60-P67
P00-P07, P10-P17, P30-P37
P20-P27
80
−40
−40
40
40
P40-P47, P50-P57, P60-P67
40
P00-P07, P10-P17, P20-P27, P30, P31, P34-P37,
P40-P47, P50-P57, P60-P67
−10
“L” peak output current(2)
IOL(peak)
P00-P07, P10-P17, P30-P37, P40-P47, P50-P57,
P60-P67
10
mA
“L” peak output current(2)
IOL(peak)
P20-P27
20
mA
mA
“H” average output current(3)
IOH(avg)
P00-P07, P10-P17, P20-P27, P30, P31, P34-P37,
P40-P47, P50-P57, P60-P67
−5
“L” average output current(3)
“L” average output current(3)
IOL(avg)
P00-P07, P10-P17, P30-P37, P40-P47, P50-P57,
P60-P67
5
mA
mA
IOL(avg)
P20-P27
10
NOTES:
1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured over 100 ms. The total peak current is the peak value of all the currents.
2. The peak output current is the peak current flowing in each port.
3. The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
Rev.1.10 Nov 14, 2005 Page 72 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Electrical characteristics
Table 13 Electrical characteristics (1)
(VCC = 1.8 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
VOH
Parameter
“H” output voltage(1)
P00-P07, P10-P17, P20-P27, P30, P31,
P34-P37, P40-P47, P50-P57, P60-P67
Test conditions
IOH = −10 mA
Min.
Typ.
Max.
VCC − 2.0
V
V
V
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 1.8 to 5.5 V
VCC − 1.0
VOL
“L” output voltage
P00-P07, P10-P17, P20-P27, P30-P37,
P40-P47, P50-P57, P60-P67
IOL = 10 mA
VCC = 4.0 to 5.5 V
2.0
1.0
2.0
0.4
IOL = 1.6 mA
VCC = 1.8 to 5.5 V
VOL
“L” output voltage
P20-P27
IOL = 20 mA
VCC = 4.0 to 5.5 V
IOL = 1.6 mA
VCC = 1.8 to 5.5 V
VT+ − VT−
VT+ − VT−
VT+ − VT−
IIH
Hysteresis
CNTR0, CNTR1, CNTR2, INT0-INT4
0.4
0.5
0.5
V
V
Hysteresis
RxD1, SCLK1, SIN2, SCLK2, RxD3, SCLK3
Hysteresis
RESET
V
“H” input current
P00-P07, P10-P17, P20-P27, P30-P37,
P40-P47, P50-P57, P60-P67
VI = VCC
(Pin floating,
Pull-up transistor “off”)
5.0
5.0
µA
IIH
IIH
IIL
“H” input current
RESET, CNVSS
VI = VCC
VI = VCC
µA
µA
µA
“H” input current
XIN
4.0
“L” input current
P00-P07, P10-P17, P20-P27, P30-P37,
P40-P47, P50-P57, P60-P67
VI = VCC
(Pin floating,
Pull-up transistor “off”)
−5.0
−5.0
IIL
IIL
IIL
“L” input current
RESET, CNVSS
VI = VSS
VI = VSS
µA
µA
µA
“L” input current
XIN
−4.0
−210
−70
“L” input current (at Pull-up)
P00-P07, P10-P17, P20-P27, P30, P31,
P34-P37, P40-P47, P50-P57, P60-P67
VI = VSS
VCC = 5.0 V
−80
−30
1.8
−420
−140
VCC
VI = VSS
VCC = 3.0 V
VRAM
RAM hold voltage
When clock stopped
V
NOTES:
1. P35 is measured when the P35/TXD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”.
P45 is measured when the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
Rev.1.10 Nov 14, 2005 Page 73 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Table 14 Electrical characteristics (2)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, f(XCIN)=32.768kHz (Stopped in middle-speed mode),
Output transistors “off”, AD converter not operated)
Limits
Typ.
8.0
6.5
5.0
2.5
2.0
1.9
1.0
0.6
4.0
3.0
2.5
1.8
1.5
1.2
1.0
55
Symbol
ICC
Parameter
Test conditions
Unit
mA
Min.
Max.
15.0
12.0
9.0
5.0
3.6
3.8
2.0
1.2
7.0
6.0
5.0
3.3
3.0
2.4
2.0
200
70
Power source High-speed
current
VCC = 5.0 V f(XIN) = 16.8 MHz
f(XIN) = 12.5 MHz
mode
f(XIN) = 8.4 MHz
f(XIN) = 4.2 MHz
f(XIN) = 16.8 MHz (in WIT state)
VCC = 3.0 V f(XIN) = 8.4 MHz
f(XIN) = 4.2 MHz
mA
mA
f(XIN) = 2.1 MHz
Middle-speed
mode
VCC = 5.0 V f(XIN) = 16.8 MHz
f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
f(XIN) = 16.8 MHz (in WIT state)
VCC = 3.0 V f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
mA
f(XIN) = 6.3 MHz
Low-speed
mode
VCC = 5.0 V f(XIN) = stopped
In WIT state
µA
µA
µA
µA
µA
40
VCC = 3.0 V f(XIN) = stopped
In WIT state
15
40
8
15
VCC = 2.0 V f(XIN) = stopped
In WIT state
6
15
3
6
In STP state
(All oscillation stopped)
Ta = 25 °C
0.1
1.0
10
Ta = 85 °C
Increment when A/D
conversion is executed
f(XIN) = 16.8 MHz, VCC = 5.0 V
In Middle-, high-speed mode
500
Rev.1.10 Nov 14, 2005 Page 74 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
A/D converter characteristics
Table 15 A/D converter recommended operating conditions
(VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VCC
Parameter
Conditions
Unit
V
Min.
2.0
2.2
2.0
Typ.
5.0
Max.
5.5
8-bit A/D mode(1)
10-bit A/D mode(2)
Power source voltage
(When A/D converter is used)
5.0
5.5
VREF
AVSS
VIA
Analog convert reference voltage
Analog power source voltage
Analog input voltage AN0-AN15
VCC
V
V
0
0
VCC
V
f(XIN)
Main clock input oscillation
frequency
(When A/D converter is used)
2.0 ≤ VCC < 2.2 V
2.2 ≤ VCC < 2.7 V
2.7 ≤ VCC < 4.0 V
4.0 ≤ VCC < 4.5 V
4.5 ≤ VCC ≤ 5.5 V
0.5
MHz
(20 × VCC – 36) × 1.05
-----------------------------------------------------------
2
0.5
0.5
0.5
0.5
(24 × VCC – 40.8) × 1.05
----------------------------------------------------------------
3
(9 × VCC – 0.3) × 1.05
---------------------------------------------------------
3
(24.6 × VCC – 62.7) × 1.05
---------------------------------------------------------------------
3
16.8
NOTES:
1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”.
2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”.
Table 16 A/D converter characteristics
(VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
8-bit A/D mode(1)
Unit
bit
Min.
Max.
8
−
Resolution
10-bit A/D mode(2)
8-bit A/D mode(1)
10
−
Absolute accuracy
(excluding quantization error)
2.0 ≤ VREF < 2.2 V
2.2 ≤ VREF ≤ 5.5 V
2.2 ≤ VREF < 2.7 V
2.7 ≤ VREF ≤ 5.5 V
±3
LSB
LSB
±2
10-bit A/D mode(2)
±5
±4
8-bit A/D mode(1)
10-bit A/D mode(2)
tCONV
Conversion time
Ladder resistor
50
2tc(XIN)
61
RLADDER
12
50
35
100
200
5.0
5.0
kΩ
µA
µA
µA
IVREF
Reference power
source input current
at A/D converter operated VREF = 5.0 V
150
at A/D converter stopped VREF = 5.0 V
II(AD)
A/D port input current
NOTES:
1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”.
2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”.
D/A converter characteristics
Table 17 D/A converter characteristics
(VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
3.5
Max.
8
−
−
Resolution
bit
%
Absolute accuracy
4.0 ≤ VREF ≤ 5.5 V
2.7 ≤ VREF < 4.0 V
1.0
2.5
3
tsu
Setting time
µs
kΩ
mA
RO
Output resistor
2
5
Reference power source input current(1)
IVREF
3.2
NOTES:
1. Using one D/A converter, with the value in the DA conversion register of the other D/A converter being “0016”.
Rev.1.10 Nov 14, 2005 Page 75 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Timing requirements and switching characteristics
Table 18 Timing requirements (1)
(VCC = 2.0 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Reset input “L” pulse width
Unit
Min.
Typ.
Max.
tW(RESET)
tC(XIN)
16
XIN cycle
ns
Main clock XIN
input cycle time
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
59.5
10000/(86 VCC − 219)
26 × 103/(82 VCC - 3)
10000/(84 VCC − 143)
10000/(105 VCC − 189)
tWH(XIN)
Main clock XIN
input “H” pulse width
25
ns
ns
4000/(86 VCC − 219)
10000/(82 VCC − 3)
4000/(84 VCC − 143)
4000/(105 VCC − 189)
tWL(XIN)
Main clock XIN
input “L” pulse width
25
4000/(86 VCC − 219)
10000/(82 VCC − 3)
4000/(84 VCC − 143)
4000/(105 VCC − 189)
tC(XCIN)
Sub-clock XCIN input cycle time
20
5
µs
µs
µs
ns
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
Sub-clock XCIN input “H” pulse width
Sub-clock XCIN input “L” pulse width
5
CNTR0−CNTR2
input cycle time
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
120
160
250
500
1000
48
tWH(CNTR)
tWL(CNTR)
tWH(INT)
CNTR0−CNTR2
input “H” pulse width
ns
ns
ns
ns
64
115
230
460
48
CNTR0−CNTR2
input “L” pulse width
64
115
230
460
48
INT00, INT01, INT1, INT2,
INT3, INT40, INT41
input “H” pulse width
64
115
230
460
48
tWL(INT)
INT00, INT01, INT1, INT2,
INT3, INT40, INT41
input “L” pulse width
64
115
230
460
Rev.1.10 Nov 14, 2005 Page 76 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Table 19 Timing requirements (2)
(VCC = 2.0 to 5.5 V, VSS = 0V, Ta = −20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol Parameter
Min.
250
320
500
1000
2000
120
150
240
480
950
120
150
240
480
950
70
Typ.
Max.
tC(SCLK1)
tC(SCLK3)
Serial I/O1, serial I/O3
clock input cycle time(1)
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWH(SCLK1)
tWH(SCLK3)
Serial I/O1, serial I/O3
clock input “H” pulse width(1)
tWL(SCLK1)
tWL(SCLK3)
Serial I/O1, serial I/O3
clock input “L” pulse width(1)
tsu(RxD1-SCLK1)
tsu(RxD3-SCLK3)
Serial I/O1, serial I/O3
clock input setup time
90
100
200
400
32
th(SCLK1-RxD1)
th(SCLK3-RxD3)
Serial I/O1, serial I/O3
clock input hold time
40
50
100
200
500
650
1000
2000
4000
200
260
400
950
2000
200
260
400
950
2000
100
130
200
400
800
100
130
150
300
600
tC(SCLK2)
Serial I/O2
clock input cycle time
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
NOTES:
Serial I/O2
clock input “H” pulse width
Serial I/O2
clock input “L” pulse width
Serial I/O2
clock input setup time
Serial I/O2
clock input hold time
1. When bit 6 of address 001A16 and bit 6 of address 003216 are “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are “0” (UART).
Rev.1.10 Nov 14, 2005 Page 77 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Table 20 Switching characteristics (1)
(VCC = 2.0 to 5.5 V, VSS = 0V, Ta = −20 to 85 °C, unless otherwise noted)
Limits
Test
conditions
Symbol
Parameter
Serial I/O1, serial I/O3
Unit
Min.
Typ.
Max.
tWH(SCLK1)
tWH(SCLK3)
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
tC(SCLK1)/2-30, tC(SCLK3)/2-30
tC(SCLK1)/2-35, tC(SCLK3)/2-35
tC(SCLK1)/2-40, tC(SCLK3)/2-40
tC(SCLK1)/2-45, tC(SCLK3)/2-45
tC(SCLK1)/2-50, tC(SCLK3)/2-50
tC(SCLK1)/2-30, tC(SCLK3)/2-30
tC(SCLK1)/2-35, tC(SCLK3)/2-35
tC(SCLK1)/2-40, tC(SCLK3)/2-40
tC(SCLK1)/2-45, tC(SCLK3)/2-45
tC(SCLK1)/2-50, tC(SCLK3)/2-50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clock output “H” pulse
width
tWL(SCLK1)
tWL(SCLK3)
Serial I/O1, serial I/O3
clock output “L” pulse
width
td(SCLK1-TxD1) Serial I/O1, serial I/O3
td(SCLK3-TxD3)
140
200
350
400
420
output delay time(1)
tV(SCLK1-TxD1) Serial I/O1, serial I/O3
tV(SCLK3-TxD3)
−30
−30
−30
−30
−30
output valid time(1)
tr(SCLK1)
tr(SCLK3)
Serial I/O1, serial I/O3
rise time of clock
output
30
35
40
45
50
30
35
40
45
50
Fig.64
tf(SCLK1)
tf(SCLK3)
Serial I/O1, serial I/O3
fall time of clock output
tWH(SCLK2)
Serial I/O2
clock output “H” pulse
width
tC(SCLK2)/2-160
tC(SCLK2)/2-200
tC(SCLK2)/2-240
tC(SCLK2)/2-260
tC(SCLK2)/2-280
tC(SCLK2)/2-160
tC(SCLK2)/2-200
tC(SCLK2)/2-240
tC(SCLK2)/2-260
tC(SCLK2)/2-280
tWL(SCLK2)
Serial I/O2
clock output “L” pulse
width
td(SCLK2-SOUT2) Serial I/O2
output delay time
200
250
300
350
400
t
V
(SCLK2-SOUT2
)
Serial I/O2
output valid time
0
0
0
0
0
NOTES:
1. When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
Rev.1.10 Nov 14, 2005 Page 78 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Table 21 Switching characteristics (2)
(VCC = 2.0 to 5.5 V, VSS = 0V, Ta = −20 to 85 °C, unless otherwise noted)
Limits
Test
conditions
Symbol
Parameter
Unit
Min.
Typ.
Max.
30
35
40
45
50
30
35
40
45
50
30
35
40
45
50
tf(SCLK2)
Serial I/O2
fall time of clock output
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
4.5 ≤ VCC ≤ 5.5 V
4.0 ≤ VCC < 4.5 V
2.7 ≤ VCC < 4.0 V
2.2 ≤ VCC < 2.7 V
2.0 ≤ VCC < 2.2 V
ns
ns
ns
tr(CMOS)
tf(CMOS)
NOTES:
CMOS
rise time of output(1)
10
12
15
17
20
10
12
15
17
20
Fig.64
CMOS
fall time of output(1)
1. When the P35/TXD3 P4-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”.
Rev.1.10 Nov 14, 2005 Page 79 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Measurement output pin
1kΩ
Measurement output pin
100pF
100pF
CMOS output
N-channel open-drain output
Fig 64. Circuit for measuring output switching characteristics (1)
Fig 65. Circuit for measuring output switching characteristics (2)
Rev.1.10 Nov 14, 2005 Page 80 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Single-chip mode timing diagram
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0, CNTR1
CNTR2
0.8VCC
0.2VCC
0.2VCC
INT1, INT2, INT3
INT00, INT40
tWH(INT)
tWL(INT)
0.8VCC
INT01, INT41
tW(RESET)
0.8VCC
RESET
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(XCIN)
tWL(XCIN)
tWH(XCIN)
0.8VCC
XCIN
0.2VCC
tC(SCLK1), tC(SCLK2), tC(SCLK3)
tWL(SCLK1), tWL(SCLK2), tWL(SCLK3)
tWH(SCLK1), tWH(SCLK2), tWH(SCLK3)
tf
tr
SCLK1
SCLK2
SCLK3
0.8VCC
0.2VCC
tsu(RXD1-SCLK1),
tsu(SIN2-SCLK2),
tsu(RXD3-SCLK3)
th(SCLK1-RXD1),
th(SCLK2-SIN2),
th(SCLK3-RXD3)
RXD1
RXD3
SIN2
0.8VCC
0.2VCC
tv(SCLK1-TXD1),
tv(SCLK2-SOUT2),
tv(SCLK3-TXD3)
td(SCLK1-TXD1), td(SCLK2-SOUT2), td(SCLK3-TXD3)
TXD1
TXD3
SOUT2
Fig 66. Timing diagram (in single-chip mode)
Rev.1.10 Nov 14, 2005 Page 81 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
PACKAGE OUTLINE
JEITA Package Code
RENESAS Code
PRDP0064BA-A
Previous Code
64P4B
MASS[Typ.]
7.9g
P-SDIP64-17x56.4-1.78
64
33
NOTE)
1
32
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*2
D
Dimension in Millimeters
Reference
Symbol
Min Nom Max
e1
D
18.75 19.05 19.35
56.2 56.4 56.6
SEATING PLANE
*3
*3
bp
b3
b2
e
E
17.0
16.85
17.15
5.08
A
A1
A2
bp
b2
b3
c
0.38
3.8
0.4 0.5 0.6
0.65 0.75 1.05
0.9 1.0 1.3
0.2 0.25 0.32
0°
15°
e
L
1.528 1.778 2.028
2.8
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
D
*1
48
33
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
49
32
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
10.0 10.1
10.0 10.1
1.4
9.9
9.9
64
17
Terminal cross section
A2
HD
HE
A
11.8 12.0 12.2
11.8 12.0 12.2
1.7
1
16
Index mark
ZD
A1
bp
b1
c
0.05
0.15
0.1
0.15 0.20 0.25
0.18
F
0.09
0.20
c
0.145
0.125
c1
0°
8°
y
e
0.5
*3
L
bp
e
x
0.08
0.08
x
L1
y
Detail F
ZD
ZE
L
1.25
1.25
0.5
0.35
0.65
L1
1.0
Rev.1.10 Nov 14, 2005 Page 82 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
JEITA Package Code
P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
64P6U-A
MASS[Typ.]
0.7g
HD
*1
D
33
48
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
49
32
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
Terminal cross section
D
E
13.9 14.0 14.1
13.9 14.0 14.1
1.4
A2
HD
HE
A
15.8 16.0 16.2
15.8 16.0 16.2
1.7
64
17
A1
bp
b1
c
0.1 0.2
0
1
16
ZD
0.32 0.37 0.42
0.35
Index mark
c
F
0.145
0.125
0.09
0.20
c1
L
L1
0°
8°
e
x
0.8
y
Detail F
0.20
0.10
*3
e
bp
y
x
ZD
ZE
L
1.0
1.0
0.3 0.5 0.7
1.0
L1
Rev.1.10 Nov 14, 2005 Page 83 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
APPENDIX
NOTES ON PROGRAMMING
1. Processor Status Register
Set D flag to “1”
ADC or SBC instruction
NOP instruction
(1) Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because
they have an important effect on calculations.
<Reason>
After a reset, the contents of the processor status register (PS) are
undefined except for the I flag which is “1”.
SEC, CLC, or CLD instruction
Reset
Fig 3. Execution of decimal calculations
Initializing of flags
4. JMP instruction
When using the JMP instruction in indirect addressing mode, do
not specify the last address on a page as an indirect address.
Main program
5. Multiplication and Division Instructions
Fig 1. Initialization of processor status register
• The index X mode (T) and the decimal mode (D) flags do not
affect the MUL and DIV instruction.
• The execution of these instructions does not change the
contents of the processor status register.
(2) How to reference the processor status register
To reference the contents of the processor status register (PS),
execute the PHP instruction once then read the contents of (S+1).
If necessary, execute the PLP instruction to return the PS to its
original status.
6. Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The instruction with the addressing mode which uses the value
of a direction register as an index
(S)
Stored PS
(S) + 1
• The bit-test instruction (BBC or BBS, etc.) to a direction
register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.)
to a direction register.
Fig 2. Stack memory contents after PHP instruction
execution
Use instructions such as LDM and STA, etc., to set the port
direction registers.
2. BRK instruction
(1) Interrupt priority level
7. Instruction Execution Timing
When the BRK instruction is executed with the following
conditions satisfied, the interrupt execution is started from the
address of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
The instruction execution time can be obtained by multiplying
the frequency of the internal clock φ by the number of cycles
mentioned in the 740 Family Software Manual.
The frequency of the internal clock φ is the twice the XIN cycle in
high-speed mode, 8 times the XIN cycle in middle-speed mode,
and the twice the XCIN in low-speed mode.
3. Decimal calculations
(1) Execution of decimal calculations
The ADC and SBC are the only instructions which will yield
proper decimal notation, set the decimal mode flag (D) to “1”
with the SED instruction. After executing the ADC or SBC
instruction, execute another instruction before executing the
SEC, CLC, or CLD instruction.
8. Reserved Area, Reserved Bit
Do not write any data to the reserved area in the SFR area and the
special page. (Do not change the contents after reset.)
9. CPU Mode Register
(2) Notes on status flag in decimal mode
Be sure to fix bit 3 of the CPU mode register (address 003B16) to
“1”.
When decimal mode is selected, the values of three of the flags in
the status register (the N, V, and Z flags) are invalid after a ADC
or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the
calculation, or is cleared to “0” if a borrow is generated. To
determine whether a calculation has generated a carry, the C flag
must be initialized to “0” before each calculation. To check for a
borrow, the C flag must be initialized to “1” before each calculation.
Rev.1.10 Nov 14, 2005 Page 84 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
NOTES ON PERIPHERAL FUNCTIONS
Notes on Input and Output Ports
Termination of Unused Pins
1. Terminate unused pins
1. Notes in standby state
(1) Output ports : Open
In standby state*1 for low-power dissipation, do not make input
levels of an I/O port “undefined”. Even when an I/O port of
Nchannel open-drain is set as output mode, if output data is “1”,
the aforementioned notes are necessary.
Pull-up (connect the port to VCC) or pull-down (connect the port
to VSS) these ports through a resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current
values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing
out to external
(2) I/O ports :
• Set the I/O ports for the input mode and connect them to VCC
or VSS through each resistor of 1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can
also use this resistor. Set the I/O ports for the output mode and
open them at “L” or “H”.
• When opening them in the output mode, the input mode of the
initial status remains until the mode of the ports is switched
over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source
current may increase in the input mode. With regard to an
effects on the system, thoroughly perform system evaluation
on the user side.
• Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program
periodically to increase the reliability of program.
<Reason>
Exclusive input ports are always in a high-impedance state. An
output transistor becomes an OFF state when an I/O port is set as
input mode by the direction register, so that the port enter a
highimpedance state. At this time, the potential which is input to
the input buffer in a microcomputer is unstable in the state that
input levels are “undefined”. This may cause power source
current.
(3) The AVSS pin when not using the A/D converter :
• When not using the A/D converter, handle a power source pin
for the A/D converter, AVSS pin as follows:
Even when an I/O port of N-channel open-drain is set as output
mode by the direction register, if the contents of the port latch is
“1”, the same phenomenon as that of an input port will occur.
AVSS: Connect to the VSS pin.
2. Termination remarks
(1) I/O ports :
Do not open in the input mode.
<Reason>
NOTES:
1. Standby state : stop mode by executing STP instruction
wait mode by executing WIT instruction
• The power source current may increase depending on the
firststage circuit.
2. Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit
managing instruction*2, the value of the unspecified bit may be
changed.
• An effect due to noise may be easily produced as compared
with proper termination (2) in 1 and shown on the above.
<Reason>
(2) I/O ports :
The bit managing instructions are read-modify-write form
instructions for reading and writing data by a byte unit.
Accordingly, when these instructions are executed on a bit of the
port latch of an I/O port, the following is executed to all bits of
the port latch.
When setting for the input mode, do not connect to VCC or VSS
directly.
<Reason>
If the direction register setup changes for the output mode
because of a program runaway or noise, a short circuit may occur
between a port and VCC (or VSS).
• As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after
bit managing.
(3) I/O ports :
• As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after
bit managing.
When setting for the input mode, do not connect multiple ports in
a lump to VCC or VSS through a resistor.
<Reason>
If the direction register setup changes for the output mode
because of a program runaway or noise, a short circuit may occur
between ports.
Note the following:
• Even when a port which is set as an output port is changed for
an input port, its port latch holds the output data.
• As for a bit of which is set for an input port, its value may be
changed even when not specified with a bit managing
instruction in case where the pin state differs from its port latch
contents.
• At the termination of unused pins, perform wiring at the
shortest possible distance (20 mm or less) from micro-
computer pins.
NOTES:
2. Bit managing instructions : SEB, and CLB instructions
Rev.1.10 Nov 14, 2005 Page 85 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Notes on Interrupts
2. Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt
request bit of an interrupt request register immediately after this
bit is set to “0”, execute one or more instructions before
executing the BBC or BBS instruction.
1. Change of relevant register settings
When the setting of the following registers or bits is changed, the
interrupt request bit may be set to “1”. When not requiring the
interrupt occurrence synchronized with these setting, take the
following sequence.
• Interrupt edge selection register (address 003A16)
• Timer XY mode register (address 002316)
• Timer Z mode register (address 002A16)
Clear the interrupt request bit to “0” (no interrupt issued)
Set the above listed registers or bits as the following sequence.
NOP (one or more instructions)
Set the corresponding interrupt enable bit to “0” (disabled).
Execute the BBC or BBS instruction
Set the interrupt edge select bit (active edge switch bit)
or the interrupt (source) select bit to “1”.
Fig 5. Sequence of check of interrupt request bit
<Reason>
NOP (one or more instructions)
If the BBC or BBS instruction is executed immediately after an
interrupt request bit of an interrupt request register is cleared to
“0”, the value of the interrupt request bit before being cleared to
“0” is read.
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
Set the corresponding interrupt enable bit to “1” (enabled).
Fig 4. Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit may be set
to “1”.
• When setting external interrupt active edge
Concerned register:Interrupt edge selection register
(address 003A16)
Timer XY mode register (address 002316)
Timer Z mode register (address 002A16)
• When switching interrupt sources of an interrupt vector
address where two or more interrupt sources are allocated.
Concerned register: Interrupt source selection register (address
003916)
Rev.1.10 Nov 14, 2005 Page 86 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Notes on 8-bit Timer (timer 1, 2, X, Y)
5. Programmable one-shot generating mode
• If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
• When switching the count source by the timer 12, X and Y
count source selection bits, the value of timer count is altered
in unconsiderable amount owing to generating of thin pulses in
the count input signals.
• Set the double-function port of CNTR2 pin and port P47 to
output, and of INT1 pin and port P42 to input in this mode.
• This mode cannot be used in low-speed mode.
• If the value of the CNTR2 active edge switch bit is changed
during one-shot generating enabled or generating one-shot
pulse, then the output level from CNTR2 pin changes.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
6. All modes
• Set the double-function port of the CNTR0/CNTR1 pin and
port P54/P55 to output in the pulse output mode.
• Set the double-function port of CNTR0/CNTR1 pin and port
P54/P55 to input in the event counter mode and the pulse width
measurement mode.
• Timer Z write control
Which write control can be selected by the timer Z write control
bit (bit 3) of the timer Z mode register (address 002A16), writing
data to both the latch and the timer at the same time or writing
data only to the latch.
When the operation “writing data only to the latch” is selected,
the value is set to the timer latch by writing data to the address of
timer Z and the timer is updated at next underflow. After reset
release, the operation “writing data to both the latch and the timer
at the same time” is selected, and the value is set to both the latch
and the timer at the same time by writing data to the address of
timer Z.
Notes on 16-bit Timer (timer Z)
1. Pulse output mode
• Set the double-function port of the CNTR2 pin and port P47 to
output.
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
2. Pulse period measurement mode
• Set the double-function port of the CNTR2 pin and port P47 to
input.
• A read-out of timer value is impossible in this mode. The timer
can be written to only during timer stop (no measurement of
pulse period).
• Timer Z read control
A read-out of timer value is impossible in pulse period
measurement mode and pulse width measurement mode. In the
other modes, a read-out of timer value is possible regardless of
count operating or stopped.
• Since the timer latch in this mode is specialized for the read-
out of measured values, do not perform any write operation
during measurement.
• “FFFF16” is set to the timer when the timer underflows or
when the valid edge of measurement start/completion is
detected.
Consequently, the timer value at start of pulse period
measurement depends on the timer value just before
measurement start.
However, a read-out of timer latch value is impossible.
• Switch of interrupt active edge of CNTR2 and INT1
Each interrupt active edge depends on setting of the CNTR2
active edge switch bit and the INT1 active edge selection bit.
• Switch of count source
When switching the count source by the timer Z count source
selection bits, the value of timer count is altered in
inconsiderable amount owing to generating of thin pulses on the
count input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
3. Pulse width measurement mode
• Set the double-function port of the CNTR2 pin and port P47 to
input.
• A read-out of timer value is impossible in this mode. The timer
can be written to only during timer stop (no measurement of
pulse period).
• Since the timer latch in this mode is specialized for the read-
out of measured values, do not perform any write operation
during measurement.
• “FFFF16” is set to the timer when the timer underflows or
when the valid edge of measurement start/completion is
detected.
Consequently, the timer value at start of pulse width
measurement depends on the timer value just before
measurement start.
4. Programmable waveform generating mode
• Set the double-function port of the CNTR2 pin and port P47 to
output.
Rev.1.10 Nov 14, 2005 Page 87 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Notes on Serial Interface
3. SRDYi (i = 1, 3) output of reception side
When signals are output from the SRDYi pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDYi output enable
bit, and the transmit enable bit to “1” (transmit enabled).
1. Notes when selecting clock synchronous serial I/O
(1) Stop of transmission operation
As for serial I/Oi (i = 1, 3) that can be used as either a clock
synchronous or an asynchronous (UART) serial I/O, clear the
serial I/Oi enable bit and the transmit enable bit to “0” (serial
I/Oi and transmit disabled).
4. Setting serial I/Oi (i = 1, 3) control register again
<Reason>
Set the serial I/Oi control register again after the transmission
and the reception circuits are reset by clearing both the transmit
enable bit and the receive enable bit to “0.”
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/Oi enable bit is cleared to
“0” (serial I/Oi disabled), the internal transmission is running (in
this case, since pins TxDi, RxDi, SCLKi, and SRDYi function as
I/O ports, the transmission data is not output). When data is
written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/Oi
enable bit is set to “1” at this time, the data during internally
shifting is output to the TxDi pin and an operation failure occurs.
Clear both the transmit enable bit (TE) and
the receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of the serial I/Oi
control register
(2) Stop of receive operation
Can be set with the
LDM instruction at
the same time
As for serial I/Oi (i = 1, 3) that can be used as either a clock
synchronous or an asynchronous (UART) serial I/O, clear the
receive enable bit to “0” (receive disabled), or clear the serial
I/Oi enable bit to “0” (serial I/Oi disabled).
Set both the transmit enable bit (TE) and the
receive enable bit (RE), or one of them to “1”
Fig 6. Sequence of setting serial I/Oi (i = 1, 3) control
register again
(3) Stop of transmit/receive operation
As for serial I/Oi (i = 1, 3) that can be used as either a clock
synchronous or an asynchronous (UART) serial I/O, clear both
the transmit enable bit and receive enable bit to “0” (transmit and
receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception
cannot be stopped.)
5. Data transmission control with referring to transmit
shift register completion flag
After the transmit data is written to the transmit buffer register,
the transmit shift register completion flag changes from “1” to
“0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after writing
the data to the transmit buffer register, note the delay.
<Reason>
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception. If any one of transmission and
reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
6. Transmission control when external clock is selected
In this mode, the clock circuit of the transmission circuit also
operates for data reception. Accordingly, the transmission circuit
does not stop by clearing only the transmit enable bit to “0”
(transmit disabled). Also, the transmission circuit is not
initialized by clearing the serial I/Oi enable bit to “0” (serial I/Oi
disabled) (refer to (1) in 1.).
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the
SCLKi (i = 1, 3) input level. Also, write the transmit data to the
transmit buffer register at “H” of the SCLKi input level.
7. Transmit interrupt request when transmit enable bit
is set
2. Notes when selecting clock asynchronous serial I/O
When using the transmit interrupt, take the following sequence.
(1) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to
“0” (disabled).
(1) Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial I/Oi
enable bit (i = 1, 3) to “0”.
(2) Set the tranasmit enable bit to “1”.
(3) Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to
“0” after 1 or more instruction has executed.
(4) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to
“1” (enabled).
<Reason>
This is the same as (1) in 1.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
<Reason>
When the transmission enable bit is set to “1”, the transmit buffer
empty flag and transmit shift register shift completion flag are
also set to “1”.
Therefore, regardless of selecting which timing for the
generating of transmit interrupts, the interrupt request is
generated and the transmit interrupt request bit is set at this point.
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial I/Oi
enable bit (i = 1, 3) to “0”.
<Reason>
This is the same as (1) in 1.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
8. Writing to baud rate generator i (BRGi) (i = 1, 3)
Write data to the baud rate generator i (BRGi) (i = 1, 3) while the
transmission/reception operation is stopped.
Rev.1.10 Nov 14, 2005 Page 88 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Notes on PWM
Notes on Watchdog Timer
The PWM starts from “H” level after the PWM enable bit is set
to enable and “L” level is temporarily output from the PWM pin.
The length of this “L” level output is as follows:
• Make sure that the watchdog timer H does not underflow
while waiting Stop release, because the watchdog timer keeps
counting during that term.
• When the STP instruction disable bit has been set to “1”, it is
impossible to switch it to “0” by a program.
n + 1
2 • f(XIN)
(s) (Count source selection bit = “0”,
where n is the value set in the prescaler)
n + 1
f(XIN)
Notes on RESET Pin
(s) (Count source selection bit = “1”,
where n is the value set in the prescaler)
Connecting capacitor
In case where the RESET signal rise time is long, connect a
ceramic capacitor or others across the RESET pin and the VSS
pin.
Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a
capacitor as short as possible.
• Be sure to verify the operation of application products on the
user side.
<Reason>
Notes on A/D Converter
1. Analog input pin
Make the signal source impedance for analog input low, or equip
an analog input pin with an external capacitor of 0.01 µF to 1 µF.
Further, be sure to verify the operation of application products on
the user side.
<Reason>
An analog input pin includes the capacitor for analog voltage
comparison. Accordingly, when signals from signal source with
high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion
precision to be worse.
If the several nanosecond or several ten nanosecond impulse
noise enters the RESET pin, it may cause a microcomputer
failure.
Notes on Low-speed Operation Mode
1. Using sub-clock
2. A/D converter power source pin
The AVSS pin is A/D converter power source pins. Regardless of
using the A/D conversion function or not, connect it as following :
• AVSS : Connect to the VSS line
To use a sub-clock, fix bit 3 of the CPU mode register to “1” or
control the Rd (refer to Figure 7) resistance value to a certain
level to stabilize an oscillation. For resistance value of Rd,
consult the oscillator manufacturer.
<Reason>
If the AVSS pin is opened, the microcomputer may have a failure
because of noise or others.
3. Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of
the capacity will be lost if the clock frequency is too low. Thus,
make sure the following during an A/D conversion.
• f(XIN) is 500 kHz or more
XCIN
XCOUT
Rf
• Do not execute the STP instruction
Rd
4. Difference between at 8-bit reading in 10-bit A/D
mode and at 8-bit A/D mode
CCIN
CCOUT
At 8-bit reading in the 10-bit A/D mode, “–1/2 LSB” correction
is not performed to the A/D conversion result.
Fig 7. Ceramic resonator circuit
In the 8-bit A/D mode, the A/D conversion characteristics is the
same as 3802 group’s characteristics because “–1/2 LSB”
correction is performed.
<Reason>
When bit 3 of the CPU mode register is set to “0”, the sub-clock
oscillation may stop.
Notes on D/A Converter
2. Switch between middle/high-speed mode and low-
speed mode
1. VCC when using D/A converter
If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient
time is required for the sub clock to stabilize, especially
immediately after power on and at returning from stop mode.
When switching the mode between middle/high-speed and low-
speed, set the frequency on condition that f(XIN) > 3•f(XCIN).
The D/A converter accuracy when VCC is 4.0 V or less differs
from that of when VCC is 4.0 V or more. When using the D/A
converter, we recommend using a VCC of 4.0 V or more.
2. D/Ai conversion register when not using D/A con-
verter
When a D/A converter is not used, set all values of the D/Ai
conversion registers (i = 1, 2) to “0016”. The initial value after
reset is “0016”.
Quartz-Crystal Oscillator
When using the quartz-crystal oscillator of high frequency, such
as 16 MHz etc., it may be necessary to select a specific oscillator
with the specification demanded.
Rev.1.10 Nov 14, 2005 Page 89 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
Notes on Restarting Oscillation
Notes on Handling of Power Source Pins
• Restarting oscillation
In order to avoid a latch-up occurrence, connect a capacitor
suitable for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin), and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the
pins to be connected, a ceramic capacitor of 0.01 µF–0.1 µF is
recommended.
Usually, when the MCU stops the clock oscillation by STP
instruction and the STP instruction has been released by an
external interrupt source, the fixed values of Timer 1 and
Prescaler 12 (Timer 1 = “0116”, Prescaler 12 = “FF16”) are
automatically reloaded in order for the oscillation to stabilize.
The user can inhibit the automatic setting by writing “1” to bit 0
of MISRG (address 001016).
However, by setting this bit to “1”, the previous values, set just
before the STP instruction was executed, will remain in Timer 1
and Prescaler 12. Therefore, you will need to set an appropriate
value to each register, in accordance with the oscillation
stabilizing time, before executing the STP instruction.
<Reason>
Oscillation will restart when an external interrupt is received.
However, internal clock φ is supplied to the CPU only when
Timer 1 starts to underflow. This ensures time for the clock
oscillation using the ceramic resonators to be stabilized.
Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less
than the recommended operating conditions and design a system
not to cause errors to the system by this unstable operation.
Notes on Using Stop Mode
• Register setting
Electric Characteristic Differences Between Flash
Memory, Mask ROM and QzROM Version MCUs
Since values of the prescaler 12 and Timer 1 are automatically
reloaded when returning from the stop mode, set them again,
respectively. (When the oscillation stabilizing time set after STP
instruction released bit is “0”)
There are differences in the manufacturing processes and the
mask pattern among flash memory, mask ROM, and QzROM
version MCUs due to the differences of the ROM type. Even
when the ROM type is the same, when the memory size is
different, the manufacturing processes and the mask pattern
differ. For these reasons, the oscillation circuit constants and the
characteristics such as a characteristic value, operation margin,
noise immunity, and noise radiation within the limits of electrical
characteristics may differ.
• Clock restoration
After restoration from the stop mode to the normal mode by an
interrupt request, the contents of the CPU mode register previous
to the STP instruction execution are retained. Accordingly, if
both main clock and sub clock were oscillating before execution
of the STP instruction, the oscillation of both clocks is resumed
at restoration.
In the above case, when the main clock side is set as a system
clock, the oscillation stabilizing time for approximately 8,000
cycles of the XIN input is reserved at restoration from the stop
mode. At this time, note that the oscillation on the sub clock side
may not be stabilized even after the lapse of the oscillation
stabilizing time of the main clock side.
When manufacturing an application system, please perform
sufficient evaluations in each product. Especially, when
switching a product (example: change from the mask ROM
version to QzROM version), please perform sufficient
evaluations by the switching product in the stage before mass-
producing an application system.
Notes on Wait Mode
Product Shipped in Blank
• Clock restoration
As for the product shipped in blank, Renesas does not perform
the writing test to user ROM area after the assembly process
though the QzROM writing test is performed enough before the
assembly process. Therefore, a writing error of approx.0.1 %
may occur. Moreover, please note the contact of cables and
foreign bodies on a socket, etc. because a writing environment
may cause some writing errors.
If the wait mode is released by a reset when XCIN is set as the
system clock and XIN oscillation is stopped during execution of
the WIT instruction, XCIN oscillation stops, XIN oscillations
starts, and XIN is set as the system clock.
In the above case, the RESET pin should be held at “L” until the
oscillation is stabilized.
Rev.1.10 Nov 14, 2005 Page 90 of 91
REJ03B0166-0110
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
3803 Group (Spec.H QzROM version)
QzROM Version
Notes On ROM Code Protect
(QzROM product shipped after writing)
Connect the CNVSS/VPP pin the shortest possible to the GND
pattern which is supplied to the VSS pin of the microcomputer.
In addition connecting an approximately 5 kΩ resistor in series to
the GND could improve noise immunity. In this case as well as
the above mention, connect the pin the shortest possible to the
GND pattern which is supplied to the VSS pin of the
microcomputer.
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the mask option setup data in the
mask file which is submitted at ordering.
Renesas Technology corp. uses the mask option setup data at the
ROM code protect address (address FFDB16) when writing to the
QzROM. Consequently, the actual written value might differ
from the ordered value as the contents of the ROM code protect
address.
The ROM option setup data in the mask file is “0016” for protect
enabled, “FE16” (protect enabled to the protect area 1 only) or
“FF16” for protect disabled. Therefore, the contents of the ROM
code protect address of the QzROM product shipped after
writing are “0016”, “FE16” or “FF16”.
• Reason
The CNVSS/VPP pin is the power source input pin for the built-in
QzROM. When programming in the QzROM, the impedance of
the VPP pin is low to allow the electric current for writing to flow
into the built-in QzROM. Because of this, noise can enter easily.
If noise enters the VPP pin, abnormal instruction codes or data
are read from the QzROM, which may cause a program runaway.
Note that the mask file which has nothing at the ROM option
data or has the data other than “0016”, “FE16” and “FF16” can not
be accepted.
The shortest
(Note)
DATA REQUIRED FOR QzROM WRITING ORDERS
CNVSS/VPP
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
Approx. 5kΩ
2. Mark Specification Form*
3. ROM data...........Mask file
VSS
(Note)
The shortest
* For the QzROM writing confirmation form and the mark
specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
Note. Shows the microcomputer’s pin.
Fig 8. Wiring for the CNVSS/VPP
Notes On QzROM Writing Orders
When ordering the QzROM product shipped after writing,
submit the mask file (extension: .mask) which is made by the
mask file converter MM.
Be sure to set the ROM option (“MASK option” written in the
mask file converter) setup when making the mask file by using
the mask file converter MM.
Rev.1.10 Nov 14, 2005 Page 91 of 91
REJ03B0166-0110
REVISION HISTORY
3803 Group (Spec.H QzROM version) Data Sheet
Rev.
Date
Description
Summary
Page
−
1.00 Sep. 30, 2005
1.10 Nov. 14, 2005
First edition issued
20
Fig 14. Port block diagram (3) (18) Port P56 revised
61
Fig 54. Block diagram of Watchdog timer;
STP instruction disable bit → STP instruction function selection bit revised
QzROM version; approximately 1 k to 5 kΩ resistor → approximately 5 kΩ resistor
Fig 47. Wiring for the CNVSS/VPP added
69
Notes On QzROM Writing Orders; (extension: .mask) → (extension: .msk) revised
82-83
84-91
Package Outline revised
Appendix added
(1/1)
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