M38060E3-FP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38060E3-FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总71页 (文件大小：1462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no ces whatsoever have been
made to the contents of the document, and these changes do not cony alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business opof high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O ...................... 8-bit ✕ 1 (UART or Clock-synchronized)
A-D converter .................................................. 8-bit ✕ 8 channels
LCD drive control circuit
DESCRIPTION
•
•
•
The 3825 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
Bias ................................................................................... 1/2, 1/3
Duty ............................................................................ 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output......................................................................... 40
2 Clock generating circuits
The 3825 group has the LCD drive control circuit, an 8-channel A-
D converter, and a Serial I/O as additional functions.
The various microcomputers in the 3825 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
•
•
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage
For details on availability of microcomputers in the 3825 Group,
refer the section on group expansion.
In high-speed mode ................................................... 4.0 to 5.5 V
In middle-speed mode ............................................... 2.5 to 5.5 V
(M version: 2.2 to 5.5 V)
FEATURES
Basic machine-language instructions ....................................... 71
•
•
(Extended operating temperature version: 3.0 to 5.5 V)
In low-speed mode..................................................... 2.5 to 5.5 V
(M version: 2.2 to 5.5 V)
The minimum instruction execution time ............................ 0.5 µs
(at 8 MHz oscillation frequency)
Memory size
•
(Extended omperature version: 3.0 to 5.5 V)
Power dissipation
ROM .................................................................. 4 K to 60 K bytes
RAM ................................................................. 192 to 2048 bytes
•
•
In high-speed m............................................... 32 mW
(at 8 MHrequency, at 5 V power source voltage)
In low-sp..........................................................45 µW
(at lation frequency, at 3 V power source voltage)
Operature range ................................... – 20 to 85°C
tended operating temperature version: –40 to 85°C)
Programmable input/output ports ............................................. 43
•
Software pull-up/pull-down resistors (Ports P0–P8)
•
Interrupts .................................................. 17 sources, 16 vectors
•
(includes key input interrupt)
Timers ........................................................... 8-bit ✕ 3, 16-bit ✕✕2
•
ICATIONS
era, household appliances, consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
873 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
8
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
6
7
0
1
2
3
4
5
6
7
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
9
8
7
6
5
4
3
2
1
0
87
88
89
90
91
92
93
94
95
96
97
98
99
100
M38258MCMXXXFP
V
X
X
SS
V
CC
REF
AVSS
OUT
IN
V
P8
P8
RESET
P7
P7
P7
P7
0
/XCOUT
/XCIN
COM
COM
COM
COM
3
2
1
0
1
0
1
2
3
VL3
VL2
C
2
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Package type : 100P6S-A (100-pin plastic-molded QFP)
Fig. 1 Pin configuration of M38258MCMXXXFP
(The pin configuration of 100D0 is same as this.)
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
5
34
33
32
31
30
29
28
27
26
SEG12
SEG11
SEG10
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
4
5
6
7
0
1
2
3
4
5
6
7
/SEG38
/SEG39
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
9
8
7
6
5
4
3
2
1
0
M38258MCMXXXGP
M38258MCMXXXHP
V
X
X
SS
OUT
IN
V
CC
REF
AVSS
V
P8
P8
RESET
P7
P7
P7
P7
P7
P7
P7
0
/XCOUT
/XCIN
1
COM
COM
COM
COM
3
2
1
0
0
1
2
3
4
5
6
VL3
VL2
C
C
2
1
VL1
1
2 3 4 5 6 7 8 9 16 17 18 19 20 21 22 23 24 25
Package type : .................. 100P6Q-A (100-pin plastic-molded LQFP)
Package type ...................... 100PFB-A (100-pin plastic-molded TQFP)
Fig. 2 Pin configuration of M38258MCMXXXGP, M38258MCMXXXHP
2
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
p u e k a w n o - y e K
n o i t c R
1 T N I , 0 T N I
3 T N I , 2 T N I
T D A
φ
Fig. 3 Functional block diagram
3
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1. Pin description (1)
Function
Pin
Name
Function except a port function
•Apply voltage of power source to VCC, and 0 V to VSS. (For the limits of VCC, refer to “Recom-
mended operating conditions”.)
VCC, VSS
VREF
Power source
Analog reference
voltage
• Reference voltage input pin for A-D converter.
• GND input pin for A-D converter.
• Connect to VSS.
AVSS
Analog power
source
• Reset input pin for active “L”
RESET
XIN
Reset input
Clock input
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or a quartz-crystal oscillator betn the XIN and XOUT pins to set
the oscillation frequency.
• If an external clock is used, connect the clock source to nd leave the XOUT pin open.
• This clock is used as the oscillating source of system
XOUT
Clock output
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage
• Input 0 – VL3 voltage to LCD
VL1 – VL3
LCD power source
• External capacitor pins for a voltage muls) of LCD contorl.
C1, C2
Charge-pump
capacitor pin
• LCD common output pins
• COM2 and COM3 are not used ratio.
• COM3 is not used at 1/3 dut
COM
0
– COM
3
Common output
• LCD segment output p
SEG0 – SEG17 Segment output
• 8-bit output port
• CMOS 3-state ure
• Pull-down coled.
• Port outpunabled.
P00/SEG26
P07/SEG33
–
Output port P0
• LCD segment pins
• 6-bit
P10/SEG34
P15/SEG39
–
Output port P1
I/O port P1
• CMoutput structure
• ntrol is enabled.
t control is enabled.
/O port
OS compatible input level
P16, P17
MOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit Input port
P20 – P27
I/O port P2
• Key input (key-on wake up) interrupt
• CMOS compatible input level
input pins
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
• 8-bit output port
• CMOS 3-state output structure
• Pull-down control is enabled.
• Port output control is enabled.
P30/SEG18
P37/SEG25
–
Output port P3
• LCD segment pins
4
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2. Pin description (2)
Pin
Name
Function
Function except a port function
• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
P40/f(XIN)/
f(XIN)/2,
P41/f(XIN)/5/
f(XIN)/10
I/O port P4
• Clock output pins
P42/INT0,
P43/INT1
• Interrupt input pins
• Serial I/O function pins
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY
• 8-bit I/O port
P50/INT2,
P51/INT3
I/O port P5
• Interrupt input pins
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
e port function pins
P52/RTP0,
P53/RTP1
mers X, Y functions pins
P54/CNTR0,
P55/CNTR1
P56/TOUT
P57/ADT
• Timer 2 output pin
• A-D trigger input pin
• A-D conversion input pins
P60/AN0–
I/O port P6
• 8-bit I/O port
P67/AN7
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows eindividually
programmed as either inpu
• Pull-up control is enable
• 1-bit input port
• CMOS compatibl
P70
Input port P7
I/O port P7
• 7-bit I/O port
• CMOS cot level
• CMOS t structure
P71–P77
• I/O dter allows each pin to be individually programmed as either input or output.
• Puis enabled.
P80/XCOUT,
P81/XCIN
I/O port P8
ort
•Sub-clock generating circuit I/O pins
(Connect a resonator. External clock
cannot be used.)
ompatible input level
S 3-state output structure
direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
5
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M3825 8 M C M XXX HP
Package type
FP: 100P6S-A package
HP: 100PFB-A package
GP: 100P6Q-A package
FS: 100D0 package
ROM number
Omitted in One Time PROM version shipped in
blank and EPROM version.
Normally, using hyphen
When electrical charactervision of quality
identification code usinmeric character
– : Standard
D : Extended operperature version
M : M version
ROM/PRO
1
2
3
8
: 4096
: 81
: es
bytes
0 bytes
576 bytes
28672 bytes
: 32768 bytes
9 : 36864 bytes
A: 40960 bytes
B: 45056 bytes
C: 49152 bytes
D: 53248 bytes
E: 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
: Mask ROM version
: EPROM or One Time PROM version
M
E
RAM size
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
0
1
2
3
4
5
6
7
8
9
Fig. 4 Part numbering
6
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (STANDARD, ONE TIME
PROM VERSION, EPROM VERSION)
Mitsubishi plans to expand the 3825 group(Standard, One Time
PROM version, EPROM version) as follows.
Packages
100PFB-A ................................ 0.4 mm-pitch plastic molded TQFP
100P6Q-A ................................ 0.5 mm-pitch plastic molded LQFP
100P6S-A ................................ 0.65 mm-pitch plastic molded QFP
100D0 ................... 0.65 mm-pitch ceramic LCC (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions.
Memory Size
ROM size ............................................................ 16 K to 60 Kbytes
RAM size ............................................................ 640 to 2048 bytes
Memory Expansion Plan
ROM size (bytes)
roduct
M38259EF
60K
56K
52K
48K
44K
40K
36K
Mass product
M
32K
28K
24K
20K
16K
12K
8K
Mass product
Mass product
M38254M
M3
4K
256
512
640
768
1,024
1,536
2,048
RAM size (bytes)
Fig. 5 Memory expansion plan
7
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Currently products are listed below.
As of Dec. 2000
Table 3. List of products
ROM size (bytes)
ROM size for User in (
Product
RAM size (bytes)
Package
Remarks
)
M38254M4-XXXFP
M38254M4-XXXGP
M38254M6-XXXFP
M38254M6-XXXGP
M38257M8-XXXFP
M38257E8FP
100P6S-A Mask ROM version
16384
(16254)
640
640
100P6Q-A Mask ROM version
100P6S-A Mask ROM version
24576
(24446)
100P6Q-A Mask ROM version
100P6S-A Mask ROM version
100P6S-A One Time PROM version (blank)
100P6Q-A Mask ROM version
32768
(32638)
M38257M8-XXXGP
M38257E8GP
1024
2048
100P6Q-A One Time PROM version (blank)
M38257E8FS
100D0
EPROM version
100P6S-A
M38259EFFP
One Time PROersion (blank)
M38259EFHP
61440
(61310)
100PFB-A One Time Pion (blank)
100P6Q-A One Timsion (blank)
M38259EFGP
M38259EFFS
100D0
EPR
8
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Memory Size
(EXTENDED OPERATING TEMPERATURE VERSION)
Mitsubishi plans to expand the 3825 group (Extended operating
temperature version) as follows.
ROM size ............................................................ 16 K to 60 Kbytes
RAM size ............................................................ 640 to 2048 bytes
Packages
Memory Type
Support for mask ROM, one time PROM version.
100P6S-A ................................ 0.65 mm-pitch plastic molded QFP
Memory Expansion Plan
ROM size (bytes)
Mass product
M38259EFD
60K
56K
52K
48K
44K
40K
Mass product
M3
36K
Mass product
32K
28K
24K
20K
16K
12K
8K
M38257M8
Mass product
Mass product
M38254M6D
M38254M4D
4K
256
0
768
1,024
1,536
2,048
RAM size (bytes)
Fig. 6 Memory expansion pladed operating temperature version
Currently products are listed below.
Table 4. List of products for extended operating temperature version
As of Dec. 2000
ROM size (bytes)
ROM size for User in (
Product
RAM size (bytes)
640
Package
Remarks
)
16384
(16254)
24576
M38254M4DXXXFP
100P6S-A Mask ROM version
M38254M6DXXXFP
M38257M8DXXXFP
M38258MCDXXXFP
M38259EFDFP
640
100P6S-A Mask ROM version
100P6S-A Mask ROM version
100P6S-A Mask ROM version
(24446)
32768
(32638)
49152
1024
1536
2048
(49022)
61440
100P6S-A One Time PROM version (blank)
(61310)
9
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (M VERSION)
Packages
Mitsubishi plans to expand the 3825 group (M version) as follows.
100PFB-A ................................ 0.4 mm-pitch plastic molded TQFP
100P6Q-A ................................ 0.5 mm-pitch plastic molded LQFP
100P6S-A ................................ 0.65 mm-pitch plastic molded QFP
Memory Type
Support for mask ROM version.
Memory Size
ROM size ......................................................................... 48 Kbytes
RAM size ....................................................................... 1536 bytes
Memory Expansion Plan
ROM size (bytes)
60K
56K
52K
48K
44K
40K
36K
32K
28K
24K
20K
16K
12K
8K
Mass product
8MCM
4K
25
12
768
1,024
1,536
2,048
RAM size (bytes)
Fig. 7 Memory expansion plan for M version
Currently products are listed below.
As of Dec. 2000
Table 5. List of products for low power source version
ROM size (bytes)
Product
Remarks
RAM size (bytes)
Package
ROM size for User in (
)
Mask ROM version
Mask ROM version
Mask ROM version
M38258MCMXXXFP
100P6S-A
49152
1536
M38258MCMXXXHP
M38258MCMXXXGP
100PFB-A
100P6Q-A
(49022)
10
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3825 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 9.
Store registers other than those described in Figure 9 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Count
The program counit counter consisting of two 8-bit
registers PCH aused to indicate the address of the
next instructicuted.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b0
b0
b0
b0
b7
A
Accumulator
b7
Index register X
Index register Y
Y
b7
S
Stack pointer
b15
b7
PCH
PC
L
Program counter
b7
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 8 740 Family CPU register structure
11
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PCH)
(S) (S) – 1
Push return address
on stack
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
M (S) (PCL)
(S) (S) – 1
Push return address
on stack
Push contents of processor
tatus register on stack
M (S) (PS)
(S) (
I
Se
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
e RTI
S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
(PS)
M (S)
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
POP return
address
from stack
Note: Condeptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 9 Register push and pop at interrupt generation and subroutine call
Table 6 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
12
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT uction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set of an arithmetic operation or data
transfer is negthe BIT instruction is executed, bit 7 of
the memorerated on by the BIT instruction is stored
in the n
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
Table 7 Set and clear instructions of each bit of processoister
N flag
C flag
SEC
CLC
Z flag
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
–
–
Set instruction
LI
CLV
Clear instruction
13
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns
(Do not write “0
Port XC switc
0 : I/O op oscillating)
1 : Xlating function
Main T) stop bit
ivision ratio selection bit
N)/2 (high-speed mode)
(XIN)/8 (middle-speed mode)
nal system clock selection bit
0 : XIN–XOUT selected (middle-/high-speed mode)
1 : XCIN–XCOUT selected (low-speed mode)
Fig. 10 Structure of CPU mode register
14
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special Page
ROM
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
Address
XXXX16
SFR area
Zero page
416
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
192
256
LCD display RAM area
010016
XXXX16
084016
384
512
640
768
896
1024
1536
2048
Reserved area
Not used
ROM area
ROM size
(bytes)
Addre
YY
dress
ZZZZ16
YYYY16
ZZZZ16
Reserved ROM area
(128 bytes)
4096
8192
F0
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. 11 Memory map diagram
15
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003
16
03B16
003C16
003D16
003E16
003F16
Port P0 (P0)
Port P1 (P1)
Timer X (low) (TXL)
Timer X (high) (TXH)
Timer Y (low) (TYL)
Timer Y (high) (TYH)
Timer 1 (T1)
Port P1 output control register (P1C)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Timer 2 (T2)
Timer 3 (T3)
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
Clock output control register (TCON)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
A-ter (ADCON)
on register (AD)
PULL register A (PULLA)
PULL register B (PULLB)
Transmit/Receive buffer register(TB/RB)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIO1C
UART control register (UARTC
Baud rate generator (BRG
gment output enable register (SEG)
LCD mode register (LM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
Fig. 12 Memory map of special funer (SFR)
16
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
Direction Registers
b7
b0
PULL register A
(PULLA : address 001616
)
The 3825 group has 43 programmable I/O pins arranged in seven
I/O ports (ports P16, P17, P2, P4–P6, P71–P77, P80 and P81). The
I/O ports have direction registers which determine the input/output
direction of each individual pin. (Ports P16 and P17 are shared
with bits 6 and 7 of the port P1 output control register). Each bit in
a direction register corresponds to one pin, and each pin can be
set to be input port or output port.
P0, P1 –P1 , P3 pull-down
0
5
(shared with P0 and P3 output
control : refer to the text)
P16
P20
P80
P40
P44
–P1
–P2
, P8
–P4
–P4
7
7
1
3
7
pull-up
pull-up
pull-up
pull-up
pull-up
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
Not used (return “0” when read)
b7
b0
PULL register B
(PULLB : address 001716
)
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
P50
P54
P60
64
74
–P5
–P5
–P6
–P6
P7
–P7
3
7
3
7
3
7
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
Port P1 Output Control Register
Bit 0 of the port P1 output control register (address 000316) en-
ables control of the output of ports P10 to P15.
When the bit is set to “1”, the port output function is valid.
In this case, setting of the PULL register A to ports P10 to P15 is
invalid.
Not used (return “0” when read)
0 : Disable
1 : Enable
Nots of PULL register A and PULL register B
ect ports programmed as the output port.
When resetting, bit 0 of the port P1 output control register is set to
“0” (the port output function is invalid.)
ucture of PULL register A and PULL register B
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PUL
ister B (address 001716), ports P0 to P8 except P70 can
ther pull-down or pull-up (pins that are shared with
output pins for LCD are pull-down; all other pins with
a program.
However, the contents of PULL register A aister B do
not affect ports programmed as the outpcept for ports
P0 and P3).
Ports P0 and P3 share the port ouunction with bit 0 of
the PULL register A. When set trt output function is in-
valid (Pull-down is valid).
When set to “0”, the port output function is valid (Pull-down is in-
valid).
The PULL register A setting is invalid for pins set to segment out-
put with the segment output enable register.
17
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8. I/O ports functions
Related SFRs
Pin
Input/Output
Output
I/O Format
Non-Port Function
Name
Diagram No.
PULL register A
Segment output enable
register
P00/SEG26–
P07/SEG33
CMOS 3-state output
LCD segment output
(1)
Port P0
PULL register A
Segment output enable
register
Port P1 output
control register
P10/SEG34–
P15/SEG39
(1)
CMOS 3-state output
LCD segment output
Output
Port P1
CMOS compatible
input level
CMOS 3-state output
Input/output,
individual bits
(2)
(2)
(1)
PULL register A
P16 , P17
CMOS compatible
input level
CMOS 3-state output
PULL register A
Interrupt control register 2
Input/output,
individual bits
Key-on wake up
interrupt input
Port P2
Port P3
P20–P27
LL register A
ment output enable
gister
P30/SEG18–
P37/SEG25
Output
CMOS 3-state output
LCD segment out
Clock o
P40/f(XIN)/
f(XIN)/2,
P41/f(XIN)/5/
f(XIN)/10
Clock output control
register
PULL register A
(2)
PULL register A
Interrupt edge selection
register
CMOS compatible
input level
CMOS 3-state outp
P42/INT0,
P43/INT1
Input/output,
individual bits
terrupt input
Serial I/O function I/O
Port P4
(3)
(4)
(5)
(6)
PULL register A
P44/RXD
P54/TXD
P46/SCLK
P47/SRDY
Serial I/O control register
Serial I/O status register
UART control register
PULL register B
Interrupt edge selection
register
P50/INT2,
P51/INT3
External interrupt input
(2)
PULL register B
Timer X mode register
Real time port
function output
P52/RTP0,
P53/RTP1
(7)
(8)
PULL register B
Timer X mode register
MOS compatible
input level
CMOS 3-state output
Inpu
in
Timer X function I/O
Timer Y function input
Timer 2 output
P54/CNTR0
Port P5
PULL register B
Timer Y mode register
P55/CNTR1
P56/TOUT
(9)
(8)
PULL register B
Timer 123 mode register
PULL register B
A-D control register
P57/ADT
(9)
A-D trigger input
CMOS compatible
input level
CMOS 3-state output
Input/output,
individual bits
P60/AN0–
P67/AN7
PULL register B
A-D control register
Port P6
Port P7
Port P8
(10)
A-D conversion input
CMOS compatible
input level
P70
(11)
(12)
Input
CMOS compatible
input level
CMOS 3-state output
Input/output,
individual bits
PULL register B
P71–P77
CMOS compatible
input level
CMOS 3-state output
(13)
(14)
(15)
(16)
P80/XCOUT
P81/XCIN
Sub-clock
generating circuit
PULL register A
CPU mode register
Input/output,
individual bits
LCD mode register
Common
Segment
LCD common output
LCD segment output
COM0–COM3
SEG0–SEG17
Output
Output
Note 1: When using double-function ports as functional I/O pins, refer the method to the relevant sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
18
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P10–P15, P3
V
/VL3/VCC
SegmeLn2t/Port
LCD drive timing
Segment data
Interface logic
level shift circuit
Segment
Data bus
Port latch
V
L1/VSS
Port
Pull-down
Port/Segment
Port ON/OFF
(2) Ports P1
6
, P17, P2, P4
0–P4
3, P5
0, P5
1
(3) Port P4
4
Pull-up control
Pull-up control
Serial I/O enable bit
Reception enable bit
Direction
register
Dire
re
Data bus
Port latch
Data bus
Key-on wake up interrupt input
INT –INT interrupt input
Serial I/O input
0
3
Except P1 , P1 , P40, P41
6
7
(4) Port P4
5
(5) Port P46
Serial I/O synchronization clock
selection bit
Pull-up contro
Pull-up control
Serial I/O enable bit
P45/T
X
D P-channel output disable bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O enable bit
Transmission enable bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Serial I/O output
Serial I/O clock output
Serial I/O clock input
(6) Port P4
7
(7) Ports P52, P53
Pull-up control
Pull-up control
Serial I/O mode selection bit
Serial I/O enable bit
S
RDY output enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Real time control bit
Real time port data
Serial I/O ready output
Fig. 14 Port block diagram (1)
19
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Ports P55, P57
(8) Ports P54, P56
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
Pulse output mode
Timer output
CNTR1 interrupt input
A-D trigger interrupt input
CNTR0 interrupt input
P54 only
(10) Port P6
Pull-up control
(11) Port P70
Direction
register
Data bus
Port latch
ta bus
A-D conversion input
Analog input pin selection bit
(12) Ports P71–P77
(13) Port P80
Port Xc switch bit + Pull-up control
Port XC switch bit
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Oscillation circuit
Port P81
(14) Port P81
Port XC switch bit
Port Xc switch bit + Pull-up control
Port XC switch bit
Direction
register
(15) COM0–COM3
VL3
Port latch
Data bus
VL2
VL1
The gate input signal of each
transistor is controlled by the
LCD duty ratio and the bias
value.
Sub-clock generating circuit input
(16) SEG0–SEG17
VSS
VL2/VL3
The voltage applied to the sources of
P-channel and N-channel transistors
is the controlled voltage by the bias
value.
VL1/VSS
Fig. 15 Port block diagram (2)
20
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight inter-
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
nal, and one software.
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 9. Interrupt vector addresses and priority
Inter
Remarks
Vector Addresses (Note 1)
Interrupt Source
Reset (Note 2)
INT0
Priority
High
Low
Genitions
1
2
FFFD16
FFFC16
At res
Non-maskable
At either rising or
of INT0 input
tion of either rising or
g edge of INT1 input
t completion of serial I/O data
reception
External interrupt
FFFB16
FFF916
FFF716
FFFA16
FFF816
F
(active edge selectable)
External interrupt
INT1
3
4
(active edge selectable)
Serial I/O
reception
Valid when serial I/O is selected
At completion of serial I/O transmit
shift or when transmission buffer is
empty
Serial I/O
5
FFF516
16
Valid when serial I/O is selected
transmission
Timer X
Timer Y
Timer 2
Timer 3
6
7
8
9
FFF
6
FFF216
FFF016
FFEE16
FFEC16
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
External interrupt
CNTR0
10
FFEB16
FFEA16
(active edge selectable)
External interrupt
CNTR1
Timer 1
INT2
11
12
13
FFE916
FFE716
FFE516
FFE816
FFE616
FFE416
(active edge selectable)
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At falling of conjunction of input
level for port P2 (at input mode)
External interrupt
(active edge selectable)
External interrupt
INT3
14
15
FFE316
FFE116
FFE216
FFE016
(active edge selectable)
External interrupt
Key input
(Key-on wake up)
(valid when an “L” level is applied)
Valid when ADT interrupt is selected
External interrupt
At falling of ADT input
ADT
16
17
FFDF16
FFDD16
FFDE16
FFDC16
(Valid at falling)
Valid when A-D interrupt is
selected
A-D conversion
BRK instruction
At completion of A-D conversion
At BRK instruction execution
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
21
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
ꢀNotes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
ꢀSet the corresponding interrupt enable bit to “0” (disabled).
ꢀSet the interrupt edge select bit or the interrupt source select bit
to “1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
ꢀSet the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Timer Y mode register (address 2816)
ꢀSet the corresponding interrupt enable bit to “1” (enabled).
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 3416)
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Inte
BRK instruction
Reset
Fig. 16 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
0
1
2
3
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
Not used (return “0” when read)
dge active
g edge active
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request regi
)
(IREQ1 : address
INT
INT
0
1
intet
it bit
CNTR
CNTR
0
1
interrupt request bit
interrupt request bit
Sernterrupt request bit
mit interrupt request bit
Trrupt request bit
Timer 1 interrupt request bit
INT
2
interrupt request bit
interrupt request bit
INT
3
Timnterrupt request bit
Key input interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
CNTR
0
1
interrupt enable bit
interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
INT
INT
2
interrupt enable bit
interrupt enable bit
3
Timer Y interrupt enable bit
Key input interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 17 Structure of interrupt-related registers
22
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-on Wake Up)
“1” to “0”. An example of using a key input interrupt is shown in
Figure 18, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P20–P23.
A Key-on wake up interrupt request is generated by applying a
falling edge to any pin of port P2 that have been set to input mode.
In other words, it is generated when AND of input level goes from
Port PXx
“L” level output
PULL register A
Bit 2 = “1”
Port P2
7
Key input interrupt request
direction register = “1”
✕
✕
✕✕✕
Port P2
latch
7
6
5
P2
7
output
output
Port P2
direction register = “1”
6
✕
✕
✕✕✕
Port P2
latch
P2
6
Port P2
direction register =
5
✕
✕
✕✕✕
Port P2
latch
P2
P2
5
output
output
P
er = “1”
✕
✕
✕✕✕
Port P2
latch
4
Port P2
3
direction register = “0”
Port P2
Input reading circuit
✕
rt P2
atch
3
P2
3
input
input
input
input
Port P2
2
direction register = “0”
✕✕✕
Port P2
latch
2
P2
2
Port P2
1
direction register = “0”
✕
✕
✕✕✕
Port P2
latch
1
P2
P2
1
Port P2
0
direction register = “0”
✕
✕
✕✕✕
Port P2
latch
0
0
✕
✕
P-channel transistor for pull-up
✕✕✕ CMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P2 block diagram
23
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Read and write operation on 16-bit timer must be performed for
both high- and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct op-
eration when reading during the write operation, or when writing
during the read operation.
TIMERS
The 3825 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is contin-
ued. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1”.
Real time port
control bit “1”
Data bus
P52 data for real time port
Q D
P5
2
2
Latch
P5
direction register “0”
P52 latch
Real time port
control bit “1”
Q D
P53 data for real time port
P5
3
3
Latch
Real time port
P5
direction register “0”
control bit “0”
Timer X mode
write signal
P53 latch
“1”
f(XIN)/16
(f(XCIN)/16 in low-speed mode✽)
Timer X stop
control bit
Timer X write
control bit
Timer X operat-
ing mode bits
“00”,“01”,“11”
CNTR0 active
edge switch bit
Timer X (l
er X (high) latch (8)
Timer X
interrupt
request
“0”
P54/CNTR0
Ti
Timer X (high) (8)
“10”
“1”
Pulse width
CNTR
0
measurement
interrupt
request
mode
tput mode
CNTR
edge switch bit
0
active
“0”
“
Timer Y operating mode bits
“00”,“01”,“10”
CNTR
interrupt
request
1
P54 direction register
Pulse width HL continuously measurement mode
P54 l
“11”
Rising edge detection
Pulse ou
Period
measurement mode
Falling edge detection
6 in low-speed mode])
Timer Y stop
control bit
CN
Timer Y (low) latch (8)
Timer Y (high) latch (8)
Timer Y (high) (8)
“00”,“01”,“11”
Timer Y
interrupt
request
P55/CNTR1
Timer Y (low) (8)
“10” Timer Y operating
“1”
mode bits
f(XIN)/16
Timer 1
interrupt
request
(f(XCIN)/16 in low-speed mode])
Timer 1 count source
selection bit
“0”
Timer 2 count source
selection bit
Timer 2 write
control bit
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
“0”
Timer 2
interrupt
request
X
CIN
Timer 2 (8)
“1”
“1”
f(XIN)/16
(f(XCIN)/16 in low-speed mode )
]
T
OUT output
T
OUT output
control bit
active edge
switch bit “0”
S
Q
P56/TOUT
T
“1”
P5
OUT output control bit
f(XIN)/16(f(XCIN)/16 in low-speed mode])
6 latch
Q
P56 direction register
“0”
“1”
Timer 3 latch (8)
Timer 3 (8)
Timer 3
interrupt
request
T
Timer 3 count
✽Internal clock φ = XCIN/2.
source selection bit
Fig. 19 Timer block diagram
24
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
b7
b0
Timer X mode register
(TXM : address 002716
)
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
(2) Pulse output mode
P5
2
data for real time port
data for real time port
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the corresponding port P54 direction register to output mode.
P53
Timer X operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR0 active edge switch bit
0 : Counat rising edge in event counter mode
Sta“H” output in pulse output mode
” pulse width in pulse width measurement
(3) Event counter mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P54 direction register to input mode.
active for CNTR0 interrupt
alling edge in event counter mode
m “L” output in pulse output mode
ure “L” pulse width in pulse width measurement
de
Rising edge active for CNTR
mer X stop control bit
0 : Count start
0 interrupt
(4) Pulse width measurement mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the in-
put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the corresponding port P54 direction register to input
mode.
1 : Count stop
0 Structure of timer X mode register
●Timer X Write Control
If the timer X write control bit is “0”, when the value is
address of timer X, the value is loaded in the timetch
at the same time.
If the timer X write control bit is “1”, when thtten in the
address of timer X, the value is loaded och. The value
in the latch is loaded in timer X after rflows.
If the value is written in latch only, value may be set in
the high-order counter when the igh-order latch and the
underflow of timer X are performed e same timing.
●Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P52 and P53 each time the timer X
underflows. (However, if the real time port control bit is changed
from “0” to “1” after set of the real time port data, data are output
independent of the timer X operation.) If the data for the real time
port is changed while the real time port function is valid, the
changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
●Note on CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
25
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7
b0
Timer Y mode register
(TYM : address 002816
)
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
(2) Period measurement mode
0
0
1
1
0 : Timer mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period measure-
ment mode is the same as in timer mode.
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously
measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
asure the rising edge period in period
urement mode
dge active for CNTR
p control bit
nt start
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
1 interrupt
ount stop
(3) Event counter mode
Fig. 21 Stmer Y mode register
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
(4) Pulse width HL continuously measure-
ment mode
CNTR1 interrupt request is generated at both rising and
edges of CNTR1 pin input signal. Except for this, the op
pulse width HL continuously measurement mode is th
period measurement mode. When using a timer iset
the corresponding port P55 direction register to
●Note on CNTR1 interrupt actielection
CNTR1 interrupt active edge dependTR1 active edge
switch bit. However, in pulse widtously measurement
mode, CNTR1 interrupt requeted at both rising and
falling edges of CNTR1 pin input siegardless of the setting of
CNTR1 active edge switch bit.
26
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an inadvert-
ent count down of the timer. Therefore, rewrite the value of timer
whenever the count source is changed.
b7
b0
Timer 123 mode register
(T123M :address 002916
)
T
T
OUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
OUT output control bit
0 : TOUT output disabled
1 : TOUT output enabled
●Timer 2 Write Control
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
: Timer 1 output
XIN)/16
(XCIN)/16 in low-speed mode)
count source selection bit
f(XIN)/16
●Timer 2 Output Control
When the timer 2 (TOUT) is output enabled, an inversion signal
from pin TOUT is output each time timer 2 underflows.
In this case, set the port P56 shared with the port TOUT to the out-
put mode.
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN
)
Not used (return “0” when read)
clock φ is f(XCIN)/2 in the low-speed mode.
●Note on Timer 1 to Timer 3
When the count source of timers 1 to 3 is changed, the timer
counting value may be changed large because a thin pulse is gen-
erated in count input of timer. If timer 1 output is selected as the
count source of timer 2 or timer 3, when timer 1 is written,
counting value of timer 2 or timer 3 may be changed lar
cause a thin pulse is generated in timer 1 output.
Structure of timer 123 mode register
Therefore, set the value of timer in the order of tim
and timer 3 after the count source selection of tim
27
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB (address 001816).
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
Data bus
Serial I/O control register
Address 001A16
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P44/RXD
Shift clock
Clock control circuit
P46/SCLK
Serial I/O synchronization
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN
)
Baud rate generator
Address 001C16
1/
(f(XCIN) in low-speed mode)
1/4
Ct
P47/SRDY
Falling-edge detector
F/F
Shift clock
Transmit shift register shift completion flag (TSC)
nsmit interrupt source selection bit
Transmit shift reg
P45/TXD
Transmit interrupt request (TI)
Transmit buffe
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O status register
01816
Fig. 23 Block diagram of clock synchronO
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
D
0
0
D
1
1
D
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
Serial input RXD
D
D
D
D
D
D
D
D
2
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Notes
1 : The transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the T
XD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 24 Operation of clock synchronous serial I/O function
28
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
Address 001A16
Serial I/O control register
OE
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Character length selection bit
7 bits
P44/RXD
STdetector
Receive shift register
1/16
8 bits
trol register
SP detector
PE FE
dress 001B16
Clock control circuit
Serial I/O synchronization clock selection bit
P46/SCLK
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
f(XIN)
( f(XCIN) in low-speed
mode)
Baud rate generator
Address 001C16
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD
Transm
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
gister
ddress 001816
Address 001916
Serial I/O status register
Fig. 25 Block diagram of UART serial I/
Transmit or receive clock
Transmit buffer write signal
TBE=0
TBE=0
TSC=0
TSC=1●
SP
TBE=1
TBE=1
ST
ST
D
0
D1
Serial output T
X
D
D
0
D
1
SP
1 start bit
● Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
D
0
D
1
ST
D
0
D1
Serial input RXD
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
Notes
2 : The transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 26 Operation of UART serial I/O function
29
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is write-
only and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer regis-
ter is “0”.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the Serial I/O Control Register) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A
The serial I/O control register contains eight control bits
rial I/O function.
[UART Control Register (UARTCB16
The UART control register consists of four its 0 to 3)
which are valid when asynchronous sercted and set
the data format of an data transfer. Oregister (bit 4) is
always valid and sets the output se P45/TXD pin.
[Baud Rate Generator (B)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
ꢀNotes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
ꢀSet the serial I/O transmit interrupt enable bit to “0” (disabled).
ꢀSet the transmit enable bit to “1”.
ꢀSet the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
ꢀSet the serial I/O transmit interrupt enable bit to “1” (enabled).
30
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Serial I/O status register
(SIOSTS : address 001916
Serial I/O control register
(SIOCON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O synchronization clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronized serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronized serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin
pin operates as SRDY output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt whesmit buffer has emptied
1: Interrupt wmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transm)
0: Tr
1: ed
Framing error flag (FE)
0: No error
1: Framing error
ble bit (RE)
disabled
ive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
rial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
b7
b0
UART control register
(UARTCON : address 001B16
(pins P4
1: Serial I/O enabled
(pins P4 –P4 operate as serial I/O pins)
4–P47 operate as ordinary I/O pins)
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
4
7
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS
0: Even parity
1: Odd parity
Stop bit length sPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel utput disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Fig. 27 Structure of serial I/O control registers
31
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
Comparator and Control Circuit
The functional blocks of the A-D converter are described below.
The comparator and control circuit compare an analog input volt-
age with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500kHz during A-D conversion.
Use the clock divided from the main clock XIN as the internal clock
φ.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the A-
D conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to “1”, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
b7
b0
A-D control register
(ADCON : address 003416
)
Analog input pin selection bits
0 0 0 : P6
0 1 : P6
1 0 : P6
0 1 1 : P6
1 0 0 : P6
1 0 1 : P6
1 1 0 : P6
1 1 1 : P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
AVSS and VREF by 256, and outputs the divided voltages.
V
REF input switch bit
0 : OFF
1 : ON
Channel Selector
The channel selector selects one of the input ports P67/AN7–P60/
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
AN0.
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
Fig. 28 Structure of A-D control register
Data bus
b7
b0
A-D control register
P57/ADT
3
ADT/A-D interrupt request
A-D control circuit
P60
P61
P62
P63
P64
P65
P66
P67
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
A-D conversion
register
Comparator
8
Resistor ladder
AVSS
VREF
Fig. 29 A-D converter block diagram
32
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and dis-
plays the data on the LCD panel.
LCD DRIVE CONTROL CIRCUIT
The 3825 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
•
Segment output enable register
•
LCD mode register
•
Table 10. Maximum number of display pixels at each duty ratio
Voltage multiplier
•
Selector
•
Duty ratio
2
Maximum number of display pixel
80 dots
Timing controller
•
Common driver
•
or 8 segment LCD 10 digits
120 dots
Segment driver
•
3
4
Bias control circuit
•
or 8 segment LCD 15 digits
160 dots
A maximum of 40 segment output pins and 4 common output pins
can be used.
or 8 segment LCD 20 digits
Up to 160 pixels can be controlled for LCD display. When the LCD
b7
b0
Segment output enable r
(SEG : address 00381
Segment outpu
0 : Output
1 : SegG18–SEG23
Segmee bit 1
0 36, P37
utput SEG24,SEG25
ut enable bit 2
t ports P00–P05
ment output SEG26–SEG31
nt output enable bit 3
: Output ports P06,P07
1 : Segment output SEG32,SEG33
Segment output enable bit 4
0 : Output port P1
0
1 : Segment output SEG34
Segment output enable bit 5
0 : Output ports P11–P15
1 : Segment output SEG35–SEG39
Not used (return “0” when read)
(Do not write “1” to this bit)
b0
LCD mode register
(LM : address 003916
)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 duty (use COM
1 0 : 3 duty (use COM
1 1 : 4 duty (use COM
Bias control bit
0 : 1/3 bias
0
0
0
, COM
–COM
–COM
1)
2)
3)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltage multiplier disable
1 : Voltage multiplier enable
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
Fig. 30 Structure of segment output enable register and LCD mode register
33
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 31 Block diagram of LCD controller/driver
34
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 11. Bias control and applied voltage to VL1–VL3
Voltage Multiplier (3 Times)
The voltage multiplier performs threefold boosting. This circuit in-
puts a reference voltage for boosting from LCD power input pin
VL1. (However, when using a 1/2 bias, connect VL1 and VL2 and
apply voltage by external resistor division.)
Bias value
Voltage value
VL3=VLCD
1/3 bias
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
The voltage multiplier control bit (bit 4 of the LCD mode register)
controls the voltage multiplier.
1/2 bias
VL2=VL1=1/2 VLCD
When voltage is input to the VL1 pin during operating the voltage
multiplier, voltage that is twice as large as VL1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
VL3 pin.
Note : VLCD is the maximum value of supplied voltage for the
LCD panel.
When using the voltage multiplier; after applying 1.3 V ≤ Voltage ≤ 2.3 V
to the VL1 pin, set the voltage multiplier control bit to “1” to select the
voltage multiplier enable.
Table 12. Duty ratio control and common pins used
Duty
ratio
Duty ratio selection bits
Common pins used
Bit 1
0
Bit 0
1
When not using the voltage multiplier, apply proper voltage to the
LCD power input pins (VL1–VL3).
2
COM0, COM1 (Note 1)
OM0–COM2 (Note 2)
COM0–COM3
3
4
1
1
Bias Control and Applied Voltage to LCD
Power Input Pins
Notes 1: COM2 re open.
2: CO
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 11 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1
LCD mode register).
Contrast control
Contrast control
V
V
L3
L2
V
V
L3
L2
V
V
L3
L2
R1
R2
R4
C
2
1
C
C
2
Open
Open
Open
Open
C
2
1
C
1
C
V
L1
V
L1
V
L1
R3
R5
R4=R5
R1=R2=R3
1/3 bias
1/3 bias
when not using the voltage multiplier
1/2 bias
when using the voltage multiplier
Fig. 32 Example of circuit at each bias
35
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD Display RAM
LCD Drive Timing
Address 004016 to 005316 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the fol-
lowing equation;
(frequency of count source for LCDCK)
f(LCDCK)=
(divider division ratio for LCD)
f(LCDCK)
Frame frequency=
duty ratio
Bit
7
6
5
4
3
2
1
0
Address
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
SEG1
SEG3
SEG0
SEG2
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
SEG5
SEG4
SEG7
SEG6
SEG9
SE
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG
S
37
EG39
16
EG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG32
SEG34
SEG36
SEG38
Fig. 33 LCD display RAM map
36
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic
LCDCK timing
1/4 duty
Voltage level
V
V
V
L3
L2=VL1
SS
COM
0
1
2
3
COM
COM
COM
V
V
L3
SEG
0
SS
OFF
ON
ON
COM
3
COM
2
COM
1
COM
0
OM
2
COM
1
COM0
1/3 duty
V
V
V
L3
L2=VL1
SS
COM
COM
COM
0
1
2
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
0
COM
2
COM
1
COM
2
COM
1
COM
0
COM2
1/2 duty
V
V
V
L3
L2=VL1
SS
COM
COM
0
1
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
1
COM
0
COM
1
COM
1
COM
0
COM
1
COM0
Fig. 34 LCD drive waveform (1/2 bias)
37
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
V
VL2
VSL1S
COM
0
COM
COM
COM
1
2
3
V
V
L3
SEG
0
SS
OFF
ON
ON
COM
3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
VL3
VL2
VSL1S
V
COM
COM
COM
0
1
2
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
2
COM
1
COM
0
COM2
COM
2
COM
1
COM0
1/2 duty
VL3
VL2
VSL1S
V
COM
0
1
COM
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
1
COM
0
COM
1
COM
0
COM
1
COM0
COM
1
COM0
Fig. 35 LCD drive waveform (1/3 bias)
38
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK OUTPUT FUNCTION
Selection of Output Clock Frequency
Bit 2 (output clock frequency selection bit) of the clock output con-
trol register selects an output clock frequency.
Input/output ports P40 and P41 can output clock. The input/output
ports and clock output function are put under double function con-
trolled by the clock output control register (address 002A16).
When setting the output clock frequency selection bit to “0”, port
P40 becomes the frequency of f(XIN) and port P41 becomes the
frequency of f(XIN)/5.
Selection of Input/Output Ports and Clock
Output Function
At this time, the output pulse of port P40 depends on the XIN input
pulse, while the output pulse of port P41 has duty ratio of about
40%.
Bits 0 and 1 of the clock output control register can select between
the input/output ports and the clock output function.
When selecting the clock output function, clocks are output while
the direction register of ports P40 and P41 are set to output.
At the next cycle of rewriting the clock output control bit, P40 is
switched between the port output and the clock output.
In synchronization with the fall of the clock (resulting from dividing
XIN by 5) on rewriting the clock output control bit, P41 is switched
between the port output and the clock output.
When setting the output clock frequency selection bit to “1”, port
P40 becomes the frequency of f(XIN)/2 and port P41 becomes the
frequency of f(XIN)/10. At this time, the output pulses of both ports
P40 and P41 have duty ratio of 50%.
b7
b
tput control register
: address 002A16
)
P40 clock output control bit
0 : I/O port
1 : Clock output
P41
clock output control bit
0 : I/O port
1 : Clock output
Output clock frequency selection bit
0 : P4
1 : P4
0
←f(XIN), P4
1
←f(XIN)/5
0←f(XIN)/2, P4
1←f(XIN)/10
Not used (return “0” when read)
Fig. 36 Structure of clock output control register
P40 port latch
P4
control bit
0 clock output
“0”
“1”
“0”
X
IN
P40
“1”
Output clock
frequency
P40 direction register
1/2
selection bit
P41 port latch
P4
control bit
1 clock output
“0”
“0”
“1”
1/5
P41
“1”
Output clock
frequency
selection bit
P41 direction register
1/2
Fig. 37 Clock output function block diagram
39
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
Address Register contents
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD16 (high-order byte) and ad-
dress FFFC16 (low-order byte). Make sure that the reset input
voltage meets VIL spec. when a power source voltage passes
VCC(min.).
(1)
000016
000216
000316
000416
000516
000616
000816
000916
000A16
000B16
000C16
000D16
00E16
00F16
001016
001116
001616
001716
001916
001A16
001B16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
003416
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
Port P0
0016
0016
0016
0016
0016
0016
(2)
Port P1
(3)
Port P1 output control register
Port P2
(4)
(5)
Port P2 direction register
Port P3
(6)
(7)
Port P4
0016
0016
(8)
Port P4 direction register
Port P5
(9)
0016
0016
0016
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18
2)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
Port P5 direction register
Port P6
Power on
Power
source
Port P6 direction register
Port P7
0016
0016
voltage
RESET
VCC
0V
Reset input
voltage
Port P7 direction
Port P8
0016
0016
0016
V
IL spec.
0V
Port P8
PU
tatus register
I/O control register
ART control register
Timer X (low)
0116
0016
1
1
0
1
0 0
0
0 0
0 0
0
0
0016
RESET
VCC
1 0
0
FF16
FF16
FF16
FF16
FF16
0116
FF16
Power source voltage
detection circuit
Timer X (high)
Timer Y (low)
Timer Y (high)
Timer 1
Timer 2
Timer 3
0016
00
Timer X mode register
Timer Y mode register
Timer 123 mode register
Clock output control register
Fig. 38 Example of reset circuit
0016
0016
0016
A-D control register
0
0
0
0
1
0 0 1
0016
0
0
0
Segment output enable register
LCD mode register
0016
Interrupt edge selection register
0016
CPU mode register
0
0 0
1
0
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Processor status register
Program counter
0016
0016
0016
0016
● ●
● ● ● 1 ● ●
(PC
H)
Contents of address FFFD16
)
Contents of address FFFC16
(PC
L
Note: The contents of all other registers and RAM are undefined after
reset, so they must be initialized by software.
● : Undefined
Fig. 39 Internal state of microcomputer immediately after re-
set
40
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
IN
φ
RESET
Internal reset
Reset address from
vector table
Address
Data
?
?
?
?
DL
FFFC
FFFD
ADL
SYNC
Notes 1 : XIN and φ are in the r
N) = 8•f(φ)
2 : A question mark (?ndefined status that depends on the previous status.
X
IN : about 8000
clock cycles
Fig. 40 Reset sequence
41
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Oscillation Control
The 3825 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116”.
Either XIN or XCIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2.
The bits of the timer 123 mode register except bit 4 are cleared to
“0”. Set the timer 1 and timer 2 interrupt enable bits to disabled
(“0”) before executing the STP instruction.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accord-
ingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Oscillator restarts at reset or when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU until
timer 2 underflows. This allows time for the clock circuit oscillation
to stabilize.
Frequency Control
(2) Wait mode
(1) Middle-speed mode
If the WIT instruction the internal clock φ stops at an
“H” level. The stateXCIN are the same as the state be-
fore the executnstruction. The internal clock restarts
at reset or wrupt is received. Since the oscillator does
not stop, ration can be started immediately after the
clock
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2)High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
•
•
A low-power consumption operation can be realized by stoppin
the main clock XIN in this mode. To stop the main clock, set
of the CPU mode register to “1”.
X
CIN
X
COUT
XIN
X
OUT
When the main clock XIN is restarted, set enough tim
lation to stabilize by programming.
Rf
Rd
Note: If you switch the mode between middle/higlow-
speed, stabilize both XIN and XCIN osce suffi-
cient time is required for the sub-clize, espe-
cially immediately after power-on ing from stop
mode. When switching the en middle/high-
speed and low-speed, set cy in the condition
that f(XIN) > 3•f(XCIN).
C
OUT
C
CIN
C
COUT
CIN
Fig. 41 Ceramic resonator circuit
X
CIN
X
COUT
X
IN
XOUT
Rf
Open
Rd
External oscillation circuit
C
CIN
CCOUT
V
CC
V
SS
Fig. 42 External clock input circuit
42
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
COUT
X
CIN
“1”
“0”
Port X
C
switch bit
Timer 1 count
source selection
bit
Timer 2 count
source selection
bit
Internal system clock selection bit
(Note)
X
IN
X
OUT
Low-speed mode
“1”
“0”
“1”
Timer 1
Timer 2
1/4
1/2
1/2
“0”
“0”
“1”
Middle-/High-speed mode
Main clock dection bit
Middle-sp
“1”
Timing φ
(Internal clock)
“0”
High-speed mode
or Low-speed
Main clock stop bit
Q
Q
S
R
S
R
S
R
Q
ction
STP instruction
STP instruction
Res
Interrupt disable flag I
Interrupt requ
Note: When using the low-speed mode, set the port X
C
switch bit to “1”.
Fig. 43 Clock generating circuit block diagram
43
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
CM
6
Middle-speed mode (f(φ) = 1 MHz)
High-speed mode (f(φ) = 4 MHz)
“1”
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selected)
= 1 (Middle-speed)
= 0 (8 MHz oscillating)
= 0 (32 kHz stopped)
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selected)
= 0 (High-speed)
= 0 (8 MHz oscillating)
= 0 (32 kHz stopped)
“0”
”
0
“
M4
”
C
0
“
”
M6
1
“
C
”
1
“
CM
6
High-speed mode (f(φ) = 4 MHz)
Middle-speed mode (f(φ) = 1 MHz)
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selected)
= 1 (Middle-speed)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selected)
= 0 (High-speed)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
“1”
“0”
CM
6
Low-speed mode (f(φ) =16 kHz)
(f(φ) =16 kHz)
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 1 (Middle-speed)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
4
2 kHz selected)
(High-speed)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
“1”
“0”
b7
b4
CPU mode register
(CPUM : address 003B16
)
CM
CM
CM
CM
4 : Port Xc switch bit
0: I/O port
1: XCIN, XCOUT
5 : Main clock (XIN–XOUT) stop bit
0: Oscillating
1: Stopped
”
0
“
M5
C
”
1
“
6
: Main clock division ratio selection bit
0: f(XIN)/2 (high-speed mode)
1: f(XIN)/8 (middle-speed mode)
Low-speed mode (f(φ) = 16 kHz)
Low-speed mode (f(φ) =16 kHz)
CM
6
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 1 (Middle-speed)
= 1 (8 MHz stopped)
= 1 (32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 0 (High-speed)
= 1 (8 MHz stopped)
= 1 (32 kHz oscillating)
“1”
“0”
7
: Internal system clock selection bit
0: XIN–XOUT selected
(middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes
1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait
mode is ended.
3: Timer and LCD operate in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6: Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-
speed mode.
7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. f indicates the internal clock.
Fig. 44 State transitions of internal clock φ
44
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit en-
able bit, the receive enable bit, and the SRDY output enable bit to
“1”.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
Interrupt
A-D Converter
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt re-
quest register, execute at least one instruction before performing a
BBC or BBS instruction.
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is at least 500kHz during an A-D conversion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
Instruction ExecutTime
The instruction executobtained by multiplying the fre-
quency of the intery the number of cycles needed to
execute an instr
The number uired to execute an instruction is shown
in the list structions.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
The free internal clock φ is half of the XIN frequency.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags
the MUL and DIV instruction.
The execution of these instructions does not chntents
of the processor status register.
Ports
The contents of the port direction rnot be read.
The following cannot be used:
• The data transfer instruction (LD)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
45
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1.Mask ROM Order Confirmation Form✽
2.Mark Specification Form✽
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
Table 13. Programming adapter
✽For the mask ROM confirmation and the mark specifications, re-
fer to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.mesc.co.jp/indexe.htm).
Package
100PFB-A
100P6Q-A
100P6S-A
100D0
Name of Programming Adapter
PCA4738H-100A
PCA4738G-100A
PCA4738F-100A
PCA4738L-100A
The PROM of the blank e PROM version is not tested or
screened in the asses and following processes. To en-
sure proper operogramming, the procedure shown in
Figure 45 is reto verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 45 Programming and testing of One Time PROM version
46
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Standard, One Time PROM Version)
Table 14. Absolute maximum ratings (Standard, One time PROM version)
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
Input voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P80, P81
V
–0.3 to VCC +0.3
VI
Input voltage P70–P77
Input voltage VL1
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
V
V
V
V
V
V
V
V
VI
VI
VI
VI
VI
VI
VO
All voltages are based on VSS.
Output transistors are cut off.
Input voltage VL2
Input voltage VL3
VL2 to 7.0
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
At output port
–0.3 to VCC
–0.3 to VL3
VO
VO
Output voltage P00–P07, P10–P15, P30–P37
At segment output
V
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81
–0.3 to VCC +0.3
V
VO
VO
VO
Pd
–0.3 to 7.0
–0.3 to VL3
–0.3 to VCC +0.3
300
Output voltage VL3
V
V
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
V
mW
°C
°C
Ta = 25°C
Operating temperature
–20 to 85
Topr
Tstg
Storage temperature
–40 to 125
Table 15. Recommended operating conditions (StandaPROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise
Limits
Symbol
Unit
V
Min.
Typ.
5.0
5.0
5.0
0
Max.
d mode f(XIN) = 8 MHz
speed mode f(XIN) = 8 MHz
-speed mode
4.0
2.5
2.5
5.5
5.5
5.5
VCC
Power source voltage
VSS
Power source voltage
V
V
V
V
VREF
AVSS
A-D conversion rege
Analog power soge
Analog input voltage 0–AN7
“H” input voltage
2.0
VCC
0
VCC
VCC
VIA
VIH
AVSS
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
V
0.7VCC
0.8VCC
0.8VCC
0.8VCC
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
V
V
V
VIH
VIH
VIH
VCC
VCC
VCC
RESET
XIN
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
0.3VCC
V
0
VIL
0
0
0
“L” input voltage
“L” input voltage
“L” input voltage
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
V
V
V
VIL
VIL
VIL
0.2VCC
0.2VCC
0.2VCC
RESET
XIN
47
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 16. Recommended operating conditions (Standard, One time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
–P0 , P1 –P1
Unit
Min.
Max.
ΣIOH(peak)
ΣIOH(peak)
“H” total peak output current
“H” total peak output current
P0
0
7
0
7
, P2
0
–P2
7
, P3
0
–P3
7
(Note 1)
–20
mA
mA
P40–P47,P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
–20
ΣIOL(peak)
“L” total peak output current
P0
P40–P47,P50–P57, P60–P67, P80, P81 (Note 1)
P7 –P7 (Note 1)
0–P07, P10–P17, P20–P27, P30–P37 (Note 1)
20
20
40
mA
mA
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
“L” total peak output current
“L” total peak output current
1
7
mA
mA
“H” total average output current P00–P07,P10–P17, P20–P27, P30–P37 (Note 1)
–10
–10
“H” total average output current P40–P47, P50–P57, P60–P67, P71–P77, P80, P81
ΣIOH(avg)
mA
(Note 1)
ΣIOL(avg)
ΣIOL(avg)
10
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
“L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1)
mA
mA
mA
10
20
“L” total average output current P71–P77 (Note 1)
ΣIOL(avg)
IOH(peak)
IOH(peak)
“H” peak output current
“H” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
–0.5
mA
mA
mA
P16, P17, P20–P27, P40–P47, P50–P57, P60–
P71–P77, P80, P81 (Note 2)
–5.0
IOL(peak)
IOL(peak)
“L” peak output current
“L” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
5.0
10
P16, P17, P20–P27, P40–P47, P50–7,
P70–P77, P80, P81 (Note 2)
mA
mA
IOH(avg)
IOH(avg)
“H” average output current
“H” average output current
P00–P07, P10–P15, P30–P37
–0.1
P16, P17, P20–P27, P40–P, P60–P67,
P71–P77, P80, P81 (Not
mA
mA
–2.5
2.5
“L” average output current
“L” average output current
P00–P07, P10–P15, te 3)
IOL(avg)
IOL(avg)
P16, P17, P20–PP50–P57, P60–P67,
P71–P77, P80, )
5.0
4.0
mA
MHz
MHz
≤ VCC ≤ 5.5 V)
CC ≤ 4.0 V)
Input frequency for timers X and Y
(duty cycle 50%)
f(CNTR0)
f(CNTR1)
(2✕VCC)
–4
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
Main clock input oscillation freque
(Note 4)
f(XIN)
8.0
MHz
MHz
High-speed mode
(VCC ≤ 4.0 V)
(4✕VCC)
–8
Middle-speed mode
8.0
50
MHz
kHz
f(XCIN)
Sub-clock input osency (Note 4, 5)
32.768
Note 1: The total output currenof all the currents flowing through all the applicable ports. The total average current is an aver-
age value measured over s. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
48
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 17. Electrical characteristics (Standard, One time PROM version)
(VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
VCC–2.0
IOH = –0.1 mA
IOH = –25 µA
VCC = 2.5 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.5 V
IOL = 5 mA
V
V
VOH
“H” output voltage P0
0–P0
7
, P1
0
–P1
5
, P3
0–P3
7
VCC–1.0
VCC–2.0
VCC–0.5
V
V
“H” output voltage P1
6
0
0
, P1
–P5
, P8
7
7
1
, P2
, P6
(Note)
0
–P2
7
, P4
, P7
0
–P4
7
,
,
VOH
VOL
P5
P8
0
–P6
7
1
–P7
7
VCC–1.0
V
2.0
0.5
V
V
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.5 V
“L” output voltage P0
0–P0
7
, P1
0
–P1
5
, P3
0–P3
7
1.0
V
2.0
0.5
V
V
“L” output voltage P1
6, P1
0–P5
0, P8
7
7
1
, P2
, P6
(Note)
0
–P2
7
,P4
0
–P4
–P7
7
,
P5
P8
0
–P6
7
, P7
1
7
,
VOL
1.0
V
V
Hysteresis
INT0–INT3, ADT, CNTR0,
CNTR1, P20–P27
VT+ – VT–
0.5
VT+ – VT–
VT+ – VT–
Hysteresis
S
CLK, R
X
D
V
V
0.5
0.5
Hysteresis
RESET
RESET: o 5.5 V
V
“H” input current
P1
P5
P8
6, P1
0–P5
0, P8
7
7
1
, P2
, P6
0
–P2
7
,P4
0
–P4
–P7
7
,
,
0
–P6
7
, P7
0
7
IIH
5.0
5.0
µA
IIH
IIH
µA
µA
“H” input current
“H” input current
RESET
VCC
4.0
X
IN
= VSS
Pull-ups “off”
µA
µA
–5.0
–140
–45
“L” input current
P1
P5
P8
6, P1
0–P5
0, P8
7
7
1
, P2
, P6
0
–P
VCC = 5 V, VI = VSS
Pull-ups “on”
0
7
,
–30
IIL
–70
–25
VCC = 3 V, VI = VSS
Pull-ups “on”
µA
µA
–6.0
“L” input current
P7
IIL
IIL
IIL
–5.0
–5.0
“L” input current
“L” input current
µA
µA
VI = VSS
VI = VSS
–4.0
V
CC = 5.0 V, V
O
= VCC, Pull-downs “on”
Output transistors “off”
= VCC, Pull-downs “on”
Output transistors “off”
= VCC, Pull-downs “off”
Output transistors “off”
= VSS, Pull-downs “off”
Output transistors “off”
µA
µA
µA
µA
30
70
140
45
Output load current P00–P07, P10–P15, P30–P37
ILOAD
ILEAK
V
CC = 3.0 V, VO
6.0
25
V
O
5.0
Output leak current P00–P07, P10–P15, P30–P37
V
O
–5.0
Note: When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P80 is different from the
value above mentioned.
49
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18. Electrical characteristics (Standard, One time PROM version)
(VCC =2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
RAM retention voltage
Test conditions
Unit
V
Min.
2.0
Typ.
Max.
5.5
VRAM
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
6.4
mA
mA
f(XCIN) = 32.768 kHz
13
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
1.6
3.2
Output transistors “off”
A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤
f(XIN) = stopped
36
14
25
7.0
15
µA
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “o
ICC
Power source current
• Low-speed mode, = 25°C
f(XIN) = stopp
f(XCIN) = 3n WIT state)
Output off”
• LowVCC = 3 V, Ta ≤ 55°C
ped
22
32.768 kHz
t transistors “off”
-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
9.0
4.5
0.1
µA
µA
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
1.0
10
Ta = 85 °C
VL1
IL1
When using voltage multiplier
VL1 = 1.8 V
1.3
1.8
3.0
10
Power source volta
2.3
6.0
50
V
Power source cur
(Note)
µA
VL1 < 1.3 V
Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
50
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 19. A-D converter characteristics (Standard, One time PROM version)
(
VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
–
–
Resolution
LSB
Absolute accuracy (excluding quantization error)
V
CC = VREF = 5 V
±2
12.5
(Note)
µs
tCONV
Conversion time
f(XIN) = 8 MHz
RLADDER
IVREF
IIA
Ladder resistor
12
50
35
100
200
5.0
kΩ
µA
µA
Reference input current
Analog port input current
150
V
REF = 5 V
Note : When an internal trigger is used in middle-speed mode, it is 14 µs.
51
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20. Timing requirements 1 (Standard, One time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Limits
Unit
Symbol
Parameter
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
250
105
105
80
80
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
800
370
370
0
100
twH(SCLK)
twL(SCLK)
t
t
su(R
X
D–SCLK
D)
)
h(SCLK–R
X
Serial I/O input hold time
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “
Table 21. Timing requirements 2 (Standard, One time PROM version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
2
µs
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
500/
tc(CNTR)
CNTR0, CNTR1 input cycle time
ns
ns
(VCC–2)
250/
(VCC–2)–20
twH(CNTR)
twL(CNTR)
CNTR0, CNTR1 input “H”
250/
(VCC–2)–20
ns
CNTR0, CNTR1 inpwidth
twH(INT)
twL(INT)
tc(SCLK)
INT0 to INT3 inpuwidth
INT0 to INT3 input “Lulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
230
230
2000
950
950
400
200
ns
ns
ns
ns
ns
ns
ns
twH(SCLK)
twL(SCLK)
t
t
su(R
X
D–SCLK
D)
)
h(SCLK–R
X
Serial I/O input hold time
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
52
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 22. Switching characteristics 1 (Standard, One time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Limits
Unit
Symbol
Parameter
Serial I/O clock output “H” pulse width
Min.
Typ.
Max.
twH(SCLK)
twL(SCLK)
t
t
c(SCLK
)
/2–30
/2–30
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
c(SCLK
)
t
t
d(SCLK–T
v(SCLK–T
X
D)
140
X
D)
–30
tr(SCLK)
tf(SCLK)
30
30
30
30
tr(CMOS)
tf(CMOS)
10
10
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Table 23. Switching characteristics 2 (Standard, One time PROM version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Limits
Symbol
Parameter
Serial I/O clock output “H” pulse width
Unit
in.
Typ.
Max.
twH(SCLK)
twL(SCLK)
t
c(SCLK
)
)
/2–50
/2–50
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
c(SCLK
t
t
d(SCLK–T
v(SCLK–T
X
D)
350
X
D)
–30
tr(SCLK)
tf(SCLK)
50
50
50
50
tr(CMOS)
tf(CMOS)
20
20
Notes 1 : When the P45/TXD P-channel output disable biT control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
53
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version)
Table 24. Absolute maximum ratings (Extended operating temperature version)
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
Input voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P80, P81
–0.3 to VCC +0.3
VI
V
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
V
V
V
V
V
V
V
V
V
VI
VI
VI
VI
VI
VI
VO
All voltages are based on VSS.
Output transistors are cut off.
VL2 to 7.0
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
Input voltage RESET, XIN
Output voltage C1, C2
–0.3 to VCC
–0.3 to VL3
At output port
Output voltage P00–P07, P10–P15, P30–P37
VO
VO
At segment output
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81
–0.3 to VCC +0.3
V
VO
–0.3 to 7.0
–0.3 to VL3
–0.3 to VCC +0.3
300
Output voltage VL3
V
V
VO
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
VO
V
Pd
Ta = 25°C
mW
°C
°C
Topr
Tstg
–40 to 85
Operating temperature
Storage temperature
–65 to 150
Table 25. Recommended operating conditions (Extendetemperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 50 to –20°C, unless otherwise noted.)
Limits
Symbol
Unit
V
Min.
Typ.
5.0
5.0
5.0
5.0
5.0
0
Max.
d mode f(XIN)=8 MHz
4.0
2.5
3.0
2.5
3.0
5.5
5.5
5.5
5.5
5.5
-speed mode
N) = 8 MHz
Ta = –20 to 85°C
Ta = –40 to –20°C
Ta = –20 to 85°C
Ta = –40 to –20°C
VCC
Power source voltage
Low-speed mode
VSS
Power source vol
V
V
V
V
VREF
AVSS
A-D conversion referce voltage
Analog power source voltage
Analog input voltage
2.0
VCC
0
VCC
VCC
AN0–AN7
AVSS
VIA
VIH
“H” input voltage
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
0.7VCC
V
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
VCC
VCC
VCC
V
V
V
VIH
VIH
VIH
0.8VCC
0.8VCC
0.8VCC
RESET
XIN
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
0
0.3VCC
0.2VCC
VIL
VIL
V
“L” input voltage
“L” input voltage
“L” input voltage
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
V
V
V
0
0
0
RESET
XIN
0.2VCC
0.2VCC
VIL
VIL
54
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 26. Recommended operating conditions (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.)
Limits
Typ.
Symbol
Parameter
–P0 , P1 –P17, P20–P27, P30–P37 (Note 1)
Unit
Min.
Max.
ΣIOH(peak)
ΣIOH(peak)
–20
mA
mA
“H” total peak output current
“H” total peak output current
P0
0
7
0
P40–P47,P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
–20
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
“L” total peak output current
“L” total peak output current
“L” total peak output current
P0
P40–P47,P50–P57, P60–P67, P80, P81 (Note 1)
P7 –P7 (Note 1)
0–P07, P10–P17, P20–P27, P30–P37 (Note 1)
20
20
mA
mA
mA
mA
1
7
40
“H” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
–10
“H” total average output current P40–P47, P50–P57, P60–P67, P70–P71, P80, P81
ΣIOH(avg)
mA
mA
–10
(Note 1)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
“L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1)
“L” total average output current P71–P77 (Note 1)
10
10
mA
mA
20
–0.5
“H” peak output current
“H” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
mA
mA
P16, P17, P20–P27, P40–P47, P50–P57, P60–
P71–P77, P80, P81 (Note 2)
–5.0
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
5.0
10
mA
mA
mA
mA
mA
mA
“L” peak output current
“L” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P40–P47, P50–P,
P71–P77, P80, P81 (Note 2)
–0.1
–2.5
2.5
“H” average output current
“H” average output current
P00–P07, P10–P15, P30–P37 (
P16, P17, P20–P27, P40–P4P60–P67,
P71–P77, P80, P81 (Note
“H” average output current
“H” average output current
P00–P07, P10–P15, Pte 3)
P16, P17, P20–P2P50–P57, P60–P67,
P71–P77, P80,
5.0
VCC ≤ 5.5 V)
MHz
MHz
f(CNTR0)
f(CNTR1)
4.0
Input frequency for timers X and Y
(duty cycle 50%)
≤ 4.0 V)
(2✕VCC)–4
gh-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
8.0
MHz
MHz
Main clock input oscillation freque
(Note 4)
f(XIN)
High-speed mode
(VCC ≤ 4.0 V)
(4✕VCC)–8
MHz
kHz
8.0
50
Middle-speed mode
f(XCIN)
Sub-clock input oscillati(Note 4, 5)
32.768
Notes 1 : The total output current iall the currents flowing through all the applicable ports. The total average current is an av-
erage value measured s. The total peak current is the peak value of all the currents.
2 : The peak output curreak current flowing in each port.
3 : The average output currs an average value measured over 100 ms.
4 : When the oscillation frequency has a duty cycle of 50%.
5 : When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
55
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 27. Electrical characteristics (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5V, Ta = –40 to –20°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –2.5 mA
Unit
Min.
Max.
VCC–2.0
V
V
VOH
“H” output voltage P0
0–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
IOH = –0.6 mA
VCC = 3.0 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 3.0 V
IOL = 5 mA
VCC–0.9
VCC–2.0
VCC–0.5
V
V
“H” output voltage P1
6, P1
0–P5
0, P8
7
7
1
, P2
, P6
(Note)
0
–P2
–P6
7
,P4
0
–P4
1
7
,
7
VOH
VOL
P5
P8
0
7
, P7
–P7
,
VCC–0.9
V
2.0
0.5
V
V
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 3.0 V
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 3.0 V
“L” output voltage P0
0–P0
7
, P1
0
–P1
5
, P3
0–P3
7
1.1
V
2.0
0.5
V
V
“L” output voltage P1
6, P1
0–P5
0, P8
7
7
1
, P2
, P6
(Note)
0
–P2
–P6
7
,P4
0
–P4
1
7
,
7
P5
P8
0
7
, P7
–P7
,
VOL
1.1
V
V
Hysteresis
INT0–INT3, ADT, CNTR0,
CNTR1, P20–P27
0.5
VT+ – VT–
Hysteresis
S
CLK, R
X
D
0.5
0.5
VT+ – VT–
VT+ – VT–
V
V
Hysteresis
RESET
RESET: V5.5 V
VI =
“H” input current
P1
P5
P8
6, P1
0–P5
0, P8
7
7
1
, P2
, P6
0
–P2
7
,P4
0
–P4
–P7
7
,
,
µA
IIH
5.0
5.0
0
–P6
7
, P7
0
7
IIH
IIH
µA
µA
“H” input current
“H” input current
RESET
C
4.0
X
IN
VSS
ull-ups “off”
µA
µA
µA
–5.0
–140
–45
“L” input current
P1
P5
P8
6, P1
0–P5
0, P8
7
7
1
, P2
, P6
0
–P2
7
VCC = 5 V, VI = VSS
Pull-ups “on”
0
–P
IIL
–70
–25
–30
VCC = 3 V, VI = VSS
Pull-ups “on”
–6.0
“L” input current
P7
0
–5.0
–5.0
µA
µA
µA
IIL
IIL
IIL
VI = VSS
VI = VSS
“L” input current
“L” input current
R
–4.0
V
CC = 5.0 V, V
O
= VCC, Pull-downs “on”
Output transistors “off”
= VCC, Pull-downs “on”
Output transistors “off”
= VCC, Pull-downs “off”
Output transistors “off”
µA
µA
µA
µA
70
170
55
30
ILOAD
ILEAK
Output load current P00–P07, P10–P15, P30–P37
V
CC = 3.0 V, VO
25
6.0
V
O
5.0
Output leak current P00–P07, P10–P15, P30–P37
V
O
= VSS, Pull-downs “off”
–5.0
Output transistors “off”
Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P80 is different from the
value above mentioned.
56
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 28. Electrical characteristics (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.)
Limits
Typ.
Symbol
Parameter
RAM retention voltage
Test conditions
At clock stop mode
Unit
V
Min.
2.0
Max.
5.5
VRAM
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
mA
mA
6.4
1.6
f(XCIN) = 32.768 kHz
13
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
3.2
Output transistors “off”
A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55
f(XIN) = stopped
µA
µA
µA
36
14
25
7.0
15
f(XCIN) = 32.768 kHz
Output transistors “off”
ICC
Power source current
• Low-speed mode, VC5°C
f(XIN) = stopped
f(XCIN) = 32.7IT state)
Output tra
• Low-spC = 3 V, Ta ≤ 55°C
f(X
22
768 kHz
ansistors “off”
eed mode, VCC = 3 V, Ta = 25°C
IN) = stopped
9.0
µA
µA
4.5
0.1
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25°C
Ta = 85°C
1.0
10
VL1
IL1
1.3
1.8
3.0
10
Power source voltage
2.3
6.0
50
V
When using voltage multiplier
VL1 = 1.8 V
Power source curr
(Note)
µA
VL1 < 1.3 V
Note : When the voltage multiplier corol bit of the LCD mode register (bit 4 at address 003916) is “1”.
Table 29. A-D converter characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
–
–
Resolution
LSB
Absolute accuracy (excluding quantization error)
V
CC = VREF = 5 V
±2
12.5
(Note)
µs
tCONV
Conversion time
f(XIN) = 8 MHz
RLADDER
IVREF
IIA
Ladder resistor
35
kΩ
µA
µA
12
50
100
200
5.0
Reference input current
Analog iinput current
150
V
REF = 5 V
Note : When an internal trigger is used in middle-speed mode, it is 14 µs.
57
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 30. Timing reguirements 1 (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted.)
Limits
Unit
Symbol
Parameter
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
250
105
105
80
80
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
800
370
370
20
100
twH(SCLK)
twL(SCLK)
t
t
su(R
X
D–SCLK
D)
)
h(SCLK–R
X
Serial I/O input hold time
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0
Table 31. Timing reguirements 2 (Extended operating temperature version
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, and VCC = 3.0 to 4.0 V, VS40 to –20°C, unless otherwise noted.)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
2
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
125
45
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
twH(XIN)
twL(XIN)
40
500/
tc(CNTR)
CNTR0, CNTR1 input cycle time
ns
ns
(VCC–2)
250/
(VCC–2)–20
twH(CNTR)
CNTR0, CNTR1 input “H” puls
250/
(VCC–2)–20
twL(CNTR)
CNTR0, CNTR1 input “L
ns
twH(INT)
twL(INT)
tc(SCLK)
230
230
2000
950
950
400
200
ns
ns
ns
ns
ns
ns
ns
INT0 to INT3 input dth
INT0 to INT3 inpwidth
Serial I/O clock inpucle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
twH(SCLK)
twL(SCLK)
t
t
su(R
X
D–SCLK
D)
)
h(SCLK–R
X
Serial I/O input hold time
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
58
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 32. Switching characteristics 1 (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted.)
Limits
Unit
Symbol
Parameter
Serial I/O clock output “H” pulse width
Min.
Max.
Typ.
twH(SCLK)
twL(SCLK)
ns
ns
ns
ns
ns
ns
ns
ns
t
t
c(SCLK
c(SCLK
)
/2–30
/2–30
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
)
t
t
d(SCLK–T
v(SCLK–T
X
D)
140
X
D)
–30
tr(SCLK)
tf(SCLK)
30
30
30
30
tr(CMOS)
tf(CMOS)
10
10
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Table 33. Switching characteristics 2 (Extended operating temperature version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –ss otherwise noted.)
Limits
Symbol
Parameter
Unit
.
Typ.
Max.
350
twH(SCLK)
twL(SCLK)
Serial I/O clock output “H” pulse width
t
CLK
)
)
/2–50
/2–50
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
c(SCLK
t
t
d(SCLK–T
v(SCLK–T
X
D)
X
D)
–30
tr(SCLK)
tf(SCLK)
50
50
50
50
tr(CMOS)
tf(CMOS)
20
20
Notes 1 : When the P45/TXD P-channel output disable bit control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
59
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (M Version)
Table 34. Absolute maximum ratings (M version)
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
Input voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P80, P81
–0.3 to VCC +0.3
VI
V
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
V
V
V
V
V
V
V
V
V
VI
VI
VI
VI
VI
VI
VO
All voltages are based on VSS.
Output transistors are cut off.
VL2 to 7.0
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
Input voltage RESET, XIN
Output voltage C1, C2
–0.3 to VCC
–0.3 to VL3
At output port
Output voltage P00–P07, P10–P15, P30–P37
VO
VO
At segment output
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77
P80, P81
–0.3 to VCC +0.3
V
VO
–0.3 to 7.0
–0.3 to VL3
–0.3 to VCC +0.3
300
Output voltage VL3
V
V
VO
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
VO
V
Pd
Ta = 25°C
mW
°C
°C
Topr
Tstg
–20 to 85
Operating temperature
Storage temperature
–40 to 125
Table 35. Recommended operating conditions (M vers
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise
Limits
Symbol
Unit
V
Min.
Typ.
5.0
5.0
5.0
0
Max.
ed mode, f(XIN)=8 MHz
-speed mode, f(XIN) = 8 MHz
w-speed mode
4.0
2.2
2.2
5.5
5.5
5.5
VCC
Power source voltage
VSS
Power source volta
V
V
V
V
2.0
VCC
VREF
AVSS
VIA
A-D conversion tage
Analog power souage
Analog input voltage
0
AVSS
VCC
VCC
AN0–AN7
“H” input voltage
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
0.7VCC
VIH
V
VCC
VCC
VCC
VIH
VIH
VIH
V
V
V
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
0.8VCC
0.8VCC
0.8VCC
RESET
XIN
P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
0.3VCC
VIL
0
V
0.2VCC
0.2VCC
0.2VCC
“L” input voltage
“L” input voltage
“L” input voltage
P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
V
V
V
0
0
0
VIL
VIL
VIL
RESET
XIN
60
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 36. Recommended operating conditions (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.)
Limits
Unit
Symbol
Parameter
–P0 , P1 –P1
Min.
Max.
Typ.
ΣIOH(peak)
ΣIOH(peak)
“H” total peak output current
“H” total peak output current
P0
0
7
0
7
, P2
0
–P2
7
, P3
0
–P3
7
(Note 1)
–20
mA
mA
P40–P47,P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
–20
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
“L” total peak output current
“L” total peak output current
“L” total peak output current
P0
P40–P47,P50–P57, P60–P67, P80, P81 (Note 1)
P7 –P7 (Note 1)
0–P07, P10–P17, P20–P27, P30–P37 (Note 1)
20
20
mA
mA
mA
mA
1
7
40
“H” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
–10
“H” total average output current P40–P47, P50–P57, P60–P67, P71–P77, P80, P81
ΣIOH(avg)
mA
mA
–10
(Note 1)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
“L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1)
“L” total average output current P71–P77 (Note 1)
10
10
mA
mA
20
–0.5
“H” peak output current
“H” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
mA
mA
P16, P17, P20–P27, P40–P47, P50–P57, P60–P
P71–P77, P80, P81 (Note 2)
–5.0
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
5.0
10
mA
mA
mA
mA
mA
mA
“L” peak output current
“L” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P40–P47, P50–P
P71–P77, P80, P81 (Note 2)
–0.1
–2.5
2.5
“H” average output current
“H” average output current
P00–P07, P10–P15, P30–P37 (
P16, P17, P20–P27, P40–P4P60–P67,
P71–P77, P80, P81 (Note
“H” average output current
“H” average output current
P00–P07, P10–P15, Pe 3)
P16, P17, P20–P250–P57, P60–P67,
P71–P77, P80, P
5.0
CC ≤ 5.5 V)
4.0
MHz
MHz
MHz
Input frequency for timers X and Y
(duty cycle 50%)
f(CNTR0)
f(CNTR1)
(10 ✕ VCC
–
–
V ≤ VCC ≤ 4.0 V)
4) / 9
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
8.0
Main clock input oscillation freq
(Note 4)
f(XIN)
High-speed mode
(2.2 V ≤ VCC ≤ 4.0 V)
(20 ✕ VCC
MHz
8) / 9
Middle-speed mode
MHz
kHz
8.0
50
Sub-clock input oscillcy (Note 4, 5)
f(XCIN)
32.768
Notes 1 : The total output curreof all the currents flowing through all the applicable ports. The total average current is an av-
erage value measurems. The total peak current is the peak value of all the currents.
2 : The peak output current e peak current flowing in each port.
3 : The average output current is an average value measured over 100 ms.
4 : When the oscillation frequency has a duty cycle of 50%.
5 : When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
61
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 37. Electrical characteristics (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
VCC–2.0
IOH = –2.5 mA
IOH = –0.25 mA
VCC = 2.2 V
V
V
VOH
“H” output voltage P0
0–P0
7
, P1
0
–P1
5
, P3
0–P3
7
VCC–0.8
VCC–2.0
VCC–0.5
V
V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.2 V
“H” output voltage P1
6
0
0
, P1
–P5
, P8
7
7
1
, P2
, P6
(Note)
0
–P2
7
,P4
0
–P4
–P7
7
,
,
VOH
VOL
P5
P8
0
–P6
7
, P7
1
7
VCC–0.8
V
IOL = 5 mA
V
V
2.0
0.5
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.2 V
“L” output voltage P0
0–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
0.8
V
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.2 V
V
V
2.0
0.5
“L” output voltage P1
6
0
0
, P1
–P5
, P8
7
7
1
, P2
, P6
(Note)
0
–P2
7
,P4
0
–P4
–P7
7
,
,
P5
P8
0
–P6
7
, P7
1
7
VOL
0.8
V
V
Hysteresis
INT0–INT3, ADT, CNTR0,
CNTR1, P20–P27
0.5
VT+ – VT–
Hysteresis
S
CLK, R
X
D
0.5
0.5
VT+ – VT–
VT+ – VT–
V
V
Hysteresis
RESET
RESET: o 5.5 V
VI
“H” input current
P1
P5
P8
6, P1
0–P5
0, P8
7
7
1
, P2
, P6
0
–P2
7
,P4
0
–P4
–P7
7
,
,
µA
IIH
5.0
5.0
0
–P6
7
, P7
0
7
IIH
IIH
µA
µA
“H” input current
“H” input current
RESET
CC
4.0
X
IN
= VSS
Pull-ups “off”
µA
µA
µA
–5.0
–140
–45
“L” input current
P1
P5
P8
6, P1
0–P5
0, P8
7
7
1
, P2
, P6
0
–P
VCC = 5 V, VI = VSS
Pull-ups “on”
0
–
7
,
IIL
–70
–25
–30
VCC = 2.2 V, VI = VSS
Pull-ups “on”
–6.0
“L” input current
P7
–5.0
–5.0
µA
µA
µA
IIL
IIL
IIL
VI = VSS
VI = VSS
“L” input current
“L” input current
–4.0
V
CC = 5.0 V, V
O
= VCC, Pull-downs “on”
Output transistors “off”
= VCC, Pull-downs “on”
Output transistors “off”
= VCC, Pull-downs “off”
Output transistors “off”
µA
µA
µA
µA
70
140
45
30
ILOAD
ILEAK
Output load current P00–P07, P10–P15, P30–P37
V
CC = 2.2 V, VO
25
6.0
V
O
5.0
Output leak current P00–P07, P10–P15, P30–P37
V
O
= VSS, Pull-downs “off”
–5.0
Output transistors “off”
Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P80 is different from the
value above mentioned.
62
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 38. Electrical characteristics (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.)
Limits
Symbol
Parameter
RAM retention voltage
Test conditions
Unit
V
Min.
2.0
Typ.
Max.
5.5
VRAM
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
mA
mA
6.4
f(XCIN) = 32.768 kHz
13
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
1.6
3.2
Output transistors “off”
A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 5
f(XIN) = stopped
µA
µA
µA
36
14
25
7.0
15
f(XCIN) = 32.768 kHz
Output transistors “off”
ICC
Power source current
• Low-speed mode, VC5°C
f(XIN) = stopped
f(XCIN) = 32.WIT state)
Output tr”
• Low-spCC = 3 V, Ta ≤ 55°C
f(Xd
22
.768 kHz
ansistors “off”
peed mode, VCC = 3 V, Ta = 25°C
XIN) = stopped
9.0
µA
µA
4.5
0.1
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25°C
1.0
10
Ta = 85°C
VL1
IL1
1.3
1.8
3.0
10
Power source voltage
2.3
6.0
50
V
When using voltage multiplier
VL1 = 1.8 V
Power source cur
(Note)
µA
VL1 < 1.3 V
Note : When the voltage multiplier cotrol bit of the LCD mode register (bit 4 at address 003916) is “1”.
Table 39. A-D converter characteristics (M version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
–
–
Resolution
LSB
Absolute accuracy (excluding quantization error)
V
CC = VREF = 5 V
±2
12.5
(Note)
µs
tCONV
Conversion time
f(XIN) = 8 MHz
RLADDER
IVREF
IIA
Ladder resistor
35
kΩ
µA
µA
12
50
100
200
5.0
Reference input current
Analog iinput current
150
V
REF = 5 V
Note : When an internal trigger is used in middle-speed mode, it is 14 µs.
63
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 40. Timing reguirements 1 (M Version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Limits
Unit
Symbol
Parameter
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
250
105
105
80
80
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
800
370
370
20
100
twH(SCLK)
twL(SCLK)
t
t
su(R
X
D–SCLK
D)
)
h(SCLK–R
X
Serial I/O input hold time
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “
Table 41. Timing reguirements 2 (M Version)
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Limits
Symbol
Parameter
Unit
Min.
Max.
Typ.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
2
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
900 /
tc(CNTR)
CNTR0, CNTR1 input cycle time
ns
ns
(VCC – 0.4)
450 /
(VCC – 0.4) – 20
twH(CNTR)
CNTR0, CNTR1 input “H” pul
450 /
(VCC – 0.4) – 20
twL(CNTR)
CNTR0, CNTR1 input “h
ns
twH(INT)
twL(INT)
tc(SCLK)
ns
ns
ns
ns
ns
ns
ns
INT0 to INT3 inpuidth
INT0 to INT3 input e width
Serial I/O clock input ycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
230
230
2000
950
950
400
200
twH(SCLK)
twL(SCLK)
t
t
su(R
X
D–SCLK
D)
)
h(SCLK–R
X
Serial I/O input hold time
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
64
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 42. Switching characteristics 1 (M version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Limits
Unit
Symbol
Parameter
Serial I/O clock output “H” pulse width
Min.
Typ.
Max.
twH(SCLK)
twL(SCLK)
t
t
c(SCLK
)
/2–30
/2–30
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
c(SCLK
)
t
t
d(SCLK–T
v(SCLK–T
X
D)
140
X
D)
–30
tr(SCLK)
tf(SCLK)
30
30
30
30
tr(CMOS)
tf(CMOS)
10
10
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Table 43. Switching characteristics 2 (M version)
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
350
twH(SCLK)
twL(SCLK)
Serial I/O clock output “H” pulse width
t
t
c(SCLK
)
)
/2–50
/2–50
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
c(SCLK
t
t
d(SCLK–T
v(SCLK–T
X
D)
X
D)
–30
tr(SCLK)
tf(SCLK)
50
50
50
50
tr(CMOS)
tf(CMOS)
20
20
Notes 1 : When the P45/TXD P-channel output disable RT control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
1 kΩ
Measurement output
Measurement output pin
100 pF
100 pF
CMOS output
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register (address
001B16) is “1” (N-channel open-drain output mode).
Fig. 46 Circuit for measuring output switching characteristics
65
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
t
C(CNTR)
t
WH(CNTR)
tWL(CNTR)
0.8VCC
CNTR0, CNTR1
0.2VCC
t
WH(INT)
tWL(INT)
INT0–INT3
0.8VCC
0.2VCC
t
W(RESET)
0.8VCC
0.2VCC
RESET
(XIN)
t
WL(XIN)
t
0.
X
IN
0.2VCC
t
C(SCLK)
t
r
t
f
tWH(SCLK)
t
WL(SCLK)
0.8VCC
h(SCLK-R
0.2VCC
S
CLK
t
su(R
X
D-SCLK
)
t
XD)
0.8VCC
0.2VCC
RXD
t
d(SCLK-T
X
D)
tv(SCLK-TXD)
T
XD
Fig. 47 Timing diagram
66
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINES
MMP
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
QFP100-P-1420-0.65
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
MD
HD
D
100
81
1
80
I2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.25
0.13
13.8
19.8
–
16.5
22.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.4
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.13
0.1
10°
–
A
A1
0.1
2.8
0.3
0.15
14.0
20.0
0.65
16.8
22.8
0.6
1.4
–
30
51
E
e
31
50
HD
HE
L
L1
x
A
y
–
–
F
b2
I2
MD
ME
0.35
–
14.6
20.6
e
b
L
x
M
–
–
–
etail F
y
–
MMP
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
EIAJ Package Code
JEDEC Code
Lead Material
Cu Alloy
MD
LQFP100-P-1414-0.50
–
HD
D
100
l2
Recommended Mount Pad
1
75
Dimension in Millimeters
Symbol
Min
–
0
Nom
–
0.1
Max
1.7
0.2
–
0.28
0.175
14.1
14.1
–
A
A1
A2
b
c
D
–
1.4
0.13
0.105
13.9
13.9
–
0.18
0.125
14.0
14.0
0.5
E
e
25
51
HD
HE
L
L1
Lp
A3
x
15.8
15.8
0.3
–
0.45
–
–
–
0°
–
16.0
16.0
0.5
1.0
0.6
0.25
–
–
16.2
16.2
0.7
–
0.75
–
0.08
0.1
10°
–
26
50
A
L1
F
e
y
–
b
x
y
L
M
b2
I2
MD
ME
0.225
–
14.4
14.4
0.9
–
–
–
–
–
Lp
Detail F
67
MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MMP
100PFB-A
Plastic 100pin 12✕12mm body TQFP
EIAJ Package Code
TQFP100-P-1212-0.40
JEDEC Code
Weight(g)
0.37
Lead Material
Cu Alloy
MD
–
HD
D
100
76
I2
1
75
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0.05
–
0.13
0.105
11.9
11.9
–
Nom
–
0.1
Max
1.2
0.15
–
0.23
0.175
12.1
12.1
–
A
A1
A2
b
c
1.0
0.18
0.125
12.0
12.0
0.4
25
51
E
L
L1
Lp
A3
x
13.8
13.8
0.4
–
0.45
–
–
–
0°
–
14.0
14.0
0.5
1.0
0.6
0.25
–
–
14.2
14.2
0.6
–
0.75
–
0.07
0.08
10°
–
26
50
A
L1
e
F
y
–
b2
I2
MD
ME
0.225
–
12.4
12.4
L
b
1.0
–
–
–
–
–
y
x
M
Lp
100D0
Glass seal 100pin QFN
EIAJ Package Code
JEDEC Code
W
–
–
5.0MAX
3.5TYP
18.85±0.15
0.65TYP 0.45TYP
21.0
51
50
80
81
31
100
1
30 1.075TYP
INDEX
68
Keep safety first in your circuit designs!
•
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personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2001 MITSUBISHI ELECTRIC CORP.
Specifications subject to change without notice.
REVISION HISTORY
3825 GROUP DATA SHEET
Rev.
Date
Description
Summary
Page
First Edition
1.0
2.0
2.1
01/23/98
05/15/98
07/13/99
Low power source version is added.
The followings are mainly revised:
7 to 10 Group expnasion
17
43
53
(11) Port P70 of port bock diagram
Name in Table 11
The “L” input current parameter of IIL in Tables 25 and 35 is not P70–P77 but P71–
P77.
“•2 Clock generating circuits” of “FEATURES” iiminated.
“•Power source voltage” of “FEATURES” is ed.
“Function” of “Vcc, Vss” into Table 1 is pad.
Figure 4 is partly revised.
Clause name and explanations of “GRANSION (STANDARD, ONE TIME
PROM VERSION, EPROM VERSpartly revised.
Table 3 is partly eliminated.
1
1
4
6
7
3.0
12/11/00
8
Table 4 is partly eliminated.
9
Clause name and explanaROUP EXPANSION (M VERSION)” are partly
revised.
10
Figure name of Figuly revised.
10
Explanations of “CPROCESSING UNIT (CPU)” are added.
(12), (13), (14) 15 is partly revised.
Figure 19 is ed.
11 to 13
20
24
Figure 31 vised.
34
ExplanaRESET CIRCUIT” are partly revised.
Figurrtly revised.
40
40
Exof “CLOCK GENERATING CIRCUIT” are partly eliminated.
is partly revised.
42
43
ations of “Decimal Calculations” of “NOTES ON PROGRAMMING” are partly
nated.
45
xplanations of “DATA REQUIRED FOR MASK ORDERS” are partly added.
Explanations of “DATA REQUIRED FOR WRITING ORDERS” in Rev.2.1 are elimi-
nated.
46
46
Note number of “IOH(avg) P00–P07, P10–P15, P30–P37” into Table 16 is revised.
Test conditions of Icc into Table 18 are partly revised.
Test conditions of Icc into Table 28 are partly revised.
Table names of Tables 34 to 43 are partly revised.
Limits of AVss into Table 35 is partly revised.
Parameter of ΣIOH(avg) into Table 36 is partly revised.
Test conditions of Icc into Table 38 is partly revised.
48
50
57
60 to 65
60
61
63
3.1
02/06/01 22
Explanations of “■Notes on interrupts” are partly revised.
Figure 19 is partly revised.
“■Notes on serial I/O” is added.
24
30
46
Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly revised.
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