M38062M4DXXXFP [RENESAS]
8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP80, 0.80 MM PITCH, PLASTIC, QFP-80;型号: | M38062M4DXXXFP |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP80, 0.80 MM PITCH, PLASTIC, QFP-80 时钟 微控制器 外围集成电路 |
文件: | 总225页 (文件大小:2050K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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April 1, 2003
3806 Group
User’s Manual
8
RENESAS 8-BIT SINGLE-CHIP
MICROCOMPUTER
740 FAMILY / 38000 SERIES
Rev.1.0 2003.04
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable, but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer’s application; they do not convey any license under any
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Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party’s rights, originating in the use of any
product data, diagrams, charts or circuit application examples contained in
these materials.
All information contained in these materials, including product data,
diagrams and charts, represent information on products at the time of
publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
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the products contained therein.
Preface
This user’s manual describes Mitsubishi’s CMOS 8-
bit microcomputers 3806 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 3806 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
For details of software, refer to the “SERIES MELPS
740 <SOFTWARE> USER’S MANUAL.”
For details of development support tools, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR MICRO-
COMPUTERS” data book.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such
as hardware design or software development. Chapter 3 also includes necessary information for systems denelopment.
Be sure to refer to this chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on setting examples
of related registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, electric
characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which
are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B16]
At reset
B
0
1
2
Name
Function
R W
b1 b0
0 0 : Single-chip mode
0
0
0
Processor mode bits
0 1 :
1 0 : Not available
1 1 :
0 : 0 page
Stack page selection bit
1 : 1 page
✕
✕
3
4
5
6
7
0
0
1
✻
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.”
0 : Operating
Main clock (XIN-XOUT) stop bit
1 : Stopped
0 : X -XOUT selected
1 : XICNIN-XCOUT selected
✻
Internal system clock selection bit
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Note 1. Contents immediately after reset release
0••••••“0” at reset release
1••••••“1” at reset release
Undefined••••••Undefined or reset release
••••••Contents determined by option at reset release
✻
Note 2. Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
••••••Read enabled
✕••••••Read disabled
W••••••Write
••••••Write enabled
✕ ••••••Write disabled
LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS
3806 group, one of the CMOS 8-bit microcomputer 38000 series presented in this user’s manual is provided with
standard functions.
The basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. For the
detailed functions of each group, refer to the related data book and user’s manual.
List of groups having the same functions
As of September 1995
3807 group
Group
3800 group
3802 group
3806 group
Function
64 pin
• 64P4B
• 64P6N-A
80 pin
• 80P6N-A
64 pin
• 64P4B
• 64P6N-A
• 64P6D-A
80 pin
Pin
• 80P6N-A
• 80P6S-A
• 80P6D-A
(Package type)
1 circuit
1 circuit
<8-bit>
1 circuit
2 circuits
<8-bit>
Clock generating circuit
<8-bit>
<8-bit>
Timer : 3
<16-bit>
Timer X/Y : 2
Timer A/B : 2
Timer
Prescaler : 3
Timer : 4
Prescaler : 3
Timer : 4
Prescaler : 3
Timer : 4
UART or
UART or
UART or
UART or
Clock synchronous ✕ 1 Clock synchronous ✕ 1
Clock synchronous ✕ 1 Clock synchronous ✕ 1
Serial I/O
—
—
Clock synchronous ✕ 1
8-bit ✕ 8-channel
Clock synchronous ✕ 1 Clock synchronous ✕ 1
8-bit ✕ 8-channel
8-bit ✕ 2-channel
8-bit ✕ 13-channel
8-bit ✕ 4-channel
A-D converter
D-A converter
8-bit ✕ 2-channel
—
24K
—
Mask
ROM
8K 16K
32K
8K
16K
32K 12K 16K 24K 32K 48K
(Note 1) (Note 1) (Note 1) (Note 3) (Note 3) (Note 3)
✽
—
—
24K
—
16K
16K
16K
512
(Note 1) (Note 1)
(Note 1)
(Note 1)
(Note 1)
One Time
16K
8K
32K
24K
48K
—
—
—
—
—
—
—
—
—
—
32K
32K
(Note 1)
(Note 1)
(Note 2)
(Note 3)
PROM
Memory
type
48K
—
16K
—
32K
24K
EPROM
—
(Note 2)
1024 384 384 512 1024 1024
RAM
384 384 512 640 384 384 384 640
PWM output
Real time port output
Analog comparator
Watchdog timer
Remarks
Notes 1: Extended operating temperature version available
2: High-speed version available
3: Extended operating temperature version and High-speed version available
✽. ROM expansion
Table of contents
Table of contents
CHAPTER 1. HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES...................................................................................................................................... 1-2
APPLICATIONS .............................................................................................................................. 1-2
PIN CONFIGURATION .................................................................................................................. 1-2
FUNCTIONAL BLOCK................................................................................................................... 1-4
PIN DESCRIPTION ........................................................................................................................ 1-5
PART NUMBERING ....................................................................................................................... 1-7
GROUP EXPANSION .................................................................................................................... 1-8
GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) ................. 1-10
GROUP EXPANSION (HIGH-SPEED VERSION) .................................................................... 1-11
FUNCTIONAL DESCRIPTION .................................................................................................... 1-12
Central Processing Unit (CPU) ............................................................................................ 1-12
Memory .................................................................................................................................... 1-16
I/O Ports .................................................................................................................................. 1-18
Interrupts ................................................................................................................................. 1-21
Timers ...................................................................................................................................... 1-23
Serial I/O ................................................................................................................................. 1-25
A-D Converter ......................................................................................................................... 1-31
D-A Converter ......................................................................................................................... 1-32
Reset Circuit ........................................................................................................................... 1-31
Clock Generating Circuit ....................................................................................................... 1-35
Processor Modes.................................................................................................................... 1-36
NOTES ON PROGRAMMING ..................................................................................................... 1-38
Processor Status Register .................................................................................................... 1-38
Interrupts ................................................................................................................................. 1-38
Decimal Calculations.............................................................................................................. 1-38
Timers ...................................................................................................................................... 1-38
Multiplication and Division Instructions ............................................................................... 1-38
Ports ......................................................................................................................................... 1-38
Serial I/O ................................................................................................................................. 1-38
A-D Converter ......................................................................................................................... 1-38
D-A Converter ......................................................................................................................... 1-38
Instruction Execution Time.................................................................................................... 1-38
Memory Expansion Mode and Microprocessor Mode ....................................................... 1-38
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-39
3806 GROUP USER'S MANUAL
i
Table of contents
3.1.9 Electrical characteristics (Extended operating temperature version) .................... 3-11
3.1.10 A-D converter characteristics (Extended operating temperature version) ........ 3-11
3.1.11 D-A converter characteristics (Extended operating temperature version) ........ 3-12
3.1.12 Timing requirements and Switching characteristics
(Extended operating temperature version).......................................................... 3-13
3.1.13 Absolute maximum ratings (High-speed version) .................................................. 3-15
3.1.14 Recommended operating conditions(High-speed version).................................... 3-15
3.1.15 Electrical characteristics (High-speed version) ...................................................... 3-16
3.1.16 A-D converter characteristics (High-speed version) ............................................ 3-16
3.1.17 D-A converter characteristics (High-speed version) ............................................ 3-17
3.1.18 Timing requirements and Switching characteristics (High-speed version)......... 3-18
3.1.19 Timing diagram ........................................................................................................... 3-22
3.2 Standard characteristics .................................................................................................... 3-25
3.2.1 Power source current characteristic examples ........................................................ 3-25
3.2.2 Port standard characteristic examples ...................................................................... 3-26
3.2.3 A-D conversion standard characteristics................................................................... 3-28
3.2.4 D-A conversion standard characteristics................................................................... 3-29
3.3 Notes on use ........................................................................................................................ 3-30
3.3.1 Notes on interrupts ...................................................................................................... 3-30
3.3.2 Notes on the serial I/O1 ............................................................................................. 3-30
3.3.3 Notes on the A-D converter ....................................................................................... 3-31
3.3.4 Notes on the RESET pin ............................................................................................ 3-32
3.3.5 Notes on input and output pins ................................................................................. 3-32
3.3.6 Notes on memory expansion mode and microprocessor mode ............................ 3-33
3.3.7 Notes on built-in PROM .............................................................................................. 3-34
3.4 Countermeasures against noise ...................................................................................... 3-36
3.4.1 Shortest wiring length .................................................................................................. 3-36
3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line............ 3-37
3.4.3 Wiring to analog input pins ........................................................................................ 3-38
3.4.4 Consideration for oscillator ......................................................................................... 3-38
3.4.5 Setup for I/O ports ....................................................................................................... 3-39
3.4.6 Providing of watchdog timer function by software .................................................. 3-39
3.5 List of registers ................................................................................................................... 3-41
3.6 Mask ROM ordering method ............................................................................................. 3-53
3.7 Mark specification form ..................................................................................................... 3-79
3.8 Package outline ................................................................................................................... 3-81
3.9 List of instruction codes ................................................................................................... 3-83
3.10 Machine Instructions ........................................................................................................ 3-84
3.11 SFR memory map .............................................................................................................. 3-94
3.12 Pin configuration ............................................................................................................... 3-95
3806 GROUP USER'S MANUAL
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. 1 Pin configuration of M38063M6-XXXFP .......................................................................... 1-2
Fig. 2 Pin configuration of M38063M6-XXXGP and M38063M6AXXXHP ............................. 1-3
Fig. 3 Functional block diagram .................................................................................................. 1-4
Fig. 4 Part numbering ................................................................................................................... 1-7
Fig. 5 Memory expansion plan .................................................................................................... 1-8
Fig. 6 Memory expansion plan (Extended operating temperature version) ........................ 1-10
Fig. 7 Memory expansion plan (High-speed version) ............................................................ 1-11
Fig. 8 740 Family CPU register structure ................................................................................ 1-12
Fig. 9 Register push and pop at interrupt generation and subroutine call ........................ 1-13
Fig. 10 Structure of CPU mode register .................................................................................. 1-15
Fig. 11 Memory map diagram.................................................................................................... 1-16
Fig. 12 Memory map of special function register (SFR) ....................................................... 1-17
Fig. 13 Port block diagram (single-chip mode) (1)................................................................. 1-19
Fig. 14 Port block diagram (single-chip mode) (2)................................................................. 1-20
Fig. 15 Interrupt control .............................................................................................................. 1-22
Fig. 16 Structure of interrupt-related registers ........................................................................ 1-22
Fig. 17 Structure of timer XY register ...................................................................................... 1-23
Fig. 18 Block diagram of timer X, timer Y, timer 1, and timer 2 ........................................ 1-24
Fig. 19 Block diagram of clock synchronous serial I/O1....................................................... 1-25
Fig. 20 Operation of clock synchronous serial I/O1 function ............................................... 1-25
Fig. 21 Block diagram of UART serial I/O............................................................................... 1-26
Fig. 22 Operation of UART serial I/O function ....................................................................... 1-27
Fig. 23 Structure of serial I/O control registers ...................................................................... 1-28
Fig. 24 Structure of serial I/O2 control register...................................................................... 1-29
Fig. 25 Block diagram of serial I/O2 function ......................................................................... 1-29
Fig. 26 Timing of serial I/O2 function....................................................................................... 1-30
Fig. 27 Structure of AD/DA control register ............................................................................ 1-31
Fig. 28 Block diagram of A-D converter .................................................................................. 1-31
Fig. 29 Block diagram of D-A converter .................................................................................. 1-32
Fig. 30 Equivalent connection circuit of D-A converter ......................................................... 1-32
Fig. 31 Example of reset circuit ................................................................................................ 1-33
Fig. 32 Internal status of microcomputer after reset.............................................................. 1-33
Fig. 33 Timing of reset ............................................................................................................... 1-34
Fig. 34 Ceramic resonator circuit .............................................................................................. 1-35
Fig. 35 External clock input circuit ........................................................................................... 1-35
Fig. 36 Block diagram of clock generating circuit.................................................................................. 1-35
Fig. 37 Memory maps in various processor modes ............................................................... 1-36
Fig. 38 Structure of CPU mode register .................................................................................. 1-36
Fig. 39 ONW function timing...................................................................................................... 1-37
Fig. 40 Programming and testing of One Time PROM version ........................................... 1-39
Fig. 41 Timing chart after an interrupt occurs ........................................................................ 1-41
Fig. 42 Time up to execution of the interrupt processing routine ....................................... 1-41
Fig. 43 A-D conversion equivalent circuit ................................................................................ 1-43
Fig. 44 A-D conversion timing chart ......................................................................................... 1-43
3806 GROUP USER’S MANUAL
i
List of figures
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of I/O port related registers ................................................................ 2-2
Fig. 2.1.2 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7, 8) ...................................................... 2-3
Fig. 2.1.3 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7, 8) ....................... 2-3
Fig. 2.2.1 Memory map of timer related registers..................................................................... 2-5
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y .............................................. 2-6
Fig. 2.2.3 Structure of Timer 1 .................................................................................................... 2-6
Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y ................................................................... 2-7
Fig. 2.2.5 Structure of Timer XY mode register ........................................................................ 2-8
Fig. 2.2.6 Structure of Interrupt request register 1 ................................................................... 2-9
Fig. 2.2.7 Structure of Interrupt request register 2 ................................................................... 2-9
Fig. 2.2.8 Structure of Interrupt control register 1 .................................................................. 2-10
Fig. 2.2.9 Structure of Interrupt control register 2 .................................................................. 2-10
Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function] ................ 2-12
Fig. 2.2.11 Setting of related registers [Clock function] ......................................................... 2-13
Fig. 2.2.12 Control procedure [Clock function] ........................................................................ 2-14
Fig. 2.2.13 Example of a peripheral circuit .............................................................................. 2-15
Fig. 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] .......... 2-15
Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output]................................... 2-16
Fig. 2.2.16 Control procedure [Piezoelectric buzzer output] .................................................. 2-16
Fig. 2.2.17 A method for judging if input pulse exists ........................................................... 2-17
Fig. 2.2.18 Setting of related registers [Measurement of frequency] ................................... 2-18
Fig. 2.2.19 Control procedure [Measurement of frequency]................................................... 2-19
Fig. 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width] ........... 2-20
Fig. 2.2.21 Setting of related registers [Measurement of pulse width] ................................ 2-21
Fig. 2.2.22 Control procedure [Measurement of pulse width]................................................ 2-22
Fig. 2.3.1 Memory map of serial I/O related registers ........................................................... 2-23
Fig. 2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-24
Fig. 2.3.3 Structure of Serial I/O1 status register ................................................................... 2-24
Fig. 2.3.4 Structure of Serial I/O1 control register.................................................................. 2-25
Fig. 2.3.5 Structure of UART control register .......................................................................... 2-25
Fig. 2.3.6 Structure of Baud rate generator ............................................................................. 2-26
Fig. 2.3.7 Structure of Serial I/O2 control register.................................................................. 2-26
Fig. 2.3.8 Structure of Serial I/O2 register ............................................................................... 2-27
Fig. 2.3.9 Structure of Interrupt edge selection register ........................................................ 2-27
Fig. 2.3.10 Structure of Interrupt request register 1 ............................................................... 2-28
Fig. 2.3.11 Structure of Interrupt request register 2 ............................................................... 2-28
Fig. 2.3.12 Structure of Interrupt control register 1 ................................................................ 2-29
Fig. 2.3.13 Structure of Interrupt control register 2 ................................................................ 2-29
Fig. 2.3.14 Serial I/O connection examples (1) ....................................................................... 2-30
Fig. 2.3.15 Serial I/O connection examples (2) ....................................................................... 2-31
Fig. 2.3.16 Setting of Serial I/O transfer data format............................................................. 2-32
Fig. 2.3.17 Connection diagram [Communication using a clock synchronous serial I/O].. 2-33
Fig. 2.3.18 Timing chart [Communication using a clock synchronous serial I/O]............... 2-33
Fig. 2.3.19 Setting of related registers at a transmitting side
[Communication using a clock synchronous serial I/O] ................................ 2-34
Fig. 2.3.20 Setting of related registers at a receiving side
[Communication using a clock synchronous serial I/O] ................................ 2-35
3806 GROUP USER’S MANUAL
ii
List of figures
Fig. 2.3.21 Control procedure at a transmitting side
[Communication using a clock synchronous serial I/O] .................................. 2-36
Fig. 2.3.22 Control procedure at a receiving side[Communication using a clock synchronous serial I/O] . 2-37
Fig. 2.3.23 Connection diagram [Output of serial data] ......................................................... 2-38
Fig. 2.3.24 Timing chart [Output of serial data] ...................................................................... 2-38
Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data].......................... 2-39
Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data] ....................... 2-39
Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data] .................................... 2-40
Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data].......................... 2-41
Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data] ....................... 2-41
Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data] .................................... 2-42
Fig. 2.3.31 Connection diagram
[Cyclic transmission or reception of block data between microcomputers] . 2-43
Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers] .......... 2-44
Fig. 2.3.33 Setting of related registers
[Cyclic transmission or reception of block data between microcomputers] . 2-44
Fig. 2.3.34 Control in the master unit ....................................................................................... 2-45
Fig. 2.3.35 Control in the slave unit ......................................................................................... 2-46
Fig. 2.3.36 Connection diagram [Communication using UART] ............................................ 2-47
Fig. 2.3.37 Timing chart [Communication using UART] ......................................................... 2-47
Fig. 2.3.38 Setting of related registers at a transmitting side [Communication using UART] ........................ 2-49
Fig. 2.3.39 Setting of related registers at a receiving side [Communication using UART] ............................ 2-50
Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART] ......... 2-51
Fig. 2.3.41 Control procedure at a receiving side [Communication using UART] .............. 2-52
Fig. 2.4.1 Memory map of A-D conversion related registers................................................. 2-53
Fig. 2.4.2 Structure of AD/DA control register ......................................................................... 2-54
Fig. 2.4.3 Structure of A-D conversion register ....................................................................... 2-54
Fig. 2.4.4 Structure of Interrupt request register 2 ................................................................. 2-55
Fig. 2.4.5 Structure of Interrupt control register 2 .................................................................. 2-55
Fig. 2.4.6 Connection diagram [Conversion of Analog input voltage] .................................. 2-56
Fig. 2.4.7 Setting of related registers [Conversion of Analog input voltage] ...................... 2-56
Fig. 2.4.8 Control procedure [Conversion of Analog input voltage]...................................... 2-57
Fig. 2.5.1 Memory map of processor mode related register ................................................. 2-58
Fig. 2.5.2 Structure of CPU mode register .............................................................................. 2-58
Fig. 2.5.3 Expansion example of ROM and RAM ................................................................... 2-59
Fig. 2.5.4 Read-cycle (OE access, SRAM) .............................................................................. 2-60
Fig. 2.5.5 Read-cycle (OE access, EPROM) ........................................................................... 2-60
Fig. 2.5.6 Write-cycle (W control, SRAM)................................................................................. 2-61
Fig. 2.5.7 Application example of the ONW function.............................................................. 2-62
Fig. 2.5.8 Expansion example of ROM and RAM [High-speed version] .............................. 2-63
Fig. 2.5.9 Read-cycle (OE access, SRAM) [High-speed version] ......................................... 2-64
Fig. 2.5.10 Read-cycle (OE access, EPROM) [High-speed version] .................................... 2-64
Fig. 2.5.11 Write-cycle (W control, SRAM) [High-speed version] ......................................... 2-65
Fig. 2.6.1 Example of Poweron reset circuit ............................................................................ 2-66
Fig. 2.6.2 RAM back-up system................................................................................................. 2-66
3806 GROUP USER’S MANUAL
iii
List of figures
CHAPTER 3 APPENDIX
Fig. 3.1.1 Circuit for measuring output switching characteristics (1) ................................... 3-21
Fig. 3.1.2 Circuit for measuring output switching characteristics (2) ................................... 3-21
Fig. 3.1.3 Timing diagram (in single-chip mode) ..................................................................... 3-22
Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (1) .. 3-23
Fig. 3.1.5 Timing diagram (in memory expansion mode and microprocessor mode) (2) .. 3-24
Fig. 3.2.1 Power source current characteristic example ........................................................ 3-25
Fig. 3.2.2 Power source current characteristic example (in wait mode).............................. 3-25
Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive(1) .. 3-26
Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive(2) .. 3-26
Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive(1) .. 3-27
Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive(2) .. 3-27
Fig. 3.2.7 A-D conversion standard characteristics................................................................. 3-28
Fig. 3.2.8 D-A conversion standard characteristics................................................................. 3-29
Fig. 3.3.1 Structure of interrupt control register 2 .................................................................. 3-30
Fig. 3.4.1 Wiring for the RESET pin ......................................................................................... 3-36
Fig. 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-37
Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM and the EPROM version ........ 3-37
Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line ...................................... 3-37
Fig. 3.4.5 Analog signal line and a resistor and a capacitor ................................................ 3-38
Fig. 3.4.6 Wiring for a large current signal line ...................................................................... 3-38
Fig. 3.4.7 Wiring to a signal line where potential levels change frequently ....................... 3-38
Fig. 3.4.8 Stepup for I/O ports................................................................................................... 3-39
Fig. 3.4.9 Watchdog timer by software ..................................................................................... 3-39
Fig. 3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7, 8) .................................................... 3-41
Fig. 3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7, 8) ..................... 3-41
Fig. 3.5.3 Structure of Transmit/Receive buffer register ........................................................ 3-42
Fig. 3.5.4 Structure of Serial I/O1 status register ................................................................... 3-42
Fig. 3.5.5 Structure of Serial I/O1 control register.................................................................. 3-43
Fig. 3.5.6 Structure of UART control register .......................................................................... 3-43
Fig. 3.5.7 Structure of Baud rate generator ............................................................................. 3-44
Fig. 3.5.8 Structure of Serial I/O2 control register.................................................................. 3-44
Fig. 3.5.9 Structure of Serial I/O2 register ............................................................................... 3-45
Fig. 3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-45
Fig. 3.5.11 Structure of Timer 1 ................................................................................................ 3-46
Fig. 3.5.12 Structure of Timer 2, Timer X, Timer Y ............................................................... 3-46
Fig. 3.5.13 Structure of Timer XY mode register .................................................................... 3-47
Fig. 3.5.14 Structure of AD/DA control register....................................................................... 3-48
Fig. 3.5.15 Structure of A-D conversion register..................................................................... 3-48
Fig. 3.5.16 Structure of D-A 1 conversion, D-A 2 conversion register ................................ 3-49
Fig. 3.5.17 Structure of Interrupt edge selection register ...................................................... 3-49
Fig. 3.5.18 Structure of CPU mode register ............................................................................ 3-50
Fig. 3.5.19 Structure of Interrupt request register 1 ............................................................... 3-51
Fig. 3.5.20 Structure of Interrupt request register 2 ............................................................... 3-51
Fig. 3.5.21 Structure of Interrupt control register 1 ................................................................ 3-52
Fig. 3.5.22 Structure of Interrupt control register 2 ................................................................ 3-52
3806 GROUP USER’S MANUAL
iv
List of tables
List of tables
CHAPTER 1 HARDWARE
Table 1 Pin description (1) ........................................................................................................... 1-5
Table 2 Pin description (2) ........................................................................................................... 1-6
Table 3 List of supported products ............................................................................................. 1-9
Table 4 List of supported products (Extended operating temperature version) .................. 1-10
Table 5 List of supported products (High-speed version) ...................................................... 1-11
Table 6 Push and pop instructions of accumulator or processor status register ............... 1-13
Table 7 Set and clear instructions of each bit of processor status register ....................... 1-14
Table 8 List of I/O port functions .............................................................................................. 1-18
Table 9 Interrupt vector addresses and priority ...................................................................... 1-21
Table 10 Functions of ports in memory expansion mode and microprocessor mode ....... 1-36
Table 11 Programming adapter.................................................................................................. 1-39
Table 12 Interrupt sources, vector addresses and interrupt priority..................................... 1-40
Table 13 Change of A-D conversion register during A-D conversion .................................. 1-42
CHAPTER 2 APPLICATION
Table 2.1.1 Handling of unused pins (in single-chip mode) .................................................... 2-4
Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) ........ 2-4
Table 2.2.1 Function of CNTR0/CNTR1 edge switch bit .......................................................... 2-8
Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values ...................... 2-48
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2
Table 3.1.2 Recommended operating conditions....................................................................... 3-3
Table 3.1.3 Electrical characteristics ........................................................................................... 3-4
Table 3.1.4 A-D converter characteristics .................................................................................. 3-4
Table 3.1.5 D-A converter characteristics .................................................................................. 3-5
Table 3.1.6 Timing requirements (1) ........................................................................................... 3-6
Table 3.1.7 Timing requirements (2) ........................................................................................... 3-6
Table 3.1.8 Switching characteristics (1) .................................................................................... 3-7
Table 3.1.9 Switching characteristics (2) .................................................................................... 3-7
Table 3.1.10 Timing requirements in memory expansion mode and microprocessor mode (1) ...................... 3-8
Table 3.1.11 Switching characteristics in memory expansion mode and microprocessor mode (1) .............. 3-8
Table 3.1.12 Timing requirements in memory expansion mode and microprocessor mode (2) ...................... 3-9
Table 3.1.13 Switching characteristics in memory expansion mode and microprocessor mode (2) .............. 3-9
Table 3.1.14 Absolute maximum ratings (Extended operating temperature version) ......... 3-10
Table 3.1.15 Recommended operating conditions (Extended operating temperature version) ..... 3-10
Table 3.1.16 Electrical characteristics (Extended operating temperature version) ............. 3-11
Table 3.1.17 A-D converter characteristics (Extended operating temperature version)..... 3-11
Table 3.1.18 D-A converter characteristics (Extended operating temperature version)..... 3-12
Table 3.1.19 Timing requirements (Extended operating temperature version).................... 3-13
Table 3.1.20 Switching characteristics (Extended operating temperature version) ............ 3-13
3806 GROUP USER’S MANUAL
i
List of tables
Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode
(Extended operating temperature version) ................................................... 3-14
Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode
(Extended operating temperature version) ................................................... 3-14
Table 3.1.23 Absolute maximum ratings (High-speed version) ............................................. 3-15
Table 3.1.24 Recommended operating conditions (High-speed version) ............................. 3-15
Table 3.1.25 Electrical characteristics (High-speed version) ................................................. 3-16
Table 3.1.26 A-D converter characteristics (High-speed version) ......................................... 3-16
Table 3.1.27 D-A converter characteristics (High-speed version) ......................................... 3-17
Table 3.1.28 Timing requirements (1) (High-speed version) ................................................. 3-18
Table 3.1.29 Timing requirements (2) (High-speed version) ................................................. 3-18
Table 3.1.30 Switching characteristics (1) (High-speed version) .......................................... 3-19
Table 3.1.31 Switching characteristics (2) (High-speed version) .......................................... 3-19
Table 3.1.32 Timing requirements in memory expansion mode and microprocessor mode (1)
(High-speed version) ....................................................................................... 3-20
Table 3.1.33 Switching characteristics in memory expansion mode and microprocessor mode (1)
(High-speed version) ....................................................................................... 3-20
Table 3.1.34 Timing requirements in memory expansion mode and microprocessor mode (2)
(High-speed version) ....................................................................................... 3-21
Table 3.1.35 Switching characteristics in memory expansion mode and microprocessor mode (2)
(High-speed version) ....................................................................................... 3-21
Table 3.3.1 Programming adapter ............................................................................................. 3-34
Table 3.3.2 Setting of programming adapter switch ............................................................... 3-34
Table 3.3.3 Setting of PROM programmer address................................................................ 3-35
Table 3.5.1 Function of CNTR0/CNTR1 edge switch bit ........................................................ 3-47
3806 GROUP USER’S MANUAL
ii
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATIONS
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
DATA REQUIRED FOR MASK
ORDERS
ROM PROGRAMMING METHOD
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION
DESCRIPTION
Clock generating circuit ....................... Internal feedback resistor
•
•
The 3806 group is 8-bit microcomputer based on the 740 family
(connect to external ceramic resonator or quartz-crystal)
Memory expansion possible
core technology.
The 3806 group is designed for controlling systems that require
analog signal processing and include two serial I/O functions, A-D
converters, and D-A converters.
Specification
(unit)
Extended operating High-speed
Standard
0.5
temperature version
version
The various microcomputers in the 3806 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
Minimum instruction
0.5
0.4
execution time
(µs)
For details on availability of microcomputers in the 3806 group, re-
fer to the section on group expansion.
Oscillation frequency
(MHz)
8
8
10
Power source voltage
(V)
FEATURES
3.0 to 5.5
32
4.0 to 5.5
32
2.7 to 5.5
40
Basic machine-language instructions ....................................... 71
•
•
Memory size
Power dissipation
(mW)
ROM ................................................................ 12 K to 48 K bytes
RAM ................................................................. 384 to 1024 bytes
Operating temperature
–20 to 85
–40 to 85
–20 to 85
Programmable input/output ports ............................................. 72
•
range
(°C)
Interrupts .................................................. 16 sources, 16 vectors
•
Timers ............................................................................. 8 bit ✕ 4
•
Serial I/O1 .................... 8-bit ✕ 1 (UART or Clock-synchronized)
•
Serial I/O2 ....................................8-bit ✕ 1 (Clock-synchronized)
APPLICATIONS
Office automation, VCRs, tuners, musical instruments, cameras,
•
A-D converter .................................................. 8-bit ✕ 8 channels
•
D-A converter .................................................. 8-bit ✕ 2 channels
air conditioners, etc.
•
PIN CONFIGURATION (TOP VIEW)
P8
P8
P8
P8
P8
P8
7
6
5
4
3
2
65
66
67
68
69
70
71
72
73
74
75
76
77
78
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
/DB
/DB
/DB
/DB
/DB
/DB
/DB
/DB
0
1
2
3
4
5
6
7
P8
P8
1
0
V
CC
V
X
X
SS
M38063M6-XXXFP
V
REF
OUT
IN
AVSS
/AN
/AN
/AN
/AN
/AN3
P6
7
7
P4
P4
RESET
CNVSS
P42/INT0
0
P66
6
1
P6
P6
P6
5
5
4
4
79
80
3
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1 Pin configuration of M38063M6-XXXFP
3806 GROUP USER’S MANUAL
1-2
HARDWARE
PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW)
P3
P3
1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
40
39
38
37
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
6
7
0
1
2
3
4
/AD14
/AD15
0
P8
P8
P8
P8
P8
P8
P8
7
/DB
/DB
/DB
/DB
/DB
/DB
/DB
/DB
0
1
2
3
4
6
36
35
34
33
5
4
3
2
1
5
6
7
5
6
7
32
31
30
29
28
27
26
25
24
P8
0
M38063M6-XXXGP
M38063M6AXXXHP
V
CC
V
ss
V
REF
X
OUT
AVSS
XIN
P4
P4
0
P6
P6
P6
P6
P6
P6
P6
7
6
5
4
3
2
/AN
7
/AN
6
1
/AN
/AN
/AN
/AN
/AN
5
4
3
2
RESET
CNVSS
P4
P4
23
22
21
78
79
80
2
/INT
/INT
0
1
3
1
1
P4
4
/RX
D
Package type : 80P6S-A/80P6D-A
80-pin plastic-molded QFP
Fig. 2 Pin configuration of M38063M6-XXXGP and M38063M6AXXXHP
3806 GROUP USER’S MANUAL
1-3
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 3 Functional block diagram
3806 GROUP USER’S MANUAL
1-4
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1. Pin description (1)
Pin
Name
Function
Function except a port function
VCC
VSS
Power source
• Apply voltage of 3.0 V to 5.5 V to VCC, and 0 V to VSS.
(Extended operating temperature version : 4.0 V to 5.5 V)
(High-speed version : 2.7 V to 5.5 V)
CNVSS
CNVSS
• This pin controls the operation mode of the chip.
• Normally connected to VSS.
• If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed.
VREF
AVSS
Analog reference • Reference voltage input pin for A-D and D-A converters
voltage
Analog power
source
• GND input pin for A-D and D-A converters
• Connect to VSS.
______
RESET
Reset input
Clock input
• Reset input pin for active “L”
XIN
• Input and output signals for the internal clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
XOUT
Clock output
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
P00 – P07
P10 – P17
P20 – P27
P30 – P37
P40, P41
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
• 8 bit CMOS I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• At reset this port is set to input mode.
• In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
P42/INT0,
P43/INT1
• CMOS 3-state output structure
• External interrupt input pin
P44/RXD,
P45/TXD,
• Serial I/O1 I/O pins
P46/SCLK1,
_____
P47/SRDY1
P50
I/O port P5
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
P51/INT2 –
P53/INT4
• CMOS 3-state output structure
• External interrupt input pin
P54/CNTR0,
P55/CNTR1
• Timer X and Timer Y I/O pins
• D-A conversion output pins
• A-D conversion input pins
P56/DA1,
P57/DA2
P60/AN0 –
P67/AN7
I/O port P6
• 8-bit CMOS I/O port with the same function as
port P0
• CMOS compatible input level
• CMOS 3-state output structure
3806 GROUP USER’S MANUAL
1-5
HARDWARE
PIN DESCRIPTION
Table 2. Pin description (2)
Pin
Name
Function
Function except a port function
• Serial I/O2 I/O pins
P70/SIN2,
P71/SOUT2,
I/O port P7
• 8-bit I/O port with the same function as port P0
• CMOS compatible input level
P72/SCLK2,
• N-channel open-drain output structure
_____
P73/SRDY2
P74 – P77
P80 – P87
I/O port P8
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
3806 GROUP USER’S MANUAL
1-6
HARDWARE
PART NUMBERING
PART NUMBERING
Product
M3806 3 M 6 - XXX FP
Package type
FP : 80P6N-A package
GP : 80P6S-A package
FS : 80D0 package
ROM number
Omitted in some types.
Normally, using hyphen
When electrical characteristic, or division of quality
identification code using alphanumeric character
– : standard
D : Extended operating temperature version
A : High-speed version
ROM/PROM size
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
0
1
2
3
4
5
6
7
Fig. 4 Part numbering
3806 GROUP USER’S MANUAL
1-7
HARDWARE
GROUP EXPANSION
Currently supported products are listed below.
Table 3. List of supported products
As of September 1995
Remarks
(P) ROM size (bytes)
Product name
RAM size (bytes)
Package
ROM size for User in (
)
M38062M3-XXXFP
M38062M3-XXXGP
M38062M4-XXXFP
M38062M4-XXXGP
M38063M6-XXXFP
M38063E6-XXXFP
M38063E6FP
80P6N-A Mask ROM version
80P6S-A Mask ROM version
80P6N-A Mask ROM version
80P6S-A Mask ROM version
Mask ROM version
12288
(12158)
384
384
16384
(16254)
80P6N-A One Time PROM version
One Time PROM version (blank)
Mask ROM version
24576
(24446)
M38063M6-XXXGP
M38063E6-XXXGP
M38063E6GP
512
80P6S-A One Time PROM version
One Time PROM version (blank)
M38063E6FS
80D0
EPROM version
M38067M8-XXXFP
M38067M8-XXXGP
M38067MC-XXXFP
M38067EC-XXXFP
M38067ECFP
80P6N-A Mask ROM version
80P6S-A Mask ROM version
Mask ROM version
32768
(32638)
1024
1024
80P6N-A One Time PROM version
One Time PROM version (blank)
Mask ROM version
49152
(49022)
M38067MC-XXXGP
M38067EC-XXXGP
M38067ECGP
80P6S-A One Time PROM version
One Time PROM version (blank)
3806 GROUP USER’S MANUAL
1-8
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
(2) Packages
Mitsubishi plans to expand the 3806 group as follows:
(1) Support for mask ROM, One Time PROM, and EPROM
versions
80P6N-A............................. 0.8 mm-pitch plastic molded QFP
80P6S-A ........................... 0.65 mm-pitch plastic molded QFP
80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version)
ROM/PROM capacity ................................ 12 K to 48 K bytes
RAM capacity .............................................. 384 to 1024 bytes
Memory Expansion Plan
Mass product
ROM size (bytes)
48K
M38067MC/EC
Mass product
M38067M8
32K
28K
Mass product
24K
20K
16K
12K
8K
M38063M6/E6
Mass product
Mass product
M38062M4
M38062M3
4K
192 256
384
512
RAM size (bytes)
640
768
896
1024
Fig. 5 Memory expansion plan
3806 GROUP USER’S MANUAL
1-9
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
(2) Packages
80P6N-A............................. 0.8 mm-pitch plastic molded QFP
(EXTENDED OPERATING TEMPERATURE VERSION)
Mitsubishi plans to expand the 3806 group (extended operating
temperature version) as follows:
(1) Support for mask ROM version
ROM/PROM capacity ................................ 12 K to 48 K bytes
RAM capacity .............................................. 384 to 1024 bytes
Memory Expansion Plan
New product
Mass product
Mass product
M38067ECD
M38067MCD
M38067M8D
ROM size (bytes)
48K
32K
28K
Mass product
24K
20K
16K
12K
8K
M38063M6D
Mass product
Mass product
M38062M4D
M38062M3D
4K
192 256
384
512
RAM size (bytes)
640
768
896
1024
Fig. 6 Memory expansion plan (Extended operating temperature version)
Currently supported products are listed below.
Table 4. List of supported products (Extended operating temperature version)
As of September 1995
Remarks
(P) ROM size (bytes)
Product name
RAM size (bytes)
Package
ROM size for User in (
12288(12158)
16384(16254)
24576(24446)
32768(32638)
)
M38062M3DXXXFP
M38062M4DXXXFP
M38063M6DXXXFP
M38067M8DXXXFP
M38067MCDXXXFP
M38067ECDXXXFP
M38067ECDFP
384
384
Mask ROM version
Mask ROM version
Mask ROM version
512
1024
80P6N-A Mask ROM version
Mask ROM version
49152(49022)
1024
One Time PROM version
One Time PROM version (blank)
3806 GROUP USER’S MANUAL
1-10
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
(2) Packages
(HIGH-SPEED VERSION)
80P6N-A............................. 0.8 mm-pitch plastic molded QFP
80P6S-A ........................... 0.65 mm-pitch plastic molded QFP
80P6D-A............................. 0.5 mm-pitch plastic molded QFP
80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version)
Mitsubishi plans to expand the 3806 group (high-speed version)
as follows:
(1) Support for mask ROM, One Time PROM, and EPROM
versions
ROM/PROM capacity ................................ 24 K to 48 K bytes
RAM capacity .............................................. 512 to 1024 bytes
Memory Expansion Plan
New product
ROM size (bytes)
48K
M38067MCA/ECA
New product
M38067M8A
32K
28K
New product
24K
20K
16K
12K
8K
M38063M6A
4K
192 256
384
512
640
768
896
1024
RAM size (bytes)
Fig. 7 Memory expansion plan (High-speed version)
Currently supported products are listed below.
Table 5. List of supported products (High-speed version)
As of September 1995
(P) ROM size (bytes)
Product name
RAM size (bytes)
Package
Remarks
ROM size for User in (
)
M38063M6AXXXFP
M38063M6AXXXGP
M38063M6AXXXHP
M38067M8AXXXFP
M38067M8AXXXGP
M38067MCAXXXFP
M38067ECAXXXFP
M38067ECAFP
80P6N-A Mask ROM version
80P6S-A Mask ROM version
80P6D-A Mask ROM version
80P6N-A Mask ROM version
80P6S-A Mask ROM version
Mask ROM version
24576
(24446)
512
32768
(32638)
1024
80P6N-A One Time PROM version
One Time PROM version (blank)
Mask ROM version
49152
(49022)
M38067MCAXXXGP
M38067ECAXXXGP
M38067ECAGP
1024
80P6S-A One Time PROM version
One Time PROM version (blank)
M38067ECAFS
80D0
EPROM version
3806 GROUP USER’S MANUAL
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Stack pointer (S)
Central Processing Unit (CPU)
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The 3806 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine in-
structions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack ad-
dress are determined by the Stack Page Selection Bit. If the Stack
Page Selection Bit is “0”, then the RAM in the zero page is used
as the stack area. If the Stack Page Selection Bit is “1”, then RAM
in page 1 is used as the stack area.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The central processing unit (CPU) has the six registers.
Accumulator (A)
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some microcom-
puter types have no Stack Page Selection Bit and the upper eight
bits of the stack address are fixed.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is added
to the contents of register X or register Y and specifies the real ad-
dress.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Fig. 9.
Program counter (PC)
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
b7
b0
Accumulator
A
b7
b7
b7
b7
b7
b0
Index Register X
X
Y
b0
Index Register Y
b0
S
Stack Pointer
b15
b0
PCH
PCL
B D
Program Counter
b0
Processor Status Register (PS)
N V
T
I Z C
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 8 740 Family CPU register structure
3806 GROUP USER’S MANUAL
1-12
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt Request
(Note 1)
M(S) ← (PCH)
Execute JSR
(S) ← (S – 1)
Store Return Address
on Stack (Note 2)
M(S) ← (PCH)
M(S) ← (PCL)
(S) ← (S – 1)
(S) ← (S – 1)
M(S) ← (PS)
(S) ← (S – 1)
Store Return Address
on Stack (Note 2)
M(S) ← (PCL)
Store Contents of
Processor Status
Register on Stack
(S) ← (S – 1)
Subroutine
Interrupt
Service Routine
I Flag “0” to “1”
Fetch the Jump
Vector
Execute RTS
Execute RTI
(S) ← (S + 1)
(PS) ← M(S)
(S) ← (S + 1)
Restore Return
Address
Restore Contents of
Processor Status
Register
(PCL) ← M(S)
(S) ← (S + 1)
(S) ← (S + 1)
(PCH) ← M(S)
(PCL) ← M(S)
Restore Return
Address
(S) ← (S + 1)
(PCH) ← M(S)
Notes 1 : The condition to enable the interrupt → Interrupt enable bit is “1”
Interrupt disable flag is “0”
2 : When an interrupt occurs, the address of the next instruction to be executed is stored in
the stack area. When a subroutine is called, the address one before the next instruction
to be executed is stored in the stack area.
Fig. 9 Register push and pop at interrupt generation and subroutine call
Table 6. Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
3806 GROUP USER’S MANUAL
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
Processor status register (PS)
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was
The processor status register is an 8-bit register consisting of flags
which indicate the status of the processor after an arithmetic op-
eration. Branch operations can be performed by testing the Carry
(C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.
In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should be
initialized in the beginning of a program.
generated by the BRK instruction. The BRK flag in the pro-
cessor status register is always “0”. When the BRK instruc-
tion is used to generate an interrupt, the processor status
register is pushed onto the stack with the break flag set to “1”.
The saved processor status is the only place where the break
flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory, e.g. the results of an op-
eration between two memory locations is stored in the accu-
mulator. When the T flag is “1”, direct arithmetic operations
and direct data transfers are enabled between memory loca-
tions, i.e. between memory and memory, memory and I/O,
and I/O and I/O. In this case, the result of an arithmetic op-
eration performed on data in memory location 1 and memory
location 2 is stored in memory location 1. The address of
memory location 1 is specified by index register X, and the
address of memory location 2 is specified by normal address-
ing modes.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arith-
metic logic unit (ALU) immediately after an arithmetic opera-
tion. It can also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic op-
eration or a data transfer is “0”, and cleared if the result is
anything other than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt gener-
ated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
(7) Overflow flag (V)
When an interrupt occurs, this flag is automatically set to “1”
to prevent other interrupts from interfering until the current in-
terrupt is serviced.
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds + 127 to
–128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instruction is stored
in the overflow flag.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it is
“1”. Decimal correction is automatic in decimal mode. Only
the ADC and SBC instructions can be used for decimal arith-
metic.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit
7 of the memory location operated on by the BIT instruction is
stored in the negative flag.
Table 7. Set and clear instructions of each bit of processor status register
C flag
SEC
CLC
Z flag
—
I flag
SEI
D flag
SED
CLD
B flag
—
T flag
SET
CLT
V flag
—
N flag
—
Set instruction
Clear instruction
—
CLI
—
CLV
—
3806 GROUP USER’S MANUAL
1-14
HARDWARE
FUNCTIONAL DESCRIPTION
CPU mode register
The CPU mode register is allocated at address 003B16.
The CPU mode register contains the stack page selection bit.
b7
b0
CPU mode register
(
CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0
1
0
1
: Single-chip mode
: Memory expansion mode
: Microprocessor mode
: Not available
Stack page selection bit
0
1
: 0 page
: 1 page
Not used (return “0” when read)
Fig. 10 Structure of CPU mode register
3806 GROUP USER’S MANUAL
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
Memory
Zero page
Special function register (SFR) area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special page
ROM
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
Address
XXXX16
RAM capacity
(bytes)
000016
SFR area
Zero page
004016
192
256
384
512
640
768
896
1024
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
010016
RAM
XXXX16
Reserved area
Not used
044016
ROM area
ROM capacity
(bytes)
Address
YYYY16
Address
ZZZZ16
YYYY16
Reserved ROM area
(128 bytes)
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ZZZZ16
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. 11 Memory map diagram
3806 GROUP USER’S MANUAL
1-16
HARDWARE
FUNCTIONAL DESCRIPTION
Port P0 (P0)
Prescaler 12 (PRE12)
Timer 1 (T1)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Port P0 direction register (P0D)
Port P1 (P1)
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Timer Y (TY)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
AD/DA control register (ADCON)
A-D conversion register (AD)
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
Serial I/O2 control register (SIO2CON)
Serial I/O2 register (SIO2)
Fig. 12 Memory map of special function register (SFR)
3806 GROUP USER’S MANUAL
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
I/O Ports
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Direction registers
The 3806 group has 72 programmable I/O pins arranged in nine
I/O ports (ports P0 to P8). The I/O ports have direction registers
which determine the input/output direction of each individual pin.
Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
Table 8. List of I/O port functions
Pin
Name
Input/Output
I/O Format
CMOS 3-state output
CMOS compatible
input level
Non-Port Function
Related SFRs
Ref.No.
Input/output,
individual bits
Address low-order byte
output
P00 – P07
Port P0
CPU mode register
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Address high-order
byte output
P10 – P17
P20 – P27
P30 – P37
Port P1
Port P2
Port P3
CPU mode register
CPU mode register
CPU mode register
(1)
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Data bus I/O
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Control signal I/O
P40,P41
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
Interrupt edge selection
register
External interrupt input
Serial I/O1 function I/O
(2)
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Port P4
(3)
(4)
(5)
(6)
(1)
Serial I/O1 control
register
P46/SCLK1,
_____
UART control register
P47/SRDY1
P50
P51/INT2,
P52/INT3,
P53/INT4
P54/CNTR0,
P55/CNTR1
P56/DA1,
P57/DA2
Interrupt edge selection
register
External interrupt input
(2)
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Port P5
Timer X and Timer Y
function I/O
Timer XY mode register
AD/DA control register
(7)
(8)
D-A conversion output
CMOS 3-state output
CMOS compatible
input level
P60/AN0 –
P67/AN7
Input/output,
individual bits
Port P6
Port P7
Port P8
A-D conversion input
(9)
P70/SIN2,
(10)
(11)
(12)
(13)
(14)
P71/SOUT2,
N-channel open-drain output
CMOS compatible
input level
Serial I/O2 control
register
Input/output,
individual bits
Serial I/O2 function I/O
P72/SCLK2,
_____
P73/SRDY2
P74 – P77
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
P80 – P87
(1)
Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func-
tion I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
3806 GROUP USER’S MANUAL
1-18
HARDWARE
FUNCTIONAL DESCRIPTION
(9) Port P6
(10) Port P70
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
A-D conversion input
Serial I/O2 input
Analog input pin selection bit
(11) Port P7
1
(12) Port P72
Serial I/O2
transmit completion signal
Serial I/O2
synchronous clock selection bit
Serial I/O2 port selection bit
Serial I/O2 port selection bit
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
Serial I/O2
external
clock input
Serial I/O2 clock output
Serial I/O2 output
(13) Port P7
3
(14) Ports P74 – Port P77
Direction register
S
RDY2 output enable bit
Direction register
Port latch
Data bus
Port latch
Data bus
Serial I/O2 ready output
Fig. 14 Port block diagram (single-chip mode) (2)
3806 GROUP USER’S MANUAL
1-20
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupts
Interrupt operation
Interrupts occur by sixteen sources: seven external, eight internal,
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering.The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
and one software.
Interrupt control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Notes on use
When the active edge of an external interrupt (INT0 to INT4,
CNTR0, or CNTR1) is changed, the corresponding interrupt re-
quest bit may also be set. Therefore, please take following se-
quence;
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Table 9. Interrupt vector addresses and priority
Interrupt Request
Remarks
Vector Addresses (Note 1)
Interrupt Source
Reset (Note 2)
INT0
Priority
High
Low
Generating Conditions
1
2
FFFD16
FFFC16
At reset
Non-maskable
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1
data reception
External interrupt
FFFB16
FFF916
FFF716
FFFA16
FFF816
FFF616
(active edge selectable)
External interrupt
INT1
3
4
(active edge selectable)
Serial I/O1
reception
Valid when serial I/O1 is selected
At completion of serial I/O1
transfer shift or when
Serial I/O1
5
FFF516
FFF416
Valid when serial I/O1 is selected
transmission
transmission buffer is empty
At timer X underflow
Timer X
Timer Y
Timer 1
Timer 2
6
7
8
9
FFF316
FFF116
FFEF16
FFED16
FFF216
FFF016
FFEE16
FFEC16
At timer Y underflow
At timer 1 underflow
STP release timer underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of serial I/O2
data transfer
External interrupt
CNTR0
CNTR1
Serial I/O2
INT2
10
11
12
13
14
FFEB16
FFE916
FFE716
FFE516
FFE316
FFEA16
FFE816
FFE616
FFE416
FFE216
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At completion of A-D conversion
External interrupt
(active edge selectable)
External interrupt
INT3
(active edge selectable)
External interrupt
INT4
15
16
17
FFE116
FFDF16
FFDD16
FFE016
FFDE16
FFDC16
(active edge selectable)
A-D converter
BRK instruction
At BRK instruction execution
Non-maskable software interrupt
Note 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3806 GROUP USER’S MANUAL
1-21
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 15 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
0
active edge selection bit
active edge selection bit
1
Not used (returns “0” when read)
INT
INT
INT
2
3
4
active edge selection bit
active edge selection bit
active edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
b7
b0
b7
b0
Interrupt request register 2
Interrupt request register 1
(IREQ2 : address 003D16
)
(IREQ1 : address 003C16
)
INT
INT
0
interrupt request bit
interrupt request bit
CNTR
0
interrupt request bit
interrupt request bit
1
CNTR
1
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Serial I/O2 interrupt request bit
INT
INT
INT
2
3
4
interrupt request bit
interrupt request bit
interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
Timer 2 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 Interrupt control register 1
(ICON1 : address 003E16
b7
b0
Interrupt control register 2
(ICON2 : address 003F16
)
)
CNTR
0
1
interrupt enable bit
interrupt enable bit
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
Serial I/O2 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
INT
INT
INT
2
3
4
interrupt enable bit
interrupt enable bit
interrupt enable bit
Timer Y interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers
3806 GROUP USER’S MANUAL
1-22
HARDWARE
FUNCTIONAL DESCRIPTION
Asynchronous serial I/O (UART) mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer, and receive data is read from the re-
ceive buffer.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can hold a character while the next charac-
ter is being received.
Data bus
Address 001816
Serial I/O1 control register Address 001A16
Receive buffer
Character length selection bit
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
P44/RXD
STdetector
7 bits
8 bits
Receive shift register
1/16
UART control register
PE FE SP detector
Address 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P46/SCLK1
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
f(XIN
)
Baud rate generator
Address 001C16
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P4
5
/TX
D
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer
Address 001816
Address 001916
Serial I/O1 status register
Data bus
Fig. 21 Block diagram of UART serial I/O
3806 GROUP USER’S MANUAL
1-26
HARDWARE
FUNCTIONAL DESCRIPTION
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
TBE=0
TSC=1✽
TBE=1
Serial output TXD
ST
SP
D0
D1
D0
D1
ST
SP
✽Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input R
X
D
D0
D1
D1
ST
D0
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes "1".
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 22 Operation of UART serial I/O function
Serial I/O1 control register (SIO1CON) 001A16
spectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of
the Serial I/O Control Register) also clears all the status flags, in-
cluding the error flags.
The serial I/O control register consists of eight control bits for the
serial I/O function.
All bits of the serial I/O1 status register are initialized to “0” at re-
set, but if the transmit enable bit (bit 4) of the serial I/O control reg-
ister has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.
UART control register (UARTCON) 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
Transmit buffer/Receive buffer register (TB/
RB) 001816
Serial I/O1 status register (SIO1STS) 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
The transmit buffer and the receive buffer are located at the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored
in the receive buffer is “0”.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
Baud rate generator (BRG) 001C16
The baud rate generator determines the baud rate for serial trans-
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer, and
the receive buffer full flag is set. A write to the serial I/O status reg-
ister clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
3806 GROUP USER’S MANUAL
1-27
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
b0
b7
Serial I/O1 status register
Serial I/O1 control register
(SIO1STS : address 0019 16
)
(SIO1CON : address 001A 16)
BRG count source selection bit (CSS)
0: f(XIN
1: f(XIN)/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
)
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
0: P4
1: P4
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinaly I/O pin
pin operates as SRDY1 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns "1" when read)
b0
b7
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
UART control register
(UARTCON : address 001B 16
)
(pins P4
1: Serial I/O enabled
(pins P4 to P4 operate as serial I/O pins)
4 to P47 operate as ordinary I/O pins)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
4
7
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return "1" when read)
Fig. 23 Structure of serial I/O control registers
3806 GROUP USER’S MANUAL
1-28
HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O2
b7
b0
Serial I/O2 control register
(SIO2CON : address 001D16
The serial I/O2 function can be used only for clock synchronous
)
serial I/O.
Internal synchronous clock selection bits
For clock synchronous serial I/O the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
b2 b1 b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
Serial I/O2 control register (SIO2CON) 001D16
The serial I/O2 control register contains seven bits which control
various serial I/O functions.
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 signal output
S
RDY2 output enable bit
0: I/O port
1: SRDY2 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
Not used (returns “0” when read)
Fig. 24 Structure of serial I/O2 control register
Internal synchronous
clock selection bits
1/8
1/16
Data bus
1/32
X
IN
1/64
1/128
1/256
P73 latch
"0"
Serial I/O2 synchronous
clock selection bit
"1"
P7
3
/SRDY2
SRDY2
Synchronization circuit
"1"
SRDY2 output enable bit
"0"
External clock
P72 latch
"0"
P7
P7
2
1
/SCLK2
/SOUT2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
"1"
Serial I/O2 port selection bit
P71 latch
"0"
"1"
Serial I/O2 port selection bit
Serial I/O shift register 2 (8)
P70/SIN2
Fig. 25 Block diagram of serial I/O2 function
3806 GROUP USER’S MANUAL
1-29
HARDWARE
FUNCTIONAL DESCRIPTION
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
D7
Serial I/O2 output SOUT2
Serial I/O2 input SIN2
D2
D0
D1
D3
D4
D5
D6
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial
I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion.
Fig. 26 Timing of serial I/O2 function
3806 GROUP USER’S MANUAL
1-30
HARDWARE
FUNCTIONAL DESCRIPTION
A-D Converter
[Comparator and Control circuit]
The functional blocks of the A-D converter are described below.
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, then stores the result in the A-D
conversion register. When an A-D conversion is complete, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
[A-D conversion register]
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to 500 kHz or more during an A-D conversion.
[AD/DA control register]
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 select a specific analog input pin. Bit 3 signals the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Bits 6 and 7 are used to control the output of the D-A converter.
b7
b0
AD/DA control register
(ADCON : address 003416
)
Analog input pin selection bits
b2 b1 b0
0 0 0: P6
0 0 1: P6
0 1 0: P6
0 1 1: P6
1 0 0: P6
1 0 1: P6
1 1 0: P6
1 1 1: P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF into 256, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of the ports P60/AN0 to P67/AN7,
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
and inputs the voltage to the comparator.
Not used (return "0" When read)
DA1 output enable bit
0: DA
1: DA
1
output disabled
output enabled
1
DA2 output enable bit
0: DA
1: DA
2
output disabled
output enabled
2
Fig. 27 Structure of AD/DA control register
Data bus
b7
3
b0
AD/DA control register
(Address 003416)
A-D control circuit
A-D interrupt request
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
Comparator
A-D conversion register (Address 003516)
8
Resistor ladder
VREF AVSS
Fig. 28 Block diagram of A-D converter
3806 GROUP USER’S MANUAL
1-31
HARDWARE
FUNCTIONAL DESCRIPTION
D-A Converter
The 3806 group has two internal D-A converters (DA1 and DA2)
with 8-bit resolutions.
The D-A converter is performed by setting the value in the D-A
conversion register. The result of D-A converter is output from the
DA1 or DA2 pin by setting the DA output enable bit to “1”.
When using the D-A converter, the corresponding port direction
register bit (DA1/P56 or DA2/P57) should be set to “0” (input sta-
tus).
D-A1 conversion register (8)
DA1 output enable bit
The output analog voltage V is determined by the value n (base
10) in the D-A conversion register as follows:
R-2R resistor ladder
P56/DA1
V = VREF ✕ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
D-A2 conversion register (8)
At reset, the D-A conversion registers are cleared to “0016”, the DA
output enable bits are cleared to “0”, and the P56/DA1 and P57/
DA2 pins are set to input (high impedance).
DA2 output enable bit
P57/DA2
R-2R resistor ladder
The D-A output is not buffered, so connect an external buffer when
driving a low-impedance load.
Set VCC to 4.0 V or more when using the D-A converter.
Fig. 29 Block diagram of D-A converter
DA
1
output enable bit
R
"0"
R
R
2R
R
R
R
R
P5 /DA1
6
"1"
2R
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
"0"
D-A1 conversion
register
"1"
AVSS
V
REF
Fig. 30 Equivalent connection circuit of D-A converter
3806 GROUP USER’S MANUAL
1-32
HARDWARE
FUNCTIONAL DESCRIPTION
Reset Circuit
______
To reset the microcomputer, the RESET pin should be held at an
Address
Register contents
0016
______
“L” level for 2 µs or more. Then the RESET pin is returned to an
“H” level (Note 1), reset is released. Internal operation does not
begin until after 8 to 13 XIN clock cycles are completed. After the
reset is completed, the program starts from the address contained
in address FFFD16 (high-order byte) and address FFFC16 (low-or-
der byte).
(000116) • • •
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
(000316) • • •
(000516) • • •
(000716) • • •
(000916) • • •
(000B16) • • •
(000D16) • • •
(000F16) • • •
(001116) • • •
(001916) • • •
(001A16) • • •
(001B16) • • •
(001D16) • • •
(002016) • • •
(002116) • • •
(002216) • • •
(002316) • • •
(002416) • • •
(002516) • • •
(002616) • • •
(002716) • • •
(003416) • • •
(003616) • • •
(003716) • • •
0016
0016
0016
0016
0016
0016
0016
0016
Make sure that the reset input voltage is less than 0.8 V for VCC of
4.0 V (Note 2).
Note 1. The power source voltage should be between the follow-
ing voltage.
(8) Port P7 direction register
• Between 3.0 V and 5.5 V for standard version
• Between 4.0 V and 5.5 V for extended operating tem-
perature version
(9)
Port P8 direction register
Serial I/O1 status register
Serial I/O1 control register
UART control register
(10)
(11)
(12)
(13)
1
1
0
1
0
1
0
0
0
0
0
0
0
0
• Between 2.7 V and 5.5 V for high-speed version
Note 2. Reset input voltage is less than the following voltage.
• 0.6 V for VCC = 3.0 V
0016
0
0
Serial I/O2 control register
• 0.8 V for VCC = 4.0 V
0016
FF16
0116
FF16
0016
FF16
FF16
FF16
FF16
• 0.54 V for VCC = 2.7 V
(14) Prescaler 12
(15)
(16)
(17)
(18)
(19)
Timer 1
Timer 2
Timer XY mode register
Prescaler X
Timer X
4.0V
Power source
0V
voltage
(20) Prescaler Y
(21)
(22)
Timer Y
0.8V
Reset input
voltage
0V
AD/DA control register
0
0
0
0
0
0
0
1
0
0
0
0
0
(23) D-A1 conversion register
0016
0016
0016
(24)
(25)
D-A2 conversion register
Interrupt edge selection register (003A16) • • •
VCC
1
5
4
(26) CPU mode register
(003B16) • • •
(003C16) • • •
(003D16) • • •
(003E16) • • •
(003F16) • • •
(PS)
RESET
0
0
✽
M51953AL
3
Interrupt request register 1
Interrupt request register 2
(27)
(28)
0016
0016
0016
0016
0.1 µ F
(29) Interrupt control register 1
VSS
(30)
Interrupt control register 2
3806 group
(31)
Processor status register
✕
✕
✕
✕
✕
✕
✕
1
(32) Program counter
(PC
H
) Contents of address FFFD16
) Contents of address FFFC16
Fig. 31 Example of reset circuit
(PC
L
Note.
✕ : Undefined
✽ : The initial values of CM1 are determined by the level at the
CNVSS pin.
The contents of all other registers and RAM are undefined
after a reset, so they must be initialized by software.
Fig. 32 Internal status of microcomputer after reset
3806 GROUP USER’S MANUAL
1-33
HARDWARE
FUNCTIONAL DESCRIPTION
X
IN
φ
RESET
RESETOUT
(internal reset)
SYNC
Address
?
?
ADH, ADL
?
?
?
FFFC
FFFD
Reset address from the vector table
ADH
Data
?
?
?
?
ADL
?
Notes 1: f(XIN) and f(φ) are in the relationship: f(XIN)=2
• f(φ).
X
IN: 8 to 13 clock cycles
2: A question mark (?) indicates an undefined status that depends on the previous status.
Fig. 33 Timing of reset
3806 GROUP USER’S MANUAL
1-34
HARDWARE
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
When the STP status is released, prescaler 12 and timer 1 will
start counting and reset will not be released until timer 1
underflows, so set the timer 1 interrupt enable bit to “0” before the
STP instruction is executed.
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT. To supply a clock signal externally, input it to
the XIN pin and make the XOUT pin open.
Oscillation control
Stop Mode
If the STP instruction is executed, the internal clock φ stops at an
“H”. Timer 1 is set to “0116” and prescaler 12 is set to “FF16”.
Oscillator restarts when an external interrupt is received, but the
internal clock φ remains at an “H” until timer 1 underflow.
This allows time for the clock circuit oscillation to stabilize.
X
IN
XOUT
If oscillator is restarted by a reset, no wait time is generated, so
______
keep the RESET pin at an “L” level until oscillation has stabilized.
Wait Mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator itself does not stop. The internal clock
restarts if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
C
IN
COUT
Fig. 34 Ceramic resonator circuit
To ensure that interrupts will be received to release the STP or
WIT state, interrupt enable bits must be set to “1” before the STP
or WIT instruction is executed.
X
IN
XOUT
Open
Vcc
Vss
External oscillation
circuit
Fig. 35 External clock input circuit
Interrupt request
Interrupt disable
Reset
S
R
Q
S
R
Q
Q
S
R
flag (I)
Reset
WIT
instruction
STP instruction
STP instruction
φ output
Internal clock φ
ONW pin
Single-chip mode
ONW
control
1/2
Rd
1/8
Prescaler 12
Timer 1
FF16
0116
Reset or STP instruction
Rf
X
IN
XOUT
Fig. 36 Block diagram of clock generating circuit
3806 GROUP USER’S MANUAL
1-35
HARDWARE
FUNCTIONAL DESCRIPTION
Processor Modes
Single-chip mode, memory expansion mode, and microprocessor
mode can be selected by changing the contents of the processor
mode bits CM0 and CM1 (bits 0 and 1 of address 003B16). In
memory expansion mode and microprocessor mode, memory can
be expanded externally through ports P0 to P3. In these modes,
ports P0 to P3 lose their I/O port functions and become bus pins.
000016
000816
000016
000816
SFR area
SFR area
004016
004016
Internal RAM
reserved area
Internal RAM
reserved area
044016
044016
Table 10. Functions of ports in memory expansion mode and
microprocessor mode
Port Name
Port P0
Function
✽
YYYY16
Outputs low-order byte of address.
Outputs high-order byte of address.
Operates as I/O pins for data D7 to D0
(including instruction codes).
Internal ROM
Port P1
FFFF16
FFFF16
Port P2
Memory expansion mode
Microprocessor mode
P30 and P31 function only as output pins
The shaded areas are external memory areas.
YYYY16 is the start address of internal ROM.
✽
(except that the port latch cannot be read).
_____
:
P32 is the ONW input pin.
_________
P33 is the RESETOUT output pin. (Note)
Fig. 37 Memory maps in various processor modes
Port P3
P34 is the φ output pin.
P35 is the SYNC output pin.
___
P36 is the WR output pin, and P37 is the
___
RD output pin.
b7
b0
Note: If CNVSS is connected to VSS, the microcomputer goes to
CPU mode register
(CPUM : address 003B16
single-chip mode after a reset, so this pin cannot be used
as the RESETOUT output pin.
_________
)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not available
Single-Chip Mode
Select this mode by resetting the microcomputer with CNVSS con-
nected to VSS.
Memory Expansion Mode
Stack page selection bit
0 : 0 page
1 : 1 page
Select this mode by setting the processor mode bits to “01” in soft-
ware with CNVSS connected to VSS. This mode enables external
memory expansion while maintaining the validity of the internal
ROM. Internal ROM will take precedence over external memory if
addresses conflict.
Not used (return “0” when read)
Fig. 38 Structure of CPU mode register
Microprocessor Mode
Select this mode by resetting the microcomputer with CNVSS con-
nected to VCC, or by setting the processor mode bits to “10” in
software with CNVSS connected to VSS. In microprocessor mode,
the internal ROM is no longer valid and external memory must be
used.
3806 GROUP USER’S MANUAL
1-36
HARDWARE
FUNCTIONAL DESCRIPTION
Bus control with memory expansion
_____
The 3806 group has a built-in ONW function to facilitate access to
external memory and I/O devices in memory expansion mode or
microprocessor mode.
_____
If an “L” level signal is input to the ONW pin when the CPU is in a
read or write state, the corresponding read or write cycle is ex-
___
tended by one cycle of φ. During this extended period, the RD or
___
WR signal remains at “L”. This extension period is valid only for
writing to and reading from addresses 000016 to 000716 and
044016 to FFFF16 in microprocessor mode, 044016 to YYYY16 in
memory expansion mode, and only read and write cycles are ex-
tended.
Dummy cycle
Read cycle Dummy cycle
Read cycle
Write cycle
Write cycle
φ
AD15 to AD
0
RD
WR
ONW
✽
✽
✽
✽:
Period during which ONW input signal is received
During this period, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW
signal has no affect on operations.
The bus cycles is not extended for an address in the area 000816 to 043F16, regardless of whether the ONW signal
is received.
_____
Fig. 39 ONW function timing
3806 GROUP USER’S MANUAL
1-37
HARDWARE
NOTES ON PROGRAMMING
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
In clock synchronous serial I/O, if the receive side is using an ex-
_____
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
ternal clock and it is to output the SRDY1 signal, set the transmit
_____
enable bit, the receive enable bit, and the SRDY1 output enable bit
to “1”.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed. The SOUT2 pin from serial I/O2 goes to
high impedance after transmission is completed.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt re-
quest register, execute at least one instruction before executing a
BBC or BBS instruction.
A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is at least 500 kHz during an A-D conver-
____
sion. (If the ONW pin has been set to “L”, the A-D conversion will
take twice as long to match the longer bus cycle, and so f(XIN)
must be at least 1 MHz.)
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
D-A Converter
The accuracy of the D-A converter becomes poor rapidly under
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
the VCC = 4.0 V or less condition.
The carry flag can be used to indicate whether a carry or borrow
has occurred. Initialize the carry flag before each calculation.
Clear the carry flag before an ADC and set the flag before an
SBC.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
The frequency of the internal clock φ is half of the XIN frequency.
_____
quency division ratio is 1/(n + 1).
When the ONW function is used in modes other than single-chip
mode, the frequency of the internal clock φ may be one fourth the
XIN frequency.
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
Memory Expansion Mode and Microproces-
sor Mode
Execute the LDM or STA instruction for writing to port P3 (address
000616) in memory expansion mode and microprocessor mode.
Set areas which can be read out and write to port P3 (address
000616) in a memory, using the read-modify-write instruction
(SEB, CLB).
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
3806 GROUP USER’S MANUAL
1-38
HARDWARE
DATA REQUIRED FOR MASK ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM produc-
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
tion:
1. Mask ROM Order Confirmation Form
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical
copies)
Table 11. Programming adapter
Package
80P6N-A
80P6S-A
80D0
Name of Programming Adapter
PCA4738F-80A
PCA4738G-80A
PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 40 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 40 Programming and testing of One Time PROM version
3806 GROUP USER’S MANUAL
1-39
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
requests occur during the same sampling, the higher-
priority interrupt is accepted first. This priority is
determined by hardware, but variety of priority
processing can be performed by software, using an
interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and inter-
rupt priority, refer to “Table 12.”
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt
3806 group permits interrupts on the basis of 16
sources. It is vector interrupts with a fixed priority
system. Accordingly, when two or more interrupt
Table 12. Interrupt sources, vector addresses and interrupt priority
Vector addresses
Priority
Interrupt sources
Reset (Note)
Remarks
Non-maskable
High-order Low-order
FFFC16
FFFA16
1
2
FFFD16
FFFB16
INT0 interrupt
External interrupt
(active edge selectable)
External interrupt
FFF816
3
INT1 interrupt
FFF916
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
4
5
Serial I/O1 receive interrupt
Serial I/O1 transmit interrupt
Timer X interrupt
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
6
7
Timer Y interrupt
8
Timer 1 interrupt
STP release timer underflow
9
Timer 2 interrupt
10
CNTR0 interrupt
External interrupt
(active edge selectable)
External interrupt
FFE816
11
CNTR1 interrupt
FFE916
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
FFE616
FFE416
12
13
Serial I/O2 interrupt
INT2 interrupt
FFE716
FFE516
(active edge selectable)
External interrupt
FFE216
FFE016
14
15
INT3 interrupt
INT4 interrupt
FFE316
FFE116
(active edge selectable)
External interrupt
(active edge selectable)
FFDE16
FFDC16
16
17
A-D conversion interrupt
BRK instruction interrupt
FFDF16
FFDD16
Non-maskable software interrupt
Note: Reset functions in the same way as an interrupt with the highest priority.
3806 GROUP USER’S MANUAL
1-40
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
Figure 41 shows a timing chart after an interrupt
occurs, and Figure 42 shows the time up to execu-
tion of the interrupt processing routine.
The interrupt processing routine begins with the
machine cycle following the completion of the in-
struction that is currently in execution.
SYNC
RD
WR
S, SPS S-1, SPS S-2, SPS
Address bus
Data bus
PC
BL
BH
A
L, AH
Not used
PC
H
PCL
PS
A
L
A
H
SYNC : CPU operation code fetch cycle
B
A
L
, B
H
: Vector address of each interrupt
: Jump destination address of each interrupt
L, A
H
SPS : “0016” or “0116
”
Fig. 41 Timing chart after an interrupt occurs
Generation of interrupt request
Start of interrupt processing
Waiting time for
post-processing
of pipeline
Stack push and
Vector fetch
Main routine
Interrupt processing routine
0 to 16 ✻cycles
2 cycles
5 cycles
7 to 23 cycles
(At performing 8.0 MHz, 1.75 µs to 5.75 µs)
✻: at execution of DIV instruction (16 cycles)
Fig. 42 Time up to execution of the interrupt processing routine
3806 GROUP USER’S MANUAL
1-41
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
By repeating the above operations up to the lowest-
order bit of the A-D conversion register, an analog
value converts into a digital value.
A-D conversion completes at 50 clock cycles (12.5
µs at f(XIN) = 8.0 MHz) after it is started, and the
result of the conversion is stored into the A-D con-
version register.
A-D conversion is started by setting AD conversion
completion bit to “0.” During A-D conversion, inter-
nal operations are performed as follows.
1. After the start of A-D conversion, A-D conversion
register goes to “0016.”
2. The highest-order bit of A-D conversion register
is set to “1,” and the comparison voltage Vref is
input to the comparator. Then, Vref is compared
with analog input voltage VIN.
Concurrently with the completion of A-D conversion,
A-D conversion interrupt request occurs, so that the
AD conversion interrupt request bit is set to “1.”
3. As a result of comparison, when Vref < VIN, the
highest-order bit of A-D conversion register be-
comes “1.” When Vref > VIN, the highest-order
bit becomes “0.”
Relative formula for a reference voltage VREF of A-D converter and Vref
When n = 0
Vref = 0
VREF
256
When n = 1 to 255
Vref =
✕ (n – 0.5)
n : the value of A-D converter (decimal numeral)
Table 13. Change of A-D conversion register during A-D conversion
Change of A-D conversion register
Value of comparison voltage (Vref)
0
At start of conversion
First comparison
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VREF
512
VREF
4
VREF
2
–
±
±
VREF
512
VREF
8
VREF
2
✽ 1
✽ 1
1
0
1
0
0
0
0
0
0
0
0
0
0
Second comparison
Third comparison
–
VREF
4
VREF
2
VREF
✽ 2
±
–
512
~
~
~
~
A result of A-D conversion
✽ 1 ✽ 2 ✽ 3 ✽4 ✽ 5 ✽ 6 ✽ 7 ✽ 8
After completion of eighth
comparison
✽1: A result of the first comparison
✽3: A result of the third comparison
✽5: A result of the fifth comparison
✽7: A result of the seventh comparison
✽2: A result of the second comparison
✽4: A result of the fourth comparison
✽6: A result of the sixth comparison
✽8: A result of the eighth comparison
3806 GROUP USER’S MANUAL
1-42
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 43 shows A-D conversion equivalent cir-
cuit, and Figure 44 shows A-D conversion timing
chart.
VCC
VSS
VCC AVSS
about 2 k
VIN
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
Sampling
clock
C
Chopper amplifier
A-D conversion register
b2 b1 b0
AD/DA control register
A-D conversion interrupt request
Vref
V
REF
Build-in
D-A converter
Reference
clock
AVSS
Fig. 43 A-D conversion equivalent circuit
Write signal for AD/DA control register
AD conversion completion bit
50 cycles
Sampling clock
Fig. 44 A-D conversion timing chart
3806 GROUP USER’S MANUAL
1-43
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
MEMORANDUM
3806 GROUP USER’S MANUAL
1-44
CHAPTER 2
APPLICATION
2.1 I/O port
2.2 Timer
2.3 Serial I/O
2.4 A-D converter
2.5 Processor mode
2.6 Reset
APPLICATION
2.1 I/O port
2.1 I/O port
2.1.1 Memory map of I/O port
Port P0 (P0)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Fig. 2.1.1 Memory map of I/O port related registers
3806 GROUP USER’S MANUAL
2-2
APPLICATION
2.1 I/O port
2.1.2 Related registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1016]
At reset
B
Name
Function
R W
Port Pi0
Port Pi1
0
1
2
3
4
5
6
7
●
●
In output mode
?
Write
Read
Port latch
?
?
?
?
?
?
?
In input mode
Port Pi2
Port Pi3
Write : Port latch
Read : Value of pins
Port Pi4
Port Pi5
Port Pi6
Port Pi7
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16, 0F16, 1116
]
Name
Function
input mode
output mode
B
0
At reset R W
0 : Port Pi
1 : Port Pi
0
0
Port Pi direction register
✕
✕
✕
0
0
0
0
0
0
0
0
0 : Port Pi
1 : Port Pi
1
1
input mode
output mode
1
2
3
4
5
6
7
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
input mode
output mode
0 : Port Pi
1 : Port Pi
3
3
✕
✕
✕
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
✕
✕
0 : Port Pi
1 : Port Pi
7
7
input mode
output mode
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
3806 GROUP USER’S MANUAL
2-3
APPLICATION
2.1 I/O port
2.1.3 Handling of unused pins
Table 2.1.1 Handling of unused pins (in single-chip mode)
Name of Pins/Ports
Handling
P0, P1, P2, P3, P4, P5, P6, P7, P8
•
Set to the input mode and connect to VCC or VSS through a
resistor of 1 k to 10 k .
• Set to the output mode and open at “L” or “H.”
Connect to VSS(GND) or open.
VREF
AVSS
XOUT
Connect to VSS(GND).
Open (only when using external clock).
Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode)
Name of Pins/Ports Handling
Open
P30, P31
•
Set to the input mode and connect to VCC or VSS through a
resistor of 1 k to 10 k .
P4, P5, P6, P7, P8
• Set to the output mode and open at “L” or “H.”
Connect to VSS(GND) or open.
VREF
____
Connect to VCC through a resistor of 1 k to 10 k .
ONW
_________
RESETOUT
Open
Open
Open
SYNC
AVSS
XOUT
Connect to VSS(GND).
Open (only when using external clock).
3806 GROUP USER’S MANUAL
2-4
APPLICATION
2.2 Timer
2.2 Timer
2.2.1 Memory map of timer
Prescaler 12 (PRE12)
Timer 1 (T1)
002016
002116
002216
002316
002416
002516
002616
002716
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
~
~
~
~
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
003C16
003D16
003E16
003F16
Fig. 2.2.1 Memory map of timer related registers
3806 GROUP USER’S MANUAL
2-5
APPLICATION
2.2 Timer
2.2.2 Related registers
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)
[Address : 2016, 2416, 2616
]
At reset
Function
R W
B
●
The count value of each prescaler is set.
The value set in this register is written to both the prescaler and
the prescaler latch at the same time.
When the prescaler is read out, the value (count value) of the
prescaler is read out.
0
1
2
3
4
5
6
7
1
●
1
1
1
1
1
1
1
●
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2116
]
At reset
Function
B
R W
●
The count value of the Timer 1 is set.
The value set in this register is written to both the Timer 1 and
the Timer 1 latch at the same time.
When the Timer 1 is read out, the value (count value) of the
Timer 1 is read out.
0
1
2
3
4
5
6
7
1
●
0
0
0
0
0
0
0
●
Fig. 2.2.3 Structure of Timer 1
3806 GROUP USER’S MANUAL
2-6
APPLICATION
2.2 Timer
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2), Timer X (TX), Timer Y (TY)
[Address : 2216, 2516, 2716]
B
At reset
Function
R W
●
●
The count value of each timer is set.
The value set in this register is written to both the Timer and the
Timer latch at the same time.
When the Timer is read out, the value (count value) of the Timer
is read out.
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
●
Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y
3806 GROUP USER’S MANUAL
2-7
APPLICATION
2.2 Timer
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register (TM) [Address : 2316
]
Name
At reset
B
0
R
Function
W
b1 b0
Timer X operating mode
0 0 : Timer mode
0
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
1
2
3
4
5
6
7
0
0
0
0
0
0
0
It depends on the operating mode
of the Timer X (refer to Table 2.2.1).
CNTR
bit
Timer X count stop bit
0 active edge switch
0 : Count start
1 : Count stop
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
It depends on the operating mode
of the Timer Y (refer to Table 2.2.1).
Timer Y operating mode
CNTR
bit
1
active edge switch
Timer Y count stop bit
0 : Count start
1 : Count stop
Fig. 2.2.5 Structure of Timer XY mode register
Table. 2.2.1 Function of CNTR0/CNTR1 edge switch bit
Operating mode of
Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6)
Timer X/Timer Y
Timer mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
(No effect on timer count)
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
(No effect on timer count)
• Start of pulse output : From “H” level
Pulse output mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Start of pulse output : From “L” level
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
• Timer X/Timer Y : Count of rising edge
Event counter mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Timer X/Timer Y : Count of falling edge
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
• Timer X/Timer Y : Measurement of “H” level width
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Timer X/Timer Y : Measurement of “L” level width
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
Pulse width measurement mode
3806 GROUP USER’S MANUAL
2-8
APPLICATION
2.2 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C16]
At reset
Name
Function
0 : No interrupt request
1 : Interrupt request
R W
B
0
INT0 interrupt request bit
0
0
0
✻
✻
✻
✻
✻
✻
✻
✻
0 : No interrupt request
1 : Interrupt request
INT1 interrupt request bit
1
2
0 : No interrupt request
1 : Interrupt request
Serial I/O1 receive interrupt
request bit
0 : No interrupt request
1 : Interrupt request
Serial I/O1 transmit interrupt
request bit
3
0
0 : No interrupt request
1 : Interrupt request
Timer X interrupt request
bit
4
5
6
7
0
0
0
0
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
Timer Y interrupt request
bit
Timer 1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
Timer 2 interrupt request bit
✻
“0” is set by software, but not “1.”
Fig. 2.2.6 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D16
]
At reset
Name
B
Function
R W
0 : No interrupt request
1 : Interrupt request
✻
CNTR
0
interrupt request bit
0
1
2
3
4
5
6
7
0
0 : No interrupt request
1 : Interrupt request
CNTR
1
interrupt request bit
✻
✻
✻
0
0
0
0
0
0
Serial I/O2 interrupt request
bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
INT
2
interrupt request bit
interrupt request bit
interrupt request bit
INT
3
✻
✻
✻
0 : No interrupt request
1 : Interrupt request
INT
4
AD conversion interrupt
request bit
0 : No interrupt request
1 : Interrupt request
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
✕
0
✻
“0” is set by software, but not “1.”
Fig. 2.2.7 Structure of Interrupt request register 2
3806 GROUP USER’S MANUAL
2-9
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
At reset
Name
Function
0 : Interrupt disabled
1 : Interrupt enabled
R W
B
0
INT0 interrupt enable bit
0
0 : Interrupt disabled
1 : Interrupt enabled
INT1 interrupt enable bit
1
2
3
4
0
0
0
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 receive interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 transmit interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Timer X interrupt enable bit
Timer Y interrupt enable bit
5
6
0 : Interrupt disabled
1 : Interrupt enabled
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
7
Fig. 2.2.8 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16
]
At reset
Name
B
Function
R W
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
CNTR
0
interrupt enable bit
0
1
2
3
4
5
6
7
0
CNTR
1
interrupt enable bit
0
0
0
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O2 interrupt enable bit
INT
INT
2
3
interrupt enable bit
interrupt enable bit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
INT
4
0 : Interrupt disabled
1 : Interrupt enabled
AD conversion interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fix this bit to “0.”
Fig. 2.2.9 Structure of Interrupt control register 2
3806 GROUP USER’S MANUAL
2-10
APPLICATION
2.2 Timer
2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2)
The Timer count stop bit is set to “0” after setting a count value to a timer. Then a timer interrupt
request occurs after a certain period.
[Use] • Generation of an output signal timing
• Generation of a waiting time
[Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2)
The value of a timer latch is automatically written to a corresponding timer every time a timer
underflows, and each cyclic timer interrupt request occurs.
[Use] • Generation of cyclic interrupts
• Clock function (measurement of 250m second) → Application example 1
• Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X, Timer Y)
The output level of the CNTR pin is inverted every time a timer underflows (Pulse output mode).
[Use] • A piezoelectric buzzer output → Application example 2
• Generation of the remote-control carrier waveforms
[Function 4] Count of External pulse (Timer X, Timer Y)
External pulses input to the CNTR pin are selected as a timer count source (Event counter
mode).
[Use] • Measurement of frequency → Application example 3
• Division of external pulses.
• Generation of interrupts in a cycle based on an external pulse.
(count of a reel pulse)
[Function 5] Measurement of External pulse width (Timer X, Timer Y)
The “H” or “L” level width of external pulses input to CNTR pin is measured (Pulse width
measurement mode).
[Use] • Measurement of external pulse frequency (Measurement of pulse width of FG pulse✽ gener-
ated by motor) → Application example 4
• Measurement of external pulse duty (when the frequency is fixed)
✽FG pulse : Pulse used for detecting the motor speed to control the motor speed.
3806 GROUP USER’S MANUAL
2-11
APPLICATION
2.2 Timer
(2) Timer application example 1 : Clock function (measurement of 250 ms)
Outline : The input clock is divided by a timer so that the clock counts up every 250 ms.
Specifications : • The clock f(XIN) = 4.19 MHz (222 Hz) is divided by a timer.
• The clock is counted at intervals of 250 ms by the Timer X interrupt.
Figure 2.2.10 shows a connection of timers and a setting of division ratios, Figure 2.2.11 shows a
setting of related registers, and Figure 2.2.12 shows a control procedure.
Fixed
1/16
Prescaler X
1/256
Timer X
1/256
Timer X interrupt request bit
The clock is divided by 4 by software.
0 or 1
1/4
f(XIN) =
4.19 MHz
250 ms
1 second
0 : No interrupt request
1 : Interrupt request
Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function]
3806 GROUP USER’S MANUAL
2-12
APPLICATION
2.2 Timer
Timer XY mode register (Address : 2316
)
b7
b0
1
TM
0 0
Timer X operating mode bits : Timer mode
Timer X count stop bit : Count stop
Set to “0” at starting count.
Prescaler X (Address : 2416
)
b7
b0
PREX
TX
255
Timer X (Address : 2516
)
Set “division ratio – 1”
b7
b0
255
Interrupt control register 1 (Address : 3E16
)
b7
b0
1
ICON1
Timer X interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C16
)
b7
b0
IREQ1
0
Timer X interrupt request bit
(becomes “1” every 250 ms)
Fig. 2.2.11 Setting of related registers [Clock function]
3806 GROUP USER’S MANUAL
2-13
APPLICATION
2.2 Timer
Control procedure :
Figure 2.2.12 shows a control procedure.
●
X : This bit is not used in this application.
RESET
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
SEI
●
All interrupts : Disabled
XXXX1X00
2
●
(Address : 2316
(Address : 3E16), bit4
)
TM
ICON1
Timer X : Timer mode
Timer X interrupt : Enabled
1
●
256 – 1
256 – 1
(Address : 2416
(Address : 2516
)
)
●
PREX
TX
Set “division ratio – 1” to the Prescaler X
and Timer X.
0
(Address : 2316), bit3
●
TM
CLI
Timer X count : Operating
Interrupts : Enabled
●
●
When restarting the clock from zero
Main processing
second after completing to set the
clock, reset timers.
[Processing for completion of setting clock]
(Note 1)
Note 1: This processing is performed only
at completing to set the clock.
(Address : 2416
(Address : 2516
(Address : 3C16), bit4
)
)
256 – 1
256 – 1
0
PREX
TX
IREQ1
~
~
Timer X interrupt processing routine
Note 2: When using the Index X mode flag (T).
Note 3: When using the Decimal mode flag (D).
CLT (Note 2)
CLD (Note 3)
Push register to stack
●
Push the register used in the interrupt
processing routine into the stack.
Y
Clock stop?
●
Check if the clock has already been set.
Count up the clock.
N
●
Clock count up (1/4 second-year)
●
Pop registers which is pushed to stack
Pop registers
RTI
Fig. 2.2.12 Control procedure [Clock function]
3806 GROUP USER’S MANUAL
2-14
APPLICATION
2.2 Timer
(3) Timer application example 2 : Piezoelectric buzzer output
Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer
output.
Specifications : • The rectangular waveform resulting from dividing clock f(XIN) = 4.19 MHz into about
2 kHz (2048 Hz) is output from the P54/CNTR0 pin.
• The level of the P54/CNTR0 pin fixes to “H” while a piezoelectric buzzer output is
stopped.
Figure 2.2.13 shows an example of a peripheral circuit, and Figure 2.2.14 shows a connection of the
timer and setting of the division ratio.
The “H” level is output while a piezoelectric buzzer output is stopped.
CNTR0 output
3806 group
P54/CNTR0
PiPiPi....
244 µs
244 µs
Set a division ratio so that the underflow output cycle of the Timer X becomes this value.
Fig. 2.2.13 Example of a peripheral circuit
Timer X
1/64
Fixed
1/16
Prescaler X
Fixed
1/2
f(XIN) = 4.19 MHz
1
CNTR
0
Fig. 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]
3806 GROUP USER’S MANUAL
2-15
APPLICATION
2.2 Timer
Timer XY mode register (Address : 23 16
)
b7
b0
TM
1
0 0 1
Timer X operating mode bits : Pulse output mode
CNTR0 active edge switch bit : Output from the “H” level
Timer X count stop bit : Count stop
Set to “0” at starting to count.
Timer X (Address : 2516
)
b7
b0
TX
63
Set “division ratio – 1”
Prescaler X (Address : 24 16
)
b7
b0
PREX
0
Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output]
Control procedure :
Figure 2.2.16 shows a control procedure.
RESET
●
X : This bit is not used in this application.
Initialization
Set it to “0” or “1.” It’s value can be disregarded.
1
(Address : 0A16), bit4
P5
P5D
XXX1XXXX
2
(Address : 0B16
)
●
●
0
(Address : 3E16), bit4
ICON1
TM
Timer X interrupts : Disabled
The CNTR0 output is stopped at this point (stop
XXXX1001
2
(Address : 2316
)
outputting a piezoelectric buzzer).
Set “division ratio – 1” to the Prescaler X and
Timer X.
●
TX
PREX
(Address : 2516
(Address : 2416
)
)
64 – 1
1 – 1
Main processing
●
The piezoelectric buzzer request occured in the
main processing is processed in the output unit.
Output unit
A piezoelectric buzzer
is requested?
Y
N
TM (Address : 2316), bit3
TX (Address : 2516
1
TM (Address : 2316), bit3
0
)
64 –1
During outputting a piezoelectric buzzer
During stopping outputting a piezoelectric buzzer
Fig. 2.2.16 Control procedure [Piezoelectric buzzer output]
3806 GROUP USER’S MANUAL
2-16
APPLICATION
2.2 Timer
Timer XY mode register (Address : 23 16
)
b7
b0
TM
1 1 1 0
Timer Y operating mode bit : Event counter mode.
CNTR1 active edge switch bit : Count at falling edge
Timer Y count stop bit : Count stop
Set to “0” at starting to count.
Prescaler 12 (Address : 20 16
)
b7
b0
PRE12
T1
63
Timer 1 (Address : 2116
)
b0
b7
Set “division ratio – 1”
7
Prescaler Y (Address : 26 16
)
b7
b0
0
PREY
TY
Timer Y (Address : 2716
)
b7
b0
Set “255” to this register immediately before
counting pulse.
255
(After a certain time, this value is decreased by
the number of input pulses)
Interrupt control register 1 (Address : 3E 16
)
b7
b0
ICON1
IREQ1
1 0
Timer Y interrupt enable bit : Interrupt disabled
Timer 1 interrupt enable bit : Interrupt enabled
Interrupt request register 1 (Address : 3C 16
)
b7
b0
0
Judgment of Timer Y interrupt request bit
(When this bit is set to “1” at reading out
the count value of the Timer Y (address : 27 16),
256 pulses or more are input (at setting 255 to
the Timer Y).)
Fig. 2.2.18 Setting of related registers [Measurement of frequency]
3806 GROUP USER’S MANUAL
2-18
APPLICATION
2.2 Timer
Control procedure :
Figure 2.2.19 shows a control procedure.
●
X
:
This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
RESET
●
All interrupts : Disabled
Initialization
SEI
(Address : 2316
(Address : 2016
(Address : 2116
(Address : 2616
(Address : 2716
)
)
)
)
)
1110XXXX
64–1
8–1
1–1
256–1
1
2
●
TM
PRE12
T1
PREY
TY
ICON1
Timer Y : Event counter mode
(Count at falling edge of pulse input from CNTR 1 pin)
●
●
Set the division ratio so that the Timer 1 interrupt
occurs every 2 ms.
Timer 1 interrupt : Enabled
(Address : 3E16), bit6
(Address : 2316), bit7
0
●
●
TM
CLI
Timer Y count : Start
Interrupts : Enabled
~
~
Timer 1 interrupt processing routine
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
Push the register used in the interrupt
processing routine into the stack
1
●
When the count value is 256 or more, the
processing is performed as out of range.
IREQ1 (Address : 3C16), bit5?
0
●
●
Read the count value.
Store the count value in the accumulator (A).
(A)
TY (Address : 2716)
In range
<
<
●
214 (A) 228?
Compare the count value read with the
reference value.
●
Store the comparison result in flag Fpulse.
Out of range
0
Fpulse
1
Fpulse
●
●
Initialize the count value.
Set the Timer Y interrupt request bit to “0.”
(Address : 2716
(Address : 3C16), bit5
)
TY
IREQ1
256 – 1
0
Processing for a result of judgment
●
Pop registers which is pushed to stack.
Pop registers
RTI
Fig. 2.2.19 Control procedure [Measurement of frequency]
3806 GROUP USER’S MANUAL
2-19
APPLICATION
2.2 Timer
(5) Timer application example 4 : Measurement of pulse width of FG pulse generated by motor
Outline : The “H” level width of a pulse input to the P54/CNTR0 pin is counted by Timer X. An
underflow is detected by Timer X interrupt and an end of the input pulse “H” level is
detected by CNTR0 interrupt.
Specifications : • The “H” level width of FG pulse input to the P54/CNTR0 pin is counted by Timer
X.
(Example : When the clock frequency is 4.19 MHz, the count source would be 3.8
µs that is obtained by dividing the clock frequency by 16. Measure-
ment can be made up to 250 ms in the range of FFFF16 to 000016.)
Figure 2.2.20 shows a connection of the timer and a setting of the division ratio, and Figure 2.2.21
shows a setting of related registers.
Fixed
1/16
Prescaler X
1/256
Timer X
1/256
Timer X interrupt request bit
f(XIN) = 4.19 MHz
0 or 1
250 ms
0 : No interrupt request
1 : Interrupt request
Fig. 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width]
3806 GROUP USER’S MANUAL
2-20
APPLICATION
2.2 Timer
Timer XY mode register (Address : 23 16
)
b7
b0
TM
1 0 1 1
Timer X operating mode bits : Pulse width
measurement mode
CNTR0 active edge switch bit : Count “H” level width
Timer X count stop bit : Count stop
Set to “0” at starting to count.
Prescaler X (Address : 24 16
)
b7
b0
PREX
TX
255
Set “division ratio – 1”
Timer X (Address : 2516
)
b0
b7
255
Interrupt control register 1 (Address : 3E 16
)
b7
b0
1
ICON1
IREQ1
Timer X interrupt enable bit : Interrupt enabled
Interrupt request register (Address : 3C 16
)
b7
b0
0
Timer X interrupt request bit
(This bit is set to “1” at underflow of Timer X.)
Interrupt control register 2 (Address : 3F 16
)
b7
b0
1
ICON2
IREQ2
CNTR
0
interrupt enable bit : Interrupt enabled
Interrupt request register 2 (Address : 3D 16
)
b7
b0
0
CNTR
0
interrupt request bit
(This bit is set to “1” at completion of inputting
“H” level signal.)
Fig. 2.2.21 Setting of related registers [Measurement of pulse width]
3806 GROUP USER’S MANUAL
2-21
APPLICATION
2.2 Timer
Figure 2.2.22 shows a control procedure.
●
X : This bit is not used in this application.
RESET
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
SEI
●
All interrupts : Disabled
●
Timer X : Pulse width measurement mode
(Count “H” level width of pulse input from CNTR
Set the division ratio so that the Timer X interrupt
occurs every 250 ms.
0
pin.)
XXXX1011
2
(Address : 2316
(Address : 2416
(Address : 2516
(Address : 3E16), bit4
(Address : 3C16), bit4
(Address : 3F16), bit0
(Address : 3D16), bit0
)
)
)
TM
PREX
TX
ICON1
IREQ1
ICON2
IREQ2
●
256–1
256–1
1
0
1
0
●
●
Timer X interrupt : Enabled
CNTR0 interrupt : Enabled
0
(Address : 2316), bit3
TM
CLI
●
●
Timer X count : Start
Interrupts : Enabled
~
~
Timer X interrupt processing routine
●
Error occurs
Processing for error
RTI
CNTR
0
interrupt processing routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
●
Push the register used in the interrupt
processing routine into the stack.
(A)
PREX
●
A count value is read out and stored to RAM.
Result of pulse width measurement
low–order 8-bit
(A)
Inversion of (A)
TX
Result of pulse width measurement
high–order 8-bit
Inversion of (A)
●
Set the division ratio so that the Timer X
interrupt occurs every 250 ms.
PREX (Address : 2416
TX (Address : 2516
)
)
256 – 1
256–1
Pop registers
RTI
●
Pop registers which is pushed to stack .
Fig. 2.2.22 Control procedure [Measurement of pulse width]
3806 GROUP USER’S MANUAL
2-22
APPLICATION
2.3 Serial I/O
2.3 Serial I/O
2.3.1 Memory map of serial I/O
Transmit/Receive buffer register (TB/RB)
001816
001916
001A16
001B16
001C16
001D16
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Serial I/O2 control register (SIO2CON)
~
~
~
~
Serial I/O2 register (SIO2)
001F16
~
~
~
~
Interrupt edge selection register (INTEDGE)
003A16
~
~
~
~
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
003C16
003D16
003E16
003F16
Fig. 2.3.1 Memory map of serial I/O related registers
3806 GROUP USER’S MANUAL
2-23
APPLICATION
2.3 Serial I/O
2.3.2 Related registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816
]
At reset
Function
B
0
R W
A transmission data is written to or a receive data is read out
from this buffer register.
?
• At writing : a data is written to the Transmit buffer register.
• At reading : a content of the Receive buffer register is read out.
1
2
3
4
5
6
?
?
?
?
?
?
?
7
Fig. 2.3.2 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status reigster (SIO1STS) [Address : 1916]
At reset
Name
Transmit buffer empty flag
(TBE)
Function
0 : Buffer full
1 : Buffer empty
B
0
R W
✕
0
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
✕
✕
✕
✕
✕
✕
Receive buffer full flag (RBF)
1
2
3
4
5
6
0
0
0
0
0
0
Transmit shift register shift
completion flag (TSC)
0 : No error
1 : Overrun error
0 : No error
1 : Parity error
Overrun error flag (OE)
Parity error flag (PE)
0 : No error
1 : Framing error
0 : (OE) (PE) (FE) = 0
1 : (OE) (PE) (FE) = 1
Framing error flag (FE)
Summing error flag (SE)
Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is “0.”
✕
7
1
Fig. 2.3.3 Structure of Serial I/O1 status register
3806 GROUP USER’S MANUAL
2-24
APPLICATION
2.3 Serial I/O
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A16
]
At reset
Name
BRG count source
selection bit (CSS)
Function
B
0
R W
0 : f(XIN
1 : f(XIN)/4
)
0
Serial I/O1
synchronous clock
selection bit (SCS)
0
At selecting clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
At selecting UART
1
0 : BRG output divided by 16
1 : External clock input divided by 16
S
RDY1 output enable bit
0 : I/O port (P4 )
7
2
3
0
0
(SRDY)
1 : SRDY1 output pin
0 : Transmit buffer empty
1 : Transmit shift operating
completion
Transmit interrupt
source selection bit
(TIC)
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0
0
Transmit enable bit (TE)
4
5
6
7
Receive enable bit (RE)
Serial I/O1 mode
selection bit (SIOM)
0 : UART
1 : Clock synchronous serial I/O
0 : Serial I/O1 disabled
0
0
Serial I/O1 enable bit
(SIOE)
(P4
1 : Serial I/O1 enabled
(P4 –P4 Serial I/O function pin)
4–P47 : I/O port)
4
7
:
Fig. 2.3.4 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B16
]
At reset
Name
Function
R W
B
0
0 : 8 bits
1 : 7 bits
Character length
0
selection bit (CHAS)
Parity enable bit
(PARE)
Parity selection bit
(PARS)
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 1 stop bit
1
2
3
4
0
0
:
Stop bit length selection
bit (STPS)
P45/TxD P-channel
output disable bit
(POFF)
0
0
1 : 2 stop bits
In output mode
0 CMOS output
:
:
1 N-channel open-drain
output
5
6
7
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “1.”
✕
✕
✕
1
1
1
Fig. 2.3.5 Structure of UART control register
3806 GROUP USER’S MANUAL
2-25
APPLICATION
2.3 Serial I/O
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C16
]
At reset
B
Function
R W
A count value of Baud rate generator is set.
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
Fig. 2.3.6 Structure of Baud rate generator
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register (SIO2CON) [Address : 1D16
]
At reset
Name
Function
R W
B
0
b2 b1 b0
0
Internal synchronous
clock selection bits
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(XIN)/8
1 : f(XIN)/16
0 : f(XIN)/32
1 : f(XIN)/64
0 : f(XIN)/128
1 : f(XIN)/256
0
1
2
3
4
5
6
7
0
0
0
1
0
1
0
1
0
1
:
:
:
:
:
:
:
:
I/O port (P71, P72)
Serial I/O2 port selection bit
S
OUT2, SCLK2 output pin
I/O port (P7
3)
S
RDY2 output enable bit
0
S
RDY2 output pin
Transfer direction
selection bit
Serial I/O2 synchronous clock
LSB first
MSB first
0
0
External clock
Internal clock
selection bit
Nothing is allocated for this bit. This is write disabled bit. When
this bit is read out, the value is “0.”
✕
0
Fig. 2.3.7 Structure of Serial I/O2 control register
3806 GROUP USER’S MANUAL
2-26
APPLICATION
2.3 Serial I/O
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 1F16]
Function
At reset
R W
B
A shift register for serial transmission and reception.
At transmitting : Set a transmission data.
● At receiving : Store a reception data.
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
●
Fig. 2.3.8 Structure of Serial I/O2 register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16
]
At reset
Name
0 interrupt edge
selection bit
Function
R W
B
0
0
0
0
INT
0 : Falling edge active
1 : Rising edge active
INT interrupt edge
selection bit
1
0 : Falling edge active
1 : Rising edge active
1
2
3
4
5
✕
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
2 interrupt edge
selection bit
0
0
0
INT
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
INT interrupt edge
selection bit
INT interrupt edge
selection bit
3
0 : Falling edge active
1 : Rising edge active
4
0
0
6
7
✕
✕
Nothing is allocated for these bits. These are write disabled
bits. When these bits are read out, the values are “0.”
Fig. 2.3.9 Structure of Interrupt edge selection register
3806 GROUP USER’S MANUAL
2-27
APPLICATION
2.3 Serial I/O
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C16
]
At reset
Name
Function
0 : No interrupt request
1 : Interrupt request
R W
B
0
✻
INT
0
interrupt request bit
0
0 : No interrupt request
1 : Interrupt request
✻
✻
1
2
INT
1
interrupt request bit
0
0
0 : No interrupt request
1 : Interrupt request
Serial I/O1 receive interrupt
request bit
Serial I/O1 transmit interrupt
request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
✻
✻
✻
✻
✻
3
4
5
6
7
0
0
0
0
0
Timer X interrupt request bit
0 : No interrupt request
1 : Interrupt request
Timer Y interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
Timer 1 interrupt request bit
Timer 2 interrupt request bit
“0” is set by software, but not “1.”
✻
Fig. 2.3.10 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D16
]
At reset
Name
Function
0 : No interrupt request
1 : Interrupt request
R W
B
0
CNTR
0
interrupt request bit
✻
0
0 : No interrupt request
1 : Interrupt request
CNTR
1
interrupt request bit
✻
✻
✻
✻
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0 : No interrupt request
1 : Interrupt request
Serial I/O2 interrupt request bit
0 : No interrupt request
1 : Interrupt request
INT
INT
INT
2
interrupt request bit
interrupt request bit
interrupt request bit
0 : No interrupt request
1 : Interrupt request
3
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
4
✻
✻
AD conversion interrupt
request bit
1 :Interrupt request
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
✕
✻ “0” is set by software, but not “1.”
Fig. 2.3.11 Structure of Interrupt request register 2
3806 GROUP USER’S MANUAL
2-28
APPLICATION
2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16
]
At reset
Name
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
R W
B
0
INT
0
1
interrupt enable bit
0
0
0
0
0
0
0
0
INT
interrupt enable bit
1
2
3
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 receive interrupt
enable bit
Serial I/O1 transmit interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
4
5
6
7
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.3.12 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16]
At reset
Name
Function
0 : Interrupt disabled
1 : Interrupt enabled
R W
B
0
CNTR0 interrupt enable bit
0
0
0
0
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
CNTR1 interrupt enable bit
1
2
3
4
5
6
7
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O2 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
INT2 interrupt enable bit
INT3 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
INT4 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AD conversion interrupt
enable bit
Fix this bit to “0.”
Fig. 2.3.13 Structure of Interrupt control register 2
3806 GROUP USER’S MANUAL
2-29
APPLICATION
2.3 Serial I/O
2.3.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
There are connection examples using a clock synchronous serial I/O mode.
Figure 2.3.14 shows connection examples of a peripheral IC equipped with the CS pin.
(2) Transmission and reception
(1) Only transmission
(using the R
X
D pin as an I/O port)
CS
Port
Port
CS
CLK
IN
S
CLK
S
CLK
CLK
DATA
TXD
TXD
RXD
OUT
3806 group
Peripheral IC
(OSD controller etc.)
3806 group
Peripheral IC
(E2 PROM etc.)
(3) Transmission and reception
(Pins R D and T D are connected)
(4) Connecting ICs
Port
X
X
(Pins IN and OUT in peripheral IC
are connected)
Port
CS
CS
S
CLK
CLK
IN
S
CLK
CLK
TXD
T
X
X
D
D
IN
RXD
OUT
OUT
R
3806 group ✻1
Peripheral IC ✻2
Peripheral IC 1
Port
(E2 PROM etc.)
3806 group
CS
✻
1: Select an N-channel open-drain output control of T
X
D pin.
CLK
IN
2: Use such OUT pin of peripheral IC as an N-channel open-
drain output in high impedance during receiving data.
OUT
“Port” is an output port controlled by software.
Notes1:
2:
Use SOUT and SIN instead of TXD and RXD in the
Peripheral IC 2
serial I/O2.
Fig. 2.3.14 Serial I/O connection examples (1)
3806 GROUP USER’S MANUAL
2-30
APPLICATION
2.3 Serial I/O
2.3.4 Setting of serial I/O transfer data format
A clock synchronous or clock asynchronous (UART) is selected as a data format of the serial I/O1. The
serial I/O2 operates in a clock synchronous.
Figure 2.3.16 shows a setting of serial I/O transfer data format.
1ST-8DATA-1SP
ST
LSB
MSB
SP
1ST-7DATA-1SP
ST
LSB
MSB
SP
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
SP
SP
1ST-7DATA-1PAR-1SP
ST
LSB
MSB PAR
UART
1ST-8DATA-2SP
ST
LSB
MSB
2SP
1ST-7DATA-2SP
ST
LSB
MSB
2SP
MSB
PAR
Serial
I/O1
1ST-8DATA-1PAR-2SP
ST
LSB
PAR
2SP
2SP
1ST-7DATA-1PAR-2SP
ST
LSB
MSB
Clock synchronous
Serial I/O
LSB first
ST : Start bit
SP : Stop bit
PAR : Parity bit
LSB first
MSB first
Clock synchronous
Serial I/O
Serial
I/O2
Fig. 2.3.16 Setting of Serial I/O transfer data format
3806 GROUP USER’S MANUAL
2-32
APPLICATION
2.3 Serial I/O
2.3.5 Serial I/O application examples
(1) Communication using a clock synchronous serial I/O (transmit/receive)
____
Outline : 2-byte data is transmitted and received through the clock synchronous serial I/O. The SRDY
signal is used for communication control.
Figure 2.3.17 shows a connection diagram, and Figure 2.3.18 shows a timing chart.
Transmitting side
Receiving side
SRDY1
P42/INT0
SCLK
S
CLK1
RXD
TXD
3806 group
3806 group
Fig. 2.3.17 Connection diagram [Communication using a clock synchronous serial I/O]
Specifications : • The Serial I/O1 is used (clock synchronous serial I/O is selected)
• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
_____
• The SRDY1 (receivable signal) is used.
_____
• The receiving side outputs the SRDY1 signal at intervals of 2 ms (generated by
timer), and 2-byte data is transferred from the transmitting side to the receiving
side.
• • • •
S
RDY1
• • • •
S
CLK1
TXD
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
• • • •
2 ms
Fig. 2.3.18 Timing chart [Communication using a clock synchronous serial I/O]
3806 GROUP USER’S MANUAL
2-33
APPLICATION
2.3 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 19 16
)
b7
b0
SIO1STS
Transmit buffer empty flag
• Check to be transferred data from the Transmit buffer register to
Transmit shift register.
• Writable the next transmission data to the Transmit buffer register
at being set to “1.”
Transmit shift register shift completion flag
Check a completion of transmitting 1-byte data with this flag
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A 16
)
b7
b0
SIO1CON 1 1 0 1
0 0
BRG counter source selection bit : f(X IN
)
Serial I/O1 synchronous clock selection bit : BRG/4
Transmit enable bit
Receive enable bit
:
Transmit enabled
:
Receive disabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit Serial I/O1 enabled
:
Baud rate generator (Address : 1C 16
)
b7
b0
Set “division radio – 1”
BRG
7
Interrupt edge selection register (Address : 3A 16
)
b7
b0
INTEDGE
0
INT0 active edge selection bit : Select INT0 falling edge
Fig. 2.3.19 Setting of related registers at a transmitting side [Communication using a clock
synchronous serial I/O]
3806 GROUP USER’S MANUAL
2-34
APPLICATION
2.3 Serial I/O
Receiving side
Serial I/O1 status register (Address : 19 16
)
b7
b0
SIO1STS
Receive buffer full flag
Check a completion of receiving 1-byte data with this flag.
“1” : At completing to receive
“0” : At reading out a receive buffer
Serial I/O1 control register (Address : 1A 16
)
b7
b0
SIO1CON
1
1 1 1
1 1
Serial I/O1 synchronous clock selection bit : External clock
S
RDY1 output enable bit
Transmit enable bit Transmit enabled
Set this bit to “1,” using SRDY1 output.
Receive enable bit Receive enabled
Serial I/O1 mode selection bit Clock synchronous serial I/O
Serial I/O1 enable bit Serial I/O1 enabled
: Use the SRDY1 output
:
:
:
:
Fig. 2.3.20 Setting of related registers at a receiving side [Communication using a clock
synchronous serial I/O]
3806 GROUP USER’S MANUAL
2-35
APPLICATION
2.3 Serial I/O
Control procedure : Figure 2.3.21 shows a control procedure at a transmitting side, and Figure
2.3.22 shows a control procedure at a receiving side.
●X : This bit is not used in this application.
RESET
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
1101XX00
2
(Address : 1A16
(Address : 1C16
)
)
SIO1CON
BRG
INTEDGE
8—1
0
(Address : 3A16), bit0
0
IREQ1 (Address:3C16), bit0?
• Detect INT0 falling edge
1
IREQ1 (Address : 3C16), bit0
0
• Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
TB/RB (Address : 1816
)
0
SIO1STS (Address : 1916), bit0?
1
• Check to be transfered data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
• Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The second byte of
a transmission data
TB/RB (Address : 1816
)
0
0
• Check to be transfered data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
SIO1STS (Address : 1916), bit0?
1
• Check a shift completion of the Transmit shift register
(Transmit shift register shift completion flag)
SIO1STS (Address : 1916), bit2?
1
Fig. 2.3.21 Control procedure at a transmitting side [Communication using a clock synchronous
serial I/O]
3806 GROUP USER’S MANUAL
2-36
APPLICATION
2.3 Serial I/O
●X : This bit is not used in this application.
RESET
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
SIO1CON (Address : 1A16
1111X11X
2
)
N
Pass 2 ms?
Y
• An interval of 2 ms is generated by a timer.
• SRDY1 output
RDY1 signal is output by writing data to
TB/RB (Address : 1816
)
Dummy data
S
the TB/RB.
Using the SRDY1 , the transmit enabled bit
(bit4) of the SIO1CON is set to “1.”
0
SIO1STS (Address : 1916), bit1?
• Check a completion of receiving
(Receive buffer full flag)
1
• Receive the first byte data.
A Receive buffer full flag is set to “0” by reading data.
Read out reception data from
TB/RB (Address : 1816
)
• Check a completion of receiving
(Receive buffer full flag)
0
SIO1STS (Address : 1916), bit1?
1
• Receive the second byte data.
A Receive buffer full flag is set to “0” by reading data.
Read out reception data from
TB/RB (Address : 1816
)
Fig. 2.3.22 Control procedure at a receiving side [Communication using a clock synchronous
serial I/O]
3806 GROUP USER’S MANUAL
2-37
APPLICATION
2.3 Serial I/O
(2) Output of serial data (control of a peripheral IC)
Outline : 4-byte data is transmitted and received through the clock synchronous serial I/O. The CS
signal is output to a peripheral IC through the port P53.
CS
CS
P5
3
P53
CS
CS
CLK
DATA
CLK
DATA
S
CLK1
SCLK2
CLK
DATA
CLK
DATA
TX
D
SOUT2
Peripheral IC
3806 group
Peripheral IC
3806 group
(1) Example for using Serial I/O1
(2) Example for using Serial I/O2
Fig. 2.3.23 Connection diagram [Output of serial data]
Specifications : • The Serial I/O is used. (clock synchronous serial I/O is selected)
• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• The Serial I/O1 interrupt is not used.
___
• The Port P53 is connected to the CS pin (“L” active) of the peripheral IC for a
transmission control (the output level of the port P53 is controlled by software).
Figre 2.3.24 shows an output timing chart of serial data.
CS
CLK
DO
0
DO
1
DO
2
DO3
DATA
Note: The SOUT2 pin is in high impedance after completing to transfer data, using the serial I/O2.
Fig. 2.3.24 Timing chart [Output of serial data]
3806 GROUP USER’S MANUAL
2-38
APPLICATION
2.3 Serial I/O
Figure 2.3.25 shows a setting of serial I/O1 related registers, and Figure 2.3.26 shows a setting of
serial I/O1 transmission data.
Serial I/O1 control register (Address : 1A 16)
b7
b0
SIO1CON
1 1 0 1 1 0 0 0
BRG count source selection bit : f(X IN)
Serial I/O1 synchronous clock selection bit : BRG/4
SRDY1 output enable bit : Not use the
SRDY1 signal output function
Transmit interrupt source selection bit : Transmit shift operating completion
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Clock synchronous serial I/O
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B 16)
b7 b0
0
UARTCON
P45/TXD P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C 16)
b7 b0
7
BRG
Set “division ratio – 1”
Interrupt control register 1 (Address : 3E 16)
b7 b0
ICON1
0
Serial I/O1 transmit interrupt enable bit : Interrupt disabled
Interrupt request register 1 (Address : 3C 16)
b7 b0
IREQ1
0
Serial I/O1 transmit interrupt request bit
Using this bit, check the completion of
transmitting 1-byte base data.
“1” : Transmit shift completion
Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data]
Transmit/Receive buffer register (Address : 1816
)
b7
b0
Set a transmission data.
TB/RB
Check that transmission of the previous data is
completed before writing data (bit 3 of the
Interrupt request register 1 is set to “1”).
Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data]
3806 GROUP USER’S MANUAL
2-39
APPLICATION
2.3 Serial I/O
Control procedure : When the registers are set as shown in Fig. 2.3.25, the Serial I/O1 can transmit
1-byte data simply by writing data to the Transmit buffer register.
Thus, after setting the CS signal to “L,” write the transmission data to the
Receive buffer register on a 1-byte base, and return the CS signal to “H” when
the desired number of bytes have been transmitted.
Figure 2.3.27 shows a control procedure of serial I/O1.
●X : This bit is not used in this application.
RESET
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
SIO1CON
UARTCON
BRG (Address : 1C16
ICON1(Address : 3E16), bit3
P5
(Address : 0A16), bit3
P5D (Address : 0B16
11011000
2
(Address : 1A16
)
●
●
●
Set the Serial I/O1.
(Address : 1B16), bit4
0
8–1
0
Serial I/O1 transmit interrupt : Disabled
)
Set the CS signal output port.
(“H” level output)
1
XXXX1XXX
2
)
●
Set the CS signal output level to “L.”
P5 (Address : 0A16), bit3
0
●
Set the Serial I/O1 transmit interrupt
request bit to “0.”
IREQ1 (Address : 3C16), bit3
0
a transmission
data
●
TB/RB (Address : 1816
)
Write a transmission data.
(start to transmit 1-byte data)
0
●
IREQ1 (Address : 3C16), bit3?
1
Check the completion of transmitting 1-
byte data.
●
●
N
Use any of RAM area as a counter for
counting the number of transmitted bytes.
Check that transmission of the target
number of bytes has been completed.
Complete to transmit data?
Y
●
Return the CS signal output level to “H”
when transmission of the target number of
bytes is completed.
P5 (Address : 0A16), bit3
1
Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data]
3806 GROUP USER’S MANUAL
2-40
APPLICATION
2.3 Serial I/O
Figure 2.3.28 shows a setting of serial I/O2 related registers, and Figure 2.3.29 shows a setting of
serial I/O2 transmission data.
Serial I/O2 control register (Address : 1D16
)
b7
b0
SIO2CON
1 0 0 1 0 1 0
Internal synchronous clock selection bits : f(XIN)/32
Serial I/O2 port selection bit :Use the Serial I/O2
S
RDY2 output enable bit : Not use the SRDY2 signal output function
Transfer direction selection bit : LSB first
Serial I/O2 synchronous clock selection bit : Internal clock
Interrupt control register 2 (Address : 3F16
)
b7
b0
ICON2
IREQ2
0
Serial I/O2 interrupt enable bit : Interrupt disabled
Interrupt request register 2 (Address : 3D16
)
b7
b0
0
Serial I/O2 interrupt request bit
Using this bit, check the completion of
transmitting 1-byte base data.
“1” : Transmit completion
Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data]
Serial I/O2 register (Address : 1F16
)
b7
b0
Set a transmission data.
SIO2
Check that transmission of the previous data is
completed before writing data (bit 2 of the Interrupt
request register 2 is set to “1”).
Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data]
3806 GROUP USER’S MANUAL
2-41
APPLICATION
2.3 Serial I/O
Control procedure : When the registers are set as shown in Fig. 2.3.28, the Serial I/O2 can transmit
1-byte data simply by writing data to the Serial I/O2 register.
Thus, after setting the CS signal to “L,” write the transmission data to the Serial
I/O1 register on a 1-byte base, and return the CS signal to “H” when the desired
number of bytes have been transmitted.
Figure 2.3.30 shows a control procedure of serial I/O2.
●X : This bit is not used in this application.
RESET
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
SIO2CON(Address : 1D16
)
2
●
X1001010
Set the Serial I/O2 control register.
Serial I/O2 interrupt : Disabled
Set the CS signal output port.
(“H” level output)
ICON2
P5
(Address : 3F16), bit2
(Address : 0A16), bit3
(Address : 0B16)
0
1
●
●
P5D
XXXX
1XXX2
●
Set the CS signal output level to “L.”
P5 (Address : 0A16), bit3
0
●
Set the Serial I/O2 interrupt
request bit to “0.”
IREQ2 (Address : 3D16), bit2
0
●
a transmission
data
SIO2 (Address : 1F16
)
Write a transmission data.
(start to transmit 1-byte data)
0
●
Check the completion of transmitting 1-
byte data.
IREQ2 (Address : 3D16), bit2?
1
●
●
Use any of RAM area as a counter for
counting the number of transmitted bytes.
Check that transmission of the target
number of bytes has been completed.
N
Complete to transmit data?
Y
●
Return the CS signal output level to “H”
when transmission of the target number of
bytes is completed.
P5 (Address : 0A16), bit3
1
Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data]
3806 GROUP USER’S MANUAL
2-42
APPLICATION
2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of a specified number of bytes)
between microcomputers
[without using an automatic transfer]
Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock
and the data between the transmitting and receiving sides may be lost because of noise
included in the synchronizing clock. Thus, it is necessary to be corrected constantly. This
“heading adjustment” is carried out by using the interval between blocks in this example.
SCLK
SCLK
RXD
TXD
T
XD
RXD
Slave unit
Master unit
Note: Use SOUT and SIN instead of TXD and RXD in the serial I/O2.
Fig. 2.3.31 Connection diagram [Cyclic transmission or reception of block data between
microcomputers]
Specifications : • The serial I/O1 is used (clock synchronous serial I/O is selected).
• Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32)
• Byte cycle: 488 µs
• Number of bytes for transmission or reception : 8 byte/block
• Block transfer cycle : 16 ms
• Block transfer period : 3.5 ms
• Interval between blocks : 12.5 ms
• Heading adjustive time : 8 ms
Limitations of the specifications
1. Reading of the reception data and setting of the next transmission data must be completed
within the time obtained from “byte cycle – time for transferring 1-byte data” (in this example,
the time taken from generating of the Serial I/O1 receive interrupt request to generating of the
next synchronizing clock is 431 µs).
2. “Heading adjustive time < interval between blocks” must be satisfied.
3806 GROUP USER’S MANUAL
2-43
APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown below. In the slave unit, when a
synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is
processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.3.33 shows a setting of related registers.
D0
D1
D2
D7
D0
Byte cycle
Block transfer period
Block transfer cycle
Interval between blocks
Heading adjustive time
Processing for heading adjustment
Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers]
Master unit
Slave unit
Serial I/O1 control register (Address : 1A16)
Serial I/O1 control register (Address : 1A16)
b7 b0
b7
b0
SIO1CON
1 1 1 1 1 0 0 0
1 1
0 1
1 1
SIO1CON
BRG count source : f(XIN)
Not be effected by
external clock
Synchronous clock : External clock
Synchronous
clock : BRG/4
Not use the SRDY1 output
Not use the SRDY1 output
Transmit interrupt source :
Transmit shift operating completion
Not use the serial I/O1 transmit interrupt
Transmit enabled
Receive enabled
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O1 enabled
Clock synchronous serial I/O
Serial I/O1 enabled
Both of units
UART control register (Address : 1B16)
b7 b0
UARTCON
0
P45/TXD pin : CMOS output
Baud rate generator (Address : 1C16)
b7 b0
BRG
7
Set “division ratio – 1”
Fig. 2.3.33 Setting of related registers [Cyclic transmission or reception of block data between
microcomputers]
3806 GROUP USER’S MANUAL
2-44
APPLICATION
2.3 Serial I/O
Control procedure :
Control in the master unit
After a setting of the related registers is completed as shown in Figure 2.3.33, in the master unit
transmission or reception of 1-byte data is started simply by writing transmission data to the
Transmit buffer register.
To perform the communication in the timing shown in Figure 2.3.32, therefore, take the timing into
account and write transmission data. Read out the reception data when the Serial I/O1 transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the Transmit
buffer register.
A processing example in the master unit using timer interrupts is shown below.
Interrupt processing routine
executed every 488 µs
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Push the register used in the interrupt
processing routine into the stack.
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
N
Within a block transfer period?
●
Generate a certain block interval by
using a timer or other functions.
Y
●
Check the block interval counter and
determine to start of a block transfer.
Count a block interval counter
Read a reception data
N
Y
Complete to transfer a block?
Start a block transfer?
Y
N
Write the first transmission data
(first byte) in a block
Write a transmission data
●
Pop registers
RTI
Pop registers which is pushed to stack.
Fig. 2.3.34 Control in the master unit
3806 GROUP USER’S MANUAL
2-45
APPLICATION
2.3 Serial I/O
Control in the slave unit
After a setting of the related registers is completed as shown in Figure 2.3.33, the slave unit becomes the
state which is received a synchronizing clock at all times, and the Serial I/O1 receive interrupt request bit
is set to “1” every time an 8-bit synchronous clock is received.
By the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to the
Transmit buffer register after received data is read out.
However, if no serial I/O1 receive interrupt occurs for more than a certain time (head adjustive time), the
following processing will be performed.
1. The first 1 byte data of the transmission data in the block is written into the Transmission buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.3.35 shows the control in the slave unit using a serial I/O1 receive interrupt and any timer interrupt
(for head adjustive).
Serial I/O1 receive interrupt
processing routine
Timer interrupt processing
routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
●
Push the register used in
the interrupt processing
routine into the stack.
Push the register used in
the interrupt processing
routine into the stack.
●
Check the received byte
counter to judge if a block
has been transfered.
Heading adjustive counter – 1
N
Within a block transfer period?
Y
N
Heading adjustive
counter = 0?
Read a reception data
Y
Write the first transmission data
(first byte) in a block
A received byte counter +1
A received byte counter
0
Y
A received byte counter
N
≥ 8?
●
Pop registers
RTI
Pop registers which is
pushed to stack.
Write any data (FF16)
Write a transmission data
Heading adjustive
counter
Initialized
value (Note 3)
●
Pop registers which is
pushed to stack.
Pop registers
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
RTI
3: In this example, set the value which is equal to the
heading adjustive time divided by the timer interrupt
cycle as the initialized value of the heading adjustive
counter.
For example: When the heading adjustive time is 8 ms
and the timer interrupt cycle is 1 ms, set
8 as the initialized value.
Fig. 2.3.35 Control in the slave unit
3806 GROUP USER’S MANUAL
2-46
APPLICATION
2.3 Serial I/O
(4) Communication (transmit/receive) using an asynchronous serial I/O (UART)
Point : 2-byte data is transmitted and received through an asynchronous serial I/O.
The port P40 is used for communication control.
Figure 2.3.36 shows a connection diagram, and Figure 2.3.37 shows a timing chart.
Transmitting side
Receiving side
P40
P40
TXD
XD
R
3806 group
3806 group
Fig. 2.3.36 Connection diagram [Communication using UART]
Specifications : • The Serial I/O1 is used (UART is selected).
• Transfer bit rate : 9600 bps (f(XIN) = 4.9152 MHz is divided by 512)
• Communication control using port P40
(The output level of the port P40 is controlled by softoware.)
• 2-byte data is transferred from the transmitting side to the receiving side at inter-
vals of 10 ms (generated by timer).
P4
0
…
TXD
…
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D0
ST
ST
ST
SP(2)
SP(2)
10 ms
Fig. 2.3.37 Timing chart [Communication using UART]
3806 GROUP USER’S MANUAL
2-47
APPLICATION
2.3 Serial I/O
Table 2.3.1 shows setting examples of Baud rate generator (BRG) values and transfer bit rate values,
Figure 2.3.38 shows a setting of related registers at a transmitting side, and Figure 2.3.39 shows a
setting of related registers at a receiving side.
Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values
Transfer bit BRG count
rate(bps) source
at f(XIN) = 4.9152 MHZ
at f(XIN) = 7.3728 MHZ
at f(XIN) = 8 MHZ
BRG setting value Actual time (bps) BRG setting value Actual time (bps) BRG setting value Actual time (bps)
(Note 2)
(Note 1)
600
1200
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)
127(7F16)
63(3F16)
31(1F16)
15(0F16)
7(0716)
600.00
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
191(BF16)
95(5F16)
47(2F16)
23(1716)
11(0B16)
5(0516)
600.00
1200.00
2400.00
4800.00
9600.00
19200.00
38400.00
76800.00
207(CF16)
103(6716)
51(3316)
25(1916)
12(0C16)
5(0516)
600.96
1201.92
2403.85
4807.69
9615.38
20833.33
41666.67
83333.33
31250.00
62500.00
2400
4800
9600
19200
38400
76800
31250
62500
3(0316)
1(0116)
2(0216)
2(0216)
3(0316)
5(0516)
5(0516)
f(XIN)
15(0F16)
7(0716)
f(XIN)
Notes 1: Equation of transfer bit rate
f(XIN)
Transfer bit rate (bps) =
(BRG setting value + 1) ✕ 16 ✕ m
m: when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0,” a value
of m is 1.
when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “1,” a value
of m is 4.
2: A BRG count source is selected by bit 0 of the Serial I/O1 control register (Address : 1A16).
3806 GROUP USER’S MANUAL
2-48
APPLICATION
2.3 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 19 16
)
b7
b0
SIO1STS
Transmit buffer empty flag
•
Check to be transferred data from the Transmit buffer
register to the Transmit shift register.
•
Writable the next transmission data to the Transmit buffer
register at being set to “1.”
Transmit shift register shift completion flag
Check a completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A 16
)
b7
b0
0 0
1
1
1
0 0
SIO1CON
BRG count source selection bit : f(XIN)/4
Serial I/O1 synchronous clock selection bit : BRG/16
S
RDY1 output enable bit : Not use SRDY1 output
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O1 mode selection bit : Asynchronous serial I/O(UART)
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B 16
)
b7
b0
0 1
0
UARTCON
0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
P4
5/T
X
D P-channel output disable bit : CMOS output
Baud rate generator (Address : 1C 16
)
b7
b0
f(XIN
)
7
BRG
Set
–1
Transfer bit rate ✕ 16 ✕ m ✻
when bit 0 of the Serial I/O1 control register (Address : 1A 16) is set to
“0,” a value of m is 1.
✻
when bit 0 of the Serial I/O1 control register (Address : 1A 16) is set to
“1,” a value of m is 4.
Fig. 2.3.38 Setting of related registers at a transmitting side [Communication using UART]
3806 GROUP USER’S MANUAL
2-49
APPLICATION
2.3 Serial I/O
Receiving side
Serial I/O1 status register (Address : 19 16
)
b0
b7
SIO1STS
Receive buffer full flag
Check a completion of receiving 1-byte data with this flag.
“1” : at completing to receive
“0” : at reading out a content of the Receive buffer register
Overrun error flag
“1” : when data are ready to be transferred to the
Receive shift register in the state of storing data
into the Receive buffer register.
Parity error flag
“1” : when parity error occurs at enabled parity.
Framing error flag
“1” : when data can not be received at the timing of
setting a stop bit.
Summing error flag
“1” : when even one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O1 control register (Address : 1A 16
)
b0
b7
SIO1CON
1
0 1
0
0
0 1
BRG count source selection bit : f(X IN)/4
Serial I/O1 synchronous clock selection bit : BRG/16
S
RDY1 output enable bit : Not use SRDY1 out
Transmit enable bit : Transmit disabled
Receive enable bit : Receive enabled
Serial I/O1 mode selection bit : Asynchronous serial I/O(UART)
Serial I/O1 enable bit : Serial I/O1 enabled
UART control register (Address : 1B 16
)
b0
b7
1
0
0
UARTCON
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 1C 16
)
b7
b0
f(XIN
)
BRG
7
Set
–1
Transfer bit rate ✕ 16 ✕ m ✻
when bit 0 of the Serial I/O1 control register (Address : 1A 16) is set to
“0,” a value of m is 1.
✻
when bit 0 of the Serial I/O1 control register (Address : 1A 16) is set to
“1,” a value of m is 4.
Fig. 2.3.39 Setting of related registers at a receiving side [Communication using UART]
3806 GROUP USER’S MANUAL
2-50
APPLICATION
2.3 Serial I/O
Control procedure : Figure 2.3.40 shows a control procedure at a transmitting side, and Figure 2.3.41
shows a control procedure at a receiving side.
:
●X This bit is not used in this application.
RESET
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
(Address : 1A16
(Address : 1B16
(Address : 1C16
)
)
)
1001X001
00001000
–1
(Address : 0816), bit0
2
SIO1CON
UARTCON
BRG
P4
P4D
2
8
0
•
•
Set port P40 for a communication control.
(Address : 0916
)
XXXXXXX1
2
N
Pass 10 ms?
Y
An interval of 10 ms is generated by a timer.
Start of communication.
1
•
•
P4 (Address : 0816), bit0
Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
TB/RB (Address : 1816)
•
Check to be transferred data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
0
SIO1STS (Address : 1916), bit0?
1
•
•
Write a transmission data
The Transmit buffer empty flag is set to “0”
by this writing.
The second byte of
a transmission data
TB/RB (Address : 1816)
Check to be transferred data from the Transmit
buffer register to the Transmit shift register.
(Transmit buffer empty flag)
0
0
SIO1STS (Address : 1916), bit0?
1
•
•
Check a shift completion of the Transmit shift register.
(Transmit shift register shift completion flag)
SIO1STS (Address : 1916), bit2?
1
P4 (Address : 0816), bit0
End of communication
0
Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART]
3806 GROUP USER’S MANUAL
2-51
APPLICATION
2.3 Serial I/O
●X
:
This bit is not used in this application.
RESET
Set it to “0” or “1.” It’s value can be disregarded.
Initialization
1010X001
2
SIO1CON (Address : 1A16
)
)
)
00001000
2
UARTCON
BRG
(Address : 1B16
(Address : 1C16
(Address : 0916
8–1
XXXXXXX0
P4D
)
2
0
•
•
Check a completion of receiving.
(Receive buffer full flag)
SIO1STS (Address : 1916), bit1?
1
Receive the first 1 byte data
A Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 1816
)
•
Check an error flag.
1
0
SIO1STS (Address : 1916), bit6?
0
•
•
Check a completion of receiving.
(Receive buffer full flag)
SIO1STS (Address : 1916), bit1?
1
Receive the second byte data
A Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 1816
)
•
Check an error flag.
1
SIO1STS (Address : 1916), bit6?
0
Processing for error
1
P4 (Address : 0816), bit0?
0
0000X001
1010X001
2
2
SIO1CON (Address : 1A16
SIO1CON (Address : 1A16
)
)
•
Countermeasure for a bit slippage
Fig. 2.3.41 Control procedure at a receiving side [Communication using UART]
3806 GROUP USER’S MANUAL
2-52
APPLICATION
2.4 A-D converter
2.4 A-D converter
2.4.1 Memory map of A-D conversion
AD/DA control register (ADCON)
003416
003516
A-D conversion register (AD)
~
~
~
~
Interrupt request register 2 (IREQ2)
003D16
~
~
~
~
003F16 Interrupt control register 2 (ICON2)
Fig. 2.4.1 Memory map of A-D conversion related registers
3806 GROUP USER’S MANUAL
2-53
APPLICATION
2.4 A-D converter
2.4.2 Related registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register (ADCON) [Address : 34 16
]
At reset
B
Name
Function
R W
b2 b1 b0
0
Analog input pin selection bits
0
1
2
3
0 0 0 : P6
0
1
2
3
4
5
6
7
/AN
0
1
2
3
4
5
6
7
0 0 1 : P6
0 1 0 : P6
0 1 1 : P6
1 0 0 : P6
1 0 1 : P6
1 1 0 : P6
1 1 1 : P6
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
0
1
0 : Conversion in progress
1 : Conversion completed
AD conversion completion bit
✕
✕
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
4
5
0
0
0 : DA
1 : DA
1
1
output disable
output enable
0
DA
1
output enable bit
6
0 : DA
1 : DA
2
2
output disabled
output enabled
DA
2
output enable bit
0
7
Fig. 2.4.2 Structure of AD/DA control register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address : 35 16
]
At reset
R W
✕
B
Function
The read-only register which A-D conversion results are stored.
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
✕
✕
✕
✕
✕
✕
✕
Fig. 2.4.3 Structure of A-D conversion register
3806 GROUP USER’S MANUAL
2-54
APPLICATION
2.4 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D 16
]
At reset
R W
B
0
Name
interrupt request bit
Function
0 : No interrupt request
1 : Interrupt request
CNTR
CNTR
0
1
0
0
0
0
✻
✻
✻
✻
interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
1
2
3
Serial I/O2 interrupt request bit
INT
2
interrupt request bit
0 : No interrupt request
1 : Interrupt request
INT
INT
3
4
interrupt request bit
interrupt request bit
4
5
6
7
0
0
0
0
✻
✻
✻
✕
0 : No interrupt request
1 : Interrupt request
AD conversion interrupt
request bit
0 : No interrupt request
1 : Interrupt request
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
✻
“0” is set by software, but not “1.”
Fig. 2.4.4 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F 16
]
At reset
Name
interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
R W
B
0
CNTR
CNTR
0
1
0
0 : Interrupt disabled
1 : Interrupt enabled
interrupt enable bit
1
2
3
4
5
6
7
0
0
0
0
0
0
Serial I/O2 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
INT
INT
INT
2
3
4
interrupt enable bit
interrupt enable bit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
AD conversion interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fix this bit to “0.”
0
Fig. 2.4.5 Structure of Interrupt control register 2
3806 GROUP USER’S MANUAL
2-55
APPLICATION
2.4 A-D converter
2.4.3 A-D conversion application example
Conversion of Analog input voltage
Outline : The analog input voltage input from the sensor is converted into digital values.
Figure 2.4.6 shows a connection diagram, and Figure 2.4.7 shows a setting of related registers.
Sensor
P6
0/AN
0
3806 group
Fig. 2.4.6 Connection diagram [Conversion of Analog input voltage]
Specifications : • The analog input voltage input from the sensor is converted into digital values.
• The P60/AN0 pin is used as an analog input pin.
AD/DA control register (Address : 3416)
0 0 0 0
ADCON
Analog input pin selection bits : Select the P6
0
/AN pin
0
AD conversion completion bit : Conversion in progress
A-D conversion register (Address : 3516)
(read-only)
AD
Store a result of A-D conversion ( Note)
Note: Read out a result of A-D conversion after bit 3 of the
AD/DA control register (ADCON) is set to “1.”
Fig. 2.4.7 Setting of related registers [Conversion of Analog input voltage]
3806 GROUP USER’S MANUAL
2-56
APPLICATION
2.4 A-D converter
Control procedure : By setting the related registers as shown in Figure 2.4.7, the analog input
voltage input from the sensor are converted into digital values.
~
~
•
•
Select the P6
Start A-D conversion.
0
/AN pin as an analog input pin.
0
ADCON (Address : 3416), bit0 – bit2
ADCON (Address : 3416), bit3
000
0
2
0
ADCON (Address : 3416), bit3?
1
•
•
Check the completion of A-D conversion.
Read out the conversion result.
Read out AD (Address : 3516
)
~
~
Fig. 2.4.8 Control procedure [Conversion of Analog input voltage]
3806 GROUP USER’S MANUAL
2-57
APPLICATION
2.5 Processor mode
2.5 Processor mode
2.5.1 Memory map of processor mode
CPU mode register (CPUM)
003B16
Fig. 2.5.1 Memory map of processor mode related register
2.5.2 Related register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address : 3B16
]
At reset
Name
B
Function
R W
0
0
1
2
Processor mode bits
00 :Single-chip mode
01 :Memory expansion mode
10 :Microprocessor mode
11 :Not available
✻
0 :0 page
1 :1 page
0
Stack page selection bit
3
4
5
6
7
0
✕
✕
✕
✕
✕
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
0
0
0
0
✻An initial value of bit 1 is determined by a level of the CNVSS pin.
Fig. 2.5.2 Structure of CPU mode register
3806 GROUP USER’S MANUAL
2-58
APPLICATION
2.5 Processor mode
2.5.3 Processor mode application examples
____
(1) Application example of memory expansion in the case where the ONW (One-Wait)
function is not used
Outline : The external memory is accessed in the microprocessor mode.
At f(XIN) = 8 MHz, an available RAM is given by the following :
___
• OE access time : ta (OE) ≤ 50 ns
• Setup time for writing data : tsu (D) ≤ 65 ns
For example, the M5M5256BP-10 whose address access is 100 ns is available.
Figure 2.5.3 shows an expansion example of a 32K byte ROM and a 32K byte RAM.
3806 group
CNVSS
AD15
ONW
M5M27C256AK-10
CE
M5M5256BP-10
S
2
P3
P4
P5
P6
P7
P8
0, P31
74F04
AD14
AD
15
8
A
0–A14
A
0–A14
0
EPROM
SRAM
8
8
8
8
DB
DB
0
7
8
D
0–D
7
DQ
1–DQ
8
Memory map
OE
OE
W
000016
External RAM area
(M5M5256BP)
000816
004016
044016
SFR area
RD
Ineternal RAM area
WR
External RAM area
(M5M5256BP)
800016
FFFF16
8MHz
VCC = 5.0V ± 10 %
External ROM area
(M5M27C256AK)
Fig. 2.5.3 Expansion example of ROM and RAM
3806 GROUP USER’S MANUAL
2-59
APPLICATION
2.5 Processor mode
Figure 2.5.4, Figure 2.5.5 and Figure 2.5.6 shows a standard timing at 8 MHz (No-Wait).
A
0
–A
7
Address (low-order)
Address (high-order)
(Port P0)
A8–A14
(Port P1)
S
(A15)
t
WL(RD)
td(AH–RD)
125 ns - 35 ns (min)
OE
(RD of 3806)
125 ns - 10 ns (min)
ta(OE)
50 ns (max)
Data
DQ1–DQ8
(Port P2)
tsu(DB–RD)
65 ns (min)
WR
“H” level
:
:
:
:
td(AH–RD)
RD delay time after outputting address of 3806
RD pulse width of 3806
t
WL(RD)
Output enabled access time of M5M5256BP
Data bus setup time before RD of 3806
ta(OE)
tsu(DB–RD)
Fig. 2.5.4 Read-cycle (OE access, SRAM)
A A7
0–
Address (low-order)
Address (high-order)
(Port P0)
A8–A14
(Port P1)
CE
t
PHL
5.8 ns (max)
t
WL(RD)
td(AH–RD)
OE
(RD of 3806)
125 ns - 10ns (min)
125 ns - 35 ns (min)
ta(OE)
50 ns (max)
Data
D0–D7
(Port P2)
tsu(DB–RD)
65 ns (min)
WR
“H” level
t
PHL
td(AH–RD)
WL(RD)
:
Output delay time of 74F04
:
:
:
RD delay time after outputting address of 3806
RD pulse width of 3806
t
ta(OE)
Output enabled access time of M5M27C256AK
tsu(DB–RD)
:
Data bus setup time before RD of 3806
Fig. 2.5.5 Read-cycle (OE access, EPROM)
3806 GROUP USER’S MANUAL
2-60
APPLICATION
2.5 Processor mode
A0–A7
Address (low-order)
Address (high-order)
(Port P0)
A8–A14
(Port P1)
S
(A15)
tWL(WR)
125 ns - 10 ns (min)
td(AH–WR)
125 ns - 35 ns (min)
W
(WR of 3806)
td(WR–DB)
65 ns (max)
DQ1–DQ8
(Port P2)
Data
tsu(D)
35 ns (min)
OE
(RD of 3806)
“H“ level
td(AH–WR)
tWL(WR)
: WR delay time after outputting address of 3806
: WR pulse width of 3806
: Data bus delay time after WR of 3806
: Data setup time of M5M5256BP
td(WR–DB)
tsu(D)
Fig. 2.5.6 Write-cycle (W control, SRAM)
3806 GROUP USER’S MANUAL
2-61
APPLICATION
2.5 Processor mode
_____
(2) Application example of memory expansion in the case where the ONW (One-Wait)
function is used
____
Outline : ONW function is used when the external memory access is slow.
____
If “L” level signal is input to the P32/ONW pin while the CPU is in the read or write status,
the read or write cycle corresponding to 1 cycle of is extended. In the extended period,
___
___
____
the RD or WR signal is kept at the “L” level. The ONW function operates only when data is
read from or written into addresses 000016 to 000716 and addresses 044016 to FFFF16.
____
Figure 2.5.7 shows an application example of the ONW function.
3806 group
CNVSS
AD15
74F04
2
P3
0, P31
M5M27C256AK-10
M5M5256BP-10
S
ONW
AD14
AD
CE
15
8
8
8
P4
A
0–A14
A
0–A14
0
EPROM
SRAM
DB
DB
0
7
8
D
0–D
7
DQ
1–DQ
8
P5
P6
Memory map
OE
OE
W
000016
External RAM area
(M5M5256BP)
000816
004016
044016
SFR area
RD
Internal RAM area
WR
External RAM area
(M5M5256BP)
800016
FFFF16
8MHz
V
CC = 5.0V±10 %
External ROM area
(M5M27C256AK)
____
Fig. 2.5.7 Application example of the ONW function
3806 GROUP USER’S MANUAL
2-62
APPLICATION
2.5 Processor mode
Figure 2.5.9, Figure 2.5.10 and Figure 2.5.11 shows a standard timing at 9 MHz (No-Wait).
A0–A7
Address (low-order)
Address (high-order)
(Port P0)
A8–A14
(Port P1)
S
(A15)
td(AH–RD)
t
WL(RD)
OE
(RD of 3806)
111 ns - 10ns (min)
111 ns - 35 ns (min)
ta(OE)
35 ns (max)
Data
DQ1–DQ8
(Port P2)
tsu(DB–RD)
50 ns (min)
WR
“H” level
td(AH–RD)
:
:
:
:
RD delay time after outputting address of 3806
RD pulse width of 3806
t
WL(RD)
ta(OE)
Output enabled access time of M5M5256BP
Data bus setup time before RD of 3806
tsu(DB–RD)
Fig. 2.5.9 Read-cycle (OE access, SRAM) [High-speed version]
A
0
–A
7
Adderss (low-order)
Adderss (high-order)
(Port P0)
A8–A14
(Port P1)
CE
t
PHL
5.8 ns (max)
t
WL(RD)
td(AH–RD)
OE
(RD of 3806)
111 ns - 10ns (min)
111 ns - 35 ns (min)
ta(OE)
45 ns (max)
Data
D0–D7
(Port P2)
tsu(DB–RD)
50 ns (min)
WR
“H” level
:
:
:
:
:
Output delay time of 74F04
t
PHL
td(AH–RD)
WL(RD)
RD delay time after outputting address of 3806
RD pulse width of 3806
t
Output enabled access time of M5M27C256AK
Data bus setup time before RD of 3806
ta(OE)
tsu(DB–RD)
Fig. 2.5.10 Read-cycle (OE access, EPROM) [High-speed version]
3806 GROUP USER’S MANUAL
2-64
APPLICATION
2.6 Reset
2.6 Reset
2.6.1 Connection example of reset IC
91
35
40
V
CC
1
Power source
Output
5
M62022L
RESET
Delay capacity
4
GND
0.1 µF
3
VSS
3806 group
Fig. 2.6.1 Example of Poweron reset circuit
Figure 2.6.2 shows the system example which switch to the RAM backup mode by detecting a drop of the
system power source voltage with the INT interrupt.
System power
source voltage
+5
91
V
CC
+
7
V
CC
1
5
35
40
RESET
RESET
INT
2
1
3
6
INT
Cd
V
CC
2
VSS
V1
GND
3806 group
4
M62009L, M62009P, M62009FP
Fig. 2.6.2 RAM back-up system
3806 GROUP USER’S MANUAL
2-66
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 List of registers
3.6 Mask ROM ordering method
3.7 Mark specification form
3.8 Package outline
3.9 List of instruction codes
3.10 Machine instructions
3.11 SFR memory map
3.12 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1 ELECTRICAL CHARACTERISTICS
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
VI
–0.3 to VCC +0.3
V
P60–P67, P70–P77, P80–P87,
VREF
______
All voltages are based on VSS.
Output transistors are cut off.
VI
VI
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to VCC +0.3
–0.3 to 13
V
V
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87,
XOUT
VO
–0.3 to VCC +0.3
V
Pd
Power dissipation
Ta = 25 °C
500
mW
°C
Topr
Tstg
Operating temperature
Storage temperature
–20 to 85
–40 to 125
°C
3806 GROUP USER’S MANUAL
3-2
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.3 Electrical characteristics (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –10 mA
Unit
V
Min.
Max.
“H” output voltage P0
0–P0
0–P3
0–P6
7
7
7
, P1
, P4
, P8
0
0
0
–P1
–P4
–P8
7
7
7
, P2
, P5
(Note 1)
0
0
–P2
–P5
7
7
,
,
V
V
CC–2.0
P3
P6
VCC = 4.0 to 5.5 V
VOH
IOH = –1.0 mA
VCC = 3.0 to 5.5 V
CC–1.0
“L” output voltage P0
0–P0
0–P3
0–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7
7
7
, P2
0
–P2
–P5
–P8
7
,
IOL = 10 mA
VCC = 4.0 to 5.5 V
2.0
1.0
P3
P6
,P5
0
7
,
VOL
V
, P8
0
7
IOL = 1.0 mA
VCC = 3.0 to 5.5 V
VT+ – VT–
VT+ – VT–
VT+ – VT–
Hysteresis
CNTR
0
, CNTR
1
, INT
0
–INT
4
0.4
0.5
0.5
V
V
V
Hysteresis
RXD, SCLK1, SIN2, SCLK2
______
RESET
Hysteresis
“H” input current
P0
P3
P6
0
0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7, P2
7, P5
7, P8
0
0
0
–P2
–P5
–P8
7
7
7
,
,
IIH
VI = VCC
5.0
5.0
µA
______
IIH
IIH
“H” input current
“H” input current
“L” input current
RESET, CNVSS
VI = VCC
VI = VCC
µA
µA
X
IN
4
P0
P3
P6
0
0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7, P2
7, P5
7, P8
0
0
0
–P2
–P5
–P8
7
7
7
,
,
IIL
VI = VSS
–5.0
–5.0
µA
______
IIL
“L” input current
“L” input current
RAM hold voltage
RESET, CNVSS
VI = VSS
µA
µA
V
IIL
X
IN
VI = VSS
–4
VRAM
When clock stopped
f(XIN) = 8 MHz, VCC = 5 V
f(XIN) = 5 MHz, VCC = 5 V
f(XIN) = 2 MHz, VCC = 3 V
2.0
5.5
13
8
6.4
4
0.8
2.0
When WIT instruction is executed
with f(XIN) = 8 MHz, VCC = 5 V
1.5
1
mA
When WIT instruction is executed
with f(XIN) = 5 MHz, VCC = 5 V
ICC
Power source current
When WIT instruction is executed
with f(XIN) = 2 MHz, VCC = 3 V
0.2
0.1
When STP instruction
Ta = 25 °C
1
is executed with clock (Note 2)
µA
stopped, output
transistors isolated.
(Note 2)
Ta = 85 °C
10
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.
3.1.4 A-D converter characteristics
Table 3.1.4 A-D converter characteristics
(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
—
—
Resolution
Bits
LSB
tC(φ)
kΩ
Absolute accuracy (excluding quantization error)
Conversion time
±1
±2.5
50
tCONV
RLADDER
IVREF
Ladder resistor
35
150
0.5
Reference power source input current (Note)
A-D port input current
VREF = 5.0 V
50
200
5.0
µA
II(AD)
µA
Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.
3806 GROUP USER’S MANUAL
3-4
APPENDIX
3.1 Electrical characteristics
3.1.5 D-A converter characteristics
Table 3.1.5 D-A converter characteristics
(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Bits
%
Min.
Typ.
Max.
8
—
—
Resolution
V
V
CC = 4.0 to 5.5 V
CC = 3.0 to 4.0 V
1.0
2.5
3
Absolute accuracy
tsu
Setting time
µs
kΩ
mA
RO
Output resistor
1
2.5
4
IVREF
Reference power source input current (Note)
3.2
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur-
rents flowing through the A-D resistance ladder.
3806 GROUP USER’S MANUAL
3-5
APPENDIX
3.1 Electrical characteristics
3.1.6 Timing requirements and Switching characteristics
Table 3.1.6 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
_____
tw(RESET)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(XIN)
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
125
50
twH(XIN)
twL(XIN)
50
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
200
80
80
80
80
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
800
1000
370
400
370
400
220
200
100
200
t
t
t
t
su(R
su(SIN2–SCLK2
D)
h(SCLK2–SIN2
X
D–SCLK1
)
)
Serial I/O2 input set up time
h(SCLK1–R
X
Serial I/O1 input hold time
)
Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
Table 3.1.7 Timing requirements (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
_____
tw(RESET)
Reset input “L” pulse width
2
µs
500/
(3 VCC–8)
tc(XIN)
External clock input cycle time
ns
200/
(3 VCC–8)
twH(XIN)
twL(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
ns
ns
200/
(3 VCC–8)
tc(CNTR)
twH(CNTR)
twH(INT)
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
500
230
230
230
230
2000
2000
950
950
950
950
400
400
200
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twL(CNTR)
twL(INT)
tc(SCLK1)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t
t
t
t
su(R
su(SIN2–SCLK2
D)
h(SCLK2–SIN2
X
D–SCLK1
)
)
Serial I/O2 input set up time
h(SCLK1–R
X
Serial I/O1 input hold time
)
Serial I/O2 input hold time
Note : When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
3806 GROUP USER’S MANUAL
3-6
APPENDIX
3.1 Electrical characteristics
Table 3.1.8 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
140
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
t
t
c(SCLK1
)
/2–30
/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK1
)
t
t
d(SCLK1–T
v(SCLK1–T
X
D)
Fig. 3.1.1
X
D)
–30
tr(SCLK1)
tf(SCLK1)
30
30
twH(SCLK2)
twL(SCLK2)
t
c(SCLK2
c(SCLK2
)
)
/2–160
t
/2–160
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
Fig. 3.1.2
Fig. 3.1.1
200
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
40
30
30
10
10
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT and P70–P77 are excluded.
Table 3.1.9 Switching characteristics (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
350
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
t
t
c(SCLK1
)
/2–50
/2–50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK1
)
t
t
d(SCLK1–T
v(SCLK1–T
X
D)
Fig. 3.1.1
X
D)
–30
tr(SCLK1)
tf(SCLK1)
50
50
twH(SCLK2)
twL(SCLK2)
t
c(SCLK2
c(SCLK2
)
)
/2–240
t
/2–240
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
Fig. 3.1.2
Fig. 3.1.1
400
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
50
50
50
20
20
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT and P70–P77 are excluded.
3806 GROUP USER’S MANUAL
3-7
APPENDIX
3.1 Electrical characteristics
Table 3.1.10 Timing requirements in memory expansion mode and microprocessor mode (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
–20
–20
60
Max.
_____
____
tsu(ONW–φ)
____
th(φ–ONW)
Before φ ONW input set up time
ns
ns
ns
ns
_____
After φ ONW input hold time
Before φ data bus set up time
tsu(DB–φ)
th(φ–DB)
After φ data bus hold time
0
___ _____
____ __
tsu(ONW–RD)
Before RD ONW input set up time
___ _____
____ ___
–20
–20
ns
ns
tsu(ONW–WR) Before WR ONW input set up time
___ _____
__ ____
th(RD–ONW) After RD ONW input hold time
___ _____
___ ____
th(WR–ONW) After WR ONW input hold time
___
__
tsu(DB–RD)
Before RD data bus set up time
___
65
0
ns
ns
__
th(RD–DB)
After RD data bus hold time
Table 3.1.11 Switching characteristics in memory expansion mode and microprocessor mode (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
tc(φ)
φ clock cycle time
2tc(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
tc(XIN)–10
tc(XIN)–10
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
20
10
25
10
20
10
10
5
40
45
6
6
tv(φ–SYNC)
___
SYNC valid time
___
___
td(φ–WR)
___
RD and WR delay time
___ ___
20
10
70
tv(φ–WR)
td(φ–DB)
tv(φ–DB)
__
RD and WR valid time
3
After φ data bus delay time
After φ data bus valid time
20
15
___
___
Fig. 3.1.1
RD pulse width, WR pulse width
___ ___
tc(XIN)–10
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
__
3tc(XIN)–10
ns
ns
ns
ns
ns
(When one-wait is valid)
___
td(AH–RD)
td(AH–WR)
__
After AD15–AD8 RD delay time
___
___
tc(XIN)–35
t
t
c(XIN
c(XIN
)
)
–15
–20
After AD15–AD8 WR delay time
___
td(AL–RD)
td(AL–WR)
__
After AD7–AD0 RD delay time
___
___
tc(XIN)–40
After AD7–AD0 WR delay time
___
tv(RD–AH)
After RD AD15–AD8 valid time
___
___
0
0
5
tv(WR–AH)
__
After WR AD15–AD8 valid time
___
tv(RD–AL)
After RD AD7–AD0 valid time
___
___
5
tv(WR–AL)
___
After WR AD7–AD0 valid time
___
td(WR–DB)
___
After WR data bus delay time
___
15
65
ns
ns
ns
ns
tv(WR–DB)
___ _____
After WR data bus valid time
_________
10
0
t
d
(RESET–RESETOUT
)
RESETOUT output delay time (Note 1)
_________
200
200
_____
tv(φ–RESET)
RESETOUT output valid time (Note 1)
__________
Note 1: The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
3806 GROUP USER’S MANUAL
3-8
APPENDIX
3.1 Electrical characteristics
Table 3.1.12 Timing requirements in memory expansion mode and microprocessor mode (2)
(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
–20
–20
180
0
Typ.
Max.
_____
____
tsu(ONW–φ)
____
th(φ–ONW)
Before φ ONW input set up time
ns
ns
ns
ns
_____
After φ ONW input hold time
Before φ data bus set up time
tsu(DB–φ)
th(φ–DB)
After φ data bus hold time
___ _____
____ __
tsu(ONW–RD)
Before RD ONW input set up time
___ _____
____ ___
ns
ns
–20
–20
tsu(ONW–WR) Before WR ONW input set up time
___ _____
__ ____
th(RD–ONW) After RD ONW input hold time
___ _____
___ ____
th(WR–ONW) After WR ONW input hold time
___
__
ns
ns
tsu(DB–RD)
Before RD data bus set up time
___
185
0
__
th(RD–DB)
After RD data bus hold time
Table 3.1.13 Switching characteristics in memory expansion mode and microprocessor mode (2)
(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
tc(φ)
φ clock cycle time
2tc(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
tc(XIN)–20
tc(XIN)–20
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
150
150
10
10
15
15
40
20
15
7
tv(φ–SYNC)
SYNC valid time
___
___
___
td(φ–WR)
___
RD and WR delay time
___ ___
25
15
tv(φ–WR)
RD and WR valid time
3
td(φ–DB)
tv(φ–DB)
__
After φ data bus delay time
After φ data bus valid time
200
15
___
___
Fig. 3.1.1
RD pulse width, WR pulse width
___ ___
tc(XIN)–20
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
__
3tc(XIN)–20
ns
ns
ns
ns
ns
(When one-wait is valid)
___
td(AH–RD)
td(AH–WR)
__
After AD15–AD8 RD delay time
___
___
tc(XIN)–145
After AD15–AD8 WR delay time
___
td(AL–RD)
td(AL–WR)
__
After AD7–AD0 RD delay time
___
___
tc(XIN)–145
After AD7–AD0 WR delay time
___
tv(RD–AH)
After RD AD15–AD8 valid time
___
___
5
5
10
10
tv(WR–AH)
__
After WR AD15–AD8 valid time
___
tv(RD–AL)
After RD AD7–AD0 valid time
___
___
tv(WR–AL)
___
After WR AD7–AD0 valid time
___
td(WR–DB)
___
After WR data bus delay time
___
195
ns
ns
tv(WR–DB)
___ _____
After WR data bus valid time
_________
10
0
t
d
(RESET–RESETOUT
)
RESETOUT output delay time (Note 1)
_________
300
300
ns
ns
_____
tv(φ–RESET)
RESETOUT output valid time (Note 1)
__________
Note1: The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
3806 GROUP USER’S MANUAL
3-9
APPENDIX
3.1 Electrical characteristics
3.1.7 Absolute maximum ratings (Extended operating temperature version)
Table 3.1.14 Absolute maximum ratings (Extended operating temperature version)
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
VI
–0.3 to VCC +0.3
V
P60–P67, P70–P77, P80–P87,
VREF
______
All voltage are based on VSS.
Output transistors are cut off.
VI
VI
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to VCC +0.3
–0.3 to 13
V
V
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87,
XOUT
VO
–0.3 to VCC +0.3
V
Pd
Power dissipation
Ta = 25 °C
500
mW
°C
Topr
Tstg
Operating temperature
Storage temperature
–40 to 85
–65 to 150
°C
3.1.8 Recommended operating conditions (Extended operating temperature version)
Table 3.1.15 Recommended operating conditions (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
4.0
Typ.
5.0
0
Max.
5.5
VCC
Power source voltage
Power source voltage
V
V
VSS
Analog reference voltage (when A-D converter is used)
Analog reference voltage (when D-A converter is used)
Analog power source voltage
2.0
4.0
VCC
VCC
V
VREF
AVSS
VIA
0
V
V
Analog input voltage
“H” input voltage
AN0–AN7
AVSS
0.8 VCC
0.8 VCC
0
VCC
VCC
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
VIH
VIH
VIL
V
V
V
P50–P57, P60–P67, P70–P77, P80–P87
______
“H” input voltage
“L” input voltage
RESET, XIN, CNVSS
VCC
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
0.2 VCC
P50–P57, P60–P67, P70–P77, P80–P87
______
VIL
“L” input voltage
RESET, CNVSS
XIN
0
0
0.2 VCC
0.16 VCC
–80
V
VIL
“L” input voltage
V
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
P0
P40–P47,P50–P57, P60–P67 (Note 1)
P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3 , P8
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P8
0
0
–P8
7
7
(Note 1)
(Note 1)
mA
mA
mA
mA
mA
mA
mA
mA
–80
0
7
0
7
0
7
0
7
–P8
80
P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)
80
“H” total average output current P0
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
“L” total average output current P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3 , P8
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P8
0
0
–P8
7
7
(Note 1)
–40
–40
0
7
0
7
0
7
0
7
–P8
(Note 1)
40
“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)
40
“H” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 2)
IOH(peak)
IOL(peak)
IOH(avg)
–10
10
mA
mA
mA
“L” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)
“H” average output current
“L” average output current
Internal clock oscillation frequency
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 3)
–5
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 3)
IOL(avg)
f(XIN)
5
8
mA
MHz
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver-
age value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
3806 GROUP USER’S MANUAL
3-10
APPENDIX
3.1 Electrical characteristics
3.1.9 Electrical characteristics (Extended operating temperature version)
Table 3.1.16 Electrical characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V,
VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
V
Min.
Typ.
Max.
“H” output voltage P0
0–P0
0–P3
0–P6
7
7
7
, P1
, P4
, P8
0
0
0
–P1
–P4
–P8
7
7
7
, P2
, P5
0
0
–P2
–P5
7
7
,
,
VOH
P3
P6
IOH = –10 mA
IOL = 10 mA
VCC–2.0
(Note 1)
, P2 –P2
–P5
–P8
“L” output voltage P0
0–P0
0–P3
0–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7
7
7
0
7
,
VOL
P3
P6
,P5
0
7
,
2.0
V
, P8
0
7
VT+ – VT–
VT+ – VT–
VT+ – VT–
Hysteresis
CNTR
0
, CNTR
1
, INT
0
–INT
4
0.4
0.5
0.5
V
V
V
Hysteresis
RXD, SCLK1, SIN2, SCLK2
______
RESET
Hysteresis
“H” input current
P0
P3
P6
0
0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7, P2
7, P5
7, P8
0
0
0
–P2
–P5
–P8
7
7
7
,
,
IIH
VI = VCC
5.0
5.0
µA
______
IIH
IIH
“H” input current
“H” input current
“L” input current
RESET, CNVSS
VI = VCC
VI = VCC
µA
µA
X
IN
4
P0
P3
P6
0
0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7, P2
7, P5
7, P8
0
0
0
–P2
–P5
–P8
7
7
7
,
,
IIL
VI = VSS
–5.0
–5.0
µA
______
IIL
“L” input current
“L” input current
RAM hold voltage
RESET, CNVSS
VI = VSS
µA
µA
V
IIL
X
IN
VI = VSS
–4
VRAM
When clock stopped
f(XIN) = 8 MHz
f(XIN) = 5 MHz
2.0
5.5
13
8
6.4
4
When WIT instruction is executed
with f(XIN) = 8 MHz
mA
1.5
1
When WIT instruction is executed
with f(XIN) = 5 MHz
ICC
Power source current
When STP instruction
is executed with clock (Note 2)
Ta = 25 °C
0.1
1
µA
stopped, output
transistors isolated.
(Note 2)
Ta = 85 °C
10
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.
3.1.10 A-D converter characteristics (Extended operating temperature version)
Table 3.1.17 A-D converter characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, T
a
= –40 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter Test conditions
Min.
Typ.
Max.
8
—
—
Resolution
Bits
LSB
tC(φ)
kΩ
Absolute accuracy (excluding quantization error)
Conversion time
±1
±2.5
50
tCONV
RLADDER
IVREF
Ladder resistor
35
150
0.5
Reference power source input current (Note)
A-D port input current
VREF = 5.0 V
50
200
5.0
µA
II(AD)
µA
Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.
3806 GROUP USER’S MANUAL
3-11
APPENDIX
3.1 Electrical characteristics
3.1.11 D-A converter characteristics (Extended operating temperature version)
Table 3.1.18 D-A converter characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, T
a
= –40 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter Test conditions
Min.
Typ.
Max.
8
—
—
Resolution
Bits
%
Absolute accuracy
Setting time
1.0
3
tsu
µs
RO
Output resistor
1
2.5
4
kΩ
mA
IVREF
Reference power source input current (Note)
3.2
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur-
rents flowing through the A-D resistance ladder.
3806 GROUP USER’S MANUAL
3-12
APPENDIX
3.1 Electrical characteristics
3.1.12 Timing requirements and Switching characteristics (Extended operating temperature version)
Table 3.1.19 Timing requirements (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
_____
tw(RESET)
Reset input “L” pulse width
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(XIN)
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
125
50
twH(XIN)
twL(XIN)
50
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
200
80
80
80
80
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
800
1000
370
400
370
400
220
200
100
200
t
t
t
t
su(R
su(SIN2–SCLK2
D)
h(SCLK2–SIN2
X
D–SCLK1
)
)
Serial I/O2 input set up time
h(SCLK1–R
X
Serial I/O1 input hold time
)
Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
Table 3.1.20 Switching characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
140
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rise time
Serial I/O1 clock output fall time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
t
t
c(SCLK1
)
/2–30
/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK1
)
t
t
d(SCLK1–T
v(SCLK1–T
X
D)
Fig. 3.1.1
X
D)
–30
tr(SCLK1)
tf(SCLK1)
30
30
twH(SCLK2)
twL(SCLK2)
t
c(SCLK2
c(SCLK2
)
)
/2–160
t
/2–160
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
Fig. 3.1.2
Fig. 3.1.1
200
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output fall time
CMOS output rise time (Note 2)
CMOS output fall time (Note 2)
40
30
30
10
10
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT pin and P70–77 are excluded.
3806 GROUP USER’S MANUAL
3-13
APPENDIX
3.1 Electrical characteristics
Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode
(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
–20
–20
60
Typ.
Max.
_____
____
tsu(ONW–φ)
____
th(φ–ONW)
Before φ ONW input set up time
ns
ns
ns
ns
_____
After φ ONW input hold time
Before φ data bus set up time
tsu(DB–φ)
th(φ–DB)
After φ data bus hold time
0
___ _____
____ __
tsu(ONW–RD)
Before RD ONW input set up time
___ _____
____ ___
–20
–20
ns
ns
tsu(ONW–WR) Before WR ONW input set up time
___ _____
__ ____
th(RD–ONW) After RD ONW input hold time
___ _____
___ ____
th(WR–ONW) After WR ONW input hold time
___
__
tsu(DB–RD)
Before RD data bus set up time
___
65
0
ns
ns
__
th(RD–DB)
After RD data bus hold time
Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode
(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
tc(φ)
φ clock cycle time
2tc(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
tc(XIN)–10
tc(XIN)–10
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
20
10
25
10
20
10
10
5
40
45
6
6
tv(φ–SYNC)
___
SYNC valid time
___
___
td(φ–WR)
___
RD and WR delay time
___ ___
20
10
70
tv(φ–WR)
RD and WR valid time
3
td(φ–DB)
tv(φ–DB)
__
After φ data bus delay time
After φ data bus valid time
20
15
___
___
Fig. 3.1.1
RD pulse width, WR pulse width
___ ___
tc(XIN)–10
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
__
3tc(XIN)–10
ns
ns
ns
ns
ns
(When one-wait is valid)
___
td(AH–RD)
td(AH–WR)
__
After AD15–AD8 RD delay time
___
___
tc(XIN)–35
t
t
c(XIN
c(XIN
)
)
–15
–20
After AD15–AD8 WR delay time
___
td(AL–RD)
td(AL–WR)
__
After AD7–AD0 RD delay time
___
___
tc(XIN)–40
After AD7–AD0 WR delay time
___
tv(RD–AH)
After RD AD15–AD8 valid time
___
___
0
0
5
tv(WR–AH)
__
After WR AD15–AD8 valid time
___
tv(RD–AL)
After RD AD7–AD0 valid time
___
___
5
tv(WR–AL)
___
After WR AD7–AD0 valid time
___
td(WR–DB)
___
After WR data bus delay time
___
15
65
ns
ns
ns
ns
tv(WR–DB)
___ _____
After WR data bus valid time
_________
10
0
t
d
(RESET–RESETOUT
)
RESETOUT output delay time (Note 1)
_________
200
200
_____
tv(φ–RESET)
RESETOUT output valid time (Note 1)
_________
Note 1: The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
3806 GROUP USER’S MANUAL
3-14
APPENDIX
3.1 Electrical characteristics
3.1.15 Electrical characteristics (High-speed version)
Table 3.1.25 Electrical characteristics (High-speed version) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
IOH = –10 mA
Unit
Min.
Typ.
Max.
“H” output voltage P0
0–P0
0–P3
0–P6
7
7
7
, P1
, P4
, P8
0
0
0
–P1
–P4
–P8
7
7
7
, P2
, P5
(Note 1)
0
0
–P2
–P5
7
7
,
,
V
V
CC–2.0
P3
P6
VCC = 4.0 to 5.5 V
VOH
V
IOH = –1.0 mA
VCC = 2.7 to 5.5 V
CC–1.0
“L” output voltage P0
0–P0
0–P3
0–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7
7
7
, P2
0
–P2
–P5
–P8
7
,
IOL = 10 mA
VCC = 4.0 to 5.5 V
2.0
1.0
P3
P6
,P5
0
7
,
VOL
V
, P8
0
7
IOL = 1.0 mA
VCC = 2.7 to 5.5 V
VT+ – VT–
VT+ – VT–
VT+ – VT–
Hysteresis
CNTR
0
, CNTR
1
, INT
0
–INT
4
0.4
0.5
0.5
V
V
V
Hysteresis
RXD, SCLK1, SIN2, SCLK2
______
RESET
Hysteresis
“H” input current
P0
P3
P6
0
0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7, P2
7, P5
7, P8
0
0
0
–P2
–P5
–P8
7
7
7
,
,
IIH
VI = VCC
5.0
5.0
µA
______
IIH
IIH
“H” input current
“H” input current
“L” input current
RESET, CNVSS
VI = VCC
VI = VCC
µA
µA
X
IN
4
P0
P3
P6
0
0
0
–P0
–P3
7
7
, P1
, P4
0
0
0
–P1
–P4
–P7
7, P2
7, P5
7, P8
0
0
0
–P2
–P5
–P87,
7
7
,
,
IIL
VI = VSS
–5.0
µA
–P6 , P7
______7
RESET, CNVSS
IIL
“L” input current
X
IN
VI = VSS
–4
µA
VRAM
RAM hold voltage
With clock stopped
f(XIN) = 10 MHz, VCC = 5 V
f(XIN) = 4 MHz, VCC = 2.7 V
2.0
5.5
16
2
V
8
1.3
When WIT instruction is executed
with f(XIN) = 10 MHz, VCC = 5 V
mA
2
0.3
0.1
When WIT instruction is executed
with f(XIN) = 4 MHz, VCC = 2.7 V
ICC
Power source current
When STP instruction
Ta = 25 °C
1
is executed with clock (Note 2)
µA
stopped, output
transistors isolated.
(Note 2)
Ta = 85 °C
10
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.
3.1.16 A-D converter characteristics (High-speed version)
Table 3.1.26 A-D converter characteristics (High-speed version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, T
a
= –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter Test conditions
Min.
Typ.
Max.
8
—
—
Resolution
Bits
LSB
tC(φ)
kΩ
Absolute accuracy (excluding quantization error)
Conversion time
±1
±2.5
50
tCONV
RLADDER
IVREF
Ladder resistor
35
150
0.5
Reference power source input current (Note)
A-D port input current
VREF = 5.0 V
50
200
5.0
µA
II(AD)
µA
Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.
3806 GROUP USER’S MANUAL
3-16
APPENDIX
3.1 Electrical characteristics
3.1.17 D-A converter characteristics (High-speed version)
Table 3.1.27 D-A converter characteristics (High-speed version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.7 V to VCC, T
a
= –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter Test conditions
Min.
Typ.
Max.
8
—
—
Resolution
Bits
%
V
V
CC = 4.0 to 5.5 V
CC = 2.7 to 5.5 V
1.0
2.5
3
Absolute accuracy
tsu
Setting time
µs
kΩ
mA
RO
Output resistor
1
2.5
4
IVREF
Reference power source input current (Note)
3.2
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur-
rents flowing through the A-D resistance ladder.
3806 GROUP USER’S MANUAL
3-17
APPENDIX
3.1 Electrical characteristics
3.1.18 Timing requirements and Switching characteristics (High-speed version)
Table 3.1.28 Timing requirements (1) (High-speed version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
_____
tw(RESET)
Reset input “L” pulse width
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(XIN)
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
100
40
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
200
80
80
80
80
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
800
1000
370
400
370
400
220
200
100
200
t
t
t
t
su(R
su(SIN2–SCLK2
D)
h(SCLK2–SIN2
X
D–SCLK1
)
)
Serial I/O2 input set up time
h(SCLK1–R
X
Serial I/O1 input hold time
)
Serial I/O2 input hold time
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”.
Table 3.1.29 Timing requirements (2) (High-speed version) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
_____
tw(RESET)
Reset input “L” pulse width
2
µs
1000/
(4.5 VCC–8)
tc(XIN)
External clock input cycle time
ns
400/
(4.5 VCC–8)
twH(XIN)
twL(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
ns
ns
400/
(4.5 VCC–8)
tc(CNTR)
twH(CNTR)
twH(INT)
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
500
230
230
230
230
2000
2000
950
950
950
950
400
400
200
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twL(CNTR)
twL(INT)
tc(SCLK1)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t
t
t
t
su(R
su(SIN2–SCLK2
D)
h(SCLK2–SIN2
X
D–SCLK1
)
)
Serial I/O2 input set up time
h(SCLK1–R
X
Serial I/O1 input hold time
)
Serial I/O2 input hold time
Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0”.
3806 GROUP USER’S MANUAL
3-18
APPENDIX
3.1 Electrical characteristics
Table 3.1.30 Switching characteristics (1) (High-speed version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
140
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
t
t
c(SCLK1
)
/2–30
/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK1
)
t
t
d(SCLK1–T
v(SCLK1–T
X
D)
Fig. 3.1.1
X
D)
–30
tr(SCLK1)
tf(SCLK1)
30
30
twH(SCLK2)
twL(SCLK2)
t
c(SCLK2
c(SCLK2
)
)
/2–160
t
/2–160
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
Fig. 3.1.2
Fig. 3.1.1
200
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
30
30
30
10
10
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
Table 3.1.31 Switching characteristics (2) (High-speed version)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
350
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
t
t
c(SCLK1
)
/2–50
/2–50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK1
)
t
t
d(SCLK1–T
v(SCLK1–T
X
D)
Fig. 3.1.1
X
D)
–30
tr(SCLK1)
tf(SCLK1)
50
50
twH(SCLK2)
twL(SCLK2)
t
c(SCLK2
c(SCLK2
)
)
/2–240
t
/2–240
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
Fig. 3.1.2
Fig. 3.1.1
400
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
50
50
50
20
20
Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
3806 GROUP USER’S MANUAL
3-19
APPENDIX
3.1 Electrical characteristics
Table 3.1.32 Timing requirements in memory expansion mode and microprocessor mode (1) (High-speed version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
–20
–20
50
Typ.
25
Max.
_____
____
tsu(ONW–φ)
____
Before φ ONW input set up time
ns
ns
ns
ns
_____
th(φ–ONW)
After φ ONW input hold time
Before φ data bus set up time
tsu(DB–φ)
th(φ–DB)
After φ data bus hold time
0
___ _____
____ __
tsu(ONW–RD)
Before RD ONW input set up time
___ _____
____ ___
–20
–20
ns
ns
tsu(ONW–WR) Before WR ONW input set up time
___ _____
__ ____
th(RD–ONW) After RD ONW input hold time
___ _____
___ ____
th(WR–ONW) After WR ONW input hold time
___
__
tsu(DB–RD)
__
Before RD data bus set up time
___
50
0
25
ns
ns
th(RD–DB)
After RD data bus hold time
Table 3.1.33 Switching characteristics in memory expansion mode and microprocessor mode (1) (High-speed version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
tc(φ)
φ clock cycle time
2tc(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
tc(XIN)–10
tc(XIN)–10
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–DB)
tv(φ–DB)
__
16
5
35
40
2
2
20
5
16
5
SYNC valid time
After φ data bus delay time
After φ data bus valid time
15
30
10
___
___
RD pulse width, WR pulse width
___ ___
tc(XIN)–10
twL(RD)
___
Fig. 3.1.1
RD pulse width, WR pulse width
twL(WR)
__
3tc(XIN)–10
ns
ns
ns
ns
ns
(When one-wait is valid)
___
td(AH–RD)
td(AH–WR)
__
After AD15–AD8 RD delay time
___
___
tc(XIN)–35
t
t
c(XIN
c(XIN
)
)
–16
–20
After AD15–AD8 WR delay time
___
td(AL–RD)
td(AL–WR)
__
After AD7–AD0 RD delay time
___
___
tc(XIN)–40
After AD7–AD0 WR delay time
___
tv(RD–AH)
After RD AD15–AD8 valid time
___
___
2
2
5
tv(WR–AH)
__
After WR AD15–AD8 valid time
___
tv(RD–AL)
After RD AD7–AD0 valid time
___
___
5
tv(WR–AL)
___
After WR AD7–AD0 valid time
___
td(WR–DB)
___
After WR data bus delay time
___
15
30
ns
ns
ns
ns
tv(WR–DB)
___ _____
After WR data bus valid time
_________
10
0
t
d
(RESET–RESETOUT
)
RESETOUT output delay time (Note 1)
_________
200
100
_____
tv(φ–RESET)
RESETOUT output valid time (Note 1)
_________
Note 1: The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
3806 GROUP USER’S MANUAL
3-20
APPENDIX
3.1 Electrical characteristics
Table 3.1.34 Timing requirements in memory expansion mode and microprocessor mode (2) (High-speed version)
(VCC = 2.7 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
____
Parameter
Min.
–20
–20
120
0
Typ.
60
Max.
_____
tsu(ONW–φ)
Before φ ONW input set up time
ns
ns
ns
ns
_____
____
th(φ–ONW)
tsu(DB–φ)
After φ ONW input hold time
Before φ data bus set up time
th(φ–DB)
After φ data bus hold time
___ _____
____ __
tsu(ONW–RD)
Before RD ONW input set up time
___ _____
____ ___
–20
–20
ns
ns
tsu(ONW–WR) Before WR ONW input set up time
___ _____
__ ____
th(RD–ONW) After RD ONW input hold time
___ _____
___ ____
th(WR–ONW) After WR ONW input hold time
___
__
tsu(DB–RD)
__
Before RD data bus set up time
___
120
0
60
ns
ns
th(RD–DB)
After RD data bus hold time
Table 3.1.35 Switching characteristics in memory expansion mode and microprocessor mode (2) (High-speed version)
(VCC = 2.7 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
tc(φ)
φ clock cycle time
2tc(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
AD15–AD8 delay time
AD15–AD8 valid time
AD7–AD0 delay time
AD7–AD0 valid time
SYNC delay time
tc(XIN)–20
tc(XIN)–20
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–DB)
tv(φ–DB)
__
40
10
50
10
40
10
30
100
100
5
5
SYNC valid time
Data bus delay time
Data bus valid time
80
10
___
___
Fig. 3.1.1
RD pulse width, WR pulse width
___ ___
tc(XIN)–20
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
__
3tc(XIN)–20
ns
ns
ns
ns
ns
(When one-wait is valid)
___
td(AH–RD)
td(AH–WR)
__
After AD15–AD8 RD delay time
___
___
tc(XIN)–100
t
t
c(XIN
c(XIN
)
)
–40
–50
After AD15–AD8 WR delay time
___
td(AL–RD)
td(AL–WR)
__
After AD7–AD0 RD delay time
___
___
tc(XIN)–100
After AD7–AD0 WR delay time
___
tv(RD–AH)
After RD AD15–AD8 valid time
___
___
5
5
10
tv(WR–AH)
__
After WR AD15–AD8 valid time
___
tv(RD–AL)
After RD AD7–AD0 valid time
___
___
10
30
tv(WR–AL)
___
After WR AD7–AD0 valid time
___
td(WR–DB)
___
After WR data bus delay time
___
80
ns
ns
ns
ns
tv(WR–DB)
___ _____
After WR data bus valid time
_________
10
0
t
d
(RESET–RESETOUT
)
RESETOUT output delay time (Note 1)
_________
300
150
_____
tv(φ–RESET)
RESETOUT output valid time (Note 1)
_________
Note 1: The RESETOUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
Measurement output pin
1kΩ
Measurement output pin
100pF
100pF
CMOS output
N-channel open-drain output
Fig. 3.1.1 Circuit for measuring output switching
characteristics (1)
Fig. 3.1.2 Circuit for measuring output switching
characteristics (2)
3806 GROUP USER’S MANUAL
3-21
APPENDIX
3.1 Electrical characteristics
3.1.19 Timing diagram
Timing Diagram
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8 VCC
CNTR
0
, CNTR
1
0.2 VCC
t
WL(INT)
tWH(INT)
0.8 VCC
INT0–INT
RESET
4
0.2 VCC
tW(RESET)
0.8 VCC
0.2 VCC
tC(XIN)
tWL(XIN)
t
WH(XIN)
0.8 VCC
XIN
0.2 VCC
tC(SCLK1),
tC(SCLK2)
tWL(SCLK1),
tWL(SCLK2
)
tWH(SCLK1), tWH(SCLK2)
tr
tf
S
S
CLK1
CLK2
0.8 VCC
0.2 VCC
t
su(R
X
D
-
S
CLK1),
CLK2
th(SCLK1-
t
R
X
D),
tsu(SIN2-
S
)
h
(SCLK2-
SIN2
)
R
S
X
D
0.8 VCC
0.2 VCC
IN2
t
t
v(SCLK1-T
v(SCLK2-
X
D),
td(SCLK1-T
X
D),td(SCLK2-SOUT2)
S
OUT2
)
TXD
SOUT2
Fig. 3.1.3 Timing diagram (in single-chip mode)
3806 GROUP USER’S MANUAL
3-22
APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode (1)
tC(φ)
t
WL(φ)
tWH(φ)
φ
0.5 VCC
tv(φ-AH)
td(φ-AH)
0.5 VCC
0.5 VCC
0.5 VCC
AD15–AD
8
t
d(φ-AL)
t
v(φ-AL)
AD7
–AD
0
t
v(φ-SYNC)
t
d(φ-SYNC)
SYNC
td(φ-WR)
tv(φ-WR)
0.5 VCC
RD,WR
th(φ-ONW)
t
SU(ONW-φ)
0.8 VCC
0.2 VCC
ONW
th(φ-DB)
tSU(DB-φ)
0.8 VCC
0.2 VCC
DB0–DB
7
(At CPU reading)
td(φ-DB)
tv(φ-DB)
DB0–DB
7
0.5 VCC
(At CPU writing)
Timing Diagram in Microprocessor Mode
0.8 VCC
RESET
0.2 VCC
φ
0.5 VCC
td(RESET- RESETOUT
)
tv(φ- RESETOUT)
0.5 VCC
RESETOUT
Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (1)
3806 GROUP USER’S MANUAL
3-23
APPENDIX
3.1 Electrical characteristics
Timing Diagram in Memory Expansion Mode and Microprocessor Mode (2)
t
WL(RD)
WL(WR)
t
RD,WR
0.5 VCC
t
d(AH-RD)
d(AH-WR)
t
t
v(RD-AH)
v(WR-AH)
t
0.5 VCC
AD15–AD
8
t
d(AL-RD)
d(AL-WR)
t
t
v(RD-AL)
v(WR-AL)
t
0.5 VCC
AD7
–AD
0
t
t
h(RD-ONW)
h(WR-ONW)
t
t
su(ONW-RD)
su(ONW-WR)
0.8 VCC
0.2 VCC
ONW
(At CPU reading)
RD
tWL(RD)
0.5 VCC
tSU(DB-RD)
th(RD-DB)
0.8 VCC
0.2 VCC
DB0–DB7
(At CPU writing)
WR
tWL(WR)
0.5 VCC
tv(WR-DB)
td(WR-DB)
0.5 VCC
DB0–DB7
Fig. 3.1.5 Timing diagram (in memory expansion mode and microprocessor mode) (2)
3806 GROUP USER’S MANUAL
3-24
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current characteristic examples
Figures 3.2.1 and Figure 3.2.2 show power source current characteristic examples.
[Measuring condition : 25 °C, A-D conversion stopped]
Rectangular waveform
Power source current
9
(mA)
Vcc = 5.5 V, Ta = 25 °C
8
7
6
5
4
3
2
1
0
Vcc = 4.0 V, Ta = 25 °C
Vcc = 2.7V, Ta = 25 °C
0
1
2
3
4
5
6
7
8
9
10
Frequency f(XIN) (MHz)
Fig. 3.2.1 Power source current characteristic example
[Measuring condition : 25 °C, A-D conversion stopped]
Rectangular waveform
Power source current
9
8
7
6
5
4
3
2
1
0
(mA)
Vcc = 5.5 V, Ta = 25 °C
Vcc = 4.0 V, Ta = 25 °C
Vcc = 2.7 V, Ta = 25 °C
0
1
2
3
4
5
6
7
8
9
10
Frequency f(XIN) (MHz)
Fig. 3.2.2 Power source current characteristic example (in wait mode)
3806 GROUP USER’S MANUAL
3-25
APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristic examples
Figures 3.2.3, Figure 3.2.4, Figure 3.2.5 and Figure 3.2.6 show port standard characteristic examples.
[Port P00 IOH–VOH characteristic (P-channel drive)]
(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P8)
IOH
(mA)
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
Vcc = 5.0 V
Ta = 85 °C
Vcc
Ta
=
4.0 V
=
85 °C
Vcc
=
2.7 V
Ta = 85 °C
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.5
VOH (V)
Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive (1)
[Port P00 IOH–VOH characteristic (P-channel drive)]
(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P8)
IOH
(mA)
–50
–45
–40
–35
–30
–25
–20
–15
–10
Vcc = 5.0 V
Ta = 25 °C
Vcc = 4.0 V
Ta = 25 °C
Vcc = 2.7 V
Ta = 25 °C
–5
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
OH (V)
Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive (2)
3806 GROUP USER’S MANUAL
3-26
APPENDIX
3.2 Standard characteristics
[Port P00 IOL–VOL characteristic (N-channel drive)]
(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7, P8)
IOL
(mA)
50
45
40
35
30
25
20
15
10
Vcc
Ta
=
5.0 V
=
85 °C
Vcc
Ta
=
=
4.0 V
85 °C
Vcc
Ta
=
=
2.7 V
85 °C
5
0
0
0.5 1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL (V)
Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive (1)
[Port P00 IOL–VOL characteristic (N-channel drive)]
(Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6, P7, P8)
IOL
(mA)
50
Vcc
=
5.0 V
45
40
35
30
25
20
15
10
Ta
= 25 °C
Vcc
Ta
=
4.0 V
= 25 °C
Vcc
Ta
=
=
2.7 V
25 °C
5
0
0
1.0
0.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
OL (V)
Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive (2)
3806 GROUP USER’S MANUAL
3-27
APPENDIX
3.2 Standard characteristics
3.2.3 A-D conversion standard characteristics
Figure 3.2.7 shows the A-D conversion standard characteristics.
The lower-side line on the graph indicates the absolute precision error. It represents the deviation from the
ideal value. For example, the conversion of output code from 0 to 1 occurs ideally at the point of AN0 =
10 mV, but the measured value is 0 mV. Accordingly, the measured point of conversion is represented as
“10 – 0 = 10 mV.”
The upper-side line on the graph indicates the width of input voltages equivalent to output codes. For
example, the measured width of the input voltage for output code 13 is 22 mV, so the differential nonlinear
error is represented as “22 – 20 = 2 mV” (0.1 LSB).
A-D CONVERTER STEP WIDTH MEASUREMENT
V
X
CC = 5.12 [V] , VREF = 5.12 [V]
IN = 4.80 [MH ] , ANALOG Port P6
Z
0
Temp. = 25deg.
1LSB WIDTH
30
20
30
20+1LSB
10
10
0
0
– 10
– 20
– 30
Absolute precision error
–1LSB
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
128
STEP No.
30
20
30
20+1LSB
10
10
0
0
– 10
– 20
– 30
–1LSB
128
136
144
152
160
168
176
184
192
200
208
216
224
232
240
248
256
STEP No.
Measured when a power source voltage is stable in the single-chip mode and the high-speed mode
Fig. 3.2.7 A-D conversion standard characteristics
3806 GROUP USER’S MANUAL
3-28
APPENDIX
3.2 Standard characteristics
3.2.4 D-A conversion standard characteristics
Figure 3.2.8 shows the D-A conversion standard characteristics. The lower-side line on the graph indicates
the absolute precision error. In this case, it represents the difference between the ideal analog output value
for an input code and the measured value.
The upper-side line on the graph indicates the change width of output analog value to a one-bit change
of input code.
D-A CONVERTER STEP WIDTH MEASUREMENT
V
X
CC = 5.12 [V] , VREF = 5.12 [V]
IN = 4.80 [MH ] , ANALOG OUTPUT
Z
DA
Temp. = 25deg.
1LSB WIDTH
30
20
30
20+1LSB
10
10
0
0
– 10
– 20
– 30
Absolute precision error
–1LSB
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
128
STEP No.
30
20
30
20+1LSB
10
0
10
0
– 10
– 20
– 30
–1LSB
128
136
144
152
160
168
176
184
192
200
208
216
224
232
240
248
256
STEP No.
Measured when a power source voltage is stable in the single-chip mode and the high-speed mode
Fig. 3.2.8 D-A conversion standard characteristics
3806 GROUP USER’S MANUAL
3-29
APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Sequence for switching an external interrupt
detection edge
Clear an interrupt enable bit to “0” (interrupt disabled)
Switch the detection edge
When the external interrupt detection edge must be
switched, make sure the following sequence.
Reason
Clear an interrupt request bit to “0” (no interrupt requ-
est issued)
The interrupt circuit recognizes the switching of the
detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
Set the interrupt enable bit to “1” ( interrupt enabled )
(2) Bit 7 of the interrupt control register 2
Fix the bit 7 of the interrupt control register 2
(Address:003F16) to “0”.
b7
b0
Interrupt control register 2
Address 003F16
0
Figure 3.3.1 shows the structure of the interrupt
control register 2.
Interrupt enable bits
Not used
Fix this bit to “0”
Fig. 3.3.1 Structure of interrupt control register 2
3.3.2 Notes on the serial I/O1
(1) Stop of data transmission
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
the transmit enable bit to “0” (transmit disabled), and clear the serial I/O enable bit to “0” (serial I/O1 disabled)in
the following cases :
● when stopping data transmission during transmitting data in the clock synchronous serial I/O mode
● when stopping data transmission during transmitting data in the UART mode
● when stopping only data transmission during transmitting and receiving data in the UART mode
Reason
Since transmission is not stopped and the transmission circuit is not initialized even if the serial I/O1 enable bit
is cleared to “0” (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK1,
______
and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer
register in this state, the data is transferred to the transmit shift register and start to be shifted. When the serial
I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and ti may cause
an operation failure to a microcomputer.
(2) Stop of data reception
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial I/O disabled) in the
following case :
● when stopping data reception during receiving data in the clock synchronous serial I/O mode
Clear the receive enable bit to “0” (receive disabled) in the following cases :
● when stopping data reception during receiving data in the UART mode
● when stopping only data reception during transmitting and receiving data in the UART mode
3806 GROUP USER’S MANUAL
3-30
APPENDIX
3.3 Notes on use
(3) Stop of data transmission and reception in a clock synchronous serial I/O mode
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) at the same time in the
following case:
● when stopping data transmission and reception during transmitting and receiving data in the clock synchronous
mode (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of
transmission and reception is disabled, a bit error occurs because transmission and reception cannot be
synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the
transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the
transmission circuit is not initialized by clearing the serial I/O1 enable bit to “0” (serial I/O1 disabled) (refer to (1)).
_____
(4) The SRDY pin on a receiving side
_____
When signals are output from the SRDY pin on the reception side by using an external clock in the clock
_____
synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and the transmit enable
bit to “1” (transmit enabled).
(5) Stop of data reception in a clock synchronous
Clear both the transmit
serial I/O mode
Set the serial I/O1 control register again after the
transmission and the reception circuits are reset by
enable bit (TE) and the
receive enable bit (RE) to “0”
clearing both the transmit enable bit and the receive
enable bit to “0.”
Set the bits 0 to 3 and bit 6 of
the serial I/O1 control
register
Can be set with the
LDM instruction at
the same time
Set both the transmit enable
bit (TE) and the receive
enable bit (RE) to “1”
(6) Control of data transmission using the transmit shift completion flag
The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When checking
the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data
transmission, note this delay.
(7) Control of data transmission using an external clock
When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1”
at “H” level of the SCLK input signal. Also, write data to the transmit buffer register at “H” level of the SCLK input
signal.
3.3.3 Notes on the A-D converter
(1) Input of signals from signal source with high impedance to an analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor
of 0.01 µF to 1 µF. Further, maek sure to check the operation of application products on the user side.
Reason
The A-D converter builds in the capacitor for analog voltage comparison. Accordingly, when signals from signal
source with high impedance are input to an analog input pin, a charge and discharge noise generates. This may
cause the A-D conversion precision to be worse.
3806 GROUP USER’S MANUAL
3-31
APPENDIX
3.3 Notes on use
(2) AVSS pin
Connect a power source for the A-D converter, AVSS pin to the VSS line of the analog circuit.
(3) A clock frequency during an A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is
too low. Thus, make sure the following during an A-D conversion.
● f(XIN) is 500 kHz or more .
(When the ONW pin is "L", f(XIN) is 1 MHz or more.)
● Do not execute the STP instruction and WIT instruction.
3.3.4 Notes on the RESET pin
When a rising time of the reset signal is long, connect a ceramic capacitor or others across the RESET pin and
the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, make
sure the following :
●Make the length of the wiring which is connected to a capacitor the shortest possible.
●Make sure to check the operation of application products on the user side.
Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, a microcomputer may
malfunction.
3.3.5 Notes on input and output pins
(1) Fix of a port input level in stand-by state
Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state, especially
for the I/O ports of the N-channel open-drain.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor.
When determining a resistance value, make sure the following:
●External circuit
●Variation of output levels during the ordinary operation
* stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
Reason
Even when setting as an output port with its direction register, in the following state :
●N-channel......when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the
level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of an input and an I/O port are “undefined.” This may cause power source current.
(2) Modify of the content of I/O port latch
When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the
unspecified bit may be changed.
Reason
The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit.
Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed
to all bits of the port latch.
●As for a bit which is set as an input port : The pin state is read in the CPU, and is written to this bit after bit
managing.
●As for a bit which is set as an output port : The bit value is read in the CPU, and is written to this bit after bit
managing.
3806 GROUP USER’S MANUAL
3-32
APPENDIX
3.3 Notes on use
Make sure the following :
●Even when a port which is set as an output port is changed for an input port, its port latch holds the output data.
●Even when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction,
its value may be changed in case where content of the pin differs from a content of the port latch.
* bit managing instructions : SEB and CLB instruction
(3) The AVSS pin when not using the A-D converter
When not using the A-D converter, handle a power source pin for the A-D converter, AVSS pin as follows :
● AVSS : Connect to the VSS pin
Reason
If the AVSS pin is opened, the microcomputer may malfunction by effect of noise or others.
3.3.6 Notes on memory expansion mode and microprocessor mode
(1) Writing data to the port latch of port P3
In the memory expansion or the microprocessor mode, ports P30 and P31 can be used as the output port. Use the
LDM or STA instruction for writing data to the port latch (address 000616) of port P3.
When using a read-modify-write instruction (the SEB or the CLB instruction), allocate the read and the write
enabled memory at address 000616.
Reason
In the memory expansion or microprocessor mode, address 000616 is allocated in the external area.
Accordingly,
● Data is read from the external memory.
● Data is written to both the port latch of the port P3 and the external memory.
Accordingly, when executing a read-modify-write instruction for address 000616, external memory data is read and
modified, and the result is written in both the port latch of the port P3 and the external memory. If the read enabled
memory is not allocated at address 000616, the read data is undefined. The undefined data is modified and written
to the port latch of the port P3. The port latch data of port P3 becomes “undefined.”
(2) Overlap of an internal memory and an external memory
When the internal and the external memory are overlapped in the memory expansion mode, the internal memory
is valid in this overlapped area. When the CPU writes or reads to this area, the following is performed :
● When reading data
Only the data in the internal memory is read into the CPU and the data in the external memory is not read into
the CPU. However, as the read signal and address are still valid, the external memory data of the
corresponding address is output to the external data bus.
● When writing data
Data is written in both the internal and the external memory.
3806 GROUP USER’S MANUAL
3-33
APPENDIX
3.3 Notes on use
3.3.7 Notes on built-in PROM
(1) Programming adapter
To write or read data into/from the internal PROM, use the dedicated programming adapter and general-purpose
PROM programmer as shown in Table 3.3.1.
Table 3.3.1 Programming adapter
Microcomputer
M38063E6FS
Programming adapter
PCA4738L-80A
PROM mode
256K
M38063E6FP
PCA4738F-80A
(one-time blank)
M38063E6GP
PCA4738G-80A
PCA4738L-80A
(one-time blank)
M38067ECAFS
M38067ECFP
(one-time blank)
M38067ECDFP
(one-time blank)
M38067ECAFP
(one-time blank)
M38067ECGP
(one-time blank)
M38067ECAGP
(one-time blank)
PCA4738F-80A
PCA4738G-80A
1M
(2) Write and read
In PROM mode, operation is the same as that of the M5M27C256AK and the M5M27C101, but programming
conditions of PROM programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data write/read. Take care not to apply 21 V to Vpp pin (is also used as
the CNVSS pin), or the product may be permanently damaged.
● Programming voltage : 12.5 V
● Setting of programming adapter switch : refer to table 3.3.2
● Setting of PROM programmer address : refer to table 3.3.3
Table 3.3.2 Setting of programming adapter switch
SW 1
SW 2
SW 3
OFF
Programming adapter
PCA4738F-80A
CMOS
CMOS
PCA4738L-80A
PCA4738G-80A
3806 GROUP USER’S MANUAL
3-34
APPENDIX
3.3 Notes on use
Table 3.3.3 Setting of PROM programmer address
Microcomputer
M38063E6FS
M38063E6FP
M38063E6GP
M38067ECFP
M38067ECGP
M38067ECDFP
M38067ECAFS
M38067ECAFP
M38067ECAGP
PROM programmer start address
PROM programmer completion address
Address : 208016 (Note 1)
Address : 7FFD16 (Note 1)
Address : 408016 (Note 2)
Address : FFFD16 (Note 2)
Note1 : Addresses A08016 to FFFD16 in the internal PROM correspond to addresses 208016 to 7FFD16 in the
ROM programmer.
2 : Addresses 408016 to FFFD16 in the internal PROM correspond to addresses 408016 to FFFD16 in the
ROM programmer.
(3) Erasing
Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537-
Angstrom . At least 15 W-sec/cm2 are required to erase EPROM contents.
3806 GROUP USER’S MANUAL
3-35
APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against noise in
theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Wiring for the RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor
across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm).
Reason
The reset works to initialize a microcomputer.
The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having
a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state
of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset
circuit
Reset
circuit
RESET
RESET
V
SS
V
SS
V
SS
V
SS
3806 group
3806 group
N.G.
O.K.
Fig. 3.4.1 Wiring for the RESET pin
(2) Wiring for clock input/output pins
●Make the length of wiring which is connected to clock I/O pins as short as possible.
●Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an
oscillatorand the VSS pin of a microcomputer as short as possible.
●Separate the VSS pattern only for oscillation from other VSS patterns.
Reason
A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock
I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway.
Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level
of an oscillator, the correct clock will not be input in the microcomputer.
3806 GROUP USER’S MANUAL
3-36
APPENDIX
3.4 Countermeasures against noise
An example of VSS patterns on the
underside of a printed circuit board
Noise
Oscillator wiring
pattern example
X
X
V
IN
X
X
V
IN
X
X
V
IN
OUT
SS
OUT
SS
OUT
SS
Separate the VSS line for oscillation from other V SS lines
N.G.
O.K.
Fig. 3.4.2 Wiring for clock I/O pins
(3) Wiring for the VPP pin of the One Time PROM
version and the EPROM version
(In this microcomputer the VPP pin is also used
as the CNVSS pin)
Approximately
Connect an approximately 5 kΩ resistor to theVPP
pin the shortest possible in series and also to the VSS
pin. When not connecting the resistor, make the
length of wiring between the VPP pin and the VSS pin
the shortest possible.
5kΩ
CNVSS/VPP
V
SS
Note:Even when a circuit which inclued an
approximately 5 kΩ resistor is used in the Mask ROM
version, the maicrocomputer operates correctly.
3806 group
Make it the shortest possible
Reason
Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM
and the EPROM version
The VPP pin of the One Time PROM and the EPROM
version is the power source input pin for the built-in
PROM. When programming in the built-in PROM,
the impedance of the VPP pin is low to allow the
electric current for wiring flow into the PROM. Be-
cause of this, noise can enter easily. If noise enters
the VPP pin, abnormal in struction codes or data are
read from the built-in PROM, which may cause a
program runaway.
3.4.2 Connection of a bypass capacitor across the
Vss line and the Vcc line
Connect an approximately 0.1 µF bypass capacitor
across the VSS line and the VCC line as follows:
●Connect a bypass capacitor across the VSS pin
and the VCC pin at equal length .
●Connect a bypass capacitor across the VSS pin
and the VCC pin with the shortest possible wiring.
●Use lines with a larger diameter than other signal
lines for VSS line and VCC line.
V
V
CC
Chip
V
CC
V
SS
SS
Fig. 3.4.4 Bypass capacitor across the VSS line and
the VCC line
3806 GROUP USER’S MANUAL
3-37
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
●Connect an approximately 100 Ω to 1 kΩ resistor to an
analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to
the microcomputer as close as possible.
●Connect an approximately 1000 pF capacitor across
the VSS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as
possible. Also, connect the capacitor across the
analog input pin and the VSS pin at equal length.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
Reason
Signals which is input in an analog input pin (such as
an A-D converter input pin) are usually output signals
from sensor. The sensor which detects a change of
event is installed far from the printed circuit board
with a microcomputer, the wiring to an analog input
pin is longer necessarily. This long wiring functions
as an antenna which feeds noise into the
microcomputer, which causes noise to an analog
input pin.
N.G.
O.K.
V
SS
Note:The resistor is for dividing resistance
with a thermister.
Fig.3.4.5 Analog signal line and a resistor and a
capacitor
3.4.4. Consideration for oscillator
Take care to prevent an oscillator that generates
clocks for a microcomputer operation from being
affected by other signals.
Microcomputer
Mutual inductance
M
(1) Keeping an oscillator away from large current
signal lines
X
X
IN
Large
current
OUT
Install a microcomputer (and especially an oscillator)
as far as possible from signal lines where a current
larger than the tolerance of current value flows.
V
SS
GND
Fig.3.4.6 Wiring for a large current signal line
Reason
In the system using a microcomputer, there are
signal lines for controlling motors, LEDs, and thermal
heads or others. When a large current flows through
those signal lines, strong noise occurs because of
mutual inductance.
(2) Keeping an oscillator away from signal lines
where potential levels change frequently
Install an oscillator and a connecting pattern of an
osillator away from signal lines where potential levels
change frequently. Also, do not cross such signal
lines over the clock lines or the signal lines which are
sensitive to noise.
CNTR
Do not cross
X
X
V
IN
OUT
SS
Reason
Signal lines where potential levels change frequently
(such as the CNTR pin line) may affect other lines at
signal rising or falling edge. If such lines cross over
a clock line, clock waveforms may be deformed,
which causes a microcomputer failure or a program
runaway.
Fig.3.4.7 Wiring to a signal line where potential levels
change frequently
3806 GROUP USER’S MANUAL
3-38
APPENDIX
3.4 Countermeasures against noise
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
Noise
O.K.
<Hardware>
Data bus
●Connect a resistor of 100 Ω or more to an I/O port
inseries.
Noise
Direction register
Port latch
N.G.
<Software>
●As for an input port, read data several times by a
program for checking whether input levels are
equal or not.
I/O port
pins
●As for an output port, since the output data may
reverse because of noise, rewrite data to its port
latch at fixed periods.
●Rewirte data to direction registers and pull-up
control registers (only the product having it) at fixed
periods.
Fig. 3.4.8 Setup for I/O ports
When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be
output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse.
3.4.6 Providing of watchdog timer function by
software
If a microcomputer runs away because of noise or
others, it can be detected by a software watchdog
Interrupt processing routine
(SWDT) ← (SWDT)—1
Interrupt processing
Main routine
timer and the microcomputer can be reset to normal
operation. This is equal to or more effective than
program runaway detection by a hardware watchdog
timer. The following shows an example of a watchdog
timer provided by software.
(SWDT)← N
CLI
In the following example, to reset a microcomputer to
normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt
processing routine detects errors of the main routine.
This example assumes that interrupt processing is
repeated multiple times in a single main routine
processing.
Main processing
>0
(SWDT)
≤0?
RTI
N
≤0
(SWDT)
=N?
Return
=N
Interrupt processing
routine errors
Main routine
errors
<The main routine>
●Assigns a single byte of RAM to a software watchdog
timer (SWDT) and writes the initial value N in the
SWDT once at each execution of the main routine.
The initial value N should satisfy the following
condition:
Fig. 3.4.9 Watchdog timer by software
N+1 ≥ (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the initial value N
should have a margin.
●Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of
interrupt processing count after the initial value N has been set.
●Detects that the interrupt processing routine has failed and determines to branch to the program initialization
routine for recovery processing in the following cases:
If the SWDT contents do not change after interrupt processing
3806 GROUP USER’S MANUAL
3-39
APPENDIX
3.4 Countermeasures against noise
<The interrupt processing routine>
●Decrements the SWDT contents by 1 at each interrupt processing.
●Determins that the main routine operates normally when the SWDT contents are reset to the initial value N at
almost fixed cycles (at the fixed interrupt processing count).
●Detects that the main routine has failed and determines to branch to the program initialization routine for recovery
processing in the following case:
When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value
N .
3806 GROUP USER’S MANUAL
3-40
APPENDIX
3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1016]
At reset
B
Name
Function
R W
Port Pi0
Port Pi1
0
1
2
3
4
5
6
7
●
●
In output mode
?
Write
Read
Port latch
?
?
?
?
?
?
?
In input mode
Port Pi2
Port Pi3
Write : Port latch
Read : Value of pins
Port Pi4
Port Pi5
Port Pi6
Port Pi7
Fig. 3.5.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16, 0F16, 1116
]
Name
Function
input mode
output mode
B
0
At reset R W
0 : Port Pi
1 : Port Pi
0
0
Port Pi direction register
✕
✕
✕
0
0
0
0
0
0
0
0
0 : Port Pi
1 : Port Pi
1
1
input mode
output mode
1
2
3
4
5
6
7
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
input mode
output mode
0 : Port Pi
1 : Port Pi
3
3
✕
✕
✕
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
✕
✕
0 : Port Pi
1 : Port Pi
7
7
input mode
output mode
Fig. 3.5.2 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6, 7, 8)
3806 GROUP USER’S MANUAL
3-41
APPENDIX
3.5 List of registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 1816]
At reset
Function
B
0
R W
A transmission data is written to or a receive data is read out
from this buffer register.
?
• At writing : a data is written to the transmit buffer register.
• At reading : a content of the receive buffer register is read out.
1
2
3
4
5
6
?
?
?
?
?
?
?
7
Fig. 3.5.3 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status reigster (SIO1STS) [Address : 1916]
At reset
Name
Transmit buffer empty flag
(TBE)
Function
0 : Buffer full
1 : Buffer empty
B
0
R W
✕
0
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
✕
✕
✕
✕
✕
✕
Receive buffer full flag (RBF)
1
2
3
4
5
6
0
0
0
0
0
0
Transmit shift register shift
completion flag (TSC)
0 : No error
1 : Overrun error
0 : No error
1 : Parity error
Overrun error flag (OE)
Parity error flag (PE)
0 : No error
1 : Framing error
0 : (OE) (PE) (FE) = 0
1 : (OE) (PE) (FE) = 1
Framing error flag (FE)
Summing error flag (SE)
Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is “0.”
✕
7
1
Fig. 3.5.4 Structure of Serial I/O1 status register
3806 GROUP USER’S MANUAL
3-42
APPENDIX
3.5 List of registers
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A16]
At reset
Name
BRG count source
selection bit (CSS)
Function
B
0
R W
0 : f(XIN)
1 : f(XIN)/4
0
Serial I/O1
synchronous clock
selection bit (SCS)
0
At selecting clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
At selecting UART
1
0 : BRG output divided by 16
1 : External clock input divided by 16
SRDY1 output enable bit
(SRDY)
0 : I/O port (P47)
2
3
0
0
1 : SRDY1 output pin
0 : Transmit buffer empty
1 : Transmit shift operating
completion
Transmit interrupt
source selection bit
(TIC)
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0
0
Transmit enable bit (TE)
4
5
6
7
Receive enable bit (RE)
Serial I/O1 mode
selection bit (SIOM)
0 : UART
1 : Clock synchronous serial I/O
0
0
0 : Serial I/O1 disabled
(P44–P47 : I/O port)
Serial I/O1 enable bit
(SIOE)
1 : Serial I/O1 enabled
(P44–P47 : Serial I/O function pin)
Fig. 3.5.5 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B16
]
At reset
Name
B
Function
R W
0 : 8 bits
1 : 7 bits
Character length
selection bit (CHAS)
0
0
Parity enable bit
(PARE)
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1
0
0
Parity selection bit
2
(PARS)
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
In output mode
0 : CMOS output
1 : N-channel open-drain
output
Stop bit length selection
3
0
0
bit (STPS)
P45/TxD P-channel
4
output disable bit
(POFF)
5
6
7
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “1.”
✕
✕
✕
1
1
1
Fig. 3.5.6 Structure of UART control register
3806 GROUP USER’S MANUAL
3-43
APPENDIX
3.5 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C16
]
At reset
B
Function
A count value of Baud rate generator is set.
R W
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
Fig. 3.5.7 Structure of Baud rate generator
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register (SIO2CON) [Address : 1D16
]
At reset
Name
Function
R W
B
0
b2 b1 b0
0
Internal synchronous
clock selection bits
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(XIN)/8
1 : f(XIN)/16
0 : f(XIN)/32
1 : f(XIN)/64
0 : f(XIN)/128
1 : f(XIN)/256
0
1
2
3
4
5
6
7
0
0
0
1
0
1
0
1
0
1
:
:
:
:
:
:
:
:
I/O port (P71, P72)
Serial I/O2 port selection bit
S
OUT2, SCLK2 output pin
I/O port (P7
RDY2 output pin
3)
S
RDY2 output enable bit
0
S
Transfer direction
selection bit
Serial I/O2 synchronous clock
LSB first
MSB first
0
0
External clock
Internal clock
selection bit
Nothing is allocated for this bit. This is write disabled bit. When
this bit is read out, the value is “0.”
✕
0
Fig. 3.5.8 Structure of Serial I/O2 control register
3806 GROUP USER’S MANUAL
3-44
APPENDIX
3.5 List of registers
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 1F16]
Function
At reset
R W
B
A shift register for serial transmission and reception.
At transmitting : Set a transmission data.
● At receiving : Store a reception data.
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
●
Fig. 3.5.9 Structure of Serial I/O2 register
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)
[Address : 2016, 2416, 2616
]
At reset
Function
R W
B
●
The count value of each prescaler is set.
The value set in this register is written to both the prescaler and
the prescaler latch at the same time.
When the prescaler is read out, the value (count value) of the
prescaler is read out.
0
1
2
3
4
5
6
7
1
●
1
1
1
1
1
1
1
●
Fig. 3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y
3806 GROUP USER’S MANUAL
3-45
APPENDIX
3.5 List of registers
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2116]
At reset
Function
B
R W
●
The count value of the Timer 1 is set.
The value set in this register is written to both the Timer 1 and
the Timer 1 latch at the same time.
When the Timer 1 is read out, the value (count value) of the
Timer 1 is read out.
0
1
2
3
4
5
6
7
1
●
0
0
0
0
0
0
0
●
Fig. 3.5.11 Structure of Timer 1
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2), Timer X (TX), Timer Y (TY)
[Address : 2216, 2516, 2716]
B
0
At reset
Function
The count value of each timer is set.
The value set in this register is written to both the Timer and the
R W
●
1
●
Timer latch at the same time.
When the Timer is read out, the value (count value) of the Timer
is read out.
1
2
3
4
5
6
7
1
1
1
1
1
1
1
●
Fig. 3.5.12 Structure of Timer 2, Timer X, Timer Y
3806 GROUP USER’S MANUAL
3-46
APPENDIX
3.5 List of registers
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register (TM) [Address : 2316]
Name
At reset
B
0
R
Function
W
b1 b0
Timer X operating mode
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
It depends on the operating mode
of the Timer X (refer to Table 3.5.1).
CNTR0 active edge switch
bit
Timer X count stop bit
0 : Count start
1 : Count stop
b5 b4
Timer Y operating mode
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
It depends on the operating mode
of the Timer Y (refer to Table 3.5.1 ).
CNTR1 active edge switch
bit
Timer Y count stop bit
0 : Count start
1 : Count stop
Fig. 3.5.13 Structure of Timer XY mode register
Table. 3.5.1 Function of CNTR0/CNTR1 edge switch bit
Operating mode of
Function of CNTR0/CNTR1 edge switch bit (bits 2 and 6)
Timer X/Timer Y
Timer mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
(No effect on timer count)
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
(No effect on timer count)
• Start of pulse output : From “H” level
Pulse output mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Start of pulse output : From “L” level
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
• Timer X/Timer Y : Count of rising edge
Event counter mode
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Timer X/Timer Y : Count of falling edge
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
• Timer X/Timer Y : Measurement of “H” level width
• Generation of CNTR0/CNTR1 interrupt request : Falling edge
• Timer X/Timer Y : Measurement of “L” level width
• Generation of CNTR0/CNTR1 interrupt request : Rising edge
Pulse width measurement mode
3806 GROUP USER’S MANUAL
3-47
APPENDIX
3.5 List of registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA control register (ADCON) [Address : 3416
]
At reset
B
Name
Function
R W
b2 b1 b0
0
Analog input pin selection bits
0
1
2
3
0 0 0 : P6
0
1
2
3
4
5
6
7
/AN
0
1
2
3
4
5
6
7
0 0 1 : P6
0 1 0 : P6
0 1 1 : P6
1 0 0 : P6
1 0 1 : P6
1 1 0 : P6
1 1 1 : P6
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
0
1
0 : Conversion in progress
1 : Conversion completed
AD conversion completion bit
✕
✕
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
4
5
0
0
0 : DA
1 : DA
1
1
output disable
output enable
0
DA
1
output enable bit
6
0 : DA
1 : DA
2
2
output disabled
output enabled
DA
2
output enable bit
0
7
Fig. 3.5.14 Structure of AD/DA control register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (AD) [Address : 3516
]
At reset
R W
✕
B
Function
0
1
2
3
4
5
6
7
?
?
?
?
?
?
?
?
The read-only register which A-D conversion results are stored.
✕
✕
✕
✕
✕
✕
✕
Fig. 3.5.15 Structure of A-D conversion register
3806 GROUP USER’S MANUAL
3-48
APPENDIX
3.5 List of registers
D-A1 conversion register, D-A2 conversion register
b7 b6 b5 b4 b3 b2 b1 b0
D-A1 conversion register (DA1), D-A2 conversion register (DA2)
[Address : 3616, 3716]
At reset
B
0
Function
An output value of each D-A converter is set.
R W
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Fig. 3.5.16 Structure of D-A 1 conversion, D-A 2 conversion register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16
]
At reset
Name
interrupt edge
selection bit
INT interrupt edge
selection bit
Function
B
0
R W
0
INT
0
0 : Falling edge active
1 : Rising edge active
0
1
0 : Falling edge active
1 : Rising edge active
1
2
3
4
5
0
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
✕
0
0
0
INT
selection bit
INT interrupt edge
selection bit
INT interrupt edge
selection bit
2 interrupt edge
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
3
0 : Falling edge active
1 : Rising edge active
4
0
6
7
Nothing is allocated for these bits. These are write disabled
bits. When these bits are read out, the values are “0.”
✕
✕
0
Fig. 3.5.17 Structure of Interrupt edge selection register
3806 GROUP USER’S MANUAL
3-49
APPENDIX
3.5 List of registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address : 3B16
]
At reset
Name
Function
B
0
R W
0
Processor mode bits
00 :Single-chip mode
01 :Memory expansion mode
10 :Microprocessor mode
11 :Not available
✻
1
2
0 :0 page
1 :1 page
0
Stack page selection bit
0
0
0
0
0
3
4
5
6
7
✕
✕
✕
✕
✕
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0.”
✻An initial value of bit 1 is determined by a level of the CNVSS pin.
Fig. 3.5.18 Structure of CPU mode register
3806 GROUP USER’S MANUAL
3-50
APPENDIX
3.5 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 1 (IREQ1) [Address : 3C16]
At reset
Name
Function
0 : No interrupt request
1 : Interrupt request
R W
B
0
INT0 interrupt request bit
✻
✻
✻
0
0
0
0 : No interrupt request
1 : Interrupt request
INT1 interrupt request bit
1
2
0 : No interrupt request
1 : Interrupt request
Serial I/O1 receive interrupt
request bit
0 : No interrupt request
1 : Interrupt request
Serial I/O1 transmit interrupt
request bit
3
✻
0
0
0
0
0
0 : No interrupt request
1 : Interrupt request
Timer X interrupt request
bit
✻
✻
✻
✻
4
5
6
7
0 : No interrupt request
1 : Interrupt request
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
“0” is set by software, but not “1.”
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
✻
Fig. 3.5.19 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request reigster 2 (IREQ2) [Address : 3D16
]
At reset
Name
B
Function
R W
0 : No interrupt request
1 : Interrupt request
✻
CNTR
0
interrupt request bit
0
1
2
3
4
5
6
7
0
0 : No interrupt request
1 : Interrupt request
CNTR
1
interrupt request bit
✻
✻
✻
0
0
0
0
0
0
Serial I/O2 interrupt request
bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
INT
2
interrupt request bit
interrupt request bit
interrupt request bit
INT
3
✻
✻
✻
0 : No interrupt request
1 : Interrupt request
INT
4
AD conversion interrupt
request bit
0 : No interrupt request
1 : Interrupt request
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
✕
0
✻
“0” is set by software, but not “1.”
Fig. 3.5.20 Structure of Interrupt request register 2
3806 GROUP USER’S MANUAL
3-51
APPENDIX
3.5 List of registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E16]
At reset
Name
Function
0 : Interrupt disabled
1 : Interrupt enabled
R W
B
0
INT0 interrupt enable bit
0
0 : Interrupt disabled
1 : Interrupt enabled
INT1 interrupt enable bit
1
2
3
0
0
0
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 receive interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 transmit interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
4
5
6
7
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 3.5.21 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address : 3F16
]
At reset
Name
B
Function
R W
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
CNTR
0
interrupt enable bit
0
1
2
3
4
5
6
7
0
CNTR
1
interrupt enable bit
0
0
0
0
0
0
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O2 interrupt enable bit
INT
INT
2
3
interrupt enable bit
interrupt enable bit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
INT
4
0 : Interrupt disabled
1 : Interrupt enabled
AD conversion interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fix this bit to “0.”
Fig. 3.5.22 Structure of Interrupt control register 2
3806 GROUP USER’S MANUAL
3-52
APPENDIX
3.6 Mask ROM ordering method
3.6 Mask ROM ordering method
GZZ-SH03-63B<07B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38062M3-XXXFP/GP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38062M3-XXXFP
M38062M3-XXXGP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address D08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M38062M3–’
ASCII code :
‘M38062M3–’
000F16
001016
000F16
001016
507F16
508016
D07F16
D08016
data
data
ROM 12158 bytes
ROM 12158 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘2’ = 3216
‘M’ = 4D16
‘3’ = 3316
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M38062M3–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-53
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-80B<16A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38062M3DXXXFP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address D08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
EPROM address
000016
000016
Product name
ASCII code :
‘M38062M3D’
Product name
ASCII code :
‘M38062M3D’
000F16
001016
000F16
001016
507F16
508016
D07F16
D08016
data
data
ROM 12158 bytes
ROM 12158 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘2’ = 3216
‘M’ = 4D16
‘3’ = 3316
‘D’ = 4416
FF16
(2) The ASCII codes of the product name “M38062M3D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-55
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-26B<13B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38062M4-XXXFP/GP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38062M4-XXXFP
M38062M4-XXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address C08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M38062M4–’
ASCII code :
‘M38062M4–’
000F16
001016
000F16
001016
407F16
408016
C07F16
C08016
data
data
ROM 16254 bytes
ROM 16254 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘2’ = 3216
‘M’ = 4D16
‘4’ = 3416
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M38062M4–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-57
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-81B<16A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38062M4DXXXFP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address C08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
EPROM address
000016
000016
Product name
ASCII code :
‘M38062M4D’
Product name
ASCII code :
‘M38062M4D’
000F16
001016
000F16
001016
407F16
408016
C07F16
C08016
data
data
ROM 16254 bytes
ROM 16254 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘2’ = 3216
‘M’ = 4D16
‘4’ = 3416
‘D’ = 4416
FF16
(2) The ASCII codes of the product name “M38062M4D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-59
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH03-26B<9ZC0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38063M6-XXXFP/GP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38063M6-XXXFP
M38063M6-XXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address A08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M38063M6–’
ASCII code :
‘M38063M6–’
000F16
001016
000F16
001016
207F16
208016
A07F16
A08016
data
data
ROM 24446 bytes
ROM 24446 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘3’ = 3316
‘M’ = 4D16
‘6’ = 3616
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M38063M6–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-61
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-64B<36B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38063M6AXXXFP/GP/HP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38063M6AXXXFP
M38063M6AXXXGP
M38063M6AXXXHP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address A08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
EPROM address
000016
Product name
Product name
ASCII code :
‘M38063M6A’
ASCII code :
‘M38063M6A’
000F16
001016
000F16
001016
207F16
208016
A07F16
A08016
data
data
ROM 24446 bytes
ROM 24446 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘3’ = 3316
‘M’ = 4D16
‘6’ = 3616
‘A’ = 4116
FF16
(2) The ASCII codes of the product name “M38063M6A”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-63
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-72B<15A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38063M6DXXXFP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer, the internal ROM
area is from address A08016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
EPROM address
000016
000016
Product name
ASCII code :
‘M38063M6D’
Product name
ASCII code :
‘M38063M6D’
000F16
001016
000F16
001016
207F16
208016
A07F16
A08016
data
data
ROM 24446 bytes
ROM 24446 bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘3’ = 3316
‘M’ = 4D16
‘6’ = 3616
‘D’ = 4416
FF16
(2) The ASCII codes of the product name “M38063M6D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-65
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-87B<17B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38067M8-XXXFP/GP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38067M8-XXXFP
M38067M8-XXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 808016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
ASCII code :
‘M38067M8–’
000F16
001016
807F16
808016
data
ROM 32638 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘8’ = 3816
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M38067M8–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-67
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-63B<36B0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38067M8AXXXFP/GP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38067M8AXXXFP
M38067M8AXXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 808016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
ASCII code :
‘M38067M8A’
000F16
001016
807F16
808016
data
ROM 32638 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘8’ = 3816
‘A’ = 4116
FF16
(2) The ASCII codes of the product name “M38067M8A”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-69
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH04-89B<17A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38067M8DXXXFP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 808016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
ASCII code :
‘M38067M8D’
000F16
001016
807F16
808016
data
ROM 32638 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘8’ = 3816
‘D’ = 4416
FF16
(2) The ASCII codes of the product name “M38067M8D”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-71
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-53B<35A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38067MC-XXXFP/GP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38067MC-XXXFP
M38067MC-XXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
ASCII code :
‘M38067MC–’
000F16
001016
407F16
408016
data
ROM 49022 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘C’ = 4316
‘ – ’ = 2D16
FF16
(2) The ASCII codes of the product name “M38067MC–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16. The
ASCII codes and addresses are listed to the right in
hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-73
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-66B<36A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38067MCAXXXFP/GP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M38067MCAXXXFP
M38067MCAXXXGP
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
ASCII code :
‘M38067MCA’
000F16
001016
407F16
408016
data
ROM 49022 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘C’ = 4316
‘A’ = 4116
FF16
(2) The ASCII codes of the product name “M38067MCA”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-75
APPENDIX
3.6 Mask ROM ordering method
GZZ-SH07-54B<35A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38067MCDXXXFP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
(hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27512
In the address space of the microcomputer, the internal ROM
area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
ASCII code :
‘M38067MCD’
000F16
001016
407F16
408016
data
ROM 49022 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘0’ = 3016
‘6’ = 3616
‘7’ = 3716
‘M’ = 4D16
‘C’ = 4316
‘D’ = 4416
FF16
(2) The ASCII codes of the product name “M38067MCD”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
3806 GROUP USER’S MANUAL
3-77
APPENDIX
3.7 Mark specification form
3.7 Mark specification form
3806 GROUP USER’S MANUAL
3-79
APPENDIX
3.7 Mark specification form
3806 GROUP USER’S MANUAL
3-80
APPENDIX
3.8 Package outline
3.8 Package outline
3806 GROUP USER’S MANUAL
3-81
APPENDIX
3.8 Package outline
3806 GROUP USER’S MANUAL
3-82
APPENDIX
3.9 List of instruction codes
3.9 List of instruction codes
D3 – D0
0000
0
0001
0010
0011
0100
4
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
C
1101
D
1110
E
1111
F
Hexadecimal
notation
1
2
3
D7 – D4
0000
ORA
JSR
BBS
ORA
ZP
ASL
ZP
BBS
0, ZP
ORA
IMM
ASL
A
SEB
0, A
ORA
ABS
ASL
ABS
SEB
0, ZP
BRK
—
PHP
CLC
PLP
SEC
PHA
CLI
—
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IND, X ZP, IND 0, A
ORA
IND, Y
BBC
0, A
ORA
ASL
BBC
ORA
ABS, Y
DEC
A
CLB
0, A
ORA
ASL
CLB
BPL
JSR
CLT
—
—
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ZP, X ZP, X 0, ZP
ABS, X ABS, X 0, ZP
AND
ABS IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
AND
ABS
ROL
ABS
SEB
1, ZP
AND
BMI
BBC
1, A
AND
ROL
BBC
AND
ABS, Y
INC
A
CLB
1, A
LDM
ZP
AND
ROL
CLB
SET
STP
—
IND, Y
ZP, X ZP, X 1, ZP
ABS, X ABS, X 1, ZP
EOR
RTI
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
EOR
ABS
LSR
ABS
SEB
2, ZP
IND, X
EOR
BVC
BBC
2, A
EOR
LSR
BBC
EOR
ABS, Y
CLB
2, A
EOR
LSR
CLB
—
—
—
—
IND, Y
ZP, X ZP, X 2, ZP
ABS, X ABS, X 2, ZP
ADC
RTS
MUL
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
ADC
ABS
ROR
ABS
SEB
3, ZP
PLA
SEI
IND, X ZP, X
ADC
—
BBC
3, A
ADC
ROR
BBC
ADC
ABS, Y
CLB
3, A
ADC
ROR
CLB
BVS
BRA
—
—
TXA
TXS
TAX
TSX
DEX
—
—
IND, Y
ZP, X ZP, X 3, ZP
ABS, X ABS, X 3, ZP
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
DEY
TYA
TAY
CLV
INY
—
STA
IND, Y
BBC
4, A
STY
STA
STX
BBC
STA
ABS, Y
CLB
4, A
STA
ABS, X
CLB
4, ZP
BCC
LDY
—
—
—
ZP, X ZP, X ZP, Y 4, ZP
LDA
LDX
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
LDA
IMM
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
IMM IND, X IMM
LDA
JMP
BBC
LDY
LDA
LDX
BBC
LDA
ABS, Y
CLB
LDY
LDA
LDX
CLB
BCS
IND, Y ZP, IND 5, A
ZP, X ZP, X ZP, Y 5, ZP
5, A ABS, X ABS, X ABS, Y 5, ZP
CPY
CMP
IMM IND, X
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
CMP
IMM
SEB
6, A
CPY
ABS
CMP
ABS
DEC
ABS
SEB
6, ZP
WIT
CMP
BNE
BBC
6, A
CMP
DEC
BBC
CMP
ABS, Y
CLB
6, A
CMP
DEC
CLB
—
—
CLD
INX
—
IND, Y
ZP, X ZP, X 6, ZP
ABS, X ABS, X 6, ZP
CPX
SBC
DIV
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
SBC
IMM
SEB
7, A
CPX
ABS
SBC
ABS
INC
ABS
SEB
7, ZP
NOP
—
IMM IND, X ZP, X
SBC
IND, Y
BBC
7, A
SBC
INC
BBC
SBC
ABS, Y
CLB
7, A
SBC
INC
CLB
BEQ
—
—
SED
—
ZP, X ZP, X 7, ZP
ABS, X ABS, X 7, ZP
3-byte instruction
2-byte instruction
1-byte instruction
3806 GROUP USER’S MANUAL
3-83
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
OP
69
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP
#
n
# OP
2
#
n
# OP
65
#
2
OP
n
#
ADC
(Note 1)
(Note 5)
When T = 0
Adds the carry, accumulator and memory con-
tents. The results are entered into the
accumulator.
2
3
←
A
A + M + C
When T = 1
Adds the contents of the memory in the ad-
dress indicated by index register X, the
contents of the memory specified by the ad-
dressing mode and the carry. The results are
entered into the memory at the address indi-
cated by index register X.
←
M(X)
M(X) + M + C
AND
(Note 1)
When T = 0
“AND’s” the accumulator and memory con-
tents.
29
2
2
25
3
2
V
←
A
A
M
The results are entered into the accumulator.
“AND’s” the contents of the memory of the ad-
dress indicated by index register X and the
contents of the memory specified by the ad-
dressing mode. The results are entered into
the memory at the address indicated by index
register X.
When T = 1
V
←
M(X)
M(X)
M
7
0
ASL
Shifts the contents of accumulator or contents
of memory one bit to the left. The low order bit
of the accumulator or memory is cleared and
the high order bit is shifted into the carry flag.
0A
2
1
06
5
2
←
←
0
C
BBC
(Note 4)
Ab or Mb = 0?
Ab or Mb = 1?
C = 0?
Branches when the contents of the bit speci-
fied in the accumulator or memory is “0”.
13
+
4
2
2
17
+
5
5
3
3
2i
2i
BBS
(Note 4)
Branches when the contents of the bit speci-
fied in the accumulator or memory is “1”.
03
+
4
07
+
2i
2i
BCC
(Note 4)
Branches when the contents of carry flag is
“0”.
BCS
(Note 4)
C = 1?
Branches when the contents of carry flag is
“1”.
BEQ
(Note 4)
Z = 1?
V
Branches when the contents of zero flag is “1”.
BIT
A
M
“AND’s” the contents of accumulator and
memory. The results are not entered any-
where.
24
3
2
BMI
(Note 4)
N = 1?
Z = 0?
N = 0?
Branches when the contents of negative flag is
“1”.
BNE
(Note 4)
Branches when the contents of zero flag is “0”.
BPL
(Note 4)
Branches when the contents of negative flag is
“0”.
←
BRA
BRK
PC
PC ± offset
Jumps to address specified by adding offset to
the program counter.
←
B
1
Executes a software interrupt.
00
7
1
←
M(S)
PCH
←
S
S – 1
←
PCL
S – 1
M(S)
←
S
←
PS
S – 1
M(S)
←
S
←
←
PCL
PCH
ADL
ADH
3806 GROUP USER’S MANUAL
3-84
APPENDIX
3.10 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
ABS, X
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
n
4
#
2
n
#
OP
6D
n
4
#
3
OP
n
5
#
OP
79
n
5
#
3
OP
#
n
#
OP
61
n
6
#
OP
71
n
6
#
OP
#
OP
#
N
N
V
V
75
35
16
7D
3D
1E
3
3
3
2
2
•
4
2
2D
4
3
5
39
5
3
21
6
2
31
6
2
N
•
•
•
•
•
Z
•
6
2
0E
6
3
7
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90
B0
F0
2
2
2
2
2
2
•
•
•
2C
4
3
M7 M6
Z
30
D0
10
80
2
2
2
4
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
3806 GROUP USER’S MANUAL
3-85
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n #
OP
#
n
# OP
#
n
# OP
#
BVC
(Note 4)
V = 0?
Branches when the contents of overflow flag is
“0”.
BVS
(Note 4)
V = 1?
Branches when the contents of overflow flag is
“1”.
←
CLB
CLC
CLD
CLI
Ab or Mb
0
Clears the contents of the bit specified in the
accumulator or memory to “0”.
1B
+
2
1
1F
+
5
2
2i
2i
←
←
C
D
0
0
Clears the contents of the carry flag to “0”.
18
2
2
2
2
2
1
1
1
1
1
Clears the contents of decimal mode flag to D8
“0”.
←
I
0
Clears the contents of interrupt disable flag to 58
“0”.
←
←
CLT
CLV
T
V
0
0
Clears the contents of index X mode flag to 12
“0”.
Clears the contents of overflow flag to “0”.
B8
CMP
(Note 3)
When T = 0
A – M
Compares the contents of accumulator and
memory.
C9
2
2
C5
3
2
When T = 1
M(X) – M
Compares the contents of the memory speci-
fied by the addressing mode with the contents
of the address indicated by index register X.
__
←
COM
CPX
CPY
DEC
DEX
DEY
DIV
M
M
Forms a one’s complement of the contents of
memory, and stores it into memory.
44
E4
C4
C6
5
3
3
5
2
2
2
2
X – M
Y – M
Compares the contents of index register X and
memory.
E0
C0
2
2
2
Compares the contents of index register Y and
memory.
2
←
←
A
M
A – 1 or
M – 1
Decrements the contents of the accumulator
or memory by 1.
1A
2
1
←
←
←
X
Y
A
X – 1
Decrements the contents of index register X CA
by 1.
2
2
1
1
Y – 1
Decrements the contents of index register Y 88
by 1.
(M(zz + X + 1),
Divides the 16-bit data that is the contents of
M (zz + x + 1) for high byte and the contents of
M (zz + x) for low byte by the accumulator.
Stores the quotient in the accumulator and the
1’s complement of the remainder on the stack.
M(zz + X)) / A
M(S)
of Remainder
←
←
1’s complememt
S
S – 1
EOR
(Note 1)
When T = 0
“Exclusive-ORs” the contents of accumulator
and memory. The results are stored in the ac-
cumulator.
49
2
2
45
3
2
–
←
A
A V M
When T = 1
“Exclusive-ORs” the contents of the memory
specified by the addressing mode and the
contents of the memory at the address indi-
cated by index register X. The results are
stored into the memory at the address indi-
cated by index register X.
–
M(X) V M
←
M(X)
←
←
INC
INX
INY
A
M
A + 1 or
M + 1
Increments the contents of accumulator or
memory by 1.
3A
2
1
E6
5
2
←
←
X
Y
X + 1
Y + 1
Increments the contents of index register X by E8
1.
2
2
1
1
Increments the contents of index register Y by C8
1.
3806 GROUP USER’S MANUAL
3-86
APPENDIX
3.10 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
V
•
5
4
B
•
3
D
•
2
I
1
Z
•
0
C
•
OP
n
#
n
#
OP
#
OP
n
#
OP
#
n
#
#
#
OP
50
#
2
OP
#
N
•
T
•
2
•
70
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
0
•
•
•
•
•
0
•
•
•
•
•
D5
4
CD
4
3
DD
5
3
D9
5
3
C1
6
2
D1
6
2
N
•
•
2
•
Z
C
N
N
N
N
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
Z
Z
Z
Z
•
•
C
C
•
EC
CC
CE
4
4
6
3
3
3
D6
6
DE
7
3
2
•
•
E2 16
2
2
•
55
4
4D
4
3
5D
5
3
59
5
3
41
6
2
51
6
2
N
•
•
•
•
•
Z
•
F6
6
EE
6
3
FE
7
3
N
N
N
•
•
•
•
•
•
•
•
•
•
•
•
2
•
•
•
Z
Z
Z
•
•
•
3806 GROUP USER’S MANUAL
3-87
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
JMP
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP #
OP
#
n
# OP
#
n
# OP
#
n
If addressing mode is ABS
Jumps to the specified address.
←
←
PCL
PCH
ADL
ADH
If addressing mode is IND
←
←
PCL
M (ADH, ADL)
PC
H
M (AD , AD + 1)
H
L
If addressing mode is ZP, IND
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
←
PCH
S – 1
JSR
M(S)
After storing contents of program counter in
stack, and jumps to the specified address.
←
S
←
PCL
S – 1
M(S)
←
S
After executing the above,
if addressing mode is ABS,
←
←
PCL
PCH
ADL
ADH
if addressing mode is SP,
←
←
PCL
PCH
ADL
FF
If addressing mode is ZP, IND,
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
LDA
(Note 2)
When T = 0
Load accumulator with contents of memory.
A9
2
2
A5
3
2
←
A
M
When T = 1
Load memory indicated by index register X
with contents of memory specified by the ad-
dressing mode.
←
nn
M
M(X)
M
←
←
←
7
LDM
LDX
LDY
LSR
M
X
Y
Load memory with immediate value.
3C
A6
A4
46
4
3
3
5
3
2
2
2
Load index register
memory.
X
Y
with contents of
with contents of
A2
A0
2
2
2
M
Load index register
memory.
2
0
Shift the contents of accumulator or memory
to the right by one bit.
4A
2
1
→
→
0
C
The low order bit of accumulator or memory is
stored in carry, 7th bit is cleared.
←
S – 1
MUL
NOP
M(S) · A
A ✕ M(zz + X)
Multiplies the accumulator with the contents of
memory specified by the zero page X address-
ing mode and stores the high byte of the result
on the stack and the low byte in the accumula-
tor.
←
S
←
PC
PC + 1
No operation.
EA
2
1
ORA
(Note 1)
When T = 0
“Logical OR’s” the contents of memory and ac-
cumulator. The result is stored in the
accumulator.
09
2
2
05
3
2
←
A
A V M
When T = 1
“Logical OR’s” the contents of memory indi-
cated by index register X and contents of
memory specified by the addressing mode.
The result is stored in the memory specified by
index register X.
←
M(X)
M(X) V M
3806 GROUP USER’S MANUAL
3-88
APPENDIX
3.10 Machine instructions
Addressing mode
Processor status register
ZP, X
OP n
ZP, Y
OP n
ABS
ABS, X
OP n
ABS, Y
IND
n
ZP, IND
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
#
#
OP
4C
n
3
#
3
#
OP
n
#
OP
6C
#
3
OP
B2
n
4
#
2
#
#
OP
#
OP
#
N
•
V
•
T
•
B
•
D
•
I
Z
•
C
•
5
•
20
6
3
02
7
2
22
5
2
•
•
•
•
•
•
•
•
B5
4
2
AD
4
3
A1
N
•
•
•
•
•
Z
•
BD
5
3
B9
5
3
6
2
B1
6
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
B6
4
2
AE
AC
4E
4
4
6
3
3
3
BE
5
3
N
N
0
Z
Z
Z
B4
56
4
6
2
2
•
BC
5E
5
7
3
3
C
62 15
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
15
4
2
0D
4
3
1D
5
3
19
5
3
01
6
2
11
6
2
N
Z
3806 GROUP USER’S MANUAL
3-89
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
PHA
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n #
OP
#
1
n
# OP
#
n
# OP
#
←
M(S)
A
Saves the contents of the accumulator in 48
memory at the address indicated by the stack
pointer and decrements the contents of stack
pointer by 1.
3
←
S
S – 1
←
S – 1
PHP
PLA
PLP
ROL
ROR
M(S)
PS
Saves the contents of the processor status 08
register in memory at the address indicated by
the stack pointer and decrements the contents
of the stack pointer by 1.
3
4
4
1
1
1
←
S
←
←
S
A
S + 1
M(S)
Increments the contents of the stack pointer 68
by 1 and restores the accumulator from the
memory at the address indicated by the stack
pointer.
←
S
S + 1
Increments the contents of stack pointer by 1 28
and restores the processor status register
from the memory at the address indicated by
the stack pointer.
←
PS
M(S)
7
←
0
Shifts the contents of the memory or accumu-
lator to the left by one bit. The high order bit is
shifted into the carry flag and the carry flag is
shifted into the low order bit.
2A
6A
2
2
1
1
26
66
82
5
5
8
2
2
2
←
←
C
Shifts the contents of the memory or accumu-
lator to the right by one bit. The low order bit is
shifted into the carry flag and the carry flag is
shifted into the high order bit.
7
0
→
→
C
RRF
RTI
7
→
0
→
Rotates the contents of memory to the right by
4 bits.
←
S
S + 1
M(S)
S + 1
M(S)
S + 1
Returns from an interrupt routine to the main 40
routine.
6
6
1
1
←
PS
←
PCL
←
PCH
S
←
S
←
M(S)
←
PCL
←
RTS
S
S + 1
M(S)
S + 1
Returns from a subroutine to the main routine. 60
←
S
←
PCH
M(S)
SBC
(Note 1)
(Note 5)
When T = 0
Subtracts the contents of memory and
complement of carry flag from the contents of
accumulator. The results are stored into the
accumulator.
E9
2
2
E5
3
2
_
←
A
A – M – C
When T = 1
_
←
M(X)
M(X) – M – C
Subtracts contents of complement of carry flag
and contents of the memory indicated by the
addressing mode from the memory at the ad-
dress indicated by index register X. The
results are stored into the memory of the ad-
dress indicated by index register X.
←
SEB
SEC
SED
SEI
Ab or Mb
1
Sets the specified bit in the accumulator or
memory to “1”.
0B
+
2
1
0F
+
5
2
2i
2i
←
←
C
D
1
1
Sets the contents of the carry flag to “1”.
38
2
2
2
2
1
1
1
1
Sets the contents of the decimal mode flag to F8
“1”.
←
I
1
Sets the contents of the interrupt disable flag 78
to “1”.
←
SET
T
1
Sets the contents of the index X mode flag to 32
“1”.
3806 GROUP USER’S MANUAL
3-90
APPENDIX
3.10 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
n
#
n
#
OP
#
OP
n
#
OP
#
n
#
#
#
OP
#
OP
#
N
•
V
•
T
•
B
•
D
•
I
Z
•
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
Z
(Value saved in stack)
36
76
6
6
2
2
2E
6E
6
6
3
3
3E
7E
7
7
3
3
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
•
C
C
•
(Value saved in stack)
•
•
•
•
•
•
•
•
•
•
•
•
N
V
Z
C
F5
4
2
ED
4
3
FD
5
3
F9
5
3
E1
6
2
F1
6
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
1
•
•
•
1
•
•
1
•
•
3806 GROUP USER’S MANUAL
3-91
APPENDIX
3.10 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP #
OP
#
1
n
# OP
#
n
# OP
85
#
2
n
←
STA
STP
STX
STY
TAX
TAY
TST
TSX
TXA
TXS
TYA
WIT
M
A
Stores the contents of accumulator in memory.
Stops the oscillator.
4
42
2
←
←
←
←
M
M
X
X
Y
Stores the contents of index register X in
memory.
86
84
4
4
2
2
Stores the contents of index register Y in
memory.
A
Transfers the contents of the accumulator to AA
index register X.
2
2
1
1
Y
A
Transfers the contents of the accumulator to A8
index register Y.
M = 0?
Tests whether the contents of memory are “0”
or not.
64
3
2
←
←
←
←
X
A
S
A
S
X
X
Y
Transfers the contents of the stack pointer to BA
index register X.
2
2
2
2
2
1
1
1
1
1
Transfers the contents of index register X to 8A
the accumulator.
Transfers the contents of index register X to 9A
the stack pointer.
Transfers the contents of index register Y to 98
the accumulator.
Stops the internal clock.
C2
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : N, V, and Z flags are invalid in decimal operation mode.
3806 GROUP USER’S MANUAL
3-92
APPENDIX
3.10 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP n
ABS
ABS, X
OP
9D
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
4
3
2
1
0
C
•
OP
95
n
5
#
2
#
2
OP
8D
n
5
#
3
n
#
OP
99
n
#
3
OP
#
n
#
OP
81
n
7
#
OP
91
n
7
#
OP
#
OP
#
N
•
V
•
T
•
B
•
D
•
I
Z
•
6
3
6
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
96
5
8E
8C
5
5
3
3
94
5
2
•
•
N
N
N
N
N
•
Z
Z
Z
Z
Z
•
N
•
Z
•
Symbol
Contents
Symbol
Contents
IMP
Implied addressing mode
+
Addition
IMM
A
Immediate addressing mode
Accumulator or Accumulator addressing mode
–
Subtraction
Logical OR
Logical AND
V
V
–
V
–
BIT, A
Accumulator bit relative addressing mode
Logical exclusive OR
Negation
ZP
BIT, ZP
Zero page addressing mode
Zero page bit relative addressing mode
←
X
Shows direction of data flow
Index register X
Y
Index register Y
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
S
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
PC
PS
PCH
PCL
ADH
ADL
FF
nn
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
M
Memory specified by address designation of any ad-
dressing mode
Memory of address indicated by contents of index
register X
M(X)
M(S)
Memory of address indicated by contents of stack
Z
Zero flag
pointer
I
D
B
Interrupt disable flag
Decimal mode flag
Break flag
M(ADH, ADL)
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-or-
der bits.
T
V
N
X-modified arithmetic mode flag
Overflow flag
Negative flag
M(00, ADL)
Contents of address indicated by zero page ADL
1 bit of accumulator
1 bit of memory
Opcode
Number of cycles
Ab
Mb
OP
n
#
Number of bytes
3806 GROUP USER’S MANUAL
3-93
APPENDIX
3.11 SFR memory map
3.11 SFR memory map
000016 Port P0 (P0)
002016 Prescaler 12 (PRE12)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
002116 Timer 1 (T1)
002216 Timer 2 (T2)
000316 Port P1 direction register (P1D)
000416 Port P2 (P2)
002316 Timer XY mode register (TM)
002416 Prescaler X (PREX)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
002516 Timer X (TX)
002616 Prescaler Y (PREY)
000716 Port P3 direction register (P3D)
000816 Port P4 (P4)
002716 Timer Y (TY)
002816
000916 Port P4 direction register (P4D)
000A16 Port P5 (P5)
002916
002A16
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
002B16
002C16
000D16 Port P6 direction register (P6D)
000E16 Port P7 (P7)
002D16
002E16
000F16 Port P7 direction register (P7D)
001016 Port P8 (P8)
002F16
003016
001116 Port P8 direction register (P8D)
001216
003116
003216
001316
003316
001416
001516
001616
001716
003416 AD/DA control register (ADCON)
003516 A-D conversion register (AD)
003616 D-A1 conversion register (DA1)
003716 D-A2 conversion register (DA2)
003816
001816 Transmit/Receive buffer register (TB/RB)
001916 Serial I/O1 status register (SIO1STS)
001A16 Serial I/O1 control register (SIO1CON)
001B16 UART control register (UARTCON)
001C16 Baud rate generator (BRG)
001D16 Serial I/O2 control register (SIO2CON)
001E16
003916
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
001F16 Serial I/O2 register (SIO2)
3806 GROUP USER’S MANUAL
3-94
APPENDIX
3.12 Pin configuration
3.12 Pin configuration
PIN CONFIGURATION (TOP VIEW)
65
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P8
P8
P8
P8
P8
P8
7
6
5
4
3
2
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
/DB
/DB
/DB
/DB
/DB
/DB
/DB
/DB
0
1
2
3
4
5
6
7
66
67
68
69
70
71
72
73
74
75
76
77
78
P8
P8
1
0
V
CC
V
X
X
SS
M38063M6-XXXFP
VREF
OUT
IN
AVSS
/AN
/AN
/AN
/AN
/AN3
P6
7
7
P4
P4
RESET
CNVSS
P42/INT0
0
P66
6
1
P6
P6
P6
5
5
4
4
79
80
3
Package type : 80P6N-A
80-pin plastic-molded QFP
3806 GROUP USER’S MANUAL
3-95
APPENDIX
3.12 Pin configuration
PIN CONFIGURATION (TOP VIEW)
P31
P30
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
40
39
38
37
P16/AD14
P17/AD15
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
Vss
P87
P86
P85
P84
P83
P82
P81
36
35
34
33
32
31
30
29
28
27
26
25
24
P80
VCC
VREF
M38063M6-XXXGP
M38063M6AXXXHP
XOUT
XIN
P40
P41
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
RESET
CNVSS
P42/INT0
P43/INT1
23
22
21
78
79
80
P61/AN1
P44/RXD
Package type : 80P6S-A/80P6D-A
80-pin plastic-molded QFP
3806 GROUP USER’S MANUAL
3-96
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
3806Group
Mar. First Edition 1996
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1996 MITSUBISHI ELECTRIC CORPORATION
3806 Group
User’s Manual
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
相关型号:
M38062M6-XXXFP
Microcontroller, 8-Bit, MROM, 8MHz, CMOS, PQFP80, 0.80 MM PITCH, PLASTIC, QFP-80
MITSUBISHI
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