M38063ED-XXXFP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38063ED-XXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总80页 (文件大小：1551K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timers ........................................................... 8-bit ✕ 3, 16-bit ✕✕2
Serial I/O1 ..................... 8-bit ✕ 1 (UART or Clock-synchronous)
Serial I/O2 .................................... 8-bit ✕ 1 (Clock-synchronous)
PWM output .................................................................... 8-bit ✕ 1
A-D converter .................................................. 8-bit ✕ 8 channels
D-A converter .................................................. 8-bit ✕ 2 channels
.................................... (used as the DTMF and CTCSS function)
LCD drive control circuit
DESCRIPTION
•
•
•
•
•
•
The 3826 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 3826 group has the LCD drive control circuit, an 8-channel A-
D/D-A converter, UART and PWM as additional functions.
The various microcomputers in the 3826 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
•
Bias ................................................................................... 1/2, 1/3
Duty ............................................................................ 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output......................................................................... 40
2 Clock generating circuits
For details on availability of microcomputers in the 3826 Group,
refer the section on group expansion.
FEATURES
Basic machine-language instructions ....................................... 71
•
•
•
(connect to external ceramic resonator or quartz-crystal oscillator)
Watchdog timer ............................................................. 14-bit ✕ 1
Power source voltage ................................................ 2.5 to 5.5 V
............................................ (2.2 to 5.5 V for low voltage version)
Power dissipation
The minimum instruction execution time ............................ 0.5 µs
(at 8 MHz oscillation frequency)
•
•
Memory size
•
ROM ................................................................ 32 K to 60 K bytes
RAM ............................................................... 1024 to 2560 bytes
•
In high-speed mode ........................................................... 40 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode..............................................................60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
Operating temperature range ................................... – 20 to 85°C
Programmable input/output ports ............................................. 55
•
Software pull-up resistors .................................................... Built-in
•
Output ports ................................................................................. 8
•
Input ports .................................................................................... 1
•
Interrupts .................................................. 17 sources, 16 vectors
(includes key input interrupt)
•
•
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
9
8
7
6
5
4
3
2
1
0
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
6
7
0
1
2
3
4
5
6
7
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
M38268MCLXXXFP
V
X
X
X
X
SS
V
CC
REF
AVSS
OUT
IN
V
COUT
CIN
COM
COM
COM
COM
3
2
1
0
RESET
P7
P7
P7
P7
0
1
2
3
/INT0
VL3
VL2
C
2
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Package type : 100P6S-A
Fig. 1 Pin configuration of M38268MCLXXXFP
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
SEG12
SEG11
SEG10
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
4
5
6
7
0
1
2
3
4
5
6
7
/SEG38
/SEG39
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
9
8
7
6
5
4
3
2
1
0
V
X
X
X
X
SS
M38268MCLXXXGP
OUT
IN
V
CC
REF
AVSS
V
COUT
CIN
COM
COM
COM
COM
3
2
1
0
RESET
P7
P7
P7
P7
P7
P7
P7
0
1
2
3
4
5
6
/INT0
VL3
VL2
C
C
2
1
VL1
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Package type : 100P6Q-A
Fig. 2 Pin configuration of M38268MCLXXXGP
2
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
t p u r r e t n i ) p u e k a w n o - y e K ( t u p n i y e K
n o i t c n u f t r o p e m i t l a e R
N I , 1 T N I
T D A
0 T N I
Fig. 3 Functional block diagram
3
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
VREF
Power source
•Apply voltage of 2.5 V to 5.5 V (2.2 V to 5.5 V for low voltage version) to VCC, and 0 V to VSS.
•Reference voltage input pin for A-D converter.
Analog refer-
ence voltage
AVSS
Analog power
source
•GND input pin for A-D converter.
•Connect to VSS.
Reset input
Clock input
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the main clock generating circuit.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. A
feedback resistor is built-in.
LCD power
source
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
VL1–VL3
C1, C2
•Input 0 – VL3 voltage to LCD. (0 ≤ VL1 ≤ VL2 ≤ VL3 when a voltage is multiplied.)
Charge-pump
capacitor pin
•External capacitor pins for a voltage multiplier (3 times) of LCD contorl.
Common output
•LCD common output pins.
COM0–COM3
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
•LCD segment output pins.
SEG0–SEG17 Segment output
P00/SEG26–
P07/SEG33
I/O port P0
•8-bit I/O port.
•LCD segment output pins
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled.
•I/O direction register allows each 8-bit pin to be pro-
grammed as either input or output.
P10/SEG34– I/O port P1
P15/SEG39
•6-bit I/O port with same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled.
•I/O direction register allows each 6-bit pin to be pro-
grammed as either input or output.
P16, P17
•2-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually programmred as either input or output.
•Pull-up control is enabled.
P20 – P27
•8-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•Key input (key-on wake-up) interrupt
input pins
I/O port P2
•CMOS 3-state output structure.
•Pull-up control is enabled.
•LCD segment output pins
P3
P3
0
7
/SEG18
/SEG25
–
Output port P3
•8-bit output port with same function as port P0.
•CMOS 3-state output structure.
•Port output control is enabled.
4
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Pin
Name
Function
Function except a port function
P40
I/O port P4
•1-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•N-channel open-drain output structure.
•7-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•Interrupt input pins
P41/INT1,
P42/INT2
•CMOS 3-state output structure.
P43/φ/TOUT
•φ clock output pin
•Timer 2 output pin
•Pull-up control is enabled.
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
•Serial I/O1 I/O pins
P50/PWM0,
P51/PWM1
I/O port P5
•8-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•PWM function pins
•CMOS 3-state output structure.
•Pull-up control is enabled.
P52/RTP0,
P53/RTP1
•Real time port function pins
•Timer X, Y function pins
•D-A conversion output pins
P54/CNTR0,
P55/CNTR1
P56/DA1,
P57/ADT/DA2
P6
P6
P6
P6
0
/AN
0
1
2
3
/SIN2,
I/O port P6
•8-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•A-D conversion input pins
•Serial I/O2 I/O pins
1
2
3
/AN
/AN
/AN
/SOUT2,
/SCLK21,
/SCLK22
•CMOS 3-state output structure.
•Pull-up control is enabled.
P64/AN4–
P67/AN7
•A-D conversion input pins
•Interrupt input pin
Input port P7
I/O port P7
•1-bit input port.
P70/INT0
•7-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
P71–P77
•N-channel open-drain output structure.
•Sub-clock generating circuit I/O pins.
XCOUT
XCIN
Sub-clock output
Sub-clock input
(Connect a resonator. External clock cannot be used.)
5
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M3826
8
M
C
L
XXX FP
Package type
FP : 100P6S-A package
GP : 100P6Q-A package
FS : 100D0
ROM number
Omitted in One Time PROM version
shipped in blank and EPROM version.
Characteristics
– :Standard
L : Low voltage version
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M: Mask ROM version
E: EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
A : 2560 bytes
Fig. 4 Part numbering
6
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Packages
(One Time PROM Version, EPROM Version)
Mitsubishi plans to expand the 3826 group (One Time PROM ver-
sion, EPROM version) as follows.
100P6Q-A .................................. 0.5 mm-pitch plastic molded QFP
100P6S-A ................................ 0.65 mm-pitch plastic molded QFP
100D0 .......................................... Ceramic LCC (EPROM version)
Memory Type
Support for One Time PROM version, EPROM version.
Memory Size
ROM/PROM size ............................................... 32 K to 60 K bytes
RAM size .......................................................... 1024 to 2560 bytes
3826 Group Memory Expansion Plan (One Time PROM version, EPROM version)
Mass product
M3826AEF
ROM size (bytes)
60K
56K
52K
48K
44K
40K
36K
32K
28K
24K
Mass product
M38267E8
20K
16K
12K
8K
4K
192 256
512
768
1024
1280
1536
1792
2048
2304
2560
RAM size (bytes)
Products under development or planning :the development schedule and specification may be revised without notice.
Fig. 5 Memory expansion plan (One Time PROM version, EPROM version)
Currently products are listed below.
As of Nov. 2001
Table 3. List of products (One Time PROM version, EPROM version)
ROM size (bytes)
ROM size for User in (
Product
RAM size (bytes)
1024
Package
Remarks
)
M38267E8FP
M38267E8GP
M3826AEFFP
M3826AEFGP
M3826AEFFS
100P6S-A One Time PROM version (shipped in blank)
100P6Q-A One Time PROM version (shipped in blank)
100P6S-A One Time PROM version (shipped in blank)
100P6Q-A One Time PROM version (shipped in blank)
32768
(32638)
61440
(61310)
2560
100D0
EPROM version
7
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (Low Voltage Version)
Mitsubishi plans to expand the 3826 group (low voltage version)
as follows.
Packages
100P6Q-A .................................. 0.5 mm-pitch plastic molded QFP
100P6S-A ................................ 0.65 mm-pitch plastic molded QFP
Memory Type
Support for Mask ROM version.
Memory Size
ROM/PROM size ............................................... 32 K to 60 K bytes
RAM size .......................................................... 1024 to 2560 bytes
3826 Group Memory Expansion Plan (Low voltage version)
Mass product
ROM size (bytes)
60K
M3826AMFL
56K
Mass product
52K
48K
44K
M38268MCL
40K
36K
32K
28K
24K
Mass product
M38267M8L
20K
16K
12K
8K
4K
192 256
512
768
1024
1280
1536
1792
2048
2304
2560
RAM size (bytes)
Products under development or planning :the development schedule and specification may be revised without notice.
Fig. 6 Memory expansion plan (Low voltage version)
Currently products are listed below.
As of Nov. 2001
Table 4. List of products (Low voltage version)
ROM size (bytes)
Product
RAM size (bytes)
Package
Remarks
ROM size for User in (
)
M38267M8LXXXFP
M38267M8LXXXGP
M38268MCLXXXFP
M38268MCLXXXGP
M3826AMFLXXXFP
M3826AMFLXXXGP
100P6S-A Mask ROM version
100P6Q-A Mask ROM version
100P6S-A Mask ROM version
100P6Q-A Mask ROM version
100P6S-A Mask ROM version
100P6Q-A Mask ROM version
32768
(32638)
1024
1536
2560
49152
(49022)
61440
(61310)
8
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3826 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 8.
Store registers other than those described in Figure 8 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b0
b0
b0
b0
b0
b7
A
Accumulator
b7
X
Index register X
Index register Y
b7
Y
b7
S
Stack pointer
b15
b7
b7
PCH
PC
L
Program counter
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 7 740 Family CPU register structure
9
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PC
(S) (S) – 1
M (S) (PC
H)
Push return address
on stack
M (S) (PC
(S) (S) – 1
M (S) (PC
H)
L
)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
Push contents of processor
status register on stack
L
)
(S) (S)– 1
Subroutine
Interrupt
Service Routine
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PC
(S) (S) + 1
(PC M (S)
L)
M (S)
(PS)
(S) (S) + 1
(PC M (S)
(S) (S) + 1
(PC M (S)
M (S)
H)
L)
POP return
address
from stack
H)
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 8 Register push and pop at interrupt generation and subroutine call
Table 5 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
10
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Processor status register (PS)]
• Bit 4: Break flag (B)
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
The B flag is used to indicate that the current interrupt was gen-
erated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
• Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled be-
tween memory locations.
• Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arith-
metic logic unit (ALU) immediately after an arithmetic operation.
It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z)
• Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location op-
erated on by the BIT instruction is stored in the overflow flag.
• Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
• Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt gener-
ated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7
of the memory location operated on by the BIT instruction is
stored in the negative flag.
Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed
when this flag is “0”; decimal arithmetic is executed when it is
“1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 6 Set and clear instructions of each bit of processor status register
N flag
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
–
–
Set instruction
CLI
CLV
Clear instruction
11
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Port XC switch bit
0 : Oscillation stop
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN–XOUT selected (middle-/high-speed mode)
1 : XCIN–XCOUT selected (low-speed mode)
Fig. 9 Structure of CPU mode register
12
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special Page
ROM
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
Address
XXXX16
000016
SFR area
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
0A3F16
192
256
Zero page
004016
005416
LCD display RAM area
384
512
010016
XXXX16
044016
RAM
640
768
896
1024
1536
2048
2560
Reserved area
Not used (Note)
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
YYYY16
ZZZZ16
Reserved ROM area
(128 bytes)
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Note: When RAM area exceeds 1024 bytes, the areas shown the table are used.
Fig. 10 Memory map diagram
13
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Port P0 (P0)
Timer X (low) (TXL)
Port P0 direction register (P0D)
Port P1 (P1)
Timer X (high) (TXH)
Timer Y (low) (TYL)
Timer Y (high) (TYH)
Timer 1 (T1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Timer 2 (T2)
Timer 3 (T3)
Port P3 (P3)
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
Port P3 output control register (P3C)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
T
OUT/φ output control register (CKOUT)
Port P5 direction register (P5D)
Port P6 (P6)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Port P6 direction register (P6D)
Port P7 (P7)
CTCSS timer (low) (CTCSSL)
CTCSS timer (high) (CTCSSH)
DTMF high group timer (DTMFH)
DTMF low group timer (DTMFL)
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
A-D control register (ADCON)
Port P7 direction register (P7D)
Reserved area (Note)
Key input control register (KIC)
PULL register A (PULLA)
A-D conversion register (AD)
D-A control register (DACON)
Watchdog timer control register (WDTCON)
PULL register B (PULLB)
Transmit/Receive buffer register(TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Segment output enable register (SEG)
LCD mode register (LM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
Serial I/O2 control register (SIO2CON)
Reserved area (Note)
Serial I/O2 register (SIO2)
Note: The register of reserved area can not be used.
Fig. 11 Memory map of special function register (SFR)
14
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
Direction Registers
b7
b0
PULL register A
(PULLA : address 001616
)
The I/O ports (ports P0, P1, P2, P4, P5, P6, P71–P77) have direc-
tion registers which determine the input/output direction of each
individual pin. (Ports P00–P07 are shared with bit 0 of the port P0
direction register, and ports P10–P15 shared with bit 0 of the port
P1 direction register.) Each bit in a direction register corresponds
to one pin, and each pin can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
P0
P0
P0
P1
P1
P1
P2
P2
0
2
4
0
4
6
0
4
, P0
, P0
–P0
–P1
, P1
, P1
–P2
–P2
1
3
7
3
5
7
3
7
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
b7
b0
PULL register B
(PULLB : address 001716
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
)
P41
P44
P50
P54
P60
P64
–P4
–P4
–P5
–P5
–P6
–P6
3
7
3
7
3
7
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
Port P3 Output Control Register
Bit 0 of the port P3 output control register (address 000716) en-
Not used (return “0” when read)
ables control of the output of ports P30–P37.
0 : Disable
1 : Enable
When the bit is set to “1”, the port output function is valid.
When resetting, bit 0 of the port P3 output control register is set to
“0” (the port output function is invalid) and pulled up.
Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
Pull-up Control
Fig. 12 Structure of PULL register A and PULL register B
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports P0 to P2, P4 to P6 can control pull-
up with a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
The PULL register A setting is invalid for pins set to segment out-
put with the segment output enable register.
15
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7 List of I/O port function (1)
Name
Input/Output
Non-Port Function
I/O Format
Related SFRs
Pin
Diagram No.
(1)
P00/SEG26–
P07/SEG33
Port P0
Input/output,
byte unit
CMOS compatible
input level
LCD segment output
PULL register A
Segment output enable
register
(2)
CMOS 3-state output
P10/SEG34–
P15/SEG39
Port P1
Input/output,
6-bit unit
CMOS compatible
input level
LCD segment output
PULL register A
(1)
(2)
Segment output enable
register
CMOS 3-state output
Input/output,
individual bits
CMOS compatible
input level
PULL register A
P16 , P17
(4)
CMOS 3-state output
P20–P27
Port P2
Port P3
Input/output,
individual bits
CMOS compatible
input level
Key input (key-on
wake-up) interrupt
input
PULL register A
Interrupt control register2
Key input control register
CMOS 3-state output
Segment output enable
register
(3)
P30/SEG18–
P37/SEG25
Output
CMOS 3-state output
LCD segment output
P3 output enable register
CMOS compatible
input level
(13)
P40
Port P4
Input/output,
individual bits
N-channel open-drain
output
CMOS compatible
input level
External interrupt input
(4)
Interrupt edge selection
register
P41/INT1,
P42/INT2
CMOS 3-state output
(12)
PULL register B
P43/φ/TOUT
Timer output
Timer 123 mode register
φ output
TOUT/φ output control
register
PULL register B
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
Serial I/O1 function I/O
(5)
(6)
Serial I/O1 control register
Serial I/O1 status register
UART control register
(7)
(8)
(10)
P50/PWM0,
P51/PWM1
Port P5
Input/output,
individual bits
CMOS compatible
input level
PWM output
PULL register B
PWM control register
CMOS 3-state output
P52/RTP0,
P53/RTP1
Real time port
function output
(9)
PULL register B
Timer X mode register
P54/CNTR0
(11)
(14)
PULL register B
Timer X function I/O
Timer X mode register
PULL register B
P55/CNTR1
Timer Y function input
DA1 output
Timer Y mode register
PULL register B
P56/DA1
(15)
(15)
D-A control register
PULL register B
DTMF input
DA2 output
P57/ADT/
DA2
CTCSS output
D-A control register
A-D control register
A-D trigger input
16
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8 List of I/O port function (2)
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFRS
Diagram No.
P60/SIN2/AN0
Port P6
Input/
A-D conversion input
Serial I/O2 function I/O
PULL register B
A-D control register
Serial I/O2 control
register
(17)
CMOS compatible input
level
CMOS 3-state output
output,
individual
bits
P61/SOUT2/
AN1
(18)
(19)
P62/SCLK21/
AN2
P63/SCLK22 /
AN3
(20)
(16)
A-D conversion input
External interrupt input
A-D control register
PULL register B
P64/AN4–
P67/AN7
P70/INT0
Port P7
Input
CMOS compatible input
level
Interrupt edge
selection register
(23)
(13)
P71–P77
Input/
CMOS compatible input
level
output,
individual
bits
N-channel open-drain
output
COM0–COM3
SEG0–SEG17
LCD mode register
Common
Segment
Output
Output
LCD common output
LCD segment output
(21)
(22)
Notes1: How to use double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate po-
tential, a current will flow VCC to VSS through the input-stage gate.
17
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P01–P07, P11–P15
Pull-up
V
L2/VL3/VCC
LCD drive timing
Segment/Port
Segment data
Data bus
Port direction register
Interface logic level
shift circuit
Segment
Port latch
V
L1/VSS
Port
Port direction register
Port/Segment
(2) Ports P00, P10
Pull-up
V
L2/VL3/VCC
LCD drive timing
Segment/Port
Direction register
Segment data
Port latch
Interface logic level
shift circuit
Segment
Data bus
V
L1/VSS
Port/Segment
Port
Port direction register
(3) Port P3
Pull-up
V
/VL3/VCC
SegLm2ent/Port
LCD drive timing
Segment data
Port latch
Interface logic level
shift circuit
Segment
Data bus
V
L1/VSS
Port
Port/Segment
Output control
(4) Ports P1
6
,P1
7
,P2,P4
1
,P42
(5) Port P4
4
Pull-up control
Pull-up control
Serial I/O1 enable bit
Reception enable bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
Key-on wake up interrupt input
INT , INT interrupt input
Serial I/O1 input
1
2
Except P1 , P17
6
Fig. 13 Port block diagram (1)
18
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(6) Port P4
5
(7) Port P46
Serial I/O1 synchronization
clock selection bit
Pull-up control
Pull-up control
Serial I/O1 enable bit
P45
/TxD P-channel output disable bit
Serial I/O1 enable bit
Transmission enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
Direction
register
register
Data bus
Port latch
Data bus
Port latch
Serial I/O1 output
Serial I/O1 clock output
Serial I/O1 clock input
(8) Port P4
7
(9) Ports P52,P53
Pull-up control
Pull-up control
Serial I/O1 mode selection bit
Serial I/O1 enable bit
S
RDY1 output enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Real time control bit
Real time port data
Serial I/O1 ready output
Pull-up control
(11) Port P5
4
(10) Ports P50,P51
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Pulse output mode
Timer output
PWM function enable bit
PWM output
CNTR0 interrupt input
Fig. 14 Port block diagram (2)
19
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(13) Ports P40,P71–P77
(12) Port P4
3
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
T
OUT/φ output control
Timer output
T
OUT/φ selection bit
φ output
(15) Ports P56,P57
(14) Port P5
5
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
A-D trigger input
CNTR1 interrupt input
Except P5
6
D-A converter output
D-A ,D-A2 output enable bit
1
(16) Ports P64–P67
(17) Port P6
0
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
A-D conversion input
Analog input pin selection bit
Serial I/O2 input
A-D conversion input
Analog input pin selection bit
Fig. 15 Port block diagram (3)
20
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(19) Port P6
2
(18) Port P6
1
Synchronous clock selection bit
Pull-up control
P61/SOUT2 P-channel output disable bit
Pull-up control
Serial I/O2 port selection bit
Synchronous clock output pin
selection bit
Serial I/O2 transmit end signal
Synchronous clock selection bit
Serial I/O2 port selection bit
Direction
Direction
register
register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 output
Serial I/O2 clock output
A-D conversion input
Serial I/O2 clock input
Analog input pin selection bit
A-D conversion input
Analog input pin selection bit
(20) Port P6
3
Pull-up control
Synchronous clock selection bit
Serial I/O2 port selection bit
Synchronous clock output pin selection bit
(21)COM0–COM3
V
L3
Direction
register
The gate input signal of each
transistor is controlled by the LCD
duty ratio and the bias value.
V
L2
L1
Data bus
Port latch
V
Serial I/O2 clock output
V
SS
A-D conversion input
Analog input pin selection bit
(23) Port P7
0
(22)SEG0–SEG17
Direction
register
V
L2/VL3
The voltage applied to the sources of P-
channel and N-channel transistors is the
controlled voltage by the bias value.
Data bus
Port latch
V
L1/VSS
INT0 input
Fig. 16 Port block diagram (4)
21
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by seventeen sources: seven external, nine inter-
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
nal, and one software.
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 9 Interrupt vector addresses and priority
Interrupt Request
Remarks
Vector Addresses (Note 1)
Interrupt Source
Priority
High
Low
Generating Conditions
Reset (Note 2)
At reset
1
2
FFFD16
FFFB16
FFFC16
FFFA16
Non-maskable
INT0
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT1 input
INT1
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
External interrupt
(active edge selectable)
3
4
Serial I/O1
reception
At completion of serial I/O1 data
reception
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
At completion of serial I/O1
transmit shift or when transmis-
sion buffer is empty
Serial I/O1
transmission
5
Timer X
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
Timer Y
Timer 2
Timer 3
8
9
CNTR0
At detection of either rising or
falling edge of CNTR0 input
10
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR1 input
CNTR1
11
FFE916
FFE816
External interrupt
(active edge selectable)
FFE616
FFE416
At timer 1 underflow
Timer 1
INT2
12
13
FFE716
FFE516
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
Serial I/O2
At completion of serial I/O2 data
transmission or reception
14
15
16
FFE316
FFE116
FFDF16
FFE216
FFE016
FFDE16
Valid when serial I/O2 is selected
Key input
(Key-on wake-up)
At falling of conjunction of input External interrupt
level for port P2 (at input mode) (valid at falling)
Valid when ADT interrupt is selected
ADT
At falling edge of ADT input
External interrupt
(valid at falling)
At completion of A-D conversion Valid when A-D interrupt is selected
A-D conversion
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution Non-maskable software interrupt
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
22
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When not requiring for the interrupt occurrence synchronous with
these setting, take the following sequence.
✕Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
✕Set the corresponding interrupt enable bit to “0” (disabled).
✕Set the interrupt edge select bit (polarity switch bit) or the inter-
rupt source select bit to “1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
✕Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Timer Y mode register (address 2816)
✕Set the corresponding interrupt enable bit to “1” (enabled).
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection bit of A-D control
regsiter (bit 6 of address 3416)
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 17 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
0
1
2
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
Not used (return “0” when read)
0 : Falling edge active
1 : Rising edge active
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
)
(IREQ1 : address 003C16
)
INT
INT
0
1
interrupt request bit
interrupt request bit
CNTR
CNTR
0
1
interrupt request bit
interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
INT interrupt request bit
Serial I/O2 interrupt request bit
Key input interrupt request bit
2
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
CNTR
0
1
interrupt enable bit
interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 1 interrupt enable bit
INT interrupt enable bit
2
Serial I/O2 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 18 Structure of interrupt-related registers
23
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-on Wake Up)
goes from “1” to “0”. An example of using a key input interrupt is
shown in Figure 19, where an interrupt request is generated by
pressing one of the keys consisted as an active-low key matrix
which inputs to ports P20–P23.
A Key-on wake up interrupt request is generated by applying “L”
level voltage to any pin of port P2 that have been set to input
mode. In other words, it is generated when AND of input level
Port PXx
“L” level output
PULL register A
Port P2
direction register = “1”
7
Key input control register = “1”
Bit 2 = “1”
Key input interrupt request
✕
✕
✕
✕
✕
✕
✕
✕
✕✕✕
Port P2
latch
7
P2
7
output
output
output
output
Key input control register = “1”
direction register = “1”
Port P2
6
✕✕✕
Port P2
latch
6
P2
6
Key input control register = “1”
Port P2
direction register = “1”
5
✕✕✕
Port P2
latch
5
P2
5
Key input control register = “1”
Port P2
direction register = “1”
4
✕✕✕
Port P2
latch
4
P2
4
Key input control register = “1”
Port P2
direction register = “0”
3
Port P2
Input reading circuit
✕✕✕
Port P2
latch
3
P23 input
Key input control register = “1”
Port P2
direction register = “0”
2
✕✕✕
Port P2
latch
2
P2
2
input
input
input
Key input control register = “1”
Port P2
direction register = “0”
1
✕✕✕
Port P2
latch
1
P2
1
Port P2
direction register = “0”
0
Key input control register = “1”
✕✕✕
Port P2
latch
0
P2
0
✕
P-channel transistor for pull-up
✕✕✕ CMOS output buffer
Fig. 19 Connection example when using key input control register, key input interrupt and port P2 block diagram
24
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Read and write operation on 16-bit timer must be performed for
both high- and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
TIMERS
The 3826 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is contin-
ued. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1”.
Data bus
Real time port
control bit “1”
P52 data for
Q D
real time port
P52/RTP0
P53/RTP1
Latch
“0”
P52 direction register
P52 latch
Real time port
control bit “1”
P53 data for
real time port
Q D
Real time port
control bit “0”
Latch
“0”
P53 direction register
Timer X mode register
write signal
P53 latch
“1”
f(XIN)/16
(f(XCIN)/16 when φ = XCIN/2)
Timer X stop
control bit
Timer X write
control bit
Timer X operat-
CNTR0 active
edge switch bit
“0”
ing mode bits
Timer X (low) latch (8)
Timer X (low) (8)
Timer X (high) latch (8)
Timer X (high) (8)
“00”,“01”,“11”
Timer X
interrupt
request
P54/CNTR0
"10"
“1”
Pulse width
measurement
mode
Pulse output mode
CNTR0 active
edge switch bit
“0”
“1”
S
Q
Q
T
P54 direction register
Pulse width HL continuously
measurement mode
P54 latch
Rising edge detection
Pulse output mode
f(XIN)/16
Period
measurement mode
Falling edge detection
(f(XCIN)/16 when φ = XCIN/2)
Timer Y stop
control bit
CNTR1 active
edge switch bit
Timer Y (low) latch (8)
Timer Y (low) (8)
Timer Y (high) latch (8)
Timer Y (high) (8)
"00","01","11"
Timer Y
interrupt
request
“0”
P55/CNTR1
Timer Y
"10"
operating
mode bits
“1”
f(XIN)/16
(f(XCIN)/16 when φ = XCIN/2)
Timer 1
interrupt
request
Timer 2 write
control bit
Timer 1 count source
selection bit
“0”
Timer 2 count source
selection bit
Timer 2 latch (8)
Timer 2 (8)
Timer 1 latch (8)
Timer 1 (8)
“0”
Timer 2
interrupt
request
XCIN
“1”
“1”
f(XIN)/16
(f(XCIN)/16 when φ = XCIN/2)
TOUT output
control bit
TOUT output
active edge
switch bit “0”
TOUT output
control bit
S
Q
P43/φ/TOUT
T
“1”
P43 latch
P43 direction register
Timer 3 latch (8)
Q
“0”
Timer 3
interrupt
request
f(XIN)/16
(f(XCIN)/16
when φ = XCIN/2)
Timer 3 (8)
φ
“1”
φ output control bit
Timer 3 count
source selection bit
Fig. 20 Timer block diagram
25
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
b7
b0
Timer X mode register
(TXM : address 002716
)
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
(2) Pulse output mode
P5
2
data for real time port
data for real time port
P53
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the corresponding port P54 direction register to output mode.
Timer X operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR0 active edge switch bit
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width measurement
mode
(3) Event counter mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P54 direction register to input mode.
Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width measurement
mode
Rising edge active for CNTR
Timer X stop control bit
0 : Count start
0 interrupt
(4) Pulse width measurement mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the in-
put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the corresponding port P54 direction register to input
mode.
1 : Count stop
Fig. 21 Structure of timer X mode register
✕Timer X Write Control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
✕Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P52 and P53 each time the timer X
underflows. (However, if the real time port control bit is changed
from “0” to “1” after set of the real time port data, data are output
independent of the timer X operation.) If the data for the real time
port is changed while the real time port function is valid, the
changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
✕Note on CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
26
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
b7
b0
Timer Y is a 16-bit timer that can be selected in one of four modes.
Timer Y mode register
(TYM : address 002816
)
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
(2) Period measurement mode
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously
measurement mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period measure-
ment mode is the same as in timer mode.
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for CNTR1 interrupt
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR
Timer Y stop control bit
0 : Count start
1 interrupt
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
1 : Count stop
(3) Event counter mode
Fig. 22 Structure of timer Y mode register
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
(4) Pulse width HL continuously measure-
ment mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P55 direction register to input mode.
✕Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
27
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an inadvert-
ent count down of the timer. Therefore, rewrite the value of timer
whenever the count source is changed.
b7
b0
Timer 123 mode register
(T123M :address 002916
)
T
T
OUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
OUT/φ output control bit
0 : TOUT/φ output disabled
1 : TOUT/φ output enabled
✕Timer 2 Write Control
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
✕Timer 2 Output Control
When the timer 2 (TOUT) is output enabled, an inversion signal
from pin TOUT is output each time timer 2 underflows.
In this case, set the port P56 shared with the port TOUT to the out-
put mode.
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN
)
Not used (return “0” when read)
Note: Internal clock φ is f(XCIN)/2 in the low-speed mode.
✕Note on Timer 1 to Timer 3
When the count source of timers 1 to 3 is changed, the timer
counting value may be changed large because a thin pulse is gen-
erated in count input of timer. If timer 1 output is selected as the
count source of timer 2 or timer 3, when timer 1 is written, the
counting value of timer 2 or timer 3 may be changed large be-
cause a thin pulse is generated in timer 1 output.
Fig. 23 Structure of timer 123 mode register
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
28
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB (address 001816).
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
Data bus
Serial I/O1 control register
Address 001A16
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P44/RXD
Shift clock
Clock control circuit
P46/SCLK1
Serial I/O1 synchronization
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
X
IN
Baud rate generator
Address 001C16
1/4
Clock control circuit
P47/SRDY1
Falling-edge detector
F/F
Shift clock
Transmit shift register
Transmit buffer register (TB)
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O1 status register
Address 001816
Data bus
Fig. 24 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
D
0
0
D
1
1
D
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
Serial input RXD
D
D
D
D
D
D
D
D
2
Receive enable signal SRDY1
Write signal to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Notes
1 : The transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the T
XD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 25 Operation of clock synchronous serial I/O1 function
29
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O1 control
register to “0”.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
Address 001A16
Serial I/O1 control register
OE
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Character length selection bit
7 bits
P44/RXD
STdetector
Receive shift register
1/16
8 bits
UART control register
SP detector
PE FE
Address 001B16
Clock control circuit
Serial I/O1 synchronization clock selection bit
P46/SCLK1
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
X
IN
Baud rate generator
Address 001C16
ST/SP/PA generator
1/16
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Address 001816
Address 001916
Serial I/O1 status register
Data bus
Fig. 26 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer write signal
TBE=0
TBE=0
TSC=0
TSC=1✕
SP
TBE=1
TBE=1
ST
ST
D
0
D1
Serial output TxD
D
0
D
1
SP
1 start bit
✕ Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
D
0
D
1
ST
D
0
D1
Serial input RxD
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
Notes
2 : The transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
Fig. 27 Operation of UART serial I/O1 function
30
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is write-
only and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer regis-
ter is “0”.
[Serial I/O1 Status Register (SIO1STS)]
001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the Serial I/O1 Control Register) also clears all the status
flags, including the error flags.
All bits of the serial I/O1 status register are initialized to “0” at re-
set, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift register shift comple-
tion flag (bit 2) and the transmit buffer empty flag (bit 0) become
“1”.
[Serial I/O1 Control Register (SIO1CON)]
001A16
The serial I/O1 control register contains eight control bits for the
serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
✕Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O1 transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronous with the transmission
enalbed, take the following sequence.
✕Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
✕Set the transmit enable bit to “1”.
✕Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
✕Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
31
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Serial I/O1 status register
(SIO1STS : address 001916
Serial I/O1 control register
)
(SIO1CON : address 001A16
BRG count source selection bit (CSS)
0: f(XIN
)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
)
1: f(XIN)/4
Serial I/O1 synchronization clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin
pin operates as SRDY1 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Serial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
b7
b0
UART control register
(UARTCON : address 001B16
(pins P4
1: Serial I/O1 enabled
(pins P4 –P4 operate as serial I/O pins)
4–P47 operate as ordinary I/O pins)
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
4
7
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Fig. 28 Structure of serial I/O1 control registers
32
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
The serial I/O2 function can be used only for clock synchronous
b7
b0
Serial I/O2 control register
(SIO2CON : address 001D16
serial I/O.
)
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer
is started by a write signal to the serial I/O2 register.
When an internal clock is selected as the synchronous clock of the
serial I/O2, either P62 or P63 can be selected as an output pin of
the synchronous clock. In this case, the pin that is not selected as
an output pin of the synchronous clock functions as a port.
Internal synchronous clock select bits
b2 b1 b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 0 0:
Do not set
1 0 1:
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
Serial I/O2 port selection bit
0: I/O port
[Serial I/O2 Control Register (SIO2CON)] 001D16
The serial I/O2 control register contains 8 bits which control vari-
ous serial I/O2 functions.
1: SOUT2,SCLK21/SCLK22 signal output
P61/SOUT2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output
(in output mode)
Transfer direction selection bit
0: LSB first
1: MSB first
Synchronous clock selection bit
0: External clock
1: Internal clock
Synchronous clock output pin selection bit
0: SCLK21
1: SCLK22
Fig. 29 Structure of serial I/O2 control register
Internal synchronous
clock select bits
1/8
1/16
Data bus
1/32
X
IN
1/64
1/128
1/256
P63 latch
Synchronous clock
selection bit
(Note)
“1”
P6
3
/SCLK22
Synchronous circuit
“0”
External clock
P62 latch
“0”
P6
P6
2
1
/SCLK21
/SOUT2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
(Note)
“1”
P61
latch
“0”
“1”
Serial I/O2 port selection bit
Serial I/O shift register 2 (8)
P60/SIN2
Note: It is selected by the synchronous clock selection bit, the synchronous
clock output pin selection bit, and the serial I/O port selection bit.
Fig. 30 Block diagram of serial I/O2 function
33
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output
SOUT2
D
2
D
0
D
1
D
3
D
4
D
5
D
6
D7
Serial I/O2 input SIN2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial
I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion.
When the external clock is selected as the transfer clock, a content of the serial I/O shift register is continued to shift
during inputting a transfer clock. The SOUT2 pin does not go to high impedance after transfer completion.
Fig. 31 Timing of serial I/O2 function
34
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PULSE WIDTH MODULATION (PWM)
The 3826 group has a PWM function with an 8-bit resolution,
based on a signal that is the clock input XIN or that clock input di-
vided by 2.
PWM Operation
When at least either bit 1 (PWM0 function enable bit) or bit 2
(PWM1 function enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”. When one PWM output is en-
abled and that the other PWM output is enabled, PWM output
which is enabled to output later starts pulse output from halfway.
When the PWM register or PWM prescaler is updated during
PWM output, the pulses will change in the cycle after the one in
which the change was made.
Data Setting
The PWM output pin also functions as ports P50 and P51. Set the
PWM period by the PWM prescaler, and set the period during
which the output pulse is an “H” by the PWM register.
If PWM count source is f(XIN) and the value in the PWM prescaler
is n and the value in the PWM register is m (where n = 0 to 255
and m = 0 to 255) :
PWM period = 255 ✕ (n+1)/f(XIN)
31.875 ✕ m ✕ (n+1)
µs
= 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz)
Output pulse “H” period = PWM period ✕ m/255
= 0.125 ✕ (n+1) ✕ m µs
255
PWM output
(when f(XIN) = 8 MHz)
T = [31.875 ✕ (n+1)] µs
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM cycle (when f(XIN) = 8 MHz)
Fig. 32 Timing of PWM cycle
Data bus
PWM
register pre-latch
PWM
prescaler pre-latch
PWM
enable bit
1 function
Transfer control circuit
Port P5
1
lacth
PWM
prescaler latch
PWM
register latch
Port P5
1
0
Count source
selection bit
“0”
PWM prescaler
PWM circuit
XIN
Port P5
“1”
1/2
Port P5
lacth
0
0
PWM
function
enable bit
Fig. 33 Block diagram of PWM function
35
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b0
b7
PWM control register
(PWMCON : address 002B16
)
Count source selection bit
0: f(XIN
)
1: f(XIN)/2
PWM
0: PWM
1: PWM
0
function enable bit
0
disabled
enabled
0
PWM1 function enable bit
0: PWM
1: PWM
1
disabled
enabled
1
Not used (return “0” when read)
Fig. 34 Structure of PWM control register
C
T2
B
T
=
C
A
B
PWM
(internal)
stop
Port
stop
T
T2
T
Port
PWM
PWM
0
1
output
output
Port
Port
PWM register
write signal
(Changes from “A” to “B” during “H” period)
PWM prescaler
write signal
(Changes from “T” to “T2” during PWM period)
PWM
0 function
enable bit
PWM
1 function
enable bit
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 35 PWM output timing when PWM register or PWM prescaler is changed
36
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
Comparator and Control Circuit
The functional blocks of the A-D converter are described below.
The comparator and control circuit compare an analog input volt-
age with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500kHz during A-D conversion.
Use the clock divided from the main clock XIN as the internal clock
φ.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the A-
D conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to “1”, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
b7
b0
A-D control register
(ADCON : address 003416
)
Analog input pin selection bits
0 0 0 : P6
0 0 1 : P6
0 1 0 : P6
0 1 1 : P6
1 0 0 : P6
1 0 1 : P6
1 1 0 : P6
1 1 1 : P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
AVSS and VREF by 256, and outputs the divided voltages.
V
REF input switch bit
0 : OFF
1 : ON
Channel Selector
The channel selector selects one of the input ports P67/AN7–P60/
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
AN0.
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
Fig. 36 Structure of A-D control register
Data bus
b7
b0
A-D control register
P57/ADT/DA2
3
ADT/A-D interrupt request
A-D control circuit
P60/SIN2/AN0
P6 /SOUT2/AN
1
1
2
3
4
5
6
7
A-D conversion
register
P62/SCLK21/AN
Comparator
P63/SCLK22/AN
8
P64
P65
P66
P67
/AN
/AN
/AN
/AN
Resistor ladder
AVSS
VREF
Fig. 37 A-D converter block diagram
37
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A Converter
b7
b0
The 3826 group has an on-chip D-A converter with 8-bit resolution
and 2 channels (DAi (i=1, 2)). After the DTMF/DA1 selection bit or
CTCSS/DA2 selection bit is set to “0”, the D-A converter is per-
formed by setting the value in the D-A conversion register. The
result of D-A converter is output from DAi pin by setting the DTMF/
DA1 output enable bit or CTCSS/DA2 output enable bit to “1”.
When using the D-A converter, the corresponding port direction
register bit (P56/DA1, P57/DA2) should be set to “0” (input status)
and the pull-up resistor should be in the OFF state.
D-A control register
(DACON : address 003616)
DTMF/DA1 output enable bit
0 : Disabled
1 : Enabled
CTCSS/DA2 output enable bit
0 : Disabled
1 : Enabled
The output analog voltage V is determined by the value n (base
10) in the D-A conversion register as follows:
DTMF/DA1 selection bit
0 : DA1 function
1 : DTMF function
V=VREF ✕ n/256 (n=0 to 255)
CTCSS/DA2 selection bit
0 : DA2 function
Where VREF is the reference voltage.
1 : CTCSS function
At reset, the D-A conversion registers are cleared to “0016”, the
DTMF/DA1 output enable bit or CTCSS/DA2 output enable bit are
cleared to “0”, and DAi pin goes to high impedance state. The DA
output is not buffered, so connect an external buffer when driving
a low-impedance load.
Low group ROM data selection bit
0 : Sine wave
1 : “0” fixed
High group ROM data selection bit
0 : Sine wave
1 : “0” fixed
✕✕Note on applied voltage to VREF pin
High/Low group timer write control bit
0 : Write value in latch only
1 : Write value in latch and counter
When the P56/DA1 pin and P57/DA2 pin are used as I/O ports, be
sure to apply Vcc level to VREF pin.
When these pins are used as D-A conversion output pins, the Vcc
level is recommended for the applied voltage to VREF pin.
When the voltage below Vcc level is applied, the D-A conversion
accuracy may be worse.
CTCSS timer write control bit
0 : Write value in latch only
1 : Write value in latch and counter
Fig. 38 Structure of D-A control register
Data bus
DA1 output enable bit
R-2R resistor ladder
Data bus
P56/DA1
D-A1 conversion register (8)
*
✕
Low
group
ROM
5-bit adder
Selector
8-bit timer
5-bit ✕✕32
High
group
ROM
8-bit timer
X
IN/2
5-bit ✕✕32
CTCSS
ROM
10-bit timer
8-bit ✕✕64
Selector
D-A2 conversion register (8)
* When DTMF is selected, the high-order 6 bits are automatically set
as the DTMF output.
The low-order 2 bits is set by writing data to the D-A1 conversion register.
P57/DA2
R-2R resistor ladder
DA2 output enable bit
Fig. 39 Block diagram of D-A converter
38
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DTMF Function (Dual Tone Multi Frequency)
DTMF function is used to output the result which generated auto-
matically the waveform of sine wave of two kinds of different
frequency, and added two kinds of this sine wave as an analog
value.
The digital value for one period of high group and low group out-
put is shown in Figure 40.
DTMF output is automatically input to high-order 6 bits of the D-A1
conversion register as 6-bit D-A data. The low-order 2 bits of the
D-A1 conversion register are fixed to the value written in the D-A1
conversion register.
DTMF output can be performed using DA1 function. DTMF wave-
form is output by setting “1” to the DTMF/DA1 output enable bit (bit
0 of address 003616), and setting “1” to the DTMF/DA1 selection
bit (bit 2 of address 003616). At this time, set “0” (input state) to the
direction register of ports P56/DA1 and pull-up resistor to be OFF
state.
Moreover, only the sine wave of high group can be output by set-
ting “1” to the bit 4 of the D-A control register. By setting “1” to the
bit 5 of the D-A control register similarly, only the sine wave of low
group can be output. Writing to the DTMF high group timer and
the DTMF low group timer can also be changed to “writing to latch
and timer simultaneously” by setting “1” to the bit 6 of the D-A con-
trol register. “Writing to only latch” is set after reset release. If the
D-A1 conversion register is read when the DTMF function is se-
lected, the digital value of DTMF output can be read.
In order to set two kinds of frequency which generates DTMF
waveform, value is written in the DTMF high group timer and the
DTMF low group timer, respectively. By the value n written in the
above-mentioned timer, respectively, the sine wave of the follow-
ing frequency can be generated.
f (XIN)/2
f =
(Hz)
(n+1) ✕ 32
Set “0616” or more to the DTMF high group timer and the DTMF
low group timer. After reset release, “0616” is automatically set to
them.
D-A data of low group waveform (1 period) for DTMF
7816
D-A data of high group waveform (1 period) for DTMF
7816
6416
5016
3C16
2816
6416
5016
3C16
2816
1416
1416
0
16
0
16
25
Conversion time of low group ROM
10
15
20
30
25
Conversion time of high group ROM
10
15
20
30
5
5
0
0
* This is the value set to D-A1 conversion register when the low-order 2 bits are “0”.
Fig. 40 Waveform data of high group and low group
39
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Low Groupt Frequency, High Group Frequency
Low group frequency and high group frequency are as follows.
Table 10 shows the example of frequency accuracy (at f(XIN)=4
MHz).
(1) Low group frequency
697Hz
A
B
2 3
1
4
7
*
• 697 Hz
• 770 Hz
• 852 Hz
• 941 Hz
770Hz
852Hz
941Hz
5
6
Low group
frequency
8 9 C
(2) High group frequency
0
D
#
• 1209 Hz
• 1336 Hz
• 1477 Hz
• 1633 Hz
High group frequency
Fig. 41 Key matrix of telephone and rating frequency
Table 10 Example of frequency accuracy (at f(XIN) = 4 MHz)
Rating frequency (Hz)
n (Timer value)
Output frequency (Hz)]
Error frequency (Hz)
Deviation (%)
697
770
89
80
72
65
51
46
41
37
694.4
771.6
–2.6
1.6
–0.367
0.208
0.488
0.630
–0.580
–0.460
0.750
0.720
852
856.2
4.2
941
946.9
5.9
1209
1336
1477
1633
1201.9
1329.7
1488.1
1644.7
–7.1
–6.3
11.1
11.7
40
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CTCSS Function
When reading a value from the CTCSS timer, read the high-order
byte first. By the value n written in the CTCSS timer, the sine wave
of the following frequency is generated.
(Continuous Tone-Controlled Squelch System)
The CTCSS function is used to generate the sine wave of single
frequency automatically. The CTCSS output waveform can be out-
put using DA2 function. CTCSS waveform is outputted by setting
“1” to the CTCSS/DA2 output enable bit (bit 1 of address 003616),
and setting “1” to the CTCSS/DA2 selection bit (bit 3 of address
003616). In order to set the frequency of CTCSS output, value is
written in the CTCSS timer. The CTCSS timer consists of a 10-bit
timer. When writing a value to the CTCSS timer, write the low-or-
der byte first.
f (XIN)/2
f =
(Hz)
(n+1) ✕ 64
Set “00616” or more to the CTCSS timer. “0016” is automatically
set to the high-order of the CTCSS timer and “0616” is automati-
cally set to the low-order of the CTCSS timer after reset release.
The amplitude of CTCSS output is obtained by the following for-
mula.
VCC
C =
2
If the D-A2 conversion register is read when the CTCSS function
is selected, the digital value of CTCSS output can be read.
Table 11 Example of frequency accuracy (at f(XIN) = 4 MHz)
Rating frequency (Hz)
67.0
n (Timer value)
465
Output frequency (Hz)]
67.06
Error frequency (Hz)
0.06
Deviation (%)
0.089
77.0
405
76.97
–0.03
0.027
–0.16
–0.18
0.09
–0.038
0.030
88.5
352
88.53
100.0
312
99.84
–0.160
–0.167
0.078
107.2
291
107.02
114.89
114.8
271
123.0
253
123.03
131.86
141.40
151.70
161.92
173.61
186.01
202.92
218.53
233.20
250.00
0.03
0.026
131.8
236
0.06
0.043
141.3
220
0.10
0.073
151.4
205
0.30
0.198
162.2
192
–0.28
–0.19
–0.19
–0.58
0.43
–0.174
–0.109
–0.101
–0.284
0.198
173.8
179
186.2
167
203.5
153
218.1
142
233.6
133
–0.39
–0.30
–0.167
–0.120
250.3
124
41
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and dis-
plays the data on the LCD panel.
LCD DRIVE CONTROL CIRCUIT
The 3826 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
•
Segment output enable register
•
LCD mode register
•
Table 12. Maximum number of display pixels at each duty ratio
Voltage multiplier
•
Selector
•
Duty ratio
2
Maximum number of display pixel
80 dots
Timing controller
•
Common driver
•
or 8 segment LCD 10 digits
120 dots
Segment driver
•
3
4
Bias control circuit
•
or 8 segment LCD 15 digits
160 dots
A maximum of 40 segment output pins and 4 common output pins
can be used.
or 8 segment LCD 20 digits
Up to 160 pixels can be controlled for LCD display. When the LCD
b7
b0
Segment output enable register
(SEG : address 003816
)
Segment output enable bit 0
0 : Output ports P3 –P35
0
1 : Segment output SEG18–SEG23
Segment output enable bit 1
0 : Output ports P36, P37
1 : Segment output SEG24,SEG25
Segment output enable bit 2
0 : I/O ports P00–P05
1 : Segment output SEG26–SEG31
Segment output enable bit 3
0 : I/O ports P06,P07
1 : Segment output SEG32,SEG33
Segment output enable bit 4
0 : I/O port P1
0
1 : Segment output SEG34
Segment output enable bit 5
0 : I/O ports P11–P15
1 : Segment output SEG35–SEG39
LCD output enable bit
0 : Disabled
1 : Enabled
Not used (return “0” when read)
(Do not write “1” to this bit)
b7
b0
LCD mode register
(LM : address 003916
)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 duty (use COM
1 0 : 3 duty (use COM
1 1 : 4 duty (use COM
Bias control bit
0 : 1/3 bias
0, COM
0–COM
0–COM
1)
2)
3
)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltage multiplier disable
1 : Voltage multiplier enable
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
Fig. 42 Structure of segment output enable register and LCD mode register
42
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 43 Block diagram of LCD controller/driver
43
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Voltage Multiplier (3 Times)
Bias Control and Applied Voltage to LCD
Power Input Pins
The voltage multiplier performs threefold boosting. This circuit in-
puts a reference voltage for boosting from LCD power input pin
VL1. (However, when using a 1/2 bias, connect VL1 and VL2 and
apply voltage by external resistor division.)
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 13 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Set each bit of the segment output enable register and the LCD
mode register in the following order for operating the voltage mul-
tiplier.
Table 13. Bias control and applied voltage to VL1–VL3
1. Set the segment output enable bits (bits 0 to 5) of the seg-
ment output enable register to “0” or “1.”
Bias value
Voltage value
VL3=VLCD
2. Set the duty ratio selection bits (bits 0 and 1), the bias con-
trol bit (bit 2), the LCD circuit divider division ratio selection
bits (bits 5 and 6), and the LCDCK count source selection
bit (bit 7) of the LCD mode register to “0” or “1.”
3. Set the LCD output enable bit (bit 6) of the segment output
enable register to “1.”
1/3 bias
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
1/2 bias
VL2=VL1=1/2 VLCD
Note : VLCD is the maximum value of supplied voltage for the
LCD panel.
4. Set the voltage multiplier control bit (bit 4) of the LCD mode
register to “1.”
When voltage is input to the VL1 pin during operating the voltage
multiplier, voltage that is twice as large as VL1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
VL3 pin.
When using the voltage multiplier, apply 1.3 V ≤ Voltage ≤ 2.3 V
(1.3 V ≤ Voltage ≤ 2.1 V for low voltage version) to the VL1 pin.
When not using the voltage multiplier,apply proper voltage to the
LCD power input pins (VL1–VL3). Then set the LCD output enable
bit to “1.”
When the LCD output enable bit is set to “0,” the VCC voltage is
applied to the VL3 pin inside of this microcomputer.
The voltage multiplier control bit (bit 4 of the LCD mode register)
controls the voltage multiplier.
Contrast control
Contrast control
V
V
L3
L2
V
V
L3
L2
V
V
L3
L2
R1
R2
R4
C
2
1
C
C
2
Open
Open
Open
Open
C
2
1
C
1
C
V
L1
V
L1
V
L1
R3
R5
PXx
R4=R5
R1=R2=R3
1/3 bias
1/3 bias
when not using the voltage multiplier
1/2 bias
when using the voltage multiplier
Fig. 44 Example of circuit at each bias
44
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
LCD Display RAM
Address 004016 to 005316 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
When releasing from reset, the VCC (VL3) voltage is output from
the common pins.
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the fol-
lowing equation;
Table 14. Duty ratio control and common pins used
Duty
ratio
Duty ratio selection bits
Common pins used
Bit 1
0
Bit 0
1
2
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
(frequency of count source for LCDCK)
f(LCDCK)=
3
4
1
1
0
1
(divider division ratio for LCD)
f(LCDCK)
Frame frequency=
duty ratio
Notes 1: COM2 and COM3 are open.
2: COM3 is open.
Segment Signal Output Pin
Segment signal output pins are classified into the segment-only
pins (SEG0–SEG17), the segment/output port pins (SEG18–
SEG25), and the segment/I/O port pins (SEG26–SEG39).
Segment signals are output according to the bit data of the LCD
RAM corresponding to the duty ratio. After reset release, a VCC
(=VL3) voltage is output to the segment-only pins and the seg-
ment/output port pins are the high impedance condition and
pulled up to VCC (=VL3) voltage.
Also, the segment/I/O port pins(SEG26–SEG39) are set to input
ports, and VCC (=VL3) is applied to them by pull-up resistor.
Bit
7
6
5
4
3
2
1
0
Address
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
SEG1
SEG3
SEG0
SEG2
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
SEG5
SEG4
SEG7
SEG6
SEG9
SEG8
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG33
SEG35
SEG37
SEG39
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG32
SEG34
SEG36
SEG38
Fig. 45 LCD display RAM map
45
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic
LCDCK timing
1/4 duty
Voltage level
V
V
V
L3
L2=VL1
SS
COM
0
1
2
3
COM
COM
COM
V
V
L3
SEG
0
SS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
V
V
V
L3
L2=VL1
SS
COM
COM
COM
0
1
2
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
0
COM
2
COM
1
COM
2
COM
1
COM
0
COM2
1/2 duty
V
V
V
L3
L2=VL1
SS
COM
COM
0
1
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
1
COM
0
COM
1
COM
1
COM
0
COM
1
COM0
Fig. 46 LCD drive waveform (1/2 bias)
46
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
V
VL2
VSL1S
COM
0
COM
COM
COM
1
2
3
VL3
SEG
0
VSS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
VL3
VL2
VSL1S
V
COM
COM
COM
0
1
2
VL3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
2
COM
1
COM
0
COM2
COM
2
COM
1
COM0
1/2 duty
VL3
VL2
VSL1S
V
COM
COM
0
1
VL3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
1
COM
0
COM
1
COM
0
COM
1
COM0
COM
1
COM0
Fig. 47 LCD drive waveform (1/3 bias)
47
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
✕value of high-order 6-bit counter
Watchdog Timer
✕value of STP instruction disable bit
✕value of count source selection bit.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software runaway).
When bit 6 of the watchdog timer control register (address 003716)
is set to “0,” the STP instruction is valid. The STP instruction is
disabled by rewriting this bit to “1.” At this time, if the STP instruc-
tion is executed, it is processed as an undefined instruction, so
that a reset occurs inside.
The watchdog timer consists of an 8-bit watchdog timer L and a 6-
bit watchdog timer H. At reset or writing to the watchdog timer
control register (address 003716), the watchdog timer is set to
“3FFF16.” When any data is not written to the watchdog timer con-
trol register (address 003716) after reset, the watchdog timer is in
stop state. The watchdog timer starts to count down from “3FFF16”
by writing an optional value into the watchdog timer control regis-
ter (address 003716) and an internal reset occurs at an underflow.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003716) may be
started before an underflow. The watchdog timer does not function
when an optional value has not been written to the watchdog timer
control register (address 003716). When address 003716 is read,
the following values are read:
This bit cannot be rewritten to “0” by programming. This bit is “0”
immediately after reset.
The count source of the watchdog timer becomes the system
clock φ divided by 8. The detection time in this case is set to 8.19 s
at f(XCIN) = 32 kHz and 32.768 ms at f(XIN) = 8 MHz.
However, count source of high-order 6-bit timer can be connected
to a signal divided system clock by 8 directly by writing the bit 7 of
the watchdog timer control register (address 003716) to “1.” The
detection time in this case is set to 32 ms at f(XCIN) = 32 kHz and
128 µs at f(XIN) = 8 MHz. There is no difference in the detection
time between the middle-speed mode and the high-speed mode.
“FF16” is set when
watchdog timer is
Data bus
XCIN
Watchdog timer H count
source selection bit
“0”
written to.
Watchdog timer
L (8)
“1”
“0”
Internal
Watchdog timer
system clock
selection bit
(Note)
1/16
“1”
H (6)
“3F16” is set when
watchdog timer is
written to.
XIN
Undefined instruction
Reset
STP instruction disable bit
STP instruction
Internal reset
Reset circuit
RESET
Reset release time wait
Note: This is the bit 7 of CPU mode register and is used to switch the middle-/high-speed mode and low-speed mode.
Fig. 48 Block diagram of watchdog timer
b7
b0
Watchdog timer register (address 003716
)
WDTCON
Watchdog timer H (for read-out of high-order 6 bit)
“3FFF16” is set to the watchdog timer by writing values to this address.
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selecion bit
0 : Watchdog timer L underflow
1 : f(XIN)/16 or f(XCIN)/16
Fig. 49 Structure of watchdog timer control register
f(XIN
)
1
ms (f(XIN) = 8 MHZ)
Internal
reset signal
Watchdog timer detection
Fig. 50 Timing of reset output
48
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TOUT/φ CLOCK OUTPUT FUNCTION
The internal system clock φ or timer 2 divided by 2 (TOUT output)
can be output from port P43 by setting the TOUT/φ output control
bit (bit 1) of the timer 123 mode register and the TOUT/φ output
control register. Set bit 3 of the port P4 direction register to “1”
when outputting the clock.
b7
b0
TOUT/φ output control register
(CKOUT : address 002A16
)
T
OUT/φ output control bit
0 : φ clock output
1 : TOUT output
Not used (return “0” when read)
b7
b0
Timer 123 mode register
(T123M : address 002916
)
T
T
OUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
OUT/φ output control bit
0 : TOUT/φ output disabled
1 : TOUT/φ output enabled
Timer 2 write control bit
0 : Write data in latch and timer
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode✕)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode✕)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode✕)
1 : f(XCIN
)
Not used (return “0” when read)
✕
✕ : Internal clock φ is f(XCIN)/2 in the low-speed mode.
Fig. 51 Structure of TOUT/φ output-related register
49
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD16 (high-order byte) and ad-
dress FFFC16 (low-order byte). Make sure that the reset input
voltage is less than 0.2 VCC for VCC of VCC (min.).
Power on
Power
(Note)
source
voltage
0V
RESET
VCC
Reset input
voltage
0.2 VCC
0V
Note: Reset release voltage VCC = VCC (min.)
RESET
VCC
Power source voltage
detection circuit
Fig. 52 Example of reset circuit
X
IN
φ
RESET
Internal reset
Reset address from
vector table
Address
Data
?
?
?
?
ADH,ADL
FFFC
FFFD
ADH
ADL
SYNC
Notes 1 : XIN and φ are in the relationship
: f(XIN) = 8•f(φ)
2 : A question mark (?) indicates an undefined status that depends on the previous status.
X
IN : about 8200
clock cycles
Fig. 53 Reset Sequence
50
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
(1)
(2)
000116
000316
000516
000716
000916
000B16
000D16
000F16
001516
001616
001716
001916
001A16
001B16
001D16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002E16
002F16
Port P0 direction register
Port P1 direction register
0016
0016
0016
0016
0016
0016
0016
0016
(3) Port P2 direction register
(4)
Port P3 output control register
Port P4 direction register
(5)
(6)
(7)
(8)
(9)
Port P5 direction register
Port P6 direction register
Port P7 direction register
Key input control register
0016
3F16
0016
(10) PULL register A
(11) PULL register B
(12)
(13)
(14)
(15)
Serial I/O1 status register
Serial I/O1 control register
UART control register
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0016
0
0
Serial I/O2 control register
0016
FF16
(16) Timer X (low)
(17) Timer X (high)
(18) Timer Y (low)
(19) Timer Y (high)
(20) Timer 1
FF16
FF16
FF16
FF16
0116
FF16
0016
0016
0016
0016
0016
0616
0016
(21) Timer 2
(22) Timer 3
(23)
Timer X mode register
(24) Timer Y mode register
Timer 123 mode register
(25)
(26)
TOUT/φ output control register
(27) PWM control register
CTCSS timer (low)
CTCSS timer (high)
(28)
(29)
(30)
003016
003116
003216
003316
003416
003616
003716
003816
003916
DTMF high group timer
0616
0616
0016
0016
(31) DTMF low group timer
D-A1 conversion register
D-A2 conversion register
(32)
(33)
(34) A-D control register
0
0
0
0
0
1
0
1
0
1
0
1
0
1
D-A control register
(35)
(36)
0016
Watchdog timer control register
1
1
(37) Segment output enable register
(38) LCD mode register
0016
0016
0016
(39) Interrupt edge selection register 003A16
(40) CPU mode register
003B16
003C16
003D16
003E16
003F16
0
1
0
0
0
0
0
1
(41) Interrupt request register 1
(42) Interrupt request register 2
0016
0016
0016
0016
Interrupt control register 1
Interrupt control register 2
Processor status register
(43)
(44)
(45)
(PS)
(PCH)
(PCL)
✕ ✕
✕ ✕ ✕ 1 ✕ ✕
(46) Program counter
Contents of address FFFD16
Contents of address FFFC16
Watchdog timer (high-order)
(47)
(48)
3F16
FF16
Watchdog timer (low-order)
Note: The contents of all other registers and RAM are undefined after
reset, so they must be initialized by software.
✕ : Undefined
Fig. 54 Internal state of microcomputer immediately after reset
51
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Oscillation Control
CLOCK GENERATING CIRCUIT
(1) Stop mode
The 3826 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop.
In this time, values set previously to timer 1 latch and timer 2 latch
are loaded automatically to timer 1 and timer 2. Set the values to
generate the wait time required for oscillation stabilization to timer
1 latch and timer 2 latch (low-order 8 bits of timer 1 and high-order
8 bits of timer 2) before the STP instruction.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accord-
ingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins go to high-impedance state.
Either XIN or XCIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2.
The bits of the timer 123 mode register except bit 4 are cleared to
“0”. Set the timer 1 and timer 2 interrupt enable bits to disabled
(“0”) before executing the STP instruction.
Oscillator restarts at reset or when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU until
timer 2 underflows. This allows time for the clock circuit oscillation
to stabilize when a ceramic resonator is used.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. The states of XIN and XCIN are the same as the state be-
fore the executing the WIT instruction. The internal clock restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
(2)High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
•
•
A low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
When the main clock XIN is restarted, set enough time for oscil-
lation to stabilize by programming.
Note: If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The suffi-
cient time is required for the sub-clock to stabilize, espe-
cially immediately after power-on and at returning from stop
mode. When switching the mode between middle/high-
speed and low-speed, set the frequency in the condition
that f(XIN) > 3•f(XCIN).
X
CIN
X
COUT
X
IN
X
OUT
Rf
Rd
C
OUT
C
CIN
C
COUT
CIN
Fig. 55 Ceramic resonator circuit
XCIN
XCOUT
XIN
XOUT
Rf
Open
Rd
External oscillation circuit
C
CIN
CCOUT
VCC
VSS
Fig. 56 External clock input circuit
52
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
COUT
X
CIN
Timer 1 count
source selection
bit
Timer 2 count
source selection
bit
Internal system clock selection bit
(Note)
X
IN
X
OUT
Low-speed mode
“1”
“0”
“0”
Timer 1
Timer 2
1/4
1/2
1/2
“1”
“0”
“1”
Middle-/High-speed mode
Main clock division ratio selection bit
Middle-speed mode
“1”
Timing φ
(Internal clock)
“0”
High-speed mode
or Low-speed mode
Main clock stop bit
Q
Q
S
R
S
R
S
R
Q
WIT
instruction
STP instruction
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Note: When using the low-speed mode, set the X
C
switch bit to “1”.
Fig. 57 Clock generating circuit block diagram
53
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode
(φ = 1 MHz)
High-speed mode
(φ = 4 MHz)
CM
6
“1”
“0”
CM
CM
CM
7
6
5
= 0 (8 MHz selected)
= 0 (High-speed)
= 0 (XIN oscillating)
CM
CM
CM
7
6
5
= 0 (8 MHz selected)
= 1 (Middle-speed)
= 0 (XIN oscillating)
CM
6
Low-speed mode
(φ =16 kHz)
Low-speed mode
(φ =16 kHz)
“1”
“0”
CM
CM
CM
7
6
5
= 1 (32 kHz selected)
= 1 (Middle-speed)
= 0 (XIN oscillating)
CM
CM
CM
7
6
5
= 1 (32 kHz selected)
= 0 (High-speed)
= 0 (XIN oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16
)
CM
CM
CM
CM
4 : Xc switch bit
0: Oscillation stop
1: XCIN, XCOUT
”
0
“
M5
”
0
C
“
”
M6
1
“
5
: Main clock (XIN–XOUT) stop bit
C
0: Oscillating
1: Stopped
”
1
“
6
: Main clock division ratio selection bit
0: f(XIN)/2 (high-speed mode)
1: f(XIN)/8 (middle-speed mode)
CM
6
Low-speed mode
(φ = 16 kHz)
Low-speed mode
(φ =16 kHz)
“1”
“0”
7
: Internal system clock selection bit
CM
CM
CM
7
6
5
= 1 (32 kHz selected)
CM
CM
CM
7
6
5
= 1 (32 kHz selected)
= 0 (High-speed)
= 1 (XIN stopped)
0: XIN–XOUT selected
= 1 (Middle-speed)
= 1 (XIN stopped)
(middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes
1: Switch the mode by the arrows shown between the mode blocks. (Do not switch between the mode directly without an arrow.)
2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait
mode is ended.
3: Timer and LCD operate in the wait mode.
4: When the stop mode is ended, a delay time can be set by timer 1 and timer 2 in middle-/high-speed mode.
5: When the stop mode is ended, a delay time in low-speed mode can be set as well.
6: Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-
speed mode.
7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 58 State transitions of system clock
54
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit en-
able bit, the receive enable bit, and the SRDY output enable bit to
“1”.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed.
In serial I/O2, the SOUT2 pin goes to high impedance state after
transmission is completed.
Interrupt
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt re-
quest register, execute at least one instruction before performing a
BBC or BBS instruction.
A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is at least 500kHz during an A-D conversion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
55
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
✽
1.Mask ROM Order Confirmation Form
✽
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
Table 15. Programming adapter
✽For the mask ROM confirmation and the mark specifications, re-
fer to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.maec.co.jp/indexe.htm).
Package
100P6Q-A
100P6S-A
100D0
Name of Programming Adapter
PCA4738G-100A
PCA4738F-100A
PCA4738L-100A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 59 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 59 Programming and testing of One Time PROM version
56
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Table 16 Absolute maximum ratings
Symbol
VCC
Parameter
Power source voltage
Conditions
Ratings
Unit
V
–0.3 to 7.0
VI
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67
–0.3 to VCC +0.3
V
VI
VI
VI
VI
VI
VI
VO
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
V
V
V
V
V
V
V
V
V
Input voltage P70–P77
Input voltage VL1
All voltages are based on VSS.
Output transistors are cut off.
Input voltage VL2
VL2 to 7.0
Input voltage VL3
–0.3 to 7.0
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC
–0.3 to VL3
At output port
VO
Output voltage P00–P07, P10–P15, P30–P37
At segment output
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77
–0.3 to VCC +0.3
V
VO
VO
Output voltage VL3
–0.3 to 7.0
–0.3 to VL3
V
V
VO
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
VO
–0.3 to VCC +0.3
V
Ta = 25°C
Pd
Power dissipation
Operating temperature
Storage temperature
300
–20 to 85
–40 to 125
mW
°C
°C
Topr
Tstg
RECOMMENDED OPERATING CONDITIONS
Table 17 Recommended operating conditions (1) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
V
Min.
4.0
2.5
2.5
Typ.
5.0
5.0
5.0
0
Max.
5.5
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
VCC
5.5
Power source voltage
Power source voltage
5.5
VSS
V
V
V
V
VREF
AVSS
VIA
A-D, D-A conversion reference voltage
Analog power source voltage
2.0
VCC
VCC
0
Analog input voltage AN0–AN7
AVSS
57
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18 Recommended operating conditions (2) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
VCC
“H” input voltage
“H” input voltage
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
VIH
0.7 VCC
V
V
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
VIH
0.8 VCC
VCC
VIH
VIH
“H” input voltage
“H” input voltage
“L” input voltage
RESET
XIN
0.8 VCC
0.8 VCC
VCC
VCC
V
V
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
V
V
VIL
VIL
0
0
0.3 VCC
0.2 VCC
“L” input voltage
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
VIL
VIL
“L” input voltage
“L” input voltage
0
0
0.2 VCC
0.2 VCC
V
V
RESET
XIN
58
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 19 Recommended operating conditions (3) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
–20
–20
20
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
20
80
–10
–10
10
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
10
40
–1.0
P00–P07, P10–P15, P30–P37 (Note 2)
“H” peak output current
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
IOH(peak)
IOL(peak)
IOL(peak)
–5.0
5.0
mA
mA
“L” peak output current
“L” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
10
mA
“L” peak output current
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
20
mA
mA
mA
mA
P40, P71–P77 (Note 2)
“H” average output current
“H” average output current
“L” average output current
–0.5
–2.5
2.5
P00–P07, P10–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
P00–P07, P10–P15, P30–P37 (Note 3)
“L” average output current
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
IOL(avg)
5.0
10
mA
mA
IOL(avg)
“L” average output current
P40, P71–P77 (Note 3)
Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
59
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20 Recommended operating conditions (4) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
(4.0 V ≤ VCC ≤ 5.5 V)
Unit
MHz
MHz
Min.
Max.
4.0
f(CNTR0)
f(CNTR1)
Input frequency for timers X and Y
(duty cycle 50%)
(2✕VCC)
(VCC ≤ 4.0 V)
–4
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
8.0
MHz
Main clock input oscillation frequency
(Note 1)
f(XIN)
High-speed mode
(2.5 V ≤ VCC ≤ 4.0 V)
(4✕VCC)
MHz
–8
Middle-speed mode
8.0
50
MHz
kHz
f(XCIN)
Sub-clock input oscillation frequency (Notes 1, 2)
32.768
Notes1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
60
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 21 Electrical characteristics (1) (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –1 mA
Unit
Max.
Min.
VCC–2.0
V
V
“H” output voltage
P00–P07, P10–P15, P30–P37
VOH
IOH = –0.25 mA
VCC = 2.5 V
VCC–0.8
IOH = –5 mA
VCC–2.0
VCC–0.5
V
V
“H” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67 (Note 1)
IOH = –1.5 mA
VOH
VOL
VOL
IOH = –1.25 mA
VCC = 2.5 V
VCC–0.8
V
IOL = 5 mA
2.0
0.5
V
V
“L” output voltage
P00–P07, P10–P15, P30–P37
IOL = 1.5 mA
IOL = 1.25 mA
VCC = 2.5 V
0.8
V
2.0
0.5
V
V
IOL = 10 mA
IOL = 3.0 mA
“L” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67
IOL = 2.5 mA
VCC = 2.5 V
0.8
0.5
0.3
V
IOL = 10 mA
V
V
“L” output voltage
P40, P71–P77
VOL
IOL = 5 mA
VCC = 2.5 V
Hysteresis
VT+ – VT–
0.5
V
INT0–INT2, ADT, CNTR0, CNTR1, P20–P27
0.5
0.5
Hysteresis
SCLK, RXD, SIN2
RESET
VT+ – VT–
VT+ – VT–
V
V
Hysteresis
“H” input current
P00–P07, P10–P17, P20–P27, P40–P47,
P50–P57, P60–P67, P70–P77
IIH
5.0
5.0
µA
VI = VCC
µA
µA
IIH
IIH
“H” input current RESET
“H” input current XIN
VI = VCC
VI = VCC
4.0
VI = VSS
Pull-ups “off”
–5.0
µA
µA
µA
“L” input current
VCC = 5 V, VI = VSS
Pull-ups “on”
P00–P07,P10–P17, P20–P27,P41–P47,
P50–P57, P60–P67
IIL
–60.0
–6.0
–120.0 –240.0
VCC = 2.5 V, VI = VSS
Pull-ups “on”
–25.0
–45.0
µA
µA
µA
“L” input current P40, P70–P77
“L” input current RESET
“L” input current XIN
–5.0
–5.0
IIL
IIL
IIL
VI = VSS
VI = VSS
–4.0
VCC = 5.0 V, VO = VCC, Pullup ON
Output transistors “off”
µA
µA
–60.0
–6.0
–120.0 –240.0
Output load current
P30–P37
ILOAD
VCC = 2.5 V,VO = VCC, Pullup ON
Output transistors “off”
–25.0
–45.0
VO = VCC, Pullup OFF
Output transistors “off”
µA
µA
5.0
Output leak current
P30–P37
ILEAK
VO = VSS, Pullup OFF
Output transistors “off”
–5.0
61
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 22 Electrical characteristics (2) (VCC =2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
V
Min.
2.0
Max.
5.5
VRAM
RAM retention voltage
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
8.0
2.5
mA
mA
15
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
4.0
Output transistors “off”
A-D converter stop
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
45
23
18
8
67
46
36
µA
µA
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
ICC
Power source current
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
16
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped (in STP state)
Output transistors “off”
(M3826AEF)
0.1
0.5
Ta = 25 °C
1.0
µA
µA
Ta = 85 °C
Ta = 25 °C
10
10
All oscillation stopped (in STP state)
Output transistors “off”
(M38267E8)
Ta = 55 °C
60
Power source voltage
Power source current
1.8
4.0
VL1
IL1
When using voltage multiplier
VL1 = 1.8 V
2.3
V
1.3
µA
(VL1)
(Note)
Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
62
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 23 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, 500 kHz ≤ f(XIN) ≤ 8 MHz, in middle/high-speed mode unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
–
–
Resolution
VCC = VREF = 2.7 to 5.5 V
f(XIN) = 8 MHz
±2
LSB
Absolute accuracy
(excluding quantization error)
12.5
(Note)
tCONV
Conversion time
µs
RLADDER
IVREF
IIA
Ladder resistor
12
50
35
kΩ
µA
µA
100
200
5.0
Reference power source input current
Analog port input current
VREF = 5 V
150
Note: When an internal trigger is used in middle-speed mode, it is 14 µs.
Table 24 D-A converter characteristics
(VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
%
–
–
Resolution
1.0
2.0
VCC = VREF = 5 V
Absolute accuracy
%
VCC = VREF = 2.7 V
Setting time
µs
tsu
3
Output resistor
1
4
kΩ
mA
mA
RO
2.5
(Note)
(Note)
IVREF
Reference power source M3826AEF
input current
M38267E8
3.2
6.0
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through
the A-D resistance ladder.
63
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 25 Timing requirements 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
250
105
105
80
80
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
800
370
370
220
100
1000
400
400
200
200
t
su(RXD–SCLK1)
th(SCLK1–RXD) Serial I/O1 input hold time
tc(SCLK2)
Serial I/O2 clock input cycle time (Note)
twH(SCLK2)
twL(SCLK2)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
t
su(SIN2–SCLK2)
th(SCLK2–SIN2) Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Table 26 Timing requirements 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
125
twH(XIN)
45
twL(XIN)
Main clock input “L” pulse width
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
CNTR0, CNTR1 input cycle time
500/(VCC–2)
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
250/(VCC–2)–20
250/(VCC–2)–20
230
230
2000
950
950
400
200
2000
950
950
400
300
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
ns
ns
t
su(R
X
D–SCLK1
)
ns
ns
ns
ns
ns
ns
ns
th(SCLK1–RXD) Serial I/O1 input hold time
tc(SCLK2)
Serial I/O2 clock input cycle time (Note)
twH(SCLK2)
twL(SCLK2)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
t
su(SIN2–SCLK2)
th(SCLK2–SIN2) Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
64
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 27 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
140
tC (SCLK1)/2–30
tC (SCLK1)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
td(SCLK1–TXD) Serial I/O1 output delay time (Note 1)
tv(SCLK1–TXD) Serial I/O1 output valid time (Note 1)
–30
tr(SCLK1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
30
30
tf(SCLK1)
t
t
C
C
(SCLK2)/2–160
(SCLK2)/2–160
twH(SCLK2)
twL(SCLK2)
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
0.2 ✕ t
C
(SCLK2
)
0
)
Serial I/O2 output valid time
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
40
30
30
10
10
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Table 28 Switching characteristics 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
350
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
tC (SCLK1)/2–50
tC (SCLK1)/2–50
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
–30
50
50
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
t
C
C
(SCLK2)/2–240
(SCLK2)/2–240
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
0.2 ✕ t
C
(SCLK2
)
Serial I/O2 output valid time
)
0
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
50
50
50
20
20
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
65
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Low Voltage Version)
ABSOLUTE MAXIMUM RATINGS (Low Voltage Version)
Table 29 Absolute maximum ratings (low voltage version)
Symbol
VCC
Parameter
Conditions
Ratings
Unit
V
–0.3 to 6.5
Power source voltage (Note 1)
VI
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67
–0.3 to VCC +0.3
V
VI
VI
VI
VI
VI
VI
VO
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
V
V
V
V
V
V
V
V
V
Input voltage P70–P77
Input voltage VL1
All voltages are based on VSS.
Output transistors are cut off.
Input voltage VL2
VL2 to 6.5
Input voltage VL3 (Note 2)
Input voltage C1, C2 (Note 1)
Input voltage RESET, XIN
Output voltage C1, C2 (Note 1)
–0.3 to 6.5
–0.3 to VCC +0.3
–0.3 to 6.5
–0.3 to VCC
–0.3 to VL3
At output port
VO
Output voltage P00–P07, P10–P15, P30–P37
At segment output
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77
–0.3 to VCC +0.3
V
VO
VO
Output voltage VL3 (Note 1)
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
–0.3 to 6.5
–0.3 to VL3
V
V
VO
VO
–0.3 to VCC +0.3
V
Ta = 25°C
Pd
Power dissipation
Operating temperature
Storage temperature
300
–20 to 85
–40 to 125
mW
°C
°C
Topr
Tstg
Notes 1: –0.3 V to 7.0 V for M38267M8L.
2: VL2 to 7.0 V for M38267M8L.
RECOMMENDED OPERATING CONDITIONS (Low Voltage Version)
Table 30 Recommended operating conditions (1) (low voltage version) (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
V
Min.
4.0
2.2
2.2
Typ.
5.0
5.0
5.0
0
Max.
5.5
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
VCC
5.5
Power source voltage
Power source voltage
5.5
VSS
V
V
V
V
VREF
AVSS
VIA
A-D, D-A conversion reference voltage
Analog power source voltage
2.0
VCC
VCC
0
Analog input voltage AN0–AN7
AVSS
66
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 31 Recommended operating conditions (2) (low voltage version) (VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
VCC
“H” input voltage
“H” input voltage
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
VIH
0.7 VCC
V
V
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
VIH
0.8 VCC
VCC
VIH
VIH
“H” input voltage
“H” input voltage
“L” input voltage
RESET
XIN
0.8 VCC
0.8 VCC
VCC
VCC
V
V
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
V
V
VIL
VIL
0
0
0.3 VCC
0.2 VCC
“L” input voltage
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
VIL
VIL
“L” input voltage
“L” input voltage
0
0
0.2 VCC
0.2 VCC
V
V
RESET
XIN
Table 32 Recommended operating conditions (3) (low voltage version) (VCC = 2.2 to 2.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
VCC
“H” input voltage
“H” input voltage
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
VIH
0.8 VCC
V
V
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
VIH
0.95 VCC
VCC
VIH
VIH
“H” input voltage
“H” input voltage
“L” input voltage
RESET
XIN
0.95 VCC
0.95 VCC
VCC
VCC
V
V
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
V
V
VIL
VIL
0
0
0.2 VCC
“L” input voltage
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
0.05 VCC
VIL
VIL
“L” input voltage
“L” input voltage
0
0
0.05 VCC
0.05 VCC
V
V
RESET
XIN
67
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 33 Recommended operating conditions (4) (low voltage version) (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
–20
–20
20
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
20
80
–10
–10
10
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
10
40
–1.0
P00–P07, P10–P15, P30–P37 (Note 2)
“H” peak output current
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
IOH(peak)
IOL(peak)
IOL(peak)
–5.0
5.0
mA
mA
“L” peak output current
“L” peak output current
P00–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
10
mA
“L” peak output current
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
20
mA
mA
mA
mA
P40, P71–P77 (Note 2)
“H” average output current
“H” average output current
“L” average output current
–0.5
–2.5
2.5
P00–P07, P10–P15, P30–P37 (Note 3)
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
P00–P07, P10–P15, P30–P37 (Note 3)
“L” average output current
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 3)
IOL(avg)
5.0
10
mA
mA
IOL(avg)
“L” average output current
P40, P71–P77 (Note 3)
Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
68
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 34 Recommended operating conditions (5) (low voltage version) (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
(4.0 V ≤ VCC ≤ 5.5 V)
Unit
MHz
MHz
Min.
Typ.
Max.
4.0
f(CNTR0)
f(CNTR1)
Input frequency for timers X and Y
(duty cycle 50%)
(10✕VCC
(VCC ≤ 4.0 V)
–4)/9
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
8.0
MHz
Main clock input oscillation frequency
(Note 1)
f(XIN)
High-speed mode
(2.2 V ≤ VCC ≤ 4.0 V)
(20✕VCC
MHz
–8)/9
Middle-speed mode
MHz
kHz
8.0
50
f(XCIN)
Sub-clock input oscillation frequency (Notes 1, 2)
32.768
Notes1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
69
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 35 Electrical characteristics (1) (low voltage version) (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
IOH = –1 mA
Unit
Max.
Typ.
Min.
VCC–2.0
V
V
“H” output voltage
P00–P07, P10–P15, P30–P37
VOH
IOH = –0.25 mA
VCC = 2.2 V
VCC–0.8
IOH = –5 mA
VCC–2.0
VCC–0.5
V
V
“H” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67 (Note 1)
IOH = –1.5 mA
VOH
VOL
VOL
IOH = –1.25 mA
VCC = 2.2 V
VCC–0.8
V
IOL = 5 mA
2.0
0.5
V
V
“L” output voltage
P00–P07, P10–P15, P30–P37
IOL = 1.5 mA
IOL = 1.25 mA
VCC = 2.2 V
0.8
V
2.0
0.5
V
V
IOL = 10 mA
IOL = 3.0 mA
“L” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67
IOL = 2.5 mA
VCC = 2.2 V
0.8
0.5
0.3
V
IOL = 10 mA
V
V
“L” output voltage
P40, P71–P77
VOL
IOL = 5 mA
VCC = 2.2 V
Hysteresis
VT+ – VT–
0.5
V
INT0–INT2, ADT, CNTR0, CNTR1, P20–P27
0.5
0.5
Hysteresis
SCLK, RXD, SIN2
RESET
VT+ – VT–
VT+ – VT–
V
V
Hysteresis
“H” input current
P00–P07, P10–P17, P20–P27, P40–P47,
P50–P57, P60–P67, P70–P77
IIH
5.0
5.0
µA
VI = VCC
µA
µA
IIH
IIH
“H” input current RESET
“H” input current XIN
VI = VCC
VI = VCC
4.0
VI = VSS
Pull-ups “off”
–5.0
µA
µA
µA
“L” input current
VCC = 5 V, VI = VSS
Pull-ups “on”
P00–P07,P10–P17, P20–P27,P41–P47,
P50–P57, P60–P67
IIL
–60.0
–5.0
–120.0 –240.0
VCC = 2.2 V, VI = VSS
Pull-ups “on”
–20.0
–40.0
µA
µA
µA
“L” input current P40, P70–P77
“L” input current RESET
“L” input current XIN
–5.0
–5.0
IIL
IIL
IIL
VI = VSS
VI = VSS
–4.0
VCC = 5.0 V, VO = VCC, Pullup ON
Output transistors “off”
µA
µA
–60.0
–5.0
–120.0 –240.0
Output load current
P30–P37
ILOAD
VCC = 2.2 V,VO = VCC, Pullup ON
Output transistors “off”
–20.0
–40.0
VO = VCC, Pullup OFF
Output transistors “off”
µA
µA
5.0
Output leak current
P30–P37
ILEAK
VO = VSS, Pullup OFF
Output transistors “off”
–5.0
70
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 36 Electrical characteristics (2) (low voltage version) (VCC =2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
V
Min.
2.0
Typ.
Max.
5.5
VRAM
RAM retention voltage
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
8.0
mA
mA
15
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
2.5
4.0
Output transistors “off”
A-D converter stop
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
45
23
18
8
67
46
36
µA
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
ICC
Power source current
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
16
µA
µA
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped (in STP state)
Output transistors “off”
(M38268MCL, M3826AMFL)
0.1
0.5
1.8
Ta = 25 °C
1.0
Ta = 85 °C
Ta = 25 °C
10
10
All oscillation stopped (in STP state)
Output transistors “off”
(M38267M8L)
µA
Ta = 55 °C
60
Power source voltage
Power source current
VL1
IL1
When using voltage multiplier
2.1
V
M38268MCL,
M3826AMFL
1.3
1.3
2.3
M38267M8L
1.8
4.0
VL1 = 1.8 V
µA
(VL1)
(Note)
Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
71
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 37 A-D converter characteristics (low voltage version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, 500 kHz ≤ f(XIN) ≤ 8 MHz, in middle/high-speed mode unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
–
–
Resolution
VCC = VREF = 2.7 to 5.5 V
f(XIN) = 8 MHz
±2
LSB
Absolute accuracy
(excluding quantization error)
12.5
(Note)
tCONV
Conversion time
µs
RLADDER
IVREF
IIA
Ladder resistor
12
50
35
kΩ
µA
µA
100
200
5.0
Reference power source input current
Analog port input current
VREF = 5 V
150
Note: When an internal trigger is used in middle-speed mode, it is 14 µs.
Table 38 D-A converter characteristics (low voltage version)
(VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
%
–
–
Resolution
1.0
2.0
VCC = VREF = 5 V
Absolute accuracy
%
VCC = VREF = 2.7 V
Setting time
µs
tsu
3
Output resistor
Reference power
1
4
kΩ
mA
mA
RO
2.5
(Note)
(Note)
IVREF
M38268MCL, M3826AMFL
3.2
6.0
source input current M38267M8L
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding currents flowing through
the A-D resistance ladder.
72
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 39 Timing requirements 1 (low voltage version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
250
105
105
80
80
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
800
370
370
220
100
1000
400
400
200
200
t
su(RXD–SCLK1)
th(SCLK1–RXD) Serial I/O1 input hold time
tc(SCLK2)
Serial I/O2 clock input cycle time (Note)
twH(SCLK2)
twL(SCLK2)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
t
su(SIN2–SCLK2)
th(SCLK2–SIN2) Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Table 40 Timing requirements 2 (low voltage version) (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
125
twH(XIN)
45
twL(XIN)
Main clock input “L” pulse width
40
900/(VCC–0.4)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
230
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
2000
950
ns
ns
950
t
su(R
X
D–SCLK1
)
400
ns
ns
ns
ns
ns
ns
ns
th(SCLK1–RXD) Serial I/O1 input hold time
200
tc(SCLK2)
Serial I/O2 clock input cycle time (Note)
2000
twH(SCLK2)
twL(SCLK2)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
950
950
t
su(SIN2–SCLK2
)
400
th(SCLK2–SIN2) Serial I/O2 input hold time
300
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
73
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 41 Switching characteristics 1 (low voltage version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Max.
140
Typ.
tC (SCLK1)/2–30
tC (SCLK1)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
td(SCLK1–TXD) Serial I/O1 output delay time (Note 1)
tv(SCLK1–TXD) Serial I/O1 output valid time (Note 1)
–30
tr(SCLK1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
30
30
tf(SCLK1)
t
t
C
C
(SCLK2)/2–160
(SCLK2)/2–160
twH(SCLK2)
twL(SCLK2)
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
0.2 ✕ t
C
(SCLK2
)
0
)
Serial I/O2 output valid time
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
40
30
30
10
10
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Table 42 Switching characteristics 2 (low voltage version) (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
350
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
tC (SCLK1)/2–50
tC (SCLK1)/2–50
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
–30
50
50
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
t
C
C
(SCLK2)/2–240
(SCLK2)/2–240
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
0.2 ✕ t
C
(SCLK2
)
Serial I/O2 output valid time
)
0
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
50
50
50
20
20
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
74
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1 kΩ
Measurement output pin
Measurement output pin
100 pF
100 pF
CMOS output
N-channel open-drain output (Note)
Note: When P71–P77, P40 and bit 4 of the UART control
register (address 001B16) is “1” (N-channel open-
drain output mode).
Fig. 60 Circuit for measuring output switching characteristics
75
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
t
C(CNTR)
t
WL(CNTR)
t
WH(CNTR)
0.8VCC
CNTR
0
, CNTR
1
0.2VCC
t
WL(INT)
t
WH(INT)
0.8VCC
INT0–INT
2
0.2VCC
t
W(RESET)
RESET
0.8VCC
0.2VCC
t
C(XIN)
t
WL(XIN)
t
WH(XIN)
0.8VCC
X
IN
0.2VCC
t
C(SCLK1),
t
C(SCLK2
)
t
r
t
f
t
WL(SCLK1),
t
WL(SCLK2
)
t
WH(SCLK1), WH(SCLK2)
t
S
S
CLK1
CLK2
0.8VCC
0.2VCC
t
t
su(R
X
D
-
S
CLK1),
CLK2
th(SCLK1-
R
X
D),
su(SIN2-
S
)
t
h(SCLK2-S
IN2)
R D
X
0.8VCC
0.2VCC
SIN2
t
t
v(SCLK1-T
v(SCLK2-
X
D),
t
d(SCLK1-T
X
D),td(SCLK2-
SOUT2)
SOUT2
)
TXD
SOUT2
Fig. 61 Timing diagram
76
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
MMP
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
EIAJ Package Code
JEDEC Code
–
Weight(g)
0.63
Lead Material
Cu Alloy
MD
LQFP100-P-1414-0.50
HD
D
100
76
l2
Recommended Mount Pad
1
75
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A
A
1
0
0.1
2
–
1.4
b
0.13
0.105
13.9
13.9
–
0.18
0.125
14.0
14.0
0.5
0.28
0.175
14.1
14.1
–
c
D
E
e
25
51
H
H
L
D
15.8
15.8
0.3
–
0.45
–
–
–
0°
–
16.0
16.0
0.5
1.0
0.6
0.25
–
–
16.2
16.2
0.7
–
0.75
–
0.08
0.1
10°
–
26
50
E
A
L
1
L1
F
e
Lp
A3
x
y
–
b
x
y
L
M
b2
0.225
–
14.4
14.4
I
2
0.9
–
–
–
–
–
Lp
Detail F
M
M
D
E
MMP
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
JEDEC Code
Weight(g)
1.58
Lead Material
Alloy 42
M
D
QFP100-P-1420-0.65
–
HD
D
100
81
1
80
I
2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.25
0.13
13.8
19.8
–
16.5
22.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.4
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.13
0.1
10°
–
A
A
A
1
2
0.1
2.8
0.3
0.15
14.0
20.0
0.65
16.8
22.8
0.6
1.4
–
b
c
D
E
e
30
51
31
50
HD
A
L1
HE
L
L1
x
y
–
–
F
b2
0.35
–
14.6
20.6
e
b
L
x
M
I
2
–
–
–
Detail F
y
M
M
D
E
–
77
MITSUBISHI MICROCOMPUTERS
3826 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
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•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2001 MITSUBISHI ELECTRIC CORP.
Specifications subject to change without notice.
REVISION HISTORY
3826 GROUP DATA SHEET
Rev.
Date
Description
Summary
Page
1.0
1.1
03/28/01
08/06/01
First Edition
57
66
7
Table 17 VREF Min. VCC+0.3 → VCC
Table 30 VREF Min. VCC+0.3 → VCC
1.2
05/12/01
Fig.5 M3826AEF; Under development → Mass product
Fig.6 M38268MCL; Under development → Mass product, M3826AMFL added.
Fig.11 Note for “Reserved area” added.
8
14
52
56
60
Oscillation Control (1) Stop mode revised.
URL revised; mesc → maec
Table 20 f(CNTR0), f(CNTR1); (10✕VCC–4)/9 → (2✕VCC)–4
f(XIN); (20✕VCC–8)/9 → (4✕VCC)–8
62
Table 22 ICC values revised.
(M38267E8) Ta = 85 °C → Ta = 55 °C
63
64
Table 23 VCC=VREF=5 V → VCC=VREF=2.7 to 5.5 V
Table 26 tC(CNTR); 900/(VCC+0.4) → 500/(VCC–2)
tWH(CNTR); tC(CNTR)/20 → 250/(VCC–2)–20
tWL(CNTR); tC(CNTR)/20 → 250/(VCC–2)–20
Table 29 VCC Note 1 added.
66
71
Vo; VL3 (Note 2) → (Note 1)
Table 36 (M38268MCL) → (M38268MCL, M3826AMFL)
(M38267M8L), Ta = 25 °C; 1.0 → 10
(M38267M8L) Ta = 85 °C → Ta = 55 °C
72
73
Table 37 VCC=VREF=5 V → VCC=VREF=2.7 to 5.5 V
Table 38 (M38268MCL) → (M38268MCL, M3826AMFL)
Table 40 tC(CNTR); 900/(VCC+0.4) → 900/(VCC–0.4)
(1/1)
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