M38237G3-XXXFP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38237G3-XXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总76页 (文件大小：888K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3823 Group
REJ03B0146-0202
Rev.2.02
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Jun.19.2007
●LCD drive control circuit
DESCRIPTION
Bias ................................................................................... 1/2, 1/3
Duty ...........................................................................1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 32
●Main clock generating circuits.............. Built-in feedback resistor
(connect to external ceramic resonator or quartz-crystal oscillator)
●Sub-clock generating circuits
The 3823 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 3823 group has the LCD drive control circuit, an 8-channel A/
D converter, a serial interface, a watchdog timer, a ROM correc-
tion function, and as additional functions.
The various microcomputers in the 3823 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
(connect to external quartz-crystal oscillator or on-chip oscillator)
●Power source voltage
In frequency/2 mode (f(XIN) ≤ 10 MHz) ................... 4.5 to 5.5 V
In frequency/2 mode (f(XIN) ≤ 8 MHz) ..................... 4.0 to 5.5 V
In frequency/4 mode (f(XIN) ≤ 10 MHz) ................... 2.5 to 5.5 V
In frequency/4 mode (f(XIN) ≤ 8 MHz) ..................... 2.0 to 5.5 V
In frequency/4 mode (f(XIN) ≤ 5 MHz) ..................... 1.8 to 5.5 V
In frequency/8 mode (f(XIN) ≤ 10 MHz) ................... 2.5 to 5.5 V
In frequency/8 mode (f(XIN) ≤ 8 MHz) ..................... 2.0 to 5.5 V
In frequency/8 mode (f(XIN) ≤ 5 MHz) ..................... 1.8 to 5.5 V
In low-speed mode .................................................... 1.8 to 5.5 V
●Power dissipation
FEATURES
●Basic machine-language instructions ...................................... 71
●The minimum instruction execution time ........................... 0.4 µs
(at f(XIN) = 10 MHz, High-speed mode)
●Memory size
ROM ............................................................... 16 K to 60 K bytes
RAM ................................................................. 640 to 2560 bytes
●ROM correction function .............................. 32 bytes ● 2 blocks
●Watchdog timer .............................................................. 8-bit ● 1
●Programmable input/output ports ............................................ 49
●Input ports .................................................................................. 5
In frequency/2 mode ............................................... 18 mW (std.)
(at f(XIN) = 8 MHz, Vcc = 5 V, Ta = 25 °C)
●Software pull-up/pull-down resistors (Ports P0-P7 except port P40)
In low-speed mode at XCIN ................................................ 18 µW (std.)
(at f(XIN) stopped, f(XCIN) = 32 kHz, Vcc = 2.5 V, Ta = 25 °C)
In low-speed mode at on-chip oscillator .................. 35 µW (std.)
(at f(XIN) stopped, f(XCIN) = stopped, Vcc = 2.5 V, Ta = 25 °C)
●Operating temperature range..................................– 20 to 85 °C
●Interrupts ................................................. 17 sources, 16 vectors
(includes key input interrupt)
●Key Input Interrupt (Key-on Wake-Up) ...................................... 8
●Timers ........................................................... 8-bit ● 3, 16-bit ● 2
●Serial interface ............ 8-bit ● 1 (UART or Clock-synchronized)
●A/D converter ............ 10-bit ● 8 channels or 8-bit ● 8 channels
APPLICATIONS
Camera, audio equipment, household appliances, consumer elec-
tronics, etc.
Rev.2.02 Jun 19, 2007 page 1 of 73
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3823 Group
PIN CONFIGURATION (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
7
6
5
4
3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P2
0
/KW
0
1
2
3
4
5
6
7
P2
P2
P2
P2
P2
P2
P2
1
/KW
/KW
/KW
/KW
/KW
/KW
2
3
4
5
6
2
1
M3823XGX-XXXFP
M3823XGXFP
0
7
/KW
V
CC
REF
AVSS
V
X
X
SS
OUT
IN
V
COM
COM
COM
COM
VL
3
2
1
0
P7
P7
0
/XCOUT
/XCIN
1
RESET
P4
P4
0
1
/φ
3
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Package code : PRQP0080GB-A (80P6N-A) (80-pin plastic-molded QFP)
Fig. 1 M3823XGX-XXXFP pin configuration
PIN CONFIGURATION (TOP VIEW)
40
39
38
37
36
35
61
62
63
64
65
66
67
68
P1
P1
P2
P2
P2
P2
P2
P2
P2
6
7
0
/SEG30
/SEG31
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
9
8
7
6
5
4
3
2
1
0
/KW
0
1
2
3
4
5
6
/KW
/KW
/KW
/KW
/KW
/KW
1
2
3
4
5
6
34
33
32
31
30
29
28
27
26
25
24
23
69
70
P2
7
/KW
7
M3823XGX-XXXHP
M3823XGXHP
V
CC
REF
AVSS
V
X
X
SS
OUT
IN
71
72
V
73
74
75
76
77
78
79
COM
COM
COM
COM
3
2
1
0
P70
/XCOUT
/XCIN
P7
1
RESET
P4
P4
P4
P4
0
VL3
VL2
VL1
1
/φ
/INT
/INT
22
21
2
0
1
80
3
Package code : PLQP0080KB-A (80P6Q-A) (80-pin plastic-molded LQFP)
Fig. 2 M3823XGX-XXXHP pin configuration
Rev.2.02 Jun 19, 2007 page 2 of 73
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3823 Group
Table 1 Performance overview
Function
Parameter
71
Number of basic instructions
Instruction execution time
Oscillation frequency
0.4 µs (Minimum instruction, f(XIN) 10 MHz, High-speed mode)
10 MHz (Maximum)
16 K to 60 K bytes
Memory sizes
Input port
I/O port
ROM
640 to 2560 bytes
RAM
4-bit ● 1, 1-bit ● 1
P34-P37, P40
(4 pins sharing SEG)
8-bit ● 5, 7-bit ● 1, 2 bit ● 1
P0-P2, P41-P47, P5, P6, P70, P71
(16 pins sharing SEG)
17 sources, 16 vectors (includes key input interrupt)
Interrupt
8-bit ● 3, 16-bit ● 2
Timer
8-bit ● 1 (UART or Clock-synchronized)
Serial interface
A/D converter
Watchdog timer
ROM correction function
10-bit ● 8 channels or 8 bit ● 8 channels
8-bit ● 1
32 bytes ● 2 blocks
1/2, 1/3
2, 3, 4
4
LCD drive control
circuit
Bias
Duty
Common output
Segment output
32
Built-in feedback resistor
Main clock generating circuits
(connect to external ceramic rasonator or quartz-crystal oscillator)
Built-in feedback resistor
Sub-clock generating circuits
(connect to external quartz-crystal oscillator or on-chip oscillator)
4.5 to 5.5V
Power source voltage In frequency/2 mode (f(XIN) ≤ 10MHz)
In frequency/2 mode (f(XIN) ≤ 8MHz)
In frequency/4 mode (f(XIN) ≤ 10MHz)
In frequency/4 mode (f(XIN) ≤ 8MHz)
In frequency/4 mode (f(XIN) ≤ 5MHz)
In frequency/8 mode (f(XIN) ≤ 10MHz)
In frequency/8 mode (f(XIN) ≤ 8MHz)
In frequency/8 mode (f(XIN) ≤ 5MHz)
In low-speed mode
4.0 to 5.5V
2.5 to 5.5V
2.0 to 5.5V
1.8 to 5.5V
2.5 to 5.5V
2.0 to 5.5V
1.8 to 5.5V
1.8 to 5.5V
Std. 18 mW (Vcc = 5V, f(XIN) = 8MHz, Ta = 25 °C)
Power dissipation
In frequency/2 mode
Std. 18 µW (Vcc = 2.5V, f(XIN) = stopped, f(XCIN) = 32kHz, Ta = 25 °C)
In low-speed mode at XCIN
In low-speed mode at on-chip oscillator
Input/Output withstand voltage
Output current
Std. 35 µW (Vcc = 2.5V, f(XIN) = stopped, f(XCIN) = stopped, Ta = 25 °C)
VCC
Input/Output
characteristics
10mA
-20 to 85 °C
Operating temperature range
Device structure
CMOS sillicon gate
80-pin plastic molded LQFP/QFP
Package
Rev.2.02 Jun 19, 2007 page 3 of 73
REJ03B0146-0202
3823 Group
p u e k a w n o y e K
n o i t c n u f t r o p e m i t l a e R
N I C X , φ
1 T N I , 0 T N I
3 T N I , 2 T N I
T D A
Fig. 3 Functional block diagram
Rev.2.02 Jun 19, 2007 page 4 of 73
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PIN DESCRIPTION
Table 2 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
Power source
•Apply voltage of power source to VCC, and 0 V to VSS. (For the limits of VCC, refer to “Recom-
mended operating conditions”).
VREF
AVSS
Analog refer-
ence voltage
•Reference voltage input pin for A/D converter.
Analog power
source
•GND input pin for A/D converter.
•Connect to VSS.
Reset input
Clock input
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the main clock generating circuit.
•Feedback resistor is built in between XIN pin and XOUT pin.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•This clock is used as the oscillating source of system clock.
LCD power
source
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.
VL1–VL3
•Input 0 – VL3 voltage to LCD.
Common output
•LCD common output pins.
COM0–COM3
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
SEG0–SEG11
Segment output
I/O port P0
•LCD segment output pins.
P00/SEG16–
P07/SEG23
•8-bit I/O port.
•LCD segment output pins
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each port to be individually
programmed as either input or output.
P10/SEG24–
P17/SEG31
I/O port P1
I/O port P2
•Pull-down control is enabled.
•8-bit I/O port.
•Key input (key-on wake-up) interrupt
input pins
P20/KW0 –
P27/KW7
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•4-bit input port.
•LCD segment output pins
P3
P3
4
7
/SEG12
/SEG15
–
Input port P3
•CMOS compatible input level.
•Pull-down control is enabled.
Rev.2.02 Jun 19, 2007 page 5 of 73
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Table 3 Pin description (2)
Pin
Name
Function
Function except a port function
•QzROM program power pin
Input port P4
P40
•1-bit Input port.
•CMOS compatible input level.
•7-bit I/O port.
•φ clock output pin
P41/φ
I/O port P4
•Interrupt input pins
•CMOS compatible input level.
•CMOS 3-state output structure.
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
P46/SCLK,
•Serial interface function pins
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port.
P47/SRDY/SOUT
I/O port P5
•Interrupt input pins
P50/INT2,
P51/INT3
•CMOS compatible input level.
•CMOS 3-state output structure.
•Real time port function pins
•Timer X, Y function pins
P52/RTP0,
P53/RTP1
•I/O direction register allows each pin to be individually
programmed as either input or output.
P54/CNTR0,
P55/CNTR1
•Pull-up control is enabled.
P56/TOUT
P57/ADT
•Timer 2 output pins
•A/D trigger input pins
P60/AN0–
P67/AN7
I/O port P6
•8-bit I/O port.
•A/D conversion input pins
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•2-bit I/O port.
I/O port P7
•Sub-clock generating circuit I/O pins.
P70/XCOUT,
P71/XCIN
•CMOS compatible input level.
•CMOS 3-state output structure.
(Connect a resonator. External clock
cannot be used.)
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
Rev.2.02 Jun 19, 2007 page 6 of 73
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3823 Group
PART NUMBERING
Product
M38234
G
6
-XXX FP
Package code
FP : PRQP0080GB-A package
HP : PLQP0080KB-A package
ROM number
Omitted in the shipped in blank version.
ROM/PROM size
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
The first 128 bites and the last 2 bytes of ROM are
reserved areas ; they cannot be used.
Memory type
G : QzROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
A : 2560 bytes
Fig. 4 Part numbering
Rev.2.02 Jun 19, 2007 page 7 of 73
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3823 Group
GROUP EXPANSION
Mitsubishi plans to expand the 3823 group as follows:
Package
PRQP0080GB-A ........................ 0.8 mm-pitch plastic molded QFP
PLQP0080KB-A....................... 0.5 mm-pitch plastic molded LQFP
Memory Type
Support for QzROM version.
Memory Size
ROM size ........................................................... 16 K to 60 K bytes
RAM size ............................................................ 640 to 2560 bytes
Memory Expansion Plan
ROM size (bytes)
60K
Mass production
M3823AGF
56K
48K
40K
32K
Mass production
M38239GC
Mass production
M38238G8
28K
Mass production
M38235G6
24K
20K
Mass production
M38234G4
16K
12K
8K
4K
1,024
2,560
192 256
384
512
640
768
896
1,536
2,048
RAM size (bytes)
Fig. 5 Memory expansion plan
Rev.2.02 Jun 19, 2007 page 8 of 73
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3823 Group
Currently products are listed below.
Table 4 List of products
Part No.
ROM size (bytes) ROM
RAM size
(bytes)
Package
Remarks
size for User in (
)
M3823AGF-XXXFP
M3823AGF-XXXHP
M3823AGFFP
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
61440
2560
Blank
Blank
(61310)
(Note 1)
M3823AGFHP
M38239GC-XXXFP
M38239GC-XXXHP
M38239GCFP
49152
2048
Blank
Blank
(49022)
(Note 2)
M38239GCHP
M38238G8-XXXFP
M38238G8-XXXHP
M38238G8FP
32768
1536
Blank
Blank
(32638)
(Note 2)
M38238G8HP
M38235G6-XXXFP
M38235G6-XXXHP
M38235G6FP
24576
768
Blank
Blank
(24446)
(Note 2)
M38235G6HP
M38234G4-XXXFP
M38234G4-XXXHP
M38234G4FP
16384
640
Blank
Blank
(16254)
(Note 2)
M38234G4HP
Note 1: RAM size includes RAM for LCD display and ROM corrections.
Note 2: RAM size includes RAM for LCD display.
Rev.2.02 Jun 19, 2007 page 9 of 73
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3823 Group
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3823 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The central processing unit (CPU) has six registers. Figure 6
shows the 740 Family CPU register structure.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 7.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
Store registers other than those described in Table 4 with program
when the user needs them during interrupts or subroutine calls.
transfer, etc., are executed mainly through the accumulator.
[Program Counter (PC)]
[Index Register X (X)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b7
b0
Y
Index register Y
b7
b0
S
Stack pointer
b15
b7
b0
PCH
PCL
Program counter
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 6 740 Family CPU register structure
Rev.2.02 Jun 19, 2007 page 10 of 73
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On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
Push return address
on stack
Push contents of processor
status register on stack
Interrupt
Service Routine
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTS
(S) (S) + 1
Execute RTI
(S) (S) + 1
POP return
POP contents of
processor status
register from stack
address from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
(PS)
M (S)
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
POP return
address
from stack
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 7 Register push and pop at interrupt generation and subroutine call
Table 5 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
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•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 6 Set and clear instructions of each bit of processor status register
N flag
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
–
–
Set instruction
CLI
CLV
Clear instruction
Rev.2.02 Jun 19, 2007 page 12 of 73
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3823 Group
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Port XC switch bit (Note 1)
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit (Note 2)
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (frequency/2 mode), or f(XIN)/4 (frequency/4 mode) (Note 3)
1 : f(XIN)/8 (frequency/8 mode)
Internal system clock selection bit
0 : XIN–XOUT selected (frequency/2/4/8 mode)
1 : XCIN–XCOUT, or on-chip oscillator selected (low-speed mode) (Note 4)
Note 1: In low speed mode (XCIN is selected as the system clock φ), XCIN-XCOUT oscillation does not stop even if the port X
switch bit is set to "0".
C
2: In frequency/2/4/8 mode, XIN-XOUT oscillation does not stop even if the main clock (XIN-XOUT) stop bit is set to "1".
3: When the system clock φ is divided by 4 of f(XIN), set the bit 6 in the CPU mode register to “0” after setting the bit 1
in the CPU mode extension register to “1”.
4: When using the on-chip oscillator in low-speed mode, set the bit 7 in the CPU mode register to “1” after setting the
bit 0 in the CPU mode extension register to “1”.
Fig. 8 Structure of CPU mode register
[CPU Mode Extension Register (EXPCM)] 002B16
f(XIN) divided by 4 for the system clock f and the on-chip oscillator
for the system clock f in low-speed mode can be selected by set-
ting the CPU mode extension register. When the system clock f is
divided by 4 of f(XIN), set the bit 6 in the CPU mode register to “0”
after setting the bit 1 in the CPU mode extension register to “1”.
When using the on-chip oscillator in low-speed mode, set the bit 7
in the CPU mode register to “1” after setting the bit 0 in the CPU
mode extension register to “1”.
b7
b0
CPU mode extension register
(EXPCM : address 002B16
)
On-chip oscillator control bit
0
: On-chip oscillator not used
(On -chip oscillator sotpping)
: On-chip oscillator used (Note 1)
(On -chip oscillator oscillating)
1
Frequency/4 mode control bit (Note 2)
0
1
: Frequency/2 mode φ = f(XIN)/2
: Frequency/4 mode φ = f(XIN)/4
Not used (returns “0” when read)
(Do not write “1” to this bit)
Note 1 : The on-chip oscillator is selected for the operation clock in low-speed mod regardless
of XCIN-XCOUT
.
2 : Valid only when the main clock division ratio selection bit (bit 6 in the CPU mode
register) is set to "0".
When "1" (frequency/8 mode) is selected for the main clock division ratio selection bit or
when the internal system clock selection bit is set to 1, set "0" to the frequency/4 mode
control bit.
Fig. 9 Structure of CPU mode extension register
Rev.2.02 Jun 19, 2007 page 13 of 73
REJ03B0146-0202
3823 Group
MEMORY
ROM Code Protect Address
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
“0016” is written into ROM code protect address (other than the
user ROM area) when selecting the protect bit write by using a se-
rial programmer or selecting protect enabled for writing shipment
by Renesas Technology corp.. When “0016” is set to the ROM
code protect address, the protect function is enabled, so that read-
ing or writing from/to QzROM is disabled by a serial programmer.
As for the QzROM product in blank, the ROM code is protected by
selecting the protect bit write at ROM writing with a serial pro-
grammer.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
As for the QzROM product shipped after writing, “0016” (protect
enabled) or “FF16” (protect disabled) is written into the ROM code
protect address when Renesas Technology corp. performs writing.
The writing of “0016" or “FF16” can be selected as ROM option
setup (“MASK option” written in the mask file converter) when or-
dering.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ter (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area.
Access to this area with only 2 bytes is possible in the special
page addressing mode.
RAM area
000016
RAM size
(bytes)
Address
XXXX16
SFR area
Zero page
004016
005016
640
768
02BF16
033F16
063F16
083F16
0A3F16
LCD display RAM area
1536
2048
2560
010016
RAM
XXXX16
0A0016
RAM 1 for ROM correction
0A1F16
RAM for ROM correction
ROM area
0A2016
RAM 2 for ROM correction
Address
YYYY16
Address
ZZZZ16
ROM size
(bytes)
0A4016
0A3F16
C00016
A00016
800016
400016
100016
C08016
A08016
808016
408016
108016
16384
24576
32768
49152
61440
Not used
YYYY16
ZZZZ16
Reserved ROM area
ROM
FF0016
FFDC16
Interrupt vector area
Special page
FFFE16
FFFF16
Reserved ROM area
Fig. 10 Memory map diagram
Rev.2.02 Jun 19, 2007 page 14 of 73
REJ03B0146-0202
3823 Group
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Port P0 register (P0)
Timer X low-order register (TXL)
Timer X high-order register (TXH)
Timer Y low-order register (TYL)
Timer Y high-order register (TYH)
Timer 1 register (T1)
Port P0 direction register (P0D)
Port P1 register (P1)
Port P1 direction register (P1D)
Port P2 register (P2)
Port P2 direction register (P2D)
Port P3 register (P3)
Timer 2 register (T2)
Timer 3 register (T3)
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
φ output control register (CKOUT)
Port P4 register (P4)
Port P4 direction register (P4D)
Port P5 register (P5)
Port P5 direction register (P5D)
CPU mode expansion register (EXPCM)
Temporary data register 0 (TD0)
Temporary data register 1 (TD1)
Temporary data register 2 (TD2)
RRF register (RRFR)
Port P6 register (P6)
Port P6 direction register (P6D)
Port P7 register (P7)
Port P7 direction register (P7D)
Peripheral function expansion register (EXP)
ROM correction address 1 high-order register (RCA1H)
ROM correction address 1 low-order register (RCA1L)
ROM correction address 2 high-order register (RCA2H)
ROM correction address 2 low-order register (RCA2L)
ROM correction enable register (RCR)
AD control register (ADCON)
AD conversion high-order register (ADH)
AD conversion low-order register (ADL)
Watchdog timer register (WDT)
PULL register A (PULLA)
PULL register B (PULLB)
Transmit/Receive buffer register(TB/RB)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Segment output enable register (SEG)
LCD mode register (LM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
Note: Do not access to the SFR area including nothing.
Fig. 11 Memory map of special function register (SFR)
Rev.2.02 Jun 19, 2007 page 15 of 73
REJ03B0146-0202
3823 Group
I/O PORTS
b7
b0
Direction Registers (ports P2, P41-P47, and
P5-P7)
PULL register A
(PULLA: address 001616
)
The 3823 group has 49 programmable I/O pins arranged in seven
I/O ports (ports P0–P2, P41–P47 and P5-P7). The I/O ports P2,
P41–P47 and P5-P7 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be in-
put port or output port.
P0
P1
P2
P3
P7
0
0
0
4
0
–P0
–P1
–P2
–P3
, P7
7
7
7
7
1
pull-down
pull-down
pull-up
pull-down
pull-up
Not used (return “0” when read)
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
b7
b0
PULL register B
(PULLB : address 001716
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
)
P41
P44
P50
P54
P60
P64
–P4
–P4
–P5
–P5
–P6
–P6
3
7
3
7
3
7
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
Direction Registers (ports P0 and P1)
Ports P0 and P1 have direction registers which determine the in-
put/output direction of each individual port.
Not used (return “0” when read)
0: Disable
1: Enable
Each port in a direction register corresponds to one port, each port
can be set to be input or output. When “0” is written to the bit 0 of
a direction register, that port becomes an input port. When “1” is
written to that port, that port becomes an output port. Bits 1 to 7 of
ports P0 and P1 direction registers are not used.
Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
Fig. 12 Structure of PULL register A and PULL register B
Ports P3 and P40
These ports are only for input.
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports except for port P40 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
Rev.2.02 Jun 19, 2007 page 16 of 73
REJ03B0146-0202
3823 Group
Table 7 List of I/O port function
Name
Pin
Input/Output
Input/output,
individual ports input level
Non-Port Function
I/O Format
Related SFRs
Diagram No.
P00/SEG16–
P07/SEG23
Port P0
CMOS compatible
LCD segment output
PULL register A
(1)
Segment output enable
register
CMOS 3-state output
P10/SEG24–
P17/SEG31
Port P1
Input/output,
individual bits
CMOS compatible
input level
(2)
(3)
PULL register A
P20/KW0–
P27/KW7
Port P2
Key input (key-on
wake-up) interrupt
input
Interrupt control register 2
CMOS 3-state output
Input
Input
CMOS compatible
input level
PULL register A
P34/SEG12–
P37/SEG15
LCD segment output
Port P3
Port P4
Segment output enable
register
(4)
(5)
CMOS compatible
input level
QzROM program
power pin
P40
P41/φ
φ clock output
CMOS compatible
input level
PULL register B
Input/output,
individual bits
XCIN frequency signal
output
φ
output control register
CMOS 3-state output
Peripheral function
extension register
P42/INT0,
P43/INT1
(2)
PULL register B
External interrupt input
Interrupt edge selection
register
(6)
(7)
(8)
(9)
Serial I/O function
input/output
PULL register B
P44/RXD
Serial I/O control register
Serial I/O status register
UART control register
P45/TXD
P46/SCLK
P47/SRDY/SOUT
Peripheral function
extension register
CMOS compatible
input level
External interrupt input
(2)
P50/INT2,
P51/INT3
PULL register B
Input/output,
individual bits
Port P5
Interrupt edge selection
register
CMOS 3-state output
Real time port
function output
PULL register B
P52/RTP0,
P53/RTP1
(10)
(11)
Timer X mode register
PULL register B
Timer X function I/O
P54/CNTR0
Timer X mode register
P55/CNTR1
Timer Y function input
Timer 2 function output
PULL register B
(12)
(13)
Timer Y mode register
PULL register B
P56/TOUT
P57/ADT
Timer 123 mode register
A/D trigger input
(12)
(14)
PULL register B
A/D control register
P60/AN0–
P67/AN7
Input/output,
individual bits
Port P6
Port P7
CMOS compatible
input level
A/D conversion input
CMOS 3-state output
(15)
(16)
CMOS compatible
input level
P70/XCOUT
P71/XCIN
Input/output,
individual bits
PULL register A
Sub-clock
CPU mode register
generating circuit I/O
CMOS 3-state output
LCD common output
LCD segment output
COM0–COM3
SEG0–SEG11
Output
Output
LCD mode register
(17)
(18)
Common
Segment
Notes 1: For details of how to use double function ports as function I/O ports, refer to the applicable sections.
2: When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
Especially, power source current may increase during execution of the STP and WIT instructions.
Fix the unused input pins to “H” or “L” through a resistor.
Rev.2.02 Jun 19, 2007 page 17 of 73
REJ03B0146-0202
3823 Group
(1) Ports P0, P1
(2) Ports P2, P42, P43, P50, P51
V
L2/VL3
Pull-up control
V
L1/VSS
Segment output enable bit
(Note)
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Key input (Key-on wake-up) interrupt input
INT –INT interrupt input
0
3
Pull-down control
Segment output enable bit
Note: Bit 0 of direction register.
(3) Ports P34–P37
(4) Port P4
0
V
L2/VL3
Q
Z
ROM programmable
power source
Data bus
V
L1/VSS
Data bus
Pull-down control
Segment output enable bit
(6) Port P4
4
(5) Port P4
1
Pull-up control
Pull-up control
Serial I/O enable bit
Receive enable bit
Direction register
Port latch
Direction register
Data bus
Data bus
Port latch
φ output control bit
CIN frequency signal
X
Serial I/O input
Output clock selection bit
φ
Fig. 13 Port block diagram (1)
Rev.2.02 Jun 19, 2007 page 18 of 73
REJ03B0146-0202
3823 Group
(8) Port P4
6
(7) Port P4
5
Serial I/O clock-
synchronized selection bit
Serial I/O enable bit
P-Channel output disabled selection bit
/SRDY/SOUT P-channel output disable bit
Pull-up control
P45
/TxD, P4
7
Pull-up control
Serial I/O enable bit
Transmit enable bit
Direction register
Serial I/O mode selection bit
Serial I/O enable bit
Direction register
Data bus
Port latch
Data bus
Port latch
Asynchronous serial I/O output
Synchronous serial I/O output pin selection bit
Serial I/O clock output
Serial I/O output
Serial I/O clock input
(synchronous or asynchronous)
(10) Ports P52, P5
3
(9) Port P4
7
Pull-up control
P-Channel output disabled selection bit
/SRDY/SOUT P-channel output disable bit
Serial I/O mode selection bit
P45/TxD, P47
Pull-up control
Serial I/O enable bit
S
RDY,SOUT output enable bit
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
Synchronous serial I/O output
Real time port control bit
Data for real time port
Synchronous serial I/O output pin selection bit
Serial I/O ready output
(11) Port P5
4
(12) Ports P55, P5
7
Pull-up control
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Timer X operating mode bit
(Pulse output mode selection)
Timer output
CNTR
1 interrupt input
A/D trigger interrupt input
CNTR
0
interrupt input
Fig. 14 Port block diagram (2)
Rev.2.02 Jun 19, 2007 page 19 of 73
REJ03B0146-0202
3823 Group
(14) Port P6
(13) Port P56
Pul-up control
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
T
OUT output control bit
Timer output
A/D conversion input
Analog input pin selection bit
(15) Port P70
(16) Port P71
Port X
C
switch bit + Pull-up control
Port XC switch bit + Pull-up control
Port X
C
switch bit
Port X
C
switch bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Oscillation circuit
Port P7
Sub-clock generating circuit input
1
Port XC switch bit
(17) COM0–COM3
(18) SEG0–SEG11
VL2/VL3
VL3
The voltage applied to the sources of
VL1/VSS
P-channel and N-channel transistors
is the controlled voltage by the bias
value.
V
L2
L1
The gate input signal of each transistor is
controlled by the LCD duty ratio and the
bias value.
V
Fig. 15 Port block diagram (3)
Rev.2.02 Jun 19, 2007 page 20 of 73
REJ03B0146-0202
3823 Group
Termination of unused pins
• Termination of common pins
I/O ports:
Select an input port or an output port and follow
each processing method.
Output ports: Open.
Input ports: If the input level become unstable, through current
flow to an input circuit, and the power supply current
may increase.
Especially, when expecting low consumption current
(at STP or WIT instruction execution etc.), pull-up or
pull-down input ports to prevent through current
(built-in resistor can be used). Pull-down the P40/
(VPP) pin.
We recommend processing unused pins through a
resistor which can secure IOH(avg) or IOL(avg).
Because, when an I/O port or a pin which have an
output function is selected as an input port, it may
operate as an output port by incorrect operation etc.
Rev.2.02 Jun 19, 2007 page 21 of 73
REJ03B0146-0202
3823 Group
Table 8 Termination of unused pins
Termination 1 (recommend)
Termination 2
Pin
Termination 3
–
I/O port
When selecting SEG output, open.
P00/SEG16–P17/SEG23
P10/SEG24–P17/SEG31
P20/KW0–P27/KW7
When selecting KW function, perform
termination of input port.
–
Input port
When selecting SEG output, open.
P34/SEG12–P37/SEG15
P40/(VPP)
–
–
–
–
Input port (pull-down)
I/O port
–
When selecting φ output, open.
P41/φ
When selecting INT0 function,
perform termination of input port.
P42/INT0
When selecting INT1 function,
perform termination of input port.
P43/INT1
–
–
–
When selecting RXD function,
perform termination of input port.
P44/RxD
When selecting TXD function,
perform termination of output port.
P45/TxD
When selecting external clock input,
perform termination of input port.
P46/SCLK
When selecting internal clock output,
perform termination of output port.
When selecting SRDY function,
perform termination of output port.
P47/SRDY/SOUT
P50/INT2
When selecting SOUT function,
perform termination of output port.
When selecting INT2 function,
perform termination of input port.
–
–
–
–
When selecting INT3 function,
perform termination of input port.
P51/INT3
When selecting RTP0 function,
perform termination of output port.
P52/RTP0
P53/RTP1
P54/CNTR0
P55/CNTR1
P56/TOUT
When selecting RTP1 function,
perform termination of output port.
When selecting CNTR0 input function,
perform termination of input port.
When selecting CNTR0 output function,
perform termination of output port.
When selecting CNTR1 function,
perform termination of input port.
–
When selecting TOUT function,
perform termination of output port.
–
–
–
When selecting ADT function,
perform termination of input port.
P57/ADT
When selecting AN function, these
pins can be opened. (A/D conversion
result cannot be guaranteed.)
P60/AN0–P67/AN7
Do not select XCIN-XCOUT oscillation
function by program.
P70/XCOUT
P71/XCIN
–
Connect to VSS
Connect to VSS
Connect to VSS
Open
–
–
–
–
–
–
–
–
VL3 (Note)
VL2 (Note)
VL1 (Note)
COM0–COM3
–
–
–
–
–
–
–
–
Open
SEG0–SEG11
Connect to VSS
Connect to VCC or VSS
AVSS
VREF
XOUT
When an external clock is
input to the XIN pin, leave
the XOUT pin open.
Note : The termination of VL3, VL2 and VL1 is applied when the bit 3 of the LCD mode register is “0”
Rev.2.02 Jun 19, 2007 page 22 of 73
REJ03B0146-0202
3823 Group
An interrupt requests is accepted when all of the following
conditions are satisfied:
INTERRUPTS
The 3823 group interrupts are vector interrupts with a fixed prior-
• Interrupt disable flag.................................“0”
• Interrupt disable request bit .....................“1”
• Interrupt enable bit................................... “1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
ity scheme, and generated by 16 sources among 17 sources: 8
external, 8 internal, and 1 software.
(1)
The interrupt sources, vector addresses
are shown in Table 9.
, and interrupt priority
Each interrupt except the BRK instruction interrupt has the inter-
rupt request bit and the interrupt enable bit. These bits and the
interrupt disable flag (I flag) control the acceptance of interrupt re-
quests. Figure 16 shows an interrupt control diagram.
Table 9 Interrupt vector addresses and priority
Interrupt Request
Remarks
Vector Addresses (Note 1)
Interrupt Source
Priority
High
Low
Generating Conditions
Reset (Note 2)
At reset
1
2
FFFD16
FFFB16
FFFC16
FFFA16
Non-maskable
INT0
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT1 input
INT1
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
External interrupt
(active edge selectable)
3
4
Serial I/O
reception
At completion of serial interface
data reception
Valid when serial interface is se-
lected
At completion of serial interface
transmit shift or when transmis-
sion buffer is empty
Serial I/O
transmission
5
Valid when serial interface is se-
lected
Timer X
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
Timer Y
Timer 2
Timer 3
8
9
CNTR0
At detection of either rising or
falling edge of CNTR0 input
10
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR1 input
CNTR1
11
FFE916
FFE816
External interrupt
(active edge selectable)
FFE616
FFE416
At timer 1 underflow
Timer 1
INT2
12
13
FFE716
FFE516
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
INT3
At detection of either rising or
falling edge of INT3 input
14
15
16
FFE316
FFE116
FFDF16
FFE216
FFE016
FFDE16
External interrupt
(active edge selectable)
Key input
(Key-on wake-up)
At falling of conjunction of input External interrupt
level for port P2 (at input mode)
(Valid at falling)
Valid when ADT interrupt is se-
lected, External interrupt
(Valid at falling)
ADT
At falling of ADT input
At completion of A/D conversion
At BRK instruction execution
A/D conversion
BRK instruction
Valid when A/D interrupt is se-
lected
17
FFDD16
FFDC16
Non-maskable software interrupt
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.2.02 Jun 19, 2007 page 23 of 73
REJ03B0146-0202
3823 Group
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
interrupt request
Fig. 16 Interrupt control diagram
Interrupt Disable Flag
Interrupt Source Selection
The interrupt disable flag is assigned to bit 2 of the processor sta-
tus register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is set
to “0”, acceptance of interrupt requests is enabled. This flag is set
to “1” with the SET instruction and set to “0” with the CLI instruc-
tion.
The following combinations can be selected by the interrupt
source selection bit of the AD control register (bit 6 of the address
003916).
• ADT or A/D conversion (refer Table 9)
When an interrupt request is accepted, the contents of the proces-
sor status register are pushed onto the stack while the interrupt
disable flag remaines set to “0”. Subsequently, this flag is auto-
matically set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI instruc-
tion within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
Interrupt Request Bits
Once an interrupt request is generated, the corresponding inter-
rupt request bit is set to “1” and remaines “1” until the request is
accepted. When the request is accepted, this bit is automatically
set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
Interrupt Enable Bits
The interrupt enable bits control the acceptance of the corre-
sponding interrupt requests. When an interrupt enable bit is set to
“0”, the acceptance of the corresponding interrupt request is dis-
abled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Rev.2.02 Jun 19, 2007 page 24 of 73
REJ03B0146-0202
3823 Group
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
0
1
2
3
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (return “0” when read)
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
)
(IREQ1 : address 003C16
)
INT
INT
0
1
interrupt request bit
interrupt request bit
CNTR
CNTR
0
1
interrupt request bit
interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
INT
INT
2
interrupt request bit
interrupt request bit
3
Timer Y interrupt request bit
Key input interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
CNTR
0
1
interrupt enable bit
interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
INT
2
interrupt enable bit
interrupt enable bit
INT
3
Timer Y interrupt enable bit
Key input interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 17 Structure of interrupt-related registers
Rev.2.02 Jun 19, 2007 page 25 of 73
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●Notes
Interrupt Request Generation, Acceptance,
and Handling
The interrupt request bit may be set to “1” in the following cases.
•When setting the external interrupt active edge
Related registers: Interrupt edge selection register
(address 003A16)
Interrupts have the following three phases.
(i) Interrupt Request Generation
An interrupt request is generated by an interrupt source (ex-
ternal interrupt signal input, timer underflow, etc.) and the
corresponding request bit is set to “1”.
Timer X mode register (address 002716)
Timer Y mode register (address 002816)
If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1) Set the corresponding enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit (the active edge switch
bit) or the interrupt source bit.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance con-
ditions (interrupt request bit, interrupt enable bit, and interrupt
disable flag) and interrupt priority levels for accepting interrupt
requests. When two or more interrupt requests are generated
simultaneously, the highest priority interrupt is accepted. The
value of interrupt request bit for an unaccepted interrupt re-
mains the same and acceptance is determined at the next
interrupt acceptance timing point.
(3) Set the corresponding interrupt request bit to “0” after one or
more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
(iii) Handling of Accepted Interrupt Request
Interrupt request
generated
Interrupt request
acceptance
Interrupt routine
starts
The accepted interrupt request is processed.
Interrupt sequence
Figure 18 shows the time up to execution in the interrupt process-
ing routine, and Figure 19 shows the interrupt sequence.
Figure 20 shows the timing of interrupt request generation, inter-
rupt request bit, and interrupt request acceptance.
Stack push and
Vector fetch
Interrupt handling
Main routine
routine
*
0 to 16 cycles
7 cycles
Interrupt Handling Execution
When interrupt handling is executed, the following operations are
performed automatically.
7 to 23 cycles
(1) Once the currently executing instruction is completed, an inter-
rupt request is accepted.
*
When executing DIV instruction
(2) The contents of the program counters and the processor status
register at this point are pushed onto the stack area in order
from 1 to 3.
Fig. 18 Time up to execution in interrupt routine
1. High-order bits of program counter (PCH)
2. Low-order bits of program counter (PCL)
3. Processor status register (PS)
Push onto stack
Vector fetch
Execute interrupt
routine
(3) Concurrently with the push operation, the jump address of the
corresponding interrupt (the start address of the interrupt pro-
cessing routine) is transferred from the interrupt vector to the
program counter.
φ
SYNC
RD
(4) The interrupt request bit for the corresponding interrupt is set
to “0”. Also, the interrupt disable flag is set to “1” and multiple
interrupts are disabled.
WR
Address bus
Data bus
PC
S,SPS S-1,SPS S-2,SPS
BL
BH
AL,AH
(5) The interrupt routine is executed.
Not used
PCH
PCL
PS
AL
AH
(6) When the RTI instruction is executed, the contents of the reg-
isters pushed onto the stack area are popped off in the order
from 3 to 1. Then, the routine that was before running interrupt
processing resumes.
SYNC :CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH:Vector address of each interrupt
AL, AH:Jump destination address of each interrupt
SPS :“0016” or “0116
”
([SPS] is a page selected by the stack page selection bit of CPU mode register.)
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each inter-
rupt to execute the interrupt processing routine.
Fig. 19 Interrupt sequence
Rev.2.02 Jun 19, 2007 page 26 of 73
REJ03B0146-0202
3823 Group
Push onto stack
Vector fetch
Instruction cycle
Instruction cycle
Internal clock φ
SYNC
1
2
T1
IR1 T2
IR2 T3
T1 T2 T3: Interrupt acceptance timing points
IR1 IR2: Timings points at which the interrupt request bit is set to “1”.
Note: Period 2 indicates the last φ cycle during one instruction cycle.
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt requests
are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2 separately.
Fig. 20 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
Rev.2.02 Jun 19, 2007 page 27 of 73
REJ03B0146-0202
3823 Group
“1” to “0”. An example of using a key input interrupt is shown in
Figure 21, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P20–P23.
Key Input Interrupt (Key-on wake-up)
A Key-on wake-up interrupt request is generated by applying a
falling edge to any pin of port P2 that have been set to input mode.
In other words, it is gener1ated when AND of input level goes from
Port PX
X
“L” level output
PULL register A bit 2 = “1”
Port P2
direction register = “1”
7
Key input interrupt request
●
●●
●●
●●
●●
Port P2
latch
7
P2
7
output
output
Port P2
6
direction register = “1”
●
Port P2
latch
6
P2
6
Port P2
5
direction register = “1”
●
●
Port P2
latch
5
P2
5
output
output
Port P2
4
direction register = “1”
Port P2
latch
4
P2
4
Port P2
direction register = “0”
3
Port P2
●
●
●●
●●
Input reading circuit
Port P2
latch
3
P2
P2
3
input
Port P2
direction register = “0”
2
Port P2
latch
2
2
input
input
Port P2
direction register = “0”
1
●
●●
Port P2
latch
1
P2
1
Port P2
0
direction register = “0”
●
●
Port P2
latch
0
P2
0
input
● P-channel transistor for pull-up
●● CMOS output buffer
Fig. 21 Connection example when using key input interrupt and port P2 block diagram
Rev.2.02 Jun 19, 2007 page 28 of 73
REJ03B0146-0202
3823 Group
responding to that timer is set to “1”.
TIMERS
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
The 3823 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
Real time port
control bit “1”
Q D
Data bus
P5
2
3
data for real time port
P5
2
Latch
“0”
P5 latch
P52
direction register
2
Real time port
control bit “1”
Q D
P5
data for real time port
P53
Real time port
control bit “0”
Latch
“0”
P5
3
direction register
f(XIN)/16
Timer X mode register
write signal
P53 latch
“1”
(f(SUB)/16 in low-speed mode●)
Timer X stop
control bit
Timer X write
control bit
CNTR
0
active
edge switch bit
“0”
Timer X operat-
ing mode bits
“00”,“01”,“11”
Timer X (low) latch (8)
Timer X (high) latch (8)
Timer X
interrupt
request
P54/CNTR0
Timer X (low) (8)
Timer X (high) (8)
“10”
“1”
Pulse width
CNTR
0
measurement
interrupt
request
mode
CNTR
edge switch bit
0
active
Pulse output
mode
“0”
“1”
S
Q
Q
Timer Y operating mode bits
“00”,“01”,“10”
T
CNTR
interrupt
request
1
P54 direction register
Pulse width HL continuously measurement mode
Rising edge detection
P54 latch
“11”
Pulse output mode
Period
measurement mode
Falling edge detection
f(XIN)/16
(f(SUB)16 in low-speed mode )
●
Timer Y stop
control bit
CNTR1 active
edge switch bit
“0”
“00”,“01”,“11”
Timer Y (low) latch (8)
Timer Y (high) latch (8)
Timer Y (high) (8)
Timer Y
interrupt
request
P55/CNTR1
Timer Y (low) (8)
“10”
Timer Y operating
mode bits
“1”
f(XIN)/16
Timer 1
interrupt
request
(f(SUB)/16 in low-speed mode])
Timer 1 count source
selection bit
“0”
Timer 2 write
control bit
Timer 2 count source
selection bit
Timer 2 latch (8)
Timer 1 latch (8)
Timer 1 (8)
“0”
Timer 2
interrupt
request
f(SUB)
“1”
Timer 2 (8)
“1”
f(XIN)/16
●
(f(SUB)/16 in low-speed mode )
T
OUT output
TOUT output
control bit
active edge
switch bit
T
OUT output
control bit
“0”
S
Q
Q
P56/TOUT
T
“1”
P5
6
latch
P56 direction register
Timer 3 latch (8)
“0”
Timer 3
interrupt
request
Timer 3 (8)
f(XIN)/16(f(SUB)/16 in low-speed mode●)
“1”
Timer 3 count
●
f(SUB) is the source oscillation frequency in low-speed mode.
f(SUB) shows the oscillation frequency of XCIN or the on-chip
oscillator.
source selection bit
Internal clock φ is f(SUB)/2 in the low-speed mode.
Fig. 22 Timer block diagram
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3823 Group
Timer X
●Real time port control
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
While the real time port function is valid, data for the real time port
are output from ports P52 and P53 each time the timer X
underflows. (However, after rewriting a data for real time port, if
the real time port control bit is changed from “0” to “1”, data are
output independent of the timer X operation.) If the data for the
real time port is changed while the real time port function is valid,
the changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
(1) Timer Mode
The timer counts f(XIN)/16 (or f(SUB)/16 in low-speed mode).
f(SUB) is the source oscillation frequency in low-speed mode.
f(SUB) shows the oscillation frequency of XCIN or the on-chip os-
cillator. Internal clock φ is f(XCIN)/2 in the low-speed mode.
(2) Pulse Output Mode
●Note on CNTR0 interrupt active edge
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the corresponding port P54 direction register to output mode.
selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
(3) Event Counter Mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P54 direction register to input mode.
b7
b0
Timer X mode register
(TXM : address 002716
)
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
(4) Pulse Width Measurement Mode
The count source is f(XIN)/16 (or f(SUB)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the in-
put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the corresponding port P54 direction register to input
mode.
P5
2
data for real time port
data for real time port
P53
Timer X operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR0 active edge switch bit
●Timer X write control
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
measurement mode
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
measurement mode
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, when writing in the timer latch at
the timer underflow, the value is set in the timer and the latch at
one time. Additionally, unexpected value may be set in the high-or-
der counter when the writing in high-order latch and the underflow
of timer X are performed at the same timing.
Rising edge active for CNTR
Timer X stop control bit
0 : Count start
0 interrupt
1 : Count stop
Fig. 23 Structure of timer X mode register
Rev.2.02 Jun 19, 2007 page 30 of 73
REJ03B0146-0202
3823 Group
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7
b0
(1) Timer Mode
The timer counts f(XIN)/16 (or f(SUB)/16 in low-speed mode).
Timer Y mode register
(TYM : address 002816
)
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
(2) Period Measurement Mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period
measurement mode is the same as in timer mode.
0
0
1
0 : Timer mode
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously measurement
mode
1
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR
Timer Y stop control bit
0 : Count start
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
1 interrupt
1 : Count stop
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
Fig. 24 Structure of timer Y mode register
(4) Pulse Width HL Continuously Measurement
Mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P55 direction register to input mode.
●Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
Rev.2.02 Jun 19, 2007 page 31 of 73
REJ03B0146-0202
3823 Group
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an
inadvertent count down of the timer, rewrite the value of timer
whenever the count source is changed.
b7
b0
Timer 123 mode register
(T123M :address 002916
)
T
OUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
TOUT output control bit
0 : TOUT output disabled
1 : TOUT output enabled
●Timer 2 write control
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
1 : f(XIN)/16
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
(or f(SUB)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(SUB)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(SUB)/16 in low-speed mode)
1 : f(SUB)
●Timer 2 output control
When the timer 2 (TOUT) is output enabled, an inversion signal
from the TOUT pin is output each time timer 2 underflows.
In this case, set the port shared with the TOUT pin to the output
mode.
Not used (return “0” when read)
Note: f(SUB) is the source oscillation frequency in low-speed
mode. f(SUB) shows the oscillation frequency of XCIN or
the on-chip oscillator.
●Notes on timer 1 to timer 3
Internal clock φ is f(SUB)/2 in the low-speed mode.
When the count source of timer 1 to 3 is changed, the timer count-
ing value may be changed large because a thin pulse is generated
in count input of timer . If timer 1 output is selected as the count
source of timer 2 or timer 3, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a thin
pulse is generated in timer 1 output.
Fig. 25 Structure of timer 123 mode register
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Rev.2.02 Jun 19, 2007 page 32 of 73
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3823 Group
(1) Clock Synchronous Serial I/O Mode
SERIAL INTERFACE
Clock synchronous serial I/O can be selected by setting the mode
Serial I/O
selection bit of the serial I/O control register to “1”.
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
The MSB first transfer is selected as the transfer direction by setting
the bit 0 in the peripheral function expansion register to “1”. Also, the
synchronous serial I/O output switches to the P47/SRDY/SOUT pin by
setting the bit 1 in the peripheral function expansion register to “1”.
Data bus
Address 001A16
Receive buffer full flag (RBF)
Serial I/O control register
Address 001816
Receive buffer register
Transfer direction selection bit
P4 /R
Receive shift register
Receive interrupt request (RI)
4
XD
Shift clock
Clock control circuit
P46/SCLK
Serial I/O
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN
)
Baud rate generator
Address 001C16
1/4
(f(SUB) in low-speed mode)
1/4
Serial output pin selection bit
Clock control circuit
Falling-edge detector
F/F
P47/SRDY1/SOUT
Shift clock
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit shift register
Transmit buffer register
Transmit interrupt request (TI)
P45/TXD
Serial output pin
selection bit
Transfer direction
selection bit
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O status register
Address 001816
Data bus
Note: f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Fig. 26 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
(or SOUT)
Serial input RXD
D0
TxD and RxD above shows the operation when selecting LSB first transfer.
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 001816)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
1 : The transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE=1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
Notes
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 27 Operation of clock synchronous serial I/O function
Rev.2.02 Jun 19, 2007 page 33 of 73
REJ03B0146-0202
3823 Group
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
Address 001A16
Receive buffer full flag (RBF)
Serial I/O control register
OE
Receive buffer register
Receive interrupt request (RI)
Character length selection bit
7 bits
P44/RXD
STdetector
Receive shift register
1/16
8 bits
PE FE
UART control register
SP detector
Address 001B16
Clock control circuit
Serial I/O synchronous clock selection bit
P46/SCLK
Frequency division ratio 1/(n+1)
BRG count source selection bit
(f(SUB) in low-speed mode)
f(XIN
)
Baud rate generator
Address 001C16
1/4
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
Transmit interrupt source selection bit
P45
/T
X
D
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Address 001916
Serial I/O status register
Address 001816
Data bus
Note: f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Internal clock φ is f(SUB)/2 in the low-speed mode.
Fig. 28 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0
TSC=0
TBE=0
TSC=1●
SP
TBE=1
TBE=1
ST
D
0
D1
ST
D
0
D1
SP
Serial output TXD
1 start bit
●Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
D
0
D
1
ST
D
0
D1
Serial input RXD
Notes
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 29 Operation of UART serial I/O function
Rev.2.02 Jun 19, 2007 page 34 of 73
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confirming that the transmit shift register is set to “1”, and then
(3) Synchronous/Asynchronous Alternate
Transmit Mode
______
changing the serial I/O mode selection bit. The SRDY output func-
tion cannot be used when the clock synchronous serial I/O is
selected. Also, when using the internal clock for the transfer clock
(the serial I/O synchronous clock selection bit is set to “0”), apply
“H” output to the P46 pin. The other operation is the same as clock
synchronous serial I/O mode and asynchronous serial I/O mode
(UART).
Synchronous/asynchronous alternate transmit mode is selected
by setting the transmit enable bit in the serial I/O control register to
“1” after setting the synchronous serial I/O output pin selection bit
in the peripheral function expansion register to “1”. Set the syn-
chronous serial I/O output pin selection bit to “1” when the serial I/
O mode selection bit is set to “0”. In this mode, transmit cannot be
performed continuously. Write to the transmit buffer register after
P46/SCLK
Serial I/O synchronous
clock selection bit
BRG count source
selection bit
f(XIN
)
Baud rate generator
1/4
(Note)
f(SUB) in low-speed mode
Frequency division
ratio 1/(n+1)
1/4
Clock control circuit
Transmit shift register shift
completion flag (TSC)
P4
7
/SRDY/SOUT
Serial I/O mode
selection bit (SIOM)
(
Synchronous output
)
Shift clock
Transmit shift register
Transmit interrupt request (TI)
P45/TXD
(
Asynchronous output)
Transmit buffer empty flag (TBE)
Serial I/O status register
Transmit buffer register
Address 001816
Address 001916
Date bus
Note: f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Fig. 30 Block diagram of synchronous/asynchronous alternate transmit
TBE=1
TSC=0
TBE=1
TSC=0
TSC=0
P46/SCLK
TSC=0
TBE=1
TBE=1
TSC=0
TSC=1
SP
TSC=1
SP
P45/TXD
(
Asynchronous output
)
ST
D1
D1
D7
ST
D1
D1
D7
P47/SOUT
(
synchronous output
)
D0
D6
D7
D1
D0
synchronous serial I/O
output selection bit
TBE=0
TBE=0
TBE=0
TBE=0
Transmit buffer
write signal
Serial I/O mode
selection bit
Synchronous
transmit
Synchronous transmit
Asynchronous transmit
Asynchronous transmit
Fig. 31 Operation of synchronous/asynchronous alternate transmit function
Rev.2.02 Jun 19, 2007 page 35 of 73
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[Transmit Buffer/Receive Buffer Register
(TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is
write-only and the receive buffer register is read-only. If a charac-
ter bit length is 7 bits, the MSB of data stored in the receive buffer
register is “0”.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE. Writ-
ing “0” to the serial I/O enable bit (SIOE) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register contains eight control bits for the se-
rial I/O function.
[UART Control Register (UARTCON) ]001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
●Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
●Set the serial I/O transmit interrupt enable bit to “0” (disabled).
●Set the transmit enable bit to “1”.
●Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
●Set the serial I/O transmit interrupt enable bit to “1” (enabled).
Rev.2.02 Jun 19, 2007 page 36 of 73
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3823 Group
b7
b0
b7
b0
Serial I/O status register
(SIOSTS : address 001916
Serial I/O control register
(SIOCON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(SUB) in low-speed mode)
1: f(XIN)/4 (f(SUB)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O synchronization clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronized serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronized serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY, SOUT output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin
7
pin operates as SRDY or SOUT output pin
Set the transmit disable bit and SRDY, SOUT output enable bits
to “0” to disable transmit when selecting SOUT. (Setting
peripheral function extension register is necessary when
selecting SOUT.)
Parity error flag (PE)
0: No error
1: Parity error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Framing error flag (FE)
0: No error
1: Framing error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Not used (returns “1” when read)
Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
b7
b0
UART control register
(UARTCON : address 001B16
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P4
1: Serial I/O enabled
(pins P4 –P4 operate as serial I/O pins)
4–P47 operate as ordinary I/O pins)
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
4
7
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD, P47/SRDY/SOUT P-channel output disable bit (POFF) (Note)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Notes
1 : The peripheral function extension register is used to choose P4
5/TXD, P47/SRDY/SOUT.
2 : f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Fig. 32 Structure of serial I/O control registers
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3823 Group
A/D CONVERTER
[AD Conversion Register (ADH, ADL)] 003516
The AD conversion register is a read-only register that contains
the result of an A/D conversion. When reading this register during
an A/D conversion, the previous conversion result is read.The
high-order 8 bits of a conversion result is stored in the AD conver-
sion high-order register (address 003516),and the low-order 2 bits
of the same result are stored in bit 7 and bit 6 of the AD conver-
sion low-order register (address 003616).
b7
b0
AD control register
(ADCON : address 003416
)
Analog input pin selection bits
0 0 0 : P6
0 0 1 : P6
0 1 0 : P6
0 1 1 : P6
1 0 0 : P6
1 0 1 : P6
1 1 0 : P6
1 1 1 : P6
0/AN
1/AN
2/AN
3/AN
4/AN
5/AN
6/AN
7/AN
0
1
2
3
4
5
6
7
The bit 0 in the AD conversion low-order register is used as the
conversion mode selection bit. 8-bit A/D mode is selected by set-
ting this bit to “0” and 10-bit A/D mode is selected by setting it to
“1”.
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
V
REF input switch bit
0 : ON during conversion
1 : Always ON
[AD Control Register (ADCON)] 003416
AD external trigger valid bit
0 : A/D external trigger invalid
1 : A/D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A/D
conversion completed
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
The AD control register controls the A/D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A/D conversion. The value of this bit remains
at “0” during an A/D conversion, then changes to “1” when the
A/D conversion is completed. Writing “0” to this bit starts the A/D
conversion. Bit 4 is the VREF input switch bit which controls con-
nection of the resistor ladder and the reference voltage input pin
(VREF). The resistor ladder is always connected to VREF when bit
4 is set to "1". When bit 4 is set to “0”, the resistor ladder is cut off
from VREF except for A/D conversion performed. When bit 5,
which is the AD external trigger valid bit, is set to “1”, this bit en-
ables A/D conversion even by a falling edge of an ADT input. Set
the P57/ADT pin to input mode (set "0" to bit 7 of port P5 direction
register) when using an A/D external trigger.
b7
b0
AD conversion low-order register
(ADL : address 003616
)
Conversion mode selection bit
0 : 8 bit A/D mode
1 : 10 bit A/D mode
AD conversion speed selection bit
00 : f(XIN)/2
(this can be used in CPUM7 = “0” )
[Comparison Voltage Generator]
01 : f(XIN
)
The comparison voltage generator divides the voltage between
(this can be used in CPUM7 = “0” )
10 : On-chip oscillator
AVSS and VREF, and outputs the divided voltages.
(this can be used in CPUM7 = “0”
and EXPCM0 = “1”)
11 : Disabled
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
Not used (returns “0” when read)
AN0, and inputs it to the comparator.
• In 10-bit A/D mode
A/D conversion data storage
• In 8-bit A/D mode
Not used (Indefinite at read)
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the AD
conversion register. When an A/D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Fig. 33 Structure of AD conversion-related registers
The comparator is constructed linked to a capacitor. The conver-
sion accuracy may be low because the charge is lost if the
conversion speed is not enough. Accordingly, set f(XIN) to at least
500kHz during A/D conversion in the middle-or high-speed mode.
Also, do not execute the STP or WIT instruction during an A/D
conversion.
In the low-speed mode, since the A/D conversion is executed by
the built-in self-oscillation circuit, the minimum value of f(XIN) fre-
quency is not limited.
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3823 Group
• 10 bit reading (Read address 003516 before 003616
)
b7
b0
AD conversion high-order register
(Address 003516) ADH
(High-order)
(low-order)
b9 b8 b7 b6 b5 b4 b3 b2
b0
b7
b1
AD conversion low-order register
(Address 003616) ADL
b0
0
0
0
Conversion mode selection bit
AD conversion speed selection bit
Note: The bit 5 to bit 3 of address 003616 become "0" at reading.
• 8 bit reading (Read only address 003516
)
b7
b0
b7 b6 b5 b4 b3 b2 b1 b0
(Address 003516
)
Fig. 34 A/D conversion register reading
Data bus
b7
b0
AD control register
P5 /ADT
7
3
ADT/A/D interrupt
request
A/D control circuit
P6
0
/SIN2/AN
0
P6 /AN
1
1
AD conversion
AD conversion
P6
P6
P6
P6
P6
P6
2/AN
3/AN
4/AN
5/AN
6/AN
7/AN
2
3
4
5
6
7
Comparator
high-order register
low-order register
(Address 003516
)
(Address 003616
)
Resistor ladder
AVSS
VREF
Fig. 35 A/D converter block diagram
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enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
LCD DRIVE CONTROL CIRCUIT
The 3823 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
●LCD display RAM
●Segment output enable register
●LCD mode register
●Selector
Table 10 Maximum number of display pixels at each duty ratio
●Timing controller
Duty ratio
2
Maximum number of display pixel
64 dots
●Common driver
●Segment driver
or 8 segment LCD 8 digits
96 dots
●Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
3
4
or 8 segment LCD 12 digits
128 dots
Up to 128 pixels can be controlled for LCD display. When the LCD
or 8 segment LCD 16 digits
b7
b0
Segment output enable register
(SEG : address 003816
)
Segment output enable bit 0
0 : Input port P3 –P3
4
7
1 : Segment output SEG12–SEG15
Segment output enable bit 1
0 : I/O port P00,P01
1 : Segment output SEG16, SEG17
Segment output enable bit 2
0 : I/O port P02–P07
1 : Segment output SEG18–SEG23
Segment output enable bit 3
0 : I/O port P10,P11
1 : Segment output SEG24, SEG25
Segment output enable bit 4
0 : I/O port P1
2
1 : Segment output SEG26
Segment output enable bit 5
0 : I/O port P13–P17
1 : Segment output SEG27–SEG31
Not used (returns “0” when read)
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
LCD mode register
(LM : address 003916
)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 (use COM
1 0 : 3 (use COM
1 1 : 4 (use COM
Bias control bit
0 : 1/3 bias
0
0
0
, COM
–COM
–COM
1
2
3
)
)
)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(SUB)/32
1 : f(XIN)/8192 (or f(SUB)/8192 in low-speed
mode)
Note: LCDCK is a clock for a LCD timing controller.
f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation
frequency of XCIN or the on-chip oscillator.
Internal clock φ is f(SUB)/2 in the low-speed mode.
Fig. 36 Structure of segment output enable register and LCD mode register
Rev.2.02 Jun 19, 2007 page 40 of 73
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3823 Group
Fig. 37 Block diagram of LCD controller/driver
Rev.2.02 Jun 19, 2007 page 41 of 73
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3823 Group
Table 11 Bias control and applied voltage to VL1–VL3
Bias Control and Applied Voltage to LCD
Power Input Pins
Bias value
Voltage value
To the LCD power input pins (VL1–VL3), apply the voltage shown
VL3=VLCD
in Table 11 according to the bias value.
1/3 bias
VL2=2/3 VLCD
VL1=1/3 VLCD
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
VL3=VLCD
1/2 bias
VL2=VL1=1/2 VLCD
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Note 1: VLCD is the maximum value of supplied voltage for the
LCD panel.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
Table 12 Duty ratio control and common pins used
Duty ratio selection bit
Duty
Common pins used
ratio
Bit 1
Bit 0
2
3
4
0
1
1
1
0
1
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
Notes1: COM2 and COM3 are open.
2: COM3 is open.
Contrast control
Contrast control
VL3
VL3
R1
R4
VL2
VL2
R2
R3
VL1
VL1
R5
R4 = R5
R1 = R2 = R3
1/3 bias
1/2 bias
Fig. 38 Example of circuit at each bias
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3823 Group
LCD Drive Timing
LCD Display RAM
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the
following equation;
Address 004016 to 004F16 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
(frequency of count source for LCDCK)
f(LCDCK) =
(divider division ratio for LCD)
f(LCDCK)
Frame frequency =
(duty ratio)
Bit
7
6
5
4
3
1
0
2
Address
SEG
SEG
SEG
SEG
SEG
0
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
SEG
SEG
SEG
SEG
SEG
1
2
4
6
8
3
5
7
9
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
COM
0
COM
3
COM
COM
2
COM
1
2
COM
1
COM0
COM
3
Fig. 39 LCD display RAM map
STP Instruction Execution
Execution of the STP instruction sets the LCD enable bit (bit 3 of
the LCD mode register) to “0” and the LCD panel turns off.To
make the LCD panel turn on after returning from the stop mode,
set the LCD enable bit to “1”.
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3823 Group
Internal logic
LCDCK timing
1/4 duty
Voltage level
V
V
V
L3
L2=VL1
SS
COM
COM
COM
COM
0
1
2
3
V
L3
SEG
0
VSS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
V
V
V
L3
L2=VL1
SS
COM
COM
COM
0
1
2
V
L3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
0
COM
2
COM
1
COM
2
COM
1
COM
0
COM2
1/2 duty
V
V
V
L3
L2=VL1
SS
COM
COM
0
1
V
L3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
1
COM
0
COM
1
COM
1
COM
0
COM
1
COM0
Fig. 40 LCD drive waveform (1/2 bias)
Rev.2.02 Jun 19, 2007 page 44 of 73
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3823 Group
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
V
VL2
VSL1S
COM
0
COM
COM
COM
1
2
3
VL3
SEG
0
VSS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
VL3
VL2
VSL1S
V
COM
COM
COM
0
1
2
VL3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
2
COM
1
COM
0
COM2
COM
2
COM
1
COM0
1/2 duty
VL3
VL2
VSL1S
V
COM
COM
0
1
VL3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
1
COM
0
COM
1
COM
0
COM
1
COM0
COM
1
COM0
Fig. 41 LCD drive waveform (1/3 bias)
Rev.2.02 Jun 19, 2007 page 45 of 73
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3823 Group
ROM CORRECTION FUNCTION
A part of program in ROM can be corrected.
ROM correction address 1 high-order register (RCA1H)
ROM correction address 1 low-order register (RCA1L)
001016
001116
001216
Set the start address of the corrected ROM data (i.e. an Op code
address of the beginning instruction) to the ROM correction ad-
dress low-order and high-order registers. The program for the
correction is stored in RAM for ROM correction.
ROM correction address 2 high-order register (RCA2H)
ROM correction address 2 low-order register (RCA2L)
When the program is being executed and the value of the program
counter matches with the set address value in the the ROM cor-
rection address registers,the program is branched to the start
address of RAM for ROM correction and then the correction pro-
gram is executed. Use the JMP instruction (3-byte instruction) to
return the main program from the correction program.
The correctable area is up to two. There are two blocks of RAM for
ROM correction:
001316
Note: Do not set addressed other than the ROM area.
Fig. 42 ROM correction address register
Block 1: Address 0A0016
Block 2: Address 0A2016
0A0016
0A1F16
The ROM correction function is controlled by the ROM correction
enable register.
RAM 1 for ROM correction
RAM 2 for ROM correction
If the ROM correction function is not used, the ROM correction
vector may be used as normal RAM. When using the ROM correc-
tion vector as normal RAM, make sure to set bits 1 and 0 in the
ROM correction enable register to “0” (Disable).
0A2016
0A3F16
Notes 1: When using the ROM correction function, set the ROM
correction address registers and then enable the ROM
correction with the ROM correction enable register.
2: Do not set addresses other than the ROM area in the
ROM correction address registers.
Fig. 43 RAM for ROM correction
Do not set the same addresses in both the ROM correc-
tion address 1 registers and the ROM correction address
2 registers.
3: It is necessary to contain the process in the program to
transfer the correction program from an external
EEPROM and others to the RAM for ROM correction.
b7
b0
ROM correction enable register (Address 001416) (Note)
RCR
Address 1 enable bit (RC0)
0 : Disable
1 : Enable
Address 2 enable bit (RC1)
0 : Disable
1 : Enable
Not used (returns “0” when read)
Note: Set the ROM correction address registers before enabling the ROM correction with the
ROM correction enable register.
Fig. 44 Structure of ROM correction enable register
Rev.2.02 Jun 19, 2007 page 46 of 73
REJ03B0146-0202
3823 Group
φ CLOCK SYSTEM OUTPUT FUNCTION
Set the bit 4 in the peripheral function expansion register to “1”
when the XCIN frequency signal is output.
The internal system clock φ or XCIN frequency signal can be out-
put from port P41 by setting the φ output control register. Set bit 1
of the port P4 direction register to “1” when outputting φ clock.
b7
b0
φ output control register
(CKOUT : address 002A16
)
φ output control bit
0 : port function
1 : φ clock output or XCIN frequency signal output
Not used (return “0” when read)
Fig. 45 Structure of φ output control register
Temporary data register
RRF register
The temporary data register (addresses 002C16 to 002E16) is the
8-bit register and does not have the control function. It can be
used to store data temporarily. It is initialized after reset.
The RRF register (address 002F16)is the 8-bit register and does
not have the control function. As for the value written in this regis-
ter, high-order 4 bits and low-order 4 bits interchange. It is
initialized after reset.
b7
b0
Temporary data register 0,1,2
(Address: 002C16, 002D16, 002E16
)
TD ,TD ,TD
0
1
2
DB
DB
DB
DB
DB
DB
DB
DB
0
1
2
3
4
5
6
7
data storage
data storage
data storage
data storage
data storage
data storage
data storage
data storage
b7
b0
RRF register (Address: 002F16
)
RRFR
DB
DB
DB
DB
DB
DB
DB
DB
4
5
6
7
0
1
2
3
data storage
data storage
data storage
data storage
data storage
data storage
data storage
data storage
Fig. 46 Structure of temporary register, RPF register
Rev.2.02 Jun 19, 2007 page 47 of 73
REJ03B0146-0202
3823 Group
WATCHDOG TIMER
executed, the watchdog timer does not operate.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit counter.
When reading the watchdog timer control register is executed, the
contents of the high-order 6-bit counter and the STP instruction bit
(bit 6), and the count source selection bit (bit 7) are read out.
Bit 6 of Watchdog Timer Control Register
• When bit 6 of the watchdog timer control register is “0”, the MCU
enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer restarts
counting (Note). When executing the WIT instruction, the watch-
dog timer does not stop.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register, each
watchdog timer is set to “FF16.” Instructions such as STA, LDM
and CLB to generate the write signals can be used.
The written data in bits 0 to 5 are not valid, and the above values
are set.
• When bit 6 is “1”, execution of STP instruction causes an internal
reset. When this bit is set to “1” once, it cannot be rewritten to
“0” by program. Bit 6 is “0” at reset.
Bits 7 and 6 can be rewritten only once after reset.
After rewriting it is disable to write any data to this bit. These bits
become “0” after reset.
The time until the underflow of the watchdog timer register after
writing to the watchdog timer control register is executed is as fol-
lows (when the bit 7 of the watchdog timer control register is “0”) ;
Standard Operation of Watchdog Timer
The watchdog timer is in the stop state at reset and the watchdog
timer starts to count down by writing an optional value in the
watchdog timer control register. An internal reset occurs at an un-
derflow of the watchdog timer. Then, reset is released after the
reset release time is elapsed, the program starts from the reset
vector address. Normally, writing to the watchdog timer control
register before an underflow of the watchdog timer is pro-
grammed. If writing to the watchdog timer control register is not
• at frequency/2/4/8 mode (f(XIN)) = 8 MHz): 32.768 ms
• at low-speed mode (f(XCIN) = 32 KHz): 8.19s
● Note
The watchdog timer continues to count even during the wait time set
by timer 1 and timer 2 to release the stop state and in the wait
mode. Accordingly, do not underflow the watchdog timer in this time.
On-chip oscillator mode
On-chip oscillator
Data bus
control bit
Watchdog timer count
source selection bit
X
CIN
“0”
“1”
“0”
Internal system clock
selection bit (bit 7 of
the CPU mode register)
1/1024
1/4
Watchdog timer L (2)
Watchdog timer H (6)
“1”
“FF16” is set when
X
IN
watchdog timer control
register is written to.
Undefined instruction
Reset
STP instruction bit
Reset
circuit
STP instruction
Internal reset
RESET
Wait until reset release
Fig. 47 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register (Address 003716
WDTCON
)
Watchdog timer H (for read-out of high-order 6 bit)
“FF16” is set to watchdog timer by writing to these bits.
STP instruction function selection bit
0: Entering stop mode by execution of STP instruction
1: Internal reset by execution of STP instruction
Watchdog timer count source selection bit
0: f(XIN)/1024 (f(SUB)/1024 at low-speed mode)
1: f(XIN)/4 (f(SUB)/1024 at low-speed mode)
Note : Bits 6 and 7 can be rewritten only once after reset.
After rewriting it is disable to write any data to this bit.
Fig. 48 Structure of Watchdog timer control register
f(XIN)
=32msec (f(XIN)=8MHZ)
Internal reset
signal
Watchdog timer
detection
Fig. 49 Timing of reset output
Rev.2.02 Jun 19, 2007 page 48 of 73
REJ03B0146-0202
3823 Group
PERIPHERAL FUNCTION EXTENSION REGISTER
The serial I/O transfer direction can be switched by setting the bit
0 in the peripheral function expansion register to “1”. This function
is valid only when the bit 6 in the serial I/O control register is set to
“1” (when the clock synchronous serial I/O is selected). P47 can
be selected as the output pin of the clock synchronous serial I/O
by setting the bit 1 in the peripheral function expansion register to
“1”. When setting P47 to the SOUT pin, set the bit 7 in the port P4
direction register to “1”. This function is valid only when the bit 6 in
the serial I/O control register to “1” (when the clock synchronous
serial I/O is selected). P-channel output of TXD and SOUT can be
disabled by the bits 2 and 3 in the peripheral function expansion
register. Set the bit 4 in the UART control register to “1” after se-
lecting the pin to disable the P-channel output. XCIN frequency
signal can be output from the port P41 by setting the bit 4 in the
peripheral function expansion register to “1”. Set the bit 0 in the φ
output control register and the bit 1 in the port P4 direction regis-
ter to “1” to output the XCIN frequency signal.
b7
b0
Peripheral function extension register (Address: 003016
)
EXP
Transfer direction selection bit (valid when UART is used)
0 : LSB first
1 : MSB first
Synchronous serial I/O output pin selection bit
0:P45/T
XD pin
1:P47/SRDY/SOUT pin
P-channel output disabled selection bit
00: P4 /T D pin
01: The bit 4 in the UART control register is invalid
5
X
10: P45/T
XD pin or P47/SRDY/SOUT pin
11: P47/SRDY/SOUT pin
Output clock selection bit
0: φ clock output
1: XCIN frequency signal output
Not used (returns “0” when read)
(Do not write “1” to this bit)
Fig. 50 Structure of peripheral function extension register
Rev.2.02 Jun 19, 2007 page 49 of 73
REJ03B0146-0202
3823 Group
RESET CIRCUIT
Power on
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD16 (high-order byte) and ad-
dress FFFC16 (low-order byte). Make sure that the reset input
voltage meets VIL spec. when a power source voltage passes
VCC(min.).
Power
source
voltage
RESET
VCC
0V
Reset input
voltage
V
IL spec.
0V
RESET
VCC
Power source voltage
detection circuit
Fig. 51 Reset Circuit Example
XIN
φ
RESET
Internal
reset
Reset address from
vector table
Address
?
?
?
?
FFFC
FFFD
ADH, ADL
Data
ADL
ADH
SYNC
XIN : about 8000 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) =8•f(φ)
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 52 Reset Sequence
Rev.2.02 Jun 19, 2007 page 50 of 73
REJ03B0146-0202
3823 Group
Register Contents
0016
Address
000116
(1)
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
ROM correctoin enable register (RCR)
PULL register A
000316
000516
000916
000B16
000D16
000F16
001416
001616
001716
001916
001A16
001B16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003416
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
0016
0016
0016
0016
0016
0016
0016
(2)
(3)
(4)
(5)
(6)
(7)
(8)
0
1
1
0
0
1
0
0
1
0
0
0
1
0016
0
0
0
0
1
0
0
1
0
0
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
PULL register B
Sirial I/O status register
Sirial I/O control register
UART control register
0016
0
FF16
FF16
FF16
FF16
FF16
0116
FF16
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
1
Timer X high-order register
Timer X low-order register
Timer Y high-order register
Timer Y low-order register
Timer 1 register
Timer 2 register
Timer 3 register
Timer X mode register
Timer Y mode register
Timer 123 mode register
φ output control register
CPU mode extension register
Temporary data register 0
Temporary data register 1
Temporary data register 2
RRF register
Peripheral function extension register
AD control register
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
●
0
●
0
AD conversion low-order register
Watchdog timer control register
Segment output enable register
LCD mode register
1
0016
0016
0016
1
Interrupt edge selection register
CPU mode register
0
1
0
0
0
0
0
0016
0016
0016
0016
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Processor status register
Program counter
1
●
●
●
●
●
●
●
(PCH)
Contents of address FFFD16
Contents of address FFFC16
(PCL)
Note: The contents of all other registers and RAM are undefined after reset, so they must be
initialized by software.
●: undefined
Fig. 53 Initial status of microcomputer after reset
Rev.2.02 Jun 19, 2007 page 51 of 73
REJ03B0146-0202
3823 Group
CLOCK GENERATING CIRCUIT
Frequency Control
The 3823 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. The os-
cillation start voltage and the oscillation start time differ in
accordance with an oscillator, a circuit constant, or temperature,
etc.
(1) frequency/8 Mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2) frequency/4 Mode
The internal clock φ is the frequency of XIN divided by 4.
When power supply voltage is low and the high frequency oscilla-
tor is used, an oscillation start will require sufficient conditions. No
external resistor is needed between XIN and XOUT since a feed-
back resistor exists on-chip. (an external feed-back resistor may
be needed depending on conditions.) However, an external feed-
back resistor is needed between XCIN and XCOUT since a resistor
does not exist between them.
(3) frequency/2 Mode
The internal clock φ is half the frequency of XIN.
(4) Low-speed Mode
●The internal clock φ is the frequency of XIN or on-chip oscillation
frequency divided by 2.
●A low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accord-
ingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
When the main clock XIN is restarted, set enough time for oscil-
lation to stabilize by programming.
In low speed mode, the system clock φ can be switched to the
on-chip oscillator or XCIN. Use the on-chip oscillator control bit
(bit 0 in the CPU mode expansion register) for settings. To set
this bit to “0” from “1”, wait until XCIN oscillation stabilizes.
Note 1: If you switch the mode between frequency/2/4/8 mode
and low-speed, stabilize both XIN and XCIN oscillations.
The sufficient time is required for the sub-clock to stabi-
lize, especially immediately after poweron and at
returning from stop mode. When switching the mode be-
tween middle/high-speed and low-speed, set the
X
CIN
X
COUT
X
IN
X
OUT
Rd
Rf
Rd
frequency on condition that f(XIN) > 3f(XCIN).
2: In frequency/2/4/8 mode, XIN-XOUT oscillation does not
stop even if the main clock (XIN-XOUT) stop bit is set to
"1".
3: In low speed mode, XCIN-XCOUT oscillation does not stop
even if the port XC switch bit is set to "0".
C
CIN
C
COUT
CIN
C
OUT
Note : Insert a damping resistor if required. The resistance will vary
depending on the oscillator and the oscillation drive capacity
setting. Use the value recommended by the maker of the
oscillator. Also, if the oscillator manufacturer's data sheet
specifies that a feedback resistor be added external to the chip
though a feedback resistor exists on-chip, insert a feedback
resistor between XIN and XOUT following the instruction.
Fig. 54 Ceramic resonator circuit example
XCOUT
XCIN
XIN
XOUT
Rf
Open
Rd
External oscillation circuit
C
CIN
CCOUT
VCC
VSS
Fig. 55 External clock input circuit
Rev.2.02 Jun 19, 2007 page 52 of 73
REJ03B0146-0202
3823 Group
Oscillation Control
(2) Wait Mode
(1) Stop Mode
If the WIT instruction is executed, only the system clock φ stops at
an "H" state. The states of main clock, on-chip oscillator and sub
clock are the same as the state before executing the WIT instruc-
tion, and oscillation does not stop. Since supply of system clock φ
is started immediately after the interrupt is received, the instruc-
tion can be executed immediately.
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to
“FF16” and timer 2 is set to “0116”.
Either XIN or XCIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2. The bits
of the timer 123 mode register except bit 4 are cleared to “0”. Set
the timer 1 and timer 2 interrupt enable bits to disabled (“0”) be-
fore executing the STP instruction. Oscillator restarts at reset or
when an external interrupt is received, but the internal clock φ is
not supplied to the CPU until timer 2 underflows. This allows timer
for the clock circuit oscillation to stabilize.
Execution of the STP instruction sets the LCD enable bit (bit 3 of
the LCD mode register) to “0” and the LCD panel turns off.To
make the LCD panel turn on after returning from the stop mode,
set the LCD enable bit to “1”.
XCOUT
XCIN
“0”
Port XC
switch bit
“1”
On-chip oscillator
On-chip
oscillator
control bit
f(SUB)
Timer 1
Timer 2
XIN
XOUT
count source
Internal system clock selection bit
count source
(Note 2)
selection bit
(Note 1)
selection bit
“1”
Low-speed mode
“0”
“1”
Timer 1
Timer 2
1/4
1/2
1/2
“0”
“0”
“1”
Frequency/2/4/8
mode
1/2
Main clock division
ratio selection bit
Frequency/4
mode
Frequency/8 mode
“1”
control bit
Timing φ
(Internal system clock)
“0”
Main clock stop bit
Frequency/2/4
mode or low-
speed mode
S
R
Q
Q
S
S
R
Q
WIT
instruction
R
STP instruction
STP instruction
Reset
Interrupt disable flag 1
Interrupt request
Notes 1: When using the low-speed mode, set the port XC switch bit to “1” .
2: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending
on conditions.
Fig. 56 Clock generating circuit block diagram
Rev.2.02 Jun 19, 2007 page 53 of 73
REJ03B0146-0202
3823 Group
Rese
t
b7
b4
CPU mode extension register
(EXPCM : address: 002B16,)
CM
6
φ) = 4 MHz)
or frequency/4 mode (f(φ) = 2 MHz)
φ) = 1 MHz)
“1”
“0”
CM7
CM6
CM5
CM4
= 0 (8 MHz selected)
= 1 (Frequency/8)
= 0 (8 MHz oscillating)
= 0 (Stopped)
CM7
CM6
CM5
CM4
= 0 (8 MHz selected)
= 0 (Frequency/2/4)
= 0 (8 MHz oscillating)
= 0 (Stopped)
On-chip oscillator control bit
0 : On-chip oscillator not used
(on-chip oscillator stopping)
1 : On-chip oscillator used (Note 1)
(on-chip oscillator oscillating)
Frequency/4 mode control bit (Note 2)
(Valid only when high-speed mode)
0 : Frequency/2 mode φ = f(XIN)/2
1 : Frequency/4 mode φ = f(XIN)/4
Not used (returns “0” when read)
(Do not write “1” to this bit)
CM
6
φ) = 4 MHz)
or frequency/4 mode (f(φ) = 2 MHz)
φ) = 1 MHz)
Note 1 : The on-chip oscillator is selected for the operation clock
in low-speed mode regardless of XCIN-
“1”
“0”
CM7
CM6
CM5
CM4
= 0 (8 MHz selected)
= 1 (frequency/8)
CM7
CM6
CM5
CM4
= 0 (8 MHz selected)
= 0 (Frequency/2/4)
= 0 (8 MHz oscillating)
= 1 (Oscillating)
XCOUT.
= 0 (8 MHz oscillating)
= 1 (Oscillating)
2 : Valid only when the main clock division ratio selection bit
(bit 6 in the CPU mode register) is set to "0".
or EXPCM0 = 1
or EXPCM0 = 1
(On-chip oscillator oscillation)
When "1" (frequency/8 mode) is selected for the main clock
division ratio selection bit or when the internal system clock
selection bit is set to 1, set "0" to the frequency/4 mode control bit.
(On-chip oscillator oscillation)
b7
b4
CPU mode register
(CPUM : address 003B16
)
Low-speed mode (f(SUB)/2)
CM = 1 (32 kHz or on-chip
CM
6
Low-speed mode (f(SUB)/2)
CM = 1 (32 kHz or on-chip
CM
CM
CM
4
: Port Xc switch bit (Note 1)
7
7
0: I/O port (Oscillation stopped)
1: XCIN, XCOUT oscillating function
“1”
“0”
oscillator selected)
oscillator selected)
CM6
CM5
CM4
= 0 (High-speed)
= 0 (8 MHz oscillating)
= 1 (Oscillating)
CM6
CM5
CM4
= 1 (Middle-speed)
= 0 (8 MHz oscillating)
= 1 (Oscillating)
5
: Main clock (XIN–XOUT) stop bit (Note 2)
0: Oscillating
1: Stopped
6
: Main clock division ratio selection bit
0: f(XIN)/2 (frequency/2 mode),
or f(XIN)/4 (frequency/4 mode) (Note 3)
1: f(XIN)/8 (frequency/8 mode)
CM
7
: Internal system clock selection bit
0: XIN–XOUT selected (frequency/2/4/8 mode)
1: XCIN–XCOUT, or on-chip oscillator selected
(low-speed mode) (Note 4)
Low-power dissipation mode
(f(SUB)/2)
Low-power dissipation mode
(f(SUB)/2)
CM
6
Note 1 : In low speed mode (XCIN is selected as the system clock φ),
CIN-XCOUT oscillation does not stop even if the port X switch bit
is set to "0".
“1”
“0”
CM
7
= 1 (32 kHz or on-chip
CM
7 = 1 (32 kHz or on-chip
X
C
oscillator selected)
oscillator selected)
CM6
CM5
CM4
= 1 (Middle-speed)
= 1 (8 MHz stopped)
= 1 (Oscillating)
CM6
CM5
CM4
= 0 (high-speed)
= 1 (8 MHz stopped)
= 1 (Oscillating)
2 : In frequency/2/4/8 mode, XIN-XOUT oscillation does not stop even if
the main clock (XIN-XOUT) stop bit is set to "1".
3 : When the system clock φ is divided by 4 of f(XIN), set the bit 6 in
the CPU mode register to “0” after setting the bit 1 in the CPU
mode extension register to “1”.
4 : When using the on-chip oscillator in low-speed mode, set the bit 7
in the CPU mode register to “1” after setting the bit 0 in the CPU
mode extension register to “1”.
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended.
3 : Timer and LCD operate in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in frequency/2/4/8 mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to frequency/2/4/8 mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
8 : f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of XCIN or the on-chip oscillator.
Internal clock φ is f(SUB)/2 in the low-speed mode.
9 : Set the CPU mode expansion register in advance when switching to low-speed mode which uses mode divided by 4 and on-chip oscillator.
10: In low speed mode, the system clock φ can be switched to the on-chip oscillator or XCIN. Use the on-chip oscillator control bit (bit 0 in the CPU mode
expansion register) for settings. To set this bit to "0" from "1", wait until XCIN oscillation stabilizes.
Fig. 57 State transitions of system clock
Rev.2.02 Jun 19, 2007 page 54 of 73
REJ03B0146-0202
3823 Group
QzROM Writing Mode
In the QzROM writing mode, the user ROM area can be rewritten
while the microcomputer is mounted on-board by using a serial
programmer which is applicable for this microcomputer.
Table 13 lists the pin description (QzROM writing mode) and Fig-
ure 58 and Figure 59 show the pin connections.
Refer to Figure 60 and Figure 61 for examples of a connection
with a serial programmer.
Contact the manufacturer of your serial programmer for serial pro-
grammer. Refer to the user’s manual of your serial programmer
for details on how to use it.
Table 13 Pin description (QzROM writing mode)
Pin
Name
Power source
I/O
Function
• Apply 1.8 to 5.5 V to VCC, and 0 V to VSS.
VCC, VSS
RESET
Input
Input
Reset input
• Reset input pin for active “L”. Reset occurs when RESET pin is hold at an “L” level
for 16 cycles or more of XIN.
XIN
Clock input
Input
• Set the same termination as the single-chip mode.
XOUT
Clock output
Output
VREF
Analog reference voltage Input
• Input the reference voltage of A/D converter to VREF.
• Connect AVss to Vss.
AVSS
Analog power source
I/O port
Input
I/O
P00 –P07
P10 –P17
P20 –P27
P34 –P37
P41–P44
P50 –P57
P60 –P67
P40
• Input “H” or “L” level signal or leave the pin open.
VPP input
Input
I/O
• QzROM programmable power source pin.
• Serial data I/O pin.
P44
ESDA input/output
ESCLK input
ESPGMB input
P42
Input
Input
• Serial clock input pin.
P43
• Read/program pulse input pin.
Rev.2.02 Jun 19, 2007 page 55 of 73
REJ03B0146-0202
3823 Group
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VCC
VREF
AVSS
COM3
COM2
COM1
COM0
65
66
67
68
69
70
71
72
73
74
75
76
40
P20/KW0
P21/KW1
P22/KW2
P23/KW3
P24/KW4
P25/KW5
P26/KW6
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
M3823XGX-XXXFP
M3823XGXFP
P27/KW7
VSS
XOU
V
CC
GND
VPP
*
GND
XIN
T
P70/XCOUT
P71/XCIN
77
78
RESET
RESET
P40
P41/φ
79
80
VL3
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
*: Connect to oscillation circuit.
: QzROM pin
ESDA
ESCLK
ESPGMB
PRQP0080GB-A (80P6N-A)
Fig. 58 Pin connection diagram (M3823XGX-XXXFP)
40
39
38
37
36
35
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
9
8
7
6
5
4
3
2
1
0
61
62
63
64
65
66
67
68
P1
P1
P2
P2
P2
P2
P2
P2
P2
6
7
0
/SEG30
/SEG31
/KW
0
1
2
3
4
5
6
/KW
/KW
/KW
/KW
/KW
/KW
1
2
3
4
5
6
34
33
32
31
30
29
28
27
26
25
24
23
69
70
P2
7
/KW
7
M3823XGX-XXXHP
M3823XGXHP
GND
V
CC
GND
V
CC
REF
AVSS
V
X
X
SS
OUT
IN
71
72
*
V
73
74
75
76
77
78
79
COM
COM
COM
COM
3
2
1
0
P70
/XCOUT
/XCIN
P7
1
RESET
RESET
V
PP
P4
P4
P4
P4
0
VL3
VL2
VL1
1
/φ
/INT
/INT
22
21
ESCLK
2
0
1
ESPGMB
80
3
*: Connect to oscillation circuit.
: QzROM pin
ESDA
PLQP0080KB-A (80P6Q-A)
Fig. 59 Pin connection diagram (M3823XGX-XXXHP)
Rev.2.02 Jun 19, 2007 page 56 of 73
REJ03B0146-0202
3823 Group
3823 Group
Vcc
Vcc
P40
4.7 kΩ
4.7 kΩ
P4
4
2
(ESDA)
P4
(ESCLK)
P43
(ESPGMB)
*1
RESET
circuit
13
14
12
10
8
11
9
RESET
Vss
7
6
5
4
3
AVss
X
2
1
IN
XOUT
Set the same termination as
the single-chip mode.
*
1
: Open-collector buffer
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig. 60 When using E8 programmer, connection example
Rev.2.02 Jun 19, 2007 page 57 of 73
REJ03B0146-0202
3823 Group
3823 Group
Vcc
T_VDD
T_VPP
P40
4.7 kΩ
4.7 kΩ
T_TXD
T_RXD
P4
4
2
(ESDA)
P4
(ESCLK)
T_SCLK
T_BUSY
N.C.
P43
(ESPGMB)
T_PGM/OE/MD
RESET circuit
RESET
T_RESET
GND
Vss
AVss
X
IN
XOUT
Set the same termination as the
single-chip mode.
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig. 61 When using programmer of Sisei Electronics System Co., LTD, connection example
Rev.2.02 Jun 19, 2007 page 58 of 73
REJ03B0146-0202
3823 Group
NOTES ON PROGRAMMING
Processor Status Register
A/D Converter
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
The comparator is constructed linked to a capacitor. The conver-
sion accuracy may be low because the charge is lost if the
conversion speed is not enough. Accordingly, set f(XIN) to at least
500kHz during A/D conversion in the middle-or high-speed mode.
Also, do not execute the STP or WIT instruction during an A/D
conversion.
the decimal mode (D) flags because of their effect on calculations.
Initialize these flags at the beginning of the program.
In the low-speed mode, since the A/D conversion is executed by
the on-chip oscillator, the minimum value of f(XIN) frequency is not
limited.
Interrupt
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
LCD Drive Control Circuit
Execution of the STP instruction sets the LCD enable bit (bit 3 of
the LCD mode register) to “0” and the LCD panel turns off.To
make the LCD panel turn on after returning from the stop mode,
set the LCD enable bit to “1”.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Timers
The frequency of the internal clock φ is half of the XIN frequency.
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial Interface
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
Rev.2.02 Jun 19, 2007 page 59 of 73
REJ03B0146-0202
3823 Group
Countermeasures against noise
Noise
(1) Shortest wiring length
● Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20mm).
X
X
IN
X
X
IN
OUT
OUT
V
SS
V
SS
● Reason
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is com-
pletely initialized. This may cause a program runaway.
O.K.
N.G.
Fig. 63 Wiring for clock I/O pins
(2) Connection of bypass capacitor across VSS line and VCC line
In order to stabilize the system operation and avoid the latch-up,
connect an approximately 0.1 µF bypass capacitor across the VSS
line and the VCC line as follows:
Noise
Reset
• Connect a bypass capacitor across the VSS pin and the VCC pin
at equal length.
RESET
circuit
V
SS
VSS
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
N.G.
• Use lines with a larger diameter than other signal lines for VSS
line and VCC line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
Reset
circuit
RESET
VSS
VSS
V
CC
V
CC
O.K.
Fig. 62 Wiring for the RESET pin
● Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins
as short as possible.
V
SS
V
SS
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS
patterns.
N.G.
O.K.
Fig. 64 Bypass capacitor across the VSS line and the VCC line
● Reason
If noise enters clock I/O pins, clock waveforms may be de-
formed. This may cause a program failure or program runaway.
Also, if a potential difference is caused by the noise between
the VSS level of a microcomputer and the VSS level of an oscil-
lator, the correct clock will not be input in the microcomputer.
Rev.2.02 Jun 19, 2007 page 60 of 73
REJ03B0146-0202
3823 Group
(4) Analog input
(3) Oscillator concerns
The analog input pin is connected to the capacitor of a voltage
In order to obtain the stabilized operation clock on the user system
and its condition, contact the oscillator manufacturer and select
the oscillator and oscillation circuit constants. Be careful espe-
cially when range of votage and temperature is wide.
Also, take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
comparator. Accordingly, sufficient accuracy may not be obtained
by the charge/discharge current at the time of A/D conversion
when the analog signal source of high-impedance is connected to
an analog input pin. In order to obtain the A/D conversion result
stabilized more, please lower the impedance of an analog signal
source, or add the smoothing capacitor to an analog input pin.
● Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the toler-
ance of current value flows.
(5) Difference of memory size
When memory size differ in one group, actual values such as an
electrical characteristics, A/D conversion accuracy, and the amount
of -proof of noise incorrect operation may differ from the ideal values.
When these products are used switching, perform system evalua-
tion for each product of every after confirming product specification.
● Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise oc-
curs because of mutual inductance.
(6) Wiring to P40/(VPP) pin
When using P40/(VPP) pin as an input port, connect an approximately
5 kΩ resistor to the P40/(VPP) pin the shortest possible in series.
When not using P40/(VPP) pin, connect the pin the shortest pos-
sible to the GND pattern which is supplied to the Vss pin of the
microcomputer. In addition connecting an approximately 5 kΩ re-
sistor in series to the GND could improve noise immunity. In this
case as well as the above mention, connect the pin the shortest
possible to the GND pattern which is supplied to the Vss pin of the
microcomputer.
● Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change frequently.
Also, do not cross such signal lines over the clock lines or the
signal lines which are sensitive to noise.
● Reason
● Reason
Signal lines where potential levels change frequently (such as
the CNTR pin signal line) may affect other lines at signal rising
edge or falling edge. If such lines cross over a clock line, clock
waveforms may be deformed, which causes a microcomputer
failure or a program runaway.
The P40/(VPP) pin of the QzROM version is the power source input pin
for the built-in QzROM. When programming in the QzROM, the im-
pedance of the VPP pin is low to allow the electric current for writing to
flow into the built-in QzROM. Because of this, noise can enter easily. If
noise enters the P40/(VPP) pin, abnormal instruction codes or data are
read from the QzROM, which may cause a program runaway.
● Keeping oscillator away from large current signal lines
(1) When using P40/(VPP) pin as an input port
The shortest
Microcomputer
Mutual inductance
M
Approx. 5kΩ
P40/(VPP)
(Note)
(Note)
X
X
IN
Large
current
OUT
V
SS
V
SS
GND
● Installing oscillator away from signal lines where potential
(2) When not using P40/(VPP) pin
levels change frequently
The shortest
P40/(VPP)
CNTR
(Note)
(Note)
Do not cross
XIN
Approx. 5kΩ
X
OUT
V
SS
V
SS
The shortest
N.G.
Note. Shows the microcomputer's pin.
Fig. 65 Wiring for a large current signal line/Wiring of signal
lines where potential levels change frequently
Fig. 66 Wiring for the P40/(VPP) pin
Rev.2.02 Jun 19, 2007 page 61 of 73
REJ03B0146-0202
3823 Group
NOTES ON USE
NOTES ON QzROM
Power Source Voltage
Notes On QzROM Writing Orders
When ordering the QzROM product shipped after writing, submit
the mask file (extension: .msk) which is made by the mask file
converter MM.
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
Be sure to set the ROM option ("MASK option" written in the mask
file converter) setup when making the mask file by using the mask
file converter MM.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less than
the recommended operating conditions and design a system not
to cause errors to the system by this unstable operation.
Notes On ROM Code Protect
(QzROM product shipped after writing)
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the ROM option setup data in the
mask file which is submitted at ordering.
The ROM option setup data in the mask file is “0016” for protect
enabled or “FF16” for protect disabled. Therefore, the contents of
the ROM code protect address (other than the user ROM area) of
the QzROM product shipped after writing is “0016” or “FF16”.
Note that the mask file which has nothing at the ROM option data
or has the data other than “0016” and “FF16” can not be accepted.
LCD drive power supply
Power supply capacitor may be insufficient with the division resis-
tance for LCD power supply,and the characteristic of the LCD panel.In
this case,there is the method of connecting the bypass capacitor
about 0.1 –0.33µF to VL1 –VL3 pins.The example of a strengthening
measure of the LCD drive power supply is shown in Figure 67.
• Connect by the shortest
possible wiring.
• Connect the bypass capacitor
to the VL1 –VL3 pins as short
as possible.
V
V
L3
L2
DATA REQUIRED FOR QzROM WRITING
ORDERS
The following are necessary when ordering a QzROM product
shipped after writing:
(Referential value:0.1–0.33µ F)
V
L1
1. QzROM Writing Confirmation Form*
3823 Group
2. Mark Specification Form*
3. ROM data...........Mask file
Fig. 67 Strengthening measure example of LCD drive power supply
* For the QzROM writing confirmation form and the mark specifi-
cation form, refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com).
Product shipped in blank
As for the product shipped in blank, Renesas does not perform the
writing test to user ROM area after the assembly process though
the QzROM writing test is performed enough before the assembly
process. Therefore, a writing error of approx.0.1 % may occur.
Moreover, please note the contact of cables and foreign bodies on a
socket, etc. because a writing environment may cause some writing errors.
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
Overvoltage
Make sure that voltage exceeding the Vcc pin voltage is not ap-
plied to other pins. In particular, ensure that the state indicated by
bold lines in figure below does not occur for pin P40 (VPP power
source pin for QzROM) during power-on or power-off. Otherwise
the contents of QzROM could be rewritten.
1.8V
1.8V
VCC pin voltage
P4
“H” input
P4 pin voltage
“L” input
0 pin voltage
0
(1) Input voltage to other MCU pins rises before Vcc pin voltage.
(2) Input voltage to other MCU pins falls after Vcc pin voltage.
Note: The internal circuitry is unstable when Vcc is below the minimum voltage specification of 1.
8 V (shaded portion), so particular care should be exercised regarding overvoltage.
Fig. 68 Timing Diagram (Applies to section indicated by bold line.)
Rev.2.02 Jun 19, 2007 page 62 of 73
REJ03B0146-0202
3823 Group
ELECTRICAL CHARACTERISTICS
Table 14 Absolute maximum ratings
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 6.5
All voltages are based on VSS.
When an input voltage is mea-
sured, output transistors are cut
off.
VI
Input voltage P00–P07, P10–P17, P20–P27,
P34–P37, P40–P47, P50–P57
P60–P67, P70, P71
–0.3 to VCC +0.3
V
V
V
V
V
V
V
V
–0.3 to VL2
VL1 to VL3
Input voltage VL1
VI
VI
VI
VI
VO
Input voltage VL2
VL2 to 6.5
Input voltage VL3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL3
Input voltage RESET, XIN
Output voltage P00–P07, P10–P17
At output port
At segment output
At segment output
VO
VO
–0.3 to VL3
Output voltage P34–P37
Output voltage P20–P27, P41–P47,P50–P57,
P60–P67, P70, P71
–0.3 to VCC +0.3
V
VO
Output voltage SEG0–SEG11
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
–0.3 to VL3
–0.3 to VCC +0.3
300
V
V
VO
Pd
mW
°C
°C
Ta = 25°C
Topr
Tstg
–20 to 85
–40 to 150
Table 15 Recommended operating conditions (1)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
4.5
4.0
2.0
1.8
2.5
2.0
1.8
2.5
2.0
1.8
1.8
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Max.
Frequency/2 mode f(XIN) = 10 MHz
f(XIN) = 8 MHz
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VCC
Power source voltage
(Note 1)
f(XIN) = 5 MHz
f(XIN) = 2.5 MHz
Frequency/4 mode f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 5 MHz
Frequency/8 mode f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 5 MHz
Low-speed mode (OCO included)
VSS
VL 3
VREF
AVSS
VIA
Power source voltage
5.5
LCD power voltage
2.5
1.8
VCC
A/D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
0
VREF
AVSS
Note : When the A/D converter is used, refer to the recommended operating condition for A/D converter.
Rev.2.02 Jun 19, 2007 page 63 of 73
REJ03B0146-0202
3823 Group
Table 16 Recommended operating conditions (2)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
V
Min.
Max.
VCC
“H” input voltage
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52,
P53,P56,P60–P67,P70,P71 (CM4= 0)
VIH
0.7VCC
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIH
VIH
VIH
VIL
0.8VCC
0.8VCC
0.8VCC
0
VCC
VCC
V
V
V
V
RESET
XIN
VCC
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4= 0)
0.3 VCC
“L” input voltage
“L” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIL
VIL
VIL
0
0
0
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
RESET
XIN
Rev.2.02 Jun 19, 2007 page 64 of 73
REJ03B0146-0202
3823 Group
Table 17 Recommended operating conditions (3)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
–40
–40
40
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17 (Note 2)
40
–20
–20
20
20
–2
“H” peak output current
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
–5
(Note 2)
IOL(peak)
IOL(peak)
“L” peak output current
“L” peak output current
mA
mA
P00–P07, P10–P17 (Note 2)
5
10
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
–1.0
–2.5
mA
mA
IOH(avg)
IOH(avg)
“H” average output current
“H” average output current
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
mA
mA
“L” average output current
“L” average output current
2.5
5.0
IOL(avg)
IOL(avg)
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
f(CNTR0)
f(CNTR1)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC ≤ 4.5 V)
(2.0 V ≤ VCC ≤ 4.0 V)
(VCC ≤ 2.0 V)
5.0
MHz
Input frequency for timers X and Y
(duty cycle 50%)
2 ● VCC – 4 MHz
0.75 ● VCC + 1 MHz
6.25 ● VCC - 10 MHz
Frequency/2 mode
(4.5 V ≤ VCC ≤ 5.5 V)
f(XIN)
Main clock input oscillation frequency
(duty cycle 50%)
10.0
MHz
(Note 4)
Frequency/2 mode
(4.0 V ≤ VCC ≤ 4.5 V)
4 ● VCC – 8 MHz
Frequency/2 mode
(2.0 V ≤ VCC ≤ 4.0 V)
1.5 ● VCC + 2 MHz
12.5 ● VCC - 20 MHz
Frequency/2 mode
(1.8 V ≤ VCC ≤ 2.0 V)
Frequency/4 mode
(2.5 V ≤ VCC ≤ 5.5 V)
10.0
MHz
MHz
Frequency/4 mode
(2.0 V ≤ VCC ≤ 2.5 V)
4 ● VCC
Frequency/4 mode
(1.8 V ≤ VCC ≤ 2.0 V)
15 ● VCC – 22 MHz
Frequency/8 mode
(2.5 V ≤ VCC ≤ 5.5 V)
10.0
MHz
MHz
Frequency/8 mode
(2.0 V ≤ VCC ≤ 2.5 V)
4 ● VCC
Frequency/8 mode
(1.8 V ≤ VCC ≤ 2.0 V)
15 ● VCC – 22 MHz
80
kHz
f(XCIN)
Sub-clock input oscillation frequency
(duty cycle 50%)
32.768
(Note 5)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value
measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the A/D converter is used, refer to the recommended operating condition for A/D converter.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
Rev.2.02 Jun 19, 2007 page 65 of 73
REJ03B0146-0202
3823 Group
Table 18 Electrical characteristics (1)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –2.5 mA
Unit
Min.
Max.
VCC–2.0
V
V
“H” output voltage
P00–P07, P10–P17
VOH
IOH = –0.6 mA
VCC = 2.5 V
VCC–1.0
IOH = –5 mA
VCC–2.0
VCC–0.5
V
V
“H” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
IOH = –1.25 mA
VOH
VOL
IOH = –1.25 mA
VCC = 2.5 V
VCC–1.0
V
IOL = 5 mA
2.0
0.5
V
V
“L” output voltage
P00–P07, P10–P7
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
1.0
V
2.0
0.5
V
V
IOL = 10 mA
IOL = 2.5 mA
“L” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VOL
IOL = 2.5 mA
VCC = 2.5 V
1.0
V
V
VT+ – VT–
Hysteresis
0.5
INT0–INT3, ADT, CNTR0, CNTR1, P20–P27
VT+ – VT–
VT+ – VT–
Hysteresis
Hysteresis
SCLK, RXD
RESET
0.5
0.5
V
V
RESET : VCC = 2.0 V to 5.5 V
IIH
IIH
“H” input current
VI = VCC
Pull-downs “off”
5.0
140
45
µA
µA
µA
P00–P07, P10–P17, P34–P37
VCC = 5 V, VI = VCC
Pull-downs “on”
30
70
25
VCC = 3 V, VI = VCC
Pull-downs “on”
6.0
“H” input current
VI = VCC
P20–P27, P40–P47, P50–P57, P60–P67,
P70, P71 (Note)
5.0
5.0
µA
IIH
IIH
IIL
“H” input current RESET
“H” input current XIN
VI = VCC
VI = VCC
VI = VSS
µA
µA
4.0
“L” input current
P00–P07, P10–P17, P34–P37,P40
–5.0
–5.0
µA
µA
IIL
“L” input current
VI = VSS
Pull-ups “off”
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VCC = 5 V, VI = VSS
Pull-ups “on”
–30
–70
–25
–140
µA
VCC = 3 V, VI = VSS
Pull-ups “on”
–6.0
–45
µA
µA
IIL
“L” input current RESET
“L” input current XIN
RAM hold voltage
VI = VSS
–5.0
IIL
VI = VSS
–4.0
µA
VRAM
When clock is stopped
V
1.8
5.5
Note: When “1” is set to the port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above
mentioned.
Rev.2.02 Jun 19, 2007 page 66 of 73
REJ03B0146-0202
3823 Group
Table 19 Electrical characteristics (2)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
4.3
3.7
2.5
0.8
0.4
2.9
2.5
1.7
1.0
0.8
0.5
0.3
2.2
1.9
1.4
1.0
0.7
0.6
0.4
0.2
1.35
1.2
0.9
0.8
0.35
0.3
0.2
0.15
13
Symbol
ICC
Parameter
Test conditions
VCC = 5.0 V
Unit
Min.
Max.
8.6
7.4
5.0
1.6
0.8
5.8
5.0
3.4
2.0
1.6
1.0
0.6
4.4
3.8
2.8
2.0
1.4
1.2
0.8
0.4
2.7
2.4
1.8
1.6
0.7
0.6
0.4
0.3
26
Power source current
Frequency/2 mode
Frequency/4 mode
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 4 MHz
f(XIN) = 2 MHz
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 2 MHz
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 2 MHz
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 2 MHz
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 2 MHz
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 2 MHz
f(XCIN) = 32 kHz
On-chip oscillator
f(XCIN) = 32 kHz
On-chip oscillator
f(XCIN) = 32 kHz
On-chip oscillator
f(XCIN) = 32 kHz
On-chip oscillator
VCC = 5 V, all modes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
VCC = 2.5 V
VCC = 5.0 V
VCC = 2.5 V
VCC = 5.0 V
VCC = 2.5 V
VCC = 5.0 V
VCC = 2.5 V
Frequency/8 mode
Frequency/2/4/8
mode
In WIT state
Low-speed mode
f(XIN) = stopped
VCC = 5.0 V
VCC = 2.5 V
VCC = 5.0 V
VCC = 2.5 V
80
240
14
µA
7
µA
14
42
µA
Low-speed mode
f(XIN) = stopped
In WIT state
5.5
20
11
µA
60
µA
3.5
3.5
500
50
7
µA
10
µA
µA
Current increased at
A/D converter operating
V
CC = 2.5 V, all modes
µA
All oscillation stopped
Ta = 25 °C, Output transistors “off” (in STP state)
0.1
1.0
10
µA
All oscillation stopped
Ta = 85 °C, Output transistors “off” (in STP state)
µA
VCC = 2.5 V, Ta = 25 °C
ROCO
On-chip oscillator oscillatoin
80
kHz
Rev.2.02 Jun 19, 2007 page 67 of 73
REJ03B0146-0202
3823 Group
Table 20 A/D converter characteristics (1) (in 8 bit A/D mode)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Min. Typ.
Symbol
Parameter
Test conditions
Unit
Max.
8
Bits
–
Resolution
±2
LSB
ABS
Absolute accuracy
(excluding quantization error)
ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”
2.2 V ≤ VCC = VREF ≤ 5.5 V
f(XIN) = 2 ● VCC MHz ≤ 10 MHz
±3
±3
±4
LSB
LSB
LSB
ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”
2.0 V ≤ VCC = VREF < 2.2 V
f(XIN) = 4.4 MHz
ADL2 = “0”, ADL1 = “1”, CPUM7 = “0”
VCC = VREF = 4.0 to 5.5 V
f(XIN) = 2 ● VCC MHz ≤ 10 MHz
ADL2 = “1”, ADL1 = “0”, CPUM7 = “1” and EXPCM0 = “1”
VCC = VREF = 1.8 to 2.2 V
TC(XIN)●100
µs
kΩ
µA
µA
tCONV
Conversion time
f(XIN) = 8 MHz (ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”)
12
50
35
100
200
5.0
RLADDER Ladder resistor
150
IVREF
IIA
Reference power source input current VREF = 5 V
Analog port input current
Table 21 A/D converter characteristics (2) (in 10 bit A/D mode)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Min. Typ.
Symbol
Parameter
Test conditions
Unit
Max.
10
Bits
–
Resolution
±4
LSB
ABS
Absolute accuracy
(excluding quantization error)
ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”
2.2 V ≤ VCC = VREF ≤ 5.5 V
f(XIN) = 2 ● VCC MHz ≤ 10 MHz
±4
±4
LSB
LSB
ADL2 = “0”, ADL1 = “1”, CPUM7 = “0”
VCC = VREF = 4.0 to 5.5 V
f(XIN) = 2 ● VCC MHz ≤ 10 MHz
ADL2 = “1”, ADL1 = “0”, CPUM7 = “1” and EXPCM0 = “1”
VCC = VREF = 1.8 to 2.2 V
TC(XIN)●100
µs
kΩ
µA
µA
tCONV
Conversion time
f(XIN) = 8 MHz (ADL2 = “0”, ADL1 = “0”, CPUM7 = “0”)
12
50
35
100
200
5.0
RLADDER Ladder resistor
150
IVREF
IIA
Reference power source input current VREF = 5 V
Analog port input current
Rev.2.02 Jun 19, 2007 page 68 of 73
REJ03B0146-0202
3823 Group
Table 22 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
1000/(4 ● VCC–8)
100
twH(XIN)
45
40
twL(XIN)
45
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
1000/(2 ● VCC–4)
200
105
85
105
85
twH(INT)
twL(INT)
tc(SCLK)
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
80
80
800
370
370
220
100
twH(SCLK)
twL(SCLK)
t
su(RXD–SCLK)
th(SCLK–RXD) Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this limits value by four when bit 6 of address 001A16 is “0” (UART).
Table 23 Timing requirements (2)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
125
1000/(10 ● VCC–12)
twH(XIN)
twL(XIN)
tc(CNTR)
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
50
70
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
50
70
1000/VCC
1000/(5 ● VCC–8)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
230
tc(SCLK)
2000
twH(SCLK)
twL(SCLK)
950
950
t
su(RXD–SCLK)
400
th(SCLK–RXD) Serial I/O input hold time
200
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this limits value by four when bit 6 of address 001A16 is “0” (UART).
Rev.2.02 Jun 19, 2007 page 69 of 73
REJ03B0146-0202
3823 Group
Table 24 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
140
tC (SCLK)/2–30
tC (SCLK)/2–30
ns
ns
ns
ns
ns
ns
twH(SCLK)
twL(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
td(SCLK–TXD) Serial I/O output delay time (Note)
tv(SCLK–TXD) Serial I/O output valid time (Note)
–30
Serial I/O clock output rising time
Serial I/O clock output falling time
30
30
tr(SCLK)
tf(SCLK)
Note : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Table 25 Switching characteristics (2)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Serial I/O clock output “H” pulse width
Unit
Min.
Max.
350
ns
ns
ns
ns
ns
ns
tC (SCLK)/2–100
tC (SCLK)/2–100
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note)
Serial I/O output valid time (Note)
Serial I/O clock output rising time
Serial I/O clock output falling time
–30
100
100
tf(SCLK)
Note : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Measurement output pin
1 kΩ
100 pF
Measurement output pin
100 pF
CMOS output
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register
(address 001B16) is “1”. (N-channel open-
drain output mode)
Fig. 69 Circuit for measuring output switching characteristics
Rev.2.02 Jun 19, 2007 page 70 of 73
REJ03B0146-0202
3823 Group
tC(CNTR)
tWH(CNTR)
0.8VCC
tWL(CNTR)
CNTR0, CNTR1
0.2VCC
tWH(INT)
0.8VCC
tWL(INT)
INT0–INT3
0.2VCC
tW(RESET)
0.8VCC
RESET
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(SCLK)
tf
tr
tWH(SCLK)
tWL(SCLK)
0.2VCC
SCLK
0.8VCC
tsu(RXD-SCLK)
th(SCLK-RXD)
RXD
TXD
0.8VCC
0.2VCC
td(SCLK-TXD)
tv(SCLK-TXD)
Fig. 70 Timing diagram
Rev.2.02 Jun 19, 2007 page 71 of 73
REJ03B0146-0202
3823 Group
PACKAGE OUTLINE
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas
Technology website.
JEITA Package Code
P-QFP80-14x20-0.80
RENESAS Code
PRQP0080GB-A
Previous Code
80P6N-A
MASS[Typ.]
1.6g
HD
*1
D
64
41
65
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Dimension in Millimeters
Reference
Symbol
80
25
Min Nom Max
D
E
19.8 20.0 20.2
13.8 14.0 14.2
2.8
1
24
ZD
A2
HD
HE
A
Index mark
22.5 22.8 23.1
16.5 16.8 17.1
3.05
F
A1
bp
c
0.1 0.2
0
0.3 0.35 0.45
0.13 0.15 0.2
*3
0° 10°
0.65 0.8 0.95
0.10
bp
y
e
L
e
y
Detail F
ZD
ZE
L
0.8
1.0
0.4 0.6 0.8
Rev.2.02 Jun 19, 2007 page 72 of 73
REJ03B0146-0202
3823 Group
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
61
40
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
Terminal cross section
D
E
11.9 12.0 12.1
11.9 12.0 12.1
1.4
80
A2
HD
HE
A
21
13.8 14.0 14.2
13.8 14.0 14.2
1.7
1
20
ZD
Index mark
A1
bp
b1
c
0.1 0.2
0
F
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
c1
0°
10°
y
*3
e
bp
e
x
L
0.5
x
0.08
0.08
L1
y
ZD
ZE
L
Detail F
1.25
1.25
0.3 0.5 0.7
1.0
L1
Rev.2.02 Jun 19, 2007 page 73 of 73
REJ03B0146-0202
REVISION HISTORY
3823 GROUP DATA SHEET
Rev.
Date
Description
Summary
Page
1.00 05/13/05
2.00 05/07/07
First edition
6
8
9
Table 3 is partly revised
Fig.5 is partly added
Table 4 is revised
14
“ROM Code Protect Address” is added
Fig.10 is revised
40
49
52
54
“STP instruction Execution” is revised
“Oscillation Control” (1) Stop Mode is partly revised
“LCD drive Control Circuit” is revised
“(6) Wiring to P40/(VPP) pin” is revised
Fig.59 is revised
55
60
Fig.60 is partly deleted
“NOTES ON QzROM” is added
Table 18 is partly added
2.01 05/11/08
2.02 07/06/19
6
61
65-66
Table 3 is partly revised
Table 19, 20 are partly revised
PACKAGE OUTLINE revised
−
6
8
“RENESAS TECHNICAL UPDATE” reflected:
TN-740-A111A/E
Table 3: Function except a port function; •Serial I/O function pins → •Serial inter-
face function pins
Fig. 5 M38234G4, M38235G6: Under development → Mass production
Note deleted
9
Table 4: Under development deleted
10
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU):
Description added
15
Fig. 11: Note added
CPU mode extension register (002B16) → CPU mode expansion register
Peripheral function extension register (003016) → Peripheral function
expansion register
22
23-27
46
Table 8: AVSS added, Note revised
INTERRUPTS: Description revised, Fig. 18-20 added
ROM CORRECTION FUNCTION: Description added
Initial Value of Watchdog Timer: Description added
Standard Operation of Watchdog Timer: A part of description deleted
Bit 6 and bit 7 of Watchdog Timer Control Register: added and revised
Fig. 48 revised, Note added
48
51
52
53
Fig. 53: Port P0 direction register (000016) → (000116)
Frequency Control: Description revised
Fig. 56: revised
54
Fig. 57: revised
55-58
58
QzROM Writing Mode: added
Processor Status Register: added
59
63
Overvoltage: Description revised and Fig. 68 added
Table 15
VCC: Frequency/4 mode → Frequency/8 mode
VREF: Limits Min. 2.0 → 1.8
66
Table 18: VRAM added
(1/2)
REVISION HISTORY
3823 GROUP DATA SHEET
Rev.
Date
Description
Summary
Page
2.02 07/06/19
67
Table 19
ROCO: Ta = 25 °C added
Note added
72
(2/2)
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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