M38502FFH-XXXFP [RENESAS]
8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES; 8位CISC单片机740系列/ 38000系列
| 型号： | M38502FFH-XXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES |
| 文件： | 总287页 (文件大小：2887K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REJ09B0080-0103Z
3850 Group (Spec. H)
User's Manual
8
RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 1.03
Revision date: Sep. 18, 2003
www.renesas.com
Keep safety first in your circuit designs!
•
Renesas Technology Corporation puts the maximum effort into making semiconductor prod-
ucts better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corporation product best suited to the customer's application; they do
not convey any license under any intellectual property rights, or any other rights, belonging
to Renesas Technology Corporation or a third party.
• Renesas Technology Corporation assumes no responsibility for any damage, or infringe-
ment of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, pro-
grams and algorithms represents information on products at the time of publication of these
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due to product improvements or other reasons. It is therefore recommended that custom-
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3850 Group (Spec. H) User’s Manual
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.0 Aug. 30, 2001
–
First edition issued
1.1 Sep. 10, 2001 3-5
Limits and test conditions into Table 3.1.5 are partly added.
1.02 Aug. 29, 2003 1-6
Fig. 4 is partly revised.
1-7
1-7
Table 2 is partly added.
Note of Table 3 is added.
1-37
Fig. 42 is partly revised.
1-38
Fig. 43 is partly revised.
2-103
2-104
2-105
2-106
Clause name of “2.11 Flash memory mode” is revised.
Notes of Fig. 2.11.3 are partly revised.
Table 2.11.2 is partly revised.
Explanations of “[Beginning procedure]” of “2.11.6 CPU rewrite mode” are partly
added.
2-107
3-4
3-20
3-22
3-24
Explanations of this page are added.
Parameter of Table 3.1.4 is partly revised.
Fig. 3.2.16 is partly revised.
Fig. 3.2.20 is partly revised.
Fig. 3.2.24 is partly revised.
Fig. 52 is partly revised.
1.03 Sep. 18, 2003 1-51
(1/1)
Preface
This user’s manual describes Renesas’s CMOS 8-bit
microcomputers 3850 Group (Spec. H).
After reading this manual, the user should have a
through knowledge of the functions and features of
the 3850 Group (Spec. H), and should be able to
fully utilize the product. The manual starts with
specifications and ends with application examples.
For details of software, refer to the “740 Family
Software Manual”.
T
he user who is using the 3850 Group (standard)
needs to refer to not this manual but “3850/3851 Group
User’s Manual”.
BEFORE USING THIS MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. Chapter 3 also includes necessary information for
systems development. You must refer to that chapter.
1. Organization
ꢀ CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
ꢀ CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
ꢀ CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the notes, and the list of registers.
ꢀFor the mask ROM confirmation form, the ROM programming confirmation form, and the mark
specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/
rom).
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B16
]
Name
B
At reset
Function
R
W
b1 b0
Processor mode bits
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
0 : 0 page
1 : 1 page
0
0
0
0
0
1
0
1
2
3
4
5
6
7
Not available
Stack page selection bit
ꢀ
ꢀ
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.”
0 : Operating
ꢀ
ꢀ
Main clock (XIN-XOUT) stop bit
1 : Stopped
0 : X -XOUT selected
1 : XCININ-XCOUT selected
Internal system clock selection bit
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Note 1:. Contents immediately after reset release
0....... “0” at reset release
1....... “1” at reset release
?....... Undefined at reset release
ꢀ.......Contents determined by option at reset release
Note 2: Bit attributes.........The attributes of control register bits are classified into 3 bytes : read-only, write-
only and read and write. In the figure, these attributes are represented as follows :
R.......Read
...... Read enabled
W......Write
..... Write enabled
ꢀ.......Read disabled
ꢀ...... Write disabled
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES.................................................................................................................................... 1-2
APPLICATION ................................................................................................................................ 1-2
PIN CONFIGURATION .................................................................................................................. 1-2
FUNCTIONAL BLOCK .................................................................................................................. 1-3
PIN DESCRIPTION ........................................................................................................................ 1-4
PART NUMBERING ....................................................................................................................... 1-5
GROUP EXPANSION .................................................................................................................... 1-6
Memory Type ............................................................................................................................ 1-6
Memory Size ............................................................................................................................. 1-6
Packages ................................................................................................................................... 1-6
Notes on differences between 3850 group (standard) and 3850 group (spec. H)......... 1-7
FUNCTIONAL DESCRIPTION ...................................................................................................... 1-8
Central Processing Unit (CPU) .............................................................................................. 1-8
Memory .................................................................................................................................... 1-12
I/O Ports .................................................................................................................................. 1-14
Interrupts .................................................................................................................................1-18
Timers ...................................................................................................................................... 1-21
Serial I/O .................................................................................................................................1-23
Pulse Width Modulation (PWM) ........................................................................................... 1-30
A-D Converter ......................................................................................................................... 1-32
Watchdog Timer .....................................................................................................................1-33
Reset Circuit ...........................................................................................................................1-34
Clock Generating Circuit ....................................................................................................... 1-36
Flash Memory Version........................................................................................................... 1-39
NOTES ON PROGRAMMING ..................................................................................................... 1-73
NOTES ON USAGE .....................................................................................................................1-73
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-74
DATA REQUIRED FOR ONE TIME PROM PROGRAMMING ORDERS ............................. 1-74
ROM PROGRAMMING METHOD .............................................................................................. 1-74
FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-75
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map ................................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-2
2.1.3 Terminate unused pins .................................................................................................. 2-3
2.1.4 Notes on I/O port ........................................................................................................... 2-4
2.1.5 Termination of unused pins .......................................................................................... 2-5
2.2 Interrupt ................................................................................................................................... 2-6
2.2.1 Memory map ................................................................................................................... 2-6
2.2.2 Relevant registers .......................................................................................................... 2-7
2.2.3 Interrupt source ............................................................................................................ 2-10
2.2.4 Interrupt operation........................................................................................................2-11
2.2.5 Interrupt control ............................................................................................................ 2-14
2.2.6 INT interrupt.................................................................................................................. 2-17
2.2.7 Notes on interrupts ...................................................................................................... 2-18
3850 Group (Spec. H) User’s Manual
i
Table of contents
2.3 Timer.......................................................................................................................................2-20
2.3.1 Memory map ................................................................................................................. 2-20
2.3.2 Relevant registers ........................................................................................................2-20
2.3.3 Timer application examples ........................................................................................ 2-27
2.3.4 Notes on timer ..............................................................................................................2-39
2.4 Serial I/O ................................................................................................................................ 2-40
2.4.1 Memory map ................................................................................................................. 2-40
2.4.2 Relevant registers ........................................................................................................2-41
2.4.3 Serial I/O connection examples ................................................................................. 2-48
2.4.4 Setting of serial I/O transfer data format ................................................................. 2-50
2.4.5 Serial I/O application examples ................................................................................. 2-51
2.4.6 Notes on serial I/O ...................................................................................................... 2-71
2.5 PWM ........................................................................................................................................2-74
2.5.1 Memory map ................................................................................................................. 2-74
2.5.2 Relevant registers ........................................................................................................2-74
2.5.3 PWM output circuit application example................................................................... 2-76
2.5.4 Notes on PWM ............................................................................................................. 2-78
2.6 A-D converter ....................................................................................................................... 2-79
2.6.1 Memory map ................................................................................................................. 2-79
2.6.2 Relevant registers ........................................................................................................2-79
2.6.3 A-D converter application examples .......................................................................... 2-82
2.6.4 Notes on A-D converter .............................................................................................. 2-84
2.7 Watchdog timer ....................................................................................................................2-85
2.7.1 Memory map ................................................................................................................. 2-85
2.7.2 Relevant registers ........................................................................................................2-85
2.7.3 Watchdog timer application examples....................................................................... 2-87
2.7.4 Notes on watchdog timer ............................................................................................ 2-88
2.8 Reset.......................................................................................................................................2-89
2.8.1 Connection example of reset IC ................................................................................ 2-89
2.8.2 Notes on RESET pin ................................................................................................... 2-90
2.9 Clock generating circuit .................................................................................................... 2-91
2.9.1 Relevant registers ........................................................................................................2-91
2.9.2 Clock generating circuit application example ........................................................... 2-92
2.10 Standby function ............................................................................................................... 2-95
2.10.1 Relevant registers ...................................................................................................... 2-95
2.10.2 Stop mode................................................................................................................... 2-96
2.10.3 Wait mode .................................................................................................................2-100
2.11 Flash memory mode .......................................................................................................2-103
2.11.1 Overview....................................................................................................................2-103
2.11.2 Memory map .............................................................................................................2-103
2.11.3 Relevant registers ....................................................................................................2-104
2.11.4 Parallel I/O mode .....................................................................................................2-105
2.11.5 Standard serial I/O mode........................................................................................2-105
2.11.6 CPU rewrite mode ...................................................................................................2-106
2.11.7 Flash memory mode application examples ..........................................................2-108
2.11.8 Notes on CPU rewrite mode ..................................................................................2-113
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions............................................................................ 3-3
3850 Group (Spec. H) User’s Manual
ii
Table of contents
3.1.3 Electrical characteristics ................................................................................................ 3-4
3.1.4 A-D converter characteristics ....................................................................................... 3-6
3.1.5 Timing requirements and switching characteristics ................................................... 3-7
3.2 Standard characteristics .................................................................................................... 3-11
3.2.1 Flash memory version power source current standard characteristics ................ 3-11
3.2.2 Mask ROM version power source current standard characteristics ..................... 3-14
3.2.3 PROM version power source current standard characteristics.............................. 3-17
3.2.4 Flash memory version port standard characteristics .............................................. 3-20
3.2.5 Mask ROM version port standard characteristics.................................................... 3-22
3.2.6 PROM version port standard characteristics............................................................ 3-24
3.2.7 A-D conversion standard characteristics................................................................... 3-26
3.3 Notes on use ........................................................................................................................ 3-31
3.3.1 Notes on input and output ports................................................................................ 3-31
3.3.2 Termination of unused pins ........................................................................................ 3-32
3.3.3 Notes on interrupts ...................................................................................................... 3-33
3.3.4 Notes on timer ..............................................................................................................3-34
3.3.5 Notes on serial I/O ...................................................................................................... 3-34
3.3.6 Notes on PWM ............................................................................................................. 3-37
3.3.7 Notes on A-D converter .............................................................................................. 3-37
3.3.8 Notes on watchdog timer ............................................................................................ 3-37
3.3.9 Notes on RESET pin ................................................................................................... 3-38
3.3.10 Notes on using stop mode ....................................................................................... 3-38
3.3.11 Notes on wait mode ..................................................................................................3-38
3.3.12 Notes on CPU rewrite mode of flash memory version......................................... 3-39
3.3.13 Notes on restarting oscillation.................................................................................. 3-39
3.3.14 Notes on programming .............................................................................................. 3-40
3.3.15 EPROM Version/One Time PROM Version/Flash Memory Version.................... 3-42
3.3.16 Handling of Source Pins ........................................................................................... 3-42
3.3.17 Differences between 3850 group (standard) and 3850 group (spec. H) ........... 3-42
3.4 Countermeasures against noise ...................................................................................... 3-43
3.4.1 Shortest wiring length ..................................................................................................3-43
3.4.2 Connection of bypass capacitor across VSS line and VCC line............................... 3-45
3.4.3 Wiring to analog input pins ........................................................................................ 3-46
3.4.4 Oscillator concerns....................................................................................................... 3-47
3.4.5 Setup for I/O ports....................................................................................................... 3-48
3.4.6 Providing of watchdog timer function by software .................................................. 3-49
3.5 List of registers ................................................................................................................... 3-50
3.6 Package outline ................................................................................................................... 3-66
3.7 Machine instructions .......................................................................................................... 3-68
3.8 List of instruction code ..................................................................................................... 3-79
3.9 SFR memory map ................................................................................................................3-80
3.10 Pin configurations ............................................................................................................. 3-81
3850 Group (Spec. H) User’s Manual
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. 1 M38503MXH-XXXFP/SP pin configuration ...................................................................... 1-2
Fig. 2 Functional block diagram................................................................................................... 1-3
Fig. 3 Part numbering.................................................................................................................... 1-5
Fig. 4 Memory expansion plan ..................................................................................................... 1-6
Fig. 5 740 Family CPU register structure................................................................................... 1-8
Fig. 6 Register push and pop at interrupt generation and subroutine call ........................... 1-9
Fig. 7 Structure of CPU mode register ..................................................................................... 1-11
Fig. 8 Memory map diagram ...................................................................................................... 1-12
Fig. 9 Memory map of special function register (SFR) .......................................................... 1-13
Fig. 10 Port block diagram (1) ................................................................................................... 1-15
Fig. 11 Port block diagram (2) ................................................................................................... 1-16
Fig. 12 Port block diagram (3) ................................................................................................... 1-17
Fig. 13 Interrupt control............................................................................................................... 1-20
Fig. 14 Structure of interrupt-related registers......................................................................... 1-20
Fig. 15 Structure of timer XY mode register............................................................................ 1-21
Fig. 16 Structure of timer count source selection register..................................................... 1-21
Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2 ......................................... 1-22
Fig. 18 Block diagram of clock synchronous serial I/O1........................................................ 1-23
Fig. 19 Operation of clock synchronous serial I/O1 function ................................................ 1-23
Fig. 20 Block diagram of UART serial I/O1 ............................................................................. 1-24
Fig. 21 Operation of UART serial I/O1 function ...................................................................... 1-25
Fig. 22 Structure of serial I/O1 control registers..................................................................... 1-26
Fig. 23 Structure of serial I/O2 control registers 1, 2 ............................................................ 1-27
Fig. 24 Block diagram of serial I/O2 ......................................................................................... 1-28
Fig. 25 Timing chart of serial I/O2 ............................................................................................ 1-28
Fig. 26 SCMP2 output operation................................................................................................... 1-29
Fig. 27 Timing of PWM period ................................................................................................... 1-30
Fig. 28 Block diagram of PWM function ................................................................................... 1-30
Fig. 29 Structure of PWM control register ............................................................................... 1-31
Fig. 30 PWM output timing when PWM register or PWM prescaler is changed................ 1-31
Fig. 31 Structure of AD control register ................................................................................... 1-32
Fig. 32 Structure of A-D conversion registers ......................................................................... 1-32
Fig. 33 Block diagram of A-D converter ................................................................................... 1-32
Fig. 34 Block diagram of Watchdog timer ................................................................................ 1-33
Fig. 35 Structure of Watchdog timer control register ............................................................. 1-33
Fig. 36 Reset circuit example .................................................................................................... 1-34
Fig. 37 Reset sequence ..............................................................................................................1-34
Fig. 38 Internal status at reset .................................................................................................. 1-35
Fig. 39 Ceramic resonator circuit .............................................................................................. 1-36
Fig. 40 External clock input circuit ............................................................................................ 1-36
Fig. 41 Structure of MISRG ........................................................................................................1-37
Fig. 42 System clock generating circuit block diagram (Single-chip mode) ........................ 1-37
Fig. 43 State transitions of system clock ................................................................................. 1-38
Fig. 44 Block diagram of flash memory version ...................................................................... 1-40
Fig. 45 Flash memory control registers .................................................................................... 1-42
3850 Group (Spec. H) User’s Manual
iv
List of figures
Fig. 46 CPU rewrite mode set/reset flowchart ......................................................................... 1-42
Fig. 47 Program flowchart........................................................................................................... 1-44
Fig. 48 Erase flowchart ............................................................................................................... 1-44
Fig. 49 Full status check flowchart and remedial procedure for errors ............................... 1-46
Fig. 50 ROM code protect control address .............................................................................. 1-47
Fig. 51 ID code store addresses ............................................................................................... 1-48
Fig. 52 Pin connection diagram in parallel I/O mode ............................................................. 1-51
Fig. 53 Page program flowchart................................................................................................. 1-53
Fig. 54 Block erase flowchart..................................................................................................... 1-53
Fig. 55 Full status check flowchart and remedial procedure for errors ............................... 1-55
Fig. 56 Connection for serial I/O mode .................................................................................... 1-58
Fig. 57 Timing for page read ..................................................................................................... 1-60
Fig. 58 Timing for reading the status register ......................................................................... 1-60
Fig. 59 Timing for clearing the status register ........................................................................ 1-60
Fig. 60 Timing for the page program ........................................................................................ 1-61
Fig. 61 Timing for erasing all blocks ........................................................................................ 1-61
Fig. 62 Timing for download....................................................................................................... 1-62
Fig. 63 Timing for version information output .......................................................................... 1-62
Fig. 64 Timing for the ID check................................................................................................. 1-63
Fig. 65 ID code storage addresses ........................................................................................... 1-63
Fig. 66 Full status check flowchart and remedial procedure for errors ............................... 1-65
Fig. 67 Example circuit application for the standard serial I/O mode .................................. 1-65
Fig. 68 Vcc power up/power down timing ................................................................................ 1-69
Fig. 69 AC wave for read operation.......................................................................................... 1-70
Fig. 70 AC electrical characteristics test condition for read operation ................................ 1-70
Fig. 71 AC wave for program operation (WE control) ............................................................ 1-71
Fig. 72 AC wave for program operation (CE control)............................................................. 1-71
Fig. 73 AC wave for erase operation (WE control) ................................................................ 1-72
Fig. 74 AC wave for erase operation (CE control) ................................................................. 1-72
Fig. 75 Programming and testing of One Time PROM version ............................................ 1-74
Fig. 76 A-D conversion equivalent circuit ................................................................................. 1-76
Fig. 77 A-D conversion timing chart.......................................................................................... 1-76
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of I/O port relevant registers .............................................................. 2-2
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4) ...................................................................... 2-2
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4) ....................................... 2-3
Fig. 2.2.1 Memory map of registers relevant to interrupt ........................................................ 2-6
Fig. 2.2.2 Structure of Interrupt edge selection register .......................................................... 2-7
Fig. 2.2.3 Structure of Interrupt request register 1 ................................................................... 2-8
Fig. 2.2.4 Structure of Interrupt request register 2 ................................................................... 2-8
Fig. 2.2.5 Structure of Interrupt control register 1 .................................................................... 2-9
Fig. 2.2.6 Structure of Interrupt control register 2 .................................................................... 2-9
Fig. 2.2.7 Interrupt operation diagram....................................................................................... 2-11
Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
........................................................................................................................................................ 2-12
Fig. 2.2.9 Time up to execution of interrupt processing routine ........................................... 2-13
Fig. 2.2.10 Timing chart after acceptance of interrupt request ............................................. 2-13
Fig. 2.2.11 Interrupt control diagram ......................................................................................... 2-14
Fig. 2.2.12 Example of multiple interrupts................................................................................ 2-16
Fig. 2.2.13 Sequence of changing relevant register ............................................................... 2-18
3850 Group (Spec. H) User’s Manual
v
List of figures
Fig. 2.2.14 Sequence of check of interrupt request bit.......................................................... 2-19
Fig. 2.3.1 Memory map of registers relevant to timers .......................................................... 2-20
Fig. 2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y ............................................ 2-20
Fig. 2.3.3 Structure of Timer 1 ..................................................................................................2-21
Fig. 2.3.4 Structure of Timer 2 ..................................................................................................2-21
Fig. 2.3.5 Structure of Timer X, Timer Y ................................................................................. 2-22
Fig. 2.3.6 Structure of Timer XY mode register ...................................................................... 2-23
Fig. 2.3.7 Structure of Timer count source selection register ............................................... 2-24
Fig. 2.3.8 Structure of Interrupt request register 1 ................................................................. 2-25
Fig. 2.3.9 Structure of Interrupt request register 2 ................................................................. 2-25
Fig. 2.3.10 Structure of Interrupt control register 1 ................................................................ 2-26
Fig. 2.3.11 Structure of Interrupt control register 2 ................................................................ 2-26
Fig. 2.3.12 Timers connection and setting of division ratios ................................................. 2-28
Fig. 2.3.13 Relevant registers setting ....................................................................................... 2-28
Fig. 2.3.14 Control procedure..................................................................................................... 2-29
Fig. 2.3.15 Peripheral circuit example....................................................................................... 2-30
Fig. 2.3.16 Timers connection and setting of division ratios ................................................. 2-30
Fig. 2.3.17 Relevant registers setting ....................................................................................... 2-31
Fig. 2.3.18 Control procedure..................................................................................................... 2-32
Fig. 2.3.19 Judgment method of valid/invalid of input pulses ............................................... 2-33
Fig. 2.3.20 Relevant registers setting ....................................................................................... 2-34
Fig. 2.3.21 Control procedure..................................................................................................... 2-35
Fig. 2.3.22 Timers connection and setting of division ratios ................................................. 2-36
Fig. 2.3.23 Relevant registers setting ....................................................................................... 2-37
Fig. 2.3.24 Control procedure..................................................................................................... 2-38
Fig. 2.4.1 Memory map of registers relevant to Serial I/O .................................................... 2-40
Fig. 2.4.2 Structure of Serial I/O2 control register 1 .............................................................. 2-41
Fig. 2.4.3 Structure of Serial I/O2 control register 2 .............................................................. 2-41
Fig. 2.4.4 Structure of Serial I/O2 register............................................................................... 2-42
Fig. 2.4.5 Structure of Transmit/Receive buffer register ........................................................ 2-42
Fig. 2.4.6 Structure of Serial I/O1 status register ................................................................... 2-43
Fig. 2.4.7 Structure of Serial I/O1 control register.................................................................. 2-44
Fig. 2.4.8 Structure of UART control register .......................................................................... 2-44
Fig. 2.4.9 Structure of Baud rate generator ............................................................................. 2-45
Fig. 2.4.10 Structure of Interrupt edge selection register ...................................................... 2-45
Fig. 2.4.11 Structure of Interrupt request register 1 ............................................................... 2-46
Fig. 2.4.12 Structure of Interrupt request register 2 ............................................................... 2-46
Fig. 2.4.13 Structure of Interrupt control register 1 ................................................................ 2-47
Fig. 2.4.14 Structure of Interrupt control register 2 ................................................................ 2-47
Fig. 2.4.15 Serial I/O connection examples (1) ....................................................................... 2-48
Fig. 2.4.16 Serial I/O connection examples (2) ....................................................................... 2-49
Fig. 2.4.17 Serial I/O transfer data format ............................................................................... 2-50
Fig. 2.4.18 Connection diagram ................................................................................................. 2-51
Fig. 2.4.19 Timing chart ..............................................................................................................2-51
Fig. 2.4.20 Registers setting relevant to transmitting side..................................................... 2-52
Fig. 2.4.21 Registers setting relevant to receiving side ......................................................... 2-53
Fig. 2.4.22 Control procedure of transmitting side.................................................................. 2-54
Fig. 2.4.23 Control procedure of receiving side ...................................................................... 2-55
Fig. 2.4.24 Connection diagram ................................................................................................. 2-56
Fig. 2.4.25 Timing chart (Serial I/O1) ....................................................................................... 2-56
Fig. 2.4.26 Registers setting relevant to Serial I/O1 .............................................................. 2-57
Fig. 2.4.27 Setting of serial I/O1 transmission data ............................................................... 2-57
3850 Group (Spec. H) User’s Manual
vi
List of figures
Fig. 2.4.28 Control procedure of Serial I/O1............................................................................ 2-58
Fig. 2.4.29 Registers setting relevant to Serial I/O2 .............................................................. 2-59
Fig. 2.4.30 Setting of serial I/O2 transmission data ............................................................... 2-59
Fig. 2.4.31 Control procedure of Serial I/O2............................................................................ 2-60
Fig. 2.4.32 Connection diagram ................................................................................................. 2-61
Fig. 2.4.33 Timing chart ..............................................................................................................2-62
Fig. 2.4.34 Relevant registers setting ....................................................................................... 2-62
Fig. 2.4.35 Control procedure of master unit ........................................................................... 2-63
Fig. 2.4.36 Control procedure of slave unit ............................................................................. 2-64
Fig. 2.4.37 Connection diagram ................................................................................................. 2-65
Fig. 2.4.38 Timing chart (using UART) ..................................................................................... 2-65
Fig. 2.4.39 Registers setting relevant to transmitting side..................................................... 2-67
Fig. 2.4.40 Registers setting relevant to receiving side ......................................................... 2-68
Fig. 2.4.41 Control procedure of transmitting side.................................................................. 2-69
Fig. 2.4.42 Control procedure of receiving side ...................................................................... 2-70
Fig. 2.4.43 Sequence of setting serial I/O1 control register again ....................................... 2-72
Fig. 2.5.1 Memory map of registers relevant to PWM ........................................................... 2-74
Fig. 2.5.2 Structure of PWM control register ........................................................................... 2-74
Fig. 2.5.3 Structure of PWM prescaler ..................................................................................... 2-75
Fig. 2.5.4 Structure of PWM register ........................................................................................ 2-75
Fig. 2.5.5 Connection diagram ................................................................................................... 2-76
Fig. 2.5.6 PWM output timing..................................................................................................... 2-76
Fig. 2.5.7 Setting of relevant registers ..................................................................................... 2-77
Fig. 2.5.8 PWM output ................................................................................................................2-77
Fig. 2.5.9 Control procedure....................................................................................................... 2-78
Fig. 2.6.1 Memory map of registers relevant to A-D converter ............................................ 2-79
Fig. 2.6.2 Structure of A-D control register .............................................................................. 2-79
Fig. 2.6.3 Structure of A-D conversion register (high-order) ................................................. 2-80
Fig. 2.6.4 Structure of A-D conversion register (low-order) ................................................... 2-80
Fig. 2.6.5 Structure of Interrupt request register 2 ................................................................. 2-81
Fig. 2.6.6 Structure of Interrupt control register 2 .................................................................. 2-81
Fig. 2.6.7 Connection diagram ................................................................................................... 2-82
Fig. 2.6.8 Relevant registers setting ......................................................................................... 2-82
Fig. 2.6.9 Control procedure for 8-bit read .............................................................................. 2-83
Fig. 2.6.10 Control procedure for 10-bit read .......................................................................... 2-83
Fig. 2.7.1 Memory map of registers relevant to watchdog timer .......................................... 2-85
Fig. 2.7.2 Structure of Watchdog timer control register ......................................................... 2-85
Fig. 2.7.3 Structure of CPU mode register .............................................................................. 2-86
Fig. 2.7.4 Watchdog timer connection and division ratio setting .......................................... 2-87
Fig. 2.7.5 Relevant registers setting ......................................................................................... 2-88
Fig. 2.7.6 Control procedure....................................................................................................... 2-88
Fig. 2.8.1 Example of poweron reset circuit ............................................................................ 2-89
Fig. 2.8.2 RAM backup system ..................................................................................................2-89
Fig. 2.9.1 Structure of CPU mode register .............................................................................. 2-91
Fig. 2.9.2 Connection diagram ................................................................................................... 2-92
Fig. 2.9.3 Status transition diagram during power failure ...................................................... 2-92
Fig. 2.9.4 Setting of relevant registers ..................................................................................... 2-93
Fig. 2.9.5 Control procedure....................................................................................................... 2-94
Fig. 2.10.1 Structure of MISRG ................................................................................................. 2-95
Fig. 2.10.2 Oscillation stabilizing time at restoration by reset input .................................... 2-97
Fig. 2.10.3 Execution sequence example at restoration by occurrence of INT interrupt request
0
........................................................................................................................................................ 2-99
3850 Group (Spec. H) User’s Manual
vii
List of figures
Fig. 2.10.4 Reset input time .....................................................................................................2-101
Fig. 2.11.1 Memory map of flash memory version for 3850 Group ...................................2-103
Fig. 2.11.2 Memory map of registers relevant to flash memory .........................................2-104
Fig. 2.11.3 Structure of Flash memory control register........................................................2-104
Fig. 2.11.4 Rewrite example of built-in flash memory in serial I/O mode ......................... 2-108
Fig. 2.11.5 Connection example in serial I/O mode (1) .......................................................2-109
Fig. 2.11.6 Connection example in serial I/O mode (2) .......................................................2-109
Fig. 2.11.7 Connection example in serial I/O mode (3) .......................................................2-110
Fig. 2.11.8 Example of rewrite system for built-in flash memory in CPU rewrite mode . 2-111
Fig. 2.11.9 CPU rewrite mode beginning/release flowchart .................................................2-112
CHAPTER 3 APPENDIX
Fig. 3.1.1 Circuit for measuring output switching characteristics ............................................ 3-9
Fig. 3.1.2 Timing diagram ........................................................................................................... 3-10
Fig. 3.2.1 Flash memory version power source current standard characteristics (in high-speed
mode, f(XIN) = 8 MHz) ............................................................................................... 3-11
Fig. 3.2.2 Flash memory version power source current standard characteristics (in high-speed
mode, f(XIN) = 4 MHz) ............................................................................................... 3-11
Fig. 3.2.3 Flash memory version power source current standard characteristics (in middle-
speed mode, f(XIN) = 8 MHz) ................................................................................... 3-12
Fig. 3.2.4 Flash memory version power source current standard characteristics (in middle-
speed mode, f(XIN) = 4 MHz) ................................................................................... 3-12
Fig. 3.2.5 Flash memory version power source current standard characteristics (in low-speed
mode) ...........................................................................................................................3-13
Fig. 3.2.6 Mask ROM version power source current standard characteristics (in high-speed
mode, f(XIN) = 8 MHz) ............................................................................................... 3-14
Fig. 3.2.7 Mask ROM version power source current standard characteristics (in high-speed
mode, f(XIN) = 4 MHz) ............................................................................................... 3-14
Fig. 3.2.8 Mask ROM version power source current standard characteristics (in middle-speed
mode, f(XIN) = 8 MHz) ............................................................................................... 3-15
Fig. 3.2.9 Mask ROM version power source current standard characteristics (in middle-speed
mode, f(XIN) = 4 MHz) ............................................................................................... 3-15
Fig. 3.2.10 Mask ROM version power source current standard characteristics (in low-speed
mode)......................................................................................................................... 3-16
Fig. 3.2.11 PROM version power source current standard characteristics (in high-speed mode,
f(XIN) = 8 MHz) ......................................................................................................... 3-17
Fig. 3.2.12 PROM version power source current standard characteristics (in high-speed mode,
f(XIN) = 4 MHz) ......................................................................................................... 3-17
Fig. 3.2.13 PROM version power source current standard characteristics (in middle-speed
mode, f(XIN) = 8 MHz) ............................................................................................. 3-18
Fig. 3.2.14 PROM version power source current standard characteristics (in middle-speed
mode, f(XIN) = 4 MHz) ............................................................................................. 3-18
Fig. 3.2.15 PROM version power source current standard characteristics (in low-speed mode)
........................................................................................................................................................ 3-19
Fig. 3.2.16 CMOS output port P-channel side characteristics (Ta = 25 °C)....................... 3-20
Fig. 3.2.17 CMOS output port N-channel side characteristics (Ta = 25 °C) ...................... 3-20
Fig. 3.2.18 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C).. 3-21
Fig. 3.2.19 CMOS large current output port N-channel side characteristics (Ta = 25 °C) . 3-21
Fig. 3.2.20 CMOS output port P-channel side characteristics (Ta = 25 °C)....................... 3-22
Fig. 3.2.21 CMOS output port N-channel side characteristics (Ta = 25 °C) ...................... 3-22
Fig. 3.2.22 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C).. 3-23
3850 Group (Spec. H) User’s Manual
viii
List of figures
Fig. 3.2.23 CMOS large current output port N-channel side characteristics (Ta = 25 °C) . 3-23
Fig. 3.2.24 CMOS output port P-channel side characteristics (Ta = 25 °C)....................... 3-24
Fig. 3.2.25 CMOS output port N-channel side characteristics (Ta = 25 °C) ...................... 3-24
Fig. 3.2.26 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C).. 3-25
Fig. 3.2.27 CMOS large current output port N-channel side characteristics (Ta = 25 °C) . 3-25
Fig. 3.2.28 Definition of A-D conversion accuracy .................................................................. 3-26
Fig. 3.2.29 Flash memory version (M38507F8) A-D conversion standard characteristics ..3-28
Fig. 3.2.30 Mask ROM version (M38503M2H, M38503M4H, M38504M6, M38507M8) A-D conversion
standard characteristics............................................................................................. 3-29
Fig. 3.2.31 PROM version (M38504E6) A-D conversion standard characteristics ............. 3-30
Fig. 3.3.1 Sequence of changing relevant register ................................................................. 3-33
Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-34
Fig. 3.3.3 Sequence of setting serial I/O1 control register again ......................................... 3-36
Fig. 3.3.4 Initialization of processor status register ................................................................ 3-40
Fig. 3.3.5 Sequence of PLP instruction execution .................................................................. 3-40
Fig. 3.3.6 Stack memory contents after PHP instruction execution ..................................... 3-40
Fig. 3.3.7 Status flag at decimal calculations .......................................................................... 3-41
Fig. 3.4.1 Selection of packages ............................................................................................... 3-43
Fig. 3.4.2 Wiring for the RESET pin ......................................................................................... 3-43
Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-44
Fig. 3.4.4 Wiring for CNVSS pin..................................................................................................3-44
Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM version, the EPROM version, and the flash
memory version ................................................................................................................... 3-45
Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line ........................................ 3-45
Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-46
Fig. 3.4.8 Wiring for a large current signal line ...................................................................... 3-47
Fig. 3.4.9 Wiring of RESET pin ................................................................................................. 3-47
Fig. 3.4.10 VSS pattern on the underside of an oscillator ...................................................... 3-48
Fig. 3.4.11 Setup for I/O ports ................................................................................................... 3-48
Fig. 3.4.12 Watchdog timer by software ................................................................................... 3-49
Fig. 3.5.1 Structure of Port Pi .................................................................................................... 3-50
Fig. 3.5.2 Structure of Port Pi direction register ..................................................................... 3-50
Fig. 3.5.3 Structure of Serial I/O2 control register 1 .............................................................. 3-51
Fig. 3.5.4 Structure of Serial I/O2 control register 2 .............................................................. 3-51
Fig. 3.5.5 Structure of Serial I/O2 register............................................................................... 3-52
Fig. 3.5.6 Structure of Transmit/Receive buffer register ........................................................ 3-52
Fig. 3.5.7 Structure of Seial I/O1 status register .................................................................... 3-53
Fig. 3.5.8 Structure of Seial I/O1 control register ................................................................... 3-54
Fig. 3.5.9 Structure of UART control register .......................................................................... 3-54
Fig. 3.5.10 Structure of Baud rate generator........................................................................... 3-55
Fig. 3.5.11 Structure of PWM control register ......................................................................... 3-55
Fig. 3.5.12 Structure of PWM prescaler ................................................................................... 3-55
Fig. 3.5.13 Structure of PWM register ...................................................................................... 3-56
Fig. 3.5.14 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-56
Fig. 3.5.15 Structure of Timer 1 ................................................................................................ 3-57
Fig. 3.5.16 Structure of Timer 2 ................................................................................................ 3-57
Fig. 3.5.17 Structure of Timer XY mode register .................................................................... 3-58
Fig. 3.5.18 Structure of Timer X, Timer Y ............................................................................... 3-59
Fig. 3.5.19 Structure of Timer count source selection register ............................................. 3-59
Fig. 3.5.20 Structure of A-D control register............................................................................ 3-60
Fig. 3.5.21 Structure of A-D conversion low-order register ................................................... 3-60
Fig. 3.5.22 Structure of A-D conversion high-order register .................................................. 3-61
3850 Group (Spec. H) User’s Manual
ix
List of figures
Fig. 3.5.23 Structure of MISRG ................................................................................................. 3-61
Fig. 3.5.24 Structure of Watchdog timer control register ....................................................... 3-62
Fig. 3.5.25 Structure of Interrupt edge selection register ...................................................... 3-62
Fig. 3.5.26 Structure of CPU mode register ............................................................................ 3-63
Fig. 3.5.27 Structure of Interrupt request register 1 ............................................................... 3-63
Fig. 3.5.28 Structure of Interrupt request register 2 ............................................................... 3-64
Fig. 3.5.29 Structure of Interrupt control register 1 ................................................................ 3-64
Fig. 3.5.30 Structure of Interrupt control register 2 ................................................................ 3-65
Fig. 3.5.31 Structure of Flash memory control register.......................................................... 3-65
3850 Group (Spec. H) User’s Manual
x
List of tables
List of tables
CHAPTER 1 HARDWARE
Table 1 Pin description ................................................................................................................. 1-4
Table 2 Support products ............................................................................................................. 1-7
Table 3 3850 group (standard) and 3850 group (spec. H) corresponding products............ 1-7
Table 4 Differences between 3850 group (standard) and 3850 group (spec. H)................. 1-7
Table 5 Push and pop instructions of accumulator or processor status register ................. 1-9
Table 6 Set and clear instructions of each bit of processor status register ....................... 1-10
Table 7 I/O port function............................................................................................................. 1-14
Table 8 Interrupt vector addresses and priority ...................................................................... 1-19
Table 9 Summary of M38507F8 (flash memory version) ....................................................... 1-39
Table 10 List of software commands (CPU rewrite mode) .................................................... 1-43
Table 11 Definition of each bit in status register .................................................................... 1-45
Table 12 Relationship between control signals and bus operation modes ......................... 1-49
Table 13 Description of Pin Function (Flash Memory Parallel I/O Mode) ........................... 1-50
Table 14 Software command list (parallel I/O mode) ............................................................. 1-52
Table 15 Status register..............................................................................................................1-54
Table 16 Pin functions (Flash memory standard serial I/O mode) ....................................... 1-57
Table 17 Software commands (Standard serial I/O mode 1) ................................................ 1-59
Table 18 Status register (SRD)..................................................................................................1-64
Table 19 Status register 1 (SRD1) ............................................................................................ 1-64
Table 20 Absolute maximum ratings ......................................................................................... 1-66
Table 21 Flash memory mode Electrical characterstics ......................................................... 1-66
Table 22 Read-only mode........................................................................................................... 1-67
Table 23 Read/Write mode (WE control).................................................................................. 1-67
Table 24 Read/Write mode (CE control) .................................................................................. 1-68
Table 25 Erase and program operation .................................................................................... 1-68
Table 26 Vcc power up/power down timing ............................................................................. 1-68
Table 27 Programming adapter..................................................................................................1-74
Table 28 Relative formula for a reference voltage VREF of A-D converter and Vref ..................... 1-75
Table 29 Change of A-D conversion register during A-D conversion .................................. 1-75
CHAPTER 2 APPLICATION
Table 2.1.1 Termination of unused pins ..................................................................................... 2-3
Table 2.2.1 Interrupt sources, vector addresses and priority of 3850 group ...................... 2-10
Table 2.2.2 List of interrupt bits according to interrupt source ............................................. 2-15
Table 2.3.1 CNTR
0
/CNTR active edge switch bit function .................................................... 2-23
1
Table 2.4.1 Setting examples of Baud rate generator values and transfer bit rate values (1) ... 2-66
Table 2.4.2 Setting examples of Baud rate generator values and transfer bit rate values (2) ... 2-66
Table 2.10.1 State in stop mode ............................................................................................... 2-96
Table 2.10.2 State in wait mode..............................................................................................2-100
Table 2.11.1 Setting of programmers when parallel programming ..................................... 2-105
Table 2.11.2 Connection example to programmer when serial programming (4 wires) ..2-105
3850 Group (Spec. H) User’s Manual
xi
List of tables
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2
Table 3.1.2 Recommended operating conditions (1) ................................................................ 3-3
Table 3.1.3 Recommended operating conditions (2) ................................................................ 3-4
Table 3.1.4 Electrical characteristics (1)..................................................................................... 3-4
Table 3.1.5 Electrical characteristics (2)..................................................................................... 3-5
Table 3.1.6 A-D converter characteristics .................................................................................. 3-6
Table 3.1.7 Timing requirements (1) ........................................................................................... 3-7
Table 3.1.8 Timing requirements (2) ........................................................................................... 3-7
Table 3.1.9 Switching characteristics (1) .................................................................................... 3-8
Table 3.1.10 Switching characteristics (2) .................................................................................. 3-8
Table 3.5.1 CNTR
0
/CNTR active edge switch bit function .................................................... 3-58
1
3850 Group (Spec. H) User’s Manual
xii
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USAGE
DATA REQUIRED FOR MASK ORDERS
DATA REQUIRED FOR One Time
PROM PROGRAMMING ORDERS
ROM PROGRAMMING METHOD
F U N C T I O N A L D E S C R I P T I O N
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
ꢀPower source voltage
DESCRIPTION
The 3850 group (spec. H) is the 8-bit microcomputer based on the
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
740 family core technology.
In middle-speed mode............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
The 3850 group (spec. H) is designed for the household products
and office automation equipment and includes serial I/O functions,
8-bit timer, and A-D converter.
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
ꢀPower dissipation
FEATURES
In high-speed mode ..........................................................34 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode
ꢀBasic machine-language instructions ...................................... 71
ꢀMinimum instruction execution time .................................. 0.5 µs
(at 8 MHz oscillation frequency)
Except M38507F8FP/SP................................................... 60 µW
M38507F8FP/SP ............................................................. 450 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
ꢀOperating temperature range....................................–20 to 85°C
ꢀMemory size
ROM ................................................................... 8K to 32K bytes
RAM ................................................................. 512 to 1024 bytes
ꢀProgrammable input/output ports ............................................ 34
ꢀInterrupts ................................................. 15 sources, 14 vectors
ꢀTimers ............................................................................. 8-bit ꢀ 4
ꢀSerial I/O1 .................... 8-bit ꢀ 1(UART or Clock-synchronized)
ꢀSerial I/O2 ................................... 8-bit ꢀ 1(Clock-synchronized)
ꢀPWM ............................................................................... 8-bit ꢀ 1
ꢀA-D converter ............................................... 10-bit ꢀ 5 channels
ꢀWatchdog timer ............................................................ 16-bit ꢀ 1
ꢀClock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
APPLICATION
Office automation equipment, FA equipment, Household products,
Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3
P3
P3
P3
P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
V
CC
V
REF
AVSS
/PWM
2/SCMP2
/INT
/INT
/CNTR
/SRDY1
/SCLK1
/TxD
3
4
P4
4
/INT
/INT
P4
P4
P4
/CNTR
P2
P2
P2
3
5
P4
3
2
1
0
1
6
P00/SIN2
1
7
P0
P0
P0
1
2
3
/SOUT2
/SCLK2
/SRDY2
0
8
P2
7
0
9
6
10
11
12
13
14
15
16
17
18
19
20
21
P0
P0
P0
P0
4
5
5
6
7
4
/RxD
P2
P2
3
2
P1
P1
P1
P1
P1
P1
P1
P1
0
1
2
3
4
5
6
7
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
0
1
2
3
4
5
6
7
)
)
)
)
)
)
)
)
CNVSS
P2 /XCIN
P2 /XCOUT
V
PP
1
0
RESET
X
IN
OUT
SS
X
V
: Flash memory version
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
Fig. 1 M38503MXH-XXXFP/SP pin configuration
3850 Group (Spec. H) User’s Manual
1-2
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
3850 Group (Spec. H) User’s Manual
1-3
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description
Functions
Pin
VCC, VSS
CNVSS
Name
Function except a port function
Power source
CNVSS input
Reset input
Clock input
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
XOUT
Clock output
•8-bit CMOS I/O port.
P00/SIN2
• Serial I/O2 function pin
•I/O direction register allows each pin to be individually
programmed as either input or output.
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
I/O port P0
I/O port P1
•CMOS compatible input level.
•CMOS 3-state output structure.
•P10 to P17 (8 bits) are enabled to output large current for LED drive.
P10–P17
P20/XCOUT
P21/XCIN
P22
• Sub-clock generating circuit I/O
pins (connect a resonator)
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
I/O port P2
•CMOS compatible input level.
P23
•P20, P21, P24 to P27: CMOS3-state output structure.
•P22, P23: N-channel open-drain structure.
• Serial I/O1 function pin
P24/RxD
P25/TxD
P26/SCLK1
• Serial I/O1 function pin/
Timer X function pin
P27/CNTR0/
SRDY1
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
• A-D converter input pin
P30/AN0–
P34/AN4
I/O port P3
I/O port P4
•CMOS 3-state output structure.
P40/CNTR1
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
• Timer Y function pin
• Interrupt input pins
P41/INT0
P42/INT1
•CMOS 3-state output structure.
• Interrupt input pin
• SCMP2 output pin
• Interrupt input pin
• PWM output pin
P43/INT2/SCMP2
P44/INT3/PWM
3850 Group (Spec. H) User’s Manual
1-4
HARDWARE
PART NUMBERING
PART NUMBERING
M3850 3
M
4
H– XXX SP
Product name
Package type
SP : 42P4B
FP : 42P2R-A/E
SS : 42S1B-A
ROM number
Omitted in One Time PROM version shipped in blank,
EPROM version, and flash memory version.
– : standard
Omitted in One Time PROM version shipped in blank, EPROM
version, and flash memory version.
H–: Partial specification changed version
ROM/PROM/Flash memory size
: 4096 bytes
: 8192 bytes
9 : 36864 bytes
A : 40960 bytes
1
2
3
4
5
6
7
8
: 12288 bytes B : 45056 bytes
: 16384 bytes C : 49152 bytes
: 20480 bytes D : 53248 bytes
: 24576 bytes E : 57344 bytes
: 28672 bytes F : 61440 bytes
: 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they
cannot be used as a user’s ROM area.
However, they can be programmed or erased in the flash memory version,
so that the users can use them.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
F : Flash memory version
RAM size
5: 768 bytes
6: 896 bytes
7: 1024 bytes
8: 1536 bytes
9: 2048 bytes
0
1
2
3
4
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
Fig. 3 Part numbering
3850 Group (Spec. H) User’s Manual
1-5
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
RAM size ...............................................................512 to 1 K bytes
Packages
42P4B ......................................... 42-pin shrink plastic-molded DIP
42P2R-A/E ......................................... 42-pin plastic-molded SSOP
42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version)
Renesas Technology plans to expand the 3850 group (spec. H) as
follows.
Memory Type
Support for mask ROM, One Time PROM, and flash memory ver-
sions.
Memory Size
Flash memory size ......................................................... 32 K bytes
One Time PROM size..................................................... 24 K bytes
Mask ROM size ................................................... 8 K to 32 K bytes
Memory Expansion Plan
ROM size (bytes)
As of Aug. 2003
ROM
exteranal
Mass production
32K
M38507M8/F8
28K
Mass production
24K
20K
16K
12K
8K
M38504M6/E6
Mass production
M38503M4H
Mass production
M38503M2H
384
512
640
768
896
1024
1152
1280
1408
1536
2048
RAM size (bytes)
Fig. 4 Memory expansion plan
3850 Group (Spec. H) User’s Manual
1-6
HARDWARE
GROUP EXPANSION
Currently support products are listed below.
As of Aug. 2003
Table 2 Support products
ROM size (bytes)
Product name
RAM size (bytes)
Package
Remarks
ROM size for User in (
)
M38503M2H-XXXSP
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
42P4B
42P2R-A/E
424P4B
8192
(8062)
512
512
M38503M2H-XXXFP
M38503M4H-XXXSP
M38503M4H-XXXFP
M38504M6-XXXSP
M38504E6-XXXSP
M38504E6SP
16384
(16254)
42P2R-A/E
One Time PROM version
One Time PROM version (blank)
EPROM version
424P4B
42S1B-A
24576
(24446)
M38504E6SS
640
M38504M6-XXXFP
M38504E6-XXXFP
M38504E6FP
Mask ROM version
One Time PROM version
One Time PROM version (blank)
42P2R-A/E
M38507M8-XXXSP
M38507M8-XXXFP
M38507F8SP
42P4B
42P2R-A/E
424P4B
Mask ROM version
32768
(32638)
1024
Flash memory version
M38507F8FP
42P2R-A/E
Table 3 3850 group (standard) and 3850 group (spec. H)
corresponding products
3850 group (standard) (Note)
M38503M2-XXXFP/SP
M38503M4-XXXFP/SP
M38503E4-XXXFP/SP
M38503E4FP/SP
3850 group (spec. H)
M38503M2H-XXXFP/SP
M38503M4H-XXXFP/SP
M38504M6-XXXFP/SP
M38504E6-XXXFP/SP
M38504E6FP/SP
Note: The user who is using the 3850 Group (standard) needs to
refer to not this manual but “3850/3851 Group User’s
Manual”.
M38503E4SS
M38504E6SS
M38507M8-XXXFP/SP
M38507F8FP/SP
Table 4 Differences between 3850 group (standard) and 3850 group (spec. H)
3850 group (spec. H)
2: Serial I/O1 (UART or Clock-synchronized)
Serial I/O2 (Clock-synchronized)
Serviceable in low-speed mode
8: P10–P17
3850 group (standard)
Serial I/O
1: Serial I/O (UART or Clock-synchronized)
A-D converter
Unserviceable in low-speed mode
5: P13–P17
Large current port
Notes on differences between 3850 group (standard) and 3850 group (spec. H)
(1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage VI = –0.3 to Vcc +0.3 V
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group
(spec. H).
(3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after reset.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
3850 Group (Spec. H) User’s Manual
1-7
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3850 group (spec. H) uses the standard 740 Family instruc-
tion set. Refer to the table of 740 Family addressing modes and
machine instructions or the 740 Family Software Manual for de-
tails on the instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b0
b0
b0
b0
b7
X
Index register X
Index register Y
b7
Y
b7
S
Stack pointer
b15
b7
PCH
PC
L
Program counter
b7
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
3850 Group (Spec. H) User’s Manual
1-8
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
Push return address
on stack
Push contents of processor
status register on stack
Interrupt
Service Routine
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
(PS)
M (S)
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
POP return
address
from stack
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 5 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
3850 Group (Spec. H) User’s Manual
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
Table 6 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
_
N flag
_
_
_
_
_
_
Set instruction
SEC
CLC
SEI
CLI
SED
CLD
SET
CLT
Clear instruction
CLV
3850 Group (Spec. H) User’s Manual
1-10
HARDWARE
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
CPUM : address 003B16
1
(
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 : Not available
1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0
0
1
1
0 : φ = f(XIN)/2 (high-speed mode)
1 : φ = f(XIN)/8 (middle-speed mode)
0 : φ = f(XCIN)/2 (low-speed mode)
1 : Not available
Fig. 7 Structure of CPU mode register
3850 Group (Spec. H) User’s Manual
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains
control registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special
RAM is used for data storage and for stack area of subroutine
page addressing mode.
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
Address
XXXX16
RAM size
(bytes)
000016
SFR area
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
010016
RAM
XXXX16
Not used
0FF016
SFR area (Note)
0FFF16
Not used
YYYY16
ROM area
Reserved ROM area
(128 bytes)
Address
YYYY16
Address
ZZZZ16
ROM size
(bytes)
ZZZZ16
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Note: Flash memory version only
Fig. 8 Memory map diagram
3850 Group (Spec. H) User’s Manual
1-12
HARDWARE
FUNCTIONAL DESCRIPTION
Port P0 (P0)
Prescaler 12 (PRE12)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
Port P0 direction register (P0D)
Port P1 (P1)
Timer 1 (T1)
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Timer Y (TY)
Port P3 direction register (P3D)
Port P4 (P4)
Timer count source selection register (TCSS)
Port P4 direction register (P4D)
002B16 Reserved ✽
Reserved ✽
002C16
002D16 Reserved ✽
002E16 Reserved ✽
002F16 Reserved ✽
003016 Reserved ✽
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Reserved ✽
Reserved ✽
001316 Reserved ✽
001416 Reserved ✽
A-D control register (ADCON)
A-D conversion low-order register (ADL)
A-D conversion high-order register (ADH)
Serial I/O2 control register 1 (SIO2CON1)
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
Reserved ✽
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Baud rate generator (BRG)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Flash memory control register (FMCR)
0FFE16
✽ Reserved : Do not write any data to this addresses, because these areas are reserved.
Fig. 9 Memory map of special function register (SFR)
3850 Group (Spec. H) User’s Manual
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 7 I/O port function
Input/Output
Related SFRs
Name
I/O Structure
Non-Port Function
Pin
P00/SIN2
Ref.No.
(1)
(2)
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
P10–P17
P20/XCOUT
P21/XCIN
P22
Serial I/O2 control register
Serial I/O2 function I/O
Port P0
(3)
CMOS compatible
input level
CMOS 3-state output
(4)
(5)
Port P1
Port P2
Sub-clock generating
circuit
(6)
(7)
CPU mode register
CMOS compatible
input level
N-channel open-drain
output
P23
(8)
P24/RxD
(9)
P25/TxD
Input/output,
individual
bits
(10)
(11)
Serial I/O1 function I/O
Serial I/O1 control register
P26/SCLK1
P27/CNTR0/SRDY1
Serial I/O1 function I/O
Timer X function I/O
Serial I/O1 control register
Timer XY mode register
(12)
P30/AN0–
P34/AN4
(13)
(14)
(15)
A-D control register
Port P3
Port P4
A-D conversion input
Timer Y function I/O
External interrupt input
CMOS compatible
input level
CMOS 3-state output
Timer XY mode register
P40/CNTR1
P41/INT0
Interrupt edge selection
register
P42/INT1
P43/INT2/SCMP2
Interrupt edge selection
register
External interrupt input
SCMP2 output
(16)
(17)
Serial I/O2 control register
P44/INT3/PWM
Interrupt edge selection
register
PWM control register
External interrupt input
PWM output
Note: When bits 5 to 7 of Ports P3 and P4 are read out, the contents are undefined.
3850 Group (Spec. H) User’s Manual
1-14
HARDWARE
FUNCTIONAL DESCRIPTION
(2) Port P0
1
(1) Port P0
0
P01/SOUT2 P-channel output disable bit
Direction
register
Serial I/O2 Transmit completion signal
Serial I/O2 port selection bit
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 input
Serial I/O2 output
(3) Port P0
2
(4) Port P0
3
P02
/SCLK2 P-channel output disable bit
S
RDY2 output enable bit
Serial I/O2 synchronous
clock selection bit
Direction
register
Serial I/O2 port selection bit
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2 external clock input
(6) Port P2
0
(5) Ports P04-P07,P1
Port XC switch bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Oscillator
Port P2
1
(7) Port P2
1
Port XC switch bit
Port X
C
switch bit
(8) Ports P22,P2
3
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Sub-clock generating circuit input
Fig. 10 Port block diagram (1)
3850 Group (Spec. H) User’s Manual
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
(10) Port P2
5
(9) Port P2
4
Serial I/O1 enable bit
Receive enable bit
P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
Serial I/O1 input
Serial I/O1 output
Pulse output mode
(11) Port P2
6
(12) Port P2
7
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
S
RDY1 output enable bit
Direction
Direction
register
register
Data bus
Port latch
Data bus
Port latch
Pulse output mode
Serial ready output
Serial I/O1 clock output
Timer output
External clock input
CNTR
0
interrupt
input
(13) Ports P30-P34
(14) Port P4
0
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
Pulse output mode
Timer output
A-D converter input
Analog input pin selection bit
CNTR
1
interrupt
input
(16) Port P4
3
Serial I/O2 I/O
comparison signal control bit
(15) Ports P41,P42
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 I/O
Interrupt input
comparison signal output
Interrupt input
Fig. 11 Port block diagram (2)
3850 Group (Spec. H) User’s Manual
1-16
HARDWARE
FUNCTIONAL DESCRIPTION
(17) Port P4
4
PWM output enable bit
Direction
register
Port latch
Data bus
PWM output
Interrupt input
Fig. 12 Port block diagram (3)
3850 Group (Spec. H) User’s Manual
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
INTERRUPTS
Interrupts occur by 15 sources among 15 sources: six external,
✽Notes
When setting the followings, the interrupt request bit may be set to
eight internal, and one software.
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer XY mode register (address 2316)
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address 3A16)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
✽Set the corresponding interrupt enable bit to “0” (disabled).
✽Set the interrupt edge select bit or the interrupt source select bit
to “1”.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
✽Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
When several interrupts occur at the same time, the interrupts are
received according to priority.
✽Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
3850 Group (Spec. H) User’s Manual
1-18
HARDWARE
FUNCTIONAL DESCRIPTION
Table 8 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Remarks
Interrupt Source
Reset (Note 2)
INT0
Priority
1
High
Low
FFFD16
FFFC16
At reset
Non-maskable
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
2
3
4
FFFB16
FFF916
FFF716
FFFA16
FFF816
FFF616
Reserved
Reserved
INT1
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT1 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT2 input
5
6
FFF516
FFF316
FFF416
FFF216
INT2
At detection of either rising or External interrupt
falling edge of INT3 input/ At (active edge selectable)
completion of serial I/O2 data Switch by Serial I/O2/INT3
INT3/ Serial I/O2
reception/transmission
interrupt source bit
FFF116
FFEF16
FFED16
7
8
FFF016
FFEE16
FFEC16
FFEA16
FFE816
Reserved
Timer X
Timer Y
Timer 1
Timer 2
Reserved
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
9
STP release timer underflow
10
11
FFEB16
FFE916
At completion of serial I/O1 data
reception
Serial I/O1
reception
12
13
FFE716
FFE516
FFE616
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
Serial I/O1
transmission
FFE416
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR0 input
CNTR0
CNTR1
14
15
FFE216
FFE016
FFE316
FFE116
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR1 input
16
17
FFDF16
FFDD16
FFDE16
FFDC16
A-D converter
At completion of A-D conversion
At BRK instruction execution
BRK instruction
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3850 Group (Spec. H) User’s Manual
1-19
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
0
active edge selection bit
1
2
3
active edge selection bit
active edge selection bit
active edge selection bit
0 : Falling edge active
1 : Rising edge active
Serial I/O2 / INT3 interrupt source bit
0 : INT interrupt selected
3
1 : Serial I/O2 interrupt selected
Not used (returns “0” when read)
b7
b0
b7
b0
Interrupt request register 2
Interrupt request register 1
(IREQ2 : address 003D16
)
(IREQ1 : address 003C16
)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O1 reception interrupt request bit
Serial I/O1 transmit interrupt request bit
INT
Reserved
INT
INT
INT
Reserved
Timer X interrupt request bit
Timer Y interrupt request bit
0 interrupt request bit
1
2
3
interrupt request bit
interrupt request bit
/ Serial I/O2 interrupt request bit
CNTR
CNTR
0
interrupt request bit
interrupt request bit
1
AD converter interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 2
Interrupt control register 1
(ICON2 : address 003F16
)
(ICON1 : address 003E16
)
INT interrupt enable bit
0
Timer 1 interrupt enable bit
Reserved(Do not write “1” to this bit.)
Timer 2 interrupt enable bit
INT
INT
INT
1
2
3
interrupt enable bit
interrupt enable bit
/ Serial I/O2 interrupt enable bit
Serial I/O1 reception interrupt enable bit
Serial I/O1 transmit interrupt enable bit
CNTR
CNTR
0
interrupt enable bit
interrupt enable bit
Reserved(Do not write “1” to this bit.)
Timer X interrupt enable bit
Timer Y interrupt enable bit
1
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
3850 Group (Spec. H) User’s Manual
1-20
HARDWARE
FUNCTIONAL DESCRIPTION
TIMERS
Timer 1 and Timer 2
The 3850 group (spec. H) has four timers: timer X, timer Y, timer
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The out-
put of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.
1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an un-
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source
selection bit.
b0
b7
(2) Pulse Output Mode
Timer XY mode register
(TM : address 002316
)
The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach “0016”, the
signal output from the CNTR0 (or CNTR1) pin is inverted. If the
CNTR0 (or CNTR1) active edge selection bit is “0”, output begins
at “ H”.
Timer X operating mode bit
b1b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P27 ( or port P40) direction register to out-
put mode.
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer X count stop bit
0: Count start
1: Count stop
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
Timer Y operating mode bits
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts the selected signals by the count source selection bit while
the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) ac-
tive edge selection bit is “1”, the timer counts it while the CNTR0
(or CNTR1) pin is at “L”.
Timer Y count stop bit
0: Count start
1: Count stop
Fig. 15 Structure of timer XY mode register
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.
b0
b7
Timer count source selection register
(TCSS : address 002816
)
Timer X count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
✽Note
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer 12 count source selection bit
When switching the count source by the timer 12, X and Y count
source bit, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XCIN
)
Not used (returns “0” when read)
Therefore, select the timer count source before set the value to
the prescaler and the timer.
Fig. 16 Structure of timer count source selection register
3850 Group (Spec. H) User’s Manual
1-21
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
Prescaler X latch (8)
Timer X latch (8)
Timer X (8)
f(XIN)/2
Pulse width
measurement
mode
(f(XCIN)/2 at low-speed mode)
Timer mode
Pulse output mode
Timer X count source selection bit
To timer X interrupt
request bit
Prescaler X (8)
Timer X count stop bit
CNTR0 active edge
Event
counter
mode
selection bit
P27/CNTR0
“0”
To CNTR
0 interrupt
request bit
“1”
CNTR0 active
“1”
“0”
edge selection
bit
Q
Q
T
Toggle flip-flop
R
Timer X latch write pulse
Pulse output mode
Port P2
latch
7
Port P2
direction register
7
Pulse output mode
Data bus
f(XIN)/16
Prescaler Y latch (8)
Timer Y latch (8)
Timer Y (8)
(f(XCIN)/16 at low-speed mode)
f(XIN)/2
Pulse width
measure-
(f(XCIN)/2 at low-speed mode)
Timer mode
ment mode Pulse output mode
Timer Y count source selection bit
To timer Y interrupt
request bit
Prescaler Y (8)
CNTR1 active edge
selection bit
Event
counter
mode
Timer Y count stop bit
P40/CNTR1
“0”
To CNTR
1 interrupt
request bit
“1”
CNTR1 active
“1”
“0”
edge selection
bit
Q
Q
T
Toggle flip-flop
R
Port
P40latch
Timer Y latch write pulse
Pulse output mode
Port P4
0
direction register
Pulse output mode
Data bus
Prescaler 12 latch (8)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
To timer 2 interrupt
request bit
f(XCIN
)
Timer 12 count source selection bit
To timer 1 interrupt
request bit
Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2
3850 Group (Spec. H) User’s Manual
1-22
HARDWARE
FUNCTIONAL DESCRIPTION
SERIAL I/O
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O1 mode selection bit of the serial I/O1 control register (bit
6 of address 001A16) to “1”.
●SERIAL I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Data bus
Serial I/O1 control register
Address 001A16
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive shift register
Receive interrupt request (RI)
P24/RXD
Shift clock
Clock control circuit
P26/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
X
IN
Baud rate generator
Address 001C16
1/4
Clock control circuit
Falling-edge detector
P27/SRDY1
F/F
Shift clock
Transmit shift register
Transmit buffer register
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P25/TXD
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 18 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
D
0
0
D
1
1
D
2
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
D
D
D
D
D
D
D
D
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has
ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 19 Operation of clock synchronous serial I/O1 function
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 001816
Serial I/O1 control register Address 001A16
Receive buffer register
OE
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Character length selection bit
P24
/R
XD
ST detector
7 bits
8 bits
Receive shift register
1/16
UART control register
PE FE
SP detector
Address 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P26/SCLK1
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
XIN
Baud rate generator
Address 001C16
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P25/TXD
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O1 status register
Data bus
Fig. 20 Block diagram of UART serial I/O1
3850 Group (Spec. H) User’s Manual
1-24
HARDWARE
FUNCTIONAL DESCRIPTION
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
TBE=0
D1
TBE=1
TSC=1
Serial output TXD
ST
SP
D0
ST
D0
D1
SP
1 start bit
Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
D1
RBF=1
SP
RBF=1
SP
ST
Serial input RXD
D0
D1
ST
D0
Notes
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 21 Operation of UART serial I/O1 function
[Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is al-
ways valid and sets the output structure of the P25/TXD pin.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
3850 Group (Spec. H) User’s Manual
1-25
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
b0
b7
Serial I/O1 status register
(SIOSTS : address 001916
Serial I/O1 control register
(SIOCON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN
1: f(XIN)/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
)
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O1 is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
0: P2
1: P2
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin
pin operates as SRDY1 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
b7
b0
UART control register
(UARTCON : address 001B16
(pins P2
1: Serial I/O1 enabled
(pins P2 to P2 operate as serial I/O1 pins)
4 to P27 operate as ordinary I/O pins)
)
4
7
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P25/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 22 Structure of serial I/O1 control registers
✽Notes on serial I/O
When setting the transmit enable bit of serial I/O1 to “1”, the serial
I/O1 transmit interrupt request bit is automatically set to “1”. When
not requiring the interrupt occurrence synchronized with the trans-
mission enalbed, take the following sequence.
✽Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
✽Set the transmit enable bit to “1”.
✽Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
✽Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
✽SERIAL I/O2
The serial I/O2 can be operated only as the clock synchronous type.
b7
b0
Serial I/O2 control register 1
As a synchronous clock for serial transfer, either internal clock or
external clock can be selected by the serial I/O2 synchronous clock
selection bit (b6) of serial I/O2 control register 1.
(SIO2CON1 : address 001516
)
Internal synchronous clock selection bits
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
0: f(XIN)/128 f(XCIN)/128 in low-speed mode)
1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
The internal clock incorporates a dedicated divider and permits se-
lecting 6 types of clock by the internal synchronous clock selection
bits (b2, b1, b0) of serial I/O2 control register 1.
Regarding SOUT2 and SCLK2 being output pins, either CMOS output
format or N-channel open-drain output format can be selected by the
P01/SOUT2, P02/SCLK2 P-channel output disable bit (b7) of
serial I/O2 control register 1.
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 output pin
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 001716). After comple-
tion of data transfer, the level of the SOUT2 pin goes to high imped-
ance automatically but bit 7 of the serial I/O2 control register 2 is not
set to “1” automatically.
S
0: P0
1: P0
RDY2 output enable bit
3
pin is normal I/O pin
3
pin is SRDY2 output pin
Transfer direction selection bit
0: LSB first
1: MSB first
When the external clock has been selected, the contents of the serial
I/O2 register is continuously sifted while transfer clocks are input.
Accordingly, control the clock externally. Note that the SOUT2 pin does
not go to high impedance after completion of data transfer.
To cause the SOUT2 pin to go to high impedance in the case where
the external clock is selected, set bit 7 of the serial I/O2 control reg-
ister 2 to “1” when SCLK2 is “H” after completion of data transfer. After
the next data transfer is started (the transfer clock falls), bit 7 of the
serial I/O2 control register 2 is set to “0” and the SOUT2 pin is put into
the active state.
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P01/SOUT2 ,P02/SCLK2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode )
b7
b0
Serial I/O2 control register 2
(SIO2CON2 : address 001616
)
Optional transfer bits
b2 b1 b0
Regardless of the internal clock to external clock, the interrupt re-
quest bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored in
the serial I/O2 register becomes a fractional number of bits close to
MSB if the transfer direction selection bit of serial I/O2 control regis-
ter 1 is LSB first, or a fractional number of bits close to LSB if the said
bit is MSB first. For the remaining bits, the previously received data
is shifted.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0: 1 bit
1: 2 bit
0: 3 bit
1: 4 bit
0: 5 bit
1: 6 bit
0: 7 bit
1: 8 bit
Not used ( returns "0" when read)
Serial I/O2 I/O comparison signal control bit
At transmit operation using the clock synchronous serial I/O, the SCMP2
signal can be output by comparing the state of the transmit pin SOUT2
with the state of the receive pin SIN2 in synchronization with a rise of
the transfer clock. If the output level of the SOUT2 pin is equal to the
input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H”
is output. At this time, an INT2 interrupt request can also be gener-
ated. Select a valid edge by bit 2 of the interrupt edge selection reg-
ister (address 003A16).
0: P43 I/O
1: SCMP2 output
S
OUT2 pin control bit (P0
0: Output active
1: Output high-impedance
1)
Fig. 23 Structure of Serial I/O2 control registers 1, 2
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 /
SIO2CON2)] 001516, 001616
The serial I/O2 control registers 1 and 2 are containing various se-
lection bits for serial I/O2 control as shown in Figure 23.
3850 Group (Spec. H) User’s Manual
1-27
HARDWARE
FUNCTIONAL DESCRIPTION
Internal synchronous
clock selection bits
1/8
X
CIN
1/16
1/32
Data bus
“10”
Main clock division ratio
selection bits (Note)
1/64
“00”
“01”
1/128
1/256
XIN
P0
3
latch
Serial I/O2 synchronous
clock selection bit
“0”
“1”
P03/SRDY2
SRDY2
Synchronous circuit
“1”
SRDY2 output enable bit
“0”
External clock
P02 latch
“0”
Optional transfer bits (3)
Serial I/O counter 2 (3)
P02
/SCLK2
Serial I/O2
“1”
interrupt request
Serial I/O2 port selection bit
P01 latch
“0”
P0
1
/SOUT2
/SIN2
“1”
Serial I/O2 port selection bit
Serial I/O2 register (8)
P00
P43 latch
“0”
D
P43
/SCMP2/INT2
Q
“1”
Serial I/O2 I/O comparison
signal control bit
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 24 Block diagram of Serial I/O2
Transfer clock (Note 1)
Write-in signal to
serial I/O2 register
(Note 2)
.
Serial I/O2 output SOUT2
Serial I/O2 input SIN2
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes
1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected
by setting bits 0 to 2 of serial I/O2 control register 1.
2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.
Fig. 25 Timing chart of Serial I/O2
3850 Group (Spec. H) User’s Manual
1-28
HARDWARE
FUNCTIONAL DESCRIPTION
SCMP2
SCLK2
SOUT2
SIN2
Judgement of I/O data comparison
Fig. 26 SCMP2 output operation
3850 Group (Spec. H) User’s Manual
1-29
HARDWARE
FUNCTIONAL DESCRIPTION
PULSE WIDTH MODULATION (PWM)
The 3850 group (spec. H) has a PWM function with an 8-bit
resolution, based on a signal that is the clock input XIN or that
clock input divided by 2.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Data Setting
The PWM output pin also functions as port P44. Set the PWM
period by the PWM prescaler, and set the “H” term of output pulse
by the PWM register.
31.875 ✽ m ✽ (n+1)
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ✽ (n+1) / f(XIN)
µs
255
PWM output
= 31.875 ✽ (n+1) µs
(when f(XIN) = 8 MHz,count source selection bit = “0”)
Output pulse “H” term = PWM period ✽ m / 255
= 0.125 ✽ (n+1) ✽ m µs
T = [31.875 ✽ (n+1)] µs
m: Contents of PWM register
(when f(XIN) = 8 MHz,count source selection bit = “0”)
n : Contents of PWM prescaler
T : PWM period (when f(XIN) = 8 MHz,count source
selection bit = “0”)
Fig. 27 Timing of PWM period
Data bus
PWM
prescaler pre-latch
PWM
register pre-latch
Transfer control circuit
PWM
prescaler latch
PWM
register latch
Count source
selection bit
Port P44
“0”
XIN
PWM prescaler
PWM register
(XCIN at low-speed mode)
“1”
1/2
Port P44 latch
PWM enable bit
Fig. 28 Block diagram of PWM function
3850 Group (Spec. H) User’s Manual
1-30
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
PWM control register
(PWMCON : address 001D16
)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN) (f(XCIN) at low-speed mode)
1: f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Not used (return “0” when read)
Fig. 29 Structure of PWM control register
B
T
C
T2
=
A
B
C
PWM output
T
T
T2
PWM register
write signal
(Changes “H” term from “A” to “B”.)
PWM prescaler
write signal
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 30 PWM output timing when PWM register or PWM prescaler is changed
✽Note
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L” level output is as follows:
n+1
sec
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
(Count source selection bit = 1, where n is the value set in the prescaler)
2 • f(XIN)
n+1
f(XIN)
3850 Group (Spec. H) User’s Manual
1-31
HARDWARE
FUNCTIONAL DESCRIPTION
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
003516, 003616
b7
b0
AD control register
(ADCON : address 003416)
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion.
Analog input pin selection bits
b2 b1 b0
0 0 0: P30/AN0
0 0 1: P31/AN1
0 1 0: P32/AN2
0 1 1: P33/AN3
1 0 0: P34/AN4
[AD Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Not used (returns “0” when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
Fig. 31 Structure of AD control register
AVSS and VREF into 1024 and outputs the divided voltages.
Channel Selector
10-bit reading
(Read address 003616 before 003516
The channel selector selects one of ports P30/AN0 to P34/AN4 and
)
inputs the voltage to the comparator.
b0
b7
(Address 003616
(Address 003516
)
b9 b8
Comparator and Control Circuit
b7
b0
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
)
b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 003616 become “0”
at reading.
Note that because the comparator consists of a capacitor cou-
pling, set f(XIN) to 500 kHz or more during an A-D conversion.
When the A-D converter is operated at low-speed mode, f(XIN)
and f(XCIN) do not have the lower limit of frequency, because of
the A-D converter has a built-in self-oscillation circuit.
8-bit reading (Read only address 003516
)
b0
b7
(Address 003516
)
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 32 Structure of A-D conversion registers
Data bus
b7
3
b0
AD control register
(Address 003416
)
A-D interrupt request
A-D control circuit
P30/AN0
P3
P3
P3
1
2
3
/AN
/AN
/AN
1
2
3
A-D conversion high-order register (Address 003616
)
)
Comparator
(Address 003516
A-D conversion low-order register
10
P34/AN4
Resistor ladder
V
REF AVSS
Fig. 33 Block diagram of A-D converter
3850 Group (Spec. H) User’s Manual
1-32
HARDWARE
FUNCTIONAL DESCRIPTION
WATCHDOG TIMER
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) per-
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at f(XIN)
= 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case
is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN)
= 32 kHz frequency. This bit is cleared to “0” after reset.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 003916) after reset, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watch-
dog timer H.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003916) may be
started before an underflow. When the watchdog timer control reg-
ister (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watch-
dog timer H count source selection bit are read.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, once the STP
instruction is executed, an internal reset occurs. When this bit is
set to “1”, it cannot be rewritten to “0” by program. This bit is
cleared to “0” after reset.
●Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L is set to “FF16”.
“FF16” is set when
watchdog timer
Data bus
“FF16” is set when
watchdog timer
control register is
XCIN
control register is
written to.
“0”
“10”
written to.
Watchdog timer L (8)
Main clock division
ratio selection bits
(Note)
Watchdog timer H (8)
1/16
“1”
“00”
“01”
Watchdog timer H count
source selection bit
XIN
STP instruction disable bit
STP instruction
Reset
circuit
Internal reset
RESET
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 34 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 003916
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 35 Structure of Watchdog timer control register
3850 Group (Spec. H) User’s Manual
1-33
HARDWARE
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an “L”
level for 20 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage must be between 2.7 V
and 5.5 V, and the oscillation must be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.54 V for VCC of 2.7 V.
Poweron
(Note)
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage; Vcc = 2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 36 Reset circuit example
X
IN
φ
RESET
RESETOUT
Address
AD
H,L
?
?
?
?
FFFC
FFFD
Reset address from the vector table.
AD
H
Data
?
?
?
AD
L
?
SYNC
X
IN: 8 to 13 clock cycles
Notes1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 2 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
3: All signals except XIN and RESET are internals.
Fig. 37 Reset sequence
3850 Group (Spec. H) User’s Manual
1-34
HARDWARE
FUNCTIONAL DESCRIPTION
Address
Register contents
Address Register contents
(1)
Port P0 (P0)
(34)MISRG
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
001516
001616
001716
0016
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
0016
0 0 1 1 1 1 1 1
0016
(2)
Port P0 direction register (P0D)
Port P1 (P1)
(35)Watchdog timer control register (WDTCON)
(36)Interrupt edge selection register (INTEDGE)
(37)CPU mode register (CPUM)
(38)Interrupt request register 1 (IREQ1)
(39)Interrupt request register 2 (IREQ2)
(40)Interrupt control register 1 (ICON1)
(41)Interrupt control register 2 (ICON2)
(42)Processor status register
(43)Program counter
0016
(3)
0016
(4)
Port P1 direction register (P1D)
Port P2 (P2)
0016
0 1 0 0 1 0 0 0
0016
(5)
0016
(6)
Port P2 direction register (P2D)
Port P3 (P3)
0016
0016
0016
(7)
0016
(8)
Port P3 direction register (P3D)
Port P4 (P4)
0016
0016
0016
(9)
X X X X X 1 X X
FFFD16 contents
FFFC16 contents
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
Port P4 direction register (P4D)
Serial I/O2 control register 1 (SIO2CON1)
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
0016
(PCH)
0016
(PCL)
0 0 0 0 0 1 1 1
X X X X X X X X
001816 X X X X X X X X
1 0 0 0 0 0 0 0
001916
001A16
001B16
0016
1 1 1 0 0 0 0 0
001C16 X X X X X X X X
001D16
001E16
0016
X X X X X X X X
001F16 X X X X X X X X
Prescaler 12 (PRE12)
002016
002116
002216
002316
002416
002516
002616
002716
002816
003416
FF16
Timer 1 (T1)
0116
Timer 2 (T2)
0016
Timer XY mode register (TM)
Prescaler X (PREX)
0016
FF16
Timer X (TX)
FF16
FF16
Prescaler Y (PREY)
Timer Y (TY)
FF16
Timer count source selection register (TCSS)
A-D control register (ADCON)
A-D conversion low-order register (ADL)
A-D conversion high-order register (ADH)
0016
0 0 0 1 0 0 0 0
003516 X X X X X X X X
003616
0 0 0 0 0 0 X X
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Fig. 38 Internal status at reset
3850 Group (Spec. H) User’s Manual
1-35
HARDWARE
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
(2) Wait mode
The 3850 group (spec. H) has two built-in oscillation circuits. An
oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT (XCIN and XCOUT). Use the circuit constants
in accordance with the resonator manufacturer’s recommended
values. No external resistor is needed between XIN and XOUT
since a feed-back resistor exists on-chip. However, an external
feed-back resistor is needed between XCIN and XCOUT.
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before ex-
ecuting of the STP or WIT instruction.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruc-
tion.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
set is released, this mode is selected.
■Note
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
■Note
If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately af-
ter power on and at returning from the stop mode. When switching
the mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3•f(XCIN).
XCIN XCOUT
XIN
XOUT
Rf
Rd
COUT
CCIN
CCOUT
CIN
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
Fig. 39 Ceramic resonator circuit
The sub-clock XCIN-XCOUT oscillating circuit can not directly input
clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
XCIN
X
COUT
XIN
XOUT
Oscillation Control
(1) Stop mode
Open
Rf
Rd
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillation stops. When the oscillation
stabilizing time set after STP instruction released bit is “0”, the
prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the
oscillation stabilizing time set after STP instruction released bit is
“1”, set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
Either XIN or XCIN divided by 16 is input to the prescaler 12 as
count source. Oscillator restarts when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU (remains
at “H”) until timer 1 underflows. The internal clock φ is supplied for
the first time, when timer 1 underflows. This ensures time for the
clock oscillation using the ceramic resonators to be stabilized.
When the oscillator is restarted by reset, apply “L” level to the
RESET pin until the oscillation is stable since a wait time will not
be generated.
External oscillation
circuit
C
CIN
CCOUT
Vcc
Vss
Fig. 40 External clock input circuit
3850 Group (Spec. H) User’s Manual
1-36
HARDWARE
FUNCTIONAL DESCRIPTION
[MISRG (MISRG)] 003816
b0
b7
MISRG
(MISRG : address 003816
MISRG consists of three control bits (bits 1 to 3) for middle-speed
mode automatic switch and one control bit (bit 0) for oscillation
stabilizing time set after STP instruction released.
)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
By setting the middle-speed mode automatic switch start bit to “1”
while operating in the low-speed mode and setting the middle-
speed mode automatic switch set bit to “1”, XIN oscillation
automatically starts and the mode is automatically switched to the
middle-speed mode.
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
Note: When the mode is automatically switched from the low-speed mode to
the middle-speed mode, the value of CPU mode register (address 003B16
changes.
)
Fig. 41 Structure of MISRG
X
COUT
XCIN
“0”
“1”
Port X
C
switch bit
X
OUT
X
IN
Main clock division ratio
selection bits (Note 1)
Low-speed mode
1/2
High-speed or
middle-speed
mode
Prescaler 12
FF16
Timer 1
0116
1/4
1/2
Reset or
STP instruction
(Note 2)
(Note 3)
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Reset
Q
S
R
S
R
Q
Q
S
R
STP instruction
STP instruction
WIT instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
2: At reset, f(XIN)/16 is supplied to the prescaler 12 as the count source. When executing the STP instruction, the count
source supplied before the STP instruction execution is supplied.
3: When bit 0 of MISRG is “0”, “FF16” is set to the prescaler 12 and “0116” is set to Timer 1. When bit 0 of MISRG is “1”,
set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and Timer 1.
Fig. 42 System clock generating circuit block diagram (Single-chip mode)
3850 Group (Spec. H) User’s Manual
1-37
HARDWARE
FUNCTIONAL DESCRIPTION
Reset
High-speed mode
(f(φ) = 4 MHz)
Middle-speed mode
(f(φ) = 1 MHz)
CM6
“1” ←→ “0”
CM
CM
CM
CM
7
= 0
= 0
CM
CM
CM
CM
7
6
5
4
= 0
= 1
6
5
4
= 0 (8 MHz oscillating)
= 0 (32 kHz stopped)
= 0 (8 MHz oscillating)
= 0 (32 kHz stopped)
C
”
M
0
“
“
4
0
”
M4
”
C
→
←→
M
←
0
“
C
“
6
1
”
”
1
“
M6
”
“
1
→
←→
←
C
”
1
“
“
0
”
Middle-speed mode
(f(φ) = 1 MHz)
High-speed mode
(f(φ) = 4 MHz)
CM6
“1” ←→ “0”
CM
CM
CM
CM
7
= 0
= 1
CM
7
6
5
4
= 0
= 0
6
5
4
CM
CM
CM
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
C
M
“
7
0
”
C
←
M
→
“
6
1
”
“
1
←
”
→
“
0
”
Middle-speed mode
automatic switch set bit = “1”
Low-speed mode
(f(φ)=16 kHz)
CM
CM
CM
CM
7
= 1
= 0
6
5
4
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16
Middle-speed mode automatic
switch start bit = “1”
)
CM4 : Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
Low-speed mode
(f(φ)=16 kHz)
CM
CM
CM
CM
7
6
5
4
= 1
= 0
0
0
1
1
0 : φ = f(XIN)/2 ( High-speed mode)
1 : φ = f(XIN)/8 (Middle-speed mode)
0 : φ = f(XCIN)/2 (Low-speed mode)
1 : Not available
= 1 (8 MHz stopped)
= 1 (32 kHz oscillating)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed
mode.
5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed.
(1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”.
(2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
7: When switching to the middle-speed mode by the middle-speed mode automatic switch bit of MISRG, the waiting time set by the middle-
speed mode automatic switch wait time set bit is generated automatically, and switch to the middle-speed mode.
8 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 43 State transitions of system clock
3850 Group (Spec. H) User’s Manual
1-38
HARDWARE
FUNCTIONAL DESCRIPTION
FLASH MEMORY VERSION
Summary
Table 9 shows the summary of the M38507F8 (flash memory version).
Table 9 Summary of M38507F8 (flash memory version)
Item
Specification
Vcc = 2.7–5.5 V (Note 1)
Vcc = 2.7–3.6 V (Note 2)
Power source voltage
Program/Erase VPP voltage
Flash memory mode
4.5–5.5 V, f(XIN) = 8 MHz
3 modes (Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode)
User ROM area
Boot ROM area
1 block (32 Kbytes)
Erase block division
1 block (4 Kbytes) (Note 3)
Program method
Erase method
Byte program
Batch erasing
Program/Erase control method
Number of commands
Program/Erase control by software command
6 commands
Number of program/Erase times
ROM code protection
100 times
Available in parallel I/O mode, and standard serial I/O mode
Notes 1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation.
2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation.
3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory.
This Boot ROM area can be rewritten in only parallel I/O mode.
3850 Group (Spec. H) User’s Manual
1-39
HARDWARE
FUNCTIONAL DESCRIPTION
Flash Memory Mode
The flash memory of the M38507F8 is divided into User ROM area
and Boot ROM area as shown in Figure 44.
The M38507F8 (flash memory version) has an internal new DINOR
(DIvided bit line NOR) flash memory that can be rewritten with a
single power source when VCC is 5 V, and 2 power sources when
VCC is 3.3-5.0 V.
In addition to the ordinary user ROM area to store a microcomputer
operation control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a stan-
dard serial I/O mode control program stored in it when shipped from
the factory. However, the user can write a rewrite control program in
this area that suits the user’s application system. This Boot ROM
area can be rewritten in only parallel I/O mode.
For this flash memory , three flash memory modes are available in
which to read, program, and erase: parallel I/O and standard serial I/
O modes in which the flash memory can be manipulated using a
programmer and a CPU rewrite mode in which the flash memory can
be manipulated by the Central Processing Unit (CPU). Each mode is
detailed in the pages to follow.
Parallel I/O mode
800016
F00016
4 kbyte
FFFF16
Block 1 : 32 kbyte
FFFF16
User ROM area
Boot ROM area
BSEL = 0
BSEL = 1
CPU rewrite mode, standard serial I/O mode
800016
F00016
4 kbyte
FFFF16
Block 1 : 32 kbyte
Flash memory
start address
Product name
FFFF16
User ROM area
Boot ROM area
M38507F8
800016
User area / Boot area selection bit = 0
User area / Boot area selection bit = 1
Notes 1: The Boot ROM area can be rewritten in only parallel
input/output mode. (Access to any other areas is inhibited.)
2: To specify a block, use the maximum address in the block.
Fig. 44 Block diagram of flash memory version
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
CPU Rewrite Mode
Bit 2 is the CPU rewrite mode entry flag. This bit can be read to
check whether the CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit of
the internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
rewrite mode select bit is “1”, writing “1” for this bit resets the control
circuit. To release the reset, it is necessary to set this bit to “0”.
Bit 4 is the User area/Boot area selection bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In boot mode, this bit is set “1” automatically.
Operation of this bit must be in RAM area.
In CPU rewrite mode, the on-chip flash memory can be operated on
(read, program, or erase) under control of the Central Processing
Unit (CPU).
In CPU rewrite mode, only the user ROM area shown in Figure 44
can be rewritten; the Boot ROM area cannot be rewritten. Make sure
the program and block erase commands are issued for only the user
ROM area and each block area.
The control program for CPU rewrite mode can be stored in either
user ROM or Boot ROM area. In the CPU rewrite mode, because the
flash memory cannot be read from the CPU, the rewrite control pro-
gram must be transferred to internal RAM area before it can be ex-
ecuted.
Figure 46 shows a flowchart for setting/releasing the CPU rewrite
mode.
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting
the flash memory in CPU rewrite mode.
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the
user ROM or Boot ROM area in parallel I/O mode beforehand. (If the
control program is written into the Boot ROM area, the standard se-
rial I/O mode becomes unusable.)
(1) Operation speed
During CPU rewrite mode, set the internal clock frequency 4MHz
or less using the main clock division ratio selection bits (bit 6, 7 at
003B16).
See Figure 44 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer is
reset with pulling CNVSS pin low. In this case, the CPU starts operat-
ing using the control program in the user ROM area.
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode be-
cause they refer to the internal data of the flash memory.
(4) Watchdog timer
When the microcomputer is reset by pulling the P41/INT0 pin high,
the CNVSS pin high, the CPU starts operating using the control pro-
gram in the Boot ROM area (program start address is FFFC16,
FFFD16 fixation). This mode is called the “boot” mode.
In case of the watchdog timer has been running already, the in-
ternal reset generated by watchdog timer underflow does not
happen, because of watchdog timer is always clearing during
program or erase operation.
Block Address
Block addresses refer to the maximum address of each block. These
addresses are used in the block erase command. In case of the
M38507F8, it has only one block.
(5) Reset
Reset is always valid. In case of CNVSS = H when reset is re-
leased, boot mode is active. So the program starts from the ad-
dress contained in address FFFC16 and FFFD16 in boot ROM
area.
Outline Performance (CPU Rewrite Mode)
In the CPU rewrite mode, the CPU erases, programs and reads the
internal flash memory as instructed by software commands. This re-
write control program must be transferred to internal RAM before it
can be executed.
The CPU rewrite mode is accessed by applying 5V ± 10% to the
CNVSS pin and writing “1” for the CPU rewrite mode select bit (bit 1
in address 0FFE16). Software commands are accepted once the
mode is accessed.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or in
error can be verified by reading the status register.
Figure 45 shows the flash memory control register.
Bit 0 is the RY/_B__Y__ status flag used exclusively to read the operating
status of the flash memory. During programming and erase opera-
tions, it is “0”. Otherwise, it is “1”.
Bit 1 is the CPU rewrite mode select bit. When this bit is set to “1” and
5V ± 10% are applied to the CNVSS pin, the M38507F8 accesses the
CPU rewrite mode. Software commands are accepted once the
mode is accessed. In CPU rewrite mode, the CPU becomes unable
to access the internal flash memory directly. Therefore, use the con-
trol program in RAM for write to bit 1. To set this bit to “1”, it is neces-
sary to write “0” and then write “1” in succession. The bit can be set
to “0” by only writing a “0”.
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HARDWARE
FUNCTIONAL DESCRIPTION
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMCR
Address
0FFE16
When reset
XXX00001
R W
Bit symbol
FMCR0
Bit name
Function
0: Busy (being written or erased)
1: Ready
RY/BY status flag
0: Normal mode
CPU rewrite mode
select bit (Note 2)
FMCR1
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
0: Normal mode
CPU rewrite mode
entry flag
FMCR2
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
Flash memory reset bit 0: Normal operation
(Note 3)
FMCR3
FMCR4
1: Reset
0: User ROM area
1: Boot ROM area
User area / Boot area
selection bit
Nothing is assigned.
When write, set “0”. When read, values are indeterminate.
Notes 1: The contents of the flash memory control register after reset is released become
“XXX00001”.
2: For this bit to be set to “1”, write “0” and then “1” to bit 1 in succession.
3: In order to perform flash memory reset by this bit setup, while the CPU rewriting
mode selection bit is set to “1”, write “1” to bit 3. In order to reset release, write “0”
to bit 3 in the next.
Fig. 45 Flash memory control registers
Program in ROM
Program in RAM
*1
Start
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)
Single-chip mode, or boot mode
Set CPU mode register (Note 1)
Check the CPU rewrite mode entry flag
Transfer CPU rewrite mode control
program to internal RAM
Using software command execute erase,
program, or other operation
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 2)
*1
Write “0” to CPU rewrite mode select bit
End
Notes 1: Set bit 6, 7 (Main clock division ratio selection bits ) at CPU mode register (003B16).
2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Fig. 46 CPU rewrite mode set/reset flowchart
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HARDWARE
FUNCTIONAL DESCRIPTION
Software Commands
Read Status Register Command (7016)
Table 10 lists the software commands.
When the command code “7016” is written in the first bus cycle, the
content of the status register is read out at the data bus (D0–D7) by a
read in the second bus cycle.
After setting the CPU rewrite mode select bit to “1”, write a software
command to specify an erase or program operation.
The content of each software command is explained below.
The status register is explained in the next section.
Read Array Command (FF16)
Clear Status Register Command (5016)
The read array mode is entered by writing the command code “FF16”
in the first bus cycle. When an address to be read is input in one of
the bus cycles that follow, the content of the specified address is
read out at the data bus (D0–D7).
This command is used to clear the bits SR1,SR4 and SR5 of the
status register after they have been set. These bits indicate that op-
eration has ended in an error. To use this command, write the com-
mand code “5016” in the first bus cycle.
The read array mode is retained intact until another command is writ-
ten. And after power on and after recover from deep power down
mode, this mode is selected also.
Table 10 List of software commands (CPU rewrite mode)
First bus cycle
Address
Second bus cycle
Mode Address
Command
Cycle number
Data
(D to D
Data
to D7)
Mode
0
7
)
(D0
(Note 4)
Read array
1
2
1
2
2
2
Write
Write
Write
Write
Write
Write
X
FF16
7016
5016
4016
2016
2016
Read status register
Clear status register
Program
X
X
X
X
X
Read
X
SRD (Note 1)
(Note 2)
WA (Note 2)
X
Write
Write
Write
WD
Erase all block
2016
D016
BA (Note 3)
Block erase
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address (Enter the maximum address of each block.)
4: X denotes a given address in the user ROM area .
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HARDWARE
FUNCTIONAL DESCRIPTION
Program Command (4016)
Block Erase Command (2016/D016)
Program operation starts when the command code “4016” is written
in the first bus cycle. Then, if the address and data to program are
written in the 2nd bus cycle, program operation (data programming
and verification) will start.
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” in the second bus cycle that
follows to the block address of a flash memory block, the system
initiates a block erase (erase and erase verify) operation.
Whether the write operation is completed can be confirmed by read-
Whether the block erase operation is completed can be confirmed
_____
____
ing the status register or the RY/BY status flag. When the program
starts, the read status register mode is accessed automatically and
the content of the status register is read into the data bus (D0–D7).
The status register bit 7 (SR7) is set to “0” at the same time the write
operation starts and is returned to “1” upon completion of the write
operation. In this case, the read status register mode remains active
by reading the status register or the RY/BY status flag. At the same
time the block erase operation starts, the read status register mode
is automatically entered, so the content of the status register can be
read out. The status register bit 7 (SR7) is set to “0” at the same time
the block erase operation starts and is returned to “1” upon comple-
tion of the block erase operation. In this case, the read status regis-
ter mode remains active until the read array command (FF16) is writ-
until the read array command (FF16) is written.
____
The RY/BY status flag is “0” during write operation and “1” when the
write operation is completed as is the status register bit 7.
At program end, program results can be checked by reading the sta-
tus register.
ten.
____
The RY/BY status flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status register
bit 7.
After the block erase operation is completed, the status register can
be read out to know the result of the block erase operation. For de-
Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that fol-
lows, the system starts erase all blocks( erase and erase verify).
Start
Whether the erase all blocks command is terminated can be con-
____
firmed by reading the status register or the RY/BY status flag. When
the erase all blocks operation starts, the read status register mode is
accessed automatically and the content of the status register can be
read out. The status register bit 7 (SR7) is set to “0” at the same time
the erase operation starts and is returned to “1” upon completion of
the erase operation. In this case, the read status register mode re-
Write 2016
2016:Erase all blocks
D016:Block erase
2016/D016
Block address
Write
Status register
read
mains active until the read array command (FF16) is written.
____
The RY/BY status flag is “0” during erase operation and “1” when the
erase operation is completed as is the status register bit 7.
At erase all blocks end, erase results can be checked by reading the
status register. For details, refer to the section where the status reg-
ister is detailed.
NO
NO
SR7=1?
or
RY/BY=1?
YES
SR5=0?
Erase error
Start
YES
Erase completed
Write 4016
Fig. 48 Erase flowchart
Write address
Write
Write data
Status register
read
SR7=1?
or
NO
RY/BY=1?
YES
NO
Program
error
SR4=0?
YES
Program
completed
Fig. 47 Program flowchart
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HARDWARE
FUNCTIONAL DESCRIPTION
Sequencer status (SR7)
After power-on, and after recover from deep power down mode, the
Status Register
The status register shows the operating state of the flash memory
and whether erase operations and programs ended successfully or
in error. It can be read in the following ways.
sequencer status is set to “1”(ready).
The sequencer status indicates the operating status of the device.
This status bit is set to “0” (busy) during write or erase operation and
is set to “1” upon completion of these operations.
(1) By reading an arbitrary address from the user ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the user ROM area in the
period from when the program starts or erase operation starts to
when the read array command (FF16) is input
Erase status (SR5)
The erase status informs the operating status of erase operation to
the CPU. When an erase error occurs, it is set to “1”.
The erase status is reset to “0” when cleared.
Table 11 shows the status register.
Also, the status register can be cleared in the following way.
(1) By writing the clear status register command (5016)
(2) In the deep power down mode
Program status (SR4)
The program status informs the operating status of write operation to
the CPU. When a write error occurs, it is set to “1”.
The program status is reset to “0” when cleared.
(3) In the power supply off state
After a reset, the status register is set to “8016”.
Each bit in this register is explained below.
If “1” is written for any of the SR5 or SR4 bits, the program, erase all
blocks, and block erase commands are not accepted. Before ex-
ecuting these commands, execute the clear status register com-
mand (5016) and clear the status register.
Also, any commands are not correct, both SR5 and SR4 are set to
“1”.
Table 11 Definition of each bit in status register
Definition
Each bit of
SRD0 bits
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
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HARDWARE
FUNCTIONAL DESCRIPTION
Full Status Check
By performing full status check, it is possible to know the execution
tus check flowchart and the action to be taken when each error oc-
curs.
results of erase and program operations. Figure 49 shows a full sta-
Read status register
YES
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
SR4=1 and SR5
=1 ?
operation one more time after confirming that the
command is entered correctly.
NO
NO
Should a block erase error occur, the block in error
cannot be used.
Block erase error
Program error
SR5=0?
YES
SR4=0?
YES
NO
Should a program error occur, the block in error
cannot be used.
End (block erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 49 Full status check flowchart and remedial procedure for errors
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HARDWARE
FUNCTIONAL DESCRIPTION
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of the flash memory version from being read
out or rewritten easily, the device incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check function
for use in standard serial I/O mode.
If one of the pair of ROM code protect bits is set to “0”, ROM code
protect is turned on, so that the contents of the flash memory ver-
sion are protected against readout and modification. ROM code
protect is implemented in two levels. If level 2 is selected, the flash
memory is protected even against readout by a shipment inspection
LSI tester, etc. When an attempt is made to select both level 1 and
level 2, level 2 is selected by default.
ROM code protect function
If both of the two ROM code protect reset bits are set to “00”, ROM
code protect is turned off, so that the contents of the flash memory
version can be read out or modified. Once ROM code protect is
turned on, the contents of the ROM code protect reset bits cannot
be modified in parallel I/O mode. Use the serial I/O or some other
mode to rewrite the contents of the ROM code protect reset bits.
The ROM code protect function is the function inhibit reading out or
modifying the contents of the flash memory version by using the
ROM code protect control address (FFDB16) during parallel I/O
mode. Figure 50 shows the ROM code protect control address
(FFDB16). (This address exists in the user ROM area.)
ROM code protect control address
Symbol
ROMCP
Address
FFDB16
When reset
FF16
b7 b6 b5 b4 b3 b2 b1 b0
1 1
Bit symbol
Function
Always set this bit to “1”
b3 b2
Bit name
Reserved bit
ROM code protect level
2 set bit (Note 1, 2)
ROMCP2
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
b5 b4
ROM code protect reset
bit (Note 3)
ROMCR
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
b7 b6
ROM code protect level
ROMCP1
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
1 set bit (Note 1)
Notes 1: When ROM code protect is turned on, the on-chip flash memory is protected against
readout or modification in parallel input/output mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, since these bits cannot be changed in parallel
input/output mode, they need to be rewritten in serial input/output mode or some other
mode.
Fig. 50 ROM code protect control address
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HARDWARE
FUNCTIONAL DESCRIPTION
ID Code Check Function
Use this function in standard serial I/O mode. When the contents of
the flash memory are not blank, the ID code sent from the peripheral
unit is compared with the ID code written in the flash memory to see
if they match. If the ID codes do not match, the commands sent from
the peripheral unit are not accepted. The ID code consists of 8-bit
data, the areas of which are FFD416 to FFDA16. Write a program
which has had the ID code preset at these addresses to the flash
memory.
Address
FFD416
FFD516
FFD616
FFD716
ID1
ID2
ID3
ID4
ID5
ID6
FFD816
FFD916
FFDA16
FFDB16
ID7
ROM cord Protect control
Interrupt vector area
Fig. 51 ID code store addresses
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HARDWARE
FUNCTIONAL DESCRIPTION
Parallel I/O Mode
The parallel I/O mode is entered by making connections shown in
Bus Operation Modes
Read
_____
_____
Figure 52 and then turning the Vcc power supply on.
The Read mode is entered by pulling the OE pin low when the CE
_____
_____
pin is low and the WE and RP pins are high. There are two read
modes: array, and status register, which are selected by software
command input. In read mode, the data corresponding to each soft-
ware command entered is output from the data I/O pins D0–D7. The
read array mode is automatically selected when the device is pow-
ered on or after it exits deep power down mode.
Address
The user ROM is only one block as shown in Figure 44. The block
address referred to in this data sheet is the maximum address value
of each block.
User ROM and Boot ROM Areas
Output Disable
The output disable mode is entered by pulling the _C__E__ pin low and the
In parallel I/O mode, the user ROM and boot ROM areas shown in
Figure 44 can be rewritten. The BSEL pin is used to choose between
these two areas. The user ROM area is selected by pulling the BSEL
input low; the boot ROM area is selected by driving the BSEL input high.
Both areas of flash memory can be operated on in the same way.
Program and block erase operations can be performed in the user
ROM area. The user ROM area and its block is shown in Figure 44.
The user ROM area is 32 Kbytes in size. In parallel I/O mode, it is
located at addresses 800016 through FFFF16. The boot ROM area is
4 Kbytes in size. In parallel I/O mode, it is located at addresses
F00016 through FFFF16. Make sure program and block erase opera-
tions are always performed within this address range. (Access to
any location outside this address range is prohibited.)
_____ _____
WE, OE, and _R__P__ pins high. Also, the data I/O pins are placed in the
high-impedance state.
Standby
_____
_____
The standby mode is entered by driving the CE pin high when the RP
pin is high. Also, the data I/O pins are placed in the high-impedance
_____
state. However, if the CE pin is set high during erase or program
operation, the internal control circuit does not halt immediately and
normal power consumption is required until the operation under way
is completed.
Write
The write mode is entered by pulling the WE pin low when the C___E__ pin
_____
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial
I/O mode control program stored in it when shipped from the
Renesas factory. Therefore, using the device in standard serial in-
put/output mode, you do not need to write to the boot ROM area.
_____
_____
is low and the OE and RP pins are high. In this mode, the device
accepts the software commands or write data entered from the data
I/O pins. A program, erase, or some other operation is initiated de-
pending on the content of the software command entered here. The
input data such as address and software command is latched at the
_____
_____
Functional Outline (Parallel I/O Mode)
rising edge of WE or CE whichever occurs earlier.
In parallel I/O mode, bus operation modes—Read, Output Disable,
Standby, Write, and Deep Power Down—are selected by the status
Deep Power Down
_____ _____ _____
_____
_____
of the CE, OE, WE, and RP input pins.
The deep power down is entered by pulling the RP pin low. Also, the
data I/O pins are placed in the high-impedance state. When the de-
vice is freed from deep power down mode, the read array mode is
The contents of erase, program, and other operations are selected
by writing a software command. The data, status register, etc. in
memory can only be read out by a read after software command
input.
selected and the content of the status register is set to “8016”. If the
_____
RP pin is pulled low during erase or program operation, the opera-
tion under way is canceled and the data in the relevant block be-
comes invalid.
Program and erase operations are controlled using software com-
mands.
The following explains about bus operation modes, software com-
mands, and status register.
Table 12 Relationship between control signals and bus operation modes
_____
_____
______
_____
Pin name
Mode
Read
CE
OE
WE
RP
D0 to D7
Data output
Array
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
VIL
VIL
VIH
X
VIH
VIH
VIH
X
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
Status register
Status register data output
High impedance
Output disabled
Stand by
High impedance
Program
VIH
VIH
VIH
X
VIL
VIL
VIL
X
Command/data input
Command input
Write
Erase all blocks
Block erase
Command input
Deep power down
High impedance
Note : X can be VIL or VIH.
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HARDWARE
FUNCTIONAL DESCRIPTION
Table 13 Description of Pin Function (Flash Memory Parallel I/O Mode)
I/O
Pin name
CC,VSS
Signal name
Power supply input
CNVSS
Function
V
Apply 5.0 ± 0.5 V to the Vcc pin and 0 V to the Vss pin.
I
I
CNVSS
RESET
Connect this pin to Vcc
.
Reset input pin. When reset is held low, more than 20 cycles of clock are
required at the XIN pin.
Reset input
Connect a ceramic or crystal resonator between the XIN and XOUT pins.
When entering an externally drived clock, enter it from XIN and leave XOUT
open.
X
X
IN
Clock input
I
OUT
Clock output
O
AVSS
REF
Analog power supply input
Reference voltage input
Connect AVss to Vss.
I
V
Input AD reference voltage or keep open.
P0
0
0
to P0
to P1
to P2
7
7
7
Data I/O D
0
to D
7
I/O These are data D
0
–D
7
input/output pins.
–A15 input pins.
–A input pins.
P1
Address input A
8
to A15
to A
I
These are address A
These are address A
8
0
P2
0
0
I
I
7
Address input A
BSEL input
0
7
P3
This is a BSEL input pin.
P3
1
2
I
I
This is a RP input pin.
This is a WE input pin.
RP input
WE input
P3
P3
3
4
I
I
CE input
This is a CE input pin.
This is a OE input pin.
P3
OE input
P4
0
1
This is a RY/BY output pin.
Enter low signals to this pin.
RY/BY output
O
I
P4
Input P4
1
P42
to P4
4
Input P4
I
Input “H” or “L” or keep open.
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
V
CC
SS
V
BSEL
P3
P3
P3
P3
P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
V
CC
1
2
3
4
42
41
40
39
38
37
36
35
34
RP
WE
CE
OE
VREF
AVSS
/PWM
/SCMP2
/INT
/INT
/CNTR
/SRDY1
/SCLK1
/TxD
/RxD
P2
P2
P4
P4
4
/INT
3
3/INT
2
5
D
0
P4
P4
2
1
0
1
P0
P0
P0
P0
P0
P0
P0
P0
P1
P1
P1
P1
P1
P1
P1
P1
0/SIN2
6
D1
1
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
/SOUT2
/SCLK2
/SRDY2
7
RY/BY
D
2
P4
/CNTR
P2
/SCL
/SDA
0
8
A
A
A
A
A
A
7
6
5
P2
7
0
D3
D4
D5
D6
D7
A8
A9
9
6
10
11
12
13
14
15
16
17
18
19
20
21
33
P2
P2
5
2
32
31
4
3
2
4
2
3
2
30
29
28
27
26
25
24
23
22
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
0
1
2
3
4
5
6
7
)
)
)
)
)
)
)
)
CNVSS
P2
P2
A
1
1
/XCIN
A10
A11
A12
A13
A14
A15
A
0
0
/XCOUT
RESET
X
IN
OUT
SS
✽
X
V
Mode setup method
✽ Connect oscillator circuit
Signal
Value
CNVSS
V
CC
SS
SS
V
P4
1/INT0
V
RESET
Fig. 52 Pin connection diagram in parallel I/O mode
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
Read Status Register Command (7016)
Software Commands
When the command code “7016” is written in the first bus cycle, the
content of the status register is output from the data I/O pins (D0–D7)
by a read in the second bus cycle. Since the content of the status
Table 14 lists the software commands. By entering a software com-
mand from the data I/O pins (D0–D7) in Write mode, specify the con-
tent of the operation, such as erase or program operation, to be per-
formed.
_____
_____
_____
_____
register is updated at the falling edge of OE or CE, the OE or CE
signal must be asserted each time the status is read. The status
register is explained in the next section.
The following explains the content of each software command.
Read Array Command (FF16)
Clear Status Register Command (5016)
This command is used to clear the bits SR4,SR5 of the status regis-
ter after they have been set. These bits indicate that operation has
ended in an error. To use this command, write the command code
“5016” in the first bus cycle.
The read array mode is entered by writing the command code “FF16”
in the first bus cycle. When an address to be read is input in one of
the bus cycles that follow, the content of the specified address is
output from the data I/O pins (D0–D7).
The read array mode is retained intact until another command is writ-
ten.
The read array mode is also selected automatically when the device
is powered on and after it exits deep power down mode.
Table 14 Software command list (parallel I/O mode)
Second bus cycle
First bus cycle
Address
Command
Read array
Cycle number
Data
Data
Mode
Mode
Read
Address
X
(D0 to D7)
(D0 to D7)
1
2
1
2
2
2
Write
Write
Write
Write
Write
Write
X(Note 4)
FF16
7016
5016
4016
2016
2016
Read status register
Clear status register
Program
X
X
X
X
X
SRD(Note 1)
Write
Write
Write
WA(Note 2) WD(Note 2)
All block erase
Block erase
X
2016
D016
BA(Note 3)
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address (Enter the maximum address of each block)
4: X denotes a given address in the user ROM area or boot ROM area.
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
____
Program Command (4016)
The RY/BY pin is “L” during erase operation and “H” when the erase
operation is completed as is the status register bit 7.
At erase all blocks end, erase results can be checked by reading the
status register. For details, refer to the section where the status reg-
ister is detailed.
The program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
Whether the write operation is completed can be confirmed by read-
ing the status register or the RY/_B__Y__ signal status. When the program
starts, the read status register mode is accessed automatically and
the content of the status register can be read out from the data bus
(D0–D7). The status register bit 7 (SR7) is set to “0” at the same time
the write operation starts and is returned to “1” upon completion of
the write operation. In this case, the read status register mode re-
Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” in the second bus cycle that
follows to the block address of a flash memory block, the system
initiates a block erase (erase and erase verify) operation.
Whether the block erase operation is completed can be confirmed
____
mains active until the read array command (FF16) is written.
by reading the status register or the RY/BY signal. At the same time
the block erase operation starts, the read status register mode is
automatically entered, so the content of the status register can be
read out. The status register bit 7 (SR7) is set to “0” at the same time
the block erase operation starts and is returned to “1” upon comple-
tion of the block erase operation. In this case, the read status regis-
ter mode remains active until the read array command (FF16) is writ-
____
The RY/BY pin is “L” during write operation and “H” when the write
operation is completed as is the status register bit 7.
At program end, program results can be checked by reading the sta-
tus register.
Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that fol-
lows, the system starts erase all blocks( erase and erase verify).
ten.
____
The RY/BY pin is “L” during block erase operation and “H” when the
block erase operation is completed as is the status register bit 7.
After the block erase operation is completed, the status register can
be read out to know the result of the block erase operation. For de-
tails, refer to the section where the status register is detailed.
Whether the erase all blocks command is terminated can be con-
____
firmed by reading the status register or the RY/BY signal status .
When the erase all blocks operation starts, the read status register
mode is accessed automatically and the content of the status regis-
ter can be read out. The status register bit 7 (SR7) is set to “0” at the
same time the erase operation starts and is returned to “1” upon
completion of the erase operation. In this case, the read status regis-
ter mode remains active until the read array command (FF16) is writ-
ten.
Start
Start
Write 4016
Write 2016
Write address
Write
2016/D016
Block address
2016:Erase all blocks
D016:Block erase
Write
Write data
Status register
read
Status register
read
SR7=1?
NO
NO
NO
SR7=1?
or
RY/BY=1?
or
RY/BY=1?
YES
YES
NO
Program
error
SR4=0?
SR5=0?
YES
Erase error
YES
Program completed
(Read command
FF16 write)
Erase completed
(Read command
FF16 write)
Fig. 53 Page program flowchart
Fig. 54 Block erase flowchart
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
Program Status (SR4)
Status Register
The program status reports the operating status of the write opera-
tion. If a write error occurs, it is set to “1”. When the program status is
cleared, it is set to “0”.
The status register indicates status such as whether an erase opera-
tion or a program ended successfully or in error. It can be read under
the following conditions.
If “1” is written for any of the SR5, SR4 bits, the program erase all
blocks, block erase, commands are not accepted. Before executing
these commands, execute the clear status register command (5016)
and clear the status register.
(1) In the read array mode when the read status register command
(7016) is written and the block address is subsequently read.
(2) In the period from when the program write or auto erase starts to
when the read array command (FF16)
Also, any commands are not correct, both SR5 and SR4 are set to
“1”.
The status register is cleared in the following situations.
(1) By writing the clear status register command (5016)
(2) In the deep power down mode
Full Status Check
Results from executed erase and program operations can be known
by running a full status check. Figure 55 shows a flowchart of the full
status check and explains how to remedy errors which occur.
(3) In the power supply off state
Table 15 gives the definition of each status register bit. When power
is turned on or returning from the deep power down mode, the status
register outputs “8016”.
____
Ready/Busy (RY/BY) pin
____
The RY/BY pin is an output pin (N-chanel open drain output) which,
like the sequencer status (SR7), indicates the operating status of the
flash memory. It is “L” level during auto program or auto erase opera-
Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. When power is turned on or returning from the deep power
down mode, “1” is set for it. This bit is “0” (busy) during the write or
erase operations and becomes “1” when these operations ends.
tions and becomes to the high impedance state (ready state) when
____
these operations end. The RY/BY pin requires an external pull-up.
Erase Status (SR5)
The erase status reports the operating status of the erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
Table 15 Status register
Definition
Each bit of
SRD0 bits
Status name
“1”
“0”
SR7 (D7)
SR6 (D6)
SR5 (D5)
SR4 (D4)
SR3 (D3)
SR2 (D2)
SR1 (D1)
SR0 (D0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Ended in error
Ended successfully
Ended in error
Ended successfully
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
Read status register
YES
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
SR4=1 and SR5
=1 ?
operation one more time after confirming that the
command is entered correctly.
NO
NO
NO
Should a block erase error occur, the block in error
cannot be used.
Block erase error
Program error
SR5=0?
YES
Should a program error occur, the block in error
cannot be used.
SR4=0?
YES
End (block erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, all blocks erase, or block erase
is accepted. Execute the clear status register command (5016) before executing these commands.
Fig. 55 Full status check flowchart and remedial procedure for errors
3850 Group (Spec. H) User’s Manual
1-55
HARDWARE
FUNCTIONAL DESCRIPTION
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the software com-
mands, addresses and data needed to operate (read, program,
erase, etc.) the internal flash memory. This I/O is clock synchronized
serial. This modes require a purpose-specific peripheral unit.
The standard serial I/O mode is different from the parallel I/O mode
in that the CPU controls flash memory rewrite (uses the CPU's re-
write mode), rewrite data input and so forth. The standard serial I/O
mode is started by connecting “H” to the P26 (SCLK1) pin and the
P41(INT0) pin and “H” to the CNVSS pin (when VCC = 4.5 V to 5.5 V,
connect to VCC; when VCC = 2.7 V to 4.5 V, supply 4.5 V to 5.5 V to
Vpp from an external source), and releasing the reset operation. (In
the ordinary command mode, set CNVss pin to “L” level.)
This control program is written in the boot ROM area when the prod-
uct is shipped from Renesas Technology Corp. Accordingly, make
note of the fact that the standard serial I/O mode cannot be used if
the boot ROM area is rewritten in the parallel I/O mode. Figure 56
shows the pin connections for the standard serial I/O mode. Serial
data I/O uses SI/O1 data serially in 8-bit units.
To use standard serial I/O mode. The operation uses the four SI/O1
pins SCLK1, RxD, TxD and SRDY1 (BUSY). The SCLK1 pin is the
transfer clock input pin through which an external transfer clock is
input. The TxD pin is for CMOS output. The SRDY1 (BUSY) pin out-
puts an “L” level when ready for reception and an “H” level when
reception starts.
In the standard serial I/O mode, only the user ROM area indicated in
Figure 44 can be rewritten. The boot ROM cannot.
In the standard serial I/O mode, a 7-byte ID code is used. When
there is data in the flash memory, commands sent from the periph-
eral unit (programmer) are not accepted unless the ID code
matches.
Overview of standard serial I/O mode
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programer, etc.) using 4-wire clock-synchronized serial I/O
(SI/O1).
In reception, software commands, addresses and program data are
synchronized with the rise of the transfer clock that is input to the
SCLK1 pin, and are then input to the MCU via the RxD pin. In trans-
mission, the read data and status are synchronized with the fall of
the transfer clock, and output from the TxD pin.
The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB
first.
When busy, such as during transmission, reception, erasing or pro-
gram execution, the SRDY1 (BUSY) pin is “H” level. Accordingly, al-
ways start the next transfer after the SRDY1 (BUSY) pin is “L” level.
Also, data and status registers in memory can be read after inputting
software commands. Status, such as the operating state of the flash
memory or whether a program or erase operation ended success-
fully or not, can be checked by reading the status register. Here fol-
lowing are explained software commands, status registers, etc.
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
Table 16 Pin functions (Flash memory standard serial I/O mode)
Pin
Name
Power input
I/O
Description
V
CC,VSS
Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin.
Connect to VCC when VCC = 4.5 V to 5.5 V.
Connect to Vpp (=4.5 V to 5.5 V) when VCC = 2.7 V to 4.5 V.
CNVSS
RESET
CNVSS
I
I
Reset input
Reset input pin. While reset is “L” level, a 20 cycle or longer clock
must be input to XIN pin.
Connect a ceramic resonator or crystal oscillator between XIN and
X
IN
OUT
AVSS
REF
Clock input
I
X
OUT pins. To input an externally generated clock, input it to XIN pin
X
Clock output
O
and open XOUT pin.
Analog power supply input
Reference voltage input
Input port P0
Connect AVSS to VSS
.
V
I
I
Enter the reference voltage for AD from this pin.
P0
P1
0
0
to P0
to P1
7
7
Input “H” or “L” level signal or open.
Input port P1
I
Input “H” or “L” level signal or open.
P2
0
to P2
3
Input port P2
RxD input
I
I
Input “H” or “L” level signal or open.
Serial data input pin
P2
P2
P2
P2
4
5
6
7
TxD output
O
I
Serial data output pin
S
CLK1 input
Serial clock input pin
BUSY output
Input port P3
Input port P4
O
I
BUSY signal output pin
P3
0
to P3
4
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” level signal, when reset is released.
P40, P4
2
to P4
4
I
P41
Input P4
1
I
3850 Group (Spec. H) User’s Manual
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HARDWARE
FUNCTIONAL DESCRIPTION
V
CC
SS
V
P3
P3
P3
P3
P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
V
CC
1
2
3
4
42
41
40
39
38
37
36
35
34
VREF
AVSS
/PWM
/SCMP2
/INT
/INT
/CNTR
/SRDY1
/SCLK1
/TxD
/RxD
P2
P2
P4
P4
4
/INT
3
3/INT
2
5
P4
P4
2
1
0
1
P0
P0
P0
P0
P0
P0
P0
P0
P1
P1
P1
P1
P1
P1
P1
P1
0/SIN2
6
P41
1
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
/SOUT2
/SCLK2
/SRDY2
7
P4
/CNTR
P2
P2
P2
0
8
B
USY
P2
7
0
9
SCLK1
6
10
11
12
13
14
15
16
17
18
19
20
21
33
5
TxD
32
31
4
RXD
RxD
3
2
30
29
28
27
26
25
24
23
22
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
0
1
2
3
4
5
6
7
)
)
)
)
)
)
)
)
✽✽2
V
PP
CNVSS
P2 /XCIN
P2 /XCOUT
1
0
RESET
RESET
X
IN
OUT
SS
✽✽1
X
V
Mode setup method
Signal
CNVSS
Value
4.5 to 5.5 V
Notes 1: Connect oscillator circuit
2: Connect to Vcc when Vcc = 4.5 V to 5.5 V.
V
V
CC ✽ 3
CC ✽ 3
P26
1
/SCLK1
Connect to VPP (=4.5 V to 5.5 V) when Vcc = 2.7 V to 4.5 V.
3: It is necessary to apply Vcc only when reset is released.
P4
/INT
0
V
SS → VCC
RESET
Fig. 56 Connection for serial I/O mode
3850 Group (Spec. H) User’s Manual
1-58
HARDWARE
FUNCTIONAL DESCRIPTION
explained here below. Basically, the software commands of the
standard serial I/O mode is as same as that of the parallel I/O mode,
but it is excluded 1 command of block erase, and it is added 3 com-
mand of ID check, download function, version data output function.
Software Commands
Table 17 lists software commands. In the standard serial I/O mode,
erase operations, programs and reading are controlled by transfer-
ring software commands via the RxD pin. Software commands are
Table 17 Software commands (Standard serial I/O mode 1)
1st byte
transfer
When ID is
not verified
Not
acceptable
Control command
Page read
2nd byte 3rd byte 4th byte 5th byte 6th byte
Address Address
(middle) (high)
Data
output
Data
output output
Data
Data
output to
259th byte
FF16
1
2
Address Address
Data
input
Data
input
Data
input
Data input
to 259th
byte
Not
acceptable
4116
Page program
(middle)
(high)
Not
acceptable
Acceptable
A716
7016
5016
F516
D016
3
4
5
6
7
Erase all blocks
Read status register
Clear status register
ID check
SRD
output
SRD1
output
Not
acceptable
Address Address Address
(low)
ID size
ID1
To
To ID7
Acceptable
(middle)
Size
(high)
(high)
Check-
sum
Not
acceptable
Download function
Size (low)
Data required
input number
of times
FA16
FB16
Version
data
output
Version Version Version Version
data
output
Version
data
output to
9th byte
8
Version data output function
data
output
data
output output
data
Acceptable
Notes 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral
unit to the flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted when the flash memory is totally blank.
4: Address high (A16 to A23) must be “0016”.
3850 Group (Spec. H) User’s Manual
1-59
HARDWARE
FUNCTIONAL DESCRIPTION
Page Read Command
(2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the 2nd
and 3rd bytes respectively.
This command reads the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page read
command as explained here following.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes)
specified with addresses A8 to A23 will be output sequentially
from the smallest address first in sync with the fall of the clock.
(1) Transfer the “FF16” command code with the 1st byte.
S
CLK1
RxD
TxD
A
8
to
A16 to
A23
FF16
A
15
data0
data255
S
RDY1(BUSY)
Fig. 57 Timing for page read
Clear Status Register Command
Read Status Register Command
This command clears the bits (SR4–SR5) which are set when the
status register operation ends in error. When the “5016” command
code is sent with the 1st byte, the aforementioned bits are cleared.
When the clear status register operation ends, the SRDY1 (BUSY)
signal changes from the “H” to the “L” level.
This command reads status information. When the “7016” command
code is sent with the 1st byte, the contents of the status register
(SRD) specified with the 2nd byte and the contents of status register
1 (SRD1) specified with the 3rd byte are read.
S
CLK1
RxD
TxD
S
CLK1
RxD
TxD
5016
7016
SRD
output
SRD1
output
S
RDY1(BUSY)
S
RDY1(BUSY)
Fig. 58 Timing for reading the status register
Fig. 59 Timing for clearing the status register
3850 Group (Spec. H) User’s Manual
1-60
HARDWARE
FUNCTIONAL DESCRIPTION
Page Program Command
(3) From the 4th byte onward, as write data (D
0–D7) for the page (256
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page program
command as explained here following.
bytes) specified with addresses A to A23 is input sequentially from
8
the smallest address first, that page is automatically written.
(1) Transfer the “4116” command code with the 1st byte.
When reception setup for the next 256 bytes ends, the SRDY1
(BUSY) signal changes from the “H” to the “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
(2) Transfer addresses A
8 to A15 and A16 to A23 (“0016”) with the 2nd
and 3rd bytes respectively.
SCLK1
A
8
to
A16 to
A23
4116
data0
data255
RxD
TxD
A
15
SRDY1(BUSY)
Fig. 60 Timing for the page program
Erase All Blocks Command
This command erases the content of all blocks. Execute the erase all
(2) Transfer the verify command code “D016” with the 2nd byte. With
the verify command code, the erase operation will start and con-
tinue for all blocks in the flash memory.
blocks command as explained here following.
(1) Transfer the “A716” command code with the 1st byte.
When block erasing ends, the SRDY1 (BUSY) signal changes from
the “H” to the “L” level . The result of the erase operation can be
known by reading the status register.
S
CLK1
RxD
TxD
A716
D016
SRDY1(BUSY)
Fig. 61 Timing for erasing all blocks
3850 Group (Spec. H) User’s Manual
1-61
HARDWARE
FUNCTIONAL DESCRIPTION
Download Command
(4) The program to execute is sent with the 5th byte onward.
This command downloads a program to the RAM for execution. Ex-
ecute the download command as explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is
added to all data sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches, the
downloaded program is executed. The size of the program will vary
according to the internal RAM.
S
CLK1
RxD
TxD
Data size Data size
(low) (high)
Program
data
Check
sum
FA16
Program
data
S
RDY1(BUSY)
Fig. 62 Timing for download
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward.
This data is composed of 8 ASCII code characters.
Version Information Output Command
This command outputs the version information of the control pro-
gram stored in the boot area. Execute the version information output
command as explained here following.
S
CLK1
RxD
TxD
FB16
‘V’
‘E’
‘R’
‘X’
S
RDY1(BUSY)
Fig. 63 Timing for version information output
3850 Group (Spec. H) User’s Manual
1-62
HARDWARE
FUNCTIONAL DESCRIPTION
ID Check
the 1st byte of the ID code with the 2nd, 3rd and 4th bytes re-
spectively.
This command checks the ID code. Execute the boot ID check com-
mand as explained here following.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st
byte of the code.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”) of
S
CLK1
RxD
TxD
F516
D416
FF16
0016
ID size
ID1
ID7
SRDY1(BUSY)
Fig. 64 Timing for the ID check
ID Code
sent from the peripheral units is not accepted. An ID code contains 8
bits of data. Area is, from the 1st byte, addresses FFD416 to
FFDA16. Write a program into the flash memory, which already has
the ID code set for these addresses.
When the flash memory is not blank, the ID code sent from the pe-
ripheral units and the ID code written in the flash memory are com-
pared to see if they match. If the codes do not match, the command
Address
FFD416
ID1
ID2
ID3
ID4
ID5
ID6
ID7
FFD516
FFD616
FFD716
FFD816
FFD916
FFDA16
FFDB16
ROM cord Protect control
Interrupt vector area
Fig. 65 ID code storage addresses
3850 Group (Spec. H) User’s Manual
1-63
HARDWARE
FUNCTIONAL DESCRIPTION
Status Register (SRD)
The sequencer status indicates the operating status of the device.
This status bit is set to “0” (busy) during write or erase operation and
is set to “1” upon completion of these operations.
The status register indicates operating status of the flash memory
and status such as whether an erase operation or a program ended
successfully or in error. It can be read by writing the read status
register command (7016). Also, the status register is cleared by writ-
ing the clear status register command (5016).
Erase Status (SR5)
The erase status reports the operating status of the auto erase op-
eration. If an erase error occurs, it is set to “1”. When the erase sta-
tus is cleared, it is set to “0”.
Table 18 gives the definition of each status register bit. After clearing
the reset, the status register outputs “8016”.
Program Status (SR4)
Sequencer status (SR7)
The program status reports the operating status of the auto write
operation. If a write error occurs, it is set to “1”. When the program
status is cleared, it is set to “0”.
After power-on and recover from deep power down mode, the se-
quencer status is set to “1”(ready).
Table 18 Status register (SRD)
Definition
SRD0 bits
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Status Register 1 (SRD1)
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a
Status register 1 indicates the status of serial communications, re-
sults from ID checks and results from check sum comparisons. It can
be read after the SRD by writing the read status register command
(7016). Also, status register 1 is cleared by writing the clear status
register command (5016).
program is downloaded for execution using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands can-
not be accepted without an ID check.
Table 19 gives the definition of each status register bit. “0016” is out-
put when power is turned on and the flag status is maintained even
after the reset.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the received
data is discarded and the microcomputer returns to the command
wait state.
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to
the RAM or not, using the download function.
Table 19 Status register 1 (SRD1)
Definition
SRD1 bits
Status name
“1”
“0”
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
Boot update completed bit
Reserved
Update completed
Not Update
-
-
-
Reserved
-
Checksum match bit
ID check completed bits
Match
00
Mismatch
Not verified
01
Verification mismatch
Reserved
10
11
Verified
SR9 (bit1)
SR8 (bit0)
Data reception time out
Reserved
Time out
-
Normal operation
-
3850 Group (Spec. H) User’s Manual
1-64
HARDWARE
FUNCTIONAL DESCRIPTION
by running a full status check. Figure 66 shows a flowchart of the full
status check and explains how to remedy errors which occur.
Full Status Check
Results from executed erase and program operations can be known
Read status register
YES
Execute the clear status register command (5016
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
)
Command
sequence error
SR4=1 and SR5
=1 ?
NO
NO
NO
Should a block erase error occur, the block in error
cannot be used.
SR5=0?
YES
Erase error
Should a program error occur, the block in error
cannot be used.
SR4=0?
YES
Program error
End (block erase, program)
Note: When one of SR5 to SR4 is set to “1”, none of the program, erase all blocks
commands is accepted. Execute the clear status register command (5016) before
executing these commands.
Fig. 66 Full status check flowchart and remedial procedure for errors
Example Circuit Application for The Standard
Serial I/O Mode
Figure 67 shows a circuit application for the standard serial I/O
mode. Control pins will vary according to programmer, therefore
see the peripheral unit manual for more information.
P41
SCLK1
Clock input
BUSY output
Data input
SRDY1 (BUSY)
RXD
TXD
Data output
M38507F8
VPP power
source input
CNVss
Notes 1: Control pins and external circuitry will vary according to peripheral unit. For more
information, see the peripheral unit manual.
2: In this example, the Vpp power supply is supplied from an external source (writer). To use
the user’s power source, connect to 4.5 V to 5.5 V.
3: It is necessary to apply Vcc to SCLK pin only when reset is released.
Fig. 67 Example circuit application for the standard serial I/O mode
3850 Group (Spec. H) User’s Manual
1-65
HARDWARE
FUNCTIONAL DESCRIPTION
Flash memory Electrical characteristics
Table 20 Absolute maximum ratings
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 6.5
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF
VI
–0.3 to VCC +0.3
V
VI
VI
VI
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to 5.8
V
V
V
All voltages are based on VSS.
Output transistors are cut off.
–0.3 to VCC +0.3
–0.3 to VCC +0.3
Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
VO
–0.3 to VCC +0.3
V
VO
Output voltage P22, P23
Power dissipation
–0.3 to 5.8
1000 (Note)
25±5
V
mW
°C
Pd
Ta = 25 °C
Topr
Tstg
Operating temperature
Storage temperature
–40 to 125
°C
Note: The rating becomes 300 mW at the 42P2R-A/E package.
Table 21 Flash memory mode Electrical characteristics
o
(Ta = 25 C, VCC = 4.5 to 5.5V unless otherwise noted)
Limits
Symbol
Parameter
Conditions
Unit
Min.
Max.
100
60
Typ.
VPP power source current (read)
VPP power source current (program)
VPP power source current (erase)
“L” input voltage (Note)
VPP = VCC
µA
mA
mA
V
IPP1
IPP2
IPP3
VIL
VPP = VCC
VPP = VCC
30
0
0.8
VCC
5.5
VIH
“H” input voltage (Note)
2.0
4.5
V
VPP power source voltage
V
VPP
Microcomputer mode operation at
VCC = 2.7 to 5.5V
4.5
3.0
5.5
3.6
V
V
VCC
VCC power source voltage
Microcomputer mode operation at
VCC = 2.7 to 3.6V
Note: Input pins for parallel I/O mode.
3850 Group (Spec. H) User’s Manual
1-66
HARDWARE
FUNCTIONAL DESCRIPTION
AC Electrical characteristics
o
(Ta = 25 C, VCC = 4.5 to 5.5V unless otherwise noted)
Table 22 Read-only mode
Limits
Unit
Symbol
Parameter
Min.
200
Typ.
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tRC
Read cycle time
ta (AD)
ta (CE)
ta (OE)
tCLZ
Address access time
100
100
80
_____
CE access time
_____
OE access time
_____
Output enable time (after CE)
0
0
_____
tDF(CE)
tOLZ
Output floating time (after CE)
25
_____
Output enable time (after OE)
_____
tDF(OE)
tPHZ
Output floating time (after OE)
25
_____
Output floating time (after PR)
300
_____ _____
tOH
Output valid time (after CE, OE, address)
0
tOEH
Write recovery time (before read)
200
10
_____
tPS
RP recovery time
Note : Timing measurement condition is showed in Figure 68.
_____
Table 23 Read / Write mode (WE control)
Limits
Typ.
Symbol
Parameter
Unit
Min.
200
Max.
tWC
tAS
Write cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
Address set up time
Address hold time
Data set up time
100
25
100
25
0
tAH
tDS
tDH
Data hold time
_____
tCS
CE set up time
_____
tCH
CE hold time
0
_____
tWP
tWPH
tDAP
tDAE
tWHRL
tPS
WE pulse width
100
50
“H” write pulse width
Program time
25
Erase all blocks time
1.5
RY/_B__Y__ delay time
200
ns
µs
_____
RP recovery time
10
Note : The read timing parameter in the command write operation mode is same as that of the read-only mode.
Typical value is at VCC = 5.0 V, Ta = 25 °C condition.
3850 Group (Spec. H) User’s Manual
1-67
HARDWARE
FUNCTIONAL DESCRIPTION
Flash memory mode Electrical characteristics
o
(Ta = 25 C, VCC = 4.5 to 5.5V unless otherwise noted)
_____
Table 24 Read / Write mode (CE control)
Limits
Typ.
Unit
Symbol
Parameter
Min.
200
Max.
tWC
tAS
Write cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
Address set up time
Address hold time
Data set up time
100
25
100
25
0
tAH
tDS
tDH
Data hold time
______
tWS
tWH
tCEP
tCEPH
tDAP
tDAE
tEHRL
tPS
WE set up time
______
0
WE hold time
_____
100
50
CE pulse width
_____
“H” CE pulse width
Program time
25
Erase all blocks time
1.5
RY/_B__Y__ delay time
200
ns
µs
_____
10
RP recovery time
Note : The read timing parameter in the command write operation mode is same as that of the read-only mode.
Typical value is at VCC = 5.0 V, Ta = 25 °C condition.
Table 25 Erase and program operation
Parameter
Min.
Typ.
1.5
Max.
Unit
s
Erase all blocks time
Block erase time
Program time (1byte)
1.0
25
s
µs
Table 26 VCC power up / power down timing
Symbol
Parameter
Min.
10
Typ.
Max.
Unit
_____
RP = VIH set up time
µs
tVCS
(after rised VCC = VCC min.)
Note : Miserase or miswrite may happen, in case of noise pulse due to the power supply on or off is input to the control pins. Therefore disableing the
write mode is need for prevent from memory data break at the power supply on or off. 10µs (min.) waiting time is need to initiate read or write op-
_____
eration after VCC rises to VCC min. at power supply on. The memory data is protected owing to keep the RP pin VIL level at power supply off. The
_____
RP pin must be kept VIL level for 10µs (min.) after VCC rises to VCC min. at the power supply on. The _R__P__ pin must be kept VIL level until the VCC
_____
_____
falls to the GND level at power supply off. RP pin doesn't have latch mode, so RP pin must be kept VIH level during read, erase and program op-
eration.
3850 Group (Spec. H) User’s Manual
1-68
HARDWARE
FUNCTIONAL DESCRIPTION
Inhibit read / write
Inhibit read / write
Inhibit read / write
5.0V
GND
V
CC
t
VCS
V
IH
RP
CE
VIL
VIH
VIL
t
PS
t
PS
V
IH
WE
VIL
Fig. 68 VCC power up / power down timing
3850 Group (Spec. H) User’s Manual
1-69
HARDWARE
FUNCTIONAL DESCRIPTION
V
IH
IL
IH
IL
IH
IL
IH
Valid address
RC
Address
CE
V
t
V
t
a (AD)
V
t
DF(CE)
DF(OE)
t
a (CE)
V
OE
V
tOEH
t
V
WE
ta (OE)
tOH
VIL
tOLZ
V
OH
tCLZ
HIGH-Z
HIGH-Z
DATA
RP
Valid output
V
OL
tPS
tPHZ
VIH
VIL
Fig. 69 AC wave for read operation
AC electrical characteristics test condition
1.3V
1N914
Input voltage : VIL = 0V, VIH = 5.0V
Input signal rising time, falling time : 10ns
3.3kΩ
Timing measurement
Reference voltage : 1.5V
measurement pin
CL =100pF
Load circuit : 1TTL gate+
CL(100pF )
Fig. 70 AC electrical characteristics test condition for read operation
3850 Group (Spec. H) User’s Manual
1-70
HARDWARE
FUNCTIONAL DESCRIPTION
Read status Write read array
Program
register
command
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
Valid Address
AS
Valid Address
Address
CE
V
t
WC
t
ta(CE)
t
AH
V
V
tCS
tCH
ta(OE)
V
tWP
OE
t
OEH
V
t
WPH
V
WE
V
t
DS
V
DATA
40H
DIN
SRD
FFH
V
tDH
VoH
RY/BY
RP
tWHRL
Vo
L
tPS
V
IH
IL
t
DAP
V
_____
Fig. 71 AC wave for program operation (WE control)
Read status Write read array
register command
Program
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
Valid Address
Valid Address
AS
Address
CE
V
t
WC
t
t
AH
t
a(CE)
a(OE)
V
V
t
V
OE
t
CEP
WH
t
OEH
V
t
WS
t
V
WE
V
t
DS
V
40H
DIN
DATA
RY/BY
SRD
FFH
V
t
DH
Vo
H
t
EHRL
VoL
tPS
VIH
RP
t
DAP
VIL
_____
Fig. 72 AC wave for program operation (CE control)
3850 Group (Spec. H) User’s Manual
1-71
HARDWARE
FUNCTIONAL DESCRIPTION
Read status
register
Write read array
command
Erase
VIH
Valid Address
tAS
Valid Address
Address
VIL
tWC
tAH
ta(CE)
ta(OE)
VIH
CE
VIL
tCS
tCH
VIH
OE
tOEH
tDAE
VIL
tWPH
VIH
WE
VIL
tDH
tWP
tDS
VIH
SRD
FFH
20H
D0H
DATA
VIL
tWHRL
VOH
VOL
RY/BY
tPS
VIH
VIL
RP
_____
Fig. 73 AC wave for erase operation (WE control)
Read status
register
Write read array
command
Erase
V
IH
Valid Address
Valid Address
Address
CE
V
IL
t
WC
tAH
tAS
t
a(CE)
V
IH
IL
IH
IL
IH
IL
IH
V
t
CEPH
t
CEP
ta(OE)
V
OE
t
OEH
V
t
WS
t
DAE
tWH
V
WE
V
tDH
tDS
V
DATA
SRD
FFH
20H
D0H
V
V
IL
t
EHRL
OH
RY/BY
V
OL
tPS
V
IH
RP
V
IL
Fig. 74 AC wave for erase operation (C___E__ control)
3850 Group (Spec. H) User’s Manual
1-72
HARDWARE
NOTES ON PROGRAMMING/NOTES ON USAGE
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) in the middle/high-speed mode is
at least on 500 kHz during an A-D conversion.
Do not execute the STP instruction during an A-D conversion.
Instruction Execution Time
Interrupts
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency in
high-speed mode.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
NOTES ON USAGE
Differences between 3850 group (standard)
and 3850 group (spec. H)
Timers
(1) The absolute maximum ratings of 3850 group (spec. H) is
If a value n (between 0 and 255) is written to a timer latch, the fre-
smaller than that of 3850 group (standard).
quency division ratio is 1/(n+1).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage VI = –0.3 to Vcc +0.3 V
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may
be some differences between 3850 group (standard) and 3850
group (spec. H).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
• The execution of these instructions does not change the con-
tents of the processor status register.
(3) Do not write any data to the reserved area and the reserved
bit. (Do not change the contents after rest.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
Handling of Source Pins
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin) and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the pins
to be connected, a ceramic capacitor of 0.01 µF–0.1µF is recom-
mended.
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
EPROM Version/One Time PROM Version/
Flash Memory Version
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY1 signal, set the transmit
enable bit, the receive enable bit, and the SRDY1 output enable bit
to “1”.
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational in-
terference even if it is connected to Vss pin or Vcc pin via a
resistor.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed.
SOUT2 pin for serial I/O2 goes to high impedance after transmis-
sion is completed.
When an external clock is used as synchronous clock in serial I/
O1 or serial I/O2, write transmission data to the transmit buffer
register or serial I/O2 register while the transfer clock is “H”.
3850 Group (Spec. H) User’s Manual
1-73
HARDWARE
DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and buit-
in EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
✽
1. Mask ROM Order Confirmation Form
✽
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
Table 27 Programming adapter
DATA REQUIRED FOR One Time PROM
PROGRAMMING ORDERS
Name of Programming Adapter
Package
PCA4738S-42A
PCA4738F-42A
42P4B, 42S1B
42P2R-A/E
The following are necessary when ordering a PROM programming
service:
✽
1. ROM Programming Confirmation Form
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 75 is recommended to verify programming.
✽
2. Mark Specification Form (only special mark with customer’s
trade mark logo)
3. Data to be programmed to PROM, in EPROM form (three iden-
tical copies) or one floppy disk.
✽For the mask ROM confirmation, the ROM programming confir-
mation form, and the mark specifications, refer to the “Renesas
Technology Corp.” Homepage (http://www.renesas.com/en/rom).
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 75 Programming and testing of One Time PROM version
3850 Group (Spec. H) User’s Manual
1-74
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
A-D conversion is started by setting AD conversion completion bit to
“0”. During A-D conversion, internal operations are performed as
follows.
By repeating the above operations up to the lowest-order bit of the
A-D conversion register, an analog value converts into a digital
value.
A-D conversion completes at 61 clock cycles (15.25 µs at f(XIN) = 8
MHz) after it is started, and the result of the conversion is stored
into the A-D conversion register.
1. After the start of A-D conversion, A-D conversion register goes to
“0016”.
Concurrently with the completion of A-D conversion, A-D conversion
interrupt request occurs, so that the AD conversion interrupt request
bit is set to “1”.
2. The highest-order bit of A-D conversion register is set to “1”, and
the comparison voltage Vref is input to the comparator. Then, Vref
is compared with analog input voltage VIN.
3. As a result of comparison, when Vref < VIN, the highest-order bit
of A-D conversion register becomes “1”. When Vref > VIN, the
highest-order bit becomes “0”.
Table 28 Relative formula for a reference voltage VREF of A-D
converter and Vref
When n = 0
Vref = 0
VREF
1024
When n = 1 to 1023
Vref =
✽ n
n: Value of A-D converter (decimal numeral)
Table 29 Change of A-D conversion register during A-D conversion
Change of A-D conversion register
Value of comparison voltage (Vref)
At start of conversion
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VREF
2
First comparison
Second comparison
Third comparison
VREF
2
VREF
±
✽1
0
0
4
VREF
2
VREF
8
VREF
4
±
±
±
✽1 ✽2
0
0
0
1
After completion of tenth
comparison
A result of A-D conversion
✽1 ✽2 ✽3 ✽4 ✽5 ✽6 ✽7 ✽8
VREF
2
VREF
1024
VREF
4
±
±
✽9 ✽10
• • • •
✽1–✽10: A result of the first comparison to the tenth comparison
3850 Group (Spec. H) User’s Manual
1-75
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 76 shows the A-D conversion equivalent circuit, and Figure
77 shows the A-D conversion timing chart.
V
CC
V
SS
VCC AVSS
About 2 kΩ
VIN
AN
AN
AN
AN
AN
0
1
2
3
4
Sampling
clock
C
Chopper
amplifier
A-D conversion register (high-order)
b4
b2 b1 b0
A-D control register
A-D conversion register
(low-order)
V
ref
V
REF
Reference
clock
Built-in
D-A converter
AD conversion interrupt request
AVSS
Fig. 76 A-D conversion equivalent circuit
φ
Write signal for A-D
control register
61 cycles
AD conversion
completion bit
Sampling clock
Fig. 77 A-D conversion timing chart
3850 Group (Spec. H) User’s Manual
1-76
CHAPTER 2
APPLICATION
2.1 I/O port
2.2 Interrupt
2.3 Timer
2.4 Serial I/O
2.5 PWM
2.6 A-D converter
2.7 Watchdog timer
2.8 Reset
2.9 Clock generating circuit
2.10 Standby function
2.11 Flash memory mode
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph describes the setting method of I/O port relevant registers, notes etc.
2.1.1 Memory map
Address
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
000716
Port P3 direction register (P3D)
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
Fig. 2.1.1 Memory map of I/O port relevant registers
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4)
(Pi: addresses 0016, 0216, 0416, 0616, 0816
)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
7
Port Pi
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
✽In output mode
Write •••••••• Port latch
Read •••••••• Port latch
✽In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Note: When reading bit 5, 6 or 7 of ports 3 and 4, the contents are undefined.
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4)
3850 Group (Spec. H) User’s Manual
2-2
APPLICATION
2.1 I/O port
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 0, 1, 2, 3, 4)
(PiD: addresses 0116, 0316, 0516, 0716, 0916)
b
0
Name
Port Pi direction
register
Functions
At reset R W
0
0 : Port Pi
0
0
input mode
output mode
1 : Port Pi
0 : Port Pi
1 : Port Pi
1
1
input mode
output mode
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
0 : Port Pi
1 : Port Pi
3
3
input mode
output mode
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
input mode
output mode
0 : Port Pi
1 : Port Pi
7
7
input mode
output mode
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4)
2.1.3 Terminate unused pins
Table 2.1.1 Termination of unused pins
Termination
Pins/Ports name
• Set to the input mode and connect each to VCC or VSS through a resistor of 1 kΩ
to 10 kΩ.
P0, P1, P2, P3, P4
• Set to the output mode and open at “L” or “H” output state.
Connect to Vss (GND).
V
REF
Connect to Vss (GND).
AVSS
Open (only when using external clock)
X
OUT
3850 Group (Spec. H) User’s Manual
2-3
APPLICATION
2.1 I/O port
2.1.4 Notes on I/O port
(1) Notes in standby state
In standby state✽1, do not make input levels of an I/O port “undefined”, especially for I/O ports of the
N-channel open-drain. When setting the N-channel open-drain port as an output, do not make input
levels of an I/O port “undefined”, too.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
✽ Reason
When setting as an input port with its direction register, the transistor becomes the OFF state,
which causes the ports to be the high-impedance state.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of an I/O port are “undefined”. This may cause power source current.
In I/O ports of N-channel open-drain, when the contents of the port latch are “1”, even if it is set
as an output port with its direction register, it becomes the same phenomenon as the case of an
input port.
✽1 standby state: stop mode by executing STP instruction
wait mode by executing WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction✽2, the value of the
unspecified bit may be changed.
✽ Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
•As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
✽2 Bit managing instructions: SEB and CLB instructions
3850 Group (Spec. H) User’s Manual
2-4
APPLICATION
2.1 I/O port
2.1.5 Termination of unused pins
(1) Terminate unused pins
✽ Output ports : Open
✽ Input ports :
Connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ.
A for pins whose potential affects to operation modes such as pins CNVSS, INT or others, select
the VCC pin or the VSS pin according to their operation mode.
✽ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
✽ The AVss pin when not using the A-D converter :
• When not using the A-D converter, handle a power source pin for the A-D converter, AVss pin
as follows:
AVss: Connect to the Vss pin.
(2) Termination remarks
✽ Input ports and I/O ports :
Do not open in the input mode.
✽ Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ✽ and
✽ shown on the above.
✽ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
✽ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and VCC (or VSS).
✽ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
✽ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
3850 Group (Spec. H) User’s Manual
2-5
APPLICATION
2.2 Interrupt
2.2 Interrupt
This paragraph explains the registers setting method and the notes relevant to the interrupt.
2.2.1 Memory map
003A16 Interrupt edge selection register (INTEDGE)
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
003E16 Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
003F16
Fig. 2.2.1 Memory map of registers relevant to interrupt
3850 Group (Spec. H) User’s Manual
2-6
APPLICATION
2.2 Interrupt
2.2.2 Relevant registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE: address 3A16
)
b
0
Name
Functions
0: Falling edge active
1: Rising edge active
At reset R W
0
INT
0
active edge
selection bit
INT active edge
selection bit
2 INT
active edge
selection bit
0: Falling edge active
1: Rising edge active
0
0
1
1
0: Falling edge active
1: Rising edge active
2
0: Falling edge active
1: Rising edge active
3
0
INT active edge
selection bit
3
SeriaI/O2/INT
interrupt source bit
3
4
0: INT
1: Serial I/O2 interrupt
selected
3
interrupt selected
0
0
0
0
5 Nothing is arranged for this bit. This is a write
6
disabled bit. When this bit is read out, the
contents are “0”.
7
Fig. 2.2.2 Structure of Interrupt edge selection register
3850 Group (Spec. H) User’s Manual
2-7
APPLICATION
2.2 Interrupt
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16
)
b
0
Name
Functions
At reset R W
✽
✽
✽
✽
✽
✽
✽
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
0
0
0
0
0
INT
0
interrupt
request bit
When writing to this bit, set “0” to this bit.
1
INT
1
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
2
3
0 : No interrupt request issued
1 : Interrupt request issued
INT interrupt
request bit
INT /Serial I/O2
interrupt request bit
2
3
0 : No interrupt request issued
1 : Interrupt request issued
4
5
6
When writing to this bit, set “0” to this bit.
0 : No interrupt request issued
1 : Interrupt request issued
Timer X interrupt
request bit
Timer Y interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
7
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.2.3 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16
)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
Timer 1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
1 Timer 2 interrupt
request bit
Serial I/O1 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
2
3
4
5
6
Serial I/O1 transmit 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
CNTR
request bit
CNTR interrupt
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
1
0 : No interrupt request issued
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.2.4 Structure of Interrupt request register 2
3850 Group (Spec. H) User’s Manual
2-8
APPLICATION
2.2 Interrupt
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
0
0
b
0
Name
Functions
At reset R W
0
INT
0
interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
1 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
2 INT
enable bit
INT interrupt
enable bit
INT /Serial I/O2
1
interrupt
2
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
3
4
3
interrupt enable bit
Fix this bit to “0”.
5
6
7
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.2.5 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
0
(ICON2 : address 3F16
)
b
0
Name
Timer 1 interrupt
enable bit
Functions
At reset R W
0
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 receive
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
CNTR
0
interrupt
enable bit
CNTR interrupt
1
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
A-D converter
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fix this bit to “0”.
Fig. 2.2.6 Structure of Interrupt control register 2
3850 Group (Spec. H) User’s Manual
2-9
APPLICATION
2.2 Interrupt
2.2.3 Interrupt source
The 3850 group permits interrupts of 15 sources. These are vector interrupts with a fixed priority system.
Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority
interrupt is accepted first. This priority is determined by hardware, but a variety of priority processing can
be performed by software, using an interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to Table 2.2.1.
Table 2.2.1 Interrupt sources, vector addresses and priority of 3850 group
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Remarks
Priority
Interrupt Source
High
Low
Reset (Note 2)
INT0
FFFD16
FFFB16
FFFC16
FFFA16
At reset
Non-maskable
1
2
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
Reserved
INT1
FFF916
FFF716
FFF816
FFF616
Reserved
3
4
At detection of either rising or
falling edge of INT1 input
External interrupt
(active edge selectable)
INT2
FFF516
FFF316
FFF416
FFF216
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
5
6
INT3
At detection of either rising or
falling edge of INT3 input
External interrupt
(active edge selectable)
Serial I/O2
At completion of serial I/O2 data Switch by Serial I/O2/INT3 interrupt
transfer
source bit
Reserved
Timer X
Timer Y
Timer 1
Timer 2
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
Reserved
7
8
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
9
STP release timer underflow
10
11
12
Serial I/O1
received
At completion of serial I/O1 data Valid when serial I/O1 is selected
reception
Serial I/O1
transmit
FFE516
FFE416
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
Valid when serial I/O1 is selected
13
CNTR0
CNTR1
FFE316
FFE116
FFE216
FFE016
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
14
15
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
A-D converter
FFDF16
FFDD16
FFDE16
FFDC16
At completion of A-D conversion
At BRK instruction execution
16
17
BRK instruction
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3850 Group (Spec. H) User’s Manual
2-10
APPLICATION
2.2 Interrupt
2.2.4 Interrupt operation
When an interrupt request is accepted, the contents of the following registers just before acceptance of the
interrupt requests are automatically pushed onto the stack area in the order of ✽, ✽ and ✽.
✽High-order contents of program counter (PC
H
)
✽Low-order contents of program counter (PC
✽Contents of processor status register (PS)
L
)
After the contents of the above registers are pushed onto the stack area, the accepted interrupt vector
address enters the program counter and consequently the interrupt processing routine is executed.
When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the
above registers pushed onto the stack area are restored to the respective registers in the order of ✽, ✽
and ✽; and the microcomputer resumes the processing executed just before acceptance of the interrupts.
Figure 2.2.7 shows an interrupt operation diagram.
Executing routine
·······
Interrupt occurs
(Accepting interrupt request)
Contents of program counter (high-order) are pushed onto stack
Suspended
operation
Contents of program counter (low-order) are pushed onto stack
Resume processing
Contents of processor status register are pushed onto stack
·······
Interrupt
processing
routine
RTI instruction
Contents of processor status register are popped from stack
Contents of program counter (low-order) are popped from stack
Contents of program counter (high-order) are popped from stack
: Operation commanded by software
: Internal operation performed automatically
Fig. 2.2.7 Interrupt operation diagram
3850 Group (Spec. H) User’s Manual
2-11
APPLICATION
2.2 Interrupt
(1) Processing upon acceptance of interrupt request
Upon acceptance of an interrupt request, the following operations are automatically performed.
✽The processing being executed is stopped.
✽The contents of the program counter and the processor status register are pushed onto the stack
area. Figure 2.2.8 shows the changes of the stack pointer and the program counter upon acceptance
of an interrupt request.
✽Concurrently with the push operation, the jump destination address (the beginning address of the
interrupt processing routine) of the occurring interrupt stored in the vector address is set in the
program counter, then the interrupt processing routine is executed.
✽After the interrupt processing routine is started, the corresponding interrupt request bit is automatically
cleared to “0”. The interrupt disable flag is set to “1” so that multiple interrupts are disabled.
Accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination
address in the vector area corresponding to each interrupt.
Stack area
Program counter
PCL Program counter (low-order)
Interrupt disable flag = “0”
PCH Program counter (high-order)
Stack pointer
(S)
S
(S)
Interrupt
request is
accepted
Program counter
Stack area
PCL
PCH
Vector address
Interrupt disable flag = “1”
(from Interrupt vector area)
(s) – 3
Processor status register
Program counter (low-order)
(S) Program counter (high-order)
Stack pointer
S
(S) – 3
Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
3850 Group (Spec. H) User’s Manual
2-12
APPLICATION
2.2 Interrupt
(2) Timing after acceptance of interrupt request
The interrupt processing routine begins with the machine cycle following the completion of the
instruction that is currently being executed.
Figure 2.2.9 shows the time up to execution of interrupt processing routine and Figure 2.2.10 shows
the timing chart after acceptance of interrupt request.
Interrupt request generated
Main routine
Start of interrupt processing
Waiting time for
post-processing
of pipeline
Stack push and
Interrupt processing routine
Vector fetch
✽
0 to 16 cycles
2 cycles
5 cycles
7 to 23 cycles
(When f(XIN) = 8 MHz, 1.75 µs to 5.75 µs)
✽ When executing DIV instruction
Fig. 2.2.9 Time up to execution of interrupt processing routine
Waiting time for pipeline
Push onto stack
Interrupt operation starts
post-processing
Vector fetch
φ
SYNC
RD
WR
S, SPS S-1, SPS S-2, SPS
Address bus
Data bus
BL
BH AL, AH
AL AH
PC
Not used
PCH PCL PS
: CPU operation code fetch cycle
SYNC
(This is an internal signal that cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
: “0016” or “0116”
SPS
Fig. 2.2.10 Timing chart after acceptance of interrupt request
3850 Group (Spec. H) User’s Manual
2-13
APPLICATION
2.2 Interrupt
2.2.5 Interrupt control
The acceptance of all interrupts, excluding the BRK instruction interrupt, can be controlled by the interrupt
request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. Figure 2.2.11
shows an interrupt control diagram.
Interrupt request bit
Interrupt enable bit
Interrupt request
Interrupt disable flag
BRK instruction
Reset
Fig. 2.2.11 Interrupt control diagram
The interrupt request bit, interrupt enable bit and interrupt disable flag function independently and do not
affect each other. An interrupt is accepted when all the following conditions are satisfied.
✽Interrupt request bit .......... “1”
✽Interrupt enable bit ........... “1”
✽Interrupt disable flag ........ “0”
Though the interrupt priority is determined by hardware, a variety of priority processing can be performed
by software using the above bits and flag. Table 2.2.2 shows a list of interrupt control bits according to the
interrupt source.
(1) Interrupt request bits
The interrupt request bits are allocated to the interrupt request register 1 (address 3C16) and interrupt
request register 2 (address 3D16).
The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to
“1”. The interrupt request bit is held in the “1” state until the interrupt is accepted. When the interrupt
is accepted, this bit is automatically cleared to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software.
(2) Interrupt enable bits
The interrupt enable bits are allocated to the interrupt control register 1 (address 003E16) and the
interrupt control register 2 (address 3F16).
The interrupt enable bits control the acceptance of the corresponding interrupt request.
When an interrupt enable bit is “0”, the corresponding interrupt request is disabled. If an interrupt
request occurs when this bit is “0”, the corresponding interrupt request bit is set to “1” but the
interrupt is not accepted. In this case, unless the interrupt request bit is set to “0” by software, the
interrupt request bit remains in the “1” state.
When an interrupt enable bit is “1”, the corresponding interrupt is enabled. If an interrupt request
occurs when this bit is “1”, the interrupt is accepted (when interrupt disable flag = “0”).
Each interrupt enable bit can be set to “0” or “1” by software.
3850 Group (Spec. H) User’s Manual
2-14
APPLICATION
2.2 Interrupt
(3) Interrupt disable flag
The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable
flag controls the acceptance of interrupt request except BRK instruction.
When this flag is “1”, the acceptance of interrupt requests is disabled. When the flag is “0”, the
acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set
to “0” with the CLI instruction.
When a main routine branches to an interrupt processing routine, this flag is automatically set to “1”,
so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine. Figure 2.2.12 shows an example of multiple interrupts.
Table 2.2.2 List of interrupt bits according to interrupt source
Interrupt enable bit
Interrupt request bit
Interrupt source
Address
Bit
b0
b2
b3
b4
b6
b7
b0
b1
b2
b3
b4
b5
b6
Bit
b0
b2
b3
b4
b6
b7
b0
b1
b2
b3
b4
b5
b6
Address
003C16
003C16
003C16
003C16
003C16
003C16
003D16
003D16
003D16
003D16
003D16
003D16
003D16
INT
INT
INT
INT
Timer X
Timer Y
Timer 1
Timer 2
0
1
2
3
003E16
003E16
003E16
003E16
003E16
003E16
003F16
003F16
003F16
003F16
003F16
003F16
003F16
/Serial I/O2
Serial I/O1 reception
Serial I/O1 transmission
CNTR
CNTR
A-D converter
0
1
3850 Group (Spec. H) User’s Manual
2-15
APPLICATION
2.2 Interrupt
Interrupt request
Nesting
Reset
Time
Main routine
I = 1
C1 = 0, C2 = 0
Interrupt
request 1
C1 = 1
I = 0
Interrupt 1
I = 1
Interrupt
request 2
Multiple interrupt
C2 = 1
I = 0
Interrupt 2
I = 1
RTI
I = 0
RTI
I = 0
I
: Interrupt disable flag
C1 : Interrupt enable bit of interrupt 1
C2 : Interrupt enable bit of interrupt 2
: Set automatically.
: Set by software.
Fig. 2.2.12 Example of multiple interrupts
3850 Group (Spec. H) User’s Manual
2-16
APPLICATION
2.2 Interrupt
2.2.6 INT interrupt
The INT interrupt requests is generated when the microcomputer detects a level change of each INT pin
(INT –INT ).
0
3
(1) Active edge selection
INT –INT can be selected from either a falling edge or rising edge detection as an active edge by
0
3
the interrupt edge selection register. In the “0” state, the falling edge of the corresponding pin is
detected. In the “1” state, the rising edge of the corresponding pin is detected.
(2) INT
Which of interrupt source of the serial I/O2/INT
INT interrupt source bit (bit 4 of address 3A16). (Set this bit to “0” when using INT
3
interrupt source selection
3
interrupt source can be selected by the serial I/O2/
.)
3
3
3850 Group (Spec. H) User’s Manual
2-17
APPLICATION
2.2 Interrupt
2.2.7 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 3A16
•Timer XY mode register (address 2316
)
)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active edge switch
bit) or the interrupt (source) select bit to “1”.
↓
NOP (One or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 2.2.13 Sequence of changing relevant register
✽ Reason
When setting the followings, the interrupt request bit may be set to “1”.
•When setting external interrupt active edge
Concerned register: Interrupt edge selection register (address 3A16
Timer XY mode register (address 2316
)
)
•When switching interrupt sources of an interrupt vector address where two or more interrupt
sources are allocated.
Concerned register: Interrupt edge selection register (address 3A16
)
3850 Group (Spec. H) User’s Manual
2-18
APPLICATION
2.2 Interrupt
(2) Check of interrupt request bit
✽ When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one
or more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 2.2.14 Sequence of check of interrupt request bit
✽ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
3850 Group (Spec. H) User’s Manual
2-19
APPLICATION
2.3 Timer
2.3 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.3.1 Memory map
Address
Prescaler 12 (PRE12)
Timer 1 (T1)
002016
002116
002216
002316
002416
002516
002616
002716
002816
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
Timer count source selection register (TCSS)
003C16
003D16
003E16
003F16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Fig. 2.3.1 Memory map of registers relevant to timers
2.3.2 Relevant registers
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)
(addresses 2016, 2416, 2616
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
• Set a count value of each prescaler.
• The value set in this register is written to both
each prescaler and the corresponding
prescaler latch at the same time.
• When this register is read out, the count value
of the corresponding prescaler is read out.
Fig. 2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y
3850 Group (Spec. H) User’s Manual
2-20
APPLICATION
2.3 Timer
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1
(T1: address 2116
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
0
0
0
0
0
0
0
• Set timer 1 count value.
• The value set in this register is written to both
the timer 1 and the timer 1 latch at the same
time.
• When the timer 1 is read out, the count value
of the timer 1 is read out.
Fig. 2.3.3 Structure of Timer 1
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2216
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
• Set timer 2 count value.
• The value set in this register is written to both
timer 2 and the timer 2 latch at the same time.
• When timer 2 is read out, the count value of
the timer 2 is read out.
Fig. 2.3.4 Structure of Timer 2
3850 Group (Spec. H) User’s Manual
2-21
APPLICATION
2.3 Timer
Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer X, Timer Y
(TX, TY: addresses 2516, 2716
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
• Set each timer count value.
• The value set in this register is written to both
each timer and the corresponding timer latch
at the same time.
• When each timer is read out, the count value
of the corresponding timer is read out.
Fig. 2.3.5 Structure of Timer X, Timer Y
3850 Group (Spec. H) User’s Manual
2-22
APPLICATION
2.3 Timer
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register
(TM: address 2316
)
b
0
Name
Functions
At reset R W
0
b1 b0
Timer X operating
mode bits
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width
0
1
2
measurement mode
Refer to Table 2.3.1
0 active edge
0
0
0
CNTR
switch bit
0: Count start
1: Count stop
3 Timer X count stop
bit
4
b5 b4
Timer Y operating
mode bits
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width
0
5
measurement mode
Refer to Table 2.3.1
CNTR1 active edge
switch bit
0
0
6
7
0: Count start
1: Count stop
Timer Y count stop
bit
Fig. 2.3.6 Structure of Timer XY mode register
Table 2.3.1 CNTR0/CNTR1 active edge switch bit function
Timer X /Timer Y
operation modes
Timer mode
Set
value
Timer function
CNTR0 / CNTR1 interrupt request
occurrence source
“0”
“1”
“0”
No influence to timer count
No influence to timer count
CNTR0/CNTR1 input signal falling edge
CNTR0/CNTR1 input signal rising edge
Pulse output
mode
Pulse output start: Beginning Output signal falling edge count
at “H” level
“1”
Pulse output start: Beginning Output signal rising edge count
at “L” level
Event counter
mode
“0”
“1”
“0”
“1”
Rising edge count
Falling edge count
Input signal falling edge count
Input signal rising edge count
Pulse width
“H” level width measurement Input signal falling edge count
“L” level width measurement
measurement mode
Input signal rising edge count
3850 Group (Spec. H) User’s Manual
2-23
APPLICATION
2.3 Timer
Timer count source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Timer count source selection register
(TCSS: address 2816
)
b
0
Name
Functions
At reset R W
0
0: f(XIN)/16 (f(XCIN)/16 at
low-speed mode)
1: f(XIN)/2 (f(XCIN)/2 at low-
speed mode)
Timer X count
source selection bit
0: f(XIN)/16 (f(XCIN)/16 at
low-speed mode)
Timer Y count
source selection bit
0
0
1
2
1: f(XIN)/2 (f(XCIN)/2 at low-
speed mode)
Timer 12 count
source selection bit
0: f(XIN)/16 (f(XCIN)/16 at
low-speed mode)
1: f(XCIN
)
3
4
5
6
0
0
0
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
7
Fig. 2.3.7 Structure of Timer count source selection register
3850 Group (Spec. H) User’s Manual
2-24
APPLICATION
2.3 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16
)
b
0
Name
Functions
At reset R W
✽
✽
✽
✽
✽
✽
✽
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
0
0
0
0
0
INT
0
interrupt
request bit
When writing to this bit, set “0” to this bit.
1
INT
1
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
2
3
0 : No interrupt request issued
1 : Interrupt request issued
INT interrupt
request bit
INT /Serial I/O2
interrupt request bit
2
3
0 : No interrupt request issued
1 : Interrupt request issued
4
5
6
When writing to this bit, set “0” to this bit.
0 : No interrupt request issued
1 : Interrupt request issued
Timer X interrupt
request bit
Timer Y interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
7
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.3.8 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16
)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
Timer 1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
1 Timer 2 interrupt
request bit
Serial I/O1 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
2
3
4
5
6
Serial I/O1 transmit 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
CNTR
request bit
CNTR interrupt
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
1
0 : No interrupt request issued
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.3.9 Structure of Interrupt request register 2
3850 Group (Spec. H) User’s Manual
2-25
APPLICATION
2.3 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
0
0
b
0
Name
Functions
At reset R W
0
INT
0
interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
1 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
2 INT
enable bit
INT nterrupt
enable bit
INT /Serial I/O2
1
interrupt
2
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
3
4
3
interrupt enable bit
Fix this bit to “0”.
5
6
7
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.3.10 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
(ICON2 : address 3F16)
0
b
0
Name
Timer 1 interrupt
enable bit
Functions
At reset R W
0
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 receive
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
CNTR
0
interrupt
enable bit
CNTR interrupt
1
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
A-D converter
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fix this bit to “0”.
Fig. 2.3.11 Structure of Interrupt control register 2
3850 Group (Spec. H) User’s Manual
2-26
APPLICATION
2.3 Timer
2.3.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request
occurs.
<Use>
•Generation of an output signal timing
•Generation of a wait time
[Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generation of cyclic interrupts
•Clock function (measurement of 250 ms); see Application example 1
•Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X, Timer Y)
The output level of the CNTR pin is inverted each time the timer underflows (in the pulse output
mode).
<Use>
•Piezoelectric buzzer output; see Application example 2
•Generation of the remote control carrier waveforms
[Function 4] Count of External pulses (Timer X, Timer Y)
External pulses input to the CNTR pin are counted as the timer count source (in the event counter
mode).
<Use>
•Frequency measurement; see Application example 3
•Division of external pulses
•Generation of interrupts due to a cycle using external pulses as the count source; count of a
reel pulse
[Function 5] Measurement of External pulse width (Timer X, Timer Y)
The “H” or “L” level width of external pulses input to CNTR pin is measured (in the pulse width
measurement mode).
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulse✽ for a
motor); see Application example 4
•Measurement of external pulse duty (when the frequency is fixed)
FG pulse✽: Pulse used for detecting the motor speed to control the motor speed.
3850 Group (Spec. H) User’s Manual
2-27
APPLICATION
2.3 Timer
(2) Timer application example 1: Clock function (measurement of 250 ms)
Outline: The input clock is divided by the timer so that the clock can count up at 250 ms intervals.
Specifications: •The clock f(XIN) = 4.19 MHz (222 Hz) is divided by the timer X.
•The clock is counted up in the process routine of the timer X interrupt which occurs
at 250 ms intervals.
Figure 2.3.12 shows the timers connection and setting of division ratios; Figure 2.3.13 shows the
relevant registers setting; Figure 2.3.14 shows the control procedure.
Dividing by 4 with software
Timer X count source
selection bit
Timer X interrupt
request bit
Prescaler X
1/256
Timer X
1/256
f(XIN) = 4.19 MHz
1/16
0 or 1
1/4
1 second
250 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.3.12 Timers connection and setting of division ratios
Timer count source selection register (address 2816
)
b7
b0
TCSS
0
Timer X count source : f(XIN)/16
Timer XY mode register (address 2316
)
b7
b0
1
0
0
TM
Timer X operating mode: Timer mode
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 2416
)
b7
b0
PREX
255
Set “division ratio – 1”
Timer X (address 2516
)
b7
b0
TX
255
Interrupt request register 1 (address 3C16
)
b7
b0
IREQ1
0
Timer X interrupt request
(becomes “1” at 250 ms intervals)
Interrupt control register 1 (address 3E16
)
b7
b0
ICON1
1
Timer X interrupt: Enabled
Fig. 2.3.13 Relevant registers setting
3850 Group (Spec. H) User’s Manual
2-28
APPLICATION
2.3 Timer
RESET
✽ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
XXXX1X00
2
TM
•Timer X : Timer mode
(address 2316
)
IREQ1
ICON1
0
1
•Clear Timer X interrupt request bit
•Timer X interrupt enabled
(address 3C16), bit6
(address 3E16), bit6
0
•Timer X count source : f(XIN)/16
•Set “division ratio – 1” to Prescaler X and Timer X
(address 2816), bit0
TCSS
PREX
TX
(address 2416
(address 2516
)
)
256 – 1
256 – 1
(address 2316), bit3
•Timer X count start
•Interrupts enabled
TM
CLI
0
Main processing
<Procedure for completion of clock set>
•Reset Timer to restart count from 0 second after completion of
clock set
(Note 1)
TM
PREX (address 2416
TX (address 2516
(address 2316), bit3
1
Note 1: Perform procedure for completion of clock set only
)
)
256 – 1
256 – 1
when completing clock set.
IREQ1 (address 3C16), bit6
TM (address 2316), bit3
0
0
Timer X interrupt process routine
CLT (Note 2)
CLD (Note 3)
Push registers to stack
Note 2: When using Index X mode flag (T)
Note 3: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
Y
•Judge whether clock stops
Clock stop ?
N
Clock count up (1/4 second to year)
•Clock count up
•Pop registers pushed to stack
Pop registers
RTI
Fig. 2.3.14 Control procedure
3850 Group (Spec. H) User’s Manual
2-29
APPLICATION
2.3 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 4.19 MHz (222 Hz) into about
2 kHz (2048 Hz), is output from the P2
7
/CNTR
0
pin.
•The level of the P2
7
/CNTR
0
pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.3.15 shows a peripheral circuit example, and Figure 2.3.16 shows the timers connection and
setting of division ratios. Figure 2.3.17 shows the relevant registers setting, and Figure 2.3.18 shows
the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
CNTR0 output
P2
7
/CNTR
0
PiPiPi.....
244 µs 244 µs
Set a division ratio so that the
underflow output period of the timer X
3850 Group
can be 244 µs.
Fig. 2.3.15 Peripheral circuit example
Timer X count
source selection
bit
Prescaler X
1
Timer X
1/64
Fixed
1/2
f(XIN) = 4.19
MHz
1/16
CNTR
0
Fig. 2.3.16 Timers connection and setting of division ratios
3850 Group (Spec. H) User’s Manual
2-30
APPLICATION
2.3 Timer
Timer count source selection register (address 2816
)
b7
b0
TCSS
0
Timer X count source: f(XIN)/16
Timer XY mode register (address 2316
)
b7
b0
1
0 0
1
TM
Timer X operating mode : Pulse output mode
CNTR active edge switch : Output starting at “H” level
0
Timer X count : Stop
Clear to “0” when starting count
Timer X (address 2516
)
b7
b0
TX
63
Set “division ratio – 1”
Prescaler X (address 2416
)
b7
b0
PREX
0
Interrupt control register 1 (address 3E16
)
b7
b0
ICON1
0
Timer X interrupt disabled
Fig. 2.3.17 Relevant registers setting
3850 Group (Spec. H) User’s Manual
2-31
APPLICATION
2.3 Timer
✽ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
P2 (address 0416), bit7
P2D (address 0516
1
)
1XXXXXXX2
•Timer X count source: f(XIN)/16
•Timer X interrupt disabled
TCSS (address 2816), bit0
ICON1 (address 3E16), bit6
0
0
•CNTR output stopped at this point (buzzer output stopped)
0
XXXX1001
64–1
1-1
2
TM
TX
(address 2316
(address 2516
)
)
)
•Set (division ratio – 1) to timer X, prescaler X
PREX (address 2416
Main processing
•Processing buzzer request, generated during main
processing, in output unit
Output unit
Yes
Buzzer request ?
No
TM
TX
(address 2316), bit3
1
64-1
0
(address 2316), bit3
TM
(address 2516
)
Start of piezoelectric buzzer output
Stop of piezoelectric buzzer
output
Fig. 2.3.18 Control procedure
3850 Group (Spec. H) User’s Manual
2-32
APPLICATION
2.3 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P4
•A reference value
0
/CNTR pin with the timer.
1
Specifications: •Clock f(XIN) = 4.19 MHz (222 Hz)
•The pulse is input to the P4
0
/CNTR pin and counted by the timer Y.
1
•A count value is read out at about 2 ms intervals, the timer 1 interrupt interval.
When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid value.
Figure 2.3.19 shows the judgment method of valid/invalid of input pulses; Figure 2.3.20 shows the
relevant registers setting; Figure 2.3.21 shows the control procedure.
Input pulse
71.4 µs or more
71.4 µs
50 µs
50 µs or less
(less than 14 kHz)
(14 kHz)
(20 kHz)
(20 kHz or more)
Valid
Invalid
Invalid
2 ms
71.4 µs
2 ms
50 µs
= 28 counts
= 40 counts
Fig. 2.3.19 Judgment method of valid/invalid of input pulses
3850 Group (Spec. H) User’s Manual
2-33
APPLICATION
2.3 Timer
Timer XY mode register (address 2316)
b7
b0
TM
1
1 1
0
Timer Y operating mode: Event counter mode
CNTR active edge switch: Falling edge count
1
Timer Y count: Stop
Clear to “0” when starting count
Timer count source selection register (address 2816)
b7
b0
TCSS
0
Timer 1 count source: f(XIN)/16
Prescaler 12 (address 2016)
b7
b0
PRE12
63
Timer 1 (address 2116)
b7
b0
T1
7
Set “division ratio – 1”
Prescaler Y (address 2616)
b7
b0
PREY
0
Timer Y (address 2716)
b7
b0
Set 255 just before counting pulses
(After a certain time has passed, the number of input
pulses is decreased from this value.)
TY
255
Interrupt control register 1 (address 3E16)
b7
b0
ICON1
ICON2
0
Timer Y interrupt: Disabled
Interrupt control register 2 (address 3F16)
b7
b0
1
Timer 1 interrupt: Enabled
Interrupt request register 1 (address 3C16)
b7
b0
IREQ1
0
Judgment of Timer Y interrupt request bit
( “1” of this bit when reading the count value indicates the 256 or more
pulses input in the condition of Timer Y = 255)
Fig. 2.3.20 Relevant registers setting
3850 Group (Spec. H) User’s Manual
2-34
APPLICATION
2.3 Timer
RESET
✽ X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
•All interrupts disabled
1110XXXX
XXXXX0XX
64 – 1
8 – 1
1 – 1
256 – 1
2
•Timer Y operating mode : Event counter mode
(Count a falling edge of pulses input from CNTR1 pin.)
(address 2316
(address 2816
(address 2016
(address 2116
(address 2616
(address 2716
)
)
)
)
)
)
TM
2
TCSS
PRE12
T1
PREY
TY
•Set division ratio so that Timer 1 interrupt will occur at
2 ms intervals.
•Timer Y initial value set
•Timer Y interrupt: Disabled
•Timer 1 interrupt: Enabled
(address 3E16), bit7
(address 3F16), bit0
0
1
ICON1
ICON2
•Timer Y count start
•Interrupts enabled
(address 2316), bit7
0
TM
CLI
Timer 1 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
1
IREQ1(address 3C16), bit7 ?
0
•Process as out of range when the count value is 256 or more
•Read the count value
•Store the count value into Accumulator (A)
TY (address 2716
)
(A)
In range
•Compare the read value with
reference value
214 < (A) < 228
•Store the comparison result to
flag Fpulse
Out of range
0
Fpulse
1
Fpulse
TY
(address 2716
)
•Initialize the counter value
256 – 1
IREQ1
(address 3C16), bit7
•Clear Timer Y interrupt request bit
•Pop registers pushed to stack
0
Process judgment result
Pop registers
RTI
Fig. 2.3.21 Control procedure
3850 Group (Spec. H) User’s Manual
2-35
APPLICATION
2.3 Timer
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the CNTR pin. An underflow
0
is detected by the timer X interrupt and an end of the input pulse “H” level is detected by
the CNTR interrupt.
0
Specifications: •The timer X counts the “H” level width of the FG pulse input to the CNTR pin.
0
<Example>
When the clock frequency is 4.19 MHz, the count source is 3.8 µs, which is obtained by dividing
the clock frequency by 16. Measurement can be made up to 250 ms in the range of FFFF16 to
000016
.
Figure 2.3.22 shows the timers connection and setting of division ratio; Figure 2.3.23 shows the
relevant registers setting; Figure 2.3.24 shows the control procedure.
Timer X count source
selection bit
Timer X interrupt
request bit
Prescaler X
1/256
Timer X
1/256
f(XIN) = 4.19 MHz
1/16
0 or 1
250 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.3.22 Timers connection and setting of division ratios
3850 Group (Spec. H) User’s Manual
2-36
APPLICATION
2.3 Timer
Timer XY mode register (address 2316
)
b7
b0
TM
1
0 1
1
Timer X operating mode: Pulse width measurement mode
CNTR active edge switch: “H” level width measurement
0
Timer X count: Stop
Clear to “0” when starting count
Prescaler X (address 2416
)
b7
b0
PREX
255
Set “division ratio – 1”
Timer X (address 2516
)
b7
b0
TX
255
Interrupt request register 1 (address 3C16
)
b7
b0
IREQ1
0
Timer X interrupt request
(Set to “1” automatically when Timer X underflows)
Interrupt control register 1 (address 3E16
)
b7
b0
ICON1
IREQ2
1
Timer X interrupt: Enabled
Interrupt request register 2 (address 3D16
)
b7
b0
0
CNTR
0
interrupt request
(Set to “1” automatically when “H” level input came to the end)
Interrupt control register 2 (address 3F16
)
b7
b0
ICON2
1
CNTR
0
interrupt: Enabled
Fig. 2.3.23 Relevant registers setting
3850 Group (Spec. H) User’s Manual
2-37
APPLICATION
2.3 Timer
RESET
✽ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
•All interrupts disabled
Initialization
SEI
•Timer X: Pulse width measurement mode
(Measure “H” level of pulses input from CNTR0 pin.)
•Set division ratio so that Timer X interrupt will occur at
250 ms intervals.
•Clear Timer X interrupt request bit
•Timer X interrupt enabled
(address 2316)
(address 2416)
(address 2516)
(address 3C16), bit6
(address 3E16), bit6
(address 3D16), bit4
(address 3F16), bit4
TM
PREX
TX
IREQ1
ICON1
IREQ2
ICON2
XXXX10112
256–1
256–1
0
1
0
1
•Clear CNTR0 interrupt request bit
•CNTR0 interrupt enabled
(address 2316), bit3
TM
CLI
•Timer X count start
•Interrupts enabled
0
Timer X interrupt process routine
•Error occured
Error processing
RTI
CNTR0 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
•Read the count value and store it to RAM
(A)
PREX
Low-order 8-bit result of
pulse width measurement
(A)
Inverted (A)
TX
High-order 8-bit result of
pulse width measurement
Inverted (A)
(address 2416)
PREX
•Division ratio set so that Timer X interrupt will
occur at 250 ms intervals.
256–1
256–1
(address 2516)
TX
•Pop registers pushed to stack
Pop registers
RTI
Fig. 2.3.24 Control procedure
3850 Group (Spec. H) User’s Manual
2-38
APPLICATION
2.3 Timer
2.3.4 Notes on timer
✽ If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
✽ When switching the count source by the timer 12, X and Y count source selection bits, the value
of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count
input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
3850 Group (Spec. H) User’s Manual
2-39
APPLICATION
2.4 Serial I/O
2.4 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the Serial I/O.
2.4.1 Memory map
Address
Serial I/O2 control register 1 (SIO2CON1)
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
001516
001616
001716
001816
001916
001A16
001B16
001C16
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt edge selection register (INTEDGE)
003A16
003C16
003D16
003E16
003F16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Fig. 2.4.1 Memory map of registers relevant to Serial I/O
3850 Group (Spec. H) User’s Manual
2-40
APPLICATION
2.4 Serial I/O
2.4.2 Relevant registers
Serial I/O2 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 1 (SIO2CON1: address 1516
)
b
0
Name
Internal
synchronous clock
selection bits
Functions
At reset R W
0
b2b1b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
0
0
0
0
0
0
1
2
3
4
5
6
Serial I/O2 port
selection bit
0: I/O port (P0
1: SOUT2, SCLK2 signal output
0: I/O port (P0
1, P0
2)
SRDY2 output
3)
enable bit
Transfer direction
selection bit
1: SRDY2 signal output
0: LSB first
1: MSB first
0: External clock
1: Internal clock
Serial I/O2
synchronous
clock selection bit
P0
1
/SOUT2
,
0: CMOS output
1: N-channel open-drain
output
0
7
P02
/SCLK2
P-channel output
disable bit
Fig. 2.4.2 Structure of Serial I/O2 control register 1
Serial I/O2 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 2
(SIO2CON2: address 1616
)
b
0
Name
Optional transfer
bits
Functions
At reset R W
1
b2b1b0
0 0 0: 1 bit
0 0 1: 2 bit
0 1 0: 3 bit
0 1 1: 4 bit
1 0 0: 5 bit
1 0 1: 6 bit
1 1 0: 7 bit
1 1 1: 8 bit
1
2
1
1
0
3
4
5
✽
✽
✽
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
0
Serial I/O2
I/O comparison
signal control bit
0: P4 I/O
1: SCMP2 output
3
0
6
S
OUT2 pin control
0: Output active
1: Output high-impedance
0
7
bit (P0
1)
Fig. 2.4.3 Structure of Serial I/O2 control register 2
3850 Group (Spec. H) User’s Manual
2-41
APPLICATION
2.4 Serial I/O
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register
(SIO2: address 1716
)
b
Name
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
1
2
3
4
5
6
7
This register becomes shift register.
At transmit: Set transmit data to this register.
At receive: Received data is stored to this
register.
Fig. 2.4.4 Structure of Serial I/O2 register
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB: address 1816
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
The transmission data is written to or the
receive data is read out from this buffer register.
• At write: A data is written to the transmit buffer
register.
• At read: The contents of the receive buffer
register are read out.
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 2.4.5 Structure of Transmit/Receive buffer register
3850 Group (Spec. H) User’s Manual
2-42
APPLICATION
2.4 Serial I/O
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status register (SIOSTS: address 1916
)
b
0
Name
Transmit buffer
empty flag (TBE)
Functions
0: Buffer full
1: Buffer empty
At reset R W
✽
✽
✽
0
0
0
0: Buffer empty
1: Buffer full
Receive buffer full
flag (RBF)
1
2 Transmit shift
register shift
completion flag
(TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag
3
0: No error
1: Overrun error
0
0
0
0
1
✽
✽
✽
✽
✽
(OE)
4
Parity error flag
(PE)
0: No error
1: Parity error
Framing error flag
(FE)
0: No error
1: Framing error
5
6
7
Summing error flag
(SE)
0: (OE) U (PE) U (FE) = 0
1: (OE) U (PE) U (FE) = 1
Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “1”.
Fig. 2.4.6 Structure of Serial I/O1 status register
3850 Group (Spec. H) User’s Manual
2-43
APPLICATION
2.4 Serial I/O
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register
(SIOCON: address 1A16)
b
Name
Functions
At reset R W
0
0 BRG count source
selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Serial I/O1
1
0
When clock synchronous
serial I/O is selected,
0: BRG output divided by 4
1: External clock input
When UART is selected,
0: BRG output divided by 16
1: External clock input
divided by16
synchronous clock
selection bit (SCS)
0
0
0: I/O port (P27)
1: SRDY1 output pin
SRDY1 output
enable bit (SRDY)
2
3
0: Transmit buffer empty
1: Transmit shift operation
completion
Transmit interrupt
source selection
bit (TIC)
0: Transmit disabled
1: Transmit enabled
Transmit enable bit
(TE)
0
0
0
4
5
6
Receive enable bit 0: Receive disabled
(RE)
1: Receive enabled
0: UART
Serial I/O1 mode
1: Clock synchronous
serial I/O
selection bit (SIOM)
0: Serial I/O1 disabled
(P24 to P27: normal I/O pins)
1: Serial I/O1 enabled
(P24 to P27: Serial I/O pins)
Serial I/O1 enable
bit (SIOE)
0
7
Fig. 2.4.7 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register
(UARTCON: address 1B16
)
b
0
Name
Functions
At reset R W
0
Character length
0: 8 bits
selection bit (CHAS)
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
1
2
3
0
0
Parity enable bit
(PARE)
0: Even parity
1: Odd parity
0: 1 stop bit
Parity selection bit
(PARS)
Stop bit length
0
0
selection bit (STPS) 1: 2 stop bits
4 P2
5/TxD P-channel
In output mode
0: CMOS output
1: N-channel open-drain
output
output disable bit
(POFF)
1
5
6
7
✽
✽
✽
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “1”.
1
1
Fig. 2.4.8 Structure of UART control register
3850 Group (Spec. H) User’s Manual
2-44
APPLICATION
2.4 Serial I/O
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator(BRG : address 1C16
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Set a count value of baud rate generator.
Fig. 2.4.9 Structure of Baud rate generator
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE: address 3A16
)
b
0
Name
Functions
0: Falling edge active
1: Rising edge active
At reset R W
0
INT0 active edge
selection bit
0: Falling edge active
1: Rising edge active
0
0
INT1 active edge
selection bit
1
0: Falling edge active
1: Rising edge active
2 INT2 active edge
selection bit
0: Falling edge active
1: Rising edge active
3
0
INT3 active edge
selection bit
SeriaI/O2/INT3
interrupt source bit
4
0: INT3 interrupt selected
1: Serial I/O2 interrupt
selected
0
0
0
0
5 Nothing is arranged for these bits. These are
6
write disabled bits. When these bits are read out,
the contents are “0”.
7
Fig. 2.4.10 Structure of Interrupt edge selection register
3850 Group (Spec. H) User’s Manual
2-45
APPLICATION
2.4 Serial I/O
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16
)
b
0
Name
Functions
At reset R W
✽
✽
✽
✽
✽
✽
✽
✽
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
0
0
0
0
0
INT
0
interrupt
request bit
When writing to this bit, set “0” to this bit.
1
INT
1
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
2
3
0 : No interrupt request issued
1 : Interrupt request issued
INT interrupt
request bit
INT /Serial I/O2
interrupt request bit
2
3
0 : No interrupt request issued
1 : Interrupt request issued
4
5
6
When writing to this bit, set “0” to this bit.
0 : No interrupt request issued
1 : Interrupt request issued
Timer X interrupt
request bit
Timer Y interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
7
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.4.11 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16
)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
Timer 1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
1 Timer 2 interrupt
request bit
Serial I/O1 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
2
3
4
5
6
Serial I/O1 transmit 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
CNTR
request bit
CNTR interrupt
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
1
0 : No interrupt request issued
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.4.12 Structure of Interrupt request register 2
3850 Group (Spec. H) User’s Manual
2-46
APPLICATION
2.4 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
0
0
b
0
Name
Functions
At reset R W
0
INT
0
interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
1 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
2 INT
enable bit
INT nterrupt
enable bit
INT /Serial I/O2
1
interrupt
2
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
3
4
3
interrupt enable bit
Fix this bit to “0”.
5
6
7
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.4.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
(ICON2 : address 3F16)
0
b
0
Name
Timer 1 interrupt
enable bit
Functions
At reset R W
0
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 receive
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
CNTR
0
interrupt
enable bit
CNTR interrupt
1
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
A-D converter
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fix this bit to “0”.
Fig. 2.4.14 Structure of Interrupt control register 2
3850 Group (Spec. H) User’s Manual
2-47
APPLICATION
2.4 Serial I/O
2.4.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.4.15 shows connection examples of a peripheral IC equipped with the CS pin.
There are connection examples using a clock synchronous serial I/O mode.
(1) Only transmission
(2) Transmission and reception
(Using the RXD pin as an I/O port)
Port
SCLK1
TXD
CS
Port
SCLK1
CS
CLK
IN
CLK
DATA
TXD
RXD
OUT
3850 group
Peripheral IC
(OSD controller etc.)
3850 group
Peripheral IC
(E2 PROM etc.)
(3) Transmission and reception
(When connecting RXD with TXD)
(When connecting IN with OUT in
peripheral IC)
(4) Connection of plural IC
Port
SCLK1
TXD
CS
Port
SCLK1
TXD
CS
CLK
IN
CLK
IN
RXD
OUT
RXD
Port
OUT
3850 group ✽1
Peripheral IC 1
Peripheral IC✽2
(E2 PROM etc.)
3850 group
CS
✽1: Select an N-channel open-drain output for TXD pin output control.
✽2: Use the OUT pin of peripheral IC which is an N-channel open-
drain output and becomes high impedance during receiving data.
CLK
IN
OUT
Notes 1:
2:
“Port” means an output port controlled by software.
When serial I/O2 is used, SOUT2 and SIN2 are used,
not TxD and RxD.
Peripheral IC 2
Fig. 2.4.15 Serial I/O connection examples (1)
3850 Group (Spec. H) User’s Manual
2-48
APPLICATION
2.4 Serial I/O
(2) Connection with microcomputer
Figure 2.4.16 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
S
CLK1
S
CLK1
CLK
IN
CLK
IN
TX
D
T
X
D
D
RX
D
R
X
OUT
OUT
3850 group
Microcomputer
3850 group Microcomputer
(3) Using SRDY1 signal output function
(Selecting an external clock)
(4) In UART✽
RDY
CLK
IN
SRDY1
CLK1
T
X
D
D
R
X
D
S
RX
T
X
D
TX
D
D
RX
OUT
3850 group Microcomputer
3850 group
Microcomputer
✽ When serial I/O2 is used, UART cannot be used.
Note: When serial I/O2 is used, SOUT2 and SIN2 are used, not TxD and RxD.
Fig. 2.4.16 Serial I/O connection examples (2)
3850 Group (Spec. H) User’s Manual
2-49
APPLICATION
2.4 Serial I/O
2.4.4 Setting of serial I/O transfer data format
A clock synchronous or clock asynchronous (UART) can be selected as a data format of Serial I/O1.
A clock synchronous is used as a data format of Serial I/O2.
Figure 2.4.17 shows the serial I/O transfer data format.
1ST-8DATA-1SP
ST
LSB
MSB
SP
SP
1ST-7DATA-1SP
ST
LSB
MSB
MSB
MSB
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
MSB
2SP
MSB
PAR
SP
SP
1ST-7DATA-1PAR-1SP
ST
LSB
UART
1ST-8DATA-2SP
ST
LSB
2SP
1ST-7DATA-2SP
ST
LSB
Serial I/O1
1ST-8DATA-1PAR-2SP
ST
LSB
PAR
2SP
2SP
1ST-7DATA-1PAR-2SP
ST
LSB
MSB PAR
Clock synchronous
Serial I/O
LSB first
LSB first (1 to 8 bits optional transfer)
MSB first (1 to 8 bits optional transfer)
ST : Start bit
SP : Stop bit
PAR : Parity bit
Clock synchronous
Serial I/O
Serial I/O2
Fig. 2.4.17 Serial I/O transfer data format
3850 Group (Spec. H) User’s Manual
2-50
APPLICATION
2.4 Serial I/O
2.4.5 Serial I/O application examples
(1) Communication using clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O.
The SRDY1 signal is used for communication control.
Figure 2.4.18 shows a connection diagram, and Figure 2.4.19 shows a timing chart.
Figure 2.4.20 shows a registers setting relevant to the transmitting side, and Figure 2.4.21 shows
registers setting relevant to the receiving side.
Transmitting side
Receiving side
P41/INT0
SCLK1
SRDY1
SCLK1
RXD
TXD
3850 group
3850 group
Fig. 2.4.18 Connection diagram
Specifications : • The Serial I/O is used (clock synchronous serial I/O is selected.)
• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
• The SRDY1 (receivable signal) is used.
• The receiving side outputs the SRDY1 signal at intervals of 2 ms (generated by timer),
and 2-byte data is transferred from the transmitting side to the receiving side.
• • • •
SRDY1
• • • •
SCLK1
• • • •
TXD
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
2 ms
Fig. 2.4.19 Timing chart
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916
)
b7
b0
SIOSTS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A16
)
b7
b0
SIOCON
1 1
1
0 0
0
BRG count source : f(XIN
)
Serial I/O1 synchronous clock : BRG/4
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O1 enabled
Baud rate generator (Address : 1C16
)
b7
b0
Set “division ratio – 1”.
BRG
7
Interrupt edge selection register (Address : 3A16
)
b7
b0
0
INTEDGE
INT
0
interrupt edge selection bit : Falling edge active
Fig. 2.4.20 Registers setting relevant to transmitting side
3850 Group (Spec. H) User’s Manual
2-52
APPLICATION
2.4 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916
)
b7
b0
SIOSTS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : At completing reception
“0” : At reading out contents of Receive buffer register
Serial I/O1 control register (Address : 1A16
)
b7
b0
SIOCON 1 1 1 1
1 1
Serial I/O1 synchronous clock : External clock
SRDY1 output enabled
Transmit enabled
Set this bit to “1”, using
Receive enabled
S
RDY1 output.
Clock synchronous serial I/O
Serial I/O1 enabled
Fig. 2.4.21 Registers setting relevant to receiving side
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
Figure 2.4.22 shows a control procedure of the transmitting side, and Figure 2.4.23 shows a control
procedure of the receiving side.
RESET
✽ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
1101xx002
(Address : 1A16)
SIOCON
BRG
INTEDGE
8 – 1
(Address : 1C16)
(Address : 3A16), bit0
0
0
IREQ1 (Address:3C16), bit0?
• Detection of INT0 falling edge
1
0
IREQ1 (Address : 3C16), bit0
The first byte of a
transmission data
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
TB/RB (Address : 1816)
0
SIOSTS (Address : 1916), bit0?
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
1
The second byte of a
transmission data
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
TB/RB (Address : 1816)
0
SIOSTS (Address : 1916), bit0?
1
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
SIOSTS (Address : 1916), bit2?
1
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
Fig. 2.4.22 Control procedure of transmitting side
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SIOCON (Address : 1A16
)
1111x11x
2
N
Pass 2 ms?
Y
• An interval of 2 ms generated by Timer
TB/RB (Address : 1816
)
Dummy data
•
S
RDY1 output
RDY1 signal is output by writing data to the TB.
Using the RDY1, set Transmit enable bit
(bit4) of the SIOCON to “1”.
S
S
0
SIOSTS (Address : 1916), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Read out reception data from
Receive buffer full flag is set to “0” by reading data.
TB/RB (Address : 1816
)
0
SIOSTS (Address : 1916), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
Read out reception data from
• Reception of the second byte data.
Receive buffer full flag is set to “0” by reading data.
TB/RB (Address : 1816
)
Fig. 2.4.23 Control procedure of receiving side
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
(2) Output of serial data (control of peripheral IC)
Outline : 4-byte data is transmitted and received, using the clock synchronous serial I/O.
The CS signal is output to a peripheral IC through port P4
3
.
Figure 2.4.24 shows a connection diagram, and Figure 2.4.25 shows a timing chart.
CS
CS
P43
P43
CS
CS
CLK
DATA
CLK
DATA
S
CLK1
SCLK2
CLK
DATA
CL
K
DATA
T
X
D
SOUT2
3850 group
Peripheral IC
3850 group
Peripheral IC
(1) Example for using Serial I/O1
Fig. 2.4.24 Connection diagram
(2) Example for using Serial I/O2
Specifications : • The Serial I/O is used (clock synchronous serial I/O is selected.)
• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• The Serial I/O interrupt is not used.
• Port P4
3
is connected to the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P4
3
is controlled by software.
CS
CLK
DO0
DO1
DO2
DO3
DATA
Note: When serial I/O1 is used, the level of the last bit is held. When serial
I/O2 is used, SOUT2 pin is in the high-impedance state after the transfer
is completed.
Fig. 2.4.25 Timing chart (Serial I/O1)
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
Figure 2.4.26 shows registers setting relevant to Serial I/O1, and Figure 2.4.27 shows a setting of
serial I/O1 transmission data.
Serial I/O1 control register (Address : 1A16
)
b7 b0
SIOCON
1 1 0 1 1 0 0 0
BRG count source : f(XIN
)
Serial I/O1 synchronous clock : BRG/4
RDY1 output disabled
S
Transmit interrupt source : Transmit shift operating completion
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O1 enabled
UART control register (Address : 1B16
)
b7 b0
0
UARTCON
P25/TXD pin : CMOS output
Baud rate generator (Address : 1C16
b7 b0
)
7
BRG
Set “division ratio – 1”.
Interrupt control register 2 (Address : 3F16
)
b7 b0
ICON2
0
Serial I/O1 transmit interrupt : Disabled
Interrupt request register 2 (Address : 3D16
)
b7 b0
IREQ2
0
Serial I/O1 transmit interrupt request
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Fig. 2.4.26 Registers setting relevant to Serial I/O1
Transmit/Receive buffer register (Address : 1816
)
b7
b0
Set a transmission data.
TB/RB
Confirm that transmission of the previous data is
completed (bit 3 of the Interrupt request register 2
is “1”) before writing data.
Fig. 2.4.27 Setting of serial I/O1 transmission data
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APPLICATION
2.4 Serial I/O
Example for using Serial I/O1
When the registers are set as shown in Figure 2.4.26, the Serial I/O1 can transmit 1-byte data by
writing data to the transmit buffer register.
Thus, after setting the CS signal to “L”, write the transmission data to the transmit buffer register by
each 1 byte, and return the CS signal to “H” when 4-byte data has been transmitted.
Figure 2.4.28 shows a control procedure of Serial I/O1.
✽
✽✽x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
(Address : 1A16
(Address : 1B16), bit4
(Address : 1C16
(Address : 3F16), bit3
(Address : 0816), bit3
)
11011000
2
•Serial I/O1 set
SIOCON
UARTCON
BRG
ICON2
P4
0
8–1
0
1
)
•Serial I/O1 transmit interrupt : Disabled
•CS signal output port set
(“H” level output)
(Address : 0916
)
xxxx1xxx
2
P4D
•CS signal output level to “L” set
P4 (Address : 0816), bit3
0
•Serial I/O1 transmit interrupt
request bit set to “0”
IREQ2 (Address : 3D16), bit3
0
•
Transmission data write
(Start of transmit 1-byte data)
a transmission
data
TB/RB (Address : 1816
)
0
•Judgment of completion of transmitting
1-byte data
IREQ2 (Address : 3D16), bit3?
1
N
Complete to transmit 4-byte data?
Y
•Use any of RAM area as a counter for
counting the number of transmitted bytes
•Judgment of completion of transmitting 4-
byte data
P4 (Address : 0816), bit3
1
•Return the CS signal output level to “H”
when transmission of 4-byte data is
completed
Fig. 2.4.28 Control procedure of Serial I/O1
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APPLICATION
2.4 Serial I/O
Figure 2.4.29 shows registers setting relevant to Serial I/O2, and Figure 2.4.30 shows a setting of
serial I/O2 transmission data.
Serial I/O2 control register 1 (Address : 1516
)
b7
b0
SIO2CON1
0
1
0 0 1 0 1
0
Synchronous clock : f(XIN)/32
Serial I/O2 used
S
RDY2 output not used
LSB first
Internal clock
P01/SOUT2, P02/SCLK2 pin : CMOS output
Serial I/O2 control register 2 (Address : 1616
)
b7
b0
SIO2CON2
0
1 1
1
Transfer bit : 8 bits
P4 : I/O port
3
Interrupt edge selection register (Address : 3A16
)
b7 b0
INTEDGE
1
Serial I/O2/ INT3 interrupt source selection : Serial I/O2 interrupt
Interrupt control register 1 (Address : 3E16
b7 b0
)
ICON1
IREQ1
0
Serial I/O2 interrupt : Disabled
Interrupt request register 1 (Address : 3C16
b7 b0
)
0
Serial I/O2 interrupt request
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Fig. 2.4.29 Registers setting relevant to Serial I/O2
Serial I/O2 register (Address : 1716
)
b7
b0
Set a transmission data.
SIO2
Confirm that transmission of the previous data is
completed (bit 4 of the Interrupt request register 1
is “1”) before writing data.
Fig. 2.4.30 Setting of serial I/O2 transmission data
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APPLICATION
2.4 Serial I/O
Example for using Sreial I/O2
When the registers are set as shown in Fig. 2.4.29, the Serial I/O2 can transmit 1-byte data by writing
data to the serial I/O2 register.
Thus, after setting the CS signal to “L”, write the transmission data to Serial I/O2 by each 1 byte, and
return the CS signal to “H” when 4-byte data has been transmitted.
Figure 2.4.31 shows a control procedure of Serial I/O2.
✽ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
•Serial I/O2 control register set
010010102
x0xxx1112
xxx0xxxx2
(Address : 1516)
(Address : 2616)
(Address : 3A16)
SIO2CON1
SIO2CON2
INTEDGE
ICON1
P4
P4D
•Serial I/O2/INT3 interrupt source selection : Serial I/O2 interrupt
•Serial I/O2 interrupt : Disabled
•CS signal output port set
(Address : 3E16), bit4
(Address : 0816), bit3
0
1
xxxx1xxx2
(Address : 0916)
(“H” level output)
P4 (Address : 0816), bit3
0
•CS signal output level set to “L”
•Serial I/O2 interrupt request bit set to “0”
IREQ1 (Address : 3C16), bit4
0
•Transmission data write
(Start of transmit 1-byte data)
a transmission
data
SIO2 (Address : 1716)
•Judgment of completion of transmitting 1-
byte data
0
IREQ1 (Address : 3C16), bit4?
1
•Use any of RAM area as a counter for
counting the number of transmitted bytes
•Judgment of completion of transmitting 4-
byte data
N
Complete to transmit 4-byte data?
Y
•Return the CS signal output level to “H”
when transmission of 4-byte data is
completed
P4 (Address : 0816), bit3
1
Fig. 2.4.31 Control procedure of Serial I/O2
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APPLICATION
2.4 Serial I/O
(3) Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.4.32 shows a connection diagram.
S
CLK1
SCLK1
T
X
D
D
R
X
D
D
RX
T
X
Master unit
Slave
Fig. 2.4.32 Connection diagram
Specifications :
• The serial I/O is used (clock synchronous serial I/O is selected).
• Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32)
• Byte cycle: 488 µs
• Number of bytes for transmission or reception : 8 byte/block
• Block transfer cycle : 16 ms
• Block transfer term : 3.5 ms
• Interval between blocks : 12.5 ms
• Heading adjustment time : 8 ms
Limitations of specifications :
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O1 receive
interrupt request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.4 Serial I/O
The communication is performed according to the timing shown in Figure 2.4.33. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjustment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.4.34 shows relevant registers setting.
DO0
DO1
DO2
DO7
DO0
Byte cycle
Interval between blocks
Block transfer term
Block transfer cycle
Heading adjustment time
Processing for heading adjustment
Fig. 2.4.33 Timing chart
Master unit
Slave unit
Serial I/O1 control register (Address : 1A16
)
Serial I/O1 control register (Address : 1A16
)
b7 b0
b7
b0
1 1 1 1 1 0 0 0
SIOCON
1 1
0 1
1 1
SIOCON
BRG count source : f(XIN
)
Not affected by external clock
Synchronous clock : BRG/4
RDY1 output disabled
Synchronous clock : External clock
S
S
RDY1 output disabled
Transmit interrupt source :
Transmit shift operating completion
Not use the serial I/O1 transmit interrupt
Transmit enabled
Transmit enabled
Receive enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O1 enabled
Clock synchronous serial I/O
Serial I/O1 enabled
Both of units
UART control register (Address : 1B16
)
b7 b0
UARTCON
0
P25/TXD pin : CMOS output
Baud rate generator (Address : 1C16
)
b7 b0
BRG
7
Set “division ratio – 1”.
Fig. 2.4.34 Relevant registers setting
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APPLICATION
2.4 Serial I/O
Control procedure :
● Control in the master unit
After setting the relevant registers shown in Figure 2.4.34, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the transmit buffer register.
To perform the communication in the timing shown in Figure 2.4.33, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O1 transmit
interrupt request bit is set to “1”, or before the next transmission data is written to the transmit
buffer register.
Figure 2.4.35 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 488 µs
CLT (Note 1)
CLD (Note 2)
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Push register to stack
•Push the register used in the interrupt
processing routine into the stack
N
Within a block
transfer term?
•Generation of a certain block interval
by using a timer or other functions
Y
•Check the block interval counter and
determine to start a block transfer
Count a block interval counter
Read a reception data
N
Y
Complete to transfer
a block?
Start a block transfer?
Y
N
Write the first transmission data
(first byte) in a block
Write a transmission data
Pop registers
RTI
•Pop registers which is pushed to stack
Fig. 2.4.35 Control procedure of master unit
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APPLICATION
2.4 Serial I/O
✽ Control in the slave unit
After setting the relevant registers as shown in Figure 2.4.34, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O receive interrupt
request bit is set to “1” each time an 8-bit synchronous clock is received.
In the serial I/O receive interrupt processing routine, the data to be transmitted next is written to
the transmit buffer register after the received data is read out.
However, if no serial I/O receive interrupt occurs for a certain time (heading adjustment time or
more), the following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.4.36 shows a control procedure of the slave unit using the serial I/O receive interrupt and
any timer interrupt (for heading adjustment).
Timer interrupt processing
routine
Serial I/O receive interrupt
processing routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
CLT (Note 1)
CLD (Note 2)
Push register to stack
•Push the register used in the
interrupt processing routine into
the stack
•Push the register used in
the interrupt processing
routine into the stack
•Confirmation of the received
byte counter to judge the
block transfer term
Heading adjustment counter – 1
N
Within a block
transfer term?
Y
N
Heading adjustment
counter = 0?
Read a reception data
Y
Write the first transmission
data (first byte) in a block
A received byte counter +1
A received byte counter
0
Y
A received byte
counter ≥ 8?
N
•Pop registers which is
pushed to stack
Pop registers
RTI
Write a transmission data
Write dummy data (FF16)
Initial
value
(Note 3)
Heading
adjustment
counter
Pop registers
•Pop registers which is pushed to stack
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
RTI
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set 8
as the initial value.
Fig. 2.4.36 Control procedure of slave unit
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APPLICATION
2.4 Serial I/O
(4) Communication (transmit/receive) using asynchronous serial I/O (UART)
Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O.
Port P4 is used for communication control.
0
Figure 2.4.37 shows a connection diagram, and Figure 2.4.38 shows a timing chart.
Transmitting side
Receiving side
P4
0
P4
0
T
X
D
RX
D
3850 group
3850 group
Fig. 2.4.37 Connection diagram
Specifications : • The Serial I/O1 is used (UART is selected).
• Transfer bit rate : 9600 bps (f(XIN) = 4.9152 MHz is divided by 512)
• Communication control using port P4
(The output level of port P4 is controlled by software.)
0
0
• 2-byte data is transferred from the transmitting side to the receiving side at intervals
of 10 ms generated by the timer.
P4
0
.
.....
.....
TXD
.
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
ST
ST
ST
SP(2)
SP(2)
10 ms
Fig. 2.4.38 Timing chart (using UART)
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APPLICATION
2.4 Serial I/O
Table 2.4.1 and Table 2.4.2 show setting examples of the baud rate generator (BRG) values and
transfer bit rate values; Figure 2.4.39 shows registers setting relevant to the transmitting side; Figure
2.4.40 shows registers setting relevant to the receiving side.
Table 2.4.1 Setting examples of Baud rate generator values and transfer bit rate values (1)
BRG count source
(Note 1)
Transfer bit rate (bps) (Note 2)
at f(XIN) = 4.9152 MHZ at f(XIN) = 8 MHZ
BRG setting value
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)
255(FF16)
127(7F16)
63(3F16)
31(1F16)
15(0F16)
7(0716)
300
600
488.28125
976.5625
1953.125
3906.25
7812.5
1200
2400
4800
9600
15625
3(0316)
19200
38400
76800
153600
307200
31250
1(0116)
62500
3(0316)
125000
250000
500000
f(XIN)
1(0116)
f(XIN)
0(0016)
Table 2.4.2 Setting examples of Baud rate generator values and transfer bit rate values (2)
BRG count source
(Note 1)
Transfer bit rate (bps) (Note 2)
at f(XIN) = 7.9872 MHZ
600
BRG setting value
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)
207(CF16)
103(6716)
51(3316)
25(1916)
12(0C16)
25(1916)
12(0C16)
1200
2400
4800
9600
19200
38400
f(XIN)
Notes 1: Select the BRG count source with bit 0 of the serial I/O1 control register (Address : 1A16).
2: Equation of transfer bit rate:
f(XIN)
Transfer bit rate (bps) =
(BRG setting value + 1) ✽ 16 ✽✽m✽
✽m: When bit 0 of the serial I/O1 control register (Address : 1A16) is set to “0”, a value of m
is 1.
When bit 0 of the serial I/O1 control register (Address : 1A16) is set to “1”, a value of m
is 4.
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APPLICATION
2.4 Serial I/O
Transmitting side
Serial I/O1 status register (Address : 1916
)
b7
b0
SIOSTS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O1 control register (Address : 1A16
)
b7
b0
1 0 0 1
0 0 1
SIOCON
BRG count source : f(XIN)/4
Serial I/O1 synchronous clock : BRG/16
SRDY1 output disabled
Transmit enabled
Receive disabled
Asynchronous serial I/O (UART)
Serial I/O1 enabled
UART control register (Address : 1B16
)
b7
b0
UARTCON
0 1
0 0
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
TXD : CMOS output
Baud rate generator (Address : 1C16
)
b7
b0
f(XIN
)
–1
Set
7
BRG
✽
Transfer bit rate ✽ 16 ✽ m
✽ When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0” ,
a value of m is 1.
When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “1” ,
a value of m is 4.
Fig. 2.4.39 Registers setting relevant to transmitting side
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APPLICATION
2.4 Serial I/O
Receiving side
Serial I/O1 status register (Address : 1916
)
b7
b0
SIOSTS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : At completing reception
“0” : At reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing.
Summing error flag
“1” : When any one of the following errors occurs.
• Overrun error
• Framing error
Serial I/O1 control register (Address : 1A16
)
b7
b0
1 0 1 0
0 0
1
SIOCON
BRG count source : f(XIN)/4
Serial I/O1 synchronous clock : BRG/16
SRDY1 out disabled
Transmit disabled
Receive enabled
Asynchronous serial I/O(UART)
Serial I/O1 enabled
UART control register (Address : 1B16
)
b7
b0
UARTCON
1
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 1C16
)
b7
b0
f(XIN
)
–1
Set
BRG
7
Transfer bit rate ✽ 16 ✽ m✽
✽ When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0” ,
a value of m is 1.
When bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “1” ,
a value of m is 4.
Fig. 2.4.40 Registers setting relevant to receiving side
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APPLICATION
2.4 Serial I/O
Figure 2.4.41 shows a control procedure of the transmitting side, and Figure 2.4.42 shows a control
procedure of the receiving side.
✽ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
1001x001
2
(Address : 1A16
(Address : 1B16
)
)
)
SIOCON
UARTCON
BRG
P4
P4D
xxx01x00
2
8–1
(Address : 1C16
(Address : 0816), bit0
(Address : 0916
0
• Port P4 set for communication control
0
)
xxxxxxx1
2
N
Pass 10 ms?
Y
• An interval of 10 ms generated by Timer
• Communication start
1
P4 (Address : 0816), bit0
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
TB/RB (Address : 1816
)
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
SIOSTS (Address : 1916), bit0?
1
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
The second byte of
a transmission data
TB/RB (Address : 1816
)
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
SIOSTS (Address : 1916), bit0?
1
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
SIOSTS (Address : 1916), bit2?
1
P4 (Address : 0816), bit0
0
• Communication completion
Fig. 2.4.41 Control procedure of transmitting side
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APPLICATION
2.4 Serial I/O
RESET
✽ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
1010x001
2
SIOCON
UARTCON
BRG
(Address : 1A16
(Address : 1B16
)
)
)
xxxx1x00
2
8–1
(Address : 1C16
(Address : 0916
P4D
xxxxxxx0
2
)
0
SIOSTS (Address : 1916), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 1816
)
• Judgment of an error flag
1
0
SIOSTS (Address : 1916), bit6?
0
• Judgment of completion of
receiving
SIOSTS (Address : 1916), bit1?
(Receive buffer full flag)
1
• Reception of the second byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 1816
)
• Judgment of an error flag
1
SIOSTS (Address : 1916), bit6?
0
Processing for error
1
P4 (Address : 0816), bit0?
0
• Countermeasure for a bit slippage
SIOCON (Address : 1A16
SIOCON (Address : 1A16
)
)
0000x000
1010x001
2
2
Fig. 2.4.42 Control procedure of receiving side
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APPLICATION
2.4 Serial I/O
2.4.6 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O (Serial I/O1)
✽ Stop of transmission operation
Clear the serial I/O1 enable bit and the transmit enable bit to “0” (Serial I/O1 and transmit disabled).
✽ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
✽ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0”
(Serial I/O1 disabled).
✽ Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive
disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
✽ Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to
“0” (Serial I/O1 disabled) (refer to (1) ✽).
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APPLICATION
2.4 Serial I/O
(2) Notes when selecting clock asynchronous serial I/O (Serial I/O1)
✽ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
✽ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
✽ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
✽ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
✽ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) SRDY1 output of reception side
When signals are output from the SRDY1 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY1 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O1 control register again (Serial I/O1)
Set the serial I/O1 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0”.
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O1 control register
Can be set with the LDM instruction at the same time
↓
Set both the transmit enable bit (TE) and
the receive enable bit (RE), or one of
them to “1”
Fig. 2.4.43 Sequence of setting serial I/O1 control register again
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APPLICATION
2.4 Serial I/O
(5) Data transmission control with referring to transmit shift register completion flag (Serial I/O1)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected (Serial I/O1)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the SCLK1 input level. Also, write the transmit data to the transmit buffer
register at “H” of the SCLK1 input level.
(7) Transmit interrupt request when transmit enable bit is set (Serial I/O1)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
✽ Set the interrupt enable bit to “0” (disabled) with CLB instruction.
✽ Prepare serial I/O for transmission/reception.
✽ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
✽ Set the interrupt enable bit to “1” (enabled).
✽ Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt bit is set regardless of which of the two timings listed below is selected as the timing for
the transmission interrupt to be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
(8) Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external clock as synchronous clock, write the
transmit data to the serial I/O2 register (serial I/O shift register) at “H” of the transfer clock input level.
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APPLICATION
2.5 PWM
2.5 PWM
This paragraph explains the registers setting method and the notes relevant to the PWM.
2.5.1 Memory map
Address
001D16 PWM control register (PWMCON)
001E16 PWM prescaler (PREPWM)
PWM register (PWM)
001F16
Fig. 2.5.1 Memory map of registers relevant to PWM
2.5.2 Relevant registers
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register (PWMCON: address 1D16
)
b
0
Name
PWM function
enable bit
Functions
At reset R W
0
0 : PWM disabled
1 : PWM enabled
Count source
selection bit
0
1
0 : f(XIN
1 : f(XIN)/2
)
✕
2
3
4
5
6
7
0
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
0
0
0
✕
✕
✕
✕
✕
0
Fig. 2.5.2 Structure of PWM control register
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APPLICATION
2.5 PWM
PWM prescaler
b7 b6 b5 b4 b3 b2 b1 b0
PWM prescaler
(PREPWM: address 1E16
)
b
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
1
2
3
4
5
6
7
•Set the PWM period.
•The value set in this register is written to both
PWM prescaler pre-latch and PWM prescaler
latch at the same time.
• When data is written to this register during
PWM output, the pulse corresponding to
changed value is output at the next period.
• When this register is read out, the count value
of the PWM prescaler latch is read out.
Fig. 2.5.3 Structure of PWM prescaler
PWM register
b7 b6 b5 b4 b3 b2 b1 b0
PWM register
(PWM: address 1F16
)
b
0
1
2
3
4
5
6
7
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• Set the PWM “H” level output interval.
• The value set in this register is written to both
PWM register pre-latch and PWM register
latch at the same time.
• When data is written to this register during
PWM output, the pulse corresponding to
changed value is output at the next period.
• When this register is read out, the contents of
the PWM register latch is read out.
Fig. 2.5.4 Structure of PWM register
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APPLICATION
2.5 PWM
2.5.3 PWM output circuit application example
<Motor control>
Outline : The rotation speed of the motor is controlled by using PWM (pulse width modulation) output.
Figure 2.5.5 shows a connection diagram ; Figures 2.5.6 shows PWM output timing, and Figure 2.5.7
shows a setting of the related registers.
M
P44/PWM
D-A converter
Motor driver
3850 group
Fig. 2.5.5 Connection diagram
Specifications : • Motor is controlled by using the PWM output function of 8-bit resolution.
• Clock f(XIN) = 5.0 MHz
• “T”, PWM cycle : 102 µs
• “t”, “H” level width of output pulse : 40 µs (Fixed speed)
✽ A motor speed can be changed by modifying the “H” level width of output pulse.
t = 40 µs
PWM output
T = 102 µs
Fig. 2.5.6 PWM output timing
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APPLICATION
2.5 PWM
PWM control register (Address : 1D16
)
b7
b0
0 1
PWMCON
PWM output: Enabled (Note)
Count source: f(XIN
)
PWM prescaler (Address : 1E16
b7 b0
)
[Equation]
Set “T”, PWM cycle
n = 1
✽
n
PREPWM
PWM
255 ✽✽(n + 1)
T =
f(XIN
)
PWM register (Address : 1F16
b7 b0
)
[Equation]
T ✽✽m
Set “t”, “H” level width of PWM
m = 100
m
t =
255
Note:
The PWM output function has priority even when bit 4 (corresponding bit to P4 pin)
4
of Port P4 direction register is set to “0” (input mode).
Fig. 2.5.7 Setting of relevant registers
<About PWM output>
1. Set the PWM function enable bit to “1” : The P44/PWM pin is used as the PWM pin.
The pulse beginning with “H” level pulse is output.
2. Set the PWM function enable bit to “0” : The P44/PWM pin is used as the port P44.
Thus, when fixing the output level, take the following procedure:
(1) Write an output value to bit 6 of the port P4 register.
(2) Write “000100002” to the port P4 direction register.
3. After data is set to the PWM prescaler and the PWM register, the PWM waveforms corresponding to updated
data will be output from the next repetitive cycle.
PWM output
Change PWM
output data
From the next repetitive cycle,
output modified data
Fig. 2.5.8 PWM output
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APPLICATION
2.5 PWM
Control procedure : By setting the related registers as shown by Figure 2.5.7, PWM waveforms are output to
the externals. This PWM output is integrated through the low pass filter, and that
converted into DC signals is used for control of the motor.
Figure 2.5.9 shows control procedure.
• X : This bit is not used here.
Set it to “0” or “1” arbitrarily.
• “L” level output from P44/PWM pin
P4 (Address : 0816), bit4
P4D (Address : 0916)
0
XXX1XXXX
2
1
• PWM period setting
PREPWM (Address : 1E16)
100
• “H” level width of PWM setting
PWM
(Address : 1F16)
XXXXXX01
2
• PWM count source selected, PWM output enabled
PWMCON (Address : 1D16)
Fig. 2.5.9 Control procedure
2.5.4 Notes on PWM
The PWM starts after the PWM enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L“ level output is as follows:
n + 1
2 • f(XIN
sec. (Count source selection bit = 0, where n is the value set in the prescaler)
)
n + 1
sec. (Count source selection bit = 1, where n is the value set in the prescaler)
f(XIN
)
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APPLICATION
2.6 A-D converter
2.6 A-D converter
This paragraph explains the registers setting method and the notes relevant to the A-D converter.
2.6.1 Memory map
Address
003416 A-D control register (ADCON)
003516 A-D conversion register (low-order) (ADL)
003616 A-D conversion register (high-order) (ADH)
003D16 Interrupt request register 2 (IREQ2)
003F16 Interrupt control register 2 (ICON2)
Fig. 2.6.1 Memory map of registers relevant to A-D converter
2.6.2 Relevant registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register
(ADCON: address 3416
)
b
0
Name
Analog input pin
selection bits
Functions
At reset R W
0
b2 b1 b0
0 0 0: P3
0 0 1: P3
0 1 0: P3
0 1 1: P3
1 0 0: P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
1
2
3
0
0
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
1
4
0: Conversion in progress
1: Conversion completed
AD conversion
completion bit
0
0
0
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
Fig. 2.6.2 Structure of A-D control register
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APPLICATION
2.6 A-D converter
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3616)
b
0
Functions
At reset R W
Undefined
This is A-D conversion result stored bits. This is
read exclusive register.
10-bit read
b7
b0
1
Undefined
b9b8
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read out,
the contents are “0”.
0
0
0
0
0
0
2
3
4
5
6
7
Fig. 2.6.3 Structure of A-D conversion register (high-order)
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3516)
b
Functions
At reset R W
Undefined
0
1
2
3
4
5
6
7
This is A-D conversion result stored bits. This is
read exclusive register.
Undefined
Undefined
8-bit read
b7
b0
Undefined
b9b8b7b6b5b4b3b2
10-bit read
Undefined
Undefined
b7
b0
Undefined
b7b6b5b4b3b2b1b0
Undefined
Fig. 2.6.4 Structure of A-D conversion register (low-order)
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APPLICATION
2.6 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16
)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
Timer 1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
1 Timer 2 interrupt
request bit
Serial I/O1 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
2
3
4
5
6
Serial I/O1 transmit 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
CNTR
request bit
CNTR interrupt
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
1
0 : No interrupt request issued
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.6.5 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
0
(ICON2 : address 3F16
)
b
0
Name
Timer 1 interrupt
enable bit
Functions
At reset R W
0
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 receive
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
CNTR
0
interrupt
enable bit
CNTR interrupt
1
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
A-D converter
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fix this bit to “0”.
Fig. 2.6.6 Structure of Interrupt control register 2
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APPLICATION
2.6 A-D converter
2.6.3 A-D converter application examples
(1) Conversion of analog input voltage
Outline : The analog input voltage input from a sensor is converted to digital values.
Figure 2.6.7 shows a connection diagram, and Figure 2.6.8 shows the relevant registers setting.
P30
/AN
0
Sensor
3850 Group
Fig. 2.6.7 Connection diagram
Specifications : •The analog input voltage input from a sensor is converted to digital values.
•P3 /AN pin is used as an analog input pin.
0
0
A-D control register (address 3416
)
b7
b0
ADCON
0
0 0
0
Analog input pin : P30/AN0 selected
A-D conversion start
A-D conversion register (high-order); (address 3616
)
b7
b0
(Read-only)
ADH
ADL
A-D conversion register (low-order); (address 3516
)
b7 b0
(Read-only)
A result of A-D conversion is stored (Note).
Note: After bit 4 of ADCON is set to “1”, read out that contents.
When reading 10-bit data, read address 003616 before address 003516
when reading 8-bit data, read address 003516 only.
;
Fig. 2.6.8 Relevant registers setting
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APPLICATION
2.6 A-D converter
An analog input signal from a sensor is converted to the digital value according to the relevant
registers setting shown by Figure 2.6.8. Figure 2.6.9 shows the control procedure for 8-bit read, and
Figure 2.6.10 shows the control procedure for 10-bit read.
✽ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
•P30/AN0 pin selected as analog input pin
•A-D conversion start
ADCON (address 3416
)
XXX0X000
2
0
•Judgment of A-D conversion completion
•Read out of conversion result
ADCON (address 3416), bit4 ?
1
Read out ADL (address 3516
)
Fig. 2.6.9 Control procedure for 8-bit read
✽ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
•P30/AN0 pin selected as analog input pin
•A-D conversion start
ADCON (address 3416
)
XXX0X000
2
0
•Judgment of A-D conversion completion
ADCON (address 3416), bit4 ?
1
•Read out of high-order digit (b9, b8) of conversion result
•Read out of low-order digit (b7 – b0) of conversion result
Read out ADH (address 3616
)
Read out ADL (address 3516
)
Fig. 2.6.10 Control procedure for 10-bit read
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APPLICATION
2.6 A-D converter
2.6.4 Notes on A-D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
✽ Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the VSS line
✽ Reason
If the AVSS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(XIN) is 500 kHz or more in middle-/high-speed mode.
• Do not execute the STP instruction.
• When the A-D converter is operated at low-speed mode, f(XIN) do not have the lower limit of
frequency, because of the A-D converter has a built-in self-oscillation circuit.
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APPLICATION
2.7 Watchdog timer
2.7 Watchdog timer
This paragraph explains the registers setting method and the notes relevant to the watchdog timer.
2.7.1 Memory map
Address
003916 Watchdog timer control register (WDTCON)
CPU mode register (CPUM)
003B16
Fig. 2.7.1 Memory map of registers relevant to watchdog timer
2.7.2 Relevant registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register
(WDTCON: address 3916)
b
0
1
2
3
4
5
6
Name
Watchdog timer H
(for read-out of high-order 6 bit)
Functions
At reset R W
1
1
1
1
1
1
0
✽
✽
✽
✽
✽
✽
STP instruction
disable bit
0: STP instruction enabled
1: STP instruction disabled
7
0
Watchdog timer H 0: Watchdog timer L
count source selection
bit
underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 2.7.2 Structure of Watchdog timer control register
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2.7 Watchdog timer
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register
(CPUM: address 3B16
)
b
0
Name
Functions
At reset R W
0
b1 b0
Processor mode
bits
00 : Single-chip mode
01 :
1
10 :
11 :
Not available
0
0
0 : 0 page
1 : 1 page
2 Stack page
selection bit
1
0
Fix this bit to “1”.
3
Port Xc switch bit
0: I/O port function
(stop oscillating)
1: XCIN-XCOUT oscillation
function
4
Main clock (XIN
-
0: Oscillating
1: Stopped
b7 b6
0
1
5
6
XOUT) stop bit
Main clock division
ratio selection bits
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
0
7
(low-speed mode)
1 1: not available
Fig. 2.7.3 Structure of CPU mode register
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2.7 Watchdog timer
2.7.3 Watchdog timer application examples
(1) Detection of program runaway
Outline: If program runaway occurs, let the microcomputer reset, using the internal timer for detection
of program runaway.
Specifications: •An underflow of watchdog timer H is judged to be program runaway, and the
microcomputer is returned to the reset status.
•Before the watchdog timer underflows, “0” is set into bits 6 and 7 of the watchdog
timer control register at every cycle in a main routine.
•High-speed mode is used as a main clock division ratio.
•An underflow signal of the watchdog timer L is supplied as the count source of
watchdog timer H.
Figure 2.7.4 shows a watchdog timer connection and division ratio setting; Figure 2.7.5 shows the
relevant registers setting; Figure 2.7.6 shows the control procedure.
Fixed
1/16
Watchdog timer L Watchdog timer H
1/256 1/256
f(XIN) = 8 MHz
Reset
circuit
Internal reset
RESET
STP instruction disable bit
STP instruction
Fig. 2.7.4 Watchdog timer connection and division ratio setting
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2.7 Watchdog timer
CPU mode register (address 3B16
)
b7
b0
1
CPUM
0
0
0
0
0
Processor mode: Single-chip mode
Fix to “1”
Main clock (XIN-XOUT): Operating
Main clock division ratio: f(XIN)/2 (high-speed mode)
Watchdog timer control register (address 3916
)
b7
b0
WDTCON
0
0
Watchdog timer H (for read-out of high-order 6 bits)
Enable STP instruction
Watchdog timer H count source: Watchdog timer L underflow
Fig. 2.7.5 Relevant registers setting
RESET
Initialization
•All interrupts disabled
SEI
CLT
•Processor mode: Single-chip mode
•Main clock f(XIN): Operating
CLD
CPUM (address 3B16)
000X1X002
•High-speed mode selected as main clock division ratio
:
:
•Interrupts enabled
CLI
WDTCON (address 3916), bit7, bit6
002
•Watchdog timer L underflow selected as Watchdog
timer H count source
•STP instruction enabled
(“FF16” is set to Watchdog timer H and Watchdog
timer L, respectively.)
Main processing
:
:
Fig. 2.7.6 Control procedure
2.7.4 Notes on watchdog timer
✽Make sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog
timer keeps counting during that term.
✽When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.
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2.8 Reset
2.8 Reset
2.8.1 Connection example of reset IC
VCC
1
Power source
5
Output
M62022L
RESET
Delay capacity
4
GND
3
0.1 µF
VSS
3850 Group
Fig. 2.8.1 Example of poweron reset circuit
Figure 2.8.2 shows the system example which switches to the RAM backup mode by detecting a drop of
the system power source voltage with the INT interrupt.
System power
source voltage
+5 V
VCC
+
7
VCC1
5
3
6
RESET
RESET
INT
2
1
INT
Cd
V
CC2
VSS
V1
3850 Group
GND
4
M62009L,M62009P,M62009FP
Fig. 2.8.2 RAM backup system
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2.8 Reset
2.8.2 Notes on RESET pin
(1) Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
✽ Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
(2) Reset release after power on
When releasing the reset after power on, such as power-on reset, release reset after XIN passes more
than 20 cycles in the state where the power supply voltage is 2.7 V or more and the XIN oscillation
is stable.
✽ Reason
To release reset, the RESET pin must be held at an “L” level for 20 cycles or more of XIN in the
state where the power source voltage is between 2.7 V and 5.5 V, and XIN oscillation is stable.
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2.9 Clock generating circuit
2.9 Clock generating circuit
This paragraph explains how to set the registers relevant to the clock generating circuit and describes an
application example.
2.9.1 Relevant registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM: address 3B16
1
)
b
0
Name
Functions
At reset R W
0
b1 b0
Processor mode
bits
00 : Single-chip mode
01 :
1
10 :
11 :
Not available
0
0
0 : 0 page
1 : 1 page
2 Stack page
selection bit
1
0
Fix this bit to “1”.
3
Port Xc switch bit
0: I/O port function
(stop oscillating)
1: XCIN-XCOUT oscillation
function
4
Main clock (XIN
-
0: Oscillating
1: Stopped
b7 b6
0
1
5
6
XOUT) stop bit
Main clock division
ratio selection bits
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
0
7
(low-speed mode)
1 1: not available
Fig. 2.9.1 Structure of CPU mode register
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2.9 Clock generating circuit
2.9.2 Clock generating circuit application example
(1) Status transition during power failure
Outline: The clock counts up every second by using the timer interrupt during a power failure.
Input port
Power failure detection signal
(Note)
3850 Group
Note: A signal is detected when input to input port, interrupt
input pin, or analog input pin.
Fig. 2.9.2 Connection diagram
Specifications: •Reducing power dissipation as low as possible while maintaining clock function
•Clock: f(XIN) = 8 MHz, f(XCIN) = 32.768 kHz
•Port processing
Input port: Fixed to “H” or “L” level externally.
Output port: Fixed to output level that does not cause current flow to the external.
(Example) Fix to “H” for an LED circuit that turns on at “L” output
level.
I/O port: Input port → Fixed to “H” or “L” level externally.
Output port → Output of data that does not consume current
V
REF pin: Stop VREF current dissipation by terminating A-D conversion operation.
Figure 2.9.3 shows the status transition diagram during power failure and Figure 2.9.4 shows the
setting of relevant registers.
Reset released
Power failure detected
XIN
X
CIN
Middle-speed
mode
Low-speed mode
High-speed mode
Internal system clock
After detection, change internal system clock to
low-speed mode and stop oscillating XIN-XOUT
Change internal system
clock to high-speed mode
XCIN-XCOUT oscillation function selected
Fig. 2.9.3 Status transition diagram during power failure
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2.9 Clock generating circuit
CPU mode register (address 3B16)
b7
b0
0 0 0 0 1
0 0
CPUM
Main clock: High-speed mode (f(XIN)/2) (Note 1)
CPU mode register (address 3B16)
b7
b0
0 0 0 1 1
(Note 2)
0 0
CPUM
Port XC: XCIN–XCOUT oscillation function
CPU mode register (address 3B16)
b7
b0
0 0
1 0 0 1 1
CPUM
Internal system clock: Low-speed mode (f(XCIN)/2)
CPU mode register (address 3B16)
b7
b0
1 0 1 1 1
0 0
CPUM
Main clock f(XIN): Stopped
Notes 1: This setting is necessary only when selecting the high-speed mode.
2: When selecting the middle-speed mode, bit 6 is “1”.
Fig. 2.9.4 Setting of relevant registers
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2.9 Clock generating circuit
Control procedure: To prepare for a power failure, set the relevant registers in the order shown
below.
✽X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
CPUM (address 3B16), bit7, bit 6
CPUM (address 3B16), bit 4
0, 0
1
When selecting main clock f(XIN)/2 (high-speed mode)
Port XC: XCIN-XCOUT oscillation function
N
Detect power failure ?
Y
≈
Internal system clock: f(XCIN)/2 (low-speed mode)
Main clock f(XIN) oscillation stopped
1, 0 (Note)
1 (Note)
CPUM (address 3B16), bit7, bit 6
CPUM (address 3B16), bit5
At power failure, clock count is performed during
timer interrupt processing (every second).
Set timer interrupt to occurs every second.
Execute WIT instruction.
N
Return condition from power failure
completed ?
Y
Return processing from power failure
Note: Do not switch simultaneously.
≈
Fig. 2.9.5 Control procedure
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2.10 Standby function
2.10 Standby function
The 3850 group is provided with standby functions to stop the CPU by software and put the CPU into the
low-power operation.
The following two types of standby functions are available.
•Stop mode using STP instruction
•Wait mode using WIT instruction
2.10.1 Relevant registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG
(MISRG: address 3816)
b
0
Name
Functions
At reset R W
Oscillation stabilizing 0: Automatically set (Note 1)
time set after STP
0
1: Autimatically set disabled
instruction released bit
0: Not set automatically
1: Automatic switching
enabled (Note 2)
Middle-speed mode
automatic switch set
bit
0
0
0
1
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
2 Middle-speed mode
automatic switch
wait time set bit
Middle-speed mode 0: Invalid
3
automatic switch
start bit
1: Automatic switch start
(Note 2)
(Depending on
program)
4
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
0
0
0
✕
✕
✕
✕
Notes 1: “0116” is set to Timer 1, “FF16” is set to Prescaler 12.
2: When automatic switch to middle-speed mode from low-speed mode occurs,
the values of CPU mode register (003B16) change.
Fig. 2.10.1 Structure of MISRG
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2.10 Standby function
2.10.2 Stop mode
The stop mode is set by executing the STP instruction. In the stop mode, the oscillation of both clocks
(XIN–XOUT, XCIN–XCOUT) stop and the internal clock φ stops at the “H” level. The CPU stops and peripheral
units stop operating. As a result, power dissipation is reduced.
(1) State in stop mode
Table 2.10.1 shows the state in the stop mode.
Table 2.10.1 State in stop mode
Item
State in stop mode
Oscillation
CPU
Stopped.
Stopped.
Stopped at “H” level.
Internal clock φ
I/O ports P0–P4
Timer
Retains the state at the STP instruction execution.
Stopped. (Timers 1, 2, X, Y)
However, Timers X and Y can be operated in the event counter
mode.
Stopped.
PWM
Stopped.
Watchdog timer
Stopped.
Serial I/O1, Serial I/O2
However, these can be operated only when an external clock
is selected.
Stopped.
A-D converter
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2.10 Standby function
(2) Release of stop mode
The stop mode is released by a reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
✽Restoration by reset input
The stop mode is released by holding the RESET pin to the “L” input level during the stop mode.
Oscillation is started when all ports are in the input state and the stop mode of the main clock (XIN
OUT) is released.
-
X
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) (Note) is required. The input of the RESET pin should be held at the “L” level until
oscillation stabilizes.
When the RESET pin is held at the “L” level for 20 cycles or more of XIN after the oscillation has
stabilized, the microcomputer will go to the reset state. After the input level of the RESET pin is
returned to “H”, the reset state is released in approximately 10.5 to 18.5 cycles of the XIN input.
Figure 2.10.2 shows the oscillation stabilizing time at restoration by reset input.
At release of the stop mode by reset input, the internal RAM retains its contents previous to the
reset. However, the previous contents of the CPU register and SFR are not retained.
For more details concerning reset, refer to “2.8 Reset”.
Note: For the setting of oscillation stabilizing time, refer to MISRG (address 003816).
Oscillation
20 cycles or
stabilizing time more of XIN
Stop mode
Operating mode
Vcc
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
RESET
XIN
(Note)
Execute Stop instruction
Note: Some cases may occur in which no waveform is input to XIN (in low-speed mode).
Fig. 2.10.2 Oscillation stabilizing time at restoration by reset input
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2.10 Standby function
✽Restoration by interrupt request
The occurrence of an interrupt request in the stop mode releases the stop mode. As a result,
oscillation is resumed. The interrupts available for restoration are:
•INT
0
–INT
3
•CNTR
0
, CNTR
1
•Serial I/O (1, 2) using an external clock
•Timer X, Y using an external event count
However, when using any of these interrupt requests for restoration from the stop mode, in order
to enable the selected interrupt, you must execute the STP instruction after setting the following
conditions.
[Necessary register setting]
✽ Interrupt disable flag I = “0” (interrupt enabled)
✽ Timer 1 interrupt enable bit = “0” (interrupt disabled)
✽ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request
issued)
✽ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) is required. For restoration by an interrupt request, waiting time prior to supplying
internal clock φ to the CPU is automatically generated✽2 by Prescaler 12 and Timer 1✽1. This
waiting time is reserved as the oscillation stabilizing time on the system clock side. The supply of
internal clock φ to the CPU is started at the Timer 1 underflow.
Figure 2.10.3 shows an execution sequence example at restoration by the occurrence of an INT
interrupt request.
0
✽1: If the STP instruction is executed when the oscillation stabilizing time set after STP instruction
released bit is “0”, “FF16” and “0116” are automatically set in the Prescaler 12 counter/latch and
Timer 1 counter/latch, respectively. When the oscillation stabilizing time set after STP instruction
released bit is “1”, nothing is automatically set to either Prescaler 12 or Timer 1. For this
reason, any suitable value can be set to Prescaler 12 and Timer 1 for the oscillation stabilizing
time.
✽2: Immediately after the oscillation is started, the count source is supplied to the prescaler 12
so that a count operation is started.
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2.10 Standby function
✽When restoring microcomputer from stop mode by INT
Stop mode
0
interrupt (rising edge selected)
Oscillation stabilizing time
X
IN or XCIN
X
X
IN; “H”
(System clock)
CIN; in high-impedance state
INT pin
0
512 counts
“FF16
”
Prescaler 12 counter
Timer 1 counter
“0116
”
INT
0
interrupt request bit
Peripheral device
CPU
Operating
Operating
Operating
Stopped
Stopped
Operating
Execute STP INT
instruction
0
interrupt signal
512 counts down by
prescaler 12
Start supplying internal
clock φ to CPU
input (INT interrupt
0
request occurs)
Oscillation start
Prescaler 12 count start
Accept INT
request
0
interrupt
Note: f(XIN)/16 or f(XCIN)/16 is input as the prescaler 12 count source.
Fig. 2.10.3 Execution sequence example at restoration by occurrence of INT interrupt request
0
(3) Notes on using stop mode
✽Register setting
Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the
stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP
instruction released bit is “0”)
✽Clock restoration
After restoration from the stop mode to the normal mode by an interrupt request, the contents of
the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both
main clock and sub clock were oscillating before execution of the STP instruction, the oscillation
of both clocks is resumed at restoration.
In the above case, when the main clock side is set as a system clock, the oscillation stabilizing
time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode.
At this time, note that the oscillation on the sub clock side may not be stabilized even after the
lapse of the oscillation stabilizing time of the main clock side.
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2.10 Standby function
2.10.3 Wait mode
The wait mode is set by execution of the WIT instruction. In the wait mode, oscillation continues, but the
internal clock φ stops at the “H” level.
The CPU stops, but most of the peripheral units continue operating.
(1) State in wait mode
The continuation of oscillation permits clock supply to the peripheral units. Table 2.10.2 shows the
state in the wait mode.
Table 2.10.2 State in wait mode
State in wait mode
Item
Operating.
Oscillation
CPU
Stopped.
Internal clock φ
I/O ports P0–P4
Timer
Stopped at “H” level.
Retains the state at the WIT instruction execution.
Operating.
Operating.
Operating.
Operating.
Operating.
PWM
Watchdog timer
Serial I/O1, Serial I/O2
A-D converter
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2.10 Standby function
(2) Release of wait mode
The wait mode is released by reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
In the wait mode, oscillation is continued, so an instruction can be executed immediately after the
wait mode is released.
✽Restoration by reset input
The wait mode is released by holding the input level of the RESET pin at “L” in the wait mode.
Upon release of the wait mode, all ports are in the input state, and supply of the internal clock
φ to the CPU is started. To reset the microcomputer, the RESET pin should be held at an “L” level
for 20 cycles or more of XIN. The reset state is released in approximately 10.5 cycles to 18.5 cycles
of the XIN input after the input of the RESET pin is returned to the “H” level.
At release of wait mode, the internal RAM retains its contents previous to the reset. However, the
previous contents of the CPU register and SFR are not retained.
Figure 2.10.4 shows the reset input time.
For more details concerning reset, refer to “2.8 Reset”.
Operating mode
Wait mode
Vcc
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
20 cycles of XIN
RESET
X
IN
(Note)
Execute WIT instruction
Note: Some cases may occur in which no waveform is input to XIN (in low-speed mode).
Fig. 2.10.4 Reset input time
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2.10 Standby function
✽Restoration by interrupt request
In the wait mode, the occurrence of an interrupt request releases the wait mode and supply of the
internal clock φ to the CPU is started. At the same time, the interrupt request used for restoration
is accepted, so the interrupt processing routine is executed.
However, when using an interrupt request for restoration from the wait mode, in order to enable
the selected interrupt, you must execute the WIT instruction after setting the following conditions.
[Necessary register setting]
✽ Interrupt disable flag I = “0” (interrupt enabled)
✽ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request
issued)
✽ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
(3) Notes on wait mode
✽Clock restoration
If the wait mode is released by a reset when XCIN is set as the system clock and XIN oscillation is
stopped during execution of the WIT instruction, XCIN oscillation stops, XIN oscillations starts, and
X
IN is set as the system clock.
In the above case, the RESET pin should be held at “L” until the oscillation is stabilized.
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2.11 Flash memory mode
2.11 Flash memory mode
This paragraph explains the registers setting method and the notes relevant to the flash memory version.
2.11.1 Overview
The functions of the flash memory version are similar to those of the mask ROM version except that the
flash memory is built-in and some of the SFR area differ from that of the mask ROM version (refer to
“2.11.2 Memory map”).
In the flash memory version, the built-in flash memory can be programmed or erased by using the following
three modes.
• CPU rewrite mode
• Parallel I/O mode
• Standard serial I/O mode
2.11.2 Memory map
M38507F8FP/SP have 32 Kbytes of built-in flash memory.
Figure 2.11.1 shows the memory map of the flash memory version.
000016
SFR area
004016
Internal RAM
area
(1 Kbyte)
RAM
043F16
044016
User ROM area
800016
Not used
SFR area
0FF016
0FFF16
100016
Not used
32 Kbytes
800016
808016
Reserved ROM area
Built-in flash memory
area
(32 Kbytes)
FFFF16
FFFF16
Boot ROM area
4 Kbytes
F00016
FFFF16
Note: Access to boot ROM area
Pararell I/O mode
Read/Write avilable
Read only available
Read only available
CPU rewrite mode
Standard serial mode
Fig. 2.11.1 Memory map of flash memory version for 3850 Group
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2.11 Flash memory mode
2.11.3 Relevant registers
Address
0FFE16 Flash memory control register (FMCR)
Fig. 2.11.2 Memory map of registers relevant to flash memory
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register
(FMCR : address 0FFE16
)
b
Name
Functions
At reset R W
1
0 : Busy (being written or
erased)
0 RY/BY status flag
1 : Ready
0
1
CPU rewrite mode 0 : Normal mode (Software
select bit (Note 1)
commands invalid)
1 : CPU rewrite mode
(Software commands
acceptable)
2
CPU rewrite mode
entry flag
0: Normal mode
1: CPU rewrite mode
0
Flash memory reset
bit (Note 2)
User area/Boot
area selection bit
3
4
0: Normal operation
1: Reset
0: User ROM area
1: Boot ROM area
0
0
5 Nothing is arranged for these bits. When write, Undefined
set “0”. When these bits are read out, the
contents are undefined.
Undefined
Undefined
6
7
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession.
2: In order to perform flash memory reset by setting of this bit, set
this bit to “1” in state of the CPU rewriting mode select bit = “1”,
and then set to “0” to release the reset state.
Fig. 2.11.3 Structure of Flash memory control register
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2.11 Flash memory mode
2.11.4 Parallel I/O mode
In the parallel I/O mode, program/erase to the built-in flash memory can be performed by a EPROM
programmer (EFP-I).
The memory area of program/erase is from 0F00016 to 0FFFF16 (boot ROM area) or from 0800016 to
0FFFF16 (user ROM area). Be especially careful when erasing; if the memory area is not set correctly, the
products will be damaged eternally.
Table 2.11.1 shows the setting of programmers when programming in the parallel I/O mode.
•EFP-I provided by Suisei Electronics System Co., Ltd. (http://www.suisei.co.jp/index_e.htm)
(product available in Asia and Oceania only)
Table 2.11.1 Setting of programmers when parallel programming
Products
Parallel unit
EF3850F-42E
EF3850F-42S
Boot ROM area
User ROM area
M38507F8FP
M38507F8SP
0F00016 to 0FFFF16
0800016 to 0FFFF16
2.11.5 Standard serial I/O mode
Table 2.11.2 shows a pin connection example (4 wires) between the programmer (EFP-I; Serial unit
EF1SRP-01U is required additionally) and the microcomputer when programming in the serial I/O mode.
•EFP-I provided by Suisei Electronics System Co., Ltd. (http://www.suisei.co.jp/index_e.htm)
(product available in Asia and Oceania only)
Table 2.11.2 Connection example to programmer when serial programming (4 wires)
3850 Group flash memory version
EFP-I (EF1SRP-01U)
EF1RP-01U side
Signal name
Function
Pin name
Pin number
connector Line number
9
T_SCLK1
T_RXD
Transfer clock input
Serial data input
P2
P2
P2
P2
6
5
4
7
/SCLK1
/TxD
/RxD
10
11
12
9
11
10
T_TXD
Serial data output
Transmit/Receive enable output
5 V input
12
T_BUSY
/CNTR /SRDY1
0
3
T_VPP
CNVSS
15
18
1
14
T_RESET
T_VDD (Note 2)
GND (Note 3)
Reset input
RESET (Note 1)
4
Target board power source monitor input
GND
V
V
CC (Note 2)
1, 2, 15, 16
SS, AVSS (Note 3)
21, 3
Notes 1: Since reset release after write verification is not performed, when operating MCU after writing,
separate a target connection cable.
2: Supply Vcc of EFP-I side from user side so that the power supply voltage of the output buffer used
by the EFP-I side becomes the same as user side power supply voltage (Vcc).
3: Four pins (No. 1, 2, 15, and 16) of the EF1SRP-01U side connector are prepared for GND signal.
When connecting with a target board, although connection of only one pin does not have a
problem, we recommend connecting with two or more pins.
3850 Group (Spec. H) User’s Manual
2-105
APPLICATION
2.11 Flash memory mode
2.11.6 CPU rewrite mode
In the CPU rewrite mode, issuing software commands through the Central Processing Unit (CPU) can
rewrite the built-in flash memory. Accordingly, the contents of the built-in flash memory can be rewritten
with the microcomputer itself mounted on board, without using the programmer.
Store the rewrite control program to the built-in flash memory in advance. The built-in flash memory cannot
be read in the CPU rewrite mode. Accordingly, after transferring the rewrite control program to the internal
RAM, execute it on the RAM.
The following commands can be used in the CPU rewrite mode: read array, read status register, clear
status register, program, erase all block, and block erase. For details concerning each command, refer to
“CHAPTER 1 Flash memory mode (CPU rewrite mode)”.
(1) CPU rewrite mode beginning/release procedures
Operation procedure in the CPU rewrite mode for the built-in flash memory is described below.
As for the control example, refer to “2.11.7 (2) Control example in the CPU rewrite mode”.
[Beginning procedure]
➀ Apply 5 V±10 % to the CNVSS/VPP pin (at selecting boot ROM area).
➀ Release reset.
➀ Set bits 6 and 7 (main clock division ratio selection bits) of the CPU mode register.
➀ After CPU rewrite mode control program is transferred to internal RAM, jump to this control
program on RAM. (The following operations are controlled by this control program).
➀ Apply 5 V±10 % to the CNVSS/VPP pin (in single-chip mode).
➀ Set “1” to the CPU rewrite mode select bit (bit 1 of address 0FFE16).
For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession.
➀ Read the CPU rewrite mode entry flag (bit 2 of address 0FFE16) to confirm that the CPU rewrite
mode is set to “1”.
➀ Flash memory operations are executed by using software commands.
Note: The following procedures are also necessary.
• Control for data which is input from the external (serial I/O etc.) and to be programmed
to the flash memory.
• Initial setting for ports, etc.
• Writing to the watchdog timer
[Release procedure]
➀ Execute the read command or set the flash memory reset bit (bit 3 of address 0FFE16).
➀ Set the CPU rewrite mode select bit (bit 0 of address 0FFE16) to “0”.
3850 Group (Spec. H) User’s Manual
2-106
APPLICATION
2.11 Flash memory mode
Also, execute the following processing before the CPU reprogramming mode is selected so that
interrupts will not occur during the CPU reprogramming mode.
• Set the interrupt disable flag (I) to “1”
When the watchdog timer has already started, write to the watchdog timer control register (address
1E16) periodically during the CPU reprogramming mode in order not to generate the reset by the
underflow of the watchdog timer H.
During the program or erase execution, watchdog timer is automatically cleared. Accordingly, the
inernal reset by underflow does not occur.
When the interrupt request or reset occurs in the CPU reprogramming mode, the microcomputer
enters the following state;
• Interrupt occurs
This may cause a program runaway because the read from the flash memory which has the interrupt
vector area cannot be performed.
• Underflow of watchdog timer H, reset
This may cause a microcomputer reset; the built-in flash memory control circuit and the flash memory
control register are reset. When reset state is released with CNVss = “H”, CPU starts in the boot
mode.
Also, when the above interrupt and reset occur during program/erase, error data may still exist after
reset release because the reprogramming of the flash memory is not completed, so that reprogramming
of the flash memory in the parallel I/O mode or serial I/O mode is required.
3850 Group (Spec. H) User’s Manual
2-107
APPLICATION
2.11 Flash memory mode
2.11.7 Flash memory mode application examples
The control pin processing example on the system board in the serial I/O mode and the control example
in the CPU rewrite mode are described below.
(1) Control pin connection example on the system board in serial I/O mode
As shown in Figure 2.11.4, in the serial I/O mode, the built-in flash memory can be rewritten with the
microcomputer mounted on board. Connection examples of control pins (P2
4
/RxD, P2 /TxD,
5
P2 , CNVSS, and RESET pin) in the serial I/O mode are described below.
6
/SCLK1, P2
7
/SRDY1, P4
1
RS-232C
Serial programmer
M
3
8
5
0
7
F
8
F
P
/
S
P
Fig. 2.11.4 Rewrite example of built-in flash memory in serial I/O mode
3850 Group (Spec. H) User’s Manual
2-108
APPLICATION
2.11 Flash memory mode
➀ When control signals are not affected to user system circuit
When the control signals in the serial I/O mode are not used or not affected to the user system
circuit, they can be connected as shown in Figure 2.11.5.
Target board
➀1
Not used or to user system circuit
M38507F8FP/SP
TXD(P25)
➀2
SCLK1(P26)
VCC
RXD(P24)
BUSY(P27)
(P41)
AVSS
VPP(CNVSS)
VSS
RESET
X
IN
XOUT
User reset signal (Low active)
➀1: When not used, set to input mode and pull up or pull down, or set to output mode and open.
➀2: It is necessary to apply Vcc to SCLK1 (P2 ) pin only when reset is released in the serial I/O mode.
6
Fig. 2.11.5 Connection example in serial I/O mode (1)
➀ When control signals are affected to user system circuit-1
Figure 2.11.6 shows an example that the jumper switch cut-off the control signals not to supply
to the user system circuit in the serial I/O mode.
Target board
To user system circuit
M38507F8FP/SP
TXD(P25)
➀
SCLK1(P26)
VCC
R
XD(P24)
B
USY(P27)
AVSS
(P41)
VSS
V
PP(CNVSS)
RESET
XIN
XOUT
User reset signal (Low active)
➀: It is necessary to apply Vcc to SCLK1 (P26) pin only when reset is released in the serial I/O mode.
Fig. 2.11.6 Connection example in serial I/O mode (2)
3850 Group (Spec. H) User’s Manual
2-109
APPLICATION
2.11 Flash memory mode
➀ When control signals are affected to user system circuit-2
Figure 2.11.7 shows an example that the analog switch (74HC4066) cut-off the control signals not
to supply to the user system circuit in the serial I/O mode.
Target board
74HC4066
To user system circuit
M38507F8FP/SP
T
XD(P25)
➀
S
CLK1(P26)
VCC
RXD(P24)
B
USY(P27)
(P41)
AVSS
V
PP(CNVss)
VSS
RESET
X
IN
XOUT
User reset signal (Low active)
➀: It is necessary to apply Vcc to SCLK1 (P26) pin only when reset is released in the serial I/O mode.
Fig. 2.11.7 Connection example in serial I/O mode (3)
3850 Group (Spec. H) User’s Manual
2-110
APPLICATION
2.11 Flash memory mode
(2) Control example in CPU rewrite mode
In this example, data is received by using serial I/O, and the data is programmed to the built-in flash
memory in the CPU rewrite mode.
Figure 2.11.8 shows an example of the reprogramming system for the built-in flash memory in the
CPU rewrite mode. Figure 2.11.9 shows the CPU rewrite mode beginning/release flowchart.
M38507F8FP/SP
P4
1
V
CC
Clock input
BUSY output
Data input
S
S
CLK1
RDY1(BUSY
)
AVSS
R
X
D
VSS
Data output
T
X
D
RESET
CNVSS
V
PP power source input
User reset signal
(Note 1)
Note 1: Apply 4.5 to 5.5 V to the VPP power source.
Fig. 2.11.8 Example of rewrite system for built-in flash memory in CPU rewrite mode
3850 Group (Spec. H) User’s Manual
2-111
APPLICATION
2.11 Flash memory mode
START
Single-chip mode or boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control
program to built-in RAM
Jump to transferred control program on RAM
(The following operations are controlled by
the control program on this RAM)
Set “1” to CPU rewrite mode select bit (by
writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read command or set flash
memory reset bit (by writing “0” and then
“1” in succession) (Note 3)
Set “0” to CPU rewrite mode select bit
END
Notes 1: When MCU starts in the single-chip mode, it is necessary to apply
5 V ± 10 % to dhe CNVss pin until confirming of the CPU rewrite
mode entry flag.
2: Set bits 6 and 7 (main clock division ratio selection bits) of the
CPU mode register (address 003B16).
3: Before releasing the CPU rewrite mode after completing erase or
program operation, always be sure to execute a read command or
reset the flash memory.
Fig. 2.11.9 CPU rewrite mode beginning/release flowchart
3850 Group (Spec. H) User’s Manual
2-112
APPLICATION
2.11 Flash memory mode
2.11.8 Notes on CPU rewrite mode
(1) Operation speed
During CPU rewrite mode, set the internal clock φ 4 MHz or less using the main clock division ratio
selection bits (bits 6 and 7 of address 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during the CPU
rewrite mode.
(3) Interrupts inhibited against use
The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data
of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog
timer underflow does not happen, because of watchdog timer is always clearing during program or
erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = “H” when reset is released, boot mode is active. So the
program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area.
3850 Group (Spec. H) User’s Manual
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APPLICATION
2.11 Flash memory mode
MEMORANDUM
3850 Group (Spec. H) User’s Manual
2-114
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 List of registers
3.6 Package outline
3.7 Machine instructions
3.8 List of instruction code
3.9 SFR memory map
3.10 Pin configurations
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
Parameter
Conditions
Ratings
Unit
V
VCC
Power source voltage
–0.3 to 6.5
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF
VI
–0.3 to VCC +0.3
V
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to 5.8
VI
VI
VI
V
V
V
All voltages are based on VSS.
Output transistors are cut off.
–0.3 to VCC +0.3
–0.3 to VCC +0.3
Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
–0.3 to VCC +0.3
VO
V
Output voltage P22, P23
Power dissipation
–0.3 to 5.8
1000 (Note)
–20 to 85
VO
V
mW
°C
Pd
Ta = 25 °C
Operating temperature
Storage temperature
Topr
Tstg
–40 to 125
°C
Note : The rating becomes 300mW at the 42P2R-A/E package.
3850 Group (Spec. H) User’s Manual
3-2
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions (1)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
4.0
Typ.
5.0
5.0
0
Max.
5.5
8 MHz (high-speed mode)
Power source voltage
Power source voltage
VCC
V
8 MHz (middle-speed mode), 4 MHz (high-speed mode)
2.7
5.5
VSS
VREF
AVSS
VIA
V
V
V
V
V
V
V
V
V
A-D convert reference voltage
Analog power source voltage
Analog input voltage
2.0
VCC
0
AN0–AN4
AVSS
VCC
VCC
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
RESET, XIN, CNVSS
VIH
0.8VCC
“H” input voltage
VIH
0.8VCC
VCC
VIL
0
0
0
“L” input voltage
“L” input voltage
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
0.2VCC
0.2VCC
0.16VCC
VIL
RESET, CNVSS
XIN
VIL
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
“H” total peak output current (Note)
“H” total peak output current (Note)
“L” total peak output current (Note)
“L” total peak output current (Note)
“L” total peak output current (Note)
P00–P07, P10–P17, P30–P34
P20, P21, P24–P27, P40–P44
P00–P07, P30–P34
–80
–80
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
P10–P17
120
80
P20–P27,P40–P44
“H” total average output current (Note) P00–P07, P10–P17, P30–P34
“H” total average output current (Note) P20, P21, P24–P27, P40–P44
–40
–40
40
“L” total average output current (Note)
“L” total average output current (Note)
P00–P07, P30–P34
P10–P17
60
“L” total average output current (Note) P20–P27,P40–P44
40
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
3850 Group (Spec. H) User’s Manual
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions (2)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
mA
Min.
Max.
–10
IOH(peak)
“H” peak output current
(Note 1)
P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44
IOL(peak)
IOL(peak)
“L” peak output current (Note 1) P00–P07, P20–P27, P30–P34, P40–P44
“L” peak output current (Note 1) P10–P17
10
20
mA
mA
“H” average output current
(Note 2)
P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44
IOH(avg)
IOL(avg)
–5
mA
“L” average output current (Note 2) P00–P07, P20–P27, P30–P34, P40–P44
“L” average output current (Note 2) P10–P17
5
15
8
mA
mA
IOL(avg)
f(XIN)
Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3)
Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3)
MHz
MHz
f(XIN)
4
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
3.1.3 Electrical characteristics
Table 3.1.4 Electrical characteristics (1)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Test conditions
Min.
Max.
VOH
VOL
VOL
“H” output voltage
IOH = –10 mA
VCC–2.0
V
V
V
V
V
V
V
V
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
(Note)
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 2.7–5.5 V
IOL = 10 mA
VCC–1.0
“L” output voltage
2.0
1.0
2.0
1.0
P00–P07, P20–P27, P30–P34,
P40–P44
VCC = 4.0–5.5 V
IOL = 1.0 mA
VCC = 2.7–5.5 V
IOL = 20 mA
“L” output voltage
P10–P17
VCC = 4.0–5.5 V
IOL = 10 mA
VCC = 2.7–5.5 V
VT+–VT–
VT+–VT–
Hysteresis
0.4
0.5
0.5
CNTR0, CNTR1, INT0–INT3
Hysteresis
RxD, SCLK1, SCLK2, SIN2
____________
VT+–VT–
IIH
Hysteresis
RESET
V
“H” input current
VI = VCC
5.0
µA
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
____________
IIH
IIH
IIL
“H” input current RESET, CNVSS
“H” input current XIN
VI = VCC
VI = VCC
VI = VSS
5.0
µA
µA
µA
4
“L” input current
–5.0
P00–P07, P10–P17, P20–P27
P30–P34, P40–P44
____________
IIL
“L” input current RESET,CNVSS
VI = VSS
–5.0
5.5
µA
µA
V
IIL
“L” input current
XIN
VI = VSS
–4
VRAM
RAM hold voltage
When clock stopped
2.0
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
3850 Group (Spec. H) User’s Manual
3-4
APPENDIX
3.1 Electrical characteristics
Table 3.1.5 Electrical characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Test conditions
Symbol
Parameter
Unit
Typ.
Max.
13
Min.
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
mA
mA
6.8
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
1.6
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Except
M38507F8FP/SP
200
µA
µA
µA
60
M38507F8FP/SP
250
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Except
M38507F8FP/SP
40
55
20
70
20
M38507F8FP/SP
µA
µA
Except
M38507F8FP/SP
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
ICC
Power source current
f(XCIN) = 32.768 kHz
Output transistors “off”
M38507F8FP/SP
µA
µA
µA
150
5.0
Except
M38507F8FP/SP
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
10.0
7.0
M38507F8FP/SP
20
Middle-speed mode
f(XIN) = 8 MHz
f(XCIN) = stopped
Output transistors “off”
mA
4.0
Middle-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = stopped
mA
1.5
Output transistors “off”
Increment when A-D conversion is
executed
f(XIN) = 8 MHz
µA
800
0.1
All oscillation stopped
(in STP state)
Output transistors “off”
1.0
10
µA
µA
Ta = 25 °C
Ta = 85 °C
3850 Group (Spec. H) User’s Manual
3-5
APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter characteristics
Table 3.1.6 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
10
–
–
Resolution
bit
Absolute accuracy (excluding quantization error)
Conversion time
±4
LSB
High-speed mode,
Middle-speed mode
tCONV
61
2tc(XIN)
Low-speed mode
40
35
µs
kΩ
µA
RLADDER
IVREF
Ladder resistor
VREF = 5.0 V
VREF “on”
VREF “off”
Reference power source input current
50
150
200
5.0
5.0
II(AD)
A-D port input current
0.5
µA
3850 Group (Spec. H) User’s Manual
3-6
APPENDIX
3.1 Electrical characteristics
3.1.5 Timing requirements and switching characteristics
Table 3.1.7 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
20
Typ.
Max.
Reset input “L” pulse width
XIN cycle
ns
tW(RESET)
tC(XIN)
External clock input cycle time
125
50
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
ns
tWH(XIN)
50
ns
tWL(XIN)
200
80
ns
tC(CNTR)
ns
tWH(CNTR)
tWL(CNTR)
tWH(INT)
80
ns
80
ns
80
ns
tWL(INT)
800
370
370
220
100
1000
400
400
200
200
ns
tC(SCLK1)
ns
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
ns
ns
ns
Serial I/O1 input hold time
ns
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
ns
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
ns
ns
ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 3.1.8 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
20
Max.
XIN cycle
ns
tW(RESET)
tC(XIN)
Reset input “L” pulse width
External clock input cycle time
250
100
100
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
ns
tWH(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
ns
tWL(XIN)
ns
tC(CNTR)
ns
tWH(CNTR)
tWL(CNTR)
tWH(INT)
ns
ns
ns
tWL(INT)
ns
tC(SCLK1)
ns
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
ns
ns
ns
Serial I/O1 input hold time
ns
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
ns
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
ns
ns
ns
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
3850 Group (Spec. H) User’s Manual
3-7
APPENDIX
3.1 Electrical characteristics
Table 3.1.9 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
140
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tC(SCLK1)/2–30
tC(SCLK1)/2–30
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig.3.1.1
–30
30
30
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tC(SCLK2)/2–160
tC(SCLK2)/2–160
200
0
30
30
30
tr (CMOS)
10
10
tf (CMOS)
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Table 3.1.10 Switching characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Unit
Parameter
Test conditions
Min.
Typ.
Max.
350
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
tC(SCLK1)/2–50
tC(SCLK1)/2–50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
Fig.3.1.1
–30
50
50
tf (SCLK1)
tC(SCLK2)/2–240
tC(SCLK2)/2–240
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
400
0
50
50
50
20
20
tr (CMOS)
tf (CMOS)
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
3850 Group (Spec. H) User’s Manual
3-8
APPENDIX
3.1 Electrical characteristics
Measurement output pin
100 pF
CMOS output
Fig. 3.1.1 Circuit for measuring output switching characteristics
3850 Group (Spec. H) User’s Manual
3-9
APPENDIX
3.1 Electrical characteristics
tC(CNTR)
t
WH(CNTR)
t
WL(CNTR)
CNTR
CNTR
0
1
0.8VCC
0.2VCC
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT0
to INT
3
tW(RESET)
0.8VCC
RESET
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
X
IN
0.2VCC
t
C(SCLK1),
t
C(SCLK2)
t
WL(SCLK1),
tWL(SCLK2
)
t
WH(SCLK1), WH(SCLK2)
t
t
r
tf
S
S
CLK1
CLK2
0.8VCC
0.2VCC
t
t
h(SCLK1
-
-
RxD),
t
t
su(R
x
D
-
S
CLK1),
CLK2
h(SCLK2
S
IN2)
su(SIN2
-
S
)
R D
X
0.8V
0.2VCCCC
S
IN2
t
t
d(SCLK1-T
XD),
t
t
v(SCLK1-T
XD),
d(SCLK2-SOUT2
)
v(SCLK2-SOUT2
)
TXD
SOUT2
Fig. 3.1.2 Timing diagram
3850 Group (Spec. H) User’s Manual
3-10
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
Standard characteristics described below are just examples of the 3850 Group (spec. H)’s characteristics
and are not guaranteed. For rated values, refer to “3.1 Electrical characteristics”.
3.2.1 Flash memory version power source current standard characteristics
Figure 3.2.1, Figure 3.2.2, Figure 3.2.3, Figure 3.2.4, and Figure 3.2.5 show flash memory version (M38507F8)
power source current standard characteristics.
Measuring conditions : 25 °C, f(XIN) = 8 MHz, in high-speed mode
6.0
5.0
4.0
Standard mode
3.0
2.0
Wait mode
1.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.1 Flash memory version power source current standard characteristics (in high-speed mode,
f(XIN) = 8 MHz)
Measuring conditions : 25 °C, f(XIN) = 4 MHz, in high-speed mode
3.0
2.5
2.0
Standard mode
1.5
1.0
Wait mode
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.2 Flash memory version power source current standard characteristics (in high-speed mode,
f(XIN) = 4 MHz)
3850 Group (Spec. H) User’s Manual
3-11
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(XIN) = 8 MHz, in middle-speed mode
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Standard mode
Wait mode
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.3 Flash memory version power source current standard characteristics (in middle-speed
mode, f(XIN) = 8 MHz)
Measuring conditions : 25 °C, f(XIN) = 4 MHz, in middle-speed mode
1.6
1.4
1.2
1.0
Standard mode
0.8
0.6
0.4
Wait mode
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.4 Flash memory version power source current standard characteristics (in middle-speed
mode, f(XIN) = 4 MHz)
3850 Group (Spec. H) User’s Manual
3-12
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(XIN) = 32 kHz, in low-speed mode
250
200
150
100
50
Standard mode
Wait mode
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.5 Flash memory version power source current standard characteristics (in low-speed mode)
3850 Group (Spec. H) User’s Manual
3-13
APPENDIX
3.2 Standard characteristics
3.2.2 Mask ROM version power source current standard characteristics
Figure 3.2.6, Figure 3.2.7, Figure 3.2.8, Figure 3.2.9 and Figure 3.2.10 show mask ROM version (M38503M2H,
M38503M4H, M38504M6, M38507M8) power source current standard characteristics.
Measuring conditions : 25 °C, f(XIN) = 8 MHz, in high-speed mode
4.0
3.5
3.0
2.5
Standard mode
2.0
1.5
1.0
Wait mode
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.6 Mask ROM version power source current standard characteristics (in high-speed mode,
f(XIN) = 8 MHz)
Measuring conditions : 25 °C, f(XIN) = 4 MHz, in high-speed mode
2.5
2.0
1.5
Standard mode
1.0
Wait mode
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.7 Mask ROM version power source current standard characteristics (in high-speed mode,
f(XIN) = 4 MHz)
3850 Group (Spec. H) User’s Manual
3-14
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(XIN) = 8 MHz, in middle-speed mode
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Standard mode
Wait mode
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.8 Mask ROM version power source current standard characteristics (in middle-speed mode,
f(XIN) = 8 MHz)
Measuring conditions : 25 °C, f(XIN) = 4 MHz, in middle-speed mode
1.0
0.9
0.8
0.7
0.6
Standard mode
0.5
0.4
0.3
Wait mode
0.2
0.1
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.9 Mask ROM version power source current standard characteristics (in middle-speed mode,
f(XIN) = 4 MHz)
3850 Group (Spec. H) User’s Manual
3-15
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(XIN) = 32 kHz, in low-speed mode
35
30
25
20
15
10
5
Standard mode
Wait mode
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.10 Mask ROM version power source current standard characteristics (in low-speed mode)
3850 Group (Spec. H) User’s Manual
3-16
APPENDIX
3.2 Standard characteristics
3.2.3 PROM version power source current standard characteristics
Figure 3.2.11, Figure 3.2.12, Figure 3.2.13, Figure 3.2.14, and Figure 3.2.15 show flash memory version
(M38504E6) power source current standard characteristics.
Measuring conditions : 25 °C, f(XIN) = 8 MHz, in high-speed mode
6.0
5.0
4.0
Standard mode
3.0
2.0
Wait mode
1.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.11 PROM version power source current standard characteristics (in high-speed mode, f(XIN
= 8 MHz)
)
Measuring conditions : 25 °C, f(XIN) = 4 MHz, in high-speed mode
3.5
3
2.5
Standard mode
2
1.5
1
Wait mode
0.5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.12 PROM version power source current standard characteristics (in high-speed mode, f(XIN
= 4 MHz)
)
3850 Group (Spec. H) User’s Manual
3-17
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(XIN) = 8 MHz, in middle-speed mode
2.5
2.0
1.5
1.0
0.5
0.0
Standard mode
Wait mode
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.13 PROM version power source current standard characteristics (in middle-speed mode, f(XIN
= 8 MHz)
)
Measuring conditions : 25 °C, f(XIN) = 4 MHz, in middle-speed mode
1.6
1.4
1.2
1.0
Standard mode
0.8
0.6
0.4
Wait mode
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.14 PROM version power source current standard characteristics (in middle-speed mode, f(XIN
= 4 MHz)
)
3850 Group (Spec. H) User’s Manual
3-18
APPENDIX
3.2 Standard characteristics
Measuring conditions : 25 °C, f(XIN) = 32 kHz, in low-speed mode
70
60
50
40
30
20
10
0
Standard mode
Wait mode
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Power source voltage Vcc [V]
Fig. 3.2.15 PROM version power source current standard characteristics (in low-speed mode)
3850 Group (Spec. H) User’s Manual
3-19
APPENDIX
3.2 Standard characteristics
3.2.4 Flash memory version port standard characteristics
Figure 3.2.16, Figure 3.2.17, Figure 3.2.18 and Figure 3.2.19 show flash memory version (M38507F8) port
standard characteristics.
Port P0
0
IOH-VOH characteristics (P-channel drive) [Ta = 25 °C]
(Same characteristics pins : P0, P1, P2
0
, P2 , P2 –P2 , P3, P4)
1
4
7
–50
–45
–40
–35
–30
Vcc = 5.0 V
IOH
[mA]
–25
–20
–15
–10
Vcc = 4.0 V
Vcc = 2.7 V
–5
0
0
0.5 1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OH [V]
V
Fig. 3.2.16 CMOS output port P-channel side characteristics (Ta = 25 °C)
Port P0
0
I
OL-VOL characteristics (N-channel drive) [Ta = 25 °C]
, P2 , P2 –P2 , P3, P4)
(Same characteristics pins : P0, P2
0
1
4
7
100
90
80
70
60
50
40
30
20
I
OL
[mA]
Vcc = 5 V
Vcc = 4.0 V
Vcc = 2.7 V
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OL [V]
5.5
V
Fig. 3.2.17 CMOS output port N-channel side characteristics (Ta = 25 °C)
3850 Group (Spec. H) User’s Manual
3-20
APPENDIX
3.2 Standard characteristics
Port P2
2
I
OL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P2 , P2
2
3)
100
90
80
70
60
50
40
30
20
I
OL
[mA]
Vcc = 5 V
Vcc = 4.0 V
Vcc = 2.7 V
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OL [V]
5.5
V
Fig. 3.2.18 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C)
Port P17 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P1)
100
90
Vcc = 5 V
80
70
IOL
[mA]
60
50
40
30
20
Vcc = 4.0 V
Vcc = 2.7 V
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL [V]
5.5
Fig. 3.2.19 CMOS large current output port N-channel side characteristics (Ta = 25 °C)
3850 Group (Spec. H) User’s Manual
3-21
APPENDIX
3.2 Standard characteristics
3.2.5 Mask ROM version port standard characteristics
Figure 3.2.20, Figure 3.2.21, Figure 3.2.22 and Figure 3.2.23 show mask ROM version (M38503M2H,
M38503M4H, M38504M6, M38507M8) port standard characteristics.
Port P0
0
I
OH-VOH characteristics (P-channel drive) [Ta = 25 °C]
, P2 , P2 –P2 , P3, P4)
(Same characteristics pins : P0, P1, P2
0
1
4
7
–50
–45
–40
–35
–30
Vcc = 5.0 V
I
OH
[mA]
–25
–20
–15
–10
Vcc = 4.0 V
Vcc = 2.7 V
–5
0
0
0.5 1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OH [V]
V
Fig. 3.2.20 CMOS output port P-channel side characteristics (Ta = 25 °C)
Port P00 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P0, P20, P21, P24–P27, P3, P4)
100
90
80
70
IOL
[mA]
60
50
40
30
20
Vcc = 5.0 V
Vcc = 4.0 V
Vcc = 2.7 V
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL [V]
5.5
Fig. 3.2.21 CMOS output port N-channel side characteristics (Ta = 25 °C)
3850 Group (Spec. H) User’s Manual
3-22
APPENDIX
3.2 Standard characteristics
Port P22 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P22, P23)
100
90
80
70
60
50
40
30
20
IOL
[mA]
Vcc = 5.0 V
Vcc = 4.0 V
Vcc = 2.7 V
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL [V]
5.5
Fig. 3.2.22 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C)
Port P17 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P1)
100
90
Vcc = 5.0 V
80
70
I
OL
60
50
40
30
20
Vcc = 4.0 V
[mA]
Vcc = 2.7 V
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL [V]
5.5
Fig. 3.2.23 CMOS large current output port N-channel side characteristics (Ta = 25 °C)
3850 Group (Spec. H) User’s Manual
3-23
APPENDIX
3.2 Standard characteristics
3.2.6 PROM version port standard characteristics
Figure 3.2.24, Figure 3.2.25, Figure 3.2.26 and Figure 3.2.27 show PROM version (M38504E6) port standard
characteristics.
Port P00 IOH-VOH characteristics (P-channel drive) [Ta = 25 °C]
(Same characteristics pins : P0, P1, P20, P21, P24–P27, P3, P4)
–50
–45
–40
–35
Vcc = 5.0 V
–30
I
OH
[mA]
Vcc = 4.0 V
Vcc = 2.7 V
–25
–20
–15
–10
–5
0
0
0.5 1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OH [V]
V
Fig. 3.2.24 CMOS output port P-channel side characteristics (Ta = 25 °C)
Port P00 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P0, P20, P21, P24–P27, P3, P4)
100
90
80
70
IOL
[mA]
60
50
40
30
20
Vcc = 5.0 V
Vcc = 4.0 V
Vcc = 2.7 V
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL [V]
5.5
Fig. 3.2.25 CMOS output port N-channel side characteristics (Ta = 25 °C)
3850 Group (Spec. H) User’s Manual
3-24
APPENDIX
3.2 Standard characteristics
Port P22 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P22, P23)
100
90
80
70
60
50
40
30
20
Vcc = 5.0 V
Vcc = 4.0 V
IOL
[mA]
Vcc = 2.7 V
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL [V]
5.5
Fig. 3.2.26 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C)
Port P17 IOL-VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins : P1)
100
Vcc = 5.0 V
Vcc = 4.0 V
90
80
70
60
50
40
30
20
IOL
[mA]
Vcc = 2.7 V
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL [V]
5.5
Fig. 3.2.27 CMOS large current output port N-channel side characteristics (Ta = 25 °C)
3850 Group (Spec. H) User’s Manual
3-25
APPENDIX
3.2 Standard characteristics
3.2.7 A-D conversion standard characteristics
(1) Definition of A-D conversion accuracy
The A-D conversion accuracy is defined below.
✽Relative accuracy
✽ Zero transition voltage (V0T
)
This means an analog input voltage when the actual A-D conversion output data changes from “0”
to “1”.
✽ Full-scale transition voltage (VFST
)
This means an analog input voltage when the actual A-D conversion output data changes from
“1023” to “1022”.
✽ Linearity error
This means a deviation from the lone between V0T and VFST of a converted value between V0T and
V
FST
.
✽ Differential non-linearity error
This means a deviation from the input potential difference required to change a converted value
between V0T and VFST by 1 LSB of the 1 LSB at the relative accuracy.
✽Absolute accuracy
This means a deviation from the ideal characteristics between 0 to VREF of actual A-D conversion
characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
b
a
n+1
n
Actual A-D conversion
characteristics
c
Ideal line of A-D
conversion between
V0 to V1022
1
0
Vn
Vn+1
V0
V1
V1022
VREF
Analog voltage
Zero transition voltage (V0T)
b-a
a
[LSB]
Differential non-linearity error =
c
Vn : Analog input voltage when the output data changes
from “n” to “n + 1” (n = 0 to 1022)
a : 1 LSB at relative accuracy
[LSB]
Linearity error =
b : Vn+1 –Vn
a
c : Difference between the aideal Vn and actual Vn
VFST-V0T
1022
[LSB]
1 LSB at relative accuracy =
1 LSB at absolute accuracy =
VREF
1024
[LSB]
Fig. 3.2.28 Definition of A-D conversion accuracy
3850 Group (Spec. H) User’s Manual
3-26
APPENDIX
3.2 Standard characteristics
(2) A-D conversion standard characteristics
Figure 3.2.29, Figure 3.2.30, and Figure 3.2.31 show the A-D conversion standard characteristics of
flash memory version, mask ROM version, and PROM version, respectively.
The thick lines of the graph indicate the absolute precision errors, These are expressed as the
deviation from the ideal value when the output code changes. For example, the change in output
code from 256 to 257 should occur at 1280 mV, but the measured value is 2.5 mV. Accordingly, the
measured point of change is 1280 + 2.5 = 1282.5 mV.
The thin lines of the graph indicate the input voltage width for which the output code is constant. For
example, the measured input voltage width for which the output code is 256 is 5.0 mV, so that the
differential non-linear error is 5.0 – 5.0 = 0 mV (0 LSB).
3850 Group (Spec. H) User’s Manual
3-27
APPENDIX
3.2 Standard characteristics
M38507F8 A-D CONVERTER ERROR & STEP WIDTH MEASUREMENT
VCC = 5.12 [V], VREF = 5.12 [V]
X
IN = 8 [MHz], Ta = 25 [deg.]
Zero transition voltage
Full-scale transition voltage
Differential non-linearity error
Linearity error
Absolute accuracy
15.0
:
:
:
:
:
10.625 [mV]
5122.812 [mV]
1.719 [mV] :
—5.659 [mV] :
8.906 [mV] :
0.344 [LSB]
—1.131 [LSB]
1.781 [LSB]
15.0
10.0
5.0
10.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
0
16
32
48
64
80
96
112
STEP No.
128
144
160
416
672
928
176
432
688
944
192
448
704
960
208 224
464 480
720 736
240 256
15.0
10.0
15.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
256 272
288
544
800
304
560
816
320
576
832
336 352 368
384
400
496 512
STEP No.
15.0
10.0
5.0
15.0
10.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
512 528
592 608 624
640
656
752 768
STEP No.
15.0
10.0
15.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
768 784
848 864 880
896
912
976 992 1008 1024
STEP No.
: ERROR (Absolute accuracy error
: 1LSB WIDTH
)
Fig. 3.2.29 Flash memory version (M38507F8) A-D conversion standard characteristics
3850 Group (Spec. H) User’s Manual
3-28
APPENDIX
3.2 Standard characteristics
M38503M2H, M38503M4H, M38504M6, M38507M8 A-D CONVERTER ERROR & STEP WIDTH MEASUREMENT
V
X
CC = 5.12 [V], VREF = 5.12 [V]
IN = 8 [MHz], Ta = 25 [deg.]
Zero transition voltage
Full-scale transition voltage
Differential non-linearity error
Linearity error
:
:
:
:
:
10.31 [mV]
5118.12 [mV]
—1.41 [mV] :
—4.72 [mV] :
6.25 [mV] :
—0.28 [LSB]
—0.94 [LSB]
1.25 [LSB]
Absolute accuracy
15.0
15.0
10.0
5.0
10.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
0
16
32
48
64
80
96
112
STEP No.
128
144
160
416
672
928
176
432
688
944
192
448
704
960
208 224
464 480
720 736
240 256
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
256 272
288
544
800
304
560
816
320
576
832
336 352 368
384
400
496 512
STEP No.
15.0
10.0
5.0
15.0
10.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
512 528
592 608 624
640
656
752 768
STEP No.
15.0
10.0
15.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
768 784
848 864 880
896
912
976 992 1008 1024
STEP No.
: ERROR (Absolute accuracy error
: 1LSB WIDTH
)
Fig. 3.2.30 Mask ROM version (M38503M2H, M38503M4H, M38504M6, M38507M8) A-D conversion standard
characteristics
3850 Group (Spec. H) User’s Manual
3-29
APPENDIX
3.2 Standard characteristics
M38504E6 A-D CONVERTER ERROR & STEP WIDTH MEASUREMENT
V
X
CC = 5.12 [V], VREF = 5.12 [V]
IN = 8 [MHz], Ta = 25 [deg.]
Zero transition voltage
Full-scale transition voltage
Differential non-linearity error
Linearity error
:
:
:
:
:
—0.62 [mV]
5112.19 [mV]
2.97 [mV] :
—3.41 [mV] :
—7.03 [mV] :
0.59 [LSB]
—0.68 [LSB]
—1.41[LSB]
Absolute accuracy
15.0
15.0
10.0
5.0
10.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
0
16
32
48
64
80
96
112
STEP No.
128
144
160
416
672
928
176
432
688
944
192
448
704
960
208 224
464 480
720 736
240 256
15.0
10.0
15.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
256 272
288
544
800
304
560
816
320
576
832
336 352 368
384
400
496 512
STEP No.
15.0
10.0
5.0
15.0
10.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
512 528
592 608 624
640
656
752 768
STEP No.
15.0
10.0
15.0
10.0
5.0
5.0
0.0
0.0
—5.0
—10.0
—15.0
768 784
848 864 880
896
912
976 992 1008 1024
STEP No.
: ERROR (Absolute accuracy error
: 1LSB WIDTH
)
Fig. 3.2.31 PROM version (M38504E6) A-D conversion standard characteristics
3850 Group (Spec. H) User’s Manual
3-30
APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on input and output ports
(1) Notes in standby state
In standby state✽1, do not make input levels of an I/O port “undefined”, especially for I/O ports of the
N-channel open-drain. When setting the N-channel open-drain port as an output, do not make input
levels of an I/O port “undefined”, too.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
✽ Reason
When setting as an input port with its direction register, the transistor becomes the OFF state,
which causes the ports to be the high-impedance state.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of an I/O port are “undefined”. This may cause power source current.
In I/O ports of N-channel open-drain, when the contents of the port latch are “1”, even if it is set
as an output port with its direction register, it becomes the same phenomenon as the case of an
input port.
✽1 standby state: stop mode by executing STP instruction
wait mode by executing WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction✽2, the value of the
unspecified bit may be changed.
✽ Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
•As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
✽2 Bit managing instructions: SEB and CLB instructions
3850 Group (Spec. H) User’s Manual
3-31
APPENDIX
3.3 Notes on use
3.3.2 Termination of unused pins
(1) Terminate unused pins
✽ Output ports : Open
✽ Input ports :
Connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pins CNVSS, INT or others, select
the VCC pin or the VSS pin according to their operation mode.
✽ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
✽ The AVss pin when not using the A-D converter :
• When not using the A-D converter, handle a power source pin for the A-D converter, AVss pin
as follows:
AVss: Connect to the Vss pin.
(2) Termination remarks
✽ Input ports and I/O ports :
Do not open in the input mode.
✽ Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ✽ and
✽ shown on the above.
✽ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
✽ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and VCC (or VSS).
✽ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
✽ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
3850 Group (Spec. H) User’s Manual
3-32
APPENDIX
3.3 Notes on use
3.3.3 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 3A16
•Timer XY mode register (address 2316
)
)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active edge switch
bit) or the interrupt (source) select bit to “1”.
↓
NOP (one or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 3.3.1 Sequence of changing relevant register
✽ Reason
When setting the followings, the interrupt request bit may be set to “1”.
•When setting external interrupt active edge
Concerned register: Interrupt edge selection register (address 3A16
Timer XY mode register (address 2316
)
)
•When switching interrupt sources of an interrupt vector address where two or more interrupt
sources are allocated.
Concerned register: Interrupt edge selection register (address 3A16
)
3850 Group (Spec. H) User’s Manual
3-33
APPENDIX
3.3 Notes on use
(2) Check of interrupt request bit
✽ When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one
or more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.2 Sequence of check of interrupt request bit
✽ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
3.3.4 Notes on timer
✽ If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
✽ When switching the count source by the timer 12, X and Y count source selection bits, the value
of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count
input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
3.3.5 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O (Serial I/O1)
✽ Stop of transmission operation
Clear the serial I/O1 enable bit and the transmit enable bit to “0” (Serial I/O1 and transmit disabled).
✽ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
✽ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0”
(Serial I/O1 disabled).
3850 Group (Spec. H) User’s Manual
3-34
APPENDIX
3.3 Notes on use
✽ Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive
disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
✽ Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to
“0” (Serial I/O1 disabled) (refer to (1) ✽).
✽ SRDY1 output of reception side (Serial I/O1)
When signals are output from the SRDY1 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY1 output enable bit,
and the transmit enable bit to “1” (transmit enabled).
(2) Notes when selecting clock asynchronous serial I/O (Serial I/O1)
✽ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
✽ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
✽ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
✽ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
✽ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (Serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
3850 Group (Spec. H) User’s Manual
3-35
APPENDIX
3.3 Notes on use
(3) Setting serial I/O1 control register again (Serial I/O1)
Set the serial I/O1 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0”.
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O1 control register
Can be set with the LDM instruction at the same time
↓
Set both the transmit enable bit (TE) and
the receive enable bit (RE), or one of
them to “1”
Fig. 3.3.3 Sequence of setting serial I/O1 control register again
(4) Data transmission control with referring to transmit shift register completion flag (Serial I/O1)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(5) Transmit interrupt request when transmit enable bit is set (Serial I/O1)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
➀ Set the interrupt enable bit to “0” (disabled) with CLB instruction.
➀ Prepare serial I/O for transmission/reception.
➀ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
➀ Set the interrupt enable bit to “1” (enabled).
➀ Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt request bit is set regardless of which of the two timings listed below is selected as the timing
for the transmission interrupt to be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
(6) Transmission control when external clock is selected (Serial I/O1 clock synchronous mode)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the SCLK1 input level. Also, write the transmit data to the transmit buffer
register (serial I/O shift register) at “H” of the SCLK1 input level.
(7) Transmit data writing (Serial I/O2)
In the clock synchronous serial I/O, when selecting an external clock as synchronous clock, write the
transmit data to the serial I/O2 register (serial I/O shift register) at “H” of the transfer clock input level.
3850 Group (Spec. H) User’s Manual
3-36
APPENDIX
3.3 Notes on use
3.3.6 Notes on PWM
The PWM starts after the PWM enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L“ level output is as follows:
n + 1
2 • f(XIN
sec. (Count source selection bit = “0”, where n is the value set in the prescaler)
)
n + 1
sec. (Count source selection bit = “1”, where n is the value set in the prescaler)
f(XIN
)
3.3.7 Notes on A-D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
✽ Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the VSS line
✽ Reason
If the AVSS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(XIN) is 500 kHz or more in middle-/high-speed mode.
• Do not execute the STP instruction.
• When the A-D converter is operated at low-speed mode, f(XIN) do not have the lower limit of
frequency, because of the A-D converter has a built-in self-oscillation circuit.
3.3.8 Notes on watchdog timer
✽Make sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog
timer keeps counting during that term.
✽When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.
3850 Group (Spec. H) User’s Manual
3-37
APPENDIX
3.3 Notes on use
3.3.9 Notes on RESET pin
(1) Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
✽ Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
(2) Reset release after power on
When releasing the reset after power on, such as power-on reset, release reset after XIN passes more
than 20 cycles in the state where the power supply voltage is 2.7 V or more and the XIN oscillation
is stable.
✽ Reason
To release reset, the RESET pin must be held at an “L” level for 20 cycles or more of XIN in the
state where the power source voltage is between 2.7 V and 5.5 V, and XIN oscillation is stable.
3.3.10 Notes on using stop mode
✽Register setting
Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the
stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP
instruction released bit is “0”)
When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate
time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
✽Clock restoration
After restoration from the stop mode to the normal mode by an interrupt request, the contents of
the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both
main clock and sub clock were oscillating before execution of the STP instruction, the oscillation
of both clocks is resumed at restoration.
In the above case, when the main clock side is set as a system clock, the oscillation stabilizing
time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode.
At this time, note that the oscillation on the sub clock side may not be stabilized even after the
lapse of the oscillation stabilizing time of the main clock side.
3.3.11 Notes on wait mode
✽Clock restoration
If the wait mode is released by a reset when XCIN is set as the system clock and XIN oscillation is
stopped during execution of the WIT instruction, XCIN oscillation stops, XIN oscillations starts, and
X
IN is set as the system clock.
In the above case, the RESET pin should be held at “L” until the oscillation is stabilized.
3850 Group (Spec. H) User’s Manual
3-38
APPENDIX
3.3 Notes on use
3.3.12 Notes on CPU rewrite mode of flash memory version
(1) Operation speed
During CPU rewrite mode, set the internal clock frequency 4MHz or less by using the main clock
division ratio selection bits (bits 6, 7 at address 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during CPU
rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of
the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog
timer underflow does not happen, because of watchdog timer is always clearing during program or
erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = “H” when reset is released, boot mode is active. So the
program starts from the address contained in addresses FFFC16 and FFFD16 in boot ROM area.
3.3.13 Notes on restarting oscillation
✽Restarting oscillation
Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has
been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer
1 = “0116”, Prescaler 12 = “FF16”) are automatically reloaded in order for the oscillation to stabilize.
The user can inhibit the automatic setting by writing “1” to bit 0 of MISRG (address 003816).
However, by setting this bit to “1”, the previous values, set just before the STP instruction was
executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate
value to each register, in accordance with the oscillation stabilizing time, before executing the STP
instruction.
✽ Reason
Oscillation will restart when an external interrupt is received. However, internal clock φ is supplied
to the CPU only when Timer 1 starts to underflow. This ensures time for the clock oscillation using
the ceramic resonators to be stabilized.
3850 Group (Spec. H) User’s Manual
3-39
APPENDIX
3.3 Notes on use
3.3.14 Notes on programming
(1) Processor status register
✽ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
✽ Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.4 Initialization of processor status register
✽ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
(S)
↓
(S)+1
Stored PS
NOP
Fig. 3.3.5 Sequence of PLP instruction execution
Fig. 3.3.6 Stack memory contents after PHP
instruction execution
(2) BRK instruction
✽ Interrupt priority level
When the BRK instruction is executed with the following conditions satisfied, the interrupt execution
is started from the address of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
3850 Group (Spec. H) User’s Manual
3-40
APPENDIX
3.3 Notes on use
(3) Decimal calculations
✽ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
✽ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.7 Status flag at decimal calculations
(4) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
(5) Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
(6) Ports
The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
(7) Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the
number of cycles needed to execute an instruction.
The number of cycles required to execute an instruction is shown in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency in high-speed mode.
3850 Group (Spec. H) User’s Manual
3-41
APPENDIX
3.3 Notes on use
3.3.15 EPROM Version/One Time PROM Version/Flash Memory Version
The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has
the multiplexed function to be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10
kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss
pin or Vcc pin via a resistor.
3.3.16 Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass
capacitor between power source pin (VCC pin) and GND pin (VSS pin) and between power source pin (VCC
pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible.
For bypass capacitor which should not be located too far from the pins to be connected, a ceramic
capacitor of 0.01 µF–0.1µF is recommended.
3.3.17 Differences between 3850 group (standard) and 3850 group (spec. H)
(1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard).
•Power source voltage Vcc = 0.3 to 6.5 V
•CNVss input voltage V = –0.3 to Vcc +0.3 V
I
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group
(standard) and 3850 group (spec. H).
(3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after
reset.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
3850 Group (Spec. H) User’s Manual
3-42
APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Package
Select the smallest possible package to make the total wiring length short.
✽ Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.4.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
✽ Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
Reset
circuit
RESET
RESET
V
SS
V
SS
V
SS
V
SS
N.G.
O.K.
Fig. 3.4.2 Wiring for the RESET pin
3850 Group (Spec. H) User’s Manual
3-43
APPENDIX
3.4 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is
connected to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
✽ Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the VSS
level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
X
X
V
IN
X
X
V
IN
OUT
SS
OUT
SS
O.K.
N.G.
Fig. 3.4.3 Wiring for clock I/O pins
(4) Wiring to CNVSS pin
Connect the CNVSS pin to the VSS pin with the shortest possible wiring.
✽ Reason
The processor mode of a microcomputer is influenced by a potential at the CNVSS pin. If a
potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may
become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
CNVSS
CNVSS
V
SS
V
SS
O.K.
N.G.
Fig. 3.4.4 Wiring for CNVSS pin
3850 Group (Spec. H) User’s Manual
3-44
APPENDIX
3.4 Countermeasures against noise
(5) Wiring to VPP pin of One Time PROM version, EPROM version, and Flash memory version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the
VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the
VSS pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
✽ Reason
The VPP pin of the One Time PROM, the EPROM version, and the flash memory version is the
power source input pin for the built-in PROM. When programming in the built-in PROM, the
impedance of the VPP pin is low to allow the electric current for writing flow into the PROM.
Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or
data are read from the built-in PROM, which may cause a program runaway.
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM version, the EPROM version, and the flash
memory version
3.4.2 Connection of bypass capacitor across VSS line and VCC line
Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin.
V
CC
V
CC
V
SS
V
SS
N.G.
O.K.
Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line
3850 Group (Spec. H) User’s Manual
3-45
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the VSS pin at equal length.
✽ Reason
Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from
the VSS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
O.K.
N.G.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.7 Analog signal line and a resistor and a capacitor
3850 Group (Spec. H) User’s Manual
3-46
APPENDIX
3.4 Countermeasures against noise
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
✽ Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
XIN
XOUT
Large
current
VSS
GND
Fig. 3.4.8 Wiring for a large current signal line
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
✽ Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
CNTR
Do not cross
XIN
XOUT
VSS
Fig. 3.4.9 Wiring of RESET pin
3850 Group (Spec. H) User’s Manual
3-47
APPENDIX
3.4 Countermeasures against noise
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides,
separate this VSS pattern from other VSS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
X
X
V
IN
OUT
SS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.10 VSS pattern on the underside of an oscillator
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
Noise
O.K.
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.11 Setup for I/O ports
3850 Group (Spec. H) User’s Manual
3-48
APPENDIX
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
Interrupt processing routine
(SWDT) ← (SWDT)—1
Interrupt processing
Main routine
(SWDT)← N
CLI
Main processing
>0
(SWDT)
≤0?
RTI
≠N
≤0
(SWDT)
=N?
Return
N
Interrupt processing
routine errors
Main routine
errors
Fig. 3.4.12 Watchdog timer by software
3850 Group (Spec. H) User’s Manual
3-49
APPENDIX
3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4)
(Pi: addresses 0016, 0216, 0416, 0616, 0816
)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
7
Port Pi
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
✽In output mode
Write •••••••• Port latch
Read •••••••• Port latch
✽In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Note: When reading bit 5, 6 or 7 of ports 3 and 4, the contents are undefined.
Fig. 3.5.1 Structure of Port Pi
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 0, 1, 2, 3, 4)
(PiD: addresses 0116, 0316, 0516, 0716, 0916
)
b
0
Name
Port Pi direction
register
Functions
At reset R W
0
0 : Port Pi
0
input mode
output mode
1 : Port Pi
0
0 : Port Pi
1 : Port Pi
1
1
input mode
output mode
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
0 : Port Pi
1 : Port Pi
3
3
input mode
output mode
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
input mode
output mode
0 : Port Pi
1 : Port Pi
7
7
input mode
output mode
Fig. 3.5.2 Structure of Port Pi direction register
3850 Group (Spec. H) User’s Manual
3-50
APPENDIX
3.5 List of registers
Serial I/O2 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 1 (SIO2CON1: address 1516
)
b
0
Name
Internal
synchronous clock
selection bits
Functions
At reset R W
0
b2b1b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
0
0
0
0
0
0
1
2
3
4
5
6
Serial I/O2 port
selection bit
0: I/O port (P01, P02)
1: SOUT2, SCLK2 signal output
SRDY2 output
enable bit
Transfer direction
selection bit
0: I/O port (P03)
1: SRDY2 signal output
0: LSB first
1: MSB first
0: External clock
1: Internal clock
Serial I/O2
synchronous
clock selection bit
P0
1
/SOUT2
,
0: CMOS output
1: N-channel open-drain
output
0
7
P02
/SCLK2
P-channel output
disable bit
Fig. 3.5.3 Structure of Serial I/O2 control register 1
Serial I/O2 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register 2
(SIO2CON2: address 1616
)
b
0
Name
Optional transfer
bits
Functions
At reset R W
1
b2b1b0
0 0 0: 1 bit
0 0 1: 2 bit
0 1 0: 3 bit
0 1 1: 4 bit
1 0 0: 5 bit
1 0 1: 6 bit
1 1 0: 7 bit
1 1 1: 8 bit
1
2
1
1
0
3
4
5
✽
✽
✽
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
0
Serial I/O2
I/O comparison
signal control bit
0: P4 I/O
1: SCMP2 output
3
0
6
S
OUT2 pin control
0: Output active
1: Output high-impedance
0
7
bit (P0
1)
Fig. 3.5.4 Structure of Serial I/O2 control register 2
3850 Group (Spec. H) User’s Manual
3-51
APPENDIX
3.5 List of registers
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register
(SIO2: address 1716
)
b
Name
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
1
2
3
4
5
6
7
This register becomes shift register.
At transmit: Set transmit data to this register.
At receive: Received data is stored to this
register.
Fig. 3.5.5 Structure of Serial I/O2 register
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB: address 1816
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
The transmission data is written to or the
receive data is read out from this buffer register.
• At write: A data is written to the transmit buffer
register.
• At read: The contents of the receive buffer
register are read out.
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 3.5.6 Structure of Transmit/Receive buffer register
3850 Group (Spec. H) User’s Manual
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APPENDIX
3.5 List of registers
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status register (SIOSTS: address 1916
)
b
0
Name
Transmit buffer
empty flag (TBE)
Functions
0: Buffer full
1: Buffer empty
At reset R W
✽
✽
✽
0
0
0
0: Buffer empty
1: Buffer full
Receive buffer full
flag (RBF)
1
2 Transmit shift
register shift
completion flag
(TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag
3
0: No error
1: Overrun error
0
0
0
0
1
✽
✽
✽
✽
✽
(OE)
4
Parity error flag
(PE)
0: No error
1: Parity error
Framing error flag
(FE)
0: No error
1: Framing error
5
6
7
Summing error flag
(SE)
0: (OE) U (PE) U (FE) = 0
1: (OE) U (PE) U (FE) = 1
Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “1”.
Fig. 3.5.7 Structure of Seial I/O1 status register
3850 Group (Spec. H) User’s Manual
3-53
APPENDIX
3.5 List of registers
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register
(SIOCON: address 1A16)
b
Name
Functions
At reset R W
0
0 BRG count source
selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Serial I/O1
1
0
When clock synchronous
serial I/O is selected,
0: BRG output divided by 4
1: External clock input
When UART is selected,
0: BRG output divided by 16
1: External clock input
divided by16
synchronous clock
selection bit (SCS)
0
0
0: I/O port (P27)
1: SRDY1 output pin
SRDY1 output
enable bit (SRDY)
2
3
0: Transmit buffer empty
1: Transmit shift operation
completion
Transmit interrupt
source selection
bit (TIC)
0: Transmit disabled
1: Transmit enabled
Transmit enable bit
(TE)
0
0
0
4
5
6
Receive enable bit 0: Receive disabled
(RE)
1: Receive enabled
0: UART
Serial I/O1 mode
1: Clock synchronous
serial I/O
selection bit (SIOM)
0: Serial I/O1 disabled
(P24 to P27: normal I/O pins)
1: Serial I/O1 enabled
(P24 to P27: Serial I/O pins)
Serial I/O1 enable
bit (SIOE)
0
7
Fig. 3.5.8 Structure of Seial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register
(UARTCON: address 1B16)
b
0
Name
Functions
At reset R W
0
Character length
0: 8 bits
selection bit (CHAS)
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
1
2
3
0
0
Parity enable bit
(PARE)
0: Even parity
1: Odd parity
0: 1 stop bit
Parity selection bit
(PARS)
Stop bit length
0
0
selection bit (STPS) 1: 2 stop bits
4 P25/TxD P-channel
output disable bit
(POFF)
In output mode
0: CMOS output
1: N-channel open-drain
output
1
5
6
7
✕
✕
✕
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “1”.
1
1
Fig. 3.5.9 Structure of UART control register
3850 Group (Spec. H) User’s Manual
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APPENDIX
3.5 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator(BRG : address 1C16
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Set a count value of baud rate generator.
Fig. 3.5.10 Structure of Baud rate generator
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register (PWMCON: address 1D16
)
b
0
Name
PWM function
enable bit
Functions
At reset R W
0
0 : PWM disabled
1 : PWM enabled
Count source
selection bit
0
1
0 : f(XIN)
1 : f(XIN)/2
✽
2
3
4
5
6
7
0
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
0
0
0
✽
✽
✽
✽
✽
0
Fig. 3.5.11 Structure of PWM control register
PWM prescaler
b7 b6 b5 b4 b3 b2 b1 b0
PWM prescaler
(PREPWM: address 1E16
)
b
0
1
2
3
4
5
6
7
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
•Set the PWM period.
•The value set in this register is written to both
PWM prescaler pre-latch and PWM prescaler
latch at the same time.
• When data is written to this register during
PWM output, the pulse corresponding to
changed value is output at the next period.
• When this register is read out, the count value
of the PWM prescaler latch is read out.
Fig. 3.5.12 Structure of PWM prescaler
3850 Group (Spec. H) User’s Manual
3-55
APPENDIX
3.5 List of registers
PWM register
b7 b6 b5 b4 b3 b2 b1 b0
PWM register
(PWM: address 1F16
)
b
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
1
2
3
4
5
6
7
• Set the PWM “H” level output interval.
• The value set in this register is written to both
PWM register pre-latch and PWM register
latch at the same time.
• When data is written to this register during
PWM output, the pulse corresponding to
changed value is output at the next period.
• When this register is read out, the contents of
the PWM register latch is read out.
Fig. 3.5.13 Structure of PWM register
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)
(addresses 2016, 2416, 2616
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
• Set a count value of each prescaler.
• The value set in this register is written to both
each prescaler and the corresponding
prescaler latch at the same time.
• When this register is read out, the count value
of the corresponding prescaler is read out.
Fig. 3.5.14 Structure of Prescaler 12, Prescaler X, Prescaler Y
3850 Group (Spec. H) User’s Manual
3-56
APPENDIX
3.5 List of registers
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1
(T1: address 2116
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
0
0
0
0
0
0
0
• Set timer 1 count value.
• The value set in this register is written to both
the timer 1 and the timer 1 latch at the same
time.
• When the timer 1 is read out, the count value
of the timer 1 is read out.
Fig. 3.5.15 Structure of Timer 1
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2216
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
• Set timer 2 count value.
• The value set in this register is written to both
timer 2 and the timer 2 latch at the same time.
• When timer 2 is read out, the count value of
the timer 2 is read out.
Fig. 3.5.16 Structure of Timer 2
3850 Group (Spec. H) User’s Manual
3-57
APPENDIX
3.5 List of registers
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register
(TM: address 2316
)
b
0
Name
Functions
At reset R W
0
b1 b0
Timer X operating
mode bits
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width
0
1
2
measurement mode
Refer to Table 3.5.1
0 active edge
0
0
0
CNTR
switch bit
0: Count start
1: Count stop
3 Timer X count stop
bit
4
b5 b4
Timer Y operating
mode bits
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width
0
5
measurement mode
Refer to Table 3.5.1
CNTR1 active edge
switch bit
0
0
6
7
0: Count start
1: Count stop
Timer Y count stop
bit
Fig. 3.5.17 Structure of Timer XY mode register
Table 3.5.1 CNTR0/CNTR1 active edge switch bit function
Timer X /Timer Y
operation modes
Timer mode
Set
value
Timer function
CNTR0 / CNTR1 interrupt request
occurrence source
“0”
“1”
“0”
No influence to timer count
No influence to timer count
CNTR0/CNTR1 input signal falling edge
CNTR0/CNTR1 input signal rising edge
Pulse output
mode
Pulse output start: Beginning Output signal falling edge count
at “H” level
“1”
Pulse output start: Beginning Output signal rising edge count
at “L” level
Event counter
mode
“0”
“1”
“0”
“1”
Rising edge count
Input signal falling edge count
Input signal rising edge count
Input signal falling edge count
Input signal rising edge count
Falling edge count
Pulse width
“H” level width measurement
“L” level width measurement
measurement mode
3850 Group (Spec. H) User’s Manual
3-58
APPENDIX
3.5 List of registers
Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer X, Timer Y
(TX, TY: addresses 2516, 2716
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
• Set each timer count value.
• The value set in this register is written to both
each timer and the corresponding timer latch
at the same time.
• When each timer is read out, the count value
of the corresponding timer is read out.
Fig. 3.5.18 Structure of Timer X, Timer Y
Timer count source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Timer count source selection register
(TCSS: address 2816
)
b
Name
Timer X count
source selection bit
Functions
At reset R W
0
0: f(XIN)/16 (f(XCIN)/16 at
low-speed mode)
1: f(XIN)/2 (f(XCIN)/2 at low-
speed mode)
0
0: f(XIN)/16 (f(XCIN)/16 at
low-speed mode)
Timer Y count
source selection bit
0
0
1
2
1: f(XIN)/2 (f(XCIN)/2 at low-
speed mode)
Timer 12 count
source selection bit
0: f(XIN)/16 (f(XCIN)/16 at
low-speed mode)
1: f(XCIN
)
3
4
5
6
0
0
0
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read out,
the contents are “0”.
0
0
7
Fig. 3.5.19 Structure of Timer count source selection register
3850 Group (Spec. H) User’s Manual
3-59
APPENDIX
3.5 List of registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register
(ADCON: address 3416
)
b
0
Name
Analog input pin
selection bits
Functions
At reset R W
0
b2 b1 b0
0 0 0: P3
0 0 1: P3
0 1 0: P3
0 1 1: P3
1 0 0: P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
1
2
3
0
0
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
1
4
0: Conversion in progress
1: Conversion completed
AD conversion
completion bit
0
0
0
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bist are read
out, the contents are “0”.
Fig. 3.5.20 Structure of A-D control register
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3516)
b
Functions
At reset R W
Undefined
0
1
2
3
4
5
6
7
This is A-D conversion result stored bits. This is
read exclusive register.
Undefined
Undefined
8-bit read
b7
b0
Undefined
b9b8b7b6b5b4b3b2
10-bit read
Undefined
Undefined
b7
b0
Undefined
b7b6b5b4b3b2b1b0
Undefined
Fig. 3.5.21 Structure of A-D conversion low-order register
3850 Group (Spec. H) User’s Manual
3-60
APPENDIX
3.5 List of registers
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3616
)
b
Functions
At reset R W
Undefined
This is A-D conversion result stored bits. This is
read exclusive register.
0
10-bit read
b7
b0
1
Undefined
b9b8
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read out,
the contents are “0”.
0
0
0
0
0
0
2
3
4
5
6
7
Fig. 3.5.22 Structure of A-D conversion high-order register
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG
(MISRG: address 3816)
b
Name
Functions
At reset R W
0 Oscillatin stabilizing 0: Automatically set (Note 1)
0
time set after STP
1: Autimatically set disabled
instruction released bit
0: Not set automatically
1: Automatic switching
enabled (Note 2)
Middle-speed mode
automatic switch set
bit
0
0
0
1
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
2 Middle-speed mode
automatic switch
wait time set bit
Middle-speed mode 0: Invalid
3
automatic switch
start bit
1: Automatic switch start
(Note 2)
(Depending on
program)
4
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
0
0
0
✕
✕
✕
✕
Notes 1: “0116” is set to Timer 1, “FF16” is set to Prescaler 12.
2: When automatic switch to middle-speed mode from low-speed mode occurs,
the values of CPU mode register (3B16) change.
Fig. 3.5.23 Structure of MISRG
3850 Group (Spec. H) User’s Manual
3-61
APPENDIX
3.5 List of registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register
(WDTCON: address 3916)
b
0
1
2
3
4
5
6
Name
Watchdog timer H
(for read-out of high-order 6 bit)
Functions
At reset R W
1
1
1
1
1
1
0
✕
✕
✕
✕
✕
✕
STP instruction
disable bit
0: STP instruction enabled
1: STP instruction disabled
7
0
Watchdog timer H 0: Watchdog timer L
count source selection
bit
underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 3.5.24 Structure of Watchdog timer control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE: address 3A16
)
b
0
Name
Functions
0: Falling edge active
1: Rising edge active
At reset R W
0
INT
0
active edge
selection bit
INT active edge
selection bit
2 INT
active edge
selection bit
0: Falling edge active
1: Rising edge active
0
0
1
1
0: Falling edge active
1: Rising edge active
2
0: Falling edge active
1: Rising edge active
3
0
INT active edge
selection bit
3
SeriaI/O2/INT
interrupt source bit
3
4
0: INT
1: Serial I/O2 interrupt
selected
3
interrupt selected
0
0
0
0
5 Nothing is arranged for these bits. These are
6
write disabled bits. When these bits are read out,
the contents are “0”.
7
Fig. 3.5.25 Structure of Interrupt edge selection register
3850 Group (Spec. H) User’s Manual
3-62
APPENDIX
3.5 List of registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register
(CPUM: address 3B16
)
b
0
Name
Functions
At reset R W
0
b1 b0
Processor mode
bits
00 : Single-chip mode
01 :
1
10 :
11 :
Not available
0
0
0 : 0 page
1 : 1 page
2 Stack page
selection bit
1
0
Fix this bit to “1”.
3
Port Xc switch bit
0: I/O port function
(stop oscillating)
1: XCIN-XCOUT oscillation
function
4
Main clock (XIN
-
0: Oscillating
1: Stopped
b7 b6
0
1
5
6
XOUT) stop bit
Main clock division
ratio selection bits
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
0
7
(low-speed mode)
1 1: not available
Fig. 3.5.26 Structure of CPU mode register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16
)
b
0
Name
Functions
At reset R W
✕
✕
✕
✕
✕
✕
✕
✕
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
0
0
0
0
0
INT
0
interrupt
request bit
When writing to this bit, set “0” to this bit.
1
INT
1
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
2
3
0 : No interrupt request issued
1 : Interrupt request issued
INT interrupt
request bit
INT /Serial I/O2
interrupt request bit
2
3
0 : No interrupt request issued
1 : Interrupt request issued
4
5
6
When writing to this bit, set “0” to this bit.
0 : No interrupt request issued
1 : Interrupt request issued
Timer X interrupt
request bit
Timer Y interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
7
✕: “0” can be set by software, but “1” cannot be set.
Fig. 3.5.27 Structure of Interrupt request register 1
3850 Group (Spec. H) User’s Manual
3-63
APPENDIX
3.5 List of registers
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16
)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
Timer 1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
1 Timer 2 interrupt
request bit
Serial I/O1 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
2
3
4
5
6
Serial I/O1 transmit 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
CNTR
request bit
CNTR interrupt
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
1
0 : No interrupt request issued
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Fig. 3.5.28 Structure of Interrupt request register 2
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
0
0
(ICON1 : address 3E16
)
b
0
Name
Functions
At reset R W
0
INT
0
interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
1 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
2 INT
enable bit
INT interrupt
enable bit
INT /Serial I/O2
1
interrupt
2
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
3
4
3
interrupt enable bit
Fix this bit to “0”.
5
6
7
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 3.5.29 Structure of Interrupt control register 1
3850 Group (Spec. H) User’s Manual
3-64
APPENDIX
3.5 List of registers
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2
(ICON2 : address 3F16)
0
b
0
Name
Timer 1 interrupt
enable bit
Functions
At reset R W
0
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt
enable bit
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 receive
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O1 transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
CNTR
0
interrupt
enable bit
CNTR interrupt
1
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
A-D converter
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fix this bit to “0”.
Fig. 3.5.30 Structure of Interrupt control register 2
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register
(FMCR : address 0FFE16)
b
Name
Functions
At reset R W
1
0 : Busy (being written or
erased)
0 RY/BY status flag
1 : Ready
0
1
CPU rewrite mode 0 : Normal mode (Software
select bit (Note 1)
commands invalid)
1 : CPU rewrite mode
(Software commands
acceptable)
2
CPU rewrite mode
entry flag
0: Normal mode
1: CPU rewrite mode
0
Flash memory reset
bit (Note 2)
User area/Boot
area selection bit
3
4
0: Normal operation
1: Reset
0: User ROM area
1: Boot ROM area
0
0
5 Nothing is arranged for these bits. When write, Undefined
set “0”. When these bits are read out, the
contents are undefined.
Undefined
Undefined
6
7
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then
a “1” to it in succession.
2: Effective only when the CPU rewrite mode select bit = “1”. Set this
bit to “0” subsequently after setting it to “1” (reset).
Fig. 3.5.31 Structure of Flash memory control register
3850 Group (Spec. H) User’s Manual
3-65
APPENDIX
3.6 Package outline
3.6 Package outline
MMP
42P4B
Plastic 42pin 600mil SDIP
EIAJ Package Code
SDIP42-P-600-1.78
JEDEC Code
–
Weight(g)
4.1
Lead Material
Alloy 42/Cu Alloy
42
22
1
21
Dimension in Millimeters
Symbol
A
Min
–
0.51
–
Nom
–
–
Max
5.5
–
D
A
A
1
2
3.8
–
b
0.35
0.9
0.63
0.22
36.5
12.85
–
–
3.0
0°
0.45
1.0
0.55
1.3
1.03
0.34
36.9
13.15
–
–
–
15°
b1
b2
0.73
0.27
36.7
13.0
1.778
15.24
–
c
D
E
e
e
b1
b
b2
e1
L
SEATING PLANE
–
42P2R-A/E
Plastic 42pin 450mil SSOP
EIAJ Package Code
SSOP42-P-450-0.80
JEDEC Code
Weight(g)
0.63
Lead Material
Alloy 42
e
b2
–
42
22
Recommended Mount Pad
Dimension in Millimeters
F
Symbol
Min
–
0.05
–
0.25
0.13
17.3
8.2
–
11.63
0.3
–
–
–
–
0°
–
–
1.27
Nom
–
–
Max
2.4
–
A
A
A
b
c
D
E
e
H
L
1
21
1
2
A
2.0
0.3
0.15
17.5
8.4
0.8
11.93
0.5
1.765
0.75
–
–
D
G
0.4
0.2
17.7
8.6
–
12.23
0.7
–
A2
A1
e
b
E
y
L1
z
Z
y
–
1
0.9
0.15
10°
–
–
–
–
–
c
z
b2
0.5
11.43
–
Z
1
Detail G
Detail F
e1
I
2
3850 Group (Spec. H) User’s Manual
3-66
APPENDIX
3.6 Package outline
42S1B-A
Metal seal 42pin 600mil DIP
EIAJ Package Code
JEDEC Code
Weight(g)
–
WDIP42-C-600-1.78
D
42
22
1
21
Dimension in Millimeters
Symbol
A
Min
–
1.0
–
0.38
0.7
0.17
–
–
–
–
3.05
–
Nom
–
–
Max
5.0
–
3.44
0.54
0.9
0.33
41.1
15.8
–
A
A
1
2
–
b
0.46
0.8
0.25
–
b1
c
D
E
e
e
Z
b
b1
–
1.778
15.24
–
e1
–
–
SEATING PLANE
L
Z
–
3.05
3850 Group (Spec. H) User’s Manual
3-67
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
OP
69
A
n
BIT,A, R
ZP
n
BIT,ZP, R
ZP, X
ZP, Y
OP
ABS
ABS, X
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
#
n
# OP
2
#
OP
n
# OP
65
#
2
OP
n
#
OP
75
n
4
#
2
n
#
OP
6D
n
4
#
3
OP
7D
n
5
#
OP
79
n
5
#
3
OP
#
n
#
OP
61
n
6
#
OP
71
n
6
#
OP
#
OP
#
N
N
V
V
ADC
(Note 1)
(Note 5)
When T = 0
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A re-
main unchanged, but the contents of status
flags are changed.
2
3
3
2
2
•
←
A
A + M + C
When T = 1
←
M(X)
M(X) + M + C
M(X) represents the contents of memory
where is indicated by X.
AND
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the con-
tents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1 the contents of A re-
main unchanged, but status flags are
changed.
29
2
2
25
3
2
35
4
2
2D
4
3
3D
5
3
39
5
3
21
6
2
31
6
2
N
•
•
•
•
•
Z
•
V
←
A
A
M
When T = 1
V
←
M(X)
M(X)
M
M(X) represents the contents of memory
where is indicated by X.
7
0
ASL
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A
2
1
06
5
2
16
6
2
0E
6
3
1E
7
3
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
C
•
←
←
0
C
BBC
(Note 4)
Ai or Mi = 0?
Ai or Mi = 1?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative ad-
dress. If the bit is 1, next instruction is
executed.
13
+
4
2
17
+
5
5
3
3
20i
20i
BBS
(Note 4)
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative ad-
dress. If the bit is 0, next instruction is
executed.
03
+
4
2
07
+
•
•
•
•
•
•
•
•
20i
20i
C = 0?
C = 1?
BCC
(Note 4)
This instruction takes a branch to the ap-
pointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
2
2
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90
B0
F0
BCS
(Note 4)
This instruction takes a branch to the ap-
pointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
Z = 1?
BEQ
(Note 4)
This instruction takes a branch to the ap-
pointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
•
V
A
M
BIT
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
24
3
2
M7 M6
Z
2C
4
3
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
N = 1?
Z = 0?
30
2
2
2
2
BMI
(Note 4)
This instruction takes a branch to the ap-
pointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D0
BNE
(Note 4)
This instruction takes a branch to the ap-
pointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
3850 Group (Spec. H) User’s Manual
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3-69
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n
ZP, X
ZP, Y
OP
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
#
n
# OP
#
n
# OP
#
#
OP
n
#
n
#
OP
#
OP
n
#
OP
#
n
#
#
#
OP
10
#
2
OP
#
N
•
V
•
T
•
B
•
D
•
I
Z
•
C
•
BPL
(Note 4)
N = 0?
This instruction takes a branch to the ap-
pointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
2
•
←
80
BRA
BRK
PC
PC ± offset
This instruction branches to the appointed ad-
dress. The branch address is specified by a
relative address.
4
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
←
B
1
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
1
1
00
7
1
←
←
(PC)
M(S)
(PC) + 2
PCH
←
S
S – 1
←
M(S)
PCL
←
S
S – 1
←
PS
S – 1
M(S)
←
S
←
I
1
←
←
PCL
PCH
ADL
ADH
50
70
2
2
2
2
BVC
(Note 4)
V = 0?
V = 1?
Ai or Mi
This instruction takes a branch to the ap-
pointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
BVS
(Note 4)
This instruction takes a branch to the ap-
pointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
1B
+
2
1
1F
+
5
2
←
CLB
CLC
CLD
CLI
0
This instruction clears the designated bit i of A
or M.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
20i
20i
18
D8
58
12
B8
2
2
2
2
2
1
1
1
1
1
←
←
C
D
0
0
This instruction clears C.
This instruction clears D.
This instruction clears I.
This instruction clears T.
This instruction clears V.
•
•
•
0
•
•
•
←
I
0
•
•
•
0
•
•
•
←
←
CLT
CLV
T
V
0
0
•
•
0
•
•
•
•
•
0
•
•
•
•
•
C9
2
2
C5
3
2
D5
4
2
CD
4
3
DD
5
3
D9
5
3
C1
6
2
D1
6
2
CMP
(Note 3)
When T = 0
A – M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the con-
tents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
N
•
•
•
Z
C
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
__
M
44
E4
5
3
2
2
←
COM
CPX
M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
E0
C0
2
2
2
EC
CC
CE
4
4
6
3
3
3
X – M
Y – M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
C
2
C4
C6
3
5
2
2
CPY
DEC
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
C
•
1A
2
1
←
←
D6
6
2
DE
7
3
A
M
A – 1 or
M – 1
This instruction subtracts 1 from the contents
of A or M.
3850 Group (Spec. H) User’s Manual
3850 Group (Spec. H) User’s Manual
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3-71
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
OP n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP
ZP, X
ZP, Y
OP n
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
CA
#
1
# OP
#
n
# OP
#
n
#
OP
n
#
#
OP
#
OP
n
#
OP
#
OP
n
#
#
#
OP
#
OP
#
N
N
V
•
T
•
B
•
D
•
I
Z
Z
C
•
←
←
←
2
•
DEX
DEY
DIV
X
Y
A
X – 1
This instruction subtracts one from the current
contents of X.
88
1
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
2
Y – 1
This instruction subtracts one from the current
contents of Y.
(M(zz + X + 1),
M(zz + X )) / A
Divides the 16-bit data in M(zz+(X)) (low-order
byte) and M(zz+(X)+1) (high-order byte) by the
contents of A. The quotient is stored in A and
the one's complement of the remainder is
pushed onto the stack.
E2 16
2
2
←
M(S)
one's comple-
ment of Remainder
←
S
S – 1
2
2
45
3
2
4
55
4D
4
3
5D
5
3
59
5
3
41
6
2
51
6
2
49
N
•
•
•
•
•
Z
•
EOR
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bit-
wise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
–
←
A
A V M
When T = 1
–
←
M(X)
M(X) V M
M(X) represents the contents of memory
where is indicated by X.
E6
5
2
6
EE
4C
6
3
3
FE
7
3
F6
2
←
←
3A
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
•
2
1
INC
INX
A
M
A + 1 or
M + 1
This instruction adds one to the contents of A
or M.
E8
C8
1
1
←
2
2
X
X + 1
Y + 1
This instruction adds one to the contents of X.
This instruction adds one to the contents of Y.
←
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
INY
Y
3
6C
5
3
B2
4
2
JMP
If addressing mode is ABS
PCL
PCH
This instruction jumps to the address desig-
nated by the following three addressing
modes:
←
←
ADL
ADH
If addressing mode is IND
Absolute
←
←
PCL
PC
M (ADH, ADL)
M (AD , AD + 1)
Indirect Absolute
Zero Page Indirect Absolute
H
H
L
If addressing mode is ZP, IND
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
←
20
6
3
02
7
2
22
5
2
•
•
•
•
•
•
•
•
JSR
M(S)
PCH
S – 1
This instruction stores the contents of the PC
in the stack, then jumps to the address desig-
nated by the following addressing modes:
Absolute
←
S
←
PCL
S – 1
M(S)
←
S
After executing the above,
Special Page
if addressing mode is ABS,
Zero Page Indirect Absolute
←
←
PCL
PCH
ADL
ADH
if addressing mode is SP,
←
←
PCL
PCH
ADL
FF
If addressing mode is ZP, IND,
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
A9
2
2
A5
3C
3
4
2
3
B5
4
2
AD
4
3
BD
5
3
B9
5
3
A1
6
2
B1
6
2
N
•
•
•
•
•
•
•
•
•
•
Z
•
•
LDA
(Note 2)
When T = 0
When T = 0, this instruction transfers the con-
tents of M to A.
←
A
M
When T = 1
When T = 1, this instruction transfers the con-
tents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
←
M(X)
M
←
•
•
LDM
M
nn
This instruction loads the immediate value in
M.
←
←
A2
A0
2
2
2
2
A6
A4
3
3
2
2
B6
4
2
AE
AC
4
4
3
3
BE
5
3
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
•
LDX
LDY
X
Y
M
M
This instruction loads the contents of M in X.
This instruction loads the contents of M in Y.
B4
4
2
BC
5
3
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3850 Group (Spec. H) User’s Manual
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3-73
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
LSR
Function
Details
IMP
n
IMM
OP n
A
n
2
BIT, A
OP
ZP
n
BIT, ZP
OP
ZP, X
ZP, Y
OP
ABS
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
#
# OP
4A
#
1
n
# OP
46
#
2
n
#
OP
56
n
6
#
2
n
#
OP
4E
n
6
#
3
OP
5E
n
7
#
OP
#
n
#
#
#
OP
#
OP
#
N
0
V
•
T
•
B
•
D
•
I
Z
Z
C
C
5
3
•
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
7
0
→
C
→
0
←
MUL
M(S) • A A M(zz + X) Multiplies Accumulator with the memory speci-
62 15
2
•
•
•
•
•
•
•
•
←
S
S – 1
fied by the Zero Page X address mode and
stores the high-order byte of the result on the
Stack and the low-order byte in A.
←
PC + 1
EA
2
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
NOP
PC
This instruction adds one to the PC but does
no otheroperation.
09
2
2
3
2
01
6
2
11
6
2
N
Z
ORA
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the con-
tents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
05
15
4
2
0D
4
3
1D
5
3
5
3
19
←
A
A V M
When T = 1
←
M(X)
M(X) V M
M(X) represents the contents of memory
where is indicated by X.
←
PHA
PHP
PLA
PLP
ROL
S
S – 1
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
48
08
68
28
3
3
4
4
1
1
1
1
←
M(S)
←
PS
This instruction pushes the contents of PS to
the memory location designated by S and dec-
rements the contents of S by one.
S
S – 1
←
←
S
A
S + 1
M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
N
Z
←
S
S + 1
M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
(Value saved in stack)
←
PS
2A
6A
2
2
1
1
26
66
82
5
5
8
2
2
2
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
•
C
C
•
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
7
0
←
36
76
6
6
2
2
2E
6E
6
6
3
3
3E
7E
7
7
3
3
←
←
C
ROR
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
7
0
→
→
C
RRF
RTI
This instruction rotates 4 bits of the M content
to the right.
7
→
0
→
←
S
S + 1
M(S)
S + 1
←
M(S)
S + 1
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PCL. S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
(Value saved in stack)
40
60
6
6
1
1
←
PS
←
PCL
←
PCH
S
S
←
M(S)
←
PCL
RTS
S
S + 1
This instruction increments S by one and
stores the contents of the memory location
•
•
•
•
•
•
•
•
←
M(S)
←
S
S + 1
designated by S in PCL. S is again
←
←
PCH
(PC)
M(S)
(PC) + 1
incremented by one and the contents of the
memory location is stored in PCH. PC is
incremented by 1.
3850 Group (Spec. H) User’s Manual
3850 Group (Spec. H) User’s Manual
3-74
3-75
APPENDIX
APPENDIX
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n
ZP, X
ZP, Y
OP n
ABS
ABS, X
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
#
OP
E9
n
2
# OP
2
#
n
# OP
E5
#
2
#
OP
n
4
#
2
#
OP
ED
n
4
#
3
OP
FD
n
5
#
OP
F9
n
5
#
3
OP
#
n
#
OP
E1
n
6
#
OP
F1
n
6
#
OP
#
OP
#
N
N
V
V
T
•
B
•
D
•
I
Z
Z
C
C
3
F5
3
2
2
SBC
(Note 1)
(Note 5)
When T = 0
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the con-
tents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
•
_
←
A
A – M – C
When T = 1
_
←
M(X)
M(X) – M – C
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
←
SEB
SEC
SED
SEI
Ai or Mi
1
This instruction sets the designated bit i of A
or M.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
0B
+
2
1
0F
+
5
2
20i
20i
←
←
C
D
1
1
This instruction sets C.
This instruction set D.
This instruction set I.
This instruction set T.
38
F8
78
32
2
2
2
2
1
1
1
1
•
1
•
•
←
I
1
•
1
•
•
←
←
SET
STA
STP
T
M
1
1
•
•
•
A
This instruction stores the contents of A in M.
The contents of A does not change.
85
4
2
95
5
2
8D
5
3
9D
6
3
99
6
3
81
7
2
91
7
2
•
•
•
This instruction resets the oscillation control F/ 42
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
2
1
•
•
•
•
←
←
←
←
5
2
STX
STY
TAX
TAY
TST
TSX
TXA
TXS
TYA
WIT
M
M
X
X
Y
This instruction stores the contents of X in M.
The contents of X does not change.
86
84
4
4
2
2
96
8E
8C
5
5
3
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
This instruction stores the contents of Y in M.
The contents of Y does not change.
94
5
2
•
A
This instruction stores the contents of A in X. AA
The contents of A does not change.
2
2
1
1
N
N
N
N
N
•
Z
Z
Z
Z
Z
•
Y
A
This instruction stores the contents of A in Y. A8
The contents of A does not change.
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
64
3
2
←
←
←
←
X
A
S
A
S
X
X
Y
This instruction transfers the contents of S in BA
X.
2
2
2
2
2
1
1
1
1
1
This instruction stores the contents of X in A.
This instruction stores the contents of X in S.
This instruction stores the contents of Y in A.
8A
9A
98
N
•
Z
•
The WIT instruction stops the internal clock C2
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All regis-
ters or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : N, V, and Z flags are invalid in decimal operation mode.
3850 Group (Spec. H) User’s Manual
3850 Group (Spec. H) User’s Manual
3-76
3-77
APPENDIX
3.7 Machine instructions
Symbol
Contents
Implied addressing mode
Symbol
Contents
IMP
+
Addition
IMM
A
Immediate addressing mode
–
✽
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
/
V
V
–
V
–
←
X
Y
ABS, X
ABS, Y
IND
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
S
Stack pointer
Program counter
PC
PS
PCH
PCL
ADH
ADL
FF
nn
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any ad-
dressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
zz
M
Z
Zero flag
I
D
B
T
V
N
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
M(X)
M(S)
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-or-
der bits.
M(ADH, ADL)
Negative flag
M(00, ADL)
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Ai
Mi
OP
n
Number of cycles
#
Number of bytes
3850 Group (Spec. H) User’s Manual
3-78
APPENDIX
3.8 List of instruction code
3.8 List of instruction code
D3 – D0
0000
0001
0010
0011
0100
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
C
1101
D
1110
1111
F
Hexadecimal
notation
0
1
2
3
4
E
D7 – D4
ORA
JSR
BBS
ORA
ZP
ASL
ZP
BBS
0, ZP
ORA
IMM
ASL
A
SEB
0, A
ORA
ABS
ASL
ABS
SEB
0, ZP
BRK
—
PHP
CLC
PLP
SEC
PHA
CLI
—
0000
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IND, X ZP, IND 0, A
ORA
IND, Y
BBC
0, A
ORA
ASL
BBC
ORA
ABS, Y
DEC
A
CLB
0, A
ORA
ASL
CLB
BPL
JSR
CLT
—
—
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ZP, X ZP, X 0, ZP
ABS, X ABS, X 0, ZP
AND
ABS IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
AND
ABS
ROL
ABS
SEB
1, ZP
AND
BMI
BBC
1, A
AND
ROL
BBC
AND
ABS, Y
INC
A
CLB
1, A
LDM
AND
ROL
CLB
SET
STP
—
IND, Y
ZP, X ZP, X 1, ZP
ZP ABS, X ABS, X 1, ZP
EOR
RTI
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
EOR
ABS
LSR
ABS
SEB
2, ZP
IND, X
EOR
BVC
BBC
2, A
EOR
LSR
BBC
EOR
ABS, Y
CLB
2, A
EOR
LSR
CLB
—
—
—
—
IND, Y
ZP, X ZP, X 2, ZP
ABS, X ABS, X 2, ZP
ADC
RTS
MUL
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
ADC
ABS
ROR
ABS
SEB
3, ZP
PLA
SEI
IND, X ZP, X
ADC
—
BBC
3, A
ADC
ROR
BBC
ADC
ABS, Y
CLB
3, A
ADC
ROR
CLB
BVS
BRA
—
—
TXA
TXS
TAX
TSX
DEX
—
—
IND, Y
ZP, X ZP, X 3, ZP
ABS, X ABS, X 3, ZP
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
DEY
TYA
TAY
CLV
INY
—
STA
IND, Y
BBC
4, A
STY
STA
STX
BBC
STA
ABS, Y
CLB
4, A
STA
ABS, X
CLB
4, ZP
BCC
LDY
—
—
—
ZP, X ZP, X ZP, Y 4, ZP
LDA
LDX
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
LDA
IMM
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
IMM IND, X IMM
LDA
JMP
BBC
LDY
LDA
LDX
BBC
LDA
ABS, Y
CLB
LDY
LDA
LDX
CLB
BCS
IND, Y ZP, IND 5, A
ZP, X ZP, X ZP, Y 5, ZP
5, A ABS, X ABS, X ABS, Y 5, ZP
CPY
CMP
IMM IND, X
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
CMP
IMM
SEB
6, A
CPY
ABS
CMP
ABS
DEC
ABS
SEB
6, ZP
WIT
CMP
BNE
BBC
6, A
CMP
DEC
BBC
CMP
ABS, Y
CLB
6, A
CMP
DEC
CLB
—
—
CLD
INX
—
IND, Y
ZP, X ZP, X 6, ZP
ABS, X ABS, X 6, ZP
CPX
SBC
DIV
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
SBC
IMM
SEB
7, A
CPX
ABS
SBC
ABS
INC
ABS
SEB
7, ZP
NOP
—
IMM IND, X ZP, X
SBC
IND, Y
BBC
7, A
SBC
INC
BBC
SBC
ABS, Y
CLB
7, A
SBC
INC
CLB
BEQ
—
—
SED
—
ZP, X ZP, X 7, ZP
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
3850 Group (Spec. H) User’s Manual
3-79
APPENDIX
3.9 SFR memory map
3.9 SFR memory map
Port P0 (P0)
000016
Prescaler 12 (PRE12)
Timer 1 (T1)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Port P0 direction register (P0D)
Port P1 (P1)
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Timer Y (TY)
Port P3 direction register (P3D)
Port P4 (P4)
Timer count source selection register (TCSS)
Port P4 direction register (P4D)
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
A-D control register (ADCON)
Reserved ✽
A-D conversion low-order register (ADL)
A-D conversion high-order register (ADH)
Serial I/O2 control register 1 (SIO2CON1)
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
Reserved ✽
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Baud rate generator (BRG)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Flash memory control register (FMCR)
0FFE16
✽ Reserved : Do not write any data to this addresses, because these areas are reserved.
3850 Group (Spec. H) User’s Manual
3-80
APPENDIX
3.10 Pin configurations
3.10 Pin configurations
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3
P3
P3
P3
P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
V
CC
V
REF
AVSS
/PWM
/SCMP2
/INT
/INT
/CNTR
/SRDY1
/SCLK1
3
4
P4
4
/INT
/INT
P4
P4
P4
/CNTR
P2
P2
P2
3
5
P4
3
2
6
2
1
0
1
P0
P0
P0
P0
0/SIN2
1
7
1
2
3
/SOUT2
/SCLK2
/SRDY2
0
8
P2
7
0
9
6
10
11
12
13
14
15
16
17
18
19
20
21
P0
P0
P0
P0
4
5
/TxD
/RxD
P2
P2
5
6
7
4
3
2
P1
P1
P1
P1
P1
P1
P1
P1
0
1
2
3
4
5
6
7
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
0
1
2
3
4
5
6
7
)
)
)
)
)
)
)
)
CNVSS
/XCIN
/XCOUT
V
PP
P2
P2
1
0
RESET
X
IN
OUT
SS
X
V
: Flash memory version
3850 Group (Spec. H) User’s Manual
3-81
APPENDIX
3.10 Pin configurations
M38517RSS PIN CONFIGURATION (TOP VIEW)
V
CC
1
2
3
4
5
6
7
42
41
40
39
38
37
36
P3
P3
P3
P3
P3
P0
P0
0
1
2
3
4
0
1
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
V
REF
AVSS
P4
P4
4
/INT
3
/PWM
28
27
26
25
24
23
22
1
2
3
/INT
2
/SCMP2
P4
P4
2
/INT
/INT
1
0
1
/SIN2
3
4
1
/SOUT2
P4
/CNTR
P2
P2
P2
0
/CNTR
8
9
35
34
P0
2
/SCLK2
/SRDY2
5
6
P2
7
0/SRDY1
P0
3
6
/SCLK1
10
11
12
13
14
15
16
17
18
19
20
21
33
32
31
30
29
28
27
26
25
24
23
22
P0
P0
P0
P0
P1
P1
P1
4
5
6
7
0
1
2
5
/T
/R
P2
P2
X
D
7
4
X
D
21
20
19
18
17
16
15
8
3
2
9
/(LED
/(LED
/(LED
0
1
2
)
)
)
10
11
12
CNVSS
P2 /XCIN
P2 /XCOUT
1
0
P1
P1
P1
P1
P1
3
4
5
6
7
/(LED
/(LED
/(LED
/(LED
/(LED
3
4
5
6
7
)
)
)
)
)
RESET
13
14
X
IN
OUT
SS
X
V
Outline : 42S1M
3850 Group (Spec. H) User’s Manual
3-82
RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER
USER’S MANUAL
3850 Group (Spec. H) Rev.1.03
Editioned by
Committee of editing of RENESAS Semiconductor User’s Manual
This book, or parts thereof, may not be reproduced in any form without permission
of Renesas Technology Corporation.
Copyright © 2003. Renesas Technology Corporation, All rights reserved.
3850 Group (Spec. H)
User’s Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
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