M38510E9-SP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38510E9-SP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总91页 (文件大小：1146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3851 Group (Built-in 24 KB or more ROM)
REJ03B0066-0101Z
Rev.1.01
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Oct 15, 2003
DESCRIPTION
Clock generating circuit ................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage
The 3851 group (built-in 24 KB or more ROM) is the 8-bit micro-
computer based on the 740 family core technology.
The 3851 group (built-in 24 KB or more ROM) is designed for the
household products and office automation equipment and includes
In high-speed mode ................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
2
serial I/O functions, 8-bit timer, I C-BUS interface, and A-D con-
In middle-speed mode ............................................. 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
verter.
In low-speed mode................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
FEATURES
Basic machine-language instructions ..................................... 71
Minimum instruction execution time ................................. 0.5 µs
(at 8 MHz oscillation frequency)
Power dissipation
In high-speed mode .........................................................34 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode
Memory size
ROM ................................................................ 24K to 32K bytes
RAM....................................................................640 to 1K bytes
Programmable input/output ports ........................................... 34
Interrupts ................................................ 17 sources, 16 vectors
Timers............................................................................ 8-bit X 4
Serial I/O1 .................... 8-bit X 1(UART or Clock-synchronized)
Serial I/O2 ................................... 8-bit X 1(Clock-synchronized)
Except M38517F8FP/SP ................................................. 60 µW
M38517F8FP/SP............................................................ 450 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
Operating temperature range ..................................–20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products,
2
Multi-master I C-BUS interface .................................. 1 channel
Consumer electronics, etc.
PWM .............................................................................. 8-bit X 1
A-D converter ...............................................10-bit X 5 channels
Watchdog timer ........................................................... 16-bit X 1
PIN CONFIGURATION (TOP VIEW)
1
42
41
40
39
38
37
36
P3
P3
P3
P3
P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
V
CC
2
3
4
5
6
7
V
REF
AVSS
P4
4
/INT
3
/PWM
/SCMP2
/INT
/INT
/CNTR
/SRDY1
/SCLK1
/TxD
P4
3
/INT
2
P4
P4
2
1
0
1
P0
P0
P0
P0
P0
P0
P0
P0
P1
P1
P1
P1
P1
P1
P1
P1
0/SIN2
1
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
/SOUT2
/SCLK2
/SRDY2
P4
0
8
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P2
7
/CNTR
0
9
P2
/SCL
6
10
11
12
13
14
15
16
17
18
19
20
21
P2
P2
5
2
4
/SDA
P2 /SCL
P2
2
/RxD
3
1
1
2
/SDA
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
0
1
2
3
4
5
6
7
)
)
)
)
)
)
)
)
CNVSS
P2 /XCIN
P2 /XCOUT
1
0
RESET
X
IN
OUT
SS
X
V
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
Fig. 1 M38517M8-XXXFP/SP pin configuration
Rev.1.01 Oct 15, 2003 page 1 of 89
3851 Group (Built-in 24 KB or more ROM)
FUNCTIONAL BLOCK
Fig.2 Functional block diagram
Rev.1.01 Oct 15, 2003 page 2 of 89
3851 Group (Built-in 24 KB or more ROM)
Table 1 Pin description
Functions
Pin
Name
Function except a port function
Power source
CNVSS input
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
VCC, VSS
CNVSS
Reference
voltage input
VREF
AVSS
•Reference voltage input pin for A-D converter.
Analog power
source input
•Analog power source input pin for A-D converter.
•Connect to Vss.
Reset input
Clock input
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
I/O port P0
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
• Serial I/O2 function pin
P00/SIN2
•I/O direction register allows each pin to be individually
programmed as either input or output.
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
•CMOS compatible input level.
•CMOS 3-state output structure.
•P10 to P17 (8 bits) are enabled to output large current
for LED drive.
I/O port P1
I/O port P2
P10–P17
P20/XCOUT
P21/XCIN
•8-bit CMOS I/O port.
• Sub-clock generating circuit I/O
pins (connect a resonator)
•I/O direction register allows each pin to be individually
programmed as either input or output.
2
P22/SDA1
• I C-BUS interface function pins
•CMOS compatible input level.
P23/SCL1
•P22 to P25 can be switched between CMOS compatible
input level or SMBUS input level in the I C-BUS inter-
face function.
2
P24/SDA2/RxD
P25/SCL2/TxD
P26/SCLK1
• I C-BUS interface function pin/
2
Serial I/O1 function pins
• Serial I/O1 function pin
•P20, P21, P24 to P27: CMOS3-state output structure.
• Serial I/O1 function pin/Timer X
function pin
2
P27/CNTR0/
SRDY1
•P24, P25: N-channel open-drain structure in the I C-
BUS interface function.
•P22, P23: N-channel open-drain structure.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
I/O port P3
I/O port P4
• A-D converter input pin
P30/AN0–
P34/AN4
•CMOS 3-state output structure.
P40/CNTR1
P41/INT0
• Timer Y function pin
• Interrupt input pins
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
P42/INT1
•CMOS 3-state output structure.
P43/INT2/SCMP2
• Interrupt input pin
• SCMP2 output pin
• Interrupt input pin
• PWM output pin
P44/INT3/PWM
Rev.1.01 Oct 15, 2003 page 3 of 89
3851 Group (Built-in 24 KB or more ROM)
PART NUMBERING
M3851 4
M
6
–
XXX SP
Product name
Package type
SP : 42P4B
FP : 42P2R-A/E
SS : 42S1B-A
ROM number
Omitted in One Time PROM version shipped in blank,
EPROM version, and flash memory version.
– : standard
Omitted in One Time PROM version shipped in blank, EPROM
version, and flash memory version.
ROM/PROM/Flash memory size
: 4096 bytes
: 8192 bytes
9 : 36864 bytes
A : 40960 bytes
1
2
3
4
5
6
7
8
: 12288 bytes B : 45056 bytes
: 16384 bytes C : 49152 bytes
: 20480 bytes D : 53248 bytes
: 24576 bytes E : 57344 bytes
: 28672 bytes F : 61440 bytes
: 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they
cannot be used as a user’s ROM area.
However, they can be programmed or erased in the flash memory version,
so that the users can use them.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
F : Flash memory version
RAM size
5: 768 bytes
6: 896 bytes
7: 1024 bytes
8: 1536 bytes
9: 2048 bytes
0
1
2
3
4
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
Fig. 3 Part numbering
Rev.1.01 Oct 15, 2003 page 4 of 89
3851 Group (Built-in 24 KB or more ROM)
GROUP EXPANSION
Packages
Renesas plans to expand the 3851 group (built-in 24 KB or more
42P4B ......................................... 42-pin shrink plastic-molded DIP
42P2R-A/E ......................................... 42-pin plastic-molded SSOP
42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version)
ROM) as follows.
Memory Type
Support for mask ROM, One Time PROM, and flash memory ver-
sions.
Memory Size
Flash memory size ......................................................... 32 K bytes
Mask ROM size ................................................. 24 K to 32 K bytes
One Time PROM size..................................................... 24 K bytes
RAM size ...............................................................640 to 1 K bytes
Memory Expansion Plan
ROM size (bytes)
ROM
exteranal
Mass production
M38517M8/F8
32K
28K
24K
20K
16K
12K
8K
Mass production
M38514M6/E6
384
512
640
768
896
1024
1152
1280
1408
1536
2048
RAM size (bytes)
Products under development or planning: the development schedule and specification may be revised without notice.
The development of planning products may be stopped.
Fig. 4 Memory expansion plan
Rev.1.01 Oct 15, 2003 page 5 of 89
3851 Group (Built-in 24 KB or more ROM)
Currently planning products are listed below.
Table 2 Support products
ROM size (bytes)
Product name
RAM size (bytes)
Package
Remarks
ROM size for User in (
M38514M6-XXXSP
)
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
M38514E6-XXXSP
42P4B
42S1B-A
42P2R-A/E
M38514E6SP
24576
640
M38514E6SS
(24446)
Mask ROM version
M38514M6-XXXFP
M38514E6-XXXFP
M38514E6FP
One Time PROM version
One Time PROM version (blank)
Table 3 3851 group (built-in 16 KB ROM) and 3851 group (built-in 24 KB or
more ROM) corresponding products
3851 group (built-in 16 KB ROM)
M38513M4-XXXFP/SP
M38513E4-XXXFP/SP
M38513E4FP/SP
3851 group (built-in 24 KB or more ROM)
M38514M6-XXXFP/SP
M38514E6-XXXFP/SP
M38514E6FP/SP
M38513E4SS
M38514E6SS
M38517M8-XXXFP/SP
M38517F8FP/SP
Table 4 Differences between 3851 group (built-in 16 KB ROM) and 3851 group (built-in 24 KB or more ROM)
3851 group (built-in 16 KB ROM)
1: Serial I/O
3851 group (built-in 24 KB or more ROM)
2: Serial I/O1 (UART or Clock-synchronized)
Serial I/O2 (Clock-synchronized)
Serviceable in low-speed mode
8: P10–P17
Serial I/O
(UART or Clock-synchronized)
Unserviceable in low-speed mode
5: P13–P17
A-D converter
Large current port
Notes on differences between 3851 group
(built-in 16 KB ROM), 3851 group (built-in 24
KB or more ROM)
(1) The absolute maximum ratings of 3851 group (built-in 24 KB or
more ROM) is smaller than that of 3851 group (built-in 16 KB
ROM).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage
VI = –0.3 to Vcc +0.3 V (M38514M6, M38517M8)
VI = –0.3 to 6.5 V (M38517F8)
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may
be some differences between 3851 group (built-in 16 KB
ROM) and 3851 group (built-in 24 KB or more ROM).
(3) Do not write any data to the reserved area and the reserved
bit. (Do not change the contents after reset.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
Rev.1.01 Oct 15, 2003 page 6 of 89
3851 Group (Built-in 24 KB or more ROM)
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3851 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b0
b0
b0
b0
b7
X
Index register X
Index register Y
b7
Y
b7
S
Stack pointer
b15
b7
PCH
PC
L
Program counter
b7
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
Rev.1.01 Oct 15, 2003 page 7 of 89
3851 Group (Built-in 24 KB or more ROM)
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PC
(S) (S) – 1
M (S) (PC
H
)
Push return address
on stack
M (S) (PC
(S) (S) – 1
M (S) (PC
H)
L
)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
Push contents of processor
status register on stack
L
)
(S) (S)– 1
Subroutine
Interrupt
Service Routine
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PC
(S) (S) + 1
(PC M (S)
L)
M (S)
(PS)
(S) (S) + 1
(PC M (S)
(S) (S) + 1
(PC M (S)
M (S)
H)
L)
POP return
address
from stack
H)
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 5 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
Rev.1.01 Oct 15, 2003 page 8 of 89
3851 Group (Built-in 24 KB or more ROM)
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 6 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
_
N flag
_
_
_
_
_
_
Set instruction
SEC
CLC
SEI
CLI
SED
CLD
SET
CLT
Clear instruction
CLV
Rev.1.01 Oct 15, 2003 page 9 of 89
3851 Group (Built-in 24 KB or more ROM)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
1
(
CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 : Not available
1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0
0
1
1
0 : φ = f(XIN)/2 (high-speed mode)
1 : φ = f(XIN)/8 (middle-speed mode)
0 : φ = f(XCIN)/2 (low-speed mode)
1 : Not available
Fig. 7 Structure of CPU mode register
Rev.1.01 Oct 15, 2003 page 10 of 89
3851 Group (Built-in 24 KB or more ROM)
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains
control registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special
RAM is used for data storage and for stack area of subroutine
page addressing mode.
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
Address
XXXX16
RAM size
(bytes)
000016
SFR area
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
010016
RAM
XXXX16
Not used
0FF016
SFR area (Note)
0FFF16
Not used
YYYY16
ROM area
Reserved ROM area
(128 bytes)
Address
YYYY16
Address
ZZZZ16
ROM size
(bytes)
ZZZZ16
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Note: Flash memory version only
Fig. 8 Memory map diagram
Rev.1.01 Oct 15, 2003 page 11 of 89
3851 Group (Built-in 24 KB or more ROM)
Port P0 (P0)
000016
Prescaler 12 (PRE12)
Timer 1 (T1)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
Port P0 direction register (P0D)
Port P1 (P1)
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Timer Y (TY)
Port P3 direction register (P3D)
Port P4 (P4)
Timer count source selection register (TCSS)
Port P4 direction register (P4D)
002B16 I2C data shift register (S0)
I2C address register (S0D)
002C16
002D16 I2C status register (S1)
002E16 I2C control register (S1D)
002F16 I2C clock control register (S2)
003016 I2C start/stop condition control register (S2D)
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Reserved ✽
Reserved ✽
001316 Reserved ✽
001416 Reserved ✽
A-D control register (ADCON)
A-D conversion low-order register (ADL)
A-D conversion high-order register (ADH)
Serial I/O2 control register 1 (SIO2CON1)
001516
001616
001716
001816
001916
001A16
001B16
001C16
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
Reserved ✽
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
001D16 PWM control register (PWMCON)
001E16
001F16 PWM register (PWM)
PWM prescaler (PREPWM)
0FFD16
0FFE16
0FFF16
Reserved
Flash memory control register 1 (FMCR)
Reserved
✽ Reserved : Do not write any data to this addresses, because these areas are reserved.
Fig. 9 Memory map of special function register (SFR)
Rev.1.01 Oct 15, 2003 page 12 of 89
3851 Group (Built-in 24 KB or more ROM)
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 7 I/O port function
Input/Output
Related SFRs
Name
I/O Structure
Non-Port Function
Pin
P00/SIN2
Ref.No.
(1)
(2)
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
Serial I/O2 function I/O
Serial I/O2 control register
Port P0
(3)
CMOS compatible
input level
CMOS 3-state output
(4)
(5)
Port P1
P10–P17
P20/XCOUT
P21/XCIN
(6)
(7)
Sub-clock generating
circuit
CPU mode register
P22/SDA1
P23/SCL1
CMOS compatible
input level
CMOS/SMBUS input
level (when selecting I C-
BUS interface function)
2
(8)
(9)
2
I C-BUS interface
I C control register
2
function I/O
N-channel open-drain
output
CMOS compatible
input level
P24/SDA2/RxD
P25/SCL2/TxD
Port P2
Input/output,
individual
bits
CMOS/SMBUS input
level (when selecting I C-
BUS interface function)
2
2
I C-BUS interface
(10)
(11)
2
I C control register
function I/O
Serial I/O1 control register
CMOS 3-state output
Serial I/O1 function I/O
N-channel open-drain
output (when selecting I2C-
BUS interface function)
Serial I/O1 function I/O
Serial I/O1 function I/O
Timer X function I/O
A-D conversion input
Timer Y function I/O
Serial I/O1 control register
Serial I/O1 control register
Timer XY mode register
A-D control register
P26/SCLK1
(12)
(13)
P27/CNTR0/SRDY1
P30/AN0–P34/AN4
P40/CNTR1
(14)
(15)
Port P3
Port P4
CMOS compatible
input level
Timer XY mode register
P41/INT0
Interrupt edge selection
register
CMOS 3-state
output
External interrupt input
(16)
(17)
P42/INT1
External interrupt input
SCMP2 output
P43/INT2/SCMP2
Interrupt edge selection register
Serial I/O2 control register
P44/INT3/PWM
External interrupt input
PWM output
Interrupt edge selection register
PWM control register
(18)
Note: When reading bit 5, 6, or 7 of ports P3 and P4, the contents are undefined.
Rev.1.01 Oct 15, 2003 page 13 of 89
3851 Group (Built-in 24 KB or more ROM)
(2) Port P0
1
(1) Port P0
0
P01/SOUT2 P-channel output disable bit
Direction
register
Serial I/O2 Transmit completion signal
Serial I/O2 port selection bit
Direction
register
Port latch
Data bus
Data bus
Port latch
Serial I/O2 input
Serial I/O2 output
(3) Port P0
2
(4) Port P0
3
P0
2/SCLK2 P-channel output disable bit
Serial I/O2 synchronous
clock selection bit
S
RDY2 output enable bit
Direction
register
Serial I/O2 port selection bit
Direction
register
Port latch
Data bus
Data bus
Port latch
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2 external clock input
(6) Port P2
0
(5) Ports P04-P07,P1
Port XC switch bit
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
Oscillator
Port P2
1
Port XC switch bit
(7) Port P2
1
(8) Port P2
2
I2C-BUS interface enable bit
SDA/SCL pin selection bit
Port X
C
switch bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Sub-clock generating circuit input
SDA output
SDA input
Fig. 10 Port block diagram (1)
Rev.1.01 Oct 15, 2003 page 14 of 89
3851 Group (Built-in 24 KB or more ROM)
(9) Port P2
3
(10) Port P24
2
2
I C-BUS interface enable bit
SDA/SCL pin selection bit
I C-BUS interface enable bit
SDA/SCL pin selection bit
Serial I/O1 enable bit
Receive enable bit
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
SDA input
SDA output
SCL output
Serial I/O1 input
SCL input
(11) Port P2
5
(12) Port P26
P-channel output disable bit
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
Serial I/O1 enable bit
Transmit enable bit
I C-BUS interface enable bit
SDA/SCL pin selection bit
2
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
Direction
register
register
Port latch
Data bus
Data bus
Port latch
SCL input
Serial I/O1 output
SCL output
Serial I/O1 clock output
Serial I/O1 external clock input
(13) Port P2
7
(14) Ports P30-P34
Pulse output mode
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
register
SRDY1 output enable bit
Direction
register
Port latch
Data bus
Data bus
Port latch
A-D converter input
Analog input pin selection bit
Pulse output mode
Serial I/O1 ready output
Timer output
CNTR
0
interrupt
input
(15) Port P4
0
(16) Ports P41,P42
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Pulse output mode
Timer output
Interrupt input
CNTR
1
interrupt
input
Fig. 11 Port block diagram (2)
Rev.1.01 Oct 15, 2003 page 15 of 89
3851 Group (Built-in 24 KB or more ROM)
(17) Port P4
3
(18) Port P44
PWM output enable bit
Serial I/O2 I/O
comparison signal control bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
PWM output
Serial I/O2 I/O
comparison signal output
Interrupt input
Interrupt input
Fig. 12 Port block diagram (3)
Rev.1.01 Oct 15, 2003 page 16 of 89
3851 Group (Built-in 24 KB or more ROM)
INTERRUPTS
Interrupts occur by 17 : seven external, nine internal, and one soft-
Notes
When setting the followings, the interrupt request bit may be set to
ware.
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 003A16)
Timer XY mode register (address 002316)
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address 003A16)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
(1) Set the corresponding interrupt enable bit to “0” (disabled).
(2) Set the interrupt edge select bit or the interrupt source select
bit.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
(3) Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
When several interrupts occur at the same time, the interrupts are
received according to priority.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Rev.1.01 Oct 15, 2003 page 17 of 89
3851 Group (Built-in 24 KB or more ROM)
Table 8 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Remarks
Non-maskable
Interrupt Source
Reset (Note 2)
INT0
Priority
High
Low
1
2
FFFD16
FFFC16
At reset
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
FFFB16
FFF916
FFFA16
FFF816
At detection of either rising or
falling edge of SCL or SDA input
External interrupt
(active edge selectable)
3
SCL, SDA
INT1
At detection of either rising or External interrupt
falling edge of INT1 input
FFF616
FFF416
4
5
FFF716
FFF516
(active edge selectable)
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT2 input
INT2
INT3
At detection of either rising or External interrupt
falling edge of INT3 input
(active edge selectable)
6
FFF316
FFF216
At completion of serial I/O2 data Switch by Serial I/O2/INT3
reception/transmission
Serial I/O2
interrupt source bit
2
FFF116
FFEF16
FFED16
FFF016
FFEE16
FFEC16
FFEA16
FFE816
7
8
9
I C
At completion of data transfer
At timer X underflow
Timer X
Timer Y
Timer 1
Timer 2
At timer Y underflow
At timer 1 underflow
10
11
FFEB16
FFE916
STP release timer underflow
Valid when serial I/O is selected
Valid when serial I/O is selected
At timer 2 underflow
At completion of serial I/O1 data
reception
Serial I/O1
reception
12
13
FFE716
FFE516
FFE616
FFE416
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
Serial I/O1
transmission
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR0 input
CNTR0
CNTR1
14
15
FFE216
FFE016
FFE316
FFE116
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
A-D converter
16
17
FFDF16
FFDD16
FFDE16
FFDC16
At completion of A-D conversion
At BRK instruction execution
BRK instruction
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.1.01 Oct 15, 2003 page 18 of 89
3851 Group (Built-in 24 KB or more ROM)
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
0
active edge selection bit
1
2
3
active edge selection bit
active edge selection bit
active edge selection bit
0 : Falling edge active
1 : Rising edge active
Serial I/O2 / INT3 interrupt source bit
0 : INT interrupt selected
3
1 : Serial I/O2 interrupt selected
Not used (returns “0” when read)
b7
b0
b7
b0
Interrupt request register 2
Interrupt request register 1
(IREQ2 : address 003D16
)
(IREQ1 : address 003C16
)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O1 reception interrupt request bit
Serial I/O1 transmit interrupt request bit
INT
0 interrupt request bit
SCL/SDA interrupt request bit
INT
INT
INT
1
2
3
interrupt request bit
interrupt request bit
/ Serial I/O2 interrupt request bit
CNTR
CNTR
0
interrupt request bit
interrupt request bit
1
I2C interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 2
Interrupt control register 1
(ICON2 : address 003F16
)
(ICON1 : address 003E16
)
INT interrupt enable bit
0
Timer 1 interrupt enable bit
SCL/SDA interrupt enable bit
Timer 2 interrupt enable bit
INT
INT
INT
1
2
3
interrupt enable bit
interrupt enable bit
/ Serial I/O2 interrupt enable bit
Serial I/O1 reception interrupt enable bit
Serial I/O1 transmit interrupt enable bit
CNTR
CNTR
0
interrupt enable bit
interrupt enable bit
I2C interrupt enable bit
1
Timer X interrupt enable bit
Timer Y interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
Rev.1.01 Oct 15, 2003 page 19 of 89
3851 Group (Built-in 24 KB or more ROM)
TIMERS
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
The 3851 group (built-in 24 KB or more ROM) has four timers:
timer X, timer Y, timer 1, and timer 2.
modes by setting the timer XY mode register.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an un-
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
(1) Timer Mode
The timer counts the count source selected by Timer count source
selection bit.
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach “0016”, the
signal output from the CNTR0 (or CNTR1) pin is inverted. If the
CNTR0 (or CNTR1) active edge selection bit is “0”, output begins
at “ H”.
b0
b7
Timer XY mode register
(TM : address 002316
)
Timer X operating mode bits
b1b0
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P27 ( or port P40) direction register to out-
put mode.
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
(3) Event Counter Mode
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bits
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts the selected signals by the count source selection bit while
the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) ac-
tive edge selection bit is “1”, the timer counts it while the CNTR0
(or CNTR1) pin is at “L”.
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.
Fig. 15 Structure of timer XY mode register
Note
b0
b7
Timer count source selection register
(TCSS : address 002816
When switching the count source by the timer 12, X and Y count
source bits, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
)
Timer X count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Therefore, select the timer count source before set the value to
the prescaler and the timer.
Timer 12 count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XCIN
)
When timer X/timer Y underflow while executing the instruction
which sets “1” to the timer X/timer Y count stop bits, the timer X/
timer Y interrupt request bits are set to “1”. Timer X/Timer Y in-
terrupts are received if these interrupts are enabled at this time.
The timing which interrupt is accepted has a case after the in-
struction which sets “1” to the count stop bit, and a case after
the next instruction according to the timing of the timer under-
flow. When this interrupt is unnecessary, set “0” (disabled) to the
interrupt enable bit and then set “1” to the count stop bit.
Not used (returns “0” when read)
Fig. 16 Structure of timer count source selection register
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The out-
put of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.
Rev.1.01 Oct 15, 2003 page 20 of 89
3851 Group (Built-in 24 KB or more ROM)
Data bus
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
Prescaler X latch (8)
Timer X latch (8)
Timer X (8)
f(XIN)/2
Pulse width
measurement
mode
(f(XCIN)/2 at low-speed mode)
Timer mode
Pulse output mode
Timer X count source selection bit
To timer X interrupt
request bit
Prescaler X (8)
Timer X count stop bit
CNTR0 active edge
Event
counter
mode
selection bit
P27/CNTR0/SRDY1
“0”
To CNTR
0 interrupt
request bit
“1”
CNTR0 active
“1”
“0”
edge selection
bit
Q
Q
T
Toggle flip-flop
R
Timer X latch write pulse
Pulse output mode
Port P2
latch
7
Port P2
direction register
7
Pulse output mode
Data bus
f(XIN)/16
Prescaler Y latch (8)
Timer Y latch (8)
Timer Y (8)
(f(XCIN)/16 at low-speed mode)
f(XIN)/2
Pulse width
measure-
(f(XCIN)/2 at low-speed mode)
Timer mode
ment mode Pulse output mode
Timer Y count source selection bit
To timer Y interrupt
request bit
Prescaler Y (8)
CNTR1 active edge
selection bit
Event
counter
mode
Timer Y count stop bit
P40/CNTR1
“0”
To CNTR
1 interrupt
request bit
“1”
CNTR1 active
“1”
“0”
edge selection
bit
Q
Q
T
Toggle flip-flop
R
Port P4
latch
0
Timer Y latch write pulse
Pulse output mode
Port P4
0
direction register
Pulse output mode
Data bus
Prescaler 12 latch (8)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
To timer 2 interrupt
request bit
f(XCIN
)
Timer 12 count source selection bit
To timer 1 interrupt
request bit
Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2
Rev.1.01 Oct 15, 2003 page 21 of 89
3851 Group (Built-in 24 KB or more ROM)
SERIAL I/O
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O1 mode selection bit of the serial I/O1 control register (bit
6 of address 001A16) to “1”.
SERIAL I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Data bus
Serial I/O1 control register
Address 001A16
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive shift register
Receive interrupt request (RI)
P24/RXD
Shift clock
Clock control circuit
P26/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
X
IN
Baud rate generator
Address 001C16
1/4
Clock control circuit
Falling-edge detector
P27/CNTR0/SRDY1
F/F
Shift clock
Transmit shift register
Transmit buffer register
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P25/TXD
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 18 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
D
0
0
D
1
1
D
2
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
D
D
D
D
D
D
D
D
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has
ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 19 Operation of clock synchronous serial I/O1 function
Rev.1.01 Oct 15, 2003 page 22 of 89
3851 Group (Built-in 24 KB or more ROM)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 001816
Serial I/O1 control register Address 001A16
OE
Character length selection bit
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
P24
/R
XD
ST detector
7 bits
8 bits
Receive shift register
1/16
UART control register
PE FE
SP detector
Address 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P26/SCLK1
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
XIN
Baud rate generator
Address 001C16
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P25/TXD
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O1 status register
Data bus
Fig. 20 Block diagram of UART serial I/O1
Rev.1.01 Oct 15, 2003 page 23 of 89
3851 Group (Built-in 24 KB or more ROM)
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=0
TBE=1
TSC=1
TBE=1
Serial output TXD
ST
SP
D0
D1
ST
D0
D1
SP
1 start bit
Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input R
XD
D0
D1
ST
D0
D1
Notes
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 21 Operation of UART serial I/O1 function
[Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is al-
ways valid and sets the output structure of the P25/TXD pin.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
Rev.1.01 Oct 15, 2003 page 24 of 89
3851 Group (Built-in 24 KB or more ROM)
b7
b0
b0
b7
Serial I/O1 status register
(SIOSTS : address 001916
Serial I/O1 control register
(SIOCON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN
1: f(XIN)/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
)
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O1 is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
0: P2
1: P2
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin
pin operates as SRDY1 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
b7
b0
UART control register
(UARTCON : address 001B16
(pins P2
1: Serial I/O1 enabled
(pins P2 to P2 operate as serial I/O1 pins)
4 to P27 operate as ordinary I/O pins)
)
4
7
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P25/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 22 Structure of serial I/O1 control registers
Notes on serial I/O1
2
1. When using the serial I/O1, clear the I C-BUS interface enable
bit to “0” or the SDA/SCL interrupt pin selection bit to “0”.
2. When setting the transmit enable bit of serial I/O1 to “1”, the
serial I/O1 transmit interrupt request bit is automatically set to
“1”. When not requiring the interrupt occurrence synchronized
with the transmission enabled, take the following sequence.
(1)Set the serial I/O1 transmit interrupt enable bit to “0” (dis-
abled).
(2)Set the transmit enable bit to “1”.
(3)Set the serial I/O1 transmit interrupt request bit to “0” after 1
or more instructions have been executed.
(4)Set the serial I/O1 transmit interrupt enable bit to “1” (en-
abled).
Rev.1.01 Oct 15, 2003 page 25 of 89
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SERIAL I/O2
The serial I/O2 can be operated only as the clock synchronous type.
As a synchronous clock for serial transfer, either internal clock or
external clock can be selected by the serial I/O2 synchronous clock
selection bit (b6) of serial I/O2 control register 1.
b7
b0
Serial I/O2 control register 1
(SIO2CON1 : address 001516
)
Internal synchronous clock selection bits
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
0: f(XIN)/128 f(XCIN)/128 in low-speed mode)
1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
The internal clock incorporates a dedicated divider and permits se-
lecting 6 types of clock by the internal synchronous clock selection
bits (b2, b1, b0) of serial I/O2 control register 1.
Regarding SOUT2 and SCLK2 being output pins, either CMOS output
format or N-channel open-drain output format can be selected by the
P01/SOUT2, P02/SCLK2 P-channel output disable bit (b7) of
serial I/O2 control register 1.
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 output pin
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 001716). After comple-
tion of data transfer, the level of the SOUT2 pin goes to high imped-
ance automatically but bit 7 of the serial I/O2 control register 2 is not
set to “1” automatically.
S
0: P0
1: P0
RDY2 output enable bit
3
pin is normal I/O pin
3
pin is SRDY2 output pin
Transfer direction selection bit
0: LSB first
When the external clock has been selected, the contents of the serial
I/O2 register is continuously sifted while transfer clocks are input.
Accordingly, control the clock externally. Note that the SOUT2 pin does
not go to high impedance after completion of data transfer.
To cause the SOUT2 pin to go to high impedance in the case where
the external clock is selected, set bit 7 of the serial I/O2 control reg-
ister 2 to “1” when SCLK2 is “H” after completion of data transfer. After
the next data transfer is started (the transfer clock falls), bit 7 of the
serial I/O2 control register 2 is set to “0” and the SOUT2 pin is put into
the active state.
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P01/SOUT2 ,P02/SCLK2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode )
b7
b0
Serial I/O2 control register 2
(SIO2CON2 : address 001616
)
Optional transfer bits
b2 b1 b0
Regardless of the internal clock to external clock, the interrupt re-
quest bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored in
the serial I/O2 register becomes a fractional number of bits close to
MSB if the transfer direction selection bit of serial I/O2 control regis-
ter 1 is LSB first, or a fractional number of bits close to LSB if the
transfer direction selection bit is MSB first. For the remaining bits, the
previously received data is shifted.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0: 1 bit
1: 2 bit
0: 3 bit
1: 4 bit
0: 5 bit
1: 6 bit
0: 7 bit
1: 8 bit
Not used ( returns "0" when read)
Serial I/O2 I/O comparison signal control bit
At transmit operation using the clock synchronous serial I/O, the SCMP2
signal can be output by comparing the state of the transmit pin SOUT2
with the state of the receive pin SIN2 in synchronization with a rise of
the transfer clock. If the output level of the SOUT2 pin is equal to the
input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H”
is output. At this time, an INT2 interrupt request can also be gener-
ated. Select a valid edge by bit 2 of the interrupt edge selection reg-
ister (address 003A16).
0: P4
1: SCMP2 output
3 I/O
S
OUT2 pin control bit (P0
0: Output active
1: Output high-impedance
1)
Fig. 23 Structure of Serial I/O2 control registers 1, 2
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 /
SIO2CON2)] 001516, 001616
The serial I/O2 control registers 1 and 2 are containing various se-
lection bits for serial I/O2 control as shown in Figure 23.
Rev.1.01 Oct 15, 2003 page 26 of 89
3851 Group (Built-in 24 KB or more ROM)
Internal synchronous
clock selection bits
1/8
X
CIN
1/16
1/32
Data bus
“10”
Main clock division ratio
selection bits (Note)
1/64
“00”
“01”
1/128
1/256
X
IN
P0
3
latch
Serial I/O2 synchronous
clock selection bit
“0”
“1”
P03/SRDY2
S
RDY2
Synchronous circuit
“1”
S
RDY2 output enable bit
“0”
External clock
P02 latch
Optional transfer bits (3)
Serial I/O counter 2 (3)
“0”
P02/SCLK2
Serial I/O2
“1”
interrupt request
Serial I/O2 port selection bit
P01 latch
“0”
P0
1
/SOUT2
/SIN2
“1”
Serial I/O2 port selection bit
P0
0
Serial I/O2 register (8)
P43 latch
“0”
D
P4
3/SCMP2/INT2
Q
“1”
Serial I/O2 I/O comparison
signal control bit
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 24 Block diagram of Serial I/O2
Transfer clock (Note 1)
Write-in signal to
serial I/O2 register
(Note 2)
.
Serial I/O2 output
SOUT2
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes
1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected
by setting bits 0 to 2 of serial I/O2 control register 1.
2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.
Fig. 25 Timing chart of Serial I/O2
Rev.1.01 Oct 15, 2003 page 27 of 89
3851 Group (Built-in 24 KB or more ROM)
S
S
CMP2
CLK2
S
OUT2
S
IN2
Judgement of I/O data comparison
Fig. 26 SCMP2 output operation
Rev.1.01 Oct 15, 2003 page 28 of 89
3851 Group (Built-in 24 KB or more ROM)
2
2
Table 9 Multi-master I C-BUS interface functions
MULTI-MASTER I C-BUS INTERFACE
2
The multi-master I C-BUS interface is a serial communications cir-
Item
Function
2
cuit, conforming to the Philips I C-BUS data transfer format. This
2
In conformity with Philips I C-BUS
standard:
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Format
2
Figure 27 shows a block diagram of the multi-master I C-BUS in-
2
terface and Table 9 lists the multi-master I C-BUS interface
functions.
2
In conformity with Philips I C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
2
2
This multi-master I C-BUS interface consists of the I C address
2
2
register, the I C data shift register, the I C clock control register,
Communication mode
SCL clock frequency
2
2
2
the I C control register, the I C status register, the I C start/stop
condition control register and other control circuits.
2
When using the multi-master I C-BUS interface, set 1 MHz or
16.1 kHz to 400 kHz (at φ= 4 MHz)
more to φ.
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
Note: Renesas Technology Corporation assumes no responsibility for in-
fringement of any third-party’s rights or originating in the use of the
connection control function between the I2C-BUS interface and the
ports SCL1, SCL2, SDA1 and SDA2 with the bit 6 of I2C control regis-
ter (002E16).
I2C address register
b7
b0
SAD6
SAD4 SAD3 SAD2
RWB
SAD1 SAD0
SAD5
Interrupt
generating
circuit
Interrupt request signal
(IICIRQ)
S0D
Address comparator
Noise
elimination
circuit
Data
control
circuit
Serial data
(SDA)
b7
b0
I2C data shift register
b7
b0
S0
AL AAS AD0 LRB
MST TRX BB PIN
S1
AL
circuit
SIS SIP
SSC4 SSC3 SSC2 SSC1 SSC0
I2C status register
2
I C start/stop condition
control register
S2D
Internal data bus
BB
circuit
I2C clock control register
Noise
elimination
circuit
S1D
Serial
clock
(SCL)
Clock
control
circuit
b7
ACK
S2
b0
b7
b0
CLK 10BIT
STP SAD
FAST
ACK
BIT
CCR4 CCR3 CCR2 CCR1 CCR0
TISS
ALS ES0 BC2 BC1 BC0
MODE
S1D I2 C control register
System clock (φ)
I2C clock control register
Bit counter
Clock division
2
Fig. 27 Block diagram of multi-master I C-BUS interface
✽✽: Purchase of Renesas Technology Corporation's I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Rev.1.01 Oct 15, 2003 page 29 of 89
3851 Group (Built-in 24 KB or more ROM)
2
[I C Data Shift Register (S0)] 002B16
2
The I C data shift register (S0 : address 002B16) is an 8-bit shift
b7
b0
I2C address register
(S0D: address 002C16)
register to store receive data and write transmit data.
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL clock, and
each time one-bit data is output, the data of this register are
shifted by one bit to the left. When data is received, it is input to
this register from bit 0 in synchronization with the SCL clock, and
each time one-bit data is input, the data of this register are shifted
by one bit to the left. The minimum 2 machine cycles are required
from the rising of the SCL clock until input to this register.
Read/write bit
Slave address
2
Fig. 28 Structure of I C address register
2
The I C data shift register is in a write enable status only when the
2
I C-BUS interface enable bit (ES0 bit : bit 3 of address 002E16) of
2
the I C control register is “1”. The bit counter is reset by a write in-
2
struction to the I C data shift register. When both the ES0 bit and
2
the MST bit of the I C status register (address 002D16) are “1”, the
2
SCL is output by a write instruction to the I C data shift register.
2
Reading data from the I C data shift register is always enabled re-
gardless of the ES0 bit value.
2
[I C Address Register (S0D)] 002C16
2
The I C address register (address 002C16) consists of a 7-bit
slave address and a read/write bit. In the addressing mode, the
slave address written in this register is compared with the address
data to be received immediately after the START condition is de-
tected.
•Bit 0: Read/write bit (RWB)
This is not used in the 7-bit addressing mode. In the 10-bit ad-
dressing mode, the first address data to be received is compared
2
with the contents (SAD6 to SAD0 + RWB) of the I C address reg-
ister.
The RWB bit is cleared to “0” automatically when the stop condi-
tion is detected.
•Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data
transmitted from the master is compared with the contents of
these bits.
Rev.1.01 Oct 15, 2003 page 30 of 89
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2
[I C Clock Control Register (S2)] 002F16
b7
b0
2
The I C clock control register (address 002F16) is used to set ACK
I2C clock control register
(S2 : address 002F16
ACK FAST
BIT MODE
ACK
CCR4 CCR3 CCR2 CCR1 CCR0
control, SCL mode and SCL frequency.
)
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 10.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0”, the
standard clock mode is selected. When the bit is set to “1”, the
high-speed clock mode is selected.
SCL frequency control bits
Refer to Table 10.
SCL mode specification bit
0 : Standard clock mode
1 : High-speed clock mode
2
ACK bit
When connecting the bus of the high-speed mode I C-BUS stan-
0 : ACK is returned.
1 : ACK is not returned.
dard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(XIN) and 2 division clock.
ACK clock bit
0 : No ACK clock
1 : ACK clock
•Bit 6: ACK bit (ACK BIT)
✽
This bit sets the SDA status when an ACK clock is generated.
When this bit is set to “0”, the ACK return mode is selected and
SDA goes to “L” at the occurrence of an ACK clock. When the bit
is set to “1”, the ACK non-return mode is selected. The SDA is
held in the “H” status at the occurrence of an ACK clock.
2
Fig. 29 Structure of I C clock control register
2
Table 10 Set values of I C clock control register and SCL
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0”, the SDA is auto-
matically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the SDA is auto-
matically made “H” (ACK is not returned).
frequency
Setting value of
CCR4–CCR0
SCL frequency (Note 1)
(at φ = 4 MHz, unit : kHz)
Standard clock
mode
High-speed clock
mode
CCR4 CCR3 CCR2 CCR1 CCR0
Setting disabled Setting disabled
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
✽ACK clock: Clock for acknowledgment
Setting disabled
Setting disabled
333
Setting disabled
Setting disabled
– (Note 2)
– (Note 2)
100
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an ac-
knowledgment response of data transfer. When this bit is set to
“0”, the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1”, the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the SDA at
the occurrence of an ACK clock (makes SDA “H”) and receives the
ACK bit generated by the data receiving device.
250
400 (Note 3)
166
83.3
500/CCR value 1000/CCR value
(Note 3)
(Note 3)
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
34.5
17.2
33.3
16.6
32.3
16.1
Note: Do not write data into the I2C clock control register during transfer. If
data is written during transfer, the I2C clock generator is reset, so
that data cannot be transferred normally.
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 %
only when the high-speed clock mode is selected and CCR value
= 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates
from –4 to +2 machine cycles in the standard clock mode, and
fluctuates from –2 to +2 machine cycles in the high-speed clock
mode. In the case of negative fluctuation, the frequency does not
increase because “L” duration is extended instead of “H” duration
reduction.
These are value when SCL clock synchronization by the syn-
chronous function is not performed. CCR value is the decimal
notation value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or
more. When using these setting value, use φ of 4 MHz or less.
3: The data formula of SCL frequency is described below:
φ/(8 ✽ CCR value) Standard clock mode
φ/(4 ✽ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✽ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the SCL frequency by
setting the SCL frequency control bits CCR4 to CCR0.
Rev.1.01 Oct 15, 2003 page 31 of 89
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2
[I C Control Register (S1D)] 002E16
2
The I C control register (address 002E16) controls data communi-
TSEL
SCL
1
2
/P23
cation format.
SCL
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
SCL
/TxD/P2
5
TSEL
TSEL
Multi-master
2
2
transmitted. The I C interrupt request signal occurs immediately
I C-BUS interface
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
clock bit (bit 7 of address 002F16)) have been transferred, and
BC0 to BC2 are returned to “0002”.
SDA
SDA
1
/P22
SDA
2
/RxD/P2
4
TSEL
Also when a START condition is received, these bits become
“0002” and the address data is always transmitted and received in
8 bits.
Fig. 30 SDA/SCL pin selection bit
2
•Bit 3: I C interface enable bit (ES0)
2
This bit enables to use the multi-master I C-BUS interface. When
this bit is set to “0”, the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“1”, use of the interface is enabled.
b7
b0
I2C control register
(S1D : address 002E16
TSEL 10 BIT
SAD
ES0
TISS
ALS
BC2 BC1 BC0
)
When ES0 = “0”, the following is performed.
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
2
• PIN = “1”, BB = “0” and AL = “0” are set (which are bits of the I C
status register at address 002D16 ).
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : 8
1 : 7
0 : 6
1 : 5
0 : 4
1 : 3
0 : 2
1 : 1
• Writing data to the I C data shift register (address 002B16) is dis-
abled.
•Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0”, the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
I2C-BUS interface
enable bit
0 : Disabled
2
when a general call (refer to “I C Status Register”, bit 1) is re-
ceived, transfer processing can be performed. When this bit is set
to “1”, the free data format is selected, so that slave addresses are
not recognized.
1 : Enabled
Data format selection bit
0 : Addressing format
1 : Free data format
•Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0”, the 7-bit addressing format is selected. In this case,
Addressing format
selection bit
0 : 7-bit addressing
2
only the high-order 7 bits (slave address) of the I C address regis-
format
ter (address 002C16) are compared with address data. When this
1 : 10-bit addressing
format
bit is set to “1”, the 10-bit addressing format is selected, and all
2
the bits of the I C address register are compared with address
SDA/SCL pin selection bit
0 : Connect to ports P2
1 : Connect to ports P2
data.
2
4
, P2
, P2
3
5
•Bit 6: SDA/SCL pin selection bit (TSEL)
This bit selects the input/output pins of SCL and SDA of the multi-
2
I2C-BUS interface pin input
level selection bit
0 : CMOS input
master I C-BUS interface.
2
•Bit 7: I C-BUS interface pin input level selection bit (TISS)
This bit selects the input level of the SCL and SDA pins of the
1 : SMBUS input
2
multi-master I C-BUS interface.
2
Fig. 31 Structure of I C control register
Rev.1.01 Oct 15, 2003 page 32 of 89
3851 Group (Built-in 24 KB or more ROM)
2
[I C Status Register (S1)] 002D16
•Bit 4: SCL pin low hold bit (PIN)
2
2
The I C status register (address 002D16) controls the I C-BUS in-
terface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0”. At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (in-
cluding the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0”, the SCL is kept in the “0” state and
clock generation is disabled. Figure 33 shows an interrupt request
signal generating timing chart.
Set “00002” to the low-order 4 bits, because these bits become the
reserved bits at writing.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0”. If ACK is not returned,
this bit is set to “1”. Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
The PIN bit is set to “1” in one of the following conditions:
2
• Executing a write instruction to the I C data shift register (ad-
2
“0” by executing a write instruction to the I C data shift register
dress 002B16). (This is the only condition which the prohibition of
the internal clock is released and data can be communicated ex-
cept for the start condition detection.)
(address 002B16).
•Bit 1: General call detecting flag (AD0)
✽
When the ALS bit is “0”, this bit is set to “1” when a general call
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives con-
trol data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
• When the ES0 bit is “0”
• At reset
• When writing “1” to the PIN bit by software
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ-
ing when arbitration lost is detected)
✽General call: The master transmits the general call address “0016” to all
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately af-
ter completion of slave address agreement or general call
address reception
slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
• In the slave reception mode, with ALS = “1” and immediately af-
ter completion of address data reception
(1) In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-or-
•Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this
bit is set to “0”, this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins
input signal regardless of master/slave. This flag is set to “1” by
detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of these detecting is set by the start/stop
2
der 7 bits of the I C address register (address 002C16).
• A general call is received.
(2) In the slave receive mode, when the 10-bit addressing format
is selected, this bit is set to “1” with the following condition:
2
condition setting bits (SSC4–SSC0) of the I C start/stop condition
2
• When the address data is compared with the I C address reg-
2
control register (address 003016). When the ES0 bit of the I C
ister (8 bits consisting of slave address and RWB bit), the first
bytes agree.
control register (address 002E16) is “0” or reset, the BB flag is set
to “0”.
2
(3) This bit is set to “0” by executing a write instruction to the I C
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Gen-
erating Method” described later.
data shift register (address 002B16) when ES0 is set to “1” or
reset.
✽
•Bit 3: Arbitration lost detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1”. At the same time, the TRX bit is set to “0”, so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0”. The arbitration lost
can be detected only in the master transmission mode. When ar-
bitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and ad-
dress data transmitted by another master device.
✽Arbitration lost :The status in which communication as a master is dis-
abled.
Rev.1.01 Oct 15, 2003 page 33 of 89
3851 Group (Built-in 24 KB or more ROM)
•Bit 6: Communication mode specification bit (transfer direc-
tion specification bit: TRX)
b7
b0
This bit decides a direction of transfer for data communication.
When this bit is “0”, the reception mode is selected and the data of
a transmitting device is received. When the bit is “1”, the transmis-
sion mode is selected and address data and control data are
output onto the SDA in synchronization with the clock generated
on the SCL.
I2C status register
(S1 : address 002D16)
MST TRX BB PIN AL AAS AD0 LRB
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
This bit is set/reset by software and hardware. About set/reset by
hardware is described below. This bit is set to “1” by hardware
when all the following conditions are satisfied:
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
• When ALS is “0”
• In the slave reception mode or the slave transmission mode
• When the R/W bit reception is “1”
Slave address comparison flag
(Note)
This bit is set to “0” in one of the following conditions:
• When arbitration lost is detected.
0 : Address disagreement
1 : Address agreement
• When a STOP condition is detected.
Arbitration lost detecting flag
(Note)
0 : Not detected
1 : Detected
• When writing “1” to this bit by software is invalid by the START
condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
SCL pin low hold bit
0 : SCL pin low hold
1 : SCL pin low release
•Bit 7: Communication mode specification bit (master/slave
specification bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0”, the slave is specified, so that a START
condition and a STOP condition generated by the master are re-
ceived, and data communication is performed in synchronization
with the clock generated by the master. When this bit is “1”, the
master is specified and a START condition and a STOP condition
are generated. Additionally, the clocks required for data communi-
cation are generated on the SCL.
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
This bit is set to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transfer when arbi-
tration lost is detected
Note: These bits and flags can be read out, but cannot
be written.
Write “0” to these bits at writing.
• When a STOP condition is detected.
• Writing “1” to this bit by software is invalid by the START condi-
tion duplication preventing function (Note).
2
• At reset
Fig. 32 Structure of I C status register
Note: START condition duplication preventing function
The MST, TRX, and BB bits is set to “1” at the same time after con-
firming that the BB flag is “0” in the procedure of a START condition
occurrence. However, when a START condition by another master
device occurs and the BB flag is set to “1” immediately after the con-
tents of the BB flag is confirmed, the START condition duplication
preventing function makes the writing to the MST and TRX bits in-
valid. The duplication preventing function becomes valid from the
rising of the BB flag to reception completion of slave address.
SCL
PIN
IICIRQ
Fig. 33 Interrupt request signal generating timing
Rev.1.01 Oct 15, 2003 page 34 of 89
3851 Group (Built-in 24 KB or more ROM)
START Condition Generating Method
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 36, 37, and Table 13. The START/STOP condition is set
by the START/STOP condition set bit.
2
When writing “1” to the MST, TRX, and BB bits of the I C status
register (address 002D16) at the same time after writing the slave
2
address to the I C data shift register (address 002B16) with the
2
condition in which the ES0 bit of the I C control register (address
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL re-
lease time, setup time, and hold time (see Table 13).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
002E16) and the BB flag are “0”, a START condition occurs. After
that, the bit counter becomes “0002” and an SCL for 1 byte is out-
put. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 34, the START condition generating timing diagram, and
Table 11, the START condition generating timing table.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 13, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “IICIRQ” occurs to the CPU.
I2C status register
write signal
SCL
SDA
Setup
time
SCL release time
Hold time
SCL
SDA
Setup
time
Hold time
BB flag
reset
time
Fig. 34 START condition generating timing diagram
Table 11 START condition generating timing table
BB flag
Fig. 36 START condition detecting timing diagram
Standard clock mode High-speed clock mode
Item
5.0 µs (20 cycles)
5.0 µs (20 cycles)
2.5 µs (10 cycles)
2.5 µs (10 cycles)
Setup time
Hold time
SCL release time
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
SCL
Setup
Hold time
time
BB flag
SDA
reset
time
BB flag
STOP Condition Generating Method
2
When the ES0 bit of the I C control register (address 002E16) is
Fig. 37 STOP condition detecting timing diagram
“1”, write “1” to the MST and TRX bits, and write “0” to the BB bit
2
of the I C status register (address 002D16) simultaneously. Then a
Table 13 START condition/STOP condition detecting conditions
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 35, the STOP condition generating timing
diagram, and Table 12, the STOP condition generating timing
table.
Standard clock mode
High-speed clock mode
SCL release time
SSC value + 1 cycle (6.25 µs)
4 cycles (1.0 µs)
SSC value + 1
Setup time
cycle < 4.0 µs (3.125 µs)
2 cycles (1.0 µs)
2 cycles (0.5 µs)
2
SSC value + 1
Hold time
cycle < 4.0 µs (3.125 µs)
2
BB flag set/
reset time
SSC value –1
3.5 cycles (0.875 µs)
I2C status register
write signal
+ 2 cycles (3.375 µs)
2
Note: Unit : Cycle number of system clock φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at φ = 4 MHz.
SCL
Setup
time
Hold time
SDA
Fig. 35 STOP condition generating timing diagram
Table 12 STOP condition generating timing table
Standard clock mode
5.0 µs (20 cycles)
4.5 µs (18 cycles)
High-speed clock mode
3.0 µs (12 cycles)
Item
Setup time
Hold time
2.5 µs (10 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
Rev.1.01 Oct 15, 2003 page 35 of 89
3851 Group (Built-in 24 KB or more ROM)
2
[I C START/STOP Condition Control Register
Address Data Communication
(S2D)] 003016
The I C START/STOP condition control register (address 003016)
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
(1) 7-bit addressing format
2
controls START/STOP condition detection.
•Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(XIN) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 13.
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
2
the I C control register (address 002E16) to “0”. The first 7-bit
address data transmitted from the master is compared with the
2
high-order 7-bit slave address stored in the I C address regis-
ter (address 002C16). At the time of this comparison, address
2
comparison of the RWB bit of the I C address register (ad-
Do not set “000002” or an odd number to the START/STOP condi-
tion set bit (SSC4 to SSC0).
dress 002C16) is not performed. For the data transmission
format when the 7-bit addressing format is selected, refer to
Figure 39, (1) and (2).
Refer to Table 14, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or
SDA pin interrupt pin.
(2) 10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
2
the I C control register (address 002E16) to “1”. An address
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
2
•Bit 6: SCL/SDA interrupt pin selection bit (SIS)
in the I C address register (address 002C16). At the time of
This bit selects the pin of which interrupt becomes valid between
this comparison, an address comparison between the RWB bit
2
the SCL pin and the SDA pin.
of the I C address register (address 002C16) and the R/W bit
Note: When changing the setting of the SCL/SDA interrupt pin polarity se-
lection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS
interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the inter-
rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/
SDA interrupt pin selection bit, or the I2C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RWB bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is pro-
cessed as an address data bit.
When the first-byte address data agree with the slave address,
2
the AAS bit of the I C status register (address 002D16) is set to
2
“1”. After the second-byte address data is stored into the I C
data shift register (address 002B16), perform an address com-
parison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
2
the slave address, set the RWB bit of the I C address register
(address 002C16) to “1” by software. This processing can
make the 7-bit slave address and R/W data agree, which are
received after a RESTART condition is detected, with the value
2
of the I C address register (address 002C16). For the data
transmission format when the 10-bit addressing format is se-
lected, refer to Figure 39, (3) and (4).
Rev.1.01 Oct 15, 2003 page 36 of 89
3851 Group (Built-in 24 KB or more ROM)
b7
b0
I2C START/STOP condition
control register
SSC4 SSC3 SSC2 SSC1 SSC0
SIS SIP
(S2D : address 003016)
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin selection bit
0 : SDA valid
1 : SCL valid
Reserved
Do not write “1” to this bit.
2
Fig. 38 Structure of I C START/STOP condition control register
Table 14 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Oscillation
frequency
f(XIN) (MHz)
START/STOP
condition
control register
System
clock φ
(MHz)
Main clock
divide ratio
SCL release time
Setup time
Hold time
(µs)
(µs)
(µs)
3.375 µs (13.5 cycles)
3.125 µs (12.5 cycles)
2.5 µs (2.5 cycles)
3.25 µs (6.5 cycles)
2.75 µs (5.5 cycles)
2.5 µs (2.5 cycles)
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
6.75 µs (27 cycles)
6.25 µs (25 cycles)
5.0 µs (5 cycles)
6.5 µs (13 cycles)
5.5 µs (11 cycles)
5.0 µs (5 cycles)
3.375 µs (13.5 cycles)
3.125 µs (12.5 cycles)
2.5 µs (2.5 cycles)
3.25 µs (6.5 cycles)
2.75 µs (5.5 cycles)
2.5 µs (2.5 cycles)
8
8
4
2
2
8
2
2
4
1
2
1
Note: Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0).
(1) A master-transmitter transnmits data to a slave-receiver
A
Data
A
Data
S
Slave address R/W
7 bits “0”
A/A
A
P
P
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
A
Data
A
Data
S
Slave address R/W
7 bits “1”
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
Slave address
2nd bytes
Slave address
1st 7 bits
A/A
A
A
Data
Data
S
R/W
A
P
1 to 8 bits
1 to 8 bits
7 bits
“0”
8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
Slave address
2nd bytes
Slave address
1st 7 bits
Slave address
1st 7 bits
Sr
A
A
A
Data
1 to 8 bits
Data
P
S
R/W
R/W
A
A
“1”
1 to 8 bits
7 bits
“0”
8 bits
7 bits
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
: Master to slave
: Slave to master
Fig. 39 Address data communication format
Rev.1.01 Oct 15, 2003 page 37 of 89
3851 Group (Built-in 24 KB or more ROM)
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
(8) When receiving control data of more than 1 byte, repeat step
(7).
(9) When a STOP condition is detected, the communication
ends.
2
(1) Set a slave address in the high-order 7 bits of the I C ad-
dress register (address 002C16) and “0” into the RWB bit.
(2) Set the ACK return mode and SCL = 100 kHz by setting
2
“8516” in the I C clock control register (address 002F16).
2
(3) Set “0016” in the I C status register (address 002D16) so that
transmission/reception mode can become initializing condi-
tion.
(4) Set a communication enable status by setting “0816” in the
2
I C control register (address 002E16).
2
(5) Confirm the bus free condition by the BB flag of the I C status
register (address 002D16).
(6) Set the address data of the destination of transmission in the
2
high-order 7 bits of the I C data shift register (address
002B16) and set “0” in the least significant bit.
2
(7) Set “F016” in the I C status register (address 002D16) to gen-
erate a START condition. At this time, an SCL for 1 byte and
an ACK clock automatically occur.
2
(8) Set transmit data in the I C data shift register (address
002B16). At this time, an SCL and an ACK clock automatically
occur.
(9) When transmitting control data of more than 1 byte, repeat
step (8).
2
(10) Set “D016” in the I C status register (address 002D16) to gen-
erate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
2
(1) Set a slave address in the high-order 7 bits of the I C ad-
dress register (address 002C16) and “0” in the RWB bit.
(2) Set the no ACK clock mode and SCL = 400 kHz by setting
2
“2516” in the I C clock control register (address 002F16).
2
(3) Set “0016” in the I C status register (address 002D16) so that
transmission/reception mode can become initializing condi-
tion.
(4) Set a communication enable status by setting “0816” in the
2
I C control register (address 002E16).
(5) When a START condition is received, an address comparison
is performed.
(6) • When all transmitted addresses are “0” (general call):
2
AD0 of the I C status register (address 002D16) is set to “1”
and an interrupt request signal occurs.
• When the transmitted addresses agree with the address set
in (1):
2
ASS of the I C status register (address 002D16) is set to “1”
and an interrupt request signal occurs.
2
• In the cases other than the above AD0 and AAS of the I C
status register (address 002D16) are set to “0” and no inter-
rupt request signal occurs.
2
(7) Set dummy data in the I C data shift register (address
002B16).
Rev.1.01 Oct 15, 2003 page 38 of 89
3851 Group (Built-in 24 KB or more ROM)
2
Precautions when using multi-master I C-
BUS interface
5. Disable interrupts during the following three process steps:
• BB flag confirming
(1) Read-modify-write instruction
• Writing of slave address value
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
2
I C-BUS interface are described below.
2
• I C data shift register (S0: address 002B16)
When executing the read-modify-write instruction for this regis-
ter during transfer, data may become a value not intended.
(3) RESTART condition generating procedure
1. Procedure example (The necessary conditions for the proce-
dure are described in items 2 to 4 below.)
2
• I C address register (S0D: address 002C16)
When the read-modify-write instruction is executed for this regis-
ter at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RWB) at the above timing.
Execute the following procedure when the PIN bit is “0”.
•
•
•
LDM #$00, S1
LDA —
(Select slave receive mode)
(Take out of slave address value)
(Disable interrupt)
2
• I C status register (S1: address 002D16)
SEI
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
STAS0
(Write slave address value)
LDM #$F0, S1
CLI
(Trigger RESTART condition generation
)
2
• I C control register (S1D: address 002E16)
(Enable interrupt)
•
•
•
When the read-modify-write instruction is executed for this regis-
ter at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
2. Select the slave receive mode when the PIN bit is “0”. Do not
write “1” to the PIN bit. Neither “0” nor “1” is specified as input to
the BB bit.
2
• I C clock control register (S2: address 002F16)
The TRX bit becomes “0” and the SDA pin is released.
3. The SCL pin is released by writing the slave address value to
The read-modify-write instruction can be executed for this regis-
2
ter.
the I C data shift register.
2
• I C START/STOP condition control register (S2D: address
4. Disable interrupts during the following two process steps:
• Write slave address value
003016)
The read-modify-write instruction can be executed for this regis-
ter.
• Trigger RESTART condition generation
2
(4) Writing to I C status register
(2) START condition generating procedure using multi-master
1. Procedure example (The necessary conditions of the generat-
ing procedure are described in Items 2 to 5 below.
Do not execute an instruction to set the PIN bit to “1” from “0” and
an instruction to set the MST and TRX bits to “0” from “1” simulta-
neously. Because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to “0” from “1” simultaneously when the PIN bit is “1”. Because it
may become the same as above.
•
•
•
LDA —
(Taking out of slave address value)
(Interrupt disabled)
SEI
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
BUSFREE:
STA S0
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
(5) Process of after STOP condition generating
2
2
LDM #$F0, S1
CLI
Do not write data in the I C data shift register S0 and the I C sta-
tus register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. Because the
STOP condition waveform might not be normally generated.
Reading to the above registers do not have the problem.
•
•
•
BUSBUSY:
CLI
(Interrupt enabled)
•
•
•
2. Use “Branch on Bit Set” of “BBS 5, $002D, –” for the BB flag
confirming and branch process.
3. Use “STA $2B, STX $2B” or “STY $2B” of the zero page ad-
dressing instruction for writing the slave address value to the
2
I C data shift register.
4. Execute the branch instruction of Item 2 and the store instruc-
tion of Item 3 continuously, as shown in the procedure example
above.
Rev.1.01 Oct 15, 2003 page 39 of 89
3851 Group (Built-in 24 KB or more ROM)
PULSE WIDTH MODULATION (PWM)
The 3851 group (built-in 24 KB or more ROM) has a PWM func-
tion with an 8-bit resolution, based on a signal that is the clock
input XIN or that clock input divided by 2.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Data Setting
The PWM output pin also functions as port P44. Set the PWM
period by the PWM prescaler, and set the “H” term of output pulse
by the PWM register.
31.875 ✽ m ✽ (n+1)
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 X (n+1) / f(XIN)
µs
255
PWM output
= 31.875 X (n+1) µs
(when f(XIN) = 8 MHz,count source selection bit = “0”)
Output pulse “H” term = PWM period X m / 255
= 0.125 X (n+1) X m µs
T = [31.875 ✽ (n+1)] µs
m: Contents of PWM register
(when f(XIN) = 8 MHz,count source selection bit = “0”)
n : Contents of PWM prescaler
T : PWM period (when f(XIN) = 8 MHz, count
source selection bit = “0”)
Fig. 40 Timing of PWM period
Data bus
PWM
prescaler pre-latch
PWM
register pre-latch
Transfer control circuit
PWM
prescaler latch
PWM
register latch
Count source
selection bit
Port P4
4
“0”
X
IN
PWM prescaler
PWM register
(XCIN at low-speed mode)
“1”
1/2
Port P44 latch
PWM enable bit
Fig. 41 Block diagram of PWM function
Rev.1.01 Oct 15, 2003 page 40 of 89
3851 Group (Built-in 24 KB or more ROM)
b7
b0
PWM control register
(PWMCON : address 001D16
)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN) (f(XCIN) at low-speed mode)
1: f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Not used (return “0” when read)
Fig. 42 Structure of PWM control register
B
T
C
T2
=
A
B
C
PWM output
T
T2
T
PWM register
write signal
(Changes “H” term from “A” to “B”.)
PWM prescaler
write signal
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 43 PWM output timing when PWM register or PWM prescaler is changed
Note
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L” level output is as follows:
n+1
sec
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
(Count source selection bit = 1, where n is the value set in the prescaler)
2 • f(XIN)
n+1
f(XIN)
Rev.1.01 Oct 15, 2003 page 41 of 89
3851 Group (Built-in 24 KB or more ROM)
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
003516, 003616
b7
b0
A-D control register
(ADCON : address 003416)
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion.
Analog input pin selection bits
b2 b1 b0
0 0 0: P30/AN0
0 0 1: P31/AN1
0 1 0: P32/AN2
0 1 1: P33/AN3
1 0 0: P34/AN4
[A-D Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Not used (returns “0” when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
Fig. 44 Structure of A-D control register
AVSS and VREF into 1024 and outputs the divided voltages.
Channel Selector
10-bit reading
(Read address 003616 before 003516
The channel selector selects one of ports P30/AN0 to P34/AN4 and
)
inputs the voltage to the comparator.
b0
b7
(Address 003616
(Address 003516
)
b9 b8
Comparator and Control Circuit
b7
b0
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
)
b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 003616 become “0”
at reading.
Note that because the comparator consists of a capacitor cou-
pling, set f(XIN) to 500 kHz or more during an A-D conversion.
When the A-D converter is operated at low-speed mode, f(XIN)
and f(XCIN) do not have the lower limit of frequency, because of
the A-D converter has a built-in self-oscillation circuit.
8-bit reading (Read only address 003516
)
b0
b7
(Address 003516
)
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 45 Structure of A-D conversion registers
Data bus
b7
3
b0
A-D control register
(Address 003416
)
A-D interrupt request
A-D control circuit
P30/AN0
P3
P3
P3
1
2
3
/AN
/AN
/AN
1
2
3
A-D conversion high-order register (Address 003616
)
)
Comparator
(Address 003516
A-D conversion low-order register
10
P34/AN4
Resistor ladder
V
REF AVSS
Fig. 46 Block diagram of A-D converter
Rev.1.01 Oct 15, 2003 page 42 of 89
3851 Group (Built-in 24 KB or more ROM)
WATCHDOG TIMER
Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) per-
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at f(XIN)
= 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal di-
vided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is
set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN) =
32 kHz frequency. This bit is cleared to “0” after reset.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 003916) after reset, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watch-
dog timer H.
Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003916) may be
started before an underflow. When the watchdog timer control reg-
ister (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watch-
dog timer H count source selection bit are read.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, once the STP
instruction is executed, an internal reset occurs. When this bit is
set to “1”, it cannot be rewritten to “0” by program. This bit is
cleared to “0” after reset.
Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L are set to “FF16”.
“FF16” is set when
watchdog timer
Data bus
“FF16” is set when
watchdog timer
control register is
X
CIN
control register is
written to.
“0”
“10”
written to.
Watchdog timer L (8)
Main clock division
ratio selection bits
(Note)
Watchdog timer H (8)
1/16
“1”
“00”
“01”
Watchdog timer H count
source selection bit
X
IN
STP instruction disable bit
STP instruction
Reset
circuit
Internal reset
RESET
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 47 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 003916
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 48 Structure of Watchdog timer control register
Rev.1.01 Oct 15, 2003 page 43 of 89
3851 Group (Built-in 24 KB or more ROM)
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an “L”
level for 20 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage must be between 2.7 V
and 5.5 V, and the oscillation must be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.54 V for VCC of 2.7 V.
Poweron
(Note)
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage; Vcc = 2.7 V
RESET
V
CC
Power source
voltage detection
circuit
Fig. 49 Reset circuit example
X
IN
φ
RESET
RESETOUT
Address
AD
H,L
?
?
?
?
FFFC
FFFD
Reset address from the vector table.
AD
H
Data
?
?
?
AD
L
?
SYNC
X
IN: 8 to 13 clock cycles
Notes1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
3: All signals except XIN and RESET are internals.
Fig. 50 Reset sequence
Rev.1.01 Oct 15, 2003 page 44 of 89
3851 Group (Built-in 24 KB or more ROM)
Address Register contents
Register contents
Address
(1)
Port P0 (P0)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
001516
001616
001716
(36) A-D control register (ADCON)
(37) A-D conversion low-order register (ADL)
(38) A-D conversion high-order register (ADH)
(39) MISRG
0016
0 0 0 1 0 0 0 0
X X X X X X X X
003416
003516
(2)
Port P0 direction register (P0D)
Port P1 (P1)
0016
(3)
0016
003616 0 0 0 0 0 0 X X
(4)
Port P1 direction register (P1D)
Port P2 (P2)
0016
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
0016
Watchdog timer control register (WDTCON)
(40)
(5)
0016
0 0 1 1 1 1 1 1
0016
(6)
Port P2 direction register (P2D)
Port P3 (P3)
(41) Interrupt edge selection register (INTEDGE)
(42) CPU mode register (CPUM)
0016
(7)
0016
0 1 0 0 1 0 0 0
0016
Interrupt request register 1 (IREQ1)
(43)
(8)
Port P3 direction register (P3D)
Port P4 (P4)
0016
0016
Interrupt request register 2 (IREQ2)
(44)
(9)
0016
0016
Interrupt control register 1 (ICON1)
(45)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
Port P4 direction register (P4D)
Serial I/O2 control register 1 (SIO2CON1)
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
0016
Interrupt control register 2 (ICON2)
(46)
0016
0016
(47) Processor status register
(48) Program counter
0 0 0 0 0 1 1 1
X X X X X X X X
X X X X X 1 X X
FFFD16 contents
FFFC16 contents
(PCH)
001816 X X X X X X X X
(PC
L
)
001916
001A16
001B16
1 0 0 0 0 0 0 0
0016
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
1 1 1 0 0 0 0 0
001C16 X X X X X X X X
001D16
001E16
0016
X X X X X X X X
001F16 X X X X X X X X
Prescaler 12 (PRE12)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002C16
002D16
002E16
002F16
FF16
0116
Timer 1 (T1)
Timer 2 (T2)
0016
Timer XY mode register (TM)
Prescaler X (PREX)
0016
FF16
Timer X (TX)
FF16
Prescaler Y (PREY)
FF16
Timer Y (TY)
FF16
Timer count source selection register (TCSS)
I2C address regiter (S0D)
I2C status register (S1)
0016
0016
0 0 0 1 0 0 0
0016
X
X
I2C control register (S1D)
I2C clock control register (S2)
0016
2
003016 0 0 0
I C start/stop condition control register (S2D)
X
X X X
Fig. 51 Internal status at reset
Rev.1.01 Oct 15, 2003 page 45 of 89
3851 Group (Built-in 24 KB or more ROM)
When the oscillator is restarted by reset, apply “L” level to the
RESET pin until the oscillation is stable since a wait time will not
be generated.
CLOCK GENERATING CIRCUIT
The 3851 group (built-in 24 KB or more ROM) has two built-in os-
cillation circuits: main clock XIN-XOUT oscillation circuit and sub
clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be
formed by connecting a resonator between XIN and XOUT (XCIN
and XCOUT). Use the circuit constants in accordance with the reso-
nator manufacturer’s recommended values. No external resistor is
needed between XIN and XOUT since a feed-back resistor exists
on-chip. However, an external feed-back resistor is needed be-
tween XCIN and XCOUT.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before ex-
ecuting of the STP or WIT instruction.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruc-
tion.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
set is released, this mode is selected.
Note
(2) High-speed mode
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
Note
If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately af-
ter power on and at returning from the stop mode. When switching
the mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3•f(XCIN).
XCIN XCOUT
XIN
XOUT
Rf
Rd
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
COUT
CCIN
CCOUT
CIN
Fig. 52 Ceramic resonator circuit
The sub-clock XCIN-XCOUT oscillation circuit can not directly input
clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
Oscillation Control
(1) Stop mode
XCIN
X
COUT
XIN
XOUT
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillation stops. When the oscillation
stabilizing time set after STP instruction released bit is “0”, the
prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the
oscillation stabilizing time set after STP instruction released bit is
“1”, set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
Either XIN or XCIN divided by 16 is input to the prescaler 12 as
count source. Oscillator restarts when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU (remains
at “H”) until timer 1 underflows. The internal clock φ is supplied for
the first time, when timer 1 underflows. This ensures time for the
clock oscillation using the ceramic resonators to be stabilized.
Open
Rf
Rd
External oscillation
circuit
C
CIN
CCOUT
Vcc
Vss
Fig. 53 External clock input circuit
Rev.1.01 Oct 15, 2003 page 46 of 89
3851 Group (Built-in 24 KB or more ROM)
Notes on middle-speed mode automatic
switch set bit
b7
b0
MISRG
(MISRG : address 003816)
When the middle-speed mode automatic switch set bit is set to “1”
while operating in the low-speed mode, by detecting the rising/fall-
ing edge of the SCL or SDA pin, XIN oscillation automatically starts
and the mode is automatically switched to the middle-speed
mode. The timing which changes from the low-speed mode to the
middle-speed mode can be set as 4.5 to 5.5 cycle, or 6.5 to 7.5
cycle in the low-speed mode by the middle-speed mode automatic
switch waiting time set bit. Select according to the oscillation start
characteristic of the XIN oscillator to be used.
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
Note: When the mode is automatically switched from the low-speed mode to
the middle-speed mode, the value of CPU mode register (address 003B16)
changes.
Fig. 54 Structure of MISRG
XCOUT
XCIN
“0”
“1”
Port X
C
switch bit
XOUT
XIN
Timer 12 count source
selection bit
Main clock division ratio
selection bits (Note 1)
Low-speed mode
1/2
Prescaler 12
FF16
Timer 1
0116
1/4
1/2
Reset or
STP instruction
(Note 2)
High-speed or
middle-speed
mode
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Reset
Q
S
R
S
R
Q
Q
S
R
STP instruction
STP instruction
WIT instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
2: When bit 0 of MISRG = “0”
Fig. 55 System clock generating circuit block diagram (Single-chip mode)
Rev.1.01 Oct 15, 2003 page 47 of 89
3851 Group (Built-in 24 KB or more ROM)
Reset
High-speed mode
(f(φ) = 4 MHz)
Middle-speed mode
(f(φ) = 1 MHz)
CM6
“1” ←→ “0”
CM
CM
CM
CM
7
= 0
= 0
CM
CM
CM
CM
7
6
5
4
= 0
= 1
6
5
4
= 0 (8 MHz oscillating)
= 0 (32 kHz stopped)
= 0 (8 MHz oscillating)
= 0 (32 kHz stopped)
C
”
M
0
“
“
4
0
”
M4
”
C
←→
M
←→
0
“
C
“
6
1
”
”
1
“
M6
”
“
1
←→
←→
C
”
1
“
“
0
”
Middle-speed mode
(f(φ) = 1 MHz)
High-speed mode
(f(φ) = 4 MHz)
CM6
“1” ←→ “0”
CM
CM
CM
CM
7
= 0
= 1
CM
7
6
5
4
= 0
= 0
6
5
4
CM
CM
CM
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
C
M
“
7
0
”
C
←→
M
“
6
1
”
“
1
←→
”
“
0
”
Low-speed mode
(f(φ)=16 kHz)
CM
CM
CM
CM
7
= 1
= 0
6
5
4
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16
)
CM
CM
CM
4
5
7
: Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
: Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
, CM
6: Main clock division ratio selection bits
Low-speed mode
(f(φ)=16 kHz)
b7 b6
CM
CM
CM
CM
7
6
5
4
= 1
= 0
0
0
1
1
0 : φ = f(XIN)/2 ( High-speed mode)
1 : φ = f(XIN)/8 (Middle-speed mode)
0 : φ = f(XCIN)/2 (Low-speed mode)
1 : Not available
= 1 (8 MHz stopped)
= 1 (32 kHz oscillating)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed
mode.
5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed.
(1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”.
(2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 56 State transitions of system clock
Rev.1.01 Oct 15, 2003 page 48 of 89
3851 Group (Built-in 24 KB or more ROM)
FLASH MEMORY MODE
Summary
The M38517F8 (flash memory version) has an internal new
DINOR (DIvided bit line NOR) flash memory that can be rewritten
with a single power source when VCC is 5 V, and 2 power sources
when VPP is 5 V and VCC is 3.0-5.5 V in the CPU rewrite and stan-
dard serial I/O modes.
Table 15 lists the summary of the M38517F8 (flash memory ver-
sion).
The flash memory of the M38517F8 is divided into User ROM area
and Boot ROM area as shown in Figure 57.
In addition to the ordinary User ROM area to store the MCU op-
eration control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user’s application sys-
tem. This Boot ROM area can be rewritten in only parallel I/O
mode.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
Table 15 Summary of M38517F8 (flash memory version)
Item
Specifications
Vcc = 2.7– 5.5 V (Note 1)
Vcc = 2.7–3.6 V (Note 2)
Power source voltage
4.5-5.5 V
VPP voltage (For Program/Erase)
Flash memory mode
3 modes (Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode)
1 block (32 Kbytes)
Erase block division
User ROM area
Boot ROM area
1 block (4 Kbytes) (Note 3)
Byte program
Program method
Erase method
Batch erasing
Program/Erase control by software command
Program/Erase control method
Number of commands
6 commands
100 times
Number of program/Erase times
ROM code protection
Available in parallel I/O mode and standard serial I/O mode
Notes 1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation.
2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation.
3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be
rewritten in only parallel I/O mode.
Rev.1.01 Oct 15, 2003 page 49 of 89
3851 Group (Built-in 24 KB or more ROM)
(1) CPU Rewrite Mode
Microcomputer Mode and Boot Mode
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central Process-
ing Unit (CPU).
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode beforehand.
(If the control program is written into the Boot ROM area, the stan-
dard serial I/O mode becomes unusable.)
In CPU rewrite mode, only the User ROM area shown in Figure 57
can be rewritten; the Boot ROM area cannot be rewritten. Make
sure the program and block erase commands are issued for only
the User ROM area and each block area.
See Figure 57 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer
is reset with pulling CNVSS pin low. In this case, the CPU starts
operating using the control program in the User ROM area.
When the microcomputer is reset by pulling the P41/INT0 pin high,
the CNVss pin high, the CPU starts operating using the control
program in the Boot ROM area (program start address is FFFC16,
FFFD16 fixation). This mode is called the “Boot” mode.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite con-
trol program must be transferred to internal RAM area to be
executed before it can be executed.
Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command. In case
of the M38517F8, it has only one block.
Parallel I/O mode
800016
F00016
4 kbyte
FFFF16
Block 1 : 32 kbyte
FFFF16
User ROM area
Boot ROM area
BSEL = 0
BSEL = 1
CPU rewrite mode, standard serial I/O mode
800016
F00016
4 kbyte
FFFF16
Block 1 : 32 kbyte
Flash memory
start address
Product name
FFFF16
User ROM area
Boot ROM area
M38517F8
800016
User area / Boot area selection bit = 0
User area / Boot area selection bit = 1
Notes 1: The Boot ROM area can be rewritten in only parallel
input/output mode. (Access to any other areas is inhibited.)
2: To specify a block, use the maximum address in the block.
Fig. 57 Block diagram of built-in flash memory
Rev.1.01 Oct 15, 2003 page 50 of 89
3851 Group (Built-in 24 KB or more ROM)
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten in CPU rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory by executing software commands. This
rewrite control program must be transferred to the RAM before it
can be executed.
Therefore, use the control program in the RAM for write to bit 1. To
set this bit to “1”, it is necessary to write “0” and then write “1” in
succession. The bit can be set to “0” by only writing “0”.
Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in
CPU rewrite mode, so that reading this flag can check whether
CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit
of internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the
control circuit. To set this bit to “1”, it is necessary to write “0” and
then write “1” in succession. To release the reset, it is necessary
to set this bit to “0”.
The MCU enters CPU rewrite mode by applying 5 V ± 0.5 V to the
CNVSS pin and setting “1” to the CPU Rewrite Mode Select Bit (bit
1 of address 0FFE16). Software commands are accepted once the
mode is entered.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In Boot mode, this bit is set to “1” auto-
matically. Reprogramming of this bit must be in the RAM.
Figure 59 shows a flowchart for setting/releasing CPU rewrite
mode.
Figure 58 shows the flash memory control register.
Bit 0 is the RY/BY status flag used exclusively to read the operat-
ing status of the flash memory. During programming and erase
operations, it is “0” (busy). Otherwise, it is “1” (ready).
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
“1”, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly.
b7
b0
Flash memory control register (address 0FFE16) (Note 1)
FMCR
RY/BY status flag
0: Busy (being programmed or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode
1: CPU rewrite mode
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User ROM area / Boot ROM area select bit (Note 4)
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (Indefinite at read/ “0” at write)
Notes 1: The contents of flash memory control register are “XXX00001” just after reset release. In the mask
ROM version, this address is reserved area.
2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not
this procedure, this bit will not be set to “1”. Additionally, it is required to ensure that no interrupt
will be generated during that interval.
Use the control program in the area except the built-in flash memory for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after
setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory for write to this bit.
Fig. 58 Structure of flash memory control register
Rev.1.01 Oct 15, 2003 page 51 of 89
3851 Group (Built-in 24 KB or more ROM)
Start
Single-chip mode or Boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control program
to RAM
Setting
Jump to control program transferred in RAM
(Subsequent operations are executed by control
program in this RAM)
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
Released
Write “0” to CPU rewrite mode select bit
End
Notes 1: When starting the MCU in the single-chip mode, supply 4.5 V to 5.5 V to the CNVss
pin until checking the CPU rewrite mode entry flag.
2: Set bits 6, 7 (main clock division ratio selection bits) at CPU mode register (003B16).
3: Before exiting the CPU rewrite mode after completing erase or program operation,
always be sure to execute the read array command or reset the flash memory.
Fig. 59 CPU rewrite mode set/release flowchart
Rev.1.01 Oct 15, 2003 page 52 of 89
3851 Group (Built-in 24 KB or more ROM)
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting
the flash memory in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode, set the internal clock frequency 4.0
MHz or less using the main clock division ratio selection bits (bit
6, 7 at 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode be-
cause they refer to the internal data of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the in-
ternal reset generated by watchdog timer underflow does not
happen, because of watchdog timer is always clearing during
program or erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = H when reset is re-
leased, boot mode is active. So the program starts from the ad-
dress contained in address FFFC16 and FFFD16 in boot ROM
area.
Rev.1.01 Oct 15, 2003 page 53 of 89
3851 Group (Built-in 24 KB or more ROM)
Software Commands (CPU Rewrite Mode)
Table 16 lists the software commands.
register mode is entered automatically and the contents of the sta-
tus register is read at the data bus (D0 to D7). The status register
bit 7 (SR7) is set to “0” at the same time the write operation starts
and is returned to “1” upon completion of the write operation. In
this case, the read status register mode remains active until the
After setting the CPU Rewrite Mode Select Bit of the flash memory
control register to “1”, execute a software command to specify an
erase or program operation.
Each software command is explained below.
next command is written.
____
The RY/BY Status Flag is “0” (busy) during write operation and “1”
(ready) when the write operation is completed as is the status reg-
ister bit 7.
Read Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified ad-
dress are read out at the data bus (D0 to D7).
At program end, program results can be checked by reading bit 4
(SR4) of the status register.
The read array mode is retained intact until another command is
written.
Start
Read Status Register Command (7016)
Write 4016
The read status register mode is entered by writing the command
code “7016” in the first bus cycle. The contents of the status regis-
ter are read out at the data bus (D0 to D7) by a read in the second
bus cycle.
Write address
Write
Write data
The status register is explained in the next section.
Status register
read
Clear Status Register Command (5016)
This command is used to clear the bits SR1, SR4, and SR5 of the
status register after they have been set. These bits indicate that
operation has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
SR7 = 1 ?
NO
or
RY/BY = 1 ?
Program Command (4016)
YES
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
NO
Program
error
SR4 = 0 ?
YES
Whether the write operation is completed can be confirmed by
_____
reading the status register or the RY/BY Status Flag of the flash
memory control register. When the program starts, the read status
Program completed
(Read array command
“FF16” write)
Fig. 60 Program flowchart
First bus cycle
Table 16 List of software commands (CPU rewrite mode)
Second bus cycle
Command
Cycle number
Data
to D7)
Data
to D7)
Mode
Address
Mode
Address
(D
0
(D0
(Note 1)
Read array
1
2
1
Write
Write
Write
X
FF16
7016
5016
(Note 2)
Read status register
Clear status register
X
X
Read
X
SRD
(Note 3)
(Note 3)
Program
2
2
2
Write
Write
Write
X
X
X
4016
2016
2016
Write
Write
Write
WA
WD
Erase all blocks
Block erase
X
2016
D016
(Note 4)
BA
Notes 1: X denotes a given address in the User ROM area .
2: SRD = Status Register Data
3: WA = Write Address, WD = Write Data
4: BA = Block Address to be erased (Input the maximum address of each block.)
Rev.1.01 Oct 15, 2003 page 54 of 89
3851 Group (Built-in 24 KB or more ROM)
Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that
follows, the operation of erase all blocks (erase and erase verify)
starts.
Start
Whether the erase all blocks command is terminated can be con-
____
Write 2016
firmed by reading the status register or the RY/BY Status Flag of
flash memory control register. When the erase all blocks operation
starts, the read status register mode is entered automatically and
the contents of the status register can be read out at the data bus
(D0 to D7). The status register bit 7 (SR7) is set to “0” at the same
time the erase operation starts and is returned to “1” upon comple-
tion of the erase operation. In this case, the read status register
2016/D016
Block address
2016:Erase all blocks command
D016:Block erase command
Write
Status register
read
mode remains active until another command is written.
____
SR7 = 1 ?
or
RY/BY = 1 ?
The RY/BY Status Flag is “0” during erase operation and “1” when
the erase operation is completed as is the status register bit 7
(SR7).
NO
NO
YES
After the erase all blocks end, erase results can be checked by
reading bit 5 (SRS) of the status register. For details, refer to the
section where the status register is detailed.
Erase error
SR5 = 0 ?
YES
Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the block address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
Erase completed
(Read comand “FF16
”
write)
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY Status Flag of flash
memory control register. At the same time the block erase opera-
tion starts, the read status register mode is automatically entered,
so that the contents of the status register can be read out. The
status register bit 7 (SR7) is set to “0” at the same time the block
erase operation starts and is returned to “1” upon completion of
the block erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is writ-
Fig. 61 Erase flowchart
ten.
____
The RY/BY Status Flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status reg-
ister bit 7.
After the block erase ends, erase results can be checked by read-
ing bit 5 (SRS) of the status register. For details, refer to the
section where the status register is detailed.
Rev.1.01 Oct 15, 2003 page 55 of 89
3851 Group (Built-in 24 KB or more ROM)
Status Register (SRD)
•Erase status (SR5)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to “1”.
The program status is set to “0” when it is cleared.
Also, the status register can be cleared by writing the clear status
register command (5016).
If “1” is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status regis-
ter command (5016) and clear the status register.
Also, if any commands are not correct, both SR5 and SR4 are set
to “1”.
After reset, the status register is set to “8016”.
Table 17 shows the status register. Each bit in this register is ex-
plained below.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
Table 17 Definition of each bit in status register (SRD)
Definition
Symbol
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Rev.1.01 Oct 15, 2003 page 56 of 89
3851 Group (Built-in 24 KB or more ROM)
Full Status Check
By performing full status check, it is possible to know the execu-
full status check flowchart and the action to be taken when each
error occurs.
tion results of erase and program operations. Figure 62 shows a
Read status register
YES
SR4 = 1 and
SR5 = 1 ?
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
operation one more time after confirming that the
command is entered correctly.
NO
NO
NO
Should an erase error occur, the block in error
cannot be used.
Erase error
SR5 = 0 ?
YES
Should a program error occur, the block in error
cannot be used.
Program error
SR4 = 0 ?
YES
End (erase, program)
Note: When one of SR5 and SR4 is set to “1”, none of the read array, the program, erase
all blocks, and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 62 Full status check flowchart and remedial procedure for errors
Rev.1.01 Oct 15, 2003 page 57 of 89
3851 Group (Built-in 24 KB or more ROM)
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check func-
tion for use in standard serial I/O mode.
the ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is se-
lected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM Code Protect Reset Bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be read out or modified. Once the ROM code
protect is turned on, the contents of the ROM Code Protect Reset
Bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM Code Pro-
tect Reset Bits.
ꢀROM Code Protect Function (in Parallel I/O Mode)
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control (address FFDB16) in parallel I/O
mode. Figure 63 shows the ROM code protect control (address
FFDB16). (This address exists in the User ROM area.)
If one or both of the pair of ROM Code Protect Bits is set to “0”,
b7
b0
ROM code protect control register (address FFDB16) (Note 1)
ROMCP
1 1
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (Note 4)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 2)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
Notes 1: This area is on the ROM in the mask ROM version.
2: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
3: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
4: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU
rewrite mode.
Fig. 63 Structure of ROM code protect control
Rev.1.01 Oct 15, 2003 page 58 of 89
3851 Group (Built-in 24 KB or more ROM)
ID Code Check Function (in Standard serial
I/O mode)
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the pro-
grammer is compared with the ID code written in the flash memory
to see if they match. If the ID codes do not match, the commands
sent from the programmer are not accepted. The ID code consists
of 8-bit data, and its areas are FFD416 to FFDA16. Write a pro-
gram which has had the ID code preset at these addresses to the
flash memory.
Address
FFD416
FFD516
FFD616
FFD716
FFD816
FFD916
FFDA16
FFDB16
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ROM code protect control
Interrupt vector area
Fig. 64 ID code store addresses
Rev.1.01 Oct 15, 2003 page 59 of 89
3851 Group (Built-in 24 KB or more ROM)
(2) Parallel I/O Mode
Parallel I/O mode is the mode which parallel output and input soft-
ware command, address, and data required for the operations
(read, program, erase, etc.) to a built-in flash memory. Use the ex-
clusive external equipment flash programmer which supports the
3851 Group (flash memory version). Refer to each programmer
maker’s handling manual for the details of the usage.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in
Figure 57 can be rewritten. Both areas of flash memory can be oper-
ated on in the same way.
Program and block erase operations can be performed in the user ROM
area. The user ROM area and its block is shown in Figure 57.
The boot ROM area is 4 Kbytes in size. It is located at addresses
F00016 through FFFF16. Make sure program and block erase opera-
tions are always performed within this address range. (Access to any
location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial I/O
mode control program stored in it when shipped from the Renesas
factory. Therefore, using the device in standard serial I/O mode, you
do not need to write to the boot ROM area.
Rev.1.01 Oct 15, 2003 page 60 of 89
3851 Group (Built-in 24 KB or more ROM)
(3) Standard serial I/O Mode
Outline Performance (Standard Serial I/O
Mode)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programmer, etc.) using 4-wire clock-synchronized serial
I/O (serial I/O1).
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, pro-
gram, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires the exclusive external
equipment (serial programmer).
The standard serial I/O mode is different from the parallel I/O
mode in that the CPU controls flash memory rewrite (uses the
CPU rewrite mode), rewrite data input and so forth. The standard
serial I/O mode is started by connecting “H” to the P26 (SCLK1) pin
and “H” to the P41 (INT0) pin and “H” to the CNVSS pin (apply 4.5
V to 5.5 V to Vpp from an external source), and releasing the re-
set operation. (In the ordinary microcomputer mode, set CNVss
pin to “L” level.)
In reception, software commands, addresses and program data
are synchronized with the rise of the transfer clock that is input to
the SCLK1 pin, and are then input to the MCU via the RxD pin. In
transmission, the read data and status are synchronized with the
fall of the transfer clock, and output from the TxD pin.
The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB
first.
When busy, such as during transmission, reception, erasing or
program execution, the SRDY1 (BUSY) pin is “H” level. Accord-
ingly, always start the next transfer after the SRDY1 (BUSY) pin is
“L” level.
This control program is written in the Boot ROM area when the
product is shipped from Renesas Technology Corporation. Accord-
ingly, make note of the fact that the standard serial I/O mode
cannot be used if the Boot ROM area is rewritten in parallel I/O
mode. Figure 65 shows the pin connection for the standard serial
I/O mode.
Also, data and status registers in a memory can be read after in-
putting software commands. Status, such as the operating state of
the flash memory or whether a program or erase operation ended
successfully or not, can be checked by reading the status register.
Here following explains software commands, status registers, etc.
In standard serial I/O mode, serial data I/O uses the four serial I/O
pins SCLK1, RxD, TxD and SRDY1 (BUSY). The SCLK1 pin is the
transfer clock input pin through which an external transfer clock is
input. The TxD pin is for CMOS output. The SRDY1 (BUSY) pin
outputs “L” level when ready for reception and “H” level when re-
ception starts.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in
Figure 57 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, commands sent from the peripheral
unit (programmer) are not accepted unless the ID code matches.
Rev.1.01 Oct 15, 2003 page 61 of 89
3851 Group (Built-in 24 KB or more ROM)
Table 18 Description of pin function (Standard Serial I/O Mode)
Pin
Name
Power input
I/O
Description
V
CC,VSS
Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin.
Connect to VCC when VCC = 4.5 V to 5.5 V.
Connect to Vpp (=4.5 V to 5.5 V) when VCC = 2.7 V to 4.5 V.
CNVSS
RESET
CNVSS
I
I
Reset input
Reset input pin. While reset is “L” level, a 20 cycle or longer clock
must be input to XIN pin.
Connect a ceramic resonator or crystal oscillator between XIN and
X
IN
OUT
AVSS
REF
Clock input
I
X
OUT pins. To input an externally generated clock, input it to XIN pin
X
Clock output
O
and open XOUT pin.
Analog power supply input
Connect AVSS to VSS
.
V
Reference voltage input
Input port P0
Input port P1
Input port P2
RxD input
I
I
I
Enter the reference voltage for AD from this pin, or open.
Input “H” or “L”, or open.
P0
0
0
to P0
to P1
7
7
Input “H” or “L”, or open.
P1
Input “H” or “L”, or open.
P2
0
to P2
3
I
I
This pin is for serial data input.
This pin is for serial data output.
P2
P2
P2
P2
4
5
6
7
TxD output
O
I
S
CLK1 input
This pin is for serial clock input.
This pin is for BUSY signal output.
O
I
BUSY output
Input port P3
Input port P4
Input port P4
Input “H” or “L”, or open.
P3
0
0
to P3
, P4
4
I
Input “H” or “L”, or open.
P4
2
to P44
P4
1
I
Input “H” when RESET is released only.
Rev.1.01 Oct 15, 2003 page 62 of 89
3851 Group (Built-in 24 KB or more ROM)
V
CC
SS
V
P3
P3
P3
P3
P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
V
CC
1
2
3
4
42
41
40
39
38
37
36
35
34
VREF
AVSS
/PWM
/SCMP2
/INT
P4
P4
4
/INT
3
3/INT
2
5
P4
P4
2
1
0
1
P0
P0
P0
P0
P0
P0
P0
P0
P1
P1
P1
P1
P1
P1
P1
P1
0/SIN2
6
P41
1
/INT
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
/SOUT2
/SCLK2
/SRDY2
7
P4
/CNTR
P2
P2
P2
P2 /SCL
P2 /SDA
CNVSS
P2
P2
0
/CNTR
8
B
USY
P2
7
0
/SRDY1
9
S
CLK1
6
/SCLK1
10
11
12
13
14
15
16
17
18
19
20
21
33
TxD
RxD
5
/TxD
32
31
4
/RxD
D
3
1
30
29
28
27
26
25
24
23
22
2
1
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
0
1
2
3
4
5
6
7
)
)
)
)
)
)
)
)
ꢀꢀ2
VPP
1
/XCIN
0
/XCOUT
RESET
RESET
X
IN
OUT
SS
ꢀꢀ1
X
V
Mode setup method
Signal
CNVSS
P4
Value
4.5 to 5.5 V
Notes 1: Connect oscillator circuit
2: Connect to Vcc when Vcc = 4.5 V to 5.5 V.
V
V
CC ꢀ 3
CC ꢀ 3
1
Connect to VPP (=4.5 V to 5.5 V) when Vcc = 2.7 V to 4.5 V.
3: It is necessary to apply Vcc only when reset is released.
S
CLK1
VSS → VCC
RESET
Fig. 65 Pin connection diagram in standard serial I/O mode
Rev.1.01 Oct 15, 2003 page 63 of 89
3851 Group (Built-in 24 KB or more ROM)
Software Commands (Standard Serial I/O
Mode)
commands via the RxD pin. Software commands are explained
here below.
Table 19 lists software commands. In standard serial I/O mode,
erase, program and read are controlled by transferring software
Table 19 Software commands (Standard serial I/O mode)
1st byte 2nd byte
transfer
3rd byte
4th byte
5th byte
6th byte
When ID is
not verified
.....
Control command
Address
(middle)
Address
(high)
Data
Data
Data
Data
output to
259th byte
Not
acceptable
FF16
1
2
Page read
output
output
output
Data input
to 259th
byte
Data
input
Data
input
Data
input
Address
4116
Address
(high)
Not
acceptable
Page program
(middle)
Not
acceptable
D016
A716
3
4
5
6
Erase all blocks
SRD1
output
SRD
7016
Acceptable
Read status register
Clear status register
ID code check
output
Not
acceptable
5016
Address
(middle)
Address
F516
Address
(high)
ID1
To ID7
Acceptable
ID size
(low)
To
Data
input
Check-
sum
Size
(high)
Size
FA16
Not
acceptable
required
number
of times
7
8
Download function
(low)
Version
data
output
Version
data output
to 9th byte
Version
data
output
Version
data
output
Version
data
output
Version
data
output
Acceptable
Version data output function
FB16
Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from an external equipment
(programmer) to the internal flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted when the flash memory is totally blank.
4: Address high must be “0016”.
Rev.1.01 Oct 15, 2003 page 64 of 89
3851 Group (Built-in 24 KB or more ROM)
ꢀPage Read Command
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
This command reads the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page read
command as explained here following.
(3) From the 4th byte onward, data (D0 to D7) for the page (256
bytes) specified with addresses A8 to A23 will be output se-
quentially from the smallest address first synchronized with the
fall of the clock.
S
CLK1
RxD
TxD
A
8
to
A16 to
FF16
A
15
A23
data0
data255
S
RDY1(BUSY)
Fig. 66 Timing for page read
ꢀRead Status Register Command
This command reads status information. When the “7016” com-
mand code is transferred with the 1st byte, the contents of the
status register (SRD) with the 2nd byte and the contents of status
register 1 (SRD1) with the 3rd byte are read.
S
CLK1
RxD
TxD
7016
SRD
output
SRD1
output
S
RDY1(BUSY)
Fig. 67 Timing for reading status register
Rev.1.01 Oct 15, 2003 page 65 of 89
3851 Group (Built-in 24 KB or more ROM)
ꢀClear Status Register Command
This command clears the bits (SR4, SR5) which are set when the
status register operation ends in error. When the “5016” command
code is sent with the 1st byte, the aforementioned bits are
cleared. When the clear status register operation ends, the SRDY1
(BUSY) signal changes from “H” to “L” level.
S
CLK1
RxD
TxD
5016
S
RDY1(BUSY)
Fig. 68 Timing for clear status register
ꢀPage Program Command
(3) From the 4th byte onward, as write data (D0 to D7) for the
page (256 bytes) specified with addresses A8 to A23 is input
sequentially from the smallest address first, that page is auto-
matically written.
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page pro-
gram command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the
2nd and 3rd bytes respectively.
When reception setup for the next 256 bytes ends, the SRDY1
(BUSY) signal changes from “H” to “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
S
CLK1
RxD
TxD
A
8
to
A16 to
4116
data0
data255
A
15
A23
SRDY1(BUSY)
Fig. 69 Timing for page program
Rev.1.01 Oct 15, 2003 page 66 of 89
3851 Group (Built-in 24 KB or more ROM)
ꢀErase All Blocks Command
When erase all blocks end, the SRDY1 (BUSY) signal changes
from “H” to “L” level. The result of the erase operation can be
known by reading the status register.
This command erases the contents of all blocks. Execute the
erase all blocks command as explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte.
With the verify command code, the erase operation will start
and continue for all blocks in the flash memory.
S
CLK1
RxD
TxD
A716
D016
SRDY1(BUSY)
Fig. 70 Timing for erase all blocks
Rev.1.01 Oct 15, 2003 page 67 of 89
3851 Group (Built-in 24 KB or more ROM)
ꢀDownload Command
This command downloads a program to the RAM for execution.
Execute the download command as explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is
added to all data sent with the 5th byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches,
the downloaded program is executed. The size of the program will
vary according to the internal RAM.
S
CLK1
RxD
TxD
Data size Data size
(low) (high)
Check
sum
Program
data
FA16
Program
data
S
RDY1(BUSY)
Fig. 71 Timing for download
Rev.1.01 Oct 15, 2003 page 68 of 89
3851 Group (Built-in 24 KB or more ROM)
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte on-
ward. This data is composed of 8 ASCII code characters.
ꢀVersion Information Output Command
This command outputs the version information of the control pro-
gram stored in the Boot ROM area. Execute the version
information output command as explained here following.
S
CLK1
RxD
TxD
FB16
‘V’
‘E’
‘R’
‘X’
S
RDY1(BUSY)
Fig. 72 Timing for version information output
Rev.1.01 Oct 15, 2003 page 69 of 89
3851 Group (Built-in 24 KB or more ROM)
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”)
of the 1st byte of the ID code with the 2nd, 3rd, and 4th bytes
respectively.
ꢀID Check
This command checks the ID code. Execute the boot ID check
command as explained here following.
(3) Transfer the number of data sets of the ID code with the 5th
byte.
(4) Transfer the ID code with the 6th byte onward, starting with the
1st byte of the code.
S
CLK1
RxD
TxD
F516
D416
FF16
0016
ID size
ID1
ID7
S
RDY1(BUSY)
Fig. 73 Timing for ID check
ꢀID Code
When the flash memory is not blank, the ID code sent from the se-
rial programmer and the ID code written in the flash memory are
compared to see if they match. If the codes do not match, the
command sent from the serial programmer is not accepted. An ID
code contains 8 bits of data. Area is, from the 1st byte, addresses
FFD416 to FFDA16. Write a program into the flash memory, which
already has the ID code set for these addresses.
Address
FFD416
ID1
ID2
ID3
ID4
ID5
ID6
ID7
FFD516
FFD616
FFD716
FFD816
FFD916
FFDA16
FFDB16
ROM code protect control
Interrupt vector area
Fig. 74 ID code storage addresses
Rev.1.01 Oct 15, 2003 page 70 of 89
3851 Group (Built-in 24 KB or more ROM)
ꢀStatus Register (SRD)
•Sequencer status (SR7)
The status register indicates operating status of the flash memory
and status such as whether an erase operation or a program
ended successfully or in error. It can be read by writing the read
status register command (7016). Also, the status register is
cleared by writing the clear status register command (5016).
Table 20 lists the definition of each status register bit. After releas-
ing the reset, the status register becomes “8016”.
The sequencer status indicates the operating status of the flash
memory.
After power-on and recover from deep power down mode, the se-
quencer status is set to “1” (ready).
This status bit is set to “0” (busy) during write or erase operation
and is set to “1” upon completion of these operations.
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write opera-
tion. If a program error occurs, it is set to “1”. When the program
status is cleared, it is set to “0”.
Table 20 Definition of each bit of status register (SRD)
Definition
SRD0 bits
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Rev.1.01 Oct 15, 2003 page 71 of 89
3851 Group (Built-in 24 KB or more ROM)
•Boot update completed bit (SR15)
ꢀStatus Register 1 (SRD1)
This flag indicates whether the control program was downloaded
to the RAM or not, using the download function.
The status register 1 indicates the status of serial communica-
tions, results from ID checks and results from check sum
comparisons. It can be read after the status register (SRD) by writ-
ing the read status register command (7016). Also, status register
1 is cleared by writing the clear status register command (5016).
Table 21 lists the definition of each status register 1 bit. This regis-
ter becomes “0016” when power is turned on and the flag status is
maintained even after the reset.
•Check sum consistency bit (SR12)
This flag indicates whether the check sum matches or not when a
program, is downloaded for execution using the download func-
tion.
•ID check completed bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands
cannot be accepted without an ID code check.
•Data reception time out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the re-
ceived data is discarded and the MCU returns to the command
wait state.
Table 21 Definition of each bit of status register 1 (SRD1)
Definition
SRD1 bits
Status name
“1”
“0”
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
Boot update completed bit
Reserved
Update completed
Not Update
-
-
-
Reserved
-
Checksum match bit
ID check completed bits
Match
00
Mismatch
Not verified
01
Verification mismatch
Reserved
10
11
Verified
SR9 (bit1)
SR8 (bit0)
Data reception time out
Reserved
Time out
-
Normal operation
-
Rev.1.01 Oct 15, 2003 page 72 of 89
3851 Group (Built-in 24 KB or more ROM)
Full Status Check
Results from executed erase and program operations can be
known by running a full status check. Figure 75 shows a flowchart
of the full status check and explains how to remedy errors which
occur.
Read status register
YES
SR4 = 1 and
SR5 = 1 ?
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
operation one more time after confirming that the
command is entered correctly.
NO
NO
NO
Should an erase error occur, the block in error
cannot be used.
Erase error
SR5 = 0 ?
YES
Should a program error occur, the block in error
cannot be used.
Program error
SR4 = 0 ?
YES
End (Erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks
commands is accepted. Execute the clear status register command (5016) before
executing these commands.
Fig. 75 Full status check flowchart and remedial procedure for errors
Rev.1.01 Oct 15, 2003 page 73 of 89
3851 Group (Built-in 24 KB or more ROM)
Example Circuit Application for Standard
Serial I/O Mode
Figure 76 shows a circuit application for the standard serial I/O
mode. Control pins will vary according to a programmer, therefore
see a programmer manual for more information.
P41
S
CLK1
Clock input
BUSY output
Data input
SRDY1 (BUSY)
R
XD
TXD
Data output
M38517F8
V
PP power
CNVss
source input
Notes 1: Control pins and external circuitry will vary according to peripheral unit. For more
information, see the peripheral unit manual.
2: In this example, the Vpp power supply is supplied from an external source (writer). To use
the user’s power source, connect to 4.5 V to 5.5 V.
3: It is necessary to apply Vcc to SCLK1 pin only when reset is released.
Fig. 76 Example circuit application for standard serial I/O mode
Rev.1.01 Oct 15, 2003 page 74 of 89
3851 Group (Built-in 24 KB or more ROM)
Flash memory Electrical characteristics
Table 22 Absolute maximum ratings
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 6.5
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF
VI
–0.3 to VCC +0.3
V
VI
VI
VI
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to 6.5
V
V
V
All voltages are based on VSS.
Output transistors are cut off.
Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
VO
–0.3 to VCC +0.3
V
VO
Output voltage P22, P23
Power dissipation
–0.3 to 5.8
1000 (Note)
25±5
V
mW
°C
Pd
Ta = 25 °C
Topr
Tstg
Operating temperature
Storage temperature
–40 to 125
°C
Note: The rating becomes 300 mW at the 42P2R-A/E package.
Table 23 Flash memory mode Electrical characteristics
o
(Ta = 25 C, VCC = 4.5 to 5.5V unless otherwise noted)
Limits
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
100
60
IPP1
VPP power source current (read)
VPP power source current (program)
VPP power source current (erase)
VPP power source voltage
VPP = VCC
µA
mA
mA
V
VPP = VCC
VPP = VCC
IPP2
IPP3
VPP
VCC
30
4.5
4.5
5.5
VCC power source voltage
Microcomputer mode operation at
VCC = 2.7 to 5.5V
5.5
3.6
V
V
Microcomputer mode operation at
VCC = 2.7 to 3.6V
3.0
Rev.1.01 Oct 15, 2003 page 75 of 89
3851 Group (Built-in 24 KB or more ROM)
NOTES ON PROGRAMMING
A-D Converter
Processor Status Register
The comparator uses capacitive coupling amplifier whose charge
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) in the middle/high-speed mode is
at least on 500 kHz during an A-D conversion.
Do not execute the STP instruction during an A-D conversion.
Instruction Execution Time
Interrupts
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency in
high-speed mode.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
NOTES ON USAGE
Differences between 3851 group (built-in 16
KB ROM) and 3851 group (built-in 24 KB or
more ROM)
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
(1) The absolute maximum ratings of 3851 group (built-in 24 KB or
more ROM) is smaller than that of 3851 group (built-in 16 KB
ROM).
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
•Power source voltage Vcc = –0.3 to 6.5 V
quency division ratio is 1/(n+1).
•CNVss input voltage
VI = –0.3 to Vcc +0.3 V (M38514M6, M38517M8)
VI = –0.3 to 6.5 V (M38517F8)
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may
be some differences between 3851 group (built-in 16 KB
ROM) and 3851 group (built-in 24 KB or more ROM).
(3) Do not write any data to the reserved area and the reserved
bit. (Do not change the contents after rest.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
• The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin) and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the pins
to be connected, a ceramic capacitor of 0.01 µF–0.1µF is recom-
mended.
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
EPROM Version/One Time PROM Version/
Flash Memory Version
In serial I/O1 (clock synchronous mode), if the receive side is us-
ing an external clock and it is to output the SRDY1 signal, set the
transmit enable bit, the receive enable bit, and the SRDY1 output
enable bit to “1”.
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational in-
terference even if it is connected to Vss pin or Vcc pin via a
resistor.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed.
SOUT2 pin for serial I/O2 goes to high impedance after transmis-
sion is completed.
When an external clock is used as synchronous clock in serial
I/O1 or serial I/O2, write transmission data to the transmit buffer
register or serial I/O2 register while the transfer clock is “H”.
Rev.1.01 Oct 15, 2003 page 76 of 89
3851 Group (Built-in 24 KB or more ROM)
Electric Characteristic Differences Among
Mask ROM, Flash Memory, and One Time
PROM Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation among mask ROM, flash
memory, and One Time PROM version MCUs due to the differ-
ences in the manufacturing processes.
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
When manufacturing an application system with the flash memory,
One Time PROM version and then switching to use of the mask
ROM version, perform sufficient evaluations for the commercial
samples of the mask ROM version.
Table 20 Programming adapter
Package
42P4B, 42S1B
42P2R-A/E
Name of Programming Adapter
PCA4738S-42A
PCA4738F-42A
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 77 is recommended to verify programming.
ꢀ
1. Mask ROM Order Confirmation Form
ꢀ
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
Programming with PROM
programmer
DATA REQUIRED FOR One Time PROM
PROGRAMMING ORDERS
The following are necessary when ordering a PROM programming
service:
ꢀ
1. ROM Programming Confirmation Form
Screening (Caution)
(150 °C for 40 hours)
ꢀ
2. Mark Specification Form (only special mark with customer’s
trade mark logo)
3. Data to be programmed to PROM, in EPROM form (three iden-
tical copies) or one floppy disk.
Verification with
PROM programmer
ꢀFor the mask ROM confirmation and the mark specifications, re-
fer to the “Renesas Technology ” Homepage ROM ordering
(http://www.renesas.com/eng/rom).
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 77 Programming and testing of One Time PROM version
Rev.1.01 Oct 15, 2003 page 77 of 89
3851 Group (Built-in 24 KB or more ROM)
Electrical characteristics
Absolute maximum ratings
Table 25 Absolute maximum ratings
Symbol
Parameter
Conditions
Ratings
Unit
V
VCC
–0.3 to 6.5
Power source voltage
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF
VI
V
–0.3 to VCC +0.3
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to 13
VI
VI
VI
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS M38514M6, M38514M8
M38514E6
V
V
V
V
V
All voltages are based on VSS.
Output transistors are cut off.
–0.3 to 6.5
M38517F8
Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
–0.3 to VCC +0.3
VO
V
–0.3 to 5.8
1000 (Note)
–20 to 85
VO
Output voltage P22, P23
Power dissipation
V
mW
°C
Pd
Ta = 25 °C
Topr
Tstg
Operating temperature
Storage temperature
–40 to 125
°C
Note : The rating becomes 300mW at the 42P2R-A/E package.
Rev.1.01 Oct 15, 2003 page 78 of 89
3851 Group (Built-in 24 KB or more ROM)
Recommended operating conditions
Table 26 Recommended operating conditions (1)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
4.0
Max.
5.5
VCC
Power source voltage
Power source voltage
8 MHz (high-speed mode)
5.0
5.0
0
V
V
8 MHz (middle-speed mode), 4 MHz(high-speed mode)
2.7
5.5
VSS
VREF
AVSS
VIA
V
A-D convert reference voltage
Analog power source voltage
Analog input voltage
2.0
0
VCC
V
0
V
AN0–AN4
AVSS
VCC
VCC
5.8
V
VIH
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P34, P40–P44 0.8VCC
V
2
VIH
“H” input voltage (when I C-BUS input level is selected)
SDA1, SCL1
SDA2, SCL2
SDA1, SCL1
SDA2, SCL2
0.7VCC
V
0.7VCC
VCC
5.8
V
VIH
“H” input voltage (when SMBUS input level is selected)
1.4
V
1.4
VCC
VCC
0.2VCC
0.3VCC
0.6
V
VIH
“H” input voltage
“L” input voltage
____________, XIN, CNVSS
RESET
0.8VCC
V
VIL
P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
0
0
0
0
0
V
2
VIL
“L” input voltage (when I C-BUS input level is selected) SDA1, SDA2, SCL1, SCL2
V
VIL
“L” input voltage (when SMBUS input level is selected) SDA1, SDA2, SCL1, SCL2
V
VIL
“L” input voltage
“L” input voltage
____________, CNVSS
RESET
0.2VCC
0.16VCC
–80
V
VIL
XIN
V
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
“H” total peak output current (Note) P00–P07, P10–P17, P30–P34
“H” total peak output current (Note) P20, P21, P24–P27, P40–P44
“L” total peak output current (Note) P00–P07, P30–P34
“L” total peak output current (Note) P10–P17
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
–80
80
120
“L” total peak output current (Note) P20–P27,P40–P44
“H” total average output current (Note) P00–P07, P10–P17, P30–P34
“H” total average output current (Note) P20, P21, P24–P27, P40–P44
“L” total average output current (Note) P00–P07, P30–P34
“L” total average output current (Note) P10–P17
80
–40
–40
40
60
“L” total average output current (Note) P20–P27,P40–P44
40
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
Rev.1.01 Oct 15, 2003 page 79 of 89
3851 Group (Built-in 24 KB or more ROM)
Table 27 Recommended operating conditions (2)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
mA
Min.
Max.
IOH(peak)
“H” peak output current
“L” peak output current
(Note 1) P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
–10
P40–P44
IOL(peak)
IOH(avg)
IOL(avg)
(Note 1) P00–P07, P20–P27, P30–P34, P40–P44,
P10–P17
10
20
–5
mA
mA
mA
“H” average output current (Note 2) P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44
“L” average output current (Note 2) P00–P07, P20–P27, P30–P34, P40–P44,
P10–P17
5
15
8
mA
mA
Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3)
Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3)
MHz
MHz
f(XIN)
f(XIN)
4
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
Electrical characteristics
Table 28 Electrical characteristics (1)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Test conditions
Min.
Max.
VOH
VOL
VOL
“H” output voltage
IOH = –10 mA
VCC–2.0
V
V
V
V
V
V
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
(Note)
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 2.7–5.5 V
IOL = 10 mA
VCC–1.0
“L” output voltage
2.0
1.0
2.0
1.0
P00–P07, P20–P27, P30–P34,
P40–P44
VCC = 4.0–5.5 V
IOL = 1.0 mA
VCC = 2.7–5.5 V
IOL = 20 mA
“L” output voltage
P10–P17
VCC = 4.0–5.5 V
IOL = 10 mA
VCC = 2.7–5.5 V
Note: P25 is measured when the P25/SCL2/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Rev.1.01 Oct 15, 2003 page 80 of 89
3851 Group (Built-in 24 KB or more ROM)
Table 29 Electrical characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
VT+–VT–
Parameter
Unit
V
Test conditions
Min.
Max.
Hysteresis
0.4
0.5
0.5
CNTR0, CNTR1, INT0–INT3
VT+–VT–
Hysteresis
V
RxD, SCLK1, SIN2, SCLK2
____________
VT+–VT–
Hysteresis
V
RESET
IIH
“H” input current
VI = VCC
5.0
µA
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
____________
IIH
IIH
IIL
“H” input current
VI = VCC
VI = VCC
VI = VSS
5.0
µA
µA
µA
RESET, CNVSS
“H” input current XIN
“L” input current
4
–5.0
P00–P07, P10–P17, P20–P27
P30–P34, P40–P44
____________
IIL
“L” input current
“L” input current
RAM hold voltage
VI = VSS
–5.0
µA
µA
V
RESET,CNVSS
XIN
IIL
VI = VSS
–4
VRAM
When clock stopped
2.0
5.5
Rev.1.01 Oct 15, 2003 page 81 of 89
3851 Group (Built-in 24 KB or more ROM)
Table 30 Electrical characteristics (3)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Test conditions
Symbol
Parameter
Unit
mA
Max.
13
Min.
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
6.8
1.6
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
mA
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Except
M38517F8FP/SP
60
200
µA
µA
µA
250
M38517F8FP/SP
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Except
M38517F8FP/SP
40
55
20
M38517F8FP/SP
µA
µA
70
20
Except
M38517F8FP/SP
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
ICC
Power source current
f(XCIN) = 32.768 kHz
Output transistors “off”
150
5.0
M38517F8FP/SP
µA
µA
µA
Except
M38517F8FP/SP
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
10.0
7.0
M38517F8FP/SP
20
Middle-speed mode
f(XIN) = 8 MHz
f(XCIN) = stopped
Output transistors “off”
mA
mA
4.0
Middle-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = stopped
1.5
Output transistors “off”
Increment when A-D conversion is executed
f(XIN) = 8 MHz
µA
µA
µA
800
0.1
All oscillation stopped
(in STP state)
Ta = 25 °C
1.0
10
Output transistors “off”
Ta = 85 °C
Rev.1.01 Oct 15, 2003 page 82 of 89
3851 Group (Built-in 24 KB or more ROM)
A-D converter characteristics
Table 31 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
10
–
–
Resolution
bit
Absolute accuracy (excluding quantization error)
Conversion time
±4
LSB
tc(φ)
High-speed mode,
Middle-speed mode
tCONV
61
Low-speed mode
40
35
µs
kΩ
µA
RLADDER
IVREF
Ladder resistor
VREF = 5.0 V
VREF “on”
VREF “off”
Reference power source input current
50
150
200
5.0
5.0
II(AD)
A-D port input current
0.5
µA
Rev.1.01 Oct 15, 2003 page 83 of 89
3851 Group (Built-in 24 KB or more ROM)
Timing requirements
Table 32 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
20
Max.
Reset input “L” pulse width
XIN cycle
ns
tW(RESET)
tC(XIN)
External clock input cycle time
125
50
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
ns
tWH(XIN)
50
ns
tWL(XIN)
200
80
ns
tC(CNTR)
ns
tWH(CNTR)
tWL(CNTR)
tWH(INT)
80
ns
80
ns
80
ns
tWL(INT)
800
370
370
220
100
1000
400
400
200
200
ns
tC(SCLK1)
ns
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
ns
ns
ns
Serial I/O1 input hold time
ns
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
ns
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
ns
ns
ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 33 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
20
Max.
XIN cycle
ns
tW(RESET)
tC(XIN)
Reset input “L” pulse width
External clock input cycle time
250
100
100
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
ns
tWH(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
ns
tWL(XIN)
ns
tC(CNTR)
ns
tWH(CNTR)
tWL(CNTR)
tWH(INT)
ns
ns
ns
tWL(INT)
ns
tC(SCLK1)
ns
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
ns
ns
ns
Serial I/O1 input hold time
ns
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
ns
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
ns
ns
ns
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
Rev.1.01 Oct 15, 2003 page 84 of 89
3851 Group (Built-in 24 KB or more ROM)
Switching characteristics
Table 34 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
140
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tC(SCLK1)/2–30
tC(SCLK1)/2–30
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig. 79
–30
30
30
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tC(SCLK2)/2–160
tC(SCLK2)/2–160
200
0
30
30
30
tr (CMOS)
10
10
tf (CMOS)
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Table 35 Switching characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Unit
Parameter
Test conditions
Min.
Typ.
Max.
350
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
tC(SCLK1)/2–50
tC(SCLK1)/2–50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
Fig. 79
–30
50
50
tf (SCLK1)
tC(SCLK2)/2–240
tC(SCLK2)/2–240
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
400
0
50
50
50
20
20
tr (CMOS)
tf (CMOS)
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Rev.1.01 Oct 15, 2003 page 85 of 89
3851 Group (Built-in 24 KB or more ROM)
2
MULTI-MASTER I C-BUS BUS LINE CHARACTERISTICS
2
Table 36 Multi-master I C-BUS bus line characteristics
Standard clock mode
High-speed clock mode
Symbol
Parameter
Unit
Test conditions
Min.
4.7
Max.
Max.
Min.
1.3
tBUF
Bus free time
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
tHD;STA
tLOW
0.6
1.3
Hold time for START condition
Hold time for SCL clock = “0”
Rising time of both SCL and SDA signals
Data hold time
4.0
4.7
tR
20+0.1Cb
0
300
0.9
1000
300
tHD;DAT
tHIGH
tF
0
Fig. 80
Hold time for SCL clock = “1”
Falling time of both SCL and SDA signals
Data setup time
4.0
0.6
20+0.1Cb
100
300
tSU;DAT
tSU;STA
tSU;STO
250
4.7
4.0
Setup time for repeated START condition
Setup time for STOP condition
0.6
0.6
Note: Cb = total capacitance of 1 bus line
SDA
t
HD:STA
tsu:STO
t
BUF
t
LOW
t
R
t
F
p
Sr
p
S
SCL
t
HD:STA
t
HD:DTA
t
HIGH
tsu:DAT
tsu:STA
2
Fig. 78 Timing diagram of multi-master I C-BUS
1 kΩ
Measurement output pin
Measurement output pin
100 pF
100 pF
CMOS output
N-channnel open-drain
Fig. 79 Circuit for measuring output switching characteristics (1)
Fig. 80 Circuit for measuring output switching characteristics (2)
Rev.1.01 Oct 15, 2003 page 86 of 89
3851 Group (Built-in 24 KB or more ROM)
t
C(CNTR)
t
WL(CNTR)
t
WH(CNTR)
CNTR
CNTR
0
1
0.8VCC
0.2VCC
0.2VCC
t
WL(INT)
t
WH(INT)
0.8VCC
INT
0
to INT
3
t
W(RESET)
0.8VCC
RESET
0.2VCC
t
C(XIN)
t
WL(XIN)
t
WH(XIN)
0.8VCC
XIN
0.2VCC
t
C(SCLK1),
t
C(SCLK2)
t
WL(SCLK1),
t
WL(SCLK2
)
t
WH(SCLK1), WH(SCLK2)
t
t
r
t
f
S
CLK1
CLK2
0.8VCC
S
0.2VCC
t
t
h(SCLK1
h(SCLK2
-
-
RxD),
t
t
su(R
x
D
-
S
CLK1),
CLK2
S
IN2)
su(SIN2
-
S
)
R D
X
IN2
0.8V
0.2VCCCC
S
t
t
d(SCLK1-TXD),
t
t
v(SCLK1-T
XD),
d(SCLK2-SOUT2
)
v(SCLK2-SOUT2
)
T D
X
SOUT2
Fig. 81 Timing diagram
Rev.1.01 Oct 15, 2003 page 87 of 89
3851 Group (Built-in 24 KB or more ROM)
PACKAGE OUTLINE
MMP
42P4B
Plastic 42pin 600mil SDIP
EIAJ Package Code
SDIP42-P-600-1.78
JEDEC Code
–
Weight(g)
4.1
Lead Material
Alloy 42/Cu Alloy
42
22
1
21
Dimension in Millimeters
Symbol
Min
–
0.51
–
Nom
–
–
Max
5.5
–
A
A1
A2
b
b1
b2
c
D
E
e
e1
D
3.8
–
0.35
0.9
0.63
0.22
36.5
12.85
–
–
3.0
0°
0.45
1.0
0.55
1.3
1.03
0.34
36.9
13.15
–
–
–
15°
0.73
0.27
36.7
13.0
1.778
15.24
–
e
b1
b
b2
L
SEATING PLANE
–
42P2R-A/E
Plastic 42pin 450mil SSOP
EIAJ Package Code
SSOP42-P-450-0.80
JEDEC Code
Weight(g)
0.63
Lead Material
Alloy 42
e
b2
–
42
22
Recommended Mount Pad
Dimension in Millimeters
F
Symbol
Min
–
0.05
–
0.25
0.13
17.3
8.2
–
11.63
0.3
–
–
–
–
0°
–
–
1.27
Nom
–
–
Max
2.4
–
A
A
A
1
21
1
2
A
2.0
0.3
0.15
17.5
8.4
0.8
11.93
0.5
1.765
0.75
–
–
D
G
b
0.4
0.2
17.7
8.6
–
12.23
0.7
–
c
D
E
e
H
L
A
2
A1
e
b
E
y
L1
z
Z
y
–
1
0.9
0.15
10°
–
–
–
–
–
c
z
b2
0.5
11.43
–
Z
1
Detail G
Detail F
e1
I
2
Rev.1.01 Oct 15, 2003 page 88 of 89
3851 Group (Built-in 24 KB or more ROM)
42S1B-A
Metal seal 42pin 600mil DIP
EIAJ Package Code
WDIP42-C-600-1.78
JEDEC Code
Weight(g)
–
D
42
22
1
21
Dimension in Millimeters
Symbol
Min
–
1.0
–
0.38
0.7
0.17
–
–
–
–
3.05
–
Nom
–
–
Max
5.0
–
3.44
0.54
0.9
0.33
41.1
15.8
–
A
A1
A2
b
b1
c
D
E
e
e1
–
0.46
0.8
0.25
–
e
Z
b
b1
SEATING PLANE
–
1.778
15.24
–
–
–
L
Z
–
3.05
Rev.1.01 Oct 15, 2003 page 89 of 89
3851 Group (built-in 24 KB or more ROM) Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Jul. 26, 2002
1.01 Oct. 15, 2003
–
First edition issued
•Mitsubishi, Mitsubishi Electric Corporation → Renesas Technology Corporation
•SCLK → SCLK1
2
2
1
5
ꢀMulti-master I C-BUS interface (option) → ꢀMulti-master I C-BUS interface
Fig.4 Memory expansion plan
Under development M38517M8/F8 → Mass production M38517M8/F8
“SDA input”, “SCL input”
“Serial I/O1 input”
(12)Port P26 External clock input → Serial I/O1 external clock input
(13)Port P27 Serial ready output → Serial I/O1 ready output
•Interrupt occur by 17 sources among 17 sources seven external
→ Interrupt occur by 17 sources : seven external
•address 3A16, address 2316 → address 003A16, address 002316
Table 8 Interrupt vector addresses and priority
14-15
15
17
18
22
Serial I/O1 reception, Serial I/O transmission : Remarks
Valid when serial I/O1 is selected → Valid when serial I/O is selected
Fig.18 Block diagram of clock synchronous serial I/O
__________
__________
P27/SRDY1 → P27/CNTR0/SRDY1
29
32
MITSUBISHI ELECTRIC CORPORATION’S → Renesas Technology Corporation’s
•Bit 6: SDA/SCL pin selection bit → Bit 6: SDA/SCL pin selection bit (TSEL)
2
•Bit 7: I C-BUS interface pin input level selection bit
2
→ Bit 7: I C-BUS interface pin input level selection bit (TISS)
77
79
“Mitsubishi MCU Technical Information” Homepage (http:// www.
infomicom.maec.co.jp/indexe.htm)
→ “Renesas Technology” Homepage Rom ordering (http:// www. renesas.com/eng/rom)
Table 26 Recommended operating conditions (1)
Limits
Typ.
Symbol
VIH
Parameter
Unit
Min.
0.7VCC
Max.
VCC
5.8
VCC
5.8
2
“H” input voltage (when I C-BUS input level is selected)
SDA2, SCL2
V
V
V
V
SDA1, SCL1 0.7VCC
1.4
SDA1, SCL1
VIH
“H” input voltage (when SMBUS input level is selected)
SDA2, SCL2
1.4
Limits
Typ.
Symbol
VIH
Parameter
2
Unit
Min.
Max.
5.8
VCC
5.8
“H” input voltage (when I C-BUS input level is selected) SDA1, SCL1 0.7VCC
V
V
V
V
SDA2, SCL2 0.7VCC
VIH
“H” input voltage (when SMBUS input level is selected) SDA1, SCL1
1.4
1.4
SDA2, SCL2
VCC
81
Table 29 Electrical characteristics (2)
VT+–VT- Hysterisis RXD, SCLK → RXD, SCLK1, SIN2, SCLK2
(1/1)
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
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