M38821FA-XXXHP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38821FA-XXXHP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总62页 (文件大小：600K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3882 Group
REJ03B0089-0101
Rev.1.01
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Nov 14, 2005
GENERAL DESCRIPTION
The 3882 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
ꢀTimers ............................................................................. 8-bit ꢀ 4
ꢀWatchdog timer ............................................................ 16-bit ꢀ 1
ꢀLPC interface.............................................................. 2 channels
ꢀSerialized IRQ ................................................................ 3 factors
ꢀClock generating circuit..................................... Built-in 1 circuits
(connect to external ceramic resonator)
The 3882 group is designed for Keyboard Controller for the note
book PC.
FEATURES
<Microcomputer mode>
ꢀPower source voltage................................................ 3.0 to 3.6 V
ꢀPower dissipation
ꢀBasic machine-language instructions ...................................... 71
ꢀMinimum instruction execution time .................................. 0.5 µs
(at 8 MHz oscillation frequency)
In high-speed mode ..........................................................20 mW
(at 8 MHz oscillation frequency, at 3.3 V power source voltage)
ꢀOperating temperature range....................................–20 to 85°C
ꢀMemory size
ROM ............................................................................. 20K bytes
RAM ............................................................................ 1024 bytes
ꢀProgrammable input/output ports ............................................ 72
ꢀSoftware pull-up transistors ....................................................... 8
ꢀInterrupts ................................................. 17 sources, 14 vectors
APPLICATION
Note book PC
PIN CONFIGURATION (TOP VIEW)
40
61
P1
P1
P2
P2
P2
6
7
P3
P3
/SERIRQ
P8 /LCLK
/LRESET
/LFRAME
1
0
39
38
37
36
35
34
33
62
63
64
65
66
67
68
69
70
71
72
73
74
75
0
P8
7
1
6
2
P8
P8
5
P2
3
4
P2
P2
P2
P2
4(LED0)
P8
P8
P8
P8
3
2
1
0
/LAD
/LAD
/LAD
/LAD
3
2
1
0
5
6
7
(LED
(LED
(LED
1)
2)
3)
32
31
30
29
28
M38827G5-XXXHP
M38827G5HP
V
X
X
SS
OUT
IN
VCC
NC
NC
27
26
25
24
23
P67
P66
P65
P64
P63
P4
P4
RESET
CNVSS
P4
P4
P4
0
1
76
77
78
79
80
2
/INT
0
22
21
P6
P6
2
1
3
4
/INT
1
Package type : PLQP0080KB-A (80P6Q-A)
Fig. 1 Pin configuration
Rev.1.01 Nov 14, 2005 page 1 of 60
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Fig. 2 Functional block diagram
Rev.1.01 Nov 14, 2005 page 2 of 60
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PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Functions
Function except a port function
VCC, VSS
Power source
•Apply voltage of 3.3 V ±10 % to Vcc, and 0 V to Vss.
•Connected to VSS.
CNVSS
RESET
CNVSS input
Reset input
•Reset input pin for active “L”.
•Input and output pins for the clock generating circuit.
XIN
Clock input
•Connect a ceramic resonator between the XIN and XOUT pins to set the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
Clock output
XOUT
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level.
P00–P07
P10–P17
I/O port P0
I/O port P1
•CMOS 3-state output structure or N-channel open-drain output structure.
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure or N-channel open-drain output structure.
•8-bit I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
P20–P27
P30–P37
I/O port P2
•CMOS compatible input level.
•CMOS 3-state output structure.
•P24 to P27 (4 bits) are enabled to output large current for LED drive.
•8-bit I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
I/O port P3
•CMOS compatible input level.
•Key-on wake-up input pins
•CMOS 3-state output structure.
•These pins function as key-on wake-up .
•These pins are enabled to control pull-up.
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Table 2 Pin description (2)
Functions
Pin
Name
Function except a port function
•8-bit I/O port with the same function as port P0
<Input level>
P40
P41
CMOS compatible input level
<Output level>
P42/INT0
P43/INT1
•Interrupt input pins
P40, P41 : CMOS 3-state output structure
I/O port P4
P44
P45
P46
P42-P47 : CMOS 3-state output structure or N-
channel open-drain output structure
•Each pin level of P42 to P46 can be read even in
output port mode.
P47
/CLKRUN
•Serialized IRQ function pin
P50/INT5
•8-bit I/O port with the same function as port P0
•CMOS compatible input level
P51/INT20
P52/INT30
P53/INT40
P54/CNTR0
P55/CNTR1
•Interrupt input pins
•CMOS 3-state output structure
I/O port P5
•Timer X, timer Y function pins
P56
P57
•8-bit I/O port with the same function as port P0
•CMOS compatible input level.
P60–P67
I/O port P6
•CMOS 3-state output structure.
•8-bit CMOS I/O port with the same function as port P0
P70
P71
P72
<Input level>
P70–P75 : CMOS compatible input level or
TTL compatible input level
P73/INT21
P74/INT31
P75/INT41
P76, P77 : CMOS compatible input level
•Interrupt input pins
I/O port P7
<Output structure>
N-channel open-drain output structure
P76
P77
•Each pin level of P70 to P75 can be read even in
output port mode.
•8-bit CMOS I/O port with the same function as port
P0
P80/LAD0
P81/LAD1
P82/LAD2
P83/LAD3
P84/LFRAME
P85/LRESET
P86/LCLK
•CMOS compatible input level.
•CMOS 3-state output structure.
•LPC interface function pins
•Serialized IRQ function pin
I/O port P8
P87/SERIRQ
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PART NUMBERING
Product name
M3882
7
G
5
-XXX HP
Package type
HP : PLQP0080KB-A
ROM number
Omitted in in shipped in blank version.
ROM size
1: 4096 bytes
2: 8192 bytes
3: 12288 bytes
4: 16384 bytes
5: 20480 bytes
6: 24576 bytes
7: 28672 bytes
8: 32768 bytes
9: 36864 bytes
A: 40960 bytes
B: 45056 bytes
C: 49152 bytes
D: 53248 bytes
E: 57344 bytes
F: 61440 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved
areas ; user cannot use those bytes.
However, they can be programmed or erased in the flash
memory version, so that the users can use them.
Memory type
M : Mask ROM version
F : Flash memory version
G : QzROM version
RAM size
0: 192 bytes
1: 256 bytes
2: 384 bytes
3: 512 bytes
4: 640 bytes
5: 768 bytes
6: 896 bytes
7: 1024 bytes
8: 1536 bytes
9: 2048 bytes
Fig. 3 Part numbering
Rev.1.01 Nov 14, 2005 page 5 of 60
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GROUP EXPANSION
Renesas plans to expand the 3882 group as follows.
Packages
PLQP0080KB-A....................... 0.5 mm-pitch plastic molded LQFP
Memory Type
Support for QzROM version.
Memory Size
ROM size ........................................................................ 20 K bytes
RAM size ....................................................................... 1024 bytes
Memory Expansion
ROM size (bytes)
ROM
external
60K
56K
48K
40K
32K
24K
M38827G5
16K
8K
256
512
768
1024
1280
1536
1792
2048
RAM size (bytes)
Fig. 4 Memory expansion plan
Table 3 Products plan list
As of Nov 2005
ROM size (bytes)
Product name
RAM size (bytes)
1024
Package
80P6Q-A
Remarks
ROM size for User in (
)
M38827G5-XXXHP
M38827G5HP
QzROM version (Programmed shipment) (Note 1)
QzROM version (blank) (Note 2)
20480(20350)
Notes 1: This means a shipment of which User ROM has been programmed.
2: The user ROM area of a blank product is blank.
Rev.1.01 Nov 14, 2005 page 6 of 60
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FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3882 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 7.
Store registers other than those described in Figure 7 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b0
b0
b0
b0
b7
X
Index register X
Index register Y
b7
Y
b7
S
Stack pointer
b15
b7
PC
H
PC
L
Program counter
b7
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
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On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PC
(S) (S) – 1
M (S) (PC
(S) (S) – 1
H)
Push return address
on stack
M (S) (PC
(S) (S) – 1
M (S) (PC
H)
L)
Push return address
on stack
Push contents of processor
status register on stack
L)
M (S) (PS)
(S) (S)– 1
(S) (S) – 1
Subroutine
Interrupt
Service Routine
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PC
(S) (S) + 1
(PC M (S)
L)
M (S)
(PS)
(S) (S) + 1
(PC M (S)
(S) (S) + 1
(PC M (S)
M (S)
H)
L
)
POP return
address from
stack
H)
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
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•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
Table 5 Set and clear instructions of each bit of processor status register
N flag
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
–
–
Set instruction
CLI
CLV
Clear instruction
Rev.1.01 Nov 14, 2005 page 9 of 60
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[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
0
0 1
(CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0
1
0
1
: Single-chip mode
: Not available
: Not available
: Not available
Stack page selection bit
0
1
: 0 page
: 1 page
Fix this bit to “1”.
Fix this bit to “0”.
Main clock division ratio selection bits
b7 b6
0
0
1
1
0
1
0
1
: φ = f(XIN)/2 (high-speed mode)
: φ = f(XIN)/8 (middle-speed mode)
: Not available
: Not available
Fig. 7 Structure of CPU mode register
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MEMORY
Special Function Register (SFR) Area
The special function register area contains the control registers
such as I/O ports, timers, serial I/O, etc.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM Code Protect Address
“0016 ” is written into ROM code protect address (other than the
user ROM area) when selecting the protect bit write by using a se-
rial programmer or selecting protect enabled for writing shipment
by Renesas Technology corp..When “0016 ” is set to the ROM
code protect address,the protect function is enabled,so that read-
ing or writing from/to QzROM is disabled by a serial programmer.
As for the QzROM product in blank, the ROM code is protected by
selecting the protect bit write at ROM writing with a serial pro-
grammer.
ROM
ROM is used for program code and data table storage.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing code and the rest is user area.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
As for the QzROM product shipped after writing,“0016 ” (protect
enabled) or “FF16 ” (protect disabled) is written into the ROM code
protect address when Renesas Technology corp. performs writing.
The writing of “0016" or “FF16 ” can be selected as ROM option
setup (“MASK option ” written in the mask file converter) when or-
dering.
Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
000016
SFR area
RAM area
Zero page
004016
RAM size
(bytes)
Address
XXXX16
010016
RAM
1024
043F16
XXXX16
Not used
0FF016
SFR area
0FFF16
YYYY16
Reserved ROM area
(Note) (128 bytes)
ZZZZ16
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
ROM
20480
B00016
B08016
FF0016
FFDC16
Special page
Interrupt vector area
FFFE16
FFFF16
Reserved ROM area
(Note)
Notes: This area is reserved in the QzROM version.
Fig. 8 Memory map diagram
Rev.1.01 Nov 14, 2005 page 11 of 60
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Port P0 (P0)
002016
000016
Prescaler 12 (PRE12)
Timer 1 (T1)
Port P0 direction register (P0D)
Port P1 (P1)
002116
002216
002316
002416
000116
000216
000316
000416
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P2 direction register (P2D)
Port P3 (P3)
002516
002616
002716
000516
000616
000716
000816
Prescaler Y (PREY)
Port P3 direction register (P3D)
Port P4 (P4)
Timer Y (TY)
002816 Data bas buffer register 0 (DBB0)
Port P4 direction register (P4D)
Port P5 (P5)
002916 Data bas buffer status register 0 (DBBSTS0)
000916
000A16
000B16
000C16
LPC control register (LPCCON)
002A16
Port P5 direction register (P5D)
Port P6 (P6)
002B16 Data bas buffer register 1 (DBB1)
002C16 Data bas buffer status register 1 (DBBSTS1)
Port P6 direction register (P6D)
Port P7 (P7)
002D16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
002E16 Port control register 1 (PCTL1)
002F16 Port control register 2 (PCTL2)
003016
Port P7 direction register (P7D)
Port P8 (P8)/Port P4 input register (P4I)
003116
003216
003316
003416
Port P8 direction register (P8D)/Port P7 input register (P7I)
003516
003616
003716
003816
003916 Interrupt source selection register (INTSEL)
Interrupt edge selection register (INTEDGE)
003A16
CPU mode register (CPUM)
003B16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
003C16
003D16
003E16
003F16
001C16
001D16
001E16
001F16
Serialized IRQ control register (SERCON)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Watchdog timer control register (WDTCON)
Serialized IRQ request register (SERIRQ)
LPC0 address register L (LPC0ADL)
0FF016
0FF116 LPC0 address register H (LPC0ADH)
0FF216 LPC1 address register L (LPC1ADL)
0FF316 LPC1 address register H (LPC1ADH)
0FF816 Port P5 input register (P5I)
0FF916 Port control register 3 (PCTL3)
Fig. 9 Memory map of special function register (SFR)
Rev.1.01 Nov 14, 2005 page 12 of 60
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I/O PORTS
comes floating. In input port mode, writing the port register
changes only the data of the port latch and the pin remains high
impedance state.
All I/O pins are programmable as input or output. All I/O ports
have direction registers which specify the data direction of each
pin like input/output. One bit in a direction register corresponds to
one pin. Each pin can be set to be input or output port.
Writing “0” to the bit corresponding to the pin, that pin becomes an
input mode. Writing “1” to the bit, that pin becomes an output
mode.
When the P8 function selection bit of the port control register 2 is
set to “1”, reading from address 001016 reads the port P4 register,
and reading from address 001116 reads the port P7 register.
Especially, the input level of P42 to P46 pins and P70 to P75 pins
can be read regardless of the data of the direction registers in this
case.
When the data is read from the bit of the port register correspond-
ing to the pin which is set to output, the value shows the port latch
data, not the input level of the pin. When a pin set to input, the pin
Table 6 I/O port function (1)
Pin
Name
Input/Output
Related SFRs
Ref.No.
(1)
I/O Structure
Non-Port Function
CMOS compatible
input level
CMOS 3-state output
or N-channel open-
drain output
P00-P07
Port P0
Port control register 1
P10-P17
P20-P27
Port P1
Port P2
(2)
(3)
CMOS compatible
input level
CMOS 3-state output
Port control register 1
Key-on wake up input
External interrupt input
P30-P37
Port P3
P40
P41
(4)
(5)
Input/output,
individual bits
Interrupt edge selection
register
Port control register 2
P42/INT0
P43/INT1
CMOS compatible
input level
CMOS 3-state output
or N-channel open-
drain output
Port P4
P44
P45
P46
(6)
(7)
Port control register 2
P47/CLKRUN
Serialized IRQ function Serialized IRQ control
output register
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Table 7 I/O port function (2)
Name
Related SFRs
Pin
Input/Output
I/O Format
Non-Port Function
Ref.No.
(8)
P50/INT5
P51/INT20
CMOS compatible
input level
CMOS 3-state output
or N-channel
Interrupt edge selection
register
Port control register 2
Port control register 3
External interrupt input
P52/INT30
P53/INT40
opendrain output
Port P5
P54/CNTR0
P55/CNTR1
Timer X, timer Y func-
tion I/O
(9)
Timer XY mode register
CMOS compatible
input level
CMOS 3-state output
P56
P57
(10)
P60–
P67
Port P6
(10)
(11)
P70
P71
P72
Port control register 2
CMOS compatible
input level or
TTL input level
Input/output,
individual bits
P73/INT21
P74/INT31
P75/INT41
Interrupt edge selection
register
Port control register 2
Pure N-channel
open-drain output
(12)
(13)
External interrupt input
Port P7
CMOS compatible
input level
P76
P77
Pure N-channel
open-drain output
P80/LAD0
P81/LAD1
P82/LAD2
P83/LAD3
(14)
Data bus buffer control
register
Port control register 2
LPC interface function
I/O
P84/
LFRAME
CMOS compatible
input level
CMOS 3-state output
Port P8
P85/
LRESET
(15)
(16)
P86/LCLK
P87/
SERIRQ
Serialized IRQ function
I/O
Notes1: For details usage of double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level of each pin should be either 0 V or VCC in STP mode.
When an input level is at an intermediate voltage level, the ICC current will become large because of the input buffer gate.
Rev.1.01 Nov 14, 2005 page 14 of 60
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3882 Group
(2) Port P2
0
–P2
7
(1) Ports P0, P1
P00
P04
P10
P14
–P0
–P0
–P1
–P1
3
7
3
7
,
,
,
output structure
selection bits
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
(3) Ports P3
0
–P3
7
(4) Port P40, P4
1
P3
P3
0
4
–P3
–P3
3
,
7
pull-up control bit
Direction
register
Data bus
Port latch
Direction
register
Data bus
Port latch
Key-on wake-up input
(5) Ports P42, P43
P4 output structure selection bit
Direction
register
Data bus
Port latch
Interrupt input
ꢀ1
ꢀ1. Reading the port P8 register (address 001016) is switched to port P4 pin input level by the P8 function selection bit of the port control
register 2 (PCTL2).
Fig. 10 Port block diagram (1)
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(7) Port P4
7
(6) Ports P44 to P46
P4 output structure selection bit
Serialized IRQ enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
ꢀ1
CLKRUN output
(9) Ports P54, P55
(8) Ports P50 to P5
3
P5i open drain selection bit
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
Pulse output mode
Timer output
Interrupt input
CNTR0, CNTR1 interrupt input
(11) Ports P70 to P72
(10) Ports P56, P57, P6
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
ꢀ2
ꢀ1. Reading the port P8 register (address 001016) is switched to port P4 pin input level by the P8 function selection bit of the port control
register 2 (PCTL2).
ꢀ2. Reading the port P8 direction register is switched to port P7 pin input level by the P8 function selection bit of the port control register 2
(PCTL2).
Fig. 11 Port block diagram (2)
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(13) Port P76, P7
7
(12) Ports P73 to P75
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
ꢀ2
Interrupt input
ꢀ2
(14) Ports P80 to P83
(15) Ports P84 to P86
LPC enable bit
LPC enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
LRESET
LCLK
LAD [3 : 0]
LFRAME
(16) Port P8
7
SIRQ enable bit
Direction
register
Data bus
Port latch
IRQSER
ꢀ2. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port
control register 2 (PCTL2).
Reading the port P8 direction register is switched to port P7 pin input level by the P8 function selection bit of the port control register 2
(PCTL2).
Fig. 12 Port block diagram (3)
Rev.1.01 Nov 14, 2005 page 17 of 60
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b0
b7
Port control register 1
(PCTL1: address 002E16)
P00–P03 output structure selection bit
0: CMOS
1: N-channel open-drain
P04–P07 output structure selection bit
0: CMOS
1: N-channel open-drain
P10–P13 output structure selection bit
0: CMOS
1: N-channel open-drain
P14–P17 output structure selection bit
0: CMOS
1: N-channel open-drain
P30–P33 pull-up control bit
0: No pull-up
1: Pull-up
P34–P37 pull-up control bit
0: No pull-up
1: Pull-up
Not used (returns “0” when read)
b7
b0
Port control register 2
(PCTL2: address 002F16)
P45 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
P7 input level selection bit (P70-P75)
0: CMOS input level
1: TTL input level
P4 output structure selection bit (P42, P43, P44, P46)
0: CMOS
1: N-channel open-drain
P8 function selection bit
0: Port P8/Port P8 direction register
1: Port P4 input register/Port P7 input register
INT2, INT3, INT4 interrupt switch bit
0: INT20, INT30, INT40 interrupt
1: INT21, INT31, INT41 interrupt
Not used (returns “0” when read)
Oscillation stabilizing time set after STP instruction released bit
0: Automatic set “0116” to timer 1 and “FF16” to prescaler 12
1: No automatic set
Not used (returns “0” when read)
Fig. 13 Structure of port I/O related registers (1)
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b0
b7
Port P5 input register
(P5I: address 0FF816
)
P5
P5
P5
P5
0
1
2
3
input level bit
input level bit
input level bit
input level bit
These bits directly show the pin input levels.
0: “L” level input
1: “H” level input
Not used (returns “0” when read)
b0
b7
Port control register 3
(PCTL3: address 0FF916
)
P5
P5
P5
P5
0
1
2
3
open drain selection bit
open drain selection bit
open drain selection bit
open drain selection bit
0: CMOS
1: N-channel open drain
Not used (returns “0” when read)
Fig. 14 Structure of port I/O related registers (2)
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INTERRUPTS
Interrupt Source Selection
Any of the following interrupt sources can be selected by the inter-
rupt source selection register (INTSEL).
1. INT0 or Input buffer full
Interrupts occur by 14 sources among 17 sources: ten external,
six internal, and one software.
Interrupt Control
2. INT1 or Output buffer empty
3. Timer 2 or INT5
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt caused by the BRK instruction. An interrupt occurs when
both the corresponding interrupt request bit and interrupt enable
bit are “1” and the interrupt disable flag is “0”.
4. CNTR0 or INT0
5. CNTR1 or INT1
External Interrupt Pin Selection
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The external interrupt sources of INT2, INT3, and INT4 can be se-
lected from either input pin from INT20, INT30, INT40 or input pin
from INT21, INT31, INT41 by the INT2, INT3, INT4 interrupt switch
bit (bit 4 of PCTL2).
The BRK instruction interrupt cannot be disabled with any flag or
bit. The I (interrupt disable) flag disables all interrupts except the
BRK instruction interrupt.
ꢀꢀNotes
When several interrupts occur at the same time, the interrupts are
serviced according to the priority.
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A16); Timer XY mode register (address
002316)
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection register (address
003916)
3. The interrupt jump destination address is read from the vector
table and stored into the program counter.
•When setting input pin of external interrupts INT2, INT3 and INT4
Related register: INT2, INT3, INT4 interrupt switch bit of Port con-
trol register 2 (bit 4 of address 002F16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
(1) Set the corresponding interrupt enable bit to “0” (disabled).
(2) Set the active edge selection bit or the interrupt source selec
tion bit to “1”.
(3) Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Rev.1.01 Nov 14, 2005 page 20 of 60
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Table 8 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Priority
1
Interrupt Source
Reset (Note 2)
INT0
Remarks
Non-maskable
Low
High
FFFC16
At reset
FFFD16
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
2
3
FFFB16
FFFA16
FFF816
Input buffer full
(IBF)
At input data bus buffer writing
At detection of either rising or
falling edge of INT1 input
External interrupt
(active edge selectable)
INT1
FFF916
FFF716
At output data bus buffer read-
ing
Output buffer
empty (OBE)
4
5
6
7
FFF616
FFF216
At falling edge of LRESET input
At timer X underflow
LRESET
External interrupt
FFF316
FFF116
FFEF16
Timer X
Timer Y
Timer 1
Timer 2
At timer Y underflow
FFF016
FFEE16
At timer 1 underflow
At timer 2 underflow
STP release timer underflow
8
FFED16
FFEC16
FFEA16
At detection of either rising or
falling edge of INT5 input
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
INT5
At detection of either rising or
falling edge of CNTR0 input
CNTR0
9
FFEB16
External interrupt
(active edge selectable)
INT0
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
CNTR1
INT1
10
FFE816
FFE916
At detection of either rising or
falling edge of INT1 input
External interrupt (falling valid)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT2 input
INT2
11
12
FFE416
FFE216
FFE516
FFE316
FFE116
FFDF16
At detection of either rising or
falling edge of INT3 input
INT3
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT4 input
INT4
13
14
FFE016
FFDE16
FFDC16
At falling of port P3 (at input)
input logical level AND
External interrupt (falling valid)
Key-on wake-up
15
BRK instruction
FFDD16
At BRK instruction execution
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset functions in the same way as an interrupt with the highest priority.
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Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 15 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
0
active edge selection bit
active edge selection bit
INT1
Not used (returns “0” when read)
INT
INT
INT
INT
2
3
4
5
active edge selection bit
active edge selection bit
active edge selection bit
active edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
b7
b0
b7
b0
Interrupt request register 2
Interrupt request register 1
(IREQ2 : address 003D16
)
(IREQ1 : address 003C16
)
INT
bit
INT
0
/input buffer full interrupt request
CNTR
0
/INT
/INT
0
interrupt request bit
CNTR
1
1 interrupt request bit
1
/output buffer empty interrupt
Not used (returns “0” when read)
request bit
LRESET request bit
INT
INT
INT
2
3
4
interrupt request bit
interrupt request bit
interrupt request bit
Not used (returns “0” when read)
key-on wake-up interrupt request bit
Not used (returns “0” when read)
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
Timer 2/INT5 interrupt request bit
b7
b0
b7
0
b0
Interrupt control register 2
Interrupt control register 1
(ICON1 : address 003E16
(ICON2 : address 003F16
)
)
CNTR
0
/INT
/INT
0
interrupt enable bit
interrupt enable bit
INT
INT
bit
0
/input buffer full interrupt enable bit
/output buffer empty interrupt enable
CNTR
1
1
1
Not used (returns “0” when read)
INT
INT
INT
2
3
4
interrupt enable bit
interrupt enable bit
interrupt enable bit
LRESET enable bit
Not used (returns “0” when read)
key-on wake-up interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
Timer 2/INT5 interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers (1)
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b7
b0
Interrupt source selection register
(INTSEL: address 003916
)
INT0/input buffer full interrupt source selection bit
0 : INT interrupt
0
1 : Input buffer full interrupt
INT
0 : INT
1
/output buffer empty interrupt source selection bit
1
interrupt
1 : Outpud buffer empty interrupt
LRESET interrupt source selection bit
0 : Not used
1 : LRESET interrupt
Not used (returns “0” when read)
(Do not write “1” to this bit)
Timer 2/INT
0 : Timer 2 interrupt
1 : INT interrupt
5 interrupt source selection bit
5
CNTR
0 : CNTR
1 : INT interrupt
0/INT
0
interrupt source selection bit
0
interrupt
0
CNTR
0 : CNTR
1 : INT interrupt
1/INT
1
interrupt source selection bit
1
interrupt
1
Key-on wake-up interrupt source selection bit
0 : Not used
1 : Key-on wake-up interrupt
Fig. 17 Structure of interrupt-related registers (2)
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Key Input Interrupt (Key-on Wake Up)
goes from “1” to “0”. An example of using a key input interrupt is
shown in Figure 18, where an interrupt request is generated by
pressing one of the keys consisted as an active-low key matrix
which inputs to ports P30–P33.
A Key input interrupt request is generated by applying “L” level to
any pin of port P3 that have been set to input mode. In other
words, it is generated when the logical AND of all port P3 input
Port PXx
“L” level output
Port control register 1
Bit 5 = “0”
Key input interrupt request
Port P3
7
direction register = “1”
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
Port P3
latch
7
6
5
4
P3
7
output
output
output
Port P3
direction register = “1”
6
Port P3
latch
P3
6
Port P3
direction register = “1”
5
Port P3
latch
P3
5
Port P3
direction register = “1”
4
Port P3
latch
P34
output
Port control register 1
Port P3
direction register = “0”
3
Bit 4 = “1”
ꢀ
ꢀ
ꢀꢀ
Port P3 input circuit
Port P3
3
latch
P3
3
input
input
input
input
Port P3
direction register = “0”
2
ꢀꢀ
ꢀꢀ
ꢀꢀ
Port P3
latch
2
P3
2
Port P3
direction register = “0”
1
ꢀ
Port P3
latch
1
P3
1
Port P3
direction register = “0”
0
ꢀ
Port P3
latch
0
P30
ꢀ P-channel transistor for pull-up
ꢀꢀ CMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P3 block diagram
Rev.1.01 Nov 14, 2005 page 24 of 60
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3882 Group
TIMERS
Timer 1 and Timer 2
The 3882 group has four timers: timer X, timer Y, timer 1, and
The count source of prescaler 12 is the oscillation frequency di-
vided by 16. The output of prescaler 12 is counted by timer 1 and
timer 2, and a timer underflow sets the interrupt request bit.
timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down structure. When the timer reaches
“0016”, an underflow occurs at the next count pulse and the corre-
sponding timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
responding to that timer is set to “1”.
Timer X and Timer Y
Timer X and Timer Y can each select one of four operating modes
by setting the timer XY mode register.
(1) Timer Mode
The timer counts f(XIN)/16.
(2) Pulse Output Mode
Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of
the timer reach “0016”, the signal output from the CNTR0 (or
CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge se-
lection bit is “0”, output begins at “ H”.
b0
b7
Timer XY mode register
(TM : address 002316
)
Timer X operating mode bit
b1b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P54 ( or port P55) direction register to out-
put mode.
CNTR0 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
Timer X count stop bit
0: Count start
1: Count stop
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
Timer Y operating mode bit
b5b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
(4) Pulse Width Measurement Mode
CNTR1 active edge selection bit
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts f(XIN)/16 while the CNTR0 (or CNTR1) pin is at “H”. If the
CNTR0 (or CNTR1) active edge selection bit is “1”, the timer
counts while the CNTR0 (or CNTR1) pin is at “L”.
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer overflows.
1: Count stop
Fig. 19 Structure of timer XY mode register
The count source for timer Y in the timer mode or the pulse output
mode can be selected from f(XIN)/16 by the timer Y count source
selection bit of the port control register 2 (bit 5 of PCTL2).
Rev.1.01 Nov 14, 2005 page 25 of 60
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Data bus
Divider
1/16
Oscillator
f(XIN
Prescaler X latch (8)
Timer X latch
(8)
)
Pulse width
measurement
mode
Timer mode
Pulse output mode
Prescaler X (8)
To timer X interrupt
request bit
Timer X (8)
CNTR
0
active
Event
counter
mode
Timer X count stop bit
edge selection
P54/CNTR0
“0”
bit
To CNTR
0 interrupt
request bit
“1”
CNTR0 active
“1”
“0”
edge selection
bit
Q
Q
T
Toggle flip-flop
R
Timer X latch write pulse
Pulse output mode
Port P5
latch
4
Port P5
direction register
4
Pulse output mode
Data bus
Timer Y count source
selection bit
“0”
Oscillator
f(XIN
Divider
1/16
Prescaler Y latch (8)
Timer Y latch (8)
Timer Y (8)
)
Pulse width
measure-
ment mode
Timer mode
Pulse output mode
To timer Y interrupt
request bit
Prescaler Y (8)
CNTR
edge selection
1 active
Event
counter
mode
Timer Y count stop bit
P55/CNTR1
“0”
“1”
bit
To CNTR
1 interrupt
request bit
CNTR1 active
“1”
“0”
edge selection
bit
Q
Q
T
Toggle flip-flop
R
Port P55
latch
Timer Y latch write pulse
Pulse output mode
Port P5
direction register
Pulse output mode
5
Data bus
Prescaler 12 latch (8)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Oscillator
f(XIN
Divider
1/16
)
To timer 2 interrupt
request bit
To timer 1 interrupt
request bit
Fig. 20 Block diagram of timer X, timer Y, timer 1, and timer 2
Rev.1.01 Nov 14, 2005 page 26 of 60
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WATCHDOG TIMER
Bit 6 of Watchdog Timer Control Register
When bit 6 of the watchdog timer control register is “0”, the MCU
enters the stop mode by execution of STP instruction. Just after
releasing the stop mode, the watchdog timer restarts counting
(Note). When executing the WIT instruction, the watchdog timer
does not stop.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Initial Value of Watchdog Timer
When bit 6 is “1”, execution of STP instruction causes an internal
reset. When this bit is set to “1” once, it cannot be rewritten to “0”
by program. Bit 6 is “0” at reset.
At reset or writing to the watchdog timer control register (address
001E16), each of watchdog timer H and L is set to “FF16”. Any in-
struction which generates a write signal such as the instructions of
STA, LDM, CLB and others can be used to write. The data of bits
6 and 7 are only valid when writing to the watchdog timer control
register. Each of watchdog timer is set to “FF16” regardless of the
written data of bits 0 to 5.
The necessary time after writing to the watchdog timer control reg-
ister to an underflow of the watchdog timer H is shown as follows.
When bit 7 of the watchdog timer control register is “0”:
131.072 ms at XIN = 8 MHz frequency.
When bit 7 of the watchdog timer control register is “1”:
512 µs at XIN = 8 MHz frequency.
Operation of Watchdog Timer
The watchdog timer stops at reset and starts to count down by
writing to the watchdog timer control register. An internal reset oc-
curs at an underflow of the watchdog timer H. The reset is
released after waiting for a reset release time and the program is
processed from the reset vector address. Accordingly, program-
ming is usually performed so that writing to the watchdog timer
control register may be started before an underflow of the watch-
dog timer H. If writing to the watchdog timer control register is not
performed once, the watchdog timer does not function.
Note: The watchdog timer continues to count for waiting for a stop mode
release time. Do not generate an underflow of the watchdog timer H
during that time.
“FF16” is set when
watchdog timer
control register is
written to.
Data bus
“FF16” is set when
watchdog timer
control register is
written to.
“0”
“1”
Watchdog timer L (8)
Main clock division
Watchdog timer H (8)
1/16
ratio selection bits
(Note)
“00”
“01”
Watchdog timer H count
source selection bit
X
IN
STP instruction function select bit
STP instruction
Reset
circuit
Internal reset
RESET
Note: Any one of high-speed or middle-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 21 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 001E16
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction function select bit
0: Entering Stop mode by excution of STP instruction
1: Internal reset by excution of STP instruction
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16
Fig. 22 Structure of Watchdog timer control register
Rev.1.01 Nov 14, 2005 page 27 of 60
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LPC INTERFACE
LPC interface function is base on Low Pin Count (LPC) Interface
Specification, Revision 1.0. The 3882 supports only I/O read cycle
and
I/O write cycle. There are two channels of bus buffers to the host.
The functions of Input Data Bus Buffer, Output Data Bus Buffer
and Data Bus Buffer Status Register are the same as that of the
8042, 3880 group, 3881 group,3886 group and 3885 group. It can
be written in or read out from the host controller through LPC in-
terface. LPC interface function block diagram is shown in Figure
23.
Functional input or output pins of LPC interface are shared with
Port 8 (P80–P86). Setting the LPC interface enable bit (bit3 of
LPCCON) to “1” enables LPC interface. Enabling channel i (i = 0,
1) of the data bus buffer is controlled by the data bus buffer i (i =
0, 1) enable bits (bit 4 or bit 5 of LPCCON).
The slave addresses of the data bus buffer channel i (i = 0, 1) are
definable by setting LPCi (i = 0, 1) address register H/L
(LPC0ADL, LPC0ADH, LPC1ADL, LPC1ADH). The bit 2 value of
LPCi address register L is not decoded. This bit returns “0” when
the internal CPU read. The bit 2 of slave address is latched to
XA2i flag when the host controller writes the data.
The input buffer full (IBF) interrupt occurs when the host controller
writes the data. The output buffer empty (OBE) interrupt is gener-
ated when the host controller reads out the data. The 3882
merges two input buffer full (IBF) interrupt requests and two output
buffer empty (OBE) interrupt requests as shown in Figure 24.
Table 9 Function explanation of the control pin in LPC interface
Input/
Output
Function
Pin name
P8
P8
P8
P8
0
1
2
3
/LAD
/LAD
/LAD
/LAD
0
1
2
3
I/O
I/O
I/O
I/O
I
These pins communicate address, control and data
information between the host and the data bus buffer of
the 3882.
Input the signal to indicate the start of new cycle and
termination of abnormal communication cycles.
P8
4
/LFRAME
/LRESET
/LCLK
Input the signal to reset the LPC interface function.
P8
5
I
Input the LPC synchronous clock signal.
P8
6
I
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P8
4
/
LFRAME
LRESET
P8 LCLK
P8
5
/
6/
P8
0
/LAD0
P8
1/LAD1
Input Control Circuit
P8
2/LAD2
Input Data
Input Data
Bus Buffer [7:4]
Bus Buffer [3:0]
Output Data
Output Data
Bus Buffer [7:4]
Bus Buffer [3:0]
P8
3/LAD3
Data bus buffer status register
4i XA2i
U7i
U6i
U5i
U
U
2i
IBFi OBFi
Output Control Circuit
Interrupt signal
IBF, OBE
Interrupt Generate
Circuit
0
b6
b3
b2
b1
b0
b5
b4
LPC control register (LPCCON)
Fig. 23 Block diagram of LPC interface function (1ch)
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One-shot pulse
Input buffer
Rising edge
generating circuit
full flag 0 IBF
0
1
detection circuit
Input buffer full interrupt
request signal IBF
One-shot pulse
generating circuit
Rising edge
detection circuit
Input buffer
full flag 1 IBF
Output buffer
One-shot pulse
Rising edge
full flag 0
OBF
0
generating circuit
detection circuit
OBE
0
Output buffer empty interrupt
request signal OBE
Output buffer
full flag 1
One-shot pulse
generating circuit
Rising edge
detection circuit
OBF
1
OBE
1
IBF
0
IBF
IBF
1
Interrupt request is set at this rising edge
OBF
0
(OBE0)
OBF
1
(OBE1)
OBE
Interrupt request is set at this rising edge
Fig. 24 Interrupt request circuit of data bus buffer
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[LPC Control Register (LPCCON)] 002A16
• SYNC output select bit (SYNCSEL)
“00”: OK
[Output Data Bus Buffer i (i = 0, 1)
(DBBOUT0, DBBOUT1)] 002816, 002B16
Writing data to data bus buffer registers (DBB0 , DBB1) address
from the internal CPU means writing to DBBOUTi (i = 0, 1). The
data of DBBOUTi (i = 1, 0) is read out from the host controller
when bit 2 of slave address (A2) is “0”.
“01”: LONG & OK
“10”: Err
“11”: LONG & Err
• LPC interface software reset bit (LPCSR)
“0”: Reset release (automatic)
“1”: Reset
[LPCi address register H/L
(LPC0ADL, LPC1ADL / LPC0ADH, LPC1ADH)]
0FF016 to 0FF316
• LPC interface enable bit (LPCBEN)
“0”: P80–P86 works as port
“1”: P80–P86 works as LPC interface
• Data bus buffer 0 enable bit (DBBEN0)
“0”: Data bus buffer 0 disable
“1”: Data bus buffer 0 enable
• Data bus buffer 1 enable bit (DBBEN1)
“0”: Data bus buffer 1 disable
“1”: Data bus buffer 1 enable
The slave addresses of data bus buffer channel i(i=0,1) are defin-
able by setting LPCi address registers H/L (LPC0ADL, LPC0ADH,
LPC1ADL, LPC1ADH ). These registers can be set and cleared
any time. When the internal CPU reads LPCi address register L,
the bit 2 (A2) is fixed to “0”. The bit 2 of slave address (A2) is
latched to XA2i flag when the host controller writes the data. The
slave addresses, set in these registers, is used for comparing with
the addresses from the host controller.
Bits 0 and 1 of the LPC control register (LPCCON) specify the
SYNC code output.
Bit 2 of the LPC control register (LPCCON) enables the LPC inter-
face to enter the reset state by software. When LPCSR is set to
“1”, LPC interface is initialized in the same manner as the external
“L” input to LRESET pin (See Figure 30). Writing “0” to LPCSR the
reset state will be released after 1.5 cycle of φ and this bit is
cleared to “0”.
[Data Bus Buffer Status Register i (i = 0, 1)
(DBBSTS0, DBBSTS1)] 002916, 002C16
Bits 0, 1 and 3 are read-only bits and indicate the status of the
data bus buffer. Bits 2, 4, 5, 6 and 7 are user definable flags which
can be read and written by software. The data bus buffer status
register can be read out by the host controller when bit 2 of the
slave address (A2) is “1”.
•Bit 0: Output buffer full flag i (OBFi)
This bit is set to “1” when a data is written into the output data bus
buffer i and cleared to “0” when the host controller reads out the
data from the output data bus buffer i.
•Bit 1: Input buffer full flag i (IBFi)
This bit is set to “1” when a data is written into the input data bus
buffer i by the host controller, and cleared to “0” when the data is
read out from the input data bus buffer i by the internal CPU.
•Bit 3: XA2 flag (XA2i)
The bit 2 of slave address is latched while a data is written into the
input data bus buffer i.
[Input Data Bus Buffer i(i=0,1)
(DBBIN0, DBBIN1)] 002816, 002B16
In I/O write cycle from the host controller, the data byte of the data
phase is latched to DBBINi (i=0,1). The data of DBBINi can be
read out form the data bus buffer registers (DBB0, DBB1) address
in SFR area.
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LPC control register
b7
b6 b5 b4 b3 b2 b1 b0
Symbol
LPCCON
Address
002A16
When reset
00000000
2
R
W
Bit symbol
Bit name
Function
SYNCSEL
SYNC output select bit
00:OK
01:Long & OK
10:Err
11:Long & Err
0 : Reset release(automatic)
1 : Reset
LPC interface software reset bit
LPC interface enable bit
LPCSR
LPCEN
0 : P80 to P86 as port
1 : LPC interface enable
0 : Data bus buffer 0 disable
1 : Data bus buffer 0 enable
Data bus buffer 0 enable bit
Data bus buffer 1 enable bit
DBBEN0
DBBEN1
0 : Data bus buffer 1 disable
1 : Data bus buffer 1 enable
Cannot write to this bit.
Returns "0"when read.
Fig. 25 LPC control register
Data bus buffer status register i (i = 0, 1)
b6 b5 b4 b3 b2 b1 b0
b7
Symbol
DBBSTS0
DBBSTS1
Address
002916
002C16
When reset
00000000
00000000
2
2
Bit symbol
Bit name
Function
R W
0 : Buffer empty
1 : Buffer full
OBFi
Output buffer full flag
Input buffer full flag
User definable flag
XA2i flag
0 : Buffer empty
1 : Buffer full
IBFi
U2i
This flag can be freely defined
by user.
This flag indicates the A2
status when IBFi flag is set.
XA2i
This flag can be freely defined
by user.
U4i
U5i
U6i
U7i
User definable flag
Fig. 26 Data bus buffer control register
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LPC
i
address register L (
i
=0,1) (Note2)
Symbol
Address
When reset
b7 b6 b5 b4 b3 b2 b1 b0
LPC0ADL
LPC1ADL
0FF0
0FF2
2
00000000
00000000
2
2
2
R
W
Bit symbol
LPCSAD0
Bit name
Slave address bit 0
LPCSAD1
LPCSAD2
LPCSAD3
LPCSAD4
LPCSAD5
LPCSAD6
LPCSAD7
Slave address bit 1
Slave address bit 2 (Note 1)
Slave address bit 3
Slave address bit 4
Slave address bit 5
Slave address bit 6
Slave address bit 7
Notes 1: Always returnes “0” when read , even if writing “1” to this bit.
2: Do not set the same 16-bit slave address to both channel 0 and channel 1.
LPCi address register H (i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
LPC0ADH
LPC1ADH
0FF1
0FF3
2
00000000
00000000
2
2
2
R
W
Bit symbol
LPCSAD8
Bit name
Slave address bit 8
Slave address bit 9
Slave address bit 10
LPCSAD9
LPCSAD10
LPCSAD11
LPCSAD12
LPCSAD13
Slave address bit 11
Slave address bit 12
Slave address bit 13
Slave address bit 14
LPCSAD14
LPCSAD15
Slave address bit 15
Fig. 27 LPC related registers
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Basic Operation of LPC Interface
Set up steps for LPC interface is as below.
(2) Example for I/O read cycle
The I/O read cycle timing is shown in Figure 29. The standard
transfer cycle number of I/O read cycle is 13. The data on LAD
[3:0] is monitored at every rising edge of LCLK. The communica-
tion starts from the falling edge of LFRAME.
•Set the LPC interface enable bit (bit3 of LPCCON) to “1”.
•Choose which data bus buffer channel use.
•Set the data bus buffer i enable bit (i = 0, 1) (bit 4 or 5 of
LPCCON) to “1”.
st
•1 clock: The last clock when LFRAME is “Low”. The host sends
•Set the slave address to LPCi address register L and H (i = 0, 1)
(LPC0ADL, LPC0ADH, LPC1ADL, LPC1ADH).
“00002” on LAD [3:0] for communication start.
nd
•2 clock: LFRAME is “High”. The host sends “000X2” on LAD
[3:0] to inform the cycle type as I/O read.
rd
(1) Example of I/O write cycle
• From 3 clock to 6th clock: In these four cycles , the host sends
The I/O write cycle timing is shown in Figure 28. The standard
transfer cycle number of I/O write cycle is 13. The communication
starts from the falling edge of LFRAME.
16-bit slave address. The 3882 compares it with the LPCi ad-
dress register H or L (i = 0, 1).
rd
3
4
5
6
clock: The slave address bit [15:12].
clock: The slave address bit [11:8].
clock: The slave address bit [7:4].
th
th
th
The data on LAD [3:0] is monitored at every rising edge of LCLK.
st
• 1 clock: The last clock when LFRAME is “Low”. The host send
“00002” on LAD [3:0] for communication start.
clock: The slave address bit [3:0].
nd
th
th
• 2 clock: LFRAME is “High”. The host send “001X2” on LAD
• 7 clock and 8 clock are used for turning the communication di-
[3:0] to inform the cycle type as I/O write.
rection from the host→the peripheral to the peripheral→the host.
rd
th
th
• From 3 clock to 6 clock : In these four cycles , the host sends
7
8
clock: The host outputs “11112” on LAD [3:0].
clock: The LAD [3:0] is set to tri-state by the host to
turn the communication direction.
th
16-bit slave address. The 3882 compares it with the LPCi ad-
dress register H and L (i = 0, 1).
rd
th
3
4
5
6
clock: The slave address bit [15:12].
clock: The slave address bit [11:8].
clock: The slave address bit [7:4].
• 9 clock: The 3882 outputs “00002” (SYNC OK) to LAD [3:0] for
th
th
th
acknowledgment.
th
th
• 10 clock and 11 clock are used for one data byte transfer from
the output data bus buffer i (DBBOUTi) or data bus buffer status
register i (DBBSTSi).
clock: The slave address bit [3:0].
th
th
• 7 clock and 8 clock are used for one data byte transfer. The
th
data is written to the input data bus buffer (DBBINi, i = 0, 1)
10 clock: The 3882 sends the data bit [3:0].
th
th
7
8
clock: The host sends the data bit [3:0].
11 clock: The 3882 sends the data bit [7:4].
th
th
clock: The host sends the data bit [7:4].
• 12 clock: The 3882 outputs “11112” to LAD [3:0]. In this timing
th
th
• 9 clock and 10 clock are for turning the communication direc-
OBFi (bit 2 of DBBSTSi) is cleared to “0” and OBE
tion from the host→the peripheral to the slave→the host.
interrupt signal is generated.
th
th
9
clock: The host outputs “11112” on LAD [3:0].
• 13 clock: The LAD [3:0] is set to tri-state by the host to turn the
th
10 clock: The LAD [3:0] is set to tri-state by the host to
turn the communication direction.
communication direction.
th
• 11 clock: The 3882 outputs “00002” (SYNC OK) to LAD [3:0] for
acknowledgment.
th
• 12 clock: The 3882 outputs “11112” to LAD [3:0]. In this timing
the address bit 2 is latched to XA2i (bit3 of DBBSTSi),
IBFi (bit 1 of DBBSTSi) is set to “1” and IBF interrupt
signal is generated.
th
• 13 clock: The LAD [3:0] is set to tri-state by the host to turn the
communication direction.
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ꢀ
Data write (I/O write cycle)
CYCTYPE
START
ADDRESS
DATA
TAR
SYNC
TAR
+
DIR
LCLK
LFRAME
LAD [3:0]
(Note)
Input data bus buffer i
XA2i flag
IBFi flag
driven by the host
driven by the 3882
ꢀ
Command write (I/O write cycle)
CYCTYPE
START
ADDRESS
DATA
TAR
SYNC
TAR
+
DIR
LCLK
LFRAME
LAD [3:0]
(Note)
Input data bus buffer i
XA2i flag
IBFi flag
driven by the 3882
to LAD3 pins remain tri-state after transfer
driven by the host
Note: LAD
0
Fig. 28 Data and command write timing
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Data Read (I/O read cycle)
CYCTYPE
START
ADDRESS
TAR
SYNC
DATA
TAR
+
DIR
LCLK
LFRAME
LAD [3:0]
(Note 1)
Output data bus buffer i
OBFi flag
driven by the host
driven by the 3882
Status Read (I/O read cycle)
CYCTYPE
START
ADDRESS
TAR
SYNC
DATA
TAR
+
DIR
LCLK
LFRAME
(Note 1)
LAD [3:0]
OBFi flag
(Note 2)
driven by the host
driven by the the 3882
Notes: 1: LAD0 to LAD3 pins remain tri-state after transfer completion.
2: OBFi flag does not change.
Fig. 29 Data and status read timing
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LPCSR write signal
LPCSR bit
(LPC interface software reset signal)
1.5 cycle of φ
LRESET
LPC interface reset signal
D
D
Q
Q
D
Q
CPU Data bus bit 2
LPCSR write signal
CK
CK
R
CK
R
R
CPU RESET
φ
CPU RESET
Fig. 30 Reset timing and block
Table 10 Reset conditions of LPC interface function
Pin name / Internal register
P80/LAD0
LRESET = “L”
Tri-state
Note
P81/LAD1
P82/LAD2
P83/LAD3
P84/LFRAME
Input
P85/LRESET
LPC bus interface function
Input
P86/LCLK
Input data bus buffer registeri
Output data bus buffer registeri
Uxi flag 7, 6, 5, 4, 2
Keep same value before
LRESET goes “L”.
XA2i flag
IBFi flag
Initialization to “0”.
Initialization to “0”.
There is possibility to generate
IBF interrupt request.
OBFi flag
Initialization to “0”.
There is possibility to generate
OBE interrupt request.
LPCi address register
LPCCON
Keep same value before
LRESET goes “L”.
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SERIALIZED INTERRUPT
The serialized IRQ circuit communicates the interrupt status to the
host controller based on the Serialized IRQ Support for PCI System,
Version 6.0.
Table 11 shows the summary of serialized interrupt of 3882.
Table 11 Smmary of serialized IRQ function
Item
Function
The factors of serialized IRQ
The numbers of serialized IRQ factor that can output simultaneously are 3.
• Channel 0 (IRQ1,IRQ2)
ꢀ Setting Software IRQi (i = 1, 12) request bit (bits 0, 1 of SERIRQ) to “1”.
ꢀ The “1” of OBF0 and Hardware IRQi ( i=1, 12) request bit (bits 3, 4 of SERCON) to “1”.
• Channel 1 (IRQx ; user selectable)
ꢀ Setting the IRQx request bit (bit 7 of SERIRQ) to “1”.
ꢀ The “1” of OBF1 and Hardware IRQx request bit to “1”.
• Channel 0 (IRQ1, IRQ12)
The number of frame
ꢀ Setting Software IRQ1 request bit (bit 0 of SERIRQ) to “1” or detecting “1” of OBF0 with
“1” of Hardware IRQ1 request bit (bit 4 of SERCON) selects IRQ1 Frame .
ꢀ Setting IRQ12 Software request bit (bit 1 of SERIRQ) to “1” or detecting “1” of OBF0 with
“1” of Hardware IRQ1 request bit (bit 4 of SERCON) selects IRQ12 Frame.
• Channel 1 (IRQx ; user selectable)
Setting IRQx frame select bit (bit 2-6 of SERIRQ) selects IRQ 1–15 frame or extend
frame 0–10.
Operation clock
Clock restart
Synchronized with LCLK (Max. 33 MHz).
LPC clock restart enable bit (bit 1 of SERCON) enables restart owing to “L” output of CLKRUN
with the interrupt when the LPC clock has stopped or slowed down.
Clock stop inhibition
LPC clock stop inhibition bit (bit 2 of SERCON) enables the inhibition of clock stop control
during the IRQSER cycle when the clock tends to stop or slow down.
Rev.1.01 Nov 14, 2005 page 38 of 60
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Internal data bus
Serialized IRQ control register
Serialized IRQ request register
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Clock stop inhibition enable
and clock restart enable
Software Serialized IRQ request
OBF interrupt control
Serialized IRQ enable
OBF0 – OBF1
Serialized interrupt request
control circuit
IRQx frame number
Serialized
IRQ request
Frame number
SERIRQ
Serialized interrupt
control circuit
Clock restart request
and start frame
Clock operation
activate request
status and finish
acknowledgement
Clock monitor
control circuit
*
CLKRUN#
LCLK
LRESET#
CPU clock φ
Open Drain
*
Fig. 31 Block diagram of serialized interrupt
Rev.1.01 Nov 14, 2005 page 39 of 60
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Register Explanation
Bit 3 : Hardware IRQ1 request bit (SEIR1)
When this bit is “1”, OBF0 status is directly connected to the IRQ1
frame.
The serialized IRQ function is configured and controlled by the se-
rialized IRQ request register (SERIRQ) and the serialized IRQ
control register (SERCON).
Bit 4 : Hardware IRQ12 request bit (SEIR12 )
When this bit is “1”, OBF0 status is directly connected to IRQ12
frame.
[Serialized IRQ control register (SERCON)] 001D16
Bit 0 : Serialized IRQ enable bit (SIRQEN )
This bit enables/disables the serialized IRQ interface. When this
bit is “1”, use of serialized IRQ is enabled. Then P87 functions as
IRQ/Data line (SERIRQ) and P47 functions as CLKRUN.
Output structure of CLKRUN pin becomes N-channel open drain.
Bit 5 : Hardware IRQx request bit (SEIRx )
When this bit is “1”, OBF1 status is directly connected to the IRQx
frame.
Bit 1 : LPC clock restart enable bit (RUNEN )
Setting this bit to “1” enables clock restart with “L” output of
CLKRUN.
Bit 6 : IRQ1/IRQ12 disable bit (SCH0EN )
This bit controls whether the serialized IRQ channel 0 transfers
the IRQ1 and IRQ12 frame to the host or not.
Bit 2 : LPC clock stop inhibition bit (SUPEN )
Setting this bit to “1” makes CLKRUN output change to “L” for in-
hibiting the clock stop.
Bit 7 : IRQx output polarity bit (SCH1POL)
This bit selects IRx frame output level.
Serialized IRQ control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SERCON
Address
001D16
When reset
00000000
2
Bit symbol
SIRQEN
Bit name
Function
R
W
0 : Serialized IRQ disable
1 : Serialized IRQ enable
Serialized IRQ enable bit
LPC clock restart enable bit
LPC clock stop inhibition bit
0 : Clock restart disable
1 : Clock restart enable
RUNEN
SUPEN
0 : Stop inhibition control disable
1 : Stop inhibition control enable
0 : No IRQ1 request
Hardware IRQ1 request bit
SEIR1
1 : OBF
0 synchronized IRQ1 request
0 : No IRQ12 request
Hardware IRQ12 request bit
Hardware IRQx request bit
SEIR12
SEIRx
1 : OBF0 synchronized IRQ12 request
0 : No IRQx request
1 : OBF synchronized IRQx request
1
IRQ1/IRQ12 disable bit
IRQx output polarity bit
0 : IRQ1/IRQ12 output enable
1 : IRQ1/IRQ12 output disable
SCH0EN
SCH1POL
0 : -Request Hiz-Hiz-Hiz
-No request L-H-Hiz
1 : -Request L-H-Hiz
-No request Hiz-Hiz-Hiz
Fig. 32 Configuration of serialized IRQ control register
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[Serialized IRQ request register (SERIRQ)] 001F16
The interrupt source is definable by this register.
Bits 2-6 : IRQx frame select bits (ISi, i = 0–4)
These bits select the active IRQ frame of serial IRQ channel 1.
When these bit are “000002”, the serial IRQ channel 1 is disabled.
Bit 0 : Software IRQ1 request bit (IR1)
SERIRQ line shows IR1 value at the sample phase of IRQ1 frame,
when the SCH0EN is “1”.
Bit 7 : Software IRQx request bit (IRx)
SERIRQ line shows IRx value at the sample phase of IRQx frame
which is selected by bits 2 to 6 of SERIRQ. Output level is select-
able by the IRQx output polarity bit (SCH1POL).
Bit 1 : Software IRQ12 request bit (IR12)
SERIRQ line shows IR12 value at the sample phase of IRQ12
frame, when the SCH0EN is “1”.
Serialized IRQ request register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SERIRQ
Address
001F16
When reset
000000002
R
W
Bit symbol
IR1
Bit name
Function
Software IRQ1
request bit
0: No IRQ1 request
1: IRQ1 request
Software IRQ12
request bit
0: No IRQ12 request
1: IRQ12 request
IR12
IS0
IRQx frame select bit
b6b5b4b3b2
0 0 0 0 0 : Disable serial IRQ channel 1
0 0 0 0 1 : IRQ1 Frame
0 0 0 1 0 : IRQ2 Frame
0 0 0 1 1 : IRQ3 Frame
0 0 1 0 0 : IRQ4 Frame
0 0 1 0 1 : IRQ5 Frame
0 0 1 1 0 : IRQ6 Frame
0 0 1 1 1 : IRQ7 Frame
0 1 0 0 0 : IRQ8 Frame
0 1 0 0 1 : IRQ9 Frame
0 1 0 1 0 : IRQ10 Frame
0 1 0 1 1 : IRQ11 Frame
0 1 1 0 0 : IRQ12 Frame
0 1 1 0 1 : IRQ13 Frame
0 1 1 1 0 : IRQ14 Frame
0 1 1 1 1 : IRQ15 Frame
1 0 0 0 0 : Do not select
1 0 0 0 1 : Do not select
1 0 0 1 0 : Do not select
1 0 0 1 1 : Do not select
1 0 1 0 0 : Do not select
1 0 1 0 1 : Extend Frame 0
1 0 1 1 0 : Extend Frame 1
1 0 1 1 1 : Extend Frame 2
1 1 0 0 0 : Extend Frame 3
1 1 0 0 1 : Extend Frame 4
1 1 0 1 0 : Extend Frame 5
1 1 0 1 1 : Extend Frame 6
1 1 1 0 0 : Extend Frame 7
1 1 1 0 1 : Extend Frame 8
1 1 1 1 0 : Extend Frame 9
1 1 1 1 1 : Extend Frame 10
IS1
IS2
IS3
IS4
IRx
Software IRQx
request bit
0: No IRQx request
1: IRQx request
Fig. 33 Structure of serialized IRQ request register
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Operation of Serialized IRQ
(2) IRQ/Data Frame
A cycle operation of serialized IRQ starts with Start Frame and fin-
ishes with Stop Frame. There are two modes of operation :
Continuous (Idle) mode and Quiet (Active) mode. The next opera-
tion mode is determined by monitoring the stop frame pulse width.
Each IRQ/Data Frame is three clocks. When the IRQi (i = 0, 1, x)
request is “0”, then the SERIRQ line is driven to “L” during the
st
Sample phase (1 clock) of the corresponding IRQ/Data frame,
nd
to “H” during the Recovery phase (2 clock), to tri-state during
rd
the Turn-around phase (3 clock). When the IRQi request is “1”,
ꢀTiming of serialized IRQ cycle
then the SERIRQ line is tri-state in all phases (3 clocks period).
Figure 54 shows the timing diagram of serialized IRQ cycle.
(3) Stop Frame
(1) Start Frame
The Stop Frame is detected when the SERIRQ line remains “L” in
2 or 3 clocks. The next operation mode is Quiet mode when the
pulse width of “L” is 2 clocks. The next operation mode is the
Continuous mode when the pulse width is 3 clocks.
The Start Frame is detected when the SERIRQ line remains “L” in
4 to 8 clocks.
Start frame
IRQ0 frame
IRQ1 frame
IRQ15 frame
IOCHK frame
Stop frame
Host control
To the next cycle
Clock
SERIRQ
Driver source
IRQ15
device
control
IRQ1
device
control
Host control
Fig. 34 Timing diagram of serialized IRQ cycle
Rev.1.01 Nov 14, 2005 page 42 of 60
REJ03B0089-0101
3882 Group
Operation Mode
Figure 35 shows the timing of continuous mode; Figure 36 shows
After receiving the start frame; the IRQ1 Frame, IRQ12 Frame or
IRQx frame is asserted.
that of Quiet mode.
Note : If the pulse width of “L” is less than 4 clocks, or 9 clocks or
more; the start frame is not detected and the next start (the
falling edge of SERIRQ) is waited.
(1) Continuous mode
Serialized IRQ cycles starts in Continuous mode after CPU reset
in the case of LRESET = “L” and the previous stop frame being 3
clocks.
Start frame (Note)
IRQ0 frame
IRQ1 frame
IRQ2 frame
IRQ3 frame
LCLK
SERIRQ line
Host SERIRQ output
3883 SERIRQ output
Drive source
Host
3882
Note: The start frame count is 4 clocks as exemple.
Fig. 35 Timing diagram of Continuous mode
(2) Quiet mode
Note: When the sum of pulse width of “L” driven by the 3882 in
st
At clock stop, clock slow down or the pulse width of the last stop
frame being 2 clocks, it is the Quiet mode.
the 1 clock and driven by the host in the rest clocks is
within 4 to 8-clock cycles, the start frame is detected.
If the sum of pulse width of “L” is less than 4 clocks, or 9
clocks or more; the start frame is not detected and the next
start (the falling edge of SERIRQ) is waited.
st
In this mode the 3882 drives the SERIRQ line to “L” in the 1
clock. After that the host drives the rest start frame (Note). The
IRQ1 frame, IRQ12 frame or IRQx frame is asserted.
IRQ0 frame
Start frame (Note)
IRQ1 frame
IRQ2 frame
IRQ3 frame
LCLK
SERIRQ line
Host SERIRQ output
3883 SERIRQ output
Drive source
3882
3882
Host
Note: The start frame count is 4 clocks as exemple
Fig. 36 Timing diagram of Quiet mode
Rev.1.01 Nov 14, 2005 page 43 of 60
REJ03B0089-0101
3882 Group
Clock Restart/Stop Inhibition Request
Asserting the CLKRUN signal can request the host to restart for
clocks stopped or slowed down, or maintain the clock tending to
stop or slow down.
(1) Clock restart operation
In case the LPC clock restart enable bit (bit 1 of SERCON) is “1”
and the CLKRUN (BUS) is “H”, when the serialized interrupt re-
quest occurs, the 3882 drives CLKRUN to “L” for requesting the
PCI clock generator to restart the LCLK if the clock is slowed
down or stopped.
Figure 37 shows the timing diagram of clock restart request; Fig-
ure 38 shows an example of timing of clock stop inhibition
request.
LCLK
Bus CLKRUN
Central Resource CLKRUN
3882 CLKRUN
Restart frame
Start frame
Bus SERIRQ
Host SERIRQ
3882 SERIRQ
φ
Interrupt request
Internal restart
request signal
Fig. 37 Timing diagram of clock restart request
(2) Clock stop inhibition request
In case the LPC clock stop inhibition bit (bit 2 of SERCON) is “1”
and the serialized interrupt request is held, if the LCLK tends to
stop, the 3882 drives CLKRUN to “L” for requesting the PCI clock
generator not to stop LCLK.
LCLK
Bus CLKRUN
Central Resource CLKRUN
3882 CLKRUN
Inhibition
request
IRQSER cycle
Bus SERIRQ
Interrupt request
Internal inhibition request signal
Fig. 38 Timing diagram of clock stop inhibition request
Rev.1.01 Nov 14, 2005 page 44 of 60
REJ03B0089-0101
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RESET CIRCUIT
____________
To reset the microcomputer, RESET pin should be held at an “L”
level for 16 XIN cycle or more. (When the power source voltage
Poweron
should be between 3.3V ± 0.3V and the oscillation should be
(Note)
____________
Power source
voltage
0V
stable.) Then the RESET pin set to “H”, the reset state is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.6 V for VCC of 3.0 V.
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; Vcc=3.0 V
RESET
V
CC
Power source
voltage detection
circuit
Fig. 39 Reset circuit example
XIN
φ
RESET
Internal
reset
Address
AD
H L
,
?
?
?
?
FFFC
FFFD
Reset address from the vector table.
Data
ADH
?
?
?
ADL
?
SYNC
XIN: 10.5 to 18.5 clock cycles
Notes
1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8
• f(φ).
2: The question marks (?) indicate an undefined data that depends on the previous state.
Fig. 40 Reset sequence
Rev.1.01 Nov 14, 2005 page 45 of 60
REJ03B0089-0101
3882 Group
Address
Register contents
Register contents
0016
Address
(1)
0016
Port P0 (P0)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002E16
002F16
003916
(38)Interrupt edge selection register (INTEDGE)
(39)CPU mode register (CPUM)
(40)Interrupt request register 1 (IREQ1)
(41)Interrupt request register 2 (IREQ2)
(42)Interrupt control register 1 (ICON1)
(43)Interrupt control register 2 (ICON2)
(44)LPC0 address register L (LPC0ADL)
(45)LPC0 address register H (LPC0ADH)
(46)LPC1 address register L (LPC1ADL)
(47)LPC1 address register H (LPC1ADH)
(48)Port P5 input register (P5I)
(49)Port control register 3 (PCTL3)
(50)Processor status register
003A16
003B16
003C16
003D16
003E16
003F16
0FF016
0FF116
0FF216
0FF316
0FF816
0FF916
(PS)
(2)
0016
Port P0 direction register (P0D)
Port P1 (P1)
0 1 0 0 1 0 0 0
0016
(3)
0016
(4)
0016
Port P1 direction register (P1D)
Port P2 (P2)
0016
0016
0016
0016
0016
0016
0016
0016
0016
(5)
0016
(6)
0016
Port P2 direction register (P2D)
Port P3 (P3)
(7)
0016
(8)
0016
Port P3 direction register (P3D)
Port P4 (P4)
(9)
0016
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
0016
Port P4 direction register (P4D)
Port P5 (P5)
0016
0016
Port P5 direction register (P5D)
Port P6 (P6)
0016
1
X X X X X X X
0016
Port P6 direction register (P6D)
Port P7 (P7)
(51)Program counter
(PCH)
FFFD16 contents
FFFC16 contents
0016
(PCL)
0016
Port P7 direction register (P7D)
Port P8 (P8)
0016
0016
Port P8 direction register (P8D)
Serialized IRQ control register (SERCON)
Watchdog timer control register (WDTCON)
Serialized IRQ request register (SERIRQ)
Prescaler 12 (PRE12)
0016
0 0 1 1 1 1 1 1
X X X X X X X X
FF16
0116
Timer 1 (T1)
FF16
Timer 2 (T2)
0016
Timer XY mode register (TM)
Prescaler X (PREX)
FF16
FF16
Timer X (TX)
FF16
FF16
Prescaler Y (PREY)
Timer Y (TY)
X X X X X X X X
0016
Data bus buffer register 0 (DBB0)
Data bus buffer status register 0 (DBBSTS0)
LPC control register (LPCCON)
Data bus buffer register 1 (DBB1)
Data bus buffer status register 1 (DBBSTS1)
Port control register 1 (PCTL1)
Port control register 2 (PCTL2)
Interrupt source selection register (INTSEL)
0016
X X X X X X X X
0016
0016
0016
0016
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Fig. 41 Internal status at reset
Rev.1.01 Nov 14, 2005 page 46 of 60
REJ03B0089-0101
3882 Group
CLOCK GENERATING CIRCUIT
The 3882 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT Use the circuit constants in accordance with the resonator
manufacturer’s recommended values. No external resistor is
needed between XIN and XOUT since a feed-back resistor exists
on-chip. (An external feed-back resistor may be needed depend-
ing on conditions.)
X
IN
XOUT
Rd (Note)
Immediately after power on, only the XIN oscillation circuit starts
oscillating.
C
IN
COUT
Frequency Control
(1) Middle-speed mode
Notes : Insert a damping resistor if required.
The internal clock φ is the frequency of XIN divided by 8. After re-
The resistance will vary depending on the oscillator and
the oscillation drive capacity setting.
set, this mode is selected.
Use the value recommended by the maker of the oscillator.
Also, if the oscillator manufacturer's data sheet specifies to
add a feedback resistor externally to the chip though a
feedback resistor exists on-chip, insert a feedback resistor
between XIN and XOUT following the instruction.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
Fig. 42 Ceramic resonator circuit
ꢀNote
If you switch the mode between middle/high-speed ,stabilize XIN
oscillations.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN oscillators stop. When the oscillation stabilizing
time set after STP instruction released bit is “0,” the prescaler 12
is set to “FF16” and timer 1 is set to “0116”. When the oscillation
stabilizing time set after STP instruction released bit is “1”, set the
sufficient time for oscillation of used oscillator to stabilize since
nothing is set to the prescaler 12 and timer 1.
X
IN
X
OUT
Open
External oscillation
circuit
XIN divided by 16 is input to the prescaler 12 as count source, and
the output of the prescaler 12 is connected to timer 1. Set the
timer 1 interrupt enable bit to disabled (“0”) before executing the
STP instruction. Oscillator restarts when an external interrupt is
received, but the internal clock φ is not supplied to the CPU (re-
mains at “H”) until timer 1 underflows. The internal clock φ is
supplied for the first time, when timer 1 underflows. Therefore
make sure not to set the timer 1 interrupt request bit to “1” before
the STP instruction stops the oscillator. When the oscillator is re-
started by reset, apply “L” level to the RESET pin until the
oscillation is stable since a wait time will not be generated.
V
CC
SS
V
Fig. 43 External clock input circuit
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
Rev.1.01 Nov 14, 2005 page 47 of 60
REJ03B0089-0101
3882 Group
X
IN
X
OUT
(Note 3)
1/2
1/4
1/2
Prescaler 12
FF16
Timer 1
0116
High-speed or
middle-speed
mode
Reset or
STP instruction
(Note 2)
Main clock division ratio
selection bits (Note1)
Middle-speed mode
Timing φ (internal clock)
High-speed
Q
S
R
S Q
R
Q
S
R
STP instruction
STP instruction
WIT instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: Either high-speed ,or middle-speed is selected by bits 7 and 6 of the CPU mode register.
2: f(XIN)/16 is supplied as the count source to the Prescaler 12 at reset. When exciting STP instruction,
the count source does not change either f(XIN))/16 after releasing stop mode. Oscillation stabilizing
time is not fixed “01FF16” when the bit 6 of PCTL2 is “1”.
3: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending
on conditions.
Fig. 44 System clock generating circuit block diagram (Single-chip mode)
Rev.1.01 Nov 14, 2005 page 48 of 60
REJ03B0089-0101
3882 Group
Reset
CM
6
Middle-speed mode
(f(φ)=1 MHz)
High-speed mode
(f(φ)=4 MHz)
“1”←→“0”
CM
CM
7
6
=0
=1
CM
7
=0
=0
CM
6
b7 b6
CPU mode register
(CPUM : address 003B16
)
CM
7
, CM
6: Main clock division ratio selection bit
b7 b6
0
0 : φ = f(XIN)/2 ( High-speed mode)
0
1
1
1 : φ = f(XIN)/8 (Middle-speed mode)
0 : Not available
1 : Not available
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode.
5 : The example assumes that 8 MHz is being applied to the XIN pin . φ indicates the internal clock.
Fig. 45 State transitions of system clock
Rev.1.01 Nov 14, 2005 page 49 of 60
REJ03B0089-0101
3882 Group
NOTES ON PROGRAMMING
Instruction Execution Time
The instruction execution time is obtained by multiplying the pe-
riod of the internal clock φ by the number of cycles needed to
execute an instruction.
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock φ is twice of the XIN period in high-
speed mode.
Interrupts
Reserved Area, Reserved Bit
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
Do not write any data to the reserved area in the SFR area and
thespecial page. (Do not change the contents after reset.)
CPU Mode Register
Be sure to fix bit 3 of the CPU mode register (address 003B16) to
Decimal Calculations
“1”.
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
• The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The instruction with the addressing mode which uses the value
of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Rev.1.01 Nov 14, 2005 page 50 of 60
REJ03B0089-0101
3882 Group
NOTES ON USAGE
Termination of Unused Pins
Be sure to perform the termination of unused pins.
The shortest
Handling of Power Source Pins
CNVSS/(VPP
)
(Note)
(Note)
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ce-
ramic capacitor of 0.01 µF–0.1 µF is recommended.
Approx. 5kΩ
VSS
The shortest
Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
Note. Shows the microcomputer's pin.
Fig. 46 Wiring for the CNVSS/(VPP) pin
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less than
the recommended operating conditions and design a system not
to cause errors to the system by this unstable operation.
NOTES ON QzROM
Notes On QzROM Writing Orders
When ordering the QzROM product shipped after writing, submit
the mask file (extension : .msk) which is made by the mask file
converter MM.
Product shipped in blank
As for the product shipped in blank, Renesas does not perform the
writing test to user ROM area after the assembly process though
the QzROM writing test is performed enough before the assembly
process. Therefore, a writing error of approx.0.1 %may occur.
Moreover, please note the contact of cables and foreign bodies on
a socket, etc. because a writing environment may cause some
writing errors.
Be sure to set the ROM option (“MASK option“ written in the mask
file converter) setup when making the mask file by using the mask
file converter MM.
Notes On ROM Code Protect
(QzROM product shipped after writing)
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the ROM option setup data in the
mask file which is submitted at ordering. The ROM option setup
data in the mask file is “0016” for protect enabled or “FF16” for pro-
tect disabled. Therefore, the contents of the ROM code protect
address (other than the user ROM area)of the QzROM product
shipped after writing is “0016” or “FF16”.
Overvoltage
Take care that overvoltage is not applied. Overvoltage may cause
the QzROM contents rewriting. Take care especially at turning on
the power.
QzROM Version
Note that the mask file which has nothing at the ROM option data
or has the data other than “0016” and “FF16” can not be accepted.
Connect the CNVSS/(VPP) pin the shortest possible to the GND
pattern which is supplied to the VSS pin of the microcomputer.
In addition connecting an approximately 5 k Ω resistor in series to
the GND could improve noise immunity. In this case as well as the
above mention, connect the pin the shortest possible to the GND
pattern which is supplied to the VSS pin of the microcomputer.
DATA REQUIRED FOR QzROM WRITING
ORDERS
The following are necessary when ordering a QzROM product
shipped after writing:
1.QzROM Writing Confirmation Form*
•Reason
2.Mark Specification Form*
The CNVSS/(VPP) pin is the power source input pin for the built-in
QzROM. When programming in the QzROM, the impedance of the
VPP pin is low to allow the electric current for writing to flow into
the built-in QzROM. Because of this, noise can enter easily.If
noise enters the CNVSS/(VPP) pin, abnormal instruction codes or
data are read from the QzROM, which may cause a program run-
away.
3.ROM data...........Mask file
*For the QzROM writing confirmation form and the mark specifica-
tion form, refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer's
trademark etc.) in QzROM microcomputer.
Rev.1.01 Nov 14, 2005 page 51 of 60
REJ03B0089-0101
3882 Group
ELECTRICAL CHARACTERISTICS
Table 12 Absolute maximum ratings
Symbol
Parameter
Power source voltages
Conditions
Ratings
Unit
V
VCC
–0.3 to 4.6
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P80–P87, RESET,
XIN,CNVSS
VI
–0.3 to VCC +0.3
V
All voltages are based on VSS.
When an input voltage is measured,
output transistors are cut off.
VI
Input voltage P70–P77
–0.3 to 5.8
V
V
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P80–P87, XOUT
Output voltage P70–P77
VO
–0.3 to VCC +0.3
VO
0.3 to 5.8
500
V
mW
°C
Pd
Power dissipation
Ta = 25°C
Topr
Tstg
Operating temperature
–20 to 85
–40 to 125
Storage temperature
°C
Table 13 Recommended operating conditions
(VCC = 3.3 V ± 0.3V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
3.3
Max.
VCC
Power source voltage
Power source voltage
“H” input voltage
3.0
3.6
V
V
V
VSS
VIH
0
P00–P07, P10–P17, P20–P27, _P__3__0__–__P__3_ 7, P40–P47,
P50–P57, P60–P67, P80–P87,
0.8VCC
VCC
, CNVSS
RESET
VIH
VIH
“H” input voltage
P70–P77
0.8VCC
2.0
5.5
5.5
V
V
“H” input voltage (when TTL input level is selected)
P70–P75
VIH
VIL
“H” input voltage
“L” input voltage
XIN
0.8VCC
0
VCC
V
V
P00–P07, P10–P17, P20–P27, P30–P37,__P__4__0__–__P__47,
P50–P57, P60–P67, P70–P77, P80–P87,
CNVSS
0.2VCC
,
RESET
VIL
VIL
“L” input voltage (when TTL input level is selected)
P70–P75
0
0
0.8
V
V
“L” input voltage
XIN
0.16VCC
Rev.1.01 Nov 14, 2005 page 52 of 60
REJ03B0089-0101
3882 Group
Table 14 Recommended operating conditions
(VCC = 3.3 V ± 0.3V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
–P0 , P1 –P1
Unit
Min.
Max.
–80
–80
80
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
P0
P40–P47, P50–P57, P60–P67
P0 –P0 , P1 –P1 , P2 –P2 , P3
P24–P27
P40–P47,P50–P57, P60–P67, P70–P77
0
7
0
7
, P2
0
–P2
3
, P3
0
–P3
7
, P8
0
0
–P8
–P8
7
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
0
7
0
7
0
3
0
–P3
7
, P8
80
80
“H” total average output current P0
“H” total average output current P40–P47,P50–P57, P60–P67
“L” total average output current P0 –P0 , P1 –P1 , P2 –P2 , P3
“L” total average output current P24–P27
“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P8
0
0
–P8
–P8
7
7
–40
–40
40
0
7
0
7
0
3
0
–P3
7
, P8
40
40
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
Table 15 Recommended operating conditions
(VCC = 3.3 V ± 0.3V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
mA
Min.
Typ.
Max.
IOH(peak)
“H” peak output current
“L” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 1)
–10
IOL(peak)
P00–P07, P10–P17, P20–P23, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 1)
10
mA
IOL(peak)
IOH(avg)
“L” peak output current
P24–P27 (Note 1)
20
mA
mA
“H” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 2)
–5
IOL(avg)
“L” average output current
“L” peak output current
P00–P07, P10–P17, P20–P23, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)
5
mA
IOL(avg)
f(XIN)
P24–P27 (Note 2)
15
8
mA
Main clock input oscillation frequency (Note 3)
MHz
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
Rev.1.01 Nov 14, 2005 page 53 of 60
REJ03B0089-0101
3882 Group
Table 16 Electrical characteristics
(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
“H” output voltage
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P80–P87 (Note)
Unit
V
Test conditions
Min.
Max.
VOH
VOL
IOH = –5 mA
VCC–1.0
“L” output voltage
IOL = 5 mA
1.0
0.4
V
V
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
IOL = 1.6 mA
Hysteresis
CNTR0, CNTR1, INT0, INT1
INT20–INT40, INT21–INT41, INT5
P30–P37, LRESET
VT+–VT–
0.4
V
LFRAME, LCLK, SERIRQ
“H” input current
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
RESET, CNVSS
VI = VCC
(Pin floating.
Pull-up transistors “off”)
5.0
IIH
IIH
IIL
µA
µA
µA
“H” input current XIN
VI = VCC
3
“L” input current
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
RESET,CNVSS
VI = VSS
(Pin floating.
Pull-up transistors “off”)
–5.0
IIL
IIL
“L” input current
“L” input current
XIN
VI = VSS
VI = VSS
–3
–100
µA
µA
–13
–50
3.6
P30–P37 (at Pull-up)
VRAM
RAM hold voltage
When clock stopped
2.0
V
Note: P00–P03 are measured when the P00–P03 output structure selection bit (bit 0 of PCTL1) is “0”.
P04–P07 are measured when the P04–P07 output structure selection bit (bit 1 of PCTL1) is “0”.
P10–P13 are measured when the P10–P13 output structure selection bit (bit 2 of PCTL1) is “0”.
P14–P17 are measured when the P14–P17 output structure selection bit (bit 3 of PCTL1) is “0”.
P42, P43, P44, and P46 are measured when the P4 output structure selection bit (bit 2 of PCTL2) is “0”.
Rev.1.01 Nov 14, 2005 page 54 of 60
REJ03B0089-0101
3882 Group
Table 17 Electrical characteristics
(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
High-speed mode
f(XIN) = 8 MHz
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz (in WIT state)
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz
Output transistors “off”
Middle-speed mode
Unit
mA
Min.
Max.
5
1.5
0.5
0.7
0.4
2
3
mA
mA
mA
ICC
Power source current
f(XIN) = 8 MHz (in WIT state)
Output transistors “off”
Additional current when LPC I/F functions
LCLK = 33 MHz
1.5
1.5
0.1
mA
µA
µA
All oscillation stopped
(in STP state)
Ta = 25 °C
1.0
10
Output transistors “off”
Ta = 85 °C
Rev.1.01 Nov 14, 2005 page 55 of 60
REJ03B0089-0101
3882 Group
Table 18 Timing requirements
(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
16
Max.
tc(XIN)
ns
tW(RESET)
tC(XIN)
Reset input “L” pulse width
Main clock input cycle time
125
50
ns
tWH(XIN)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
ns
tWL(XIN)
50
ns
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
200
80
ns
ns
80
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “H” pulse width
tWH(INT)
80
80
ns
ns
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “L” pulse width
tWL(INT)
Table 19 Switching characteristics
(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Test
conditions
Symbol
Parameter
Unit
Min.
Typ.
10
Max.
tr (CMOS)
tf (CMOS)
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
30
30
ns
ns
Fig. 46
10
Notes 1: The XOUT pin is excluded.
Rev.1.01 Nov 14, 2005 page 56 of 60
REJ03B0089-0101
3882 Group
Measurement output pin
50pF
CMOS output
Fig. 47 Circuit for measuring output switching characteristics
Rev.1.01 Nov 14, 2005 page 57 of 60
REJ03B0089-0101
3882 Group
Timing diagram
tC(CNTR)
t
WH(CNTR)
t
WL(CNTR)
0.8VCC
CNTR
0
, CNTR
1
0.2VCC
0.2VCC
t
WH(INT)
t
WL(INT)
INT0, INT1, INT
INT20, INT30, INT40
INT21, INT31, INT41
5
0.8VCC
t
W(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWH(XIN)
tWL(XIN)
0.8VCC
X
IN
0.2VCC
Fig. 48 Timing diagram
Rev.1.01 Nov 14, 2005 page 58 of 60
REJ03B0089-0101
3882 Group
Table 20 Timing requirements and switching characteristics
(VCC = 3.3 V ± 0.3V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Standard
Typ.
Symbol
Parameter
LCLK clock input cycle time
LCLK clock input “H” pulse width
LCLK clock input “L” pulse width
Unit
Min.
30
11
11
13
Max.
tC(CLK)
tWH(CLK)
tWL(CLK)
tsu(D-C)
ns
ns
ns
ns
input set up time LAD3 to LAD0,
SERIRQ, CLKRUN, LFRAME
7
0
th(C-D)
tV(C-D)
ns
ns
input hold time LAD3 to LAD0, CLKRUN, LFRAME
SERIRQ,
2
2
15
28
LAD3 to LAD0, SERIRQ, CLKRUN
valid delay time
toff(A-F)
ns
LAD3 to LAD0,SERIRQ,CLKRUN
floating output delay time
Timing diagrams of LPC Bus Interface and Serial Interrupt Output
tC(CLK)
tWH(CLK)
tWL(CLK)
VIH
VIL
LCLK
tsu(D-C)
th(C-D)
LAD[3:0]
SERIRQ, CLKRUN, LFRAME
(Input)
tv(C-D)
LAD[3:0]
SERIRQ, CLKRUN
(Active output)
toff(A-F)
LAD[3:0]
SERIRQ, CLKRUN
(Floating output )
Fig. 49 Timing diagram of LPC Interface and Serialized IRQ
Rev.1.01 Nov 14, 2005 page 59 of 60
REJ03B0089-0101
3882 Group
PACKAGE OUTLINE
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
PLQP0080KB-A
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
61
40
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
Terminal cross section
D
E
A2
HD
HE
A
11.9 12.0 12.1
11.9 12.0 12.1
1.4
13.8 14.0 14.2
13.8 14.0 14.2
1.7
80
21
1
20
ZD
Index mark
A1
bp
b1
c
0.1 0.2
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0
F
c1
0°
10°
y
*3
e
bp
e
x
y
0.5
L
x
0.08
0.08
L1
ZD
ZE
L
Detail F
1.25
1.25
0.3 0.5 0.7
1.0
L1
Rev.1.01 Nov 14, 2005 page 60 of 60
REJ03B0089-0101
3882 Group Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Oct 29, 2004
1.01 Nov 14, 2005
–
1
First edition issued
Power dissipation is revised. 1.5 mA → 20mW
1-2,5-6 Package name of 80P6Q-A is revised. 80P6Q-A → PLQP0080KB-A
3
5
Table 1 is partly revised.
Fig.3 is partly revised.
6
Table 3 is partly added. Note of Table 2 is added.
ROM Code Protect Address is added.
Table 7 is partly revised.
11
14
16
27
Note 2 of Fig.11 is added.
• WATCHDOG TIMER is revised.
• Fig.21 and Fig.22 are partly revised.
• CLOCK GENERATING CIRCUIT is partly revised.
• Fig.42 is partly revised.
47
48
50
51
Note 3 of Fig.44 is added.
Reserved Area, Reserved Bit and CPU Mode Register are added.
The following are added;
-Termination of Unused Pins
-Product shipped in blank
-Overvoltage
-QzROM Version
-Fig.46 Wiring for the CNVSS/(VPP) pin
-Notes On QzROM Writing Orders
-Notes On ROM Code Protect
-DATA REQUIRED FOR QzROM WRITING ORDERS
Table 12 is partly revised.
52
55
60
Table 17 is partly revised.
PACKAGE OUTLINE of 80P6Q-A is revised.
1 / 1
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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