M38868FC-XXXHP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38868FC-XXXHP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总111页 (文件大小：1975K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●Power dissipation
DESCRIPTION
The 3886 group is the 8-bit microcomputer based on the 740 fam-
In high-speed mode ..........................................................40 mW
(at 10 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ............................................................ 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Memory expansion possible (only for M38867M8A/E8A)
●Operating temperature range.................................... –20 to 85°C
ily core technology.
The 3886 group is designed for controlling systems that require
analog signal processing and include two serial I/O functions, A-D
converters, D-A converters, system data bus interface function,
watchdog timer, and comparator circuit.
2
The multi-master I C bus interface can be added by option.
<Flash memory mode>
●Supply voltage ................................................. VCC = 5 V ± 10 %
●Program/Erase voltage ............................... VPP = 11.7 to 12.6 V
●Programming method...................... Programming in unit of byte
●Erasing method
FEATURES
<Microcomputer mode>
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time .................................. 0.4 µs
(at 10 MHz oscillation frequency)
Batch erasing ........................................ Parallel/Serial I/O mode
Block erasing .................................... CPU reprogramming mode
●Program/Erase control by software command
●Memory size
ROM ................................................................. 32K to 60K bytes
RAM ............................................................... 1024 to 2048 bytes
●Programmable input/output ports ............................................ 72
●Software pull-up resistors ................................................. Built-in
●Interrupts ................................................. 21 sources, 16 vectors
(Included key input interrupt)
●Number of times for programming/erasing ............................ 100
●Operating temperature range (at programming/erasing)
..................................................................... Normal temperature
■Notes
●Timers ............................................................................. 8-bit ✕ 4
●Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized)
●Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)
●PWM output circuit ....................................................... 14-bit ✕ 2
●Bus interface .................................................................... 2 bytes
1. The flash memory version cannot be used for application em-
bedded in the MCU card.
2. Power source voltage Vcc of the flash memory version is 4.0
to 5.5 V.
2
●I C bus interface (option) ............................................. 1 channel
APPLICATION
●A-D converter ............................................... 10-bit ✕ 8 channels
●D-A converter ................................................. 8-bit ✕ 2 channels
●Comparator circuit ...................................................... 8 channels
●Watchdog timer ............................................................ 16-bit ✕ 1
●Clock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
Household product, consumer electronics, communications, note
book PC, etc.
In high-speed mode .................................................. 4.0 to 5.5 V
(at 10 MHz oscillation frequency)
In middle-speed mode........................................... 2.7 to 5.5 V(*)
(at 10 MHz oscillation frequency)
In low-speed mode ............................................... 2.7 to 5.5 V (*)
(at 32 kHz oscillation frequency)
(*: 4.0 to 5.5 V for Flash memory version)
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
40
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P1
P1
P20/DB0
P2
P2
P2
P2
P2
P2
P2
6
/AD14
/AD15
P3
1
/PWM10
/PWM00
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
7
P30
P8
7/DQ
6/DQ
5/DQ
4/DQ
3/DQ
2/DQ
1/DQ
0/DQ
7
6
5
4
3
2
1
0
1
/DB
/DB
/DB
/DB
/DB
/DB
/DB
1
P8
P8
P8
P8
P8
P8
P8
2
3
4
5
6
7
2
3
4
5
6
7
M38867M8A-XXXHP
M38867E8AHP
V
SS
V
CC
REF
AVSS
X
X
OUT
IN
V
P6
P6
P6
P6
P6
7
/AN7
/AN6
/AN5
/AN4
/AN3
P4
P4
RESET
CNVSS
P4
P4
P4
0
/XCOUT
/XCIN
6
5
4
3
1
V
PP
2
3
4
/INT
0
/OBF00
/OBF01
/INT
1
P6
P6
2
/AN
/AN
2
1
/RXD
1
: PROM version
Note: The pin number and the position of the
function pin may change by the kind of
package.
Package type : 80P6Q-A
Fig. 1 M38867M8A-XXXHP, M38867E8AHP pin configuration
PIN CONFIGURATION (TOP VIEW)
P8
P8
P8
P8
P8
P8
P8
P8
7
6
5
4
3
2
1
0
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
7
6
5
4
3
2
1
0
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
/DB
/DB
/DB
/DB
/DB
/DB
/DB
0
1
2
3
4
5
6
7
7/DB
V
CC
REF
AVSS
V
SS
V
X
OUT
X
IN
P6
P6
P6
P6
P6
7
6
5
4
3
/AN
/AN
/AN
/AN
/AN
7
6
5
4
3
P4
P4
RESET
CNVSS
P4
0
/XCOUT
/XCIN
1
V
PP
2
/INT
0
/OBF00
Note: The pin number and the position of
the function pin may change by the
kind of package.
Package type : 80D0
Fig. 2 M38867E8AFS pin configuration
2
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
40
61
P16
P17
P20
P21
P22
P23
P24
P25
P31/PWM10
39
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
38
37
36
35
34
33
32
P26
M38869MFA-XXXGP/HP
31
30
29
28
27
26
25
24
23
22
21
P27
VSS
XOUT
XIN
M38869FFAGP/HP
VREF
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P40/XCOUT
P41/XCIN
RESET
CNVSS
VPP
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
: Flash memory version
Note: The pin number and the position of the
function pin may change by the kind of
package.
Package type : 80P6S-A/80P6Q-A
Fig. 3 M38869MFA-XXXGP/HP, M38869FFAGP/HP pin configuration
3
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK
Fig. 4 Functional block diagram
4
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Functions
Pin
Name
Function except a port function
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•In the flash memory version, apply voltage of 4.0 V – 5.5 V to Vcc, and 0 V to Vss
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
Power source
VCC, VSS
•
If this pin is connected to Vcc, the internal ROM is inhibited and an external memory is accessed.
CNVSS
CNVSS input
•In the flash memory version, connected to VSS.
•In the EPROM version or the flash memory version, this pin functions as the VPP power source input pin.
•Reference voltage input pin for A-D and D-A converters.
•Analog power source input pin for A-D and D-A converters.
•Connect to VSS.
VREF
AVSS
Reference voltage
Analog power source
Reset input
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the clock generating circuit.
Clock input
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
XOUT
Clock output
I/O port P0
•8-bit CMOS I/O port.
•Comparator reference power source
input pin
P00/P3REF
•I/O direction register allows each pin to be individually
programmed as either input or output.
•When the external memory is used, these pins are used as the address bus.
•CMOS compatible input level.
P01–P07
P10–P17
•CMOS 3-state output structure or N-channel open-drain output structure.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•When the external memory is used, these pins are used as the address bus.
•CMOS compatible input level.
I/O port P1
I/O port P2
•CMOS 3-state output structure or N-channel open-drain output structure.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•When the external memory is used, these pins are used as the data bus.
•CMOS compatible input level.
P20–P27
•CMOS 3-state output structure.
•P24 to P27 (4 bits) are enabled to output large current for LED drive (only in single-chip mode).
•8-bit CMOS I/O port.
•Key-on wake-up input pin
•I/O direction register allows each pin to be individually
•Comparator input pin
P3
P3
0
1
/PWM00
/PWM10
programmed as either input or output.
•PWM output pin
•When the external memory is used, these pins are
used as the control bus.
I/O port P3
•CMOS compatible input level.
•CMOS 3-state output structure.
•Key-on wake-up input pin
•Comparator input pin
•These pins function as key-on wake-up and compara-
tor input.
P32–P37
•These pins are enabled to control pull-up.
5
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Functions
Pin
Name
Function except a port function
•8-bit I/O port with the same function as port P0.
<Input level>
•Sub-clock generating circuit I/O
pins
P40/XCOUT
P41/XCIN
P40, P41 : CMOS input level
(Connect a resonator.)
P42–P46 : CMOS compatible input level or TTL in-
put level
P42/INT0
/OBF00
•Interrupt input pins
P47 : CMOS compatible input level or TTL input
level in the bus interface function
•Bus interface function pins
P43/INT1
/OBF01
I/O port P4
<Output structure>
P40, P41, P47 : CMOS 3-state output structure
P42–P46 : CMOS 3-state output structure or N-
channel open-drain output structure
P44/RxD
P45/TxD
•Serial I/O1 function pins
•Regardless of input or output port, P42 to P46 can
be input every pin level.
P46/SCLK1
/OBF10
•When P42 and P43 are used as output port, the
function which makes P42 and P43 clear to “0”
when the host CPU reads the output data bus
buffer 0 can be added.
•Serial I/O1 function pins
P47/SRDY1
/S1
•Bus interface function pins
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
•Bus interface function pins
P50/A0
P51/INT20
/S0
•CMOS 3-state output structure.
•Interrupt input pins
P52/INT30
/R
•P50 to P53 can be switched between CMOS com-
patible input level or TTL input level in the bus
interface function.
•Bus interface function pins
P53/INT40
/W
I/O port P5
P54/CNTR0
P55/CNTR1
•Timer X, timer Y function pins
P56/DA1
/PWM01
•D-A converter output pin
•PWM output pin
P57/DA2
/PWM11
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
P60/AN0–
P67/AN7
I/O port P6
•A-D converter output pin
•Serial I/O2 function pin
•CMOS 3-state output structure.
P70/SIN2
•8-bit I/O port with the same function as port P0.
P71/SOUT2
P72/SCLK2
P70–P75 : CMOS compatible input level or TTL in-
put level
P76, P77 : CMOS compatible input level or •Serial I/O2 function pin
P73/SRDY2
/INT21
2
SMBUS input level in the I C-BUS inter-
•Interrupt input pin
I/O port P7
face function, N-channel open-drain
P74/INT31
P75/INT41
P76/SDA
P77/SCL
output structure
•Interrupt input pin
•Regardless of input or output port, P70 to P75 can
be input every pin level.
2
•I C-BUS interface function pin
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
P80/DQ0–
P87/DQ7
I/O port P8
•Bus interface function pin
•CMOS 3-state output structure.
•CMOS compatible input level or TTL input level in
the bus interface function.
6
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
M3886
7
M
8 A- XXX HP
Product name
Package type
HP : 80P6Q-A
GP : 80P6S-A
FS : 80D0
ROM number
Omitted in the one time PROM version shipped in blank,
the EPROM version and the flash memory version.
A– : High-speed version
– is omitted in the One Time PROM version shipped in blank,
the EPROM version and the flash memory version.
ROM/PROM size
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved
areas ; they cannot be used.
However, they can be programmed or erased in the EPROM
version and the flash memory version, so that the users can
use them.
Memory type
M
E
F
: Mask ROM version
: EPROM or One Time PROM version
: Flash memory version
RAM size
0: 192 bytes
1: 256 bytes
2: 384 bytes
3: 512 bytes
4: 640 bytes
5: 768 bytes
6: 896 bytes
7: 1024 bytes
8: 1536 bytes
9: 2048 bytes
Fig. 5 Part numbering
7
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 3886 group as follows.
80P6Q-A .................................. 0.5 mm-pitch plastic molded LQFP
80P6S-A ................................... 0.65mm pitch plastic molded QFP
80D0 ....................... 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, EPROM and flash
memory version.
The pin number and the position of the function pin may change
by the kind of package.
Memory Size
ROM size ........................................................... 32 K to 60 K bytes
RAM size .......................................................... 1024 to 2048 bytes
Memory Expansion
ROM size (bytes)
: Mass production
ROM
external
M38869FFA/MFA
M38869MCA
60K
48K
32K
28K
24K
20K
16K
12K
8K
M38869M8A
M38867E8A/M8A
384
512
640
768
896
1024
1152
1280
1408
1536
2048
3072
4032
RAM size (bytes)
Fig. 6 Memory expansion plan
Currently products are listed below.
As of Jan. 2000
Table 3 Support products
(P) ROM size (bytes)
Product name
RAM size (bytes)
1024
Package
80P6Q-A
Remarks
ROM size for User in (
)
M38867M8A-XXXHP
M38867E8A-XXXHP
M38867E8AHP
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
32768 (32638)
M38867E8AFS
80D0
M38869M8A-XXXHP
M38869M8A-XXXGP
M38869MCA-XXXHP
M38869MCA-XXXGP
M38869MFA-XXXHP
M38869MFA-XXXGP
M38869FFAHP
80P6Q-A
80P6S-A
80P6Q-A
80P6S-A
80P6Q-A
80P6S-A
80P6Q-A
80P6S-A
49152 (19022)
61440 (61310)
Mask ROM version
2048
Flash memory version
M38869FFAGP
8
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3886 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, the
processor mode bits specifying the chip operation mode, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0
1
0
1
: Single-chip mode
: Memory expansion mode (Note)
: Microprocessor mode (Note)
: Not available
Stack page selection bit
0
1
: 0 page
: 1 page
Reserved
(Do not write “0” to this bit when using
XCIN–XCOUT oscillation function.)
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0
0
1
1
0
1
0
1
: φ = f(XIN)/2 (high-speed mode)
: φ = f(XIN)/8 (middle-speed mode)
: φ = f(XCIN)/2 (low-speed mode)
: Not available
Note: This mode is not available for M38869M8A/MCA/MFA and the flash memory version.
Fig. 7 Structure of CPU mode register
9
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Interrupt Vector Area
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
RAM
addressing mode.
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special Page
Access to this area with only 2 bytes is possible in the special
ROM
page addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs. Pro-
gram/Erase of the reserved ROM area is possible in the EPROM
version and the flash memory version
RAM area
Address
XXXX16
RAM size
(bytes)
000016
SFR area
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
010016
RAM
XXXX16
Not used
SFR area (Note 1)
0FFE16
0FFF16
YYYY16
ZZZZ16
ROM area
Reserved ROM area
(Note 2) (128 bytes)
Address
YYYY16
Address
ZZZZ16
ROM size
(bytes)
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
FFFE16
FFFF16
Reserved ROM area
(Note 2)
Notes 1: This area is SFR in M38869FFA.
This area is Reserved in M38869MFA/MCA/M8A.
This area is not used in M38867M8A/E8A.
2: This area is usable in EPROM version and flash memory version.
Fig. 8 Memory map diagram
10
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0 (P0)
Prescaler 12 (PRE12)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
002016
002116
002216
002316
002416
002516
002616
002716
Port P0 direction register (P0D)
Port P1 (P1)
Timer 1 (T1)
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Timer Y (TY)
Port P3 direction register (P3D)
Port P4 (P4)
002816 Data bas buffer register 0 (DBB0)
002916 Data bas buffer status register 0 (DBBSTS0)
002A16 Data bas buffer control register (DBBCON)
002B16 Data bas buffer register 1 (DBB1)
002C16 Data bas buffer status register 1 (DBBSTS1)
002D16 Comparator data register (CMPD)
002E16 Port control register 1 (PCTL1)
002F16 Port control register 2 (PCTL2)
003016 PWM0H register (PWM0H)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)/Port P4 input register (P4I)
003116 PWM0L register (PWM0L)
Port P8 direction register (P8D)/Port P7 input register (P7I)
2
003216 PWM1H register (PWM1H)
I C data shift register (S0)
2
003316 PWM1L register (PWM1L)
I C address register (S0D)
2
AD/DA control register (ADCON)
A-D conversion register 1 (AD1)
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
A-D conversion register 2 (AD2)
003416
003516
003616
003716
003816
I C status register (S1)
2
I C control register (S1D)
2
I C clock control register (S2)
2
I C start/stop condition control register (S2D)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
003916 Interrupt source selection register (INTSEL)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
003A16
003B16
003C16
003D16
003E16
003F16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Serial I/O2 control register (SIO2CON)
001E16 Watchdog timer control register (WDTCON)
Serial I/O2 register (SIO2)
001F16
Flash memory control register (FCON)
Flash command register (FCMD)
(Note)
(Note)
0FFE16
0FFF16
Note: Flash memory version only
Fig. 9 Memory map of special function register (SFR)
11
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
output latch is written to and the pin remains floating.
When the P8 function select bit of the port control register 2 (ad-
dress 002F16) is set to “1”, read from address 001016 becomes
the port P4 input register, and read from address 001116 becomes
the port P7 input register.
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
As the particular function, value of P42 to P46 pins and P70 to P75
pins can be read regardless of setting direction registers, by read-
ing the port P4 input register (address 001016) or the port P7 input
register (address 001116) respectively.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
Table 4 I/O port function (1)
Pin
Name
Input/Output
Related SFRs
Ref.No.
(1)
I/O Structure
Non-Port Function
CPU mode register
Port control register 1
Serial I/O2 control
register
Address low-order byte
output
Analog comparator
power source input pin
P00/P3REF
CMOS compatible
input level
CMOS 3-state output
or N-channel open-
drain output
Port P0
Address low-order byte
output
P01–P07
CPU mode register
Port control register 1
(2)
(3)
Address high-order
byte output
P10–P17
P20–P27
Port P1
Port P2
Data bus I/O
CPU mode register
Control signal I/O
PWM output
Key-on wake up input
Comparator input
CPU mode register
Port control register 1
AD/DA control register
(4)
(5)
P30/PWM00
P31/PWM10
CMOS compatible
input level
Port P3
Control signal I/O
Key-on wake up input
Comparator input
CMOS 3-state output
CPU mode register
Port control register 1
P32–P37
(6)
(7)
(8)
Sub-clock generating
circuit
P40/XCOUT
P41/XCIN
CPU mode register
P42/INT0/
OBF00
P43/INT1/
OBF01
Interrupt edge selection
register
Port control register 2
External interrupt input
Bus interface function
I/O
(9)
(10)
Input/output,
individual bits
CMOS compatible
input level or TTL
input level
CMOS 3-state output
or N-channel open-
drain output
Serial I/O1 control
register
Port control register 2
Serial I/O1 function in-
put
(11)
(12)
P44/RXD
P45/TXD
Serial I/O1 control
register
UART control register
Port control register 2
Serial I/O1 function out-
put
Port P4
Serial I/O1 control
register
Data bus buffer control
register
Serial I/O1 function I/O
Bus interface function
output
P46/SCLK1
/OBF10
(13)
(14)
Port control register 2
CMOS compatible
input level
Serial I/O1 control
register
Data bus buffer control
register
Serial I/O1 function out-
put
Bus interface function
input
CMOS 3-state output
(when selecting bus
interface function)
CMOS compatible
input level or TTL
input level
P47/SRDY1
/S1
12
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 5 I/O port function (2)
Name
Related SFRs
Bus interface function Data bus buffer control
Pin
Non-Port Function
Input/Output
I/O Format
Ref.No.
(15)
CMOS compatible
input level
P50/A0
input
register
CMOS 3-state output
(when selecting bus
interface function)
CMOS compatible
input level or TTL
input level
P51/INT20
/S0
Interrupt edge selection
register
Data bus buffer control
register
External interrupt input
Bus interface function
input
P52/INT30
/R
(16)
(17)
Port P5
P53/INT40
/W
Timer X, timer Y func-
tion I/O
P54/CNTR0
P55/CNTR1
Timer XY mode register
P56/DA1/
PWM01
CMOS compatible
input level
CMOS 3-state output
D-A converter output
PWM output
AD/DA control register
UART control register
(18)
(19)
P57/DA2/
PWM11
P60/AN0–
P67/AN7
A-D converter input
(20)
Port P6
AD/DA control register
P70/SIN2
(21)
(22)
(23)
Serial I/O2 control
register
Port control register 2
Serial I/O2 function I/O
P71/SOUT2
P72/SCLK2
Input/output,
individual bits
CMOS compatible
input level or TTL
input level
N-channel open-drain
output
Serial I/O2 function out-
put
Bus interface function
input
Serial I/O2 control
register
Port control register 2
P73/SRDY2/
INT21
(24)
(25)
Interrupt edge selection
register
Port control register 2
P74/INT31
P75/INT41
External interrupt input
Port P7
CMOS compatible
input level
N-channel open-drain
output
(when selecting I C-
BUS interface
function)
P76/SDA
P77/SCL
2
2
I C-BUS interface func-
(26)
(27)
2
I C control register
tion I/O
CMOS compatible
input level or SMBUS
input level
CMOS compatible
input level
CMOS 3-state output
(when selecting bus
interface function)
Bus interface function
I/O
Data bus buffer control
register
P80/DQ0–
P87/DQ7
(28)
Port P8
CMOS compatible
input level or TTL
input level
Notes1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer
to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
13
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P0
0
(2) Ports P01–P07,P1
P00–P03 output
structure selection bit
P00–P03,
P04–P07,
P10–P13,
Direction
register
P14–P17 output structure
selection bits
Direction
register
Data bus
Port latch
Data bus
Port latch
Comparator reference power source input
Comparator reference input
pin select bit
(3) Port P2
(4) Port P3
0
P30–P33 pull-up control bit
Direction
register
PWM0 output pin selection bit
PWM0 enable bit
Direction
register
Data bus
Port latch
Data bus
Port latch
PWM00 output
Comparator
Key-on wake-up
input
(6) Ports P3
2
–P3
7
(5) Port P3
1
P30–P33 pull-up control bit
PWM1 output pin selection bit
PWM1 enable bit
P30–P33,
P34–P37 pull-up control bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
PWM10 output
Comparator
Key-on wake-up
input
Comparator
input
Key-on wake-up
(7) Port P4
0
(8) Port P41
Port XC switch bit
Port XC switch bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Oscillator
Sub-clock generating circuit input
Port P41
Port XC switch bit
Fig. 10 Port block diagram (1)
14
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Port P4
2
(10) Port P4
3
P4 output structure selection bit
P4 output structure selection bit
OBF00 output enable bit
OBF01 output enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
✻1
✻2
✻1
✻2
OBF01 output
OBF00 output
INT1 interrupt input
INT0 interrupt input
(11) Port P4
4
(12) Port P45
P4 output structure selection bit
P45/TXD P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Serial I/O1 enable bit
Receive enable bit
Direction
Direction
register
register
Data bus
Port latch
Port latch
Data bus
✻1
✻1
✻2
✻2
Serial I/O1 output
Serial I/O1 input
(13) Port P4
6
(14) Port P47
Serial I/O1
synchronous clock selection bit
P4 output structure selection bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Serial I/O1 enable bit
S
RDY1 output enable bit
Serial I/O1 mode selection bit
Data bus buffer function
selection bit
Serial I/O1 enable bit
OBF10 output enable bit
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
✻1
✻2
✻3
Serial I/O1 ready output
S1 input
Data bus buffer function
selection bit
Serial I/O1 clock output
OBF10 output
Serial I/O1 external clock input
(15) Port P5
0
(16) Ports P51,P52,P53
Data bus buffer enable bit
Data bus buffer enable bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
✻3
A
0
input
INT20, INT30, INT40 interrupt input
,R,W input
Data bus buffer
enable bit
✻3
S
0
Data bus buffer
enable bit
✻1. The input level can be switched between CMOS compatible input level and TTL level by the P4 input level selection bit of the port control
register 2 (address 002F16).
✻2. The input level can be switched between CMOS compatible input level and TTL level by the P4 input level selection bit of the port control
register 2 (address 002F16).
The port P8 and port P4 input register can be switched by the P8 function selection bit of the port control register 2 (address 002F16).
✻3. The input level can be switched between CMOS compatible input level and TTL level by the input level selection bit of the data bus buffer
control register (address 002A16).
Fig. 11 Port block diagram (2)
15
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(17) Ports P54,P55
(18) Port P56
Direction
register
PWM
0
output pin selection bit
PWM enable bit
0
Direction
register
Data bus
Port latch
Data bus
Port latch
Pulse output mode
Timer output
CNTR0,CNTR1 interrupt input
PWM01 output
D-A converter output
D-A
1
output enable bit
(19) Port P5
7
(20) Port P6
PWM
1
output pin selection bit
PWM enable bit
Direction
register
1
Direction
register
Data bus
Port latch
Data bus
Port latch
A-D converter input
Analog input pin selection bit
PWM11 output
D-A converter output
D-A2 output enable bit
(21) Port P7
0
(22) Port P71
Serial IO/2 transmit completion signal
Serial I/O2 port selection bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
✻4
✻5
✻4
✻5
Serial I/O2 input
Serial I/O2 output
(23) Port P7
2
(24) Port P73
Serial I/O2 synchronization
clock selection bit
Serial I/O2 port selection bit
S
RDY2 output enable bit
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
✻4
✻5
✻4
✻5
Serial I/O2 ready output
INT21 interrupt input
Serial I/O2 clock output
Serial I/O2
external clock input
✻4. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port
control register 2 (address 002F16).
✻5. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port
control register 2 (address 002F16).
The port P8 direction register and port P7 input register can be switched by the P8 function selection bit of the port control register 2
(address 002F16).
Fig. 12 Port block diagram (3)
16
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(25) Ports P74,P7
5
(26) Port P76
2
I C-BUS interface
enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
✻4
✻5
INT31,INT41 interrupt input
S
DA output
✻6
S
DA input
(27) Port P7
7
(28) Port P8
S
S
0
1
2
R
I C-BUS interface
enable bit
Data bus buffer enable bit
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
Output buffer 0
Status register 0
SCL output
✻6
S
CL input
Output buffer 1
Status register 1
✻3
✻3
Input buffer 0
Input buffer 1
2
✻6.
The input level can be switched between CMOS compatible input level and SMBUS level by the I C-BUS interface pin input
selection bit of the I C control register (address 001516).
2
Fig. 13 Port block diagram (4)
17
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Port control register 1
(PCTL1: address 002E16
)
P00–P03 output structure selection bit
0: CMOS
1: N-channel open-drain
P04–P07 output structure selection bit
0: CMOS
1: N-channel open-drain
P10–P13 output structure selection bit
0: CMOS
1: N-channel open-drain
P14–P17 output structure selection bit
0: CMOS
1: N-channel open-drain
P30–P33 pull-up control bit
0: No pull-up
1: Pull-up
P34–P37 pull-up control bit
0: No pull-up
1: Pull-up
PWM0 enable bit
0: PWM
1: PWM
0
output disabled
output enabled
0
PWM1 enable bit
0: PWM
1: PWM
1
output disabled
output enabled
1
b7
b0
Port control register 2
(PCTL2: address 002F16
)
P4 input level selection bit (P4
2
–P4
6
)
)
0: CMOS level input
1: TTL level input
P7 input level selection bit (P7
0
–P7
5
0: CMOS level input
1: TTL level input
P4 output structure selection bit (P42, P43, P44, P46)
0: CMOS
1: N-channel open-drain
P8 function selection bit
0: Port P8/Port P8 direction register
1: Port P4 input register/Port P7 input register
INT , INT , INT interrupt switch bit
2
3
4
0: INT20, INT30, INT40 interrupt
1: INT21, INT31, INT41 interrupt
Timer Y count source selection bit
0: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
1: f(XCIN
)
Oscillation stabilizing time set after STP instruction released bit
0: Automatic set “0116” to timer 1 and “FF16” to prescaler 12
1: No automatic set
Port output P42/P43 clear function selection bit
0: Only software clear
1: Software clear and output data bus buffer 0 reading
(system bus side)
Fig. 14 Structure of port I/O related register
18
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupt Source Selection
Interrupts occur by 16 sources among 21 sources: nine external,
Any of the following interrupt sources can be selected by the inter-
rupt source selection register (address 003916).
1. INT0 or Input buffer full
eleven internal, and one software.
Interrupt Control
2. INT1 or Output buffer empty
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
3. Serial I/O1 transmission or SCLSDA
4. CNTR0 or SCLSDA
2
5. Serial I/O2 or I C
2
6. INT2 or I C
7. CNTR1 or Key-on wake-up
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
8. A-D conversion or Key-on wake-up
External Interrupt Pin Selection
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
The occurrence sources of the external interrupt INT2, INT3, and
INT4 can be selected from either input from INT20, INT30, INT40
pin, or input from INT21, INT31, INT41 pin by the INT2, INT3, INT4
interrupt switch bit (bit 4 of address 002F16).
When several interrupts occur at the same time, the interrupts are
received according to priority.
■ Notes
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
When setting of the following register or bit is changed, the inter-
rupt request bit may be set to “1.”
matically performed:
• Interrupt edge selection register (address 003A16)
• Interrupt source selection register (address 003916)
• INT2, INT3, INT4 interrupt switch bit of Port control register 2 (bit
4 of address 002F16)
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
Accept the interrupt after clearing the interrupt request bit to “0”
after interrupt is disabled and the above register or bit is set.
3. The interrupt jump destination address is read from the vector
table into the program counter.
19
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Remarks
Non-maskable
Interrupt Source
Reset (Note 2)
INT0
Priority
1
High
Low
FFFD16
FFFC16
At reset
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT0 input
2
FFFB16
FFF916
FFFA16
FFF816
Input buffer full
(IBF)
At input data bus buffer writing
At detection of either rising or External interrupt
falling edge of INT1 input
INT1
(active edge selectable)
3
Output buffer
empty (OBE)
At output data bus buffer read-
ing
At completion of serial I/O1 data
reception
Serial I/O1
reception
4
5
FFF716
FFF516
FFF616
FFF416
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
Serial I/O1
transmission
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of SCL or SDA
SCL, SDA
Timer X
Timer Y
Timer 1
Timer 2
6
7
8
9
FFF316
FFF116
FFEF16
FFED16
FFF216
FFF016
FFEE16
FFEC16
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
STP release timer underflow
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
CNTR0
10
FFEB16
FFEA16
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of SCL or SDA
SCL, SDA
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
CNTR1
11
12
13
FFE916
FFE716
FFE516
FFE816
FFE616
FFE416
At falling of port P3 (at input) in-
put logical level AND
External interrupt (falling valid)
Valid when serial I/O2 is selected
Key-on wake-up
Serial I/O2
At completion of serial I/O2 data
transfer
2
At completion of data transfer
I C
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
INT2
2
At completion of data transfer
I C
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT3 input
INT3
14
15
FFE316
FFE116
FFE216
FFE016
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT4 input
INT4
At completion of A-D conversion
A-D converter
16
17
FFDF16
FFDD16
FFDE16
FFDC16
At falling of port P3 (at input) in-
put logical level AND
External interrupt (falling valid)
Non-maskable software interrupt
Key-on wake-up
BRK instruction
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
20
MITSUBISHI MICROCOMPUTERS
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Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 15 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
0
active edge selection bit
active edge selection bit
1
Not used (returns “0” when read)
INT
INT
INT
2
3
4
active edge selection bit
active edge selection bit
active edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
b7
b0
b7 b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
)
(IREQ1 : address 003C16
)
INT
bit
0
/input buffer full interrupt request
CNTR
0
/SCL, SDA interrupt request bit
/key-on wake-up interrupt
CNTR
1
INT
1/output buffer empty interrupt
request bit
2
request bit
Serial I/O2/I C interrupt request bit
2
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit/SCL, SDA interrupt
request bit
INT
INT
INT
2/I C interrupt request bit
3 interrupt request bit
4 interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
AD converter/key-on wake-up interrupt
request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 2
Interrupt control register 1
(ICON2 : address 003F16
)
(ICON1 : address 003E16
)
CNTR
0
/SCL, SDA interrupt enable bit
/key-on wake-up interrupt
INT
INT
0
1
/input buffer full interrupt enable bit
/output buffer empty interrupt
CNTR
1
enable bit
enable bit
2
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit/SCL, SDA interrupt
enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O2/I C interrupt enable bit
2
INT
INT
INT
2/I C interrupt enable bit
3 interrupt enable bit
4 interrupt enable bit
AD converter/key-on wake-up interrupt
enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers (1)
21
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Interrupt source selection register
(INTSEL: address 003916)
INT0/input buffer full interrupt source selection bit
0 : INT0 interrupt
1 : Input buffer full interrupt
INT1/output buffer empty interrupt source selection bit
0 : INT1 interrupt
1 : Output buffer empty interrupt
Serial I/O1 transmit/SCL,SDA interrupt source selection bit
0 : Serial I/O1 transmit interrupt
1 : SCL,SDA interrupt
(Do not write “1” to these bits simultaneously.)
(Do not write “1” to these bits simultaneously.)
CNTR0/SCL,SDA interrupt source selection bit
0 : CNTR0 interrupt
1 : SCL,SDA interrupt
2
Serial I/O2/I C interrupt source selection bit
0 : Serial I/O2 interrupt
2
1 : I C interrupt
2
INT2/I C interrupt source selection bit
0 : INT2 interrupt
2
1 : I C interrupt
CNTR1/key-on wake-up interrupt source selection bit
0 : CNTR1 interrupt
1 : Key-on wake-up interrupt
(Do not write “1” to these bits simultaneously.)
AD converter/key-on wake-up interrupt source selection bit
0 : A-D converter interrupt
1 : Key-on wake-up interrupt
Fig. 17 Structure of interrupt-related registers (2)
22
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
“0”. An example of using a key input interrupt is shown in Figure
18, where an interrupt request is generated by pressing one of the
keys consisted as an active-low key matrix which inputs to ports
P30–P33.
Key Input Interrupt (Key-on Wake Up)
A Key input interrupt request is generated by applying “L” level to
any pin of port P3 that have been set to input mode. In other
words, it is generated when AND of input level goes from “1” to
Port PXx
“L” level output
Port control register 1
Bit 5 = “1”
Port P37
direction register = “1”
Port P37
latch
Key input interrupt request
✻
✻
✻✻
✻✻
✻✻
✻✻
P37 output
P36 output
Port P36
direction register = “1”
Port P36
latch
Port P35
direction register = “1”
✻
✻
Port P35
latch
P35 output
Port P34
direction register = “1”
Port P34
latch
P34 output
P33 input
Port control register 1
Port P33
direction register = “0”
Bit 4= “1”
Port P3
Input reading circuit
Comparator circuit
✻
✻
✻✻
Port P33
latch
Port P32
direction register = “0”
✻✻
✻✻
✻✻
Port P32
latch
P32 input
P31 input
P30 input
Port P31
direction register = “0”
✻
Port P31
latch
Port P30
direction register = “0”
✻
Port P30
latch
✻P-channel transistor for pull-up
✻✻CMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P3 block diagram
23
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
Timer 1 and Timer 2
The 3886 group has four timers: timer X, timer Y, timer 1, and
The count source of prescaler 12 is the oscillation frequency di-
vided by 16. The output of prescaler 12 is counted by timer 1 and
timer 2, and a timer underflow sets the interrupt request bit.
timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an un-
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts f(XIN)/16.
(2) Pulse Output Mode
Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of
the timer reach “0016”, the signal output from the CNTR0 (or
CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge se-
lection bit is “0”, output begins at “ H”.
b0
b7
Timer XY mode register
(TM : address 002316
)
Timer X operating mode bit
b1b0
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P54 ( or port P55) direction register to out-
put mode.
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
(3) Event Counter Mode
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bit
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
(4) Pulse Width Measurement Mode
CNTR1 active edge selection bit
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts f(XIN)/16 while the CNTR0 (or CNTR1) pin is at “H”. If the
CNTR0 (or CNTR1) active edge selection bit is “1”, the timer
counts while the CNTR0 (or CNTR1) pin is at “L”.
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer overflows.
Fig. 19 Structure of timer XY mode register
The count source for timer Y in the timer mode or the pulse output
mode can be selected from either f(XIN)/16 or f(XCIN) by the timer
Y count source selection bit of the port control register 2 (bit 5 of
address 002F16).
24
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
Divider
1/16
Oscillator
f(XIN
Prescaler X latch (8)
Timer X latch (8)
)
Pulse width
measurement
mode
Timer mode
Pulse output mode
(f(XCIN) in low-speed mode)
To timer X interrupt
request bit
Prescaler X (8)
Timer X count stop bit
Timer X (8)
CNTR0 active
Event
counter
mode
edge selection
P54/CNTR0
bit
“0”
To CNTR
0 interrupt
request bit
“1”
CNTR0 active
“1”
“0”
edge selection
bit
Q
Q
T
Toggle flip-flop
R
Timer X latch write pulse
Pulse output mode
Port P5
latch
4
Port P5
direction register
4
Pulse output mode
Data bus
Oscillator
Divider
Timer Y count source
selection bit
“0”
f(XIN
)
1/16
(f(XCIN) in low-speed mode)
Oscillator
Prescaler Y latch (8)
Timer Y latch (8)
Timer Y (8)
Pulse width
measure-
“1”
Timer mode
f(XCIN
)
ment mode Pulse output mode
To timer Y interrupt
request bit
Prescaler Y (8)
CNTR
edge selection
1 active
Event
counter
mode
Timer Y count stop bit
P55/CNTR1
bit
“0”
“1”
To CNTR
1 interrupt
request bit
CNTR1 active
“1”
“0”
edge selection
bit
Q
Q
T
Toggle flip-flop
R
Port P55
latch
Timer Y latch write pulse
Pulse output mode
Port P5
5
direction register
Pulse output mode
Data bus
Prescaler 12 latch (8)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Oscillator
f(XIN
(f(XCIN) in low-speed mode)
Divider
1/16
)
To timer 2 interrupt
request bit
To timer 1 interrupt
request bit
Fig. 20 Block diagram of timer X, timer Y, timer 1, and timer 2
25
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A16) to “1”.
SERIAL I/O
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Data bus
Serial I/O1 control register
Receive buffer full flag (RBF)
Address 001A16
Address 001816
Receive buffer register
Receive shift register
Receive interrupt request (RI)
P44/RXD
Shift clock
Clock control circuit
P46/SCLK1/OBF10
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN)
Baud rate generator
Address 001C16
1/4
(f(XCIN) in low-speed mode)
1/4
Falling-edge detector
Clock control circuit
P47/SRDY1/S1
F/F
Shift clock
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD
Transmit shift register
Transmit buffer register
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 21 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
D
0
0
D
1
D
2
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
D
D1
D
D
D
D
D
D
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 22 Operation of clock synchronous serial I/O1 function
26
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 001816
Receive buffer register
Serial I/O1 control register Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Character length selection bit
7 bits
P44/RXD
ST detector
Receive shift register
1/16
8 bits
UART control register
Address 001B16
PE FE SP detector
Clock control circuit
Serial I/O1 synchronous clock selection bit
P46/SCLK1/OBF10
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN
)
Baud rate generator
Address 001C16
(f(XCIN) in low-speed mode)
1/4
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P45/T
XD
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Address 001816
Address 001916
Serial I/O1 status register
Data bus
Fig. 23 Block diagram of UART serial I/O1
27
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
TBE=0
D1
TSC=1✽
SP
TBE=1
Serial output TXD
ST
D0
ST
D0
D1
SP
✽ Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
D1
RBF=1
SP
RBF=1
SP
ST
Serial input RXD
D0
D1
ST
D0
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 24 Operation of UART serial I/O1 function
[Serial I/O1 Control Register (SIO1CON)]
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is al-
ways valid and sets the output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
[Serial I/O1 Status Register (SIO1STS)]
001916
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
28
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b0
b7
Serial I/O1 status register
(SIO1STS : address 001916
Serial I/O1 control register
(SIO1CON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
0: P4
1: P4
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin
pin operates as SRDY1 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O1 enable bit (SIOE)
0: Serial I/O disabled
b7
b0
(pins P4
1: Serial I/O enabled
(pins P4 to P4 operate as serial I/O pins)
4 to P47 operate as ordinary I/O pins)
UART control register
(UARTCON : address 001B16
)
4
7
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 25 Structure of serial I/O1 control registers
29
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
b7
b0
Serial I/O2 control register
The serial I/O2 function can be used only for clock synchronous
(SIO2CON : address 001D16)
serial I/O.
Internal synchronous clock selection bits
For clock synchronous serial I/O the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
b2 b1 b0
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode)
1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
[Serial I/O2 Control Register (SIO2CON)]
001D16
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 signal output
The serial I/O2 control register contains seven bits which control
various serial I/O functions.
SRDY2 output enable bit
0: I/O port
1: SRDY2 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
Comparator reference input selection bit
0: P00/P3REF input
1: Reference input fixed
Fig. 26 Structure of serial I/O2 control register
Internal synchronous
clock selection bits
1/8
X
CIN
1/16
Data bus
1/32
“10”
Main clock divide ratio
selection bits (Note)
1/64
“00”
“01”
1/128
1/256
XIN
P7
3
latch
Serial I/O2 synchronous
clock selection bit
“0”
“1”
P73/SRDY2
S
RDY2
Synchronization
circuit
/INT21
“1”
S
RDY2 output enable bit
“0”
External clock
P72 latch
“0”
P72
/SCLK2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
“1”
Serial I/O2 port selection bit
P71 latch
“0”
P7
1
/SOUT2
/SIN2
“1”
Serial I/O2 port selection bit
Serial I/O2 register (8)
P70
Note:
These are assigned to bits 7 and 6 of the CPU mode register (address 003B16).
These bits select any of the high-speed mode, the middle-speed mode, and the low-speed mode.
Fig. 27 Block diagram of serial I/O2 function
30
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output SOUT2
Serial I/O2 input SIN2
D2
D0
D1
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial
I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion.
Fig. 28 Timing of serial I/O2 function
31
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The following explanation assumes f(XIN) = 8 MHz.
PULSE WIDTH MODULATION (PWM)
OUTPUT CIRCUIT
The 3886 group has two PWM output circuits, PWM0 and PWM1,
with 14-bit resolution respectively. These can operate indepen-
dently. When the oscillation frequency XIN is 10 MHz, the
minimum resolution bit width is 200 ns and the cycle period is
3276.8 µs. The PWM timing generator supplies a PWM control
signal based on a signal that is the frequency of the XIN clock.
Data Bus
Set to “1”
at write
PWM0L register (address 003116)
bit 7
bit 5
bit 0
bit 0
bit 7
PWM0H register
(address 003016)
PWM0 latch (14 bits)
MSB
LSB
14
P30 latch
P30/PWM00
PWM0
14-bit PWM0 circuit
PWM0 enable bit
PWM0 output selection bit
PWM0 enable bit
(64 µs period)
PWM0
f(XIN)
(8MHz)
1/2
(4MHz)
timing
P30 direction register
generator
(4096 µs period)
P56 latch
P56/DA1/PWM01
PWM0 enable bit
PWM0 output selection bit
PWM0 enable bit
P56 direction register
Fig. 29 PWM block diagram (PWM0)
32
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
mum resolution (250 ns).
Data Setup (PWM0)
“H” or “L” of the bit in the ADD part shown in Figure 30 is added to
this “H” duration by the contents of the low-order 6-bit data accord-
ing to the rule in Table 7.
The PWM0 output pin also functions as port P30 or P56. The
PWM0 output pin is selected from either P30/PWM00 or
P56/PWM01 by bit 4 of the AD/DA control register (address
003416).
That is, only in the sub-period tm shown by Table 7 in the PWM
cycle period T = 64t, its “H” duration is lengthened to the minimum
resolution τ added to the length of other periods.
The PWM0 output becomes enabled state by setting bit 6 of the
port control register 1 (address 002E16). The high-order eight bits
of output data are set in the PWM0H register (address 003016)
and the low-order six bits are set in the PWM0L register (address
003116).
For example, if the high-order eight bits of the 14-bit data are 0316
and the low-order six bits are 0516, the length of the “H”-level out-
put in sub-periods t8, t24, t32, t40, and t56 is 4 τ, and its length is 3
τ in all other sub-periods.
PWM1 is set as the same way.
Time at the “H” level of each sub-period almost becomes equal,
because the time becomes length set in the high-order 8 bits or
becomes the value plus τ, and this sub-period t (= 64 µs, approxi-
mate 15.6 kHz) becomes cycle period approximately.
PWM Operation
The 14-bit PWM data is divided into the low-order six bits and the
high-order eight bits in the PWM latch.
The high-order eight bits of data determine how long an “H”-level
signal is output during each sub-period. There are 64 sub-periods
in each period, and each sub-period is 256 ✕ τ (64 µs) long. The
signal is “H” for a length equal to N times τ, where τ is the mini-
Transfer From Register to Latch
Data written to the PWML register is transferred to the PWM latch
at each PWM period (every 4096 µs), and data written to the
PWMH register is transferred to the PWM latch at each sub-period
(every 64 µs). The signal which is output to the PWM output pin is
corresponding to the contents of this latch. When the PWML regis-
ter is read, the latch contents are read. However, bit 7 of the
PWML register indicates whether the transfer to the PWM latch is
completed; the transfer is completed when bit 7 is “0” and it is not
done when bit 7 is “1.”
Table 7 Relationship between low-order 6 bits of data and
period set by the ADD bit
Low-order 6 bits of data (PWML)
Sub-periods tm Lengthened (m=0 to 63)
0 0 0 0 0 L0SB
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
None
m=32
m=16, 48
m=8, 24, 40, 56
m=4, 12, 20, 28, 36, 44, 52, 60
m=2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m=1, 3, 5, 7, ................................................ ,57, 59, 61, 63
4096 µs
64 µs
m=0
64 µs
64 µs
64 µs
64 µs
m=63
m=8
m=7
m=9
15.75 µs
15.75 µs
15.75 µs
15.75 µs
16.0 µs
15.75 µs
15.75 µs
Pulse width modulation register H :
Pulse width modulation register L :
00111111
000101
Sub-periods where “H” pulse width is 16.0 µs :
Sub-periods where “H” pulse width is 15.75 µs :
m = 8, 24, 32, 40, 56
m = all other values
Fig. 30 PWM timing
33
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data 6A16 stored at address 003016
6A16
Data 7B16 stored at address 003016
7B16
PWM0H
register
5916
Data 2416 stored at address 003116
1316 A416
Bit 7 cleared after transfer
2416
Data 3516 stored at address 003116
3516
PWM0L
register
Transfer from register to latch
1AA416
Transfer from register to latch
1EF516
B516
1EE416
PWM0 latch
(14bits)
165316
1A9316
1AA416
When bit 7 of PWM0L is 0, transfer
from register to latch is disabled.
T = 4096 µs
(64 ✕ 64 µs)
t = 64 µs
Example 1
6A 6B 6A 6B 6A 6B 6A 6B 6A 6B 6B 6B 6A 6B 6A 6B 6A 6B 6A
6B 6A 6B 6A 6B 6A 6B 6A
PWM
0
output
1
low-order
H
5
5
5
5
5
2
5
5
5
5
5
5
5
5
5
6-bit output:
L
6A16, 2416
6B16 ·············· 36 times
(107)
6A16 ············· 28 times
(106)
106 ✕ 64 + 36
Example 2
6A 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A
6A 6B 6A 6B 6A 6B 6A 6A
PWM0 output
low-order
6-bit output:
4
3
4
4
3
4
4
3
4
H
L
6A16 ······· 40 times
6A16, 1816
6B16 ·············· 24 times
106 ✕ 64 + 24
t = 64 µs
(256 ✕ 0.25 µs)
Minimum resolution bit width τ = 0.25 µs
·······
·······
·······
PWM output
6B 6A 69 68 67
02 01
6A 69 68 67
02 01
2
ADD
ADD
02 01 00 FF FE FD FC
8-bit
counter
·······
·······
·······
02 01 00 FF FE FD FC
97 96 95
97 96 95
The ADD
H duration length specified by PWM0H
portions with
additional τ are
determined by
PWML.
256 τ (64 µs), fixed
Fig. 31 14-bit PWM timing (PWM0)
34
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The selection of either the single data bus buffer mode, which
uses 1 byte: data bus buffer 0 only, or the double data bus buffer
mode, which uses 2 bytes: data bus buffer 0 and data bus buffer
1, is performed by bit 1 (data bus buffer function selection bit) of
the data bus buffer control register (address 002A16). Port P47 be-
comes S1 input in the double data bus buffer mode. When data is
written from the host CPU side, an input buffer full interrupt oc-
curs. When data is read from the host CPU, an output buffer
empty interrupt occurs. This microcomputer shares two input
buffer full interrupt requests and two output buffer empty interrupt
requests as shown in Figure 32, respectively.
BUS INTERFACE
The 3886 group has a 2-byte bus interface function which is al-
most functionally equal to MELPS8-41 series and the control
signal from the host CPU side can operate it (slave mode).
It is possible to connect the 3886 group with the RD and WR
separated CPU bus directly. Figure 34 shows the block diagram of
the bus interface function.
The data bus buffer function I/O pins (P42, P43, P46, P47, P50–
P53, P8) also function as the normal digital port I/O pins. When bit
0 (data bus buffer enable bit) of the data bus buffer control regis-
ter (address 002A16) is “0,” these pins become the normal digital
port I/O pins. When it is “1,” these bits become the data bus buffer
function I/O pins.
One-shot pulse
generating circuit
Input buffer
full flag 0 IBF
Rising edge
detection circuit
0
1
Input buffer full interrupt
request signal IBF
One-shot pulse
generating circuit
Rising edge
detection circuit
Input buffer
full flag 1 IBF
Output buffer
full flag 0
One-shot pulse
generating circuit
Rising edge
detection circuit
OBF
OBF
0
1
OBE
0
Output buffer empty interrupt
request signal OBE
Output buffer
full flag 1
One-shot pulse
generating circuit
Rising edge
detection circuit
OBE
1
IBF
0
1
IBF
IBF
Interrupt request is set at this rising edge
OBF
OBE0)
0
(
OBF
OBE1)
1
(
OBE
Interrupt request is set at this rising edge
Fig. 32 Interrupt request circuit of data bus buffer
35
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b0
b7
Data bus buffer control register
(DBBCON : address 002A16
)
Data bus buffer enable bit
0 : P50–P53, P8 I/O port
1 : Data bus buffer enabled
Data bus buffer function selection bit
0 : Single data bus buffer mode (P4
7
functions as I/O port.)
functions S input.)
1 : Double data bus buffer mode (P4
OBF output selection bit
7
1
0
0 : OBF00 valid
1 : OBF01 valid
OBF00 output enable bit
0 : P4
1 : P4
2
functions as port I/O pin.
functions as OBF00 output pin.
2
OBF01 output enable bit
0 : P4
1 : P4
3
functions as port I/O pin.
functions as OBF01 output pin.
3
OBF10 output enable bit
0 : P4
1 : P4
6
functions as port I/O pin.
functions as OBF10 output pin.
6
Input level selection bit
0 : CMOS level input
1 : TTL level input
Reserved
Do not write “1” to this bit.
b0
b7
Data bus buffer status register 0
(DBBSTS0 : address 002916
)
Output buffer full flag 0 (OBF0)
0
1
: Buffer empty
: Buffer full
Input buffer full flag 0 (IBF0)
0
1
: Buffer empty
: Buffer full
User definable flag (U02
This flag can be defined by user freely.
A0 flag (A0
This flag indicates the condition of A0
when the IBF flag is set.
User definable flag (U04–U07
)
0
0)
0
status
0
)
This flag can be defined by user freely.
b0
b7
Data bus buffer status register 1
(DBBSTS1 : address 002C16
)
Output buffer full flag 1 (OBF1)
0
1
: Buffer empty
: Buffer full
Input buffer full flag 1 (IBF1)
0
1
: Buffer empty
: Buffer full
User definable flag (U12
This flag can be defined by user freely.
A0 flag (A0
This flag indicates the condition of A0
when the IBF flag is set.
User definable flag (U14–U17
This flag can be defined by user freely.
)
1
1)
1
status
1
)
Fig. 33 Structure of bus interface related register
36
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(Address 002A16
)
b7
b6
b5
b4
b
3
b2
b1
b0
P42/INT0/OBF00
P43/INT1/OBF01
P50/A0
P5
P5
P5
1
/INT20/S
/INT30/R
/INT40/W
0
2
3
(Address 002916
)
U
07
U
06
U
05
U
04 A0
0
U
02 IBF
0
OBF
0
P8
P8
P8
P8
P8
P8
P8
P8
0/DQ
1/DQ
2/DQ
3/DQ
4/DQ
5/DQ
6/DQ
7/DQ
0
1
2
3
4
5
6
7
Output data bus buffer 0
(Address 002816
)
WR
DBBSTS
0
Input data bus buffer 0
(Address 002816
)
DBB
0
RD
DBB
1
RD
Input data bus buffer 1
(Address 002B16
DBBSTS
1
WR
)
Output data bus buffer 1
(Address 002B16
)
U
17
U
16
U
15
U
14
A0
1
U12 IBF
1 OBF1
(Address 002C16
)
P47/SRDY1/S1
P46/SCLK1/OBF10
Fig. 34 Bus interface device block diagram
37
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Data Bus Buffer Status Register 0, 1
(DBBSTS0, DBBSTS1)] 002916, 002C16
The data bus buffer status register 0, 1 consist of eight bits.
Bits 0, 1, and 3 are read-only bits and indicate the condition of the
data bus buffer. Bits 2, 4, 5, 6, and 7 are user definable flags
which can be set by program, and can be read/written. This regis-
ter can be read from the host CPU when the A0 pin is set to “H”
only.
•Bit 0: Output buffer full flag OBF0, OBF1
When writing data to the output data bus buffer, these flags are
set to “1”. When reading the output data bus buffer from the host
CPU, these flags are cleared to “0”.
•Bit 1: Input buffer full flag IBF0, IBF1
When writing data from the host CPU to the input data bus
buffer, these flags are set to “1”. When reading the input data
bus buffer from the slave CPU side, these flags are cleared to
“0”.
•Bit 3: A0 flag A00, A01
When writing data from the host CPU to the input data bus
buffer, the level of the A0 pin is latched.
[Input Data Bus Buffer Register 0, 1 (DBBIN0,
DBBIN1)] 002816, 002B16
Data on the data bus is latched to DBBIN by writing request from
the host CPU. Data of DBBIN can be read from the data bus
buffer registers (address 002816 or 002B16) on SFR.
[Output Data Bus Buffer Register 0, 1
(DBBOUT0, DBBOUT1)] 002816, 002B16
When writing data to the data bus buffer registers (address 002816
or 002B16) on SFR, data is set to DBBOUT. Data of DBBOUT is
output from the host CPU to the data bus by performing the read-
ing request when the A0 pin is set to “L”.
38
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8 Function description of control I/O pins at bus interface function selected
OBF00
output
enable bit
OBF10
output
enable bit
OBF01
output
enable bit
Input
/Output
Pin
Name
Functions
Chip select input
This is used for selecting the data bus buffer and is
selected at “L” level.
P47/SRDY1
/S1
S1
A0
S0
–
–
–
–
–
–
–
–
–
Input
Input
Input
Address input
This is used for selecting DBBSTS and DBBOUT
when the host CPU is read.
This is used for distinguishing command from data
when writing to the host CPU.
P50/A0
Chip select input
This is used for selecting the data bus buffer and is
selected at “L” level.
P51/INT20
/S0
P52/INT30
/R
This is a timing signal for reading data from the
data bus buffer to the host CPU.
R
–
–
1
0
0
–
–
0
1
0
–
–
0
0
1
Input
P53/INT40
/W
This is a timing signal for writing data to the data
bus buffer by the host CPU.
W
Output
Output
Output
Output
P42/INT0
/OBF00
Status output signal
OBF00 signal is output.
OBF00
OBF01
OBF10
P43/INT1
/OBF01
Status output signal
OBF01 signal is output.
P46/SCLK1
/OBF10
Status output signal
OBF10 signal is output.
39
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2
2
Table 9 Multi-master I C-BUS interface functions
MULTI-MASTER I C-BUS INTERFACE
2
The multi-master I C-BUS interface is a serial communications cir-
Item
Function
2
cuit, conforming to the Philips I C-BUS data transfer format. This
2
In conformity with Philips I C-BUS
standard:
interface, offering both arbitration lost detection and a synchro-
nous functions, is useful for the multi-master serial
communications.
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Format
2
Figure 35 shows a block diagram of the multi-master I C-BUS in-
2
terface and Table 9 lists the multi-master I C-BUS interface
2
In conformity with Philips I C-BUS
functions.
standard:
2
2
Master transmission
Master reception
Slave transmission
Slave reception
This multi-master I C-BUS interface consists of the I C address
Communication mode
SCL clock frequency
2
2
register, the I C data shift register, the I C clock control register,
2
2
2
the I C control register, the I C status register, the I C start/stop
condition control register and other control circuits.
16.1 kHz to 400 kHz (at φ= 4 MHz)
20.2 kHz to 312.5 kHz (at φ = 5 MHz)
2
When using the multi-master I C-BUS interface, set 1 MHz or
more to φ.
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
b7
I2C address register
b0
Interrupt
generating
circuit
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Interrupt
generating
circuit
Interrupt request signal
(I2CIRQ)
Interrupt request signal
(SCL DAIRQ)
S
S0D
Address comparator
I2C data shift register
Serial data
Noise
elimination
circuit
Data
control
circuit
b7
b0
(SDA
)
b7
b0
S
0
AL AAS AD0 LRB
MST TRX BB PIN
S1
S2D
AL
circuit
STSP
SEL
SIS SIP
SSC4 SSC3 SSC2 SSC1 SSC0
I2C status register
2
I C start/stop condition
control register
Internal data bus
BB
circuit
Serial
clock
I2C clock control register
Noise
elimination
circuit
S1D
Clock
control
circuit
b7
ACK
S2
b0
b7
b0
(SCL
)
CLK 10BIT
STP SAD
ACK FAST
CCR4 CCR3 CCR2 CCR1 CCR0
TISS
ALS ES0 BC2 BC1 BC0
MODE
BIT
I2C clock control register
System clock (φ)
Stop selection
Clock division
Bit counter
2
Fig. 35 Block diagram of multi-master I C-BUS interface
✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components
an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
40
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2
[I C Data Shift Register (S0)] 001216
2
The I C data shift register (S0 : address 001216) is an 8-bit shift
b7
b0
I2C address register
(S0D: address 001316
register to store receive data and write transmit data.
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
)
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL clock, and
each time one-bit data is output, the data of this register are
shifted by one bit to the left. When data is received, it is input to
this register from bit 0 in synchronization with the SCL clock, and
each time one-bit data is input, the data of this register are shifted
by one bit to the left. The minimum 2 cycles of φ are required from
the rising of the SCL clock until input to this register.
Read/write bit
Slave address
2
Fig. 36 Structure of I C address register
2
The I C data shift register is in a write enable status only when the
2
I C-BUS interface enable bit (ES0 bit : bit 3 of address 1516) of
2
the I C control register is “1.” The bit counter is reset by a write in-
2
struction to the I C data shift register. When both the ES0 bit and
2
the MST bit of the I C status register (address 001416) are “1,” the
2
SCL is output by a write instruction to the I C data shift register.
2
Reading data from the I C data shift register is always enabled re-
gardless of the ES0 bit value.
2
[I C Address Register (S0D)] 001316
2
The I C address register (address 001316) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition is detected.
•Bit 0: Read/write bit (RBW)
This is not used in the 7-bit addressing mode. In the 10-bit ad-
dressing mode, the first address data to be received is compared
2
with the contents (SAD6 to SAD0 + RBW) of the I C address reg-
ister.
The RBW bit is cleared to “0” automatically when the stop condi-
tion is detected.
•Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data
transmitted from the master is compared with the contents of
these bits.
41
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2
[I C Clock Control Register (S2)] 001616
2
b7
b0
The I C clock control register (address 001616) is used to set ACK
I2C clock control register
(S2 : address 001616)
ACK FAST
BIT MODE
ACK
CCR4 CCR3 CCR2 CCR1 CCR0
control, SCL mode and SCL frequency.
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 10.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the
standard clock mode is selected. When the bit is set to “1,” the
high-speed clock mode is selected.
SCL frequency control
bits
Refer to Table 10.
SCL mode specification bit
0 : Standard clock mode
1 : High-speed clock
mode
2
When connecting the bus of the high-speed mode I C bus stan-
ACK bit
0 : ACK is returned.
1 : ACK is not
returned.
dard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(XIN) and high-speed mode (2 division main clock).
•Bit 6: ACK bit (ACK BIT)
ACK clock bit
0 : No ACK clock
1 : ACK clock
✽
This bit sets the SDA status when an ACK clock is generated.
When this bit is set to “0,” the ACK return mode is selected and
SDA goes to “L” at the occurrence of an ACK clock. When the bit is
set to “1,” the ACK non-return mode is selected. The SDA is held in
the “H” status at the occurrence of an ACK clock.
2
Fig. 37 Structure of I C clock control register
2
Table 10 Set values of I C clock control register and SCL
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0,” the SDA is auto-
matically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the SDA is auto-
matically made “H” (ACK is not returned).
frequency
Setting value of
CCR4–CCR0
SCL frequency
(at φ = 4 MHz, unit : kHz) (Note 1)
Standard clock
mode
High-speed clock
mode
CCR4 CCR3 CCR2 CCR1 CCR0
Setting disabled Setting disabled
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
✽ACK clock: Clock for acknowledgment
Setting disabled
Setting disabled
333
Setting disabled
Setting disabled
– (Note 2)
– (Note 2)
100
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an ac-
knowledgment response of data transfer. When this bit is set to
“0,” the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1,” the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the SDA at the
occurrence of an ACK clock (makes SDA “H”) and receives the
ACK bit generated by the data receiving device.
250
400 (Note 3)
166
83.3
1000/CCR value
500/CCR value
(Note 3)
(Note 3)
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
34.5
33.3
32.3
17.2
16.6
16.1
Note: Do not write data into the I2C clock control register during transfer. If
data is written during transfer, the I2C clock generator is reset, so
that data cannot be transferred normally.
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 %
only when the high-speed clock mode is selected and CCR value
= 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates
from –4 to +2 cycles of φ in the standard clock mode, and fluctu-
ates from –2 to +2 cycles of φ in the high-speed clock mode. In
the case of negative fluctuation, the frequency does not increase
because “L” duration is extended instead of “H” duration reduc-
tion.
These are value when SCL clock synchronization by the synchro-
nous function is not performed. CCR value is the decimal
notation value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or
more. When using these setting value, use φ of 4 MHz or less.
3: The data formula of SCL frequency is described below:
φ/(8 ✕ CCR value) Standard clock mode
φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the SCL frequency by set-
ting the SCL frequency control bits CCR4 to CCR0.
42
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2
[I C Control Register (S1D)] 001516
b7
b0
2
The I C control register (address 001516) controls data communi-
I2C control register
10 BIT
SAD
CLK
STP
TISS
ALS
BC2 BC1 BC0
ES0
cation format.
(S1D : address 001516
)
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
2
transmitted. The I C interrupt request signal occurs immediately
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
bit (bit 7 of address 001616)) have been transferred, and BC0 to
BC2 are returned to “0002”.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : 8
1 : 7
0 : 6
1 : 5
0 : 4
1 : 3
0 : 2
1 : 1
Also when a START condition is received, these bits become
“0002” and the address data is always transmitted and received in
8 bits.
2
•Bit 3: I C interface enable bit (ES0)
I2C-BUS interface
enable bit
2
This bit enables to use the multi-master I C BUS interface. When
0 : Disabled
1 : Enabled
this bit is set to “0,” the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
Data format selection bit
0 : Addressing format
1 : Free data format
When ES0 = “0,” the following is performed.
2
• PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I C
status register at address 001416 ).
Addressing format
selection bit
2
• Writing data to the I C data shift register (address 001216) is dis
0 : 7-bit addressing
format
1 : 10-bit
abled.
•Bit 4: Data format selection bit (ALS)
addressing format
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0,” the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
System clock stop
selection bit
0 : System clock stop
when executing WIT
or STP instruction
1 : Not system clock
stop when executing
WIT instruction
2
when a general call (refer to “(5) I C Status Register,” bit 1) is re-
ceived, transfer processing can be performed. When this bit is set
to “1,” the free data format is selected, so that slave addresses are
not recognized.
(Do not use the STP
instruction.)
•Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0,” the 7-bit addressing format is selected. In this case,
I2C-BUS interface pin input
level selection bit
2
only the high-order 7 bits (slave address) of the I C address regis-
0 : CMOS input
1 : SMBUS input
ter (address 001316) are compared with address data. When this
bit is set to “1,” the 10-bit addressing format is selected, and all
2
the bits of the I C address register are compared with address
2
Fig. 38 Structure of I C control register
data.
•Bit 6: System clock stop selection bit (CLKSTP)
When executing the WIT or STP instruction, this bit selects the
2
condition of system clock provided to the multi-master I C-BUS in-
terface. When this bit is set to “0,” system clock and operation of
2
the multi-master I C-BUS interface stop by executing the WIT or
STP instruction.
When this bit is set to “1,” system clock and operation of the multi-
2
master I C-BUS interface do not stop even when the WIT
instruction is executed.
When the system clock stop selection bit is “1,” do not execute the
STP instruction.
2
•Bit 7: I C-BUS interface pin input level selection bit
This bit selects the input level of the SCL and SDA pins of the multi-
2
master I C-BUS interface.
43
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2
2
[I C Status Register (S1)] 001416
•Bit 4: I C-BUS interface interrupt request bit (PIN)
2
2
The I C status register (address 001416) controls the I C-BUS in-
terface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (in-
cluding the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and
clock generation is disabled. Figure 40 shows an interrupt request
signal generating timing chart.
Set “00002” to the low-order 4 bits, because these bits become the
reserved bits at writing.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,
this bit is set to “1.” Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
The PIN bit is set to “1” in one of the following conditions:
2
• Executing a write instruction to the I C data shift register (ad-
2
“0” by executing a write instruction to the I C data shift register
dress 001216). (This is the only condition which the prohibition of
the internal clock is released and data can be communicated ex-
cept for the start condition detection.)
(address 001216).
•Bit 1: General call detecting flag (AD0)
✽
When the ALS bit is “0,” this bit is set to “1” when a general call
• When the ES0 bit is “0”
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives con-
trol data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
• At reset
• When writing “1” to the PIN bit by software
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ-
ing when arbitration lost is detected)
✽General call: The master transmits the general call address “0016” to all
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately af-
ter completion of slave address agreement or general call
address reception
slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
• In the slave reception mode, with ALS = “1” and immediately af-
ter completion of address data reception
➀ In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-or-
•Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this
bit is set to “0,” this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins in-
put signal regardless of master/slave. This flag is set to “1” by
detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of these detecting is set by the start/stop
2
der 7 bits of the I C address register (address 001316).
• A general call is received.
➁ In the slave reception mode, when the 10-bit addressing format
is selected, this bit is set to “1” with the following condition:
2
condition setting bits (SSC4–SSC0) of the I C start/stop condition
2
• When the address data is compared with the I C address reg-
control register (address 001716). When the ES0 bit (bit 3) of the
ister (8 bits consisting of slave address and RBW bit), the first
bytes agree.
2
I C control register (address 001516) is “0” or reset, the BB flag is
set to “0.”
2
➂ This bit is set to “0” by executing a write instruction to the I C
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Gen-
erating Method” described later.
data shift register (address 001216) when ES0 is set to “1” or
reset.
✽
•Bit 3: Arbitration lost detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1.” At the same time, the TRX bit is set to “0,” so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0.” The arbitration lost
can be detected only in the master transmission mode. When ar-
bitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and ad-
dress data transmitted by another master device.
✽Arbitration lost :The status in which communication as a master is dis-
abled.
44
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•Bit 6: Communication mode specification bit (transfer direc-
tion specification bit: TRX)
b7
b0
I2C status register
(S1 : address 001416)
This bit decides a direction of transfer for data communication.
When this bit is “0,” the reception mode is selected and the data of
a transmitting device is received. When the bit is “1,” the transmis-
sion mode is selected and address data and control data are
output onto the SDA in synchronization with the clock generated on
the SCL.
MST TRX BB PIN AL AAS AD0 LRB
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
This bit is set/reset by software and hardware. About set/reset by
hardware is described below. This bit is set to “1” by hardware
when all the following conditions are satisfied:
• When ALS is “0”
Slave address comparison flag
(Note)
0 : Address disagreement
1 : Address agreement
• In the slave reception mode or the slave transmission mode
• When the R/W bit reception is “1”
This bit is set to “0” in one of the following conditions:
• When arbitration lost is detected.
• When a STOP condition is detected.
Arbitration lost detecting flag
(Note)
0 : Not detected
1 : Detected
• When writing “1” to this bit by software is invalid by the START
condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
I2C-BUS interface interrupt
request bit
0 : Interrupt request issued
1 : No interrupt request
issued
•Bit 7: Communication mode specification bit (master/slave
specification bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are re-
ceived, and data communication is performed in synchronization
with the clock generated by the master. When this bit is “1,” the
master is specified and a START condition and a STOP condition
are generated. Additionally, the clocks required for data communi-
cation are generated on the SCL.
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
This bit is set to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transfer when arbi-
tration lost is detected
Note: These bit and flags can be read out but cannot
be written.
• When a STOP condition is detected.
Write “0” to these bits at writing.
• Writing “1” to this bit by software is invalid by the START condi-
tion duplication preventing function (Note).
2
• At reset
Fig. 39 Structure of I C status register
Note: START condition duplication preventing function
The MST, TRX, and BB bits is set to “1” at the same time after con-
firming that the BB flag is “0” in the procedure of a START condition
occurrence. However, when a START condition by another master
device occurs and the BB flag is set to “1” immediately after the con-
tents of the BB flag is confirmed, the START condition duplication
preventing function makes the writing to the MST and TRX bits in-
valid. The duplication preventing function becomes valid from the
rising of the BB flag to reception completion of slave address.
S
CL
PIN
I2CIRQ
Fig. 40 Interrupt request signal generating timing
45
MITSUBISHI MICROCOMPUTERS
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START Condition Generating Method
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 43, 44, and Table 13. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL re-
lease time, setup time, and hold time (see Table 13).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
2
When writing “1” to the MST, TRX, and BB bits of the I C status
register (address 001416) at the same time after writing the slave
2
address to the I C data shift register (address 001216) with the
2
condition in which the ES0 bit of the I C control register (address
001516) and the BB flag are “0”, a START condition occurs. After
that, the bit counter becomes “0002” and an SCL for 1 byte is out-
put. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 41, the START condition generating timing diagram, and
Table 11, the START condition generating timing table.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 13, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “I2CIRQ” occurs to the CPU.
I2C status register
write signal
S
S
CL
DA
Setup
time
S
CL release time
Hold time
S
CL
DA
Setup
time
Hold time
S
Fig. 41 START condition generating timing diagram
BB flag
reset
time
BB flag
Table 11 START condition generating timing table
START/STOP condition
generating selection bit clock mode
Standard
High-speed
clock mode
Fig. 43 START condition detecting timing diagram
Item
5.0 µs (20 cycles) 2.5 µs (10 cycles)
13.0 µs (52 cycles) 6.5 µs (26 cycles)
5.0 µs (20 cycles) 2.5 µs (10 cycles)
13.0 µs (52 cycles) 6.5 µs (26 cycles)
“0”
“1”
“0”
“1”
Setup
time
S
CL release time
S
CL
DA
Hold
time
Setup
time
Hold time
S
BB flag
reset
time
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
BB flag
STOP Condition Generating Method
Fig. 44 STOP condition detecting timing diagram
2
When the ES0 bit of the I C control register (address 001516) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
2
Table 13 START condition/STOP condition detecting conditions
of the I C status register (address 001416) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 42, the STOP condition generating timing
diagram, and Table 12, the STOP condition generating timing
table.
Standard clock mode
High-speed clock mode
S
CL release time
SSC value + 1 cycle (6.25 µs)
4 cycles (1.0 µs)
SSC value
Setup time
Hold time
+ 1 cycle < 4.0 µs (3.25 µs)
2 cycles (1.0 µs)
2 cycles (0.5 µs)
2
SSC value
cycle < 4.0 µs (3.0 µs)
2
BB flag set/
reset time
SSC value –1
3.5 cycles (0.875 µs)
+ 2 cycles (3.375 µs)
I2C status register
write signal
2
Note: Unit : Cycle number of system clock φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at φ = 4 MHz.
SCL
Setup
time
Hold time
SDA
Fig. 42 STOP condition generating timing diagram
Table 12 STOP condition generating timing table
START/STOP condition
generating selection bit clock mode
Standard
High-speed
clock mode
Item
“0”
“1”
“0”
“1”
5.5 µs (22 cycles) 3.0 µs (12 cycles)
13.5 µs (54 cycles) 7.0 µs (28 cycles)
5.5 µs (22 cycles) 3.0 µs (12 cycles)
13.5 µs (54 cycles) 7.0 µs (28 cycles)
Setup
time
Hold
time
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
46
MITSUBISHI MICROCOMPUTERS
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2
[I C START/STOP Condition Control Register
➁ 10-bit addressing format
(S2D)] 001716
The I C START/STOP condition control register (address 001716)
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
2
2
the I C control register (address 001516) to “1.” An address
controls START/STOP condition detection.
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
•Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(XIN) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 13.
2
in the I C address register (address 001316). At the time of this
comparison, an address comparison between the RBW bit of
2
the I C address register (address 001316) and the R/W bit
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RBW bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is pro-
cessed as an address data bit.
Do not set “000002” or an odd number to the START/STOP condi-
tion set bit (SSC4 to SSC0).
Refer to Table 14, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or SDA
pin interrupt pin.
When the first-byte address data agree with the slave address,
2
the AAS bit of the I C status register (address 001416) is set to
2
“1.” After the second-byte address data is stored into the I C
data shift register (address 001216), perform an address com-
parison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
2
•Bit 6: SCL/SDA interrupt pin selection bit (SIS)
the slave address, set the RBW bit of the I C address register
This bit selects the pin of which interrupt becomes valid between
(address 001316) to “1” by software. This processing can make
the 7-bit slave address and R/W data agree, which are re-
ceived after a RESTART condition is detected, with the value of
the SCL pin and the SDA pin.
Note: When changing the setting of the SCL/SDA interrupt pin polarity se-
lection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS
interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the inter-
rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/
SDA interrupt pin selection bit, or the I2C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
2
the I C address register (address 001316). For the data trans-
mission format when the 10-bit addressing format is selected,
refer to Figure 46, (3) and (4).
•Bit 7: START/STOP condition generating selection bit
(STSPSEL)
Setup/Hold time when the START/STOP condition is generated
can be selected.
Cycle number of system clock becomes standard for setup/hold
time. Additionally, setup/hold time is different between the START
condition and the STP condition. (Refer to Tables 11 and 12.) Set
“1” to this bit when the system clock frequency is 4 MHz or more.
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
➀ 7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
2
the I C control register (address 001516) to “0.” The first 7-bit
address data transmitted from the master is compared with the
2
high-order 7-bit slave address stored in the I C address register
(address 001316). At the time of this comparison, address com-
2
parison of the RBW bit of the I C address register (address
001316) is not performed. For the data transmission format
when the 7-bit addressing format is selected, refer to Figure 46,
(1) and (2).
47
MITSUBISHI MICROCOMPUTERS
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b7
STSP
SEL
b0
I2C START/STOP condition
control register
SSC4 SSC3 SSC2 SSC1 SSC0
SIS SIP
(S2D : address 001716
)
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin selection bit
0 : SDA valid
1 : SCL valid
START/STOP condition generating
selection bit
0 : Setup/Hold time short mode
1 : Setup/Hold time long mode
2
Fig. 45 Structure of I C START/STOP condition control register
Table 14 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Oscillation
frequency
f(XIN) (MHz)
START/STOP
condition
control register
System
clock φ
(MHz)
Main clock
divide ratio
SCL release time
Setup time
Hold time
(µs)
(µs)
(µs)
10
XXX11110
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
6.2 µs (31 cycles)
6.75 µs (27 cycles)
6.25 µs (25 cycles)
5.0 µs (5 cycles)
6.5 µs (13 cycles)
5.5 µs (11 cycles)
5.0 µs (5 cycles)
3.2 µs (16 cycles)
3.5 µs (14 cycles)
3.25 µs (13 cycles)
3.0 µs (3 cycles)
3.5 µs (7 cycles)
3.0 µs (6 cycles)
3.0 µs (3 cycles)
3.0 µs (15 cycles)
3.25 µs (13 cycles)
3.0 µs (12 cycles)
2.0 µs (2 cycles)
3.0 µs (6 cycles)
2.5 µs (5 cycles)
2.0 µs (2 cycles)
2
2
8
2
2
5
4
1
2
1
8
8
4
2
Note: Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
A
Data
A
Data
S
Slave address R/W
7 bits “0”
A/A
P
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transnmits data to a slave-receiver
A
Data
A
Data
Slave address
7 bits
S
R/W
“1”
P
A
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
Slave address
1st 7 bits
Slave address
2nd bytes
A
A
Data
1 to 8 bits
A
Data
S
R/W
“0”
A/A
P
7 bits
8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
Slave address
1st 7 bits
Slave address
2nd bytes
Slave address
1st 7 bits
Data
1 to 8 bits
P
A
A
A
A
Data
S
R/W
“0”
Sr
R/W
“1”
A
1 to 8 bits
7 bits
8 bits
7 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
P : STOP condition
R/W : Read/Write bit
Sr : Restart condition
Fig. 46 Address data communication format
48
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2
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
■Precautions when using multi-master I C-
BUS interface
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
2
➀ Set a slave address in the high-order 7 bits of the I C address
SEB, CLB etc. is executed for each register of the multi-master
2
register (address 001316) and “0” into the RBW bit.
I C-BUS interface are described below.
2
➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in
• I C data shift register (S0: address 001216)
2
the I C clock control register (address 001616).
When executing the read-modify-write instruction for this regis-
ter during transfer, data may become a value not intended.
2
➂ Set “0016” in the I C status register (address 001416) so that
2
transmission/reception mode can become initializing condition.
• I C address register (S0D: address 001316)
2
➃ Set a communication enable status by setting “0816” in the I C
When the read-modify-write instruction is executed for this regis-
ter at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RBW) at the above timing.
control register (address 001516).
2
➄ Confirm the bus free condition by the BB flag of the I C status
register (address 001416).
2
➅ Set the address data of the destination of transmission in the
• I C status register (S1: address 001416)
2
high-order 7 bits of the I C data shift register (address 001216)
Do not execute the read-modify-write instruction for this register
and set “0” in the least significant bit.
because all bits of this register are changed by H/W.
2
2
➆ Set “F016” in the I C status register (address 001416) to gener-
• I C control register (S1D: address 001516)
ate a START condition. At this time, an SCL for 1 byte and an
When the read-modify-write instruction is executed for this regis-
ter at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
ACK clock automatically occur.
2
➇Set transmit data in the I C data shift register (address 001216).
At this time, an SCL and an ACK clock automatically occur.
2
➈ When transmitting control data of more than 1 byte, repeat step
➇.
• I C clock control register (S2: address 001616)
The read-modify-write instruction can be executed for this regis-
ter.
2
➉ Set “D016” in the I C status register (address 001416) to gener-
2
ate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
• I C START/STOP condition control register (S2D: address
001716)
The read-modify-write instruction can be executed for this regis-
ter.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
2
➀ Set a slave address in the high-order 7 bits of the I C address
register (address 001316) and “0” in the RBW bit.
➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516”
2
in the I C clock control register (address 001616).
2
➂ Set “0016” in the I C status register (address 001416) so that
transmission/reception mode can become initializing condition.
2
➃ Set a communication enable status by setting “0816” in the I C
control register (address 001516).
➄ When a START condition is received, an address comparison is
performed.
➅ •When all transmitted addresses are “0” (general call):
2
AD0 of the I C status register (address 001416) is set to “1”
and an interrupt request signal occurs.
• When the transmitted addresses agree with the address set
in ➀:
2
ASS of the I C status register (address 001416) is set to “1”
and an interrupt request signal occurs.
2
• In the cases other than the above AD0 and AAS of the I C sta-
tus register (address 001416) are set to “0” and no interrupt
request signal occurs.
2
➆ Set dummy data in the I C data shift register (address 001216).
➇When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
49
MITSUBISHI MICROCOMPUTERS
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2
(2) START condition generating procedure using multi-master
1. Procedure example (The necessary conditions of the generat-
ing procedure are described as the following 2 to 5.
(4) Writing to I C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and
an instruction to set the MST and TRX bits to “0” from “1” simulta-
neously. It is because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to “0” from “1” simultaneously when the PIN bit is “1.” It is because
it may become the same as above.
LDA —
SEI
(Taking out of slave address value)
(Interrupt disabled)
BBS 5, S1, BUSBUSY (BB flag confirming and branch pro-
cess)
BUSFREE:
STA S0
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
(5) Process of after STOP condition generating
2
2
LDM #$F0, S1
CLI
Do not write data in the I C data shift register S0 and the I C sta-
tus register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. It is because
the STOP condition waveform might not be normally generated.
Reading to the above registers do not have the problem.
BUSBUSY:
CLI
(Interrupt enabled)
2. Use “Branch on Bit Set” of “BBS 5, $0014, –” for the BB flag
confirming and branch process.
(6) STOP condition input at 7th clock pulse
In the slave mode, the STOP condition is input at the 7th clock
pulse while receiving a slave address or data. As the clock pulse
is continuously input, the SDA line may be held at LOW even if
flag BB is set to “0” (only for M38867M8A and M38867E8).
Countermeasure:
3. Use “STA $12, STX $12” or “STY $12” of the zero page ad-
dressing instruction for writing the slave address value to the
2
I C data shift register.
4. Execute the branch instruction of above 2 and the store instruc-
tion of above 3 continuously shown the above procedure
example.
2
Write dummy data to the I C shift register or reset the ES0 bit in
the S1D register (ES0 = “L” → ES0 = “H”) during a stop condition
interrupt routine with flag PIN = “1”.
5. Disable interrupts during the following three process steps:
• BB flag confirming
Note: Do not use the read-modify-write instruction at this time.
Furthermore, when the ES0 bit is set to “0”, it becomes a
general-purpose port; so that the port must be set to input
mode or “H”.
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
(7) ES0 bit switch
(3) RESTART condition generating procedure
In standard clock mode when SSC = “000102” or in high-speed
clock mode, flag BB may switch to “1” if ES0 bit is set to “1” when
SDA is “L”.
This cannot be applied when the external memory is used and the
bus cycle is extended by ONW function.
Countermeasure:
1. Procedure example (The necessary conditions of the generat-
ing procedure are described as the following 2 to 4.)
Set ES0 to “1” when SDA is “H”.
Execute the following procedure when the PIN bit is “0.”
LDM #$00, S1
LDA —
(Select slave receive mode)
(Taking out of slave address value)
(Interrupt disabled)
SEI
STAS0
(Writing of slave address value)
LDM #$F0, S1
CLI
(
Trigger of RESTART condition generating
)
(Interrupt enabled)
2. Select the slave receive mode when the PIN bit is “0.” Do not
write “1” to the PIN bit. Neither “0” nor “1” is specified for the
writing to the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
3. The SCL pin is released by writing the slave address value to
2
the I C data shift register.
4. Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating
50
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
[A-D Conversion Register 1,2 (AD1, AD2)]
003516, 003816
Channel Selector
The channel selector selects one of ports P60/AN0 to P67/AN7,
and inputs the voltage to the comparator.
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
Bit 7 of the A-D conversion register 2 is the conversion mode se-
lection bit. When this bit is set to “0,” the A-D converter becomes
the 10-bit A-D mode. When this bit is set to “1,” that becomes the
8-bit A-D mode. The conversion result of the 8-bit A-D mode is
stored in the A-D conversion register 1. As for 10-bit A-D mode,
10-bit reading or 8-bit reading can be performed by selecting the
reading procedure of the A-D conversion register 1, 2 after A-D
conversion is completed (in Figure 48).
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, and then stores the result in the
A-D conversion registers 1, 2. When an A-D conversion is com-
pleted, the control circuit sets the A-D conversion completion bit
and the A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(XIN) to 500 kHz or more during an A-D conversion.
The A-D conversion register 1 performs the 8-bit reading inclined
to MSB after reset, the A-D conversion is started, or reading of the
A-D converter register 1 is generated; and the register becomes
the 8-bit reading inclined to LSB after the A-D converter register 2
is generated.
b7
b0
AD/DA control register
(ADCON : address 003416
)
Analog input pin selection bits
b2 b1 b0
0 0 0: P6
0 0 1: P6
0 1 0: P6
0 1 1: P6
1 0 0: P6
1 0 1: P6
1 1 0: P6
1 1 1: P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
[AD/DA Control Register (ADCON)] 003416
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 select a specific analog input pin. Bit 3 signals the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
PWM0 output pin selection bit
0: P5
6
/PWM01
/PWM00
Comparison Voltage Generator
1: P3
0
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024, and outputs the divided voltages in the
10-bit A-D mode (256 division in 8-bit A-D mode).
The A-D converter successively compares the comparison voltage
Vref in each mode, dividing the VREF (see below), with the input
voltage.
PWM1 output pin selection bit
0: P5
7
/PWM11
/PWM10
1: P3
1
DA1 output enable bit
0: DA1 output disabled
1: DA1 output enabled
DA2 output enable bit
0: DA2 output disabled
1: DA2 output enabled
• 10-bit A-D mode (10-bit reading)
VREF
Vref =
✕ n (n = 0–1023)
1024
Fig. 47 Structure of AD/DA control register
• 10-bit A-D mode (8-bit reading)
VREF
Vref =
✕ n (n = 0–255)
256
• 8-bit A-D mode
VREF
10-bit reading
(Read address 003816 before 003516)
Vref =
✕ (n–0.5) (n = 1–255)
256
b0
b7
=0
(n = 0)
(Address 003816)
(Address 003516)
b9 b8
0
b7
b0
b7 b6 b5 b4 b3 b2 b1 b0
Note: Bits 2 to 6 of address 003816 becomes “0”at reading.
8-bit reading (Read only address 003516)
b7
b0
(Address 003516)
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 48 Structure of 10-bit A-D mode reading
51
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
b7
3
b0
AD/DA control register
(Address 003416
)
A-D control circuit
A-D interrupt request
P60
P61
P62
P63
P64
P65
P66
P67
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
A-D conversion register 2 (Address 003816
A-D conversion register 1 (Address 003516
)
)
Comparator
10
Resistor ladder
V
REF AVSS
Fig. 49 Block diagram of A-D converter
52
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER
The 3886 group has two internal D-A converters (DA1 and DA2)
with 8-bit resolution.
The D-A converter is performed by setting the value in each D-A
conversion register. The result of D-A conversion is output from
the DA1 or DA2 pin by setting the DA output enable bit to “1”.
When using the D-A converter, the corresponding port direction
register bit (P56/DA1/PWM01 or P57/DA2/PWM11) must be set to
“0” (input status).
D-A1 conversion register (8)
DA
1
output enable bit
P5 /DA /PWM01
The output analog voltage V is determined by the value n (decimal
notation) in the D-A conversion register as follows:
R-2R resistor ladder
6
1
V = VREF ✕ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
D-A2 conversion register (8)
DA
At reset, the D-A conversion registers are cleared to “0016”, the
DA output enable bits are cleared to “0”, and the P56/DA1/PWM01
and P57/DA2/PWM11 pins become high impedance.
2
output enable bit
P5 /DA /PWM11
R-2R resistor ladder
7
2
The DA output does not have buffers. Accordingly, connect an ex-
ternal buffer when driving a low-impedance load.
Set VCC to 4.0 V or more when using the D-A converter.
Fig. 50 Block diagram of D-A converter
DA1
output enable bit
R
“0”
R
2R
R
R
R
R
R
P56/DA1/PWM01
“1”
2R
2R
2R
2R
2R
2R
2R
2R
MSB
LSB
D-A1 conversion register
“0”
“1”
AVSS
VREF
Fig. 51 Equivalent connection circuit of D-A converter (DA1)
53
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
performed by the writing operation to the comparator data register
(address 002D16). After 14 cycles of the internal system clock φ
(the time required for the comparison), the comparison result is
stored in the comparator register (address 002D16).
COMPARATOR CIRCUIT
Comparator Configuration
The comparator circuit consists of resistors, comparators, a com-
parator control circuit, the comparator reference input selection bit
(bit 7 of address 001D16), a comparator data register (address
002D16), the comparator reference power source input pin (P00/
P3REF) and analog signal input pins (P30–P37). The analog input
pin (P30–P37) also functions as an ordinary digital port.
If the analog input voltage is greater than the internal reference
voltage, each bit of this register is “1”; if it is less than the internal
reference voltage, each bit of this register is “0”. To perform an-
other comparison, the voltage comparison must be performed
again by writing to the comparator data register (address 002D16).
Read the result when 14 cycles of φ or more have passed after the
comparator operation starts. The ladder resistor is turned on dur-
ing 14 cycles of φ , which is required for the comparison, and the
reference voltage is generated. An unnecessary current is not
consumed because the ladder resistor is turned off while the com-
parator operation is not performed. Since the comparator consists
of capacitor coupling, the electric charge is lost if the clock fre-
quency is low.
Comparator Operation
To activate the comparator, first set port P3 to input mode by set-
ting the corresponding direction register (address 000716) to “0” to
use port P3 as an analog voltage input pin. The internal fixed ana-
log voltage (VCC ✕ 29/32) can be generated by setting “1” to the
comparator reference input selection bit (bit 7) of the serial I/O2
control register (address 001D16). (The internal fixed analog volt-
age becomes about 4.5 V at VCC = 5.0 V.) When setting “0” to the
comparator reference input selection bit, the P00/P3REF pin be-
comes the comparator reference power source input pin and it is
possible to input the comparator reference power source option-
ally from the external. The voltage comparison is immediately
Keep that the clock frequency is 1 MHz or more during the com-
parator operation. Do not execute the STP, WIT, or port P3 I/O
instruction.
Data bus
8
8
P3 (8)
Comparator data register
(address 002D16
)
b0
P3
7
Compar-
ator
P3
P3
6
0
Comparator reference input selection
bit (bit 7) of serial I/O2 control
Compar-
ator
register(address 001D16
)
“0”
V
CC
Compar-
ator
“1”
V
CC✕29/32
Comparator
control circuit
Comparator connecting
signal
Ladder resistor
connecting signal
P00/P3REF
V
SS
Fig. 52 Comparator circuit
54
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 001E16) per-
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to f(XIN)=131.072 ms
at 8 MHz frequency and f(XCIN)=32.768 s at 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case
is set to f(XIN)= 512 µs at 8 MHz frequency and f(XCIN)=128 ms at
32 kHz frequency. This bit is cleared to “0” after resetting.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 001E16) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
001E16) and an internal reset occurs at an underflow of the watch-
dog timer H.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 001E16) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 001E16) may be
started before an underflow. When the watchdog timer control reg-
ister (address 001E16) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watch-
dog timer H count source selection bit are read.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
Once the STP instruction is executed, an internal reset occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register (address
001E16), each watchdog timer H and L is set to “FF16.”
“FF16” is set when
Data bus
watchdog timer
control register is
written to.
“10”
“FF16” is set when
watchdog timer
control register is
written to.
XCIN
“0”
“1”
Watchdog timer L (8)
Main clock division
ratio selection bits
Watchdog timer H (8)
1/16
(Note)
“00”
“01”
Watchdog timer H count
source selection bit
XIN
STP instruction disable bit
STP instruction
Reset
circuit
Internal reset
RESET
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 53 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 001E16
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 54 Structure of Watchdog timer control register
55
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an "L"
level for 2 µs or more. Then the RESET pin is returned to an "H"
level (the power source voltage should be between 2.7 V and 5.5
V (4.0 V to 5.5 V for flash memory version), and the oscillation
should be stable), reset is released. After the reset is completed,
the program starts from the address contained in address FFFD16
(high-order byte) and address FFFC16 (low-order byte). Make sure
that the reset input voltage is less than 0.54 V for VCC of 2.7 V. For
flash memory version, make sure that the reset input voltage is
less than 0.8 V for Vcc of 4.0 V.
Poweron
(Note)
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
(Vcc = 4.0 V for flash memory version)
RESET
VCC
Power source
voltage detection
circuit
Fig. 55 Reset circuit example
XIN
φ
RESET
Internal
reset
Address
AD
H,L
?
?
?
?
FFFC
FFFD
Reset address from the vector table.
AD
H
Data
?
?
?
AD
L
?
SYNC
XIN: 10.5 to 18.5 clock cycles
Notes1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8
• f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 56 Reset sequence
56
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
Register contents
Address
(1)
0016
FF16
Port P0 (P0)
000016
(33)Prescaler 12 (PRE12)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
(2)
0016
0116
Port P0 direction register (P0D)
Port P1 (P1)
000116
(34)Timer 1 (T1)
(3)
0016
FF16
000216
(35)Timer 2 (T2)
(4)
0016
0016
Port P1 direction register (P1D)
Port P2 (P2)
000316
(36)Timer XY mode register (TM)
(37)Prescaler X (PREX)
(5)
0016
FF16
000416
(6)
0016
FF16
Port P2 direction register (P2D)
Port P3 (P3)
000516
(38)Timer X (TX)
(7)
0016
FF16
000616
(39)Prescaler Y (PREY)
(8)
0016
FF16
X X X X X X X X
0016
Port P3 direction register (P3D)
Port P4 (P4)
000716
(40)Timer Y (TY)
(9)
0016
000816
(41)Data bus buffer register 0 (DBB0)
(42)Data bus buffer status register 0 (DBBSTS0)
(43)Data bus buffer control register (DBBCON)
(44)Data bus buffer register 1 (DBB1)
(45)Data bus buffer status register 1 (DBBSTS1)
(46)Comparator data register (CMPD)
(47)Port control register 1 (PCTL1)
(48)Port control register 2 (PCTL2)
(49)PWM0H register (PWM0H)
(50)PWM0L register (PWM0L)
(51)PWM1H register (PWM1H)
(52)PWM1L register (PWM1L)
(53)AD/DA control register (ADCON)
(54)A-D conversion register 1 (AD1)
(55)D-A1 conversion register (DA1)
(56)D-A2conversion register (DA2)
(57)A-D conversion register 2 (AD2)
(58)Interrupt source selection register (INTSEL)
(59)Interrupt edge selection register (INTEDGE)
(60)CPU mode register (CPUM)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
0016
Port P4 direction register (P4D)
Port P5 (P5)
000916
0016
0016
000A16
0016
Port P5 direction register (P5D)
Port P6 (P6)
000B16
002B16 X X X X X X X X
0016
0016
000C16
002C16
0016
Port P6 direction register (P6D)
Port P7 (P7)
000D16
X X X X X X X X
0016
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
0FFE16
0FFF16
(PS)
0016
000E16
0016
0016
Port P7 direction register (P7D)
Port P8 (P8)
000F16
0016
001016
X X X X X X X X
0016
Port P8 direction register (P8D)
001116
X 0 X X X X X X
X X X X X X X X
2
16 X X X X X X X X
0012
I C data shift register (S0)
2
0016
0 0 0 1 0 0 0 X
0016
001316
001416
001516
001616
001716
X 0 X X X X X X
0 0 0 0 1 0 0 0
I C address register (S0D)
2
I C status register (S1)
2
X X X X X X X X
0016
I C control register (S1D)
2
0016
I C clock control register (S2)
0 0 0 1 1 0 1 0
2
0016
I C start/stop condition control register (S2D)
16 X X X X X X X X
0 0 0 0 0 0 X X
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
0018
0016
001916
001A16
001B16
1 0 0 0 0 0 0 0
0016
0016
✻
0 1 0 0 1 0
0016
0
1 1 1 0 0 0 0 0
Interrupt request register 1 (IREQ1)
(61)
001C
16 X X X X X X X X
0016
Interrupt request register 2 (IREQ2)
(62)
0016
Serial I/O2 control register (SIO2CON)
Watchdog timer control register (WDTCON)
Serial I/O2 register (SIO2)
001D16
001E16
001F16
Interrupt control register 1 (ICON1)
(63)
0 0 1 1 1 1 1 1
X X X X X X X X
0016
0016
(64)Interrupt control register 2 (ICON2)
Flash memory control register (FCON)
(65)
0016
0016
(66)Flash command register (FCMD)
(67)Processor status register
(68)Program counter
Note : ✻The initial values depend on level of the CNVSS pin.
X : Not fixed
1
X X X X X X X
FFFD16 contents
FFFC16 contents
(PC
H)
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
(PC
L
)
Fig. 57 Internal status at reset
57
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Wait mode
CLOCK GENERATING CIRCUIT
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
The 3886 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
X
CIN
X
COUT
XIN
XOUT
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
Rf
Rd
set, this mode is selected.
CCIN
CCOUT
C
IN
COUT
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
Fig. 58 Ceramic resonator circuit
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
■Note
If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately af-
ter power on and at returning from stop mode. When switching the
mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3f(XCIN).
X
CIN
X
COUT
X
IN
XOUT
Open
Open
External oscillation
circuit
External oscillation
circuit
V
CC
SS
V
V
CC
SS
(4) Low power dissipation mode
V
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1.” When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
Fig. 59 External clock input circuit
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
Either XIN or XCIN divided by 16 is input to the prescaler 12 as
count source, and the output of the prescaler 12 is connected to
timer 1. Set the timer 1 interrupt enable bit to disabled (“0”) before
executing the STP instruction. Oscillator restarts when an external
interrupt is received, but the internal clock φ is not supplied to the
CPU (remains at “H”) until timer 1 underflows. The internal clock φ
is supplied for the first time, when timer 1 underflows. Therefore
make sure not to set the timer 1 interrupt request bit to “1” before
the STP instruction stops the oscillator. When the oscillator is re-
started by reset, apply “L” level to the RESET pin until the
oscillation is stable since a wait time will not be generated.
58
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCOUT
XCIN
“0”
“1”
Port XC
switch bit
XOUT
XIN
Main clock division ratio
selection bits (Note)
Low-speed mode
1/2
Prescaler 12
FF16
Timer 1
0116
1/4
1/2
High-speed or
middle-speed
mode
Reset or
STP instruction
Main clock division ratio
selection bits (Note)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Q
S
R
S Q
Q
S
R
STP instruction
STP instruction
WIT instruction
R
Reset
Interrupt disable flag l
Interrupt request
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
Fig. 60 System clock generating circuit block diagram (Single-chip mode)
59
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode
High-speed mode
(f(φ)=1.25 MHz)
(f(φ)=5 MHz)
CM
6
CM
CM
CM
CM
7
6
5
4
=0
=0
“1”←→“0”
CM
CM
CM
CM
7
6
5
4
=0
=1
=0(10 MHz oscillating)
=0(32 kHz stopped)
=0(10 MHz oscillating)
=0(32 kHz stopped)
C
”
M
“
”
0
4
0
“
←
C
”
M4
→
M
→
“
”
C
←
1
6
“
”
0
1
“
←
1
M6
”
“
→
→
“
C
←
”
0
1
”
“
High-speed mode
(f(φ)=5 MHz)
Middle-speed mode
(f(φ)=1.25 MHz)
CM
6
“1”←→“0”
CM
CM
CM
CM
7
=0
CM
7
6
5
4
=0
=0
6
5
4
=1
CM
CM
CM
=0(10 MHz oscillating)
=1(32 kHz oscillating)
=0(10 MHz oscillating)
=1(32 kHz oscillating)
C
M
“
7
0
”
←
C
M
→
“
6
1
“
1
”
←
”
→
“
0
”
Low-speed mode
(f(φ)=16 kHz)
CM
CM
CM
CM
7
=1
6
5
4
=0
=0(10 MHz oscillating)
=1(32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16
)
CM
CM
CM
4
5
7
: Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
: Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
, CM
6: Main clock division ratio selection bit
Low-speed mode
(f(φ)=16 kHz)
b7 b6
0
0
1
1
0 : φ = f(XIN)/2 ( High-speed mode)
1 : φ = f(XIN)/8 (Middle-speed mode)
0 : φ = f(XCIN)/2 (Low-speed mode)
1 : Not available
CM
CM
CM
CM
7
=1
=0
6
5
4
=1(10 MHz stopped)
=1(32 kHz oscillating)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
7 : The example assumes that 10 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 61 State transitions of system clock
60
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PROCESSOR MODE
Single-chip mode, memory expansion mode, and microprocessor
mode in the M38867M8A/E8A can be selected by changing the
contents of the processor mode bits (CM0 and CM1 : b1 and b0 of
address 003B16). In memory expansion mode and microprocessor
mode, memory can be expanded externally through ports P0 to
P3. In these modes, ports P0 to P3 lose their I/O port functions
and become bus pins.
000016
000816
000016
000816
SFR area
SFR area
004016
004016
Internal RAM
reserved area
Internal RAM
reserved area
Table 15 Port functions in memory expansion mode and
microprocessor mode
Function
Port Name
Port P0
*
*
XXXX16
XXXX16
Outputs low-order 8 bits of address.
Outputs high-order 8 bits of address.
Port P1
Operates as I/O pins for data D7 to D0
(including instruction code).
Port P2
*
YYYY16
P30 and P31 function only as output pins
(except that the port latch cannot be read).
Port P3
Internal ROM
P32 is the ONW input pin.
P33 is the RESETOUT output pin. (Note)
P34 is the φ output pin.
FFFF16
FFFF16
Memory expansion mode
Microprocessor mode
P35 is the SYNC output pin.
P36 is the WR output pin, and P37 is the RD out-
put pin.
The shaded area are external memory area.
*:
Note : If CNVSS is connected to VSS, the microcomputer goes to single-
chip mode after a reset, so that this pin cannot be used as the
RESETOUT output pin.
XXXX16 indicates the last address of internal RAM.
YYYY16 indicates the first address of internal ROM.
Fig. 62 Memory maps in various processor modes
(1) Single-chip mode
Select this mode by resetting the microcomputer with CNVSS con-
nected to VSS.
(2) Memory expansion mode
b7
b0
Select this mode by setting the processor mode bits (b1, b0) to
“01” in software with CNVSS connected to VSS. This mode enables
external memory expansion while maintaining the validity of the in-
ternal ROM.
CPU mode register
(CPUM : address 003B16
)
Processor mode bits (CM
b1 b0
1, CM0)
0
0
1
1
0: Single-chip mode
However, do not set this mode in the M38869M8A/MCA/MFA and
the flash memory version.
1: Memory expansion mode (Note)
0: Microprocessor mode (Note)
1: Not available
Stack page selection bit
0: 0 page
1: 1 page
(3) Microprocessor mode
Select this mode by resetting the microcomputer with CNVSS con-
nected to VCC, or by setting the processor mode bits to “10” in
software with CNVSS connected to VSS. In microprocessor mode,
the internal ROM is no longer valid and external memory must be
used.
Note: This is not available for the products except
M38867M8A/E8A.
Do not set this mode in the M38869M8A/MCA/MFA and the flash
memory version.
Fig. 63 Structure of CPU mode register
61
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
BUS CONTROL AT MEMORY EXPANSION
The M38867M8A/E8A have a built-in ONW function to facilitate
access to an external (expanded) memory and I/O devices in
memory expansion mode or microprocessor mode.
If an “L” level signal is input to the P32/ONW pin when the CPU is
in a read or write state, the corresponding read or write cycle is
extended by one cycle of φ. During this extended term, the RD
and WR signals remain at “L.” This extension function is valid only
for writing to and reading from addresses 000016 to 000716 and
044016 to FFFF16, and only read and write cycles are extended.
Dummy cycle
Read cycle Dummy cycle
Read cycle
Write cycle
Write cycle
φ
AD15—AD
RD
0
WR
ONW
*
*
*
* Term where ONW input signal is received.
During this term, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW
signal has no affect on operations. The bus cycles is not extended for an address in the area 000816 to 043F16,
because the ONW signal is not received.
Fig. 64 ONW function timing
62
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
EPROM MODE
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. The One Time PROM version and the built-in EPROM
version have the function of the M5M27C101 corresponding for
writing to the built-in PROM. Set the address of PROM program-
mer in the user ROM area.
Table 16 Programming adapter
Package
80P6Q-A
80D0
Name of Programming Adapter
PCA4738H-80A
PCA4738L-80A
Table 17 PROM programmer setup
PROM programmer setup
ROM area of
microcomputer
Product name
Corresponding
device
Writing
area
M5M27C101K
byte
program
M38867E8AHP
M38867E8AFS
0808016
|
0FFFD16
808016
|
FFFD16
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 65 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 65 Programming and testing of One Time PROM version
63
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLASH MEMORY MODE
Functional Outline (parallel input/output mode)
In the parallel input/output mode, the M38869FFAHP/GP allow the
user to choose an operation mode between the read-only mode
and the read/write mode (software command control mode) de-
pending on the voltage applied to the VPP pin. When VPP = VPPL,
the read-only mode is selected, and the user can choose one of
three states (e.g., read, output disable, or standby) depending on
The M38869FFAHP/GP has the flash memory mode in addition to
the normal operation mode (microcomputer mode). The user can
use this mode to perform read, program, and erase operations for
the internal flash memory.
The M38869FFAHP/GP has three modes the user can choose:
the parallel input/output and serial input/output mode, where the
flash memory is handled by using the external programmer, and
the CPU reprogramming mode, where the flash memory is
handled by the central processing unit (CPU). The following ex-
plains these modes.
___ ___
___
inputs to the CE, OE, and WE pins. When VPP = VPPH, the read/
write mode is selected, and the user can choose one of four states
(e.g., read, output disable, standby, or write) depending on inputs
__ __
___
to the CE, OE, and WE pins. Table 19 shows assignment states of
control input and each state.
(1) Flash memory mode 1 (parallel I/O mode)
The parallel I/O mode can be selected by connecting wires as
shown in Figures 65 and supplying power to the VCC and VPP
pins. In this mode, the M38869FFAHP/GP operates as an equiva-
lent of MITSUBISHI’s CMOS flash memory M5M28F101.
However, because the M38869FFAHP/GP’s internal memory has
a capacity of 60 Kbytes, programming is available for addresses
0100016 to 0FFFF16, and make sure that the data in addresses
0000016 to 00FFF16 and addresses 1000016 to 1FFFF16 are FF16.
Note also that the M38869FFAHP/GP does not contain a facility to
read out a device identification code by applying a high voltage to
address input (A9). Be careful not to erratically set program condi-
tions when using a general-purpose PROM programmer.
Table 18 shows the pin assignments when operating in the paral-
lel input/output mode.
● Read
__
The microcomputer enters the read state by driving the CE, and
__
___
OE pins low and the WE pin high; and the contents of memory
corresponding to the address to be input to address input pins
(A0–A16).
are output to the data input/output pins (D0–D7).
● Output disable
The microcomputer enters the output disable state by driving the
__
___
__
CE pin low and the WE and OE pins high; and the data input/out-
put pins enter the floating state.
● Standby
__
The microcomputer enters the standby state by driving the CE pin
high. the M38869FFAHP/GP is placed in a power-down state con-
suming only a minimal supply current. At this time, the data input/
output pins enter the floating state.
Table 18 Pin assignments of M38869FFAHP/GP when
operating in the parallel input/output mode
M38869FFAHP/GP
M5M28F101
VCC
● Write
VCC
CNVSS
VSS
VCC
VPP
The microcomputer enters the write state by driving the VPP pin
___
__
VPP
high (VPP = VPPH) and then the WE pin low when the CE pin is
__
VSS
VSS
low and the OE pin is high. In this state, software commands can
be input from the data input/output pins, and the user can choose
program or erase operation depending on the contents of this soft-
ware command.
Ports P0, P1, P31
Port P2
P36
Address input
A0–A16
Data I/O
D0–D7
__
CE
__
CE
___
OE
__
OE
P37
___
WE
___
WE
P33
Table 19 Assignment sates of control input and each state
Pin
__
__
OE
___
WE
CE
VPP
Data I/O
Mode
Read-only
State
Read
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
×
VIH
VIH
×
VPPL
VPPL
VPPL
VPPH
VPPH
VPPH
VPPH
Output
Floating
Floating
Output
Floating
Floating
Input
Output disable
Standby
Read
VIL
VIH
×
VIH
VIH
×
Output disable
Standby
Read/Write
Write
VIH
VIL
Note: × can be VIL or VIH.
64
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20 Pin description (flash memory parallel I/O mode)
Input
/Output
Pin
Name
Power supply
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
VCC, VSS
—
CNVSS
VPP input
Input
Input
Input
Output
—
Connect to 5 V ± 10 % in read-only mode, connect to 11.7 to 12.6 V in read/write mode.
Connect to VSS.
_____
RESET
XIN
Reset input
Clock input
Connect a ceramic resonator between XIN and XOUT.
XOUT
Clock output
AVSS
Analog supply input
Reference voltage input
Address input (A0–A7)
Address input (A8–A15)
Data I/O (D0–D7)
Control signal input
Connect to VSS.
VREF
Input
Input
Input
I/O
Connect to VSS.
P00–P07
P10–P17
P20–P27
P30–P37
Port P0 functions as 8-bit address input (A0–A7).
Port P1 functions as 8-bit address input (A8–A15).
Function as 8-bit data’s I/O pins (D0–D7).
__ __
___
P37, P36 and P33 function as the OE, CE and WE input pins respectively. P31 functions as
Input
the A16 input pin. Connect P30 and P32 to VSS. Input “H” or “L” to P34, P35, or keep
them open.
Connect P44, P46 to VSS. Input “H” or “L” to P40 - P43, P45, P47, or keep them open.
Input “H” or “L”, or keep them open.
P40–P47
P50–P57
P60–P67
P70–P77
P80–P87
Input port P4
Input port P5
Input port P6
Input port P7
Input port P8
Input
Input
Input
Input
Input
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
65
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
A16
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P1
P1
P2
P2
P2
6
7
0
1
2
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
P3
1
/PWM10
/PWM00
P30
P8
7/DQ
6/DQ
5/DQ
4/DQ
3/DQ
2/DQ
1/DQ
0/DQ
7
6
5
4
3
2
1
0
P8
P8
P8
P8
P8
P8
P8
P2
3
P2
P2
P2
P2
4
5
6
7
M38869FFAHP
M38869FFAGP
Vcc
V
X
X
SS
Vss
V
CC
REF
AVSS
OUT
IN
V
*
P6
P6
P6
P6
P6
7
/AN7
/AN6
/AN5
/AN4
/AN3
P4
P4
RESET
CNVSS
P4
P4
P4
0
/XCOUT
/XCIN
6
5
4
3
1
Vpp
2
3
4
/INT
/INT
0
/OBF00
/OBF01
1
P6
P6
2
/AN
/AN
2
1
/RXD
1
1
2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20
:Connect to the ceramic oscillation circuit.
indicates the flash memory pin.
*
Fig. 66 Pin connection of M38869FFAHP/GP when operating in parallel input/output mode
66
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
shown in Figure 67, and the M38869FFAHP/GP will output the
contents of the user’s specified address from data I/O pin to the
external. In this mode, the user cannot perform any operation
other than read.
Read-only Mode
The microcomputer enters the read-only mode by applying VPPL
to the VPP pin. In this mode, the user can input the address of a
memory location to be read and the control signals at the timing
VIH
Address
Valid address
tRC
VIL
VIH
CE
VIL
VIH
ta(CE)
OE
VIL
tWRR
tDF
VIH
WE
VIL
ta(OE)
tOLZ
tDH
VOH
Floating
Floating
Data
Dout
tCLZ
ta(AD)
VOL
Fig. 67 Read timing
Read/Write Mode
Table 21 shows the software commands and the input/output in-
The microcomputer enters the read/write mode by applying VPPH
to the VPP pin. In this mode, the user must first input a software
command to choose the operation (e. g., read, program, or erase)
to be performed on the flash memory (this is called the first cycle),
and then input the information necessary for execution of the com-
mand (e.g, address and data) and control signals (this is called
the second cycle). When this is done, the M38869FFAHP/GP ex-
ecutes the specified operation.
formation in the first and the second cycles. The input address is
___
latched internally at the falling edge of the WE input; software
commands and other input data are latched internally at the rising
___
edge of the WE input.
The following explains each software command. Refer to Figures 68
to 70 for details about the signal input/output timings.
Table 21 Software command (Parallel input/output mode)
First cycle
Second cycle
Symbol
Address input
Data input
0016
Address input
Data I/O
Read
×
Read address
Read data (Output)
Program data (Input)
Verify data (Output)
2016 (Input)
Program
×
4016
Program address
Program verify
Erase
×
C016
2016
×
×
×
Erase verify
Reset
Verify address
A016
×
Verify data (Output)
FF16 (Input)
×
×
FF16
×
Device identification
9016
ADI
DDI (Output)
Note: ADI = Device identification address : manufacturer’s code 0000016, device code 0000116
DDI = Device identification data : manufacturer’s code 1C16, device code D016
X can be VIL or VIH.
67
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Read command
The read mode is retained until any other command is latched into
the command latch. Consequently, once the M38869FFAHP/GP en-
ters the read mode, the user can read out the successive memory
contents simply by changing the input address and executing the
second cycle only. Any command other than the read command
must be input beginning from its command code over again each
time the user execute it. The contents of the command latch immedi-
ately after power-on is 0016.
The microcomputer enters the read mode by inputting command
code “0016” in the first cycle. The command code is latched into
___
the internal command latch at the rising edge of the WE input.
When the address of a memory location to be read is input in the
second cycle, with control signals input at the timing shown in
Figure 68, the M38869FFAHP/GP outputs the contents of the
specified address from the data I/O pins to the external.
V
IH
IL
Address
Valid address
V
t
WC
tRC
V
IH
IL
CE
OE
V
t
CH
t
a(CE)
t
CS
V
IH
IL
V
t
RRW
t
WP
t
WRR
tDF
V
IH
IL
WE
V
t
a(OE)
t
DS
V
IH
IL
t
OLZ
Data
0016
Dout
t
CLZ
V
t
DH
tDH
t
VSC
t
a(AD)
V
PP
H
L
VPP
V
PP
Fig. 68 Timings during reading
68
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Program command
● Program verify command
The microcomputer enters the program mode by inputting com-
The microcomputer enters the program verify mode by inputting
command code “C016” in the first cycle. This command is used to
verify the programmed data after executing the program com-
mand code “4016” in the first cycle. The command code is latched
___
into the internal command latch at the rising edge of the WE input.
When the address which indicates a program location and data is
mand. The command code is latched into the internal command
___
input in the second cycle, the M38869FFAHP/GP internally
latch at the rising edge of the WE input. When control signals are
input in the second cycle at the timing shown in Figure 69, the
M38869FFAHP/GP outputs the programmed address’s contents to
the external. Since the address is internally latched when the pro-
gram command is executed, there is no need to input it in the
second cycle.
___
latches the address at the falling edge of the WE input and the
___
data at the rising edge of the WE input. The M38869FFAHP/GP
___
starts programming at the rising edge of the WE input in the sec-
ond cycle and finishes programming within 10 µs as measured by
its internal timer. Programming is performed in units of bytes.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a pro-
gram verify command after executing the program command.
When the failure is found in this verification, the user must re-
peatedly execute the program command until the pass. Refer
to Figure 71 for the programming flowchart.
Program verify
V
V
IH
IL
Program
address
Address
Program
t
WC
t
AS
tAH
V
V
IH
IL
CE
t
CS
t
CS
tCS
t
CH
t
CH
tCH
V
V
IH
IL
OE
t
RRW
t
WP
tWPH
t
WP
t
DP
t
WP
tWRR
V
V
IH
IL
WE
Data
t
DS
tDS
tDS
V
V
IH
IL
4016
DIN
C016
Dout
tDH
t
DH
tDH
Verify data output
t
VSC
V
V
PP
H
L
VPP
PP
Fig. 69 Input/output timings during programming (Verify data is output at the same timing as for read.)
69
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Erase command
● Erase verify command
The erase command is executed by inputting command code 2016
in the first cycle and command code 2016 again in the second
The user must verify the contents of all addresses after complet-
ing the erase command. The microcomputer enters the erase
verify mode by inputting the verify address and command code
cycle. The command code is latched into the internal command
___
latch at the rising edges of the WE input in the first cycle and in
A016 in the first cycle. The address is internally latched at the fall-
___
ing edge of the WE input, and the command code is internally
___
the second cycle, respectively. The erase operation is initiated at
___
the rising edge of the WE input in the second cycle, and the
memory contents are collectively erased within 9.5 ms as mea-
sured by the internal timer. Note that data 0016 must be written to
all memory locations before executing the erase command.
Note: An erase operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the fail-
ure is found in this verification, the user must repeatedly ex-
ecute the erase command until the pass. Refer to Figure 71
for the erase flowchart.
latched at the rising edge of the WE input. When control signals
are input in the second cycle at the timing shown in Figure 70, the
M38869FFAHP/GP outputs the contents of the specified address
to the external.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the op-
eration of “erase → erase verify” over again. In this case,
however, the user does not need to write data 0016 to memory
locations before erasing.
Erase verify
V
V
IH
IL
Verify
address
Address
Erase
t
WC
t
AS
tAH
V
V
IH
IL
CE
t
CS
t
CS
tCS
t
CH
t
CH
tCH
V
V
IH
IL
OE
t
RRW
t
WP
tWPH
t
WP
t
DE
t
WP
tWRR
V
V
IH
IL
WE
Data
t
DS
tDS
tDS
V
V
IH
IL
2016
2016
A016
Dout
Verify data output
t
VSC
tDH
t
DH
tDH
V
V
PP
PP
H
L
V
PP
Fig. 70 Input/output timings during erasing (verify data is output at the same timing as for read.)
70
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Reset command
The reset command provides a means of stopping execution of
the erase or program command safely. If the user inputs command
code FF16 in the second cycle after inputting the erase or program
command in the first cycle and again input command code FF16 in
the third cycle, the erase or program command is disabled (i.e.,
reset), and the M38869FFAHP/GP is placed in the read mode. If
the reset command is executed, the contents of the memory does
not change.
● Device identification code command
By inputting command code 9016 in the first cycle, the user can
read out the device identification code. The command code is
latched into the internal command latch at the rising edge of the
___
WE input. At this time, the user can read out manufacture’s code
1C16 (i.e., MITSUBISHI) by inputting 000016 to the address input
pins in the second cycle; the user can read out device code D016
(i. e., 1M-bit flash memory) by inputting 000116.
These command and data codes are input/output at the same tim-
ing as for read.
71
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Program
Erase
START
START
V
CC = 5 V, VPP = VPP
H
V
CC = 5 V, VPP = VPP
H
ADRS = first location
X = 0
ALL
BYTES = 0016
YES
?
NO
PROGRAM
ALL BYTES = 0016
WRITE PROGRAM
COMMAND
4016
ADRS = first location
X = 0
WRITE PROGRAM
DATA
DIN
DURATION = 10 µs
X = X + 1
WRITE ERASE
COMMAND
2016
2016
WRITE ERASE
COMMAND
WRITE PROGRAM-VERIFY
COMMAND
C016
DURATION = 9.5 ms
DURATION = 6 µs
YES
X = X + 1
X = 25 ?
NO
WRITE ERASE-VERIFY
COMMAND
A016
PASS
FAIL
DURATION = 6 µs
VERIFY BYTE ?
VERIFY BYTE ?
FAIL
PASS
YES
X = 1000 ?
NO
NO
INC ADRS
LAST ADRS ?
YES
PASS
FAIL
VERIFY BYTE ?
PASS
VERIFY BYTE ?
FAIL
0016
WRITE READ COMMAND
V
PP = VPP
L
NO
INC ADRS
LAST ADRS ?
DEVICE
PASSED
DEVICE
FAILED
YES
0016
WRITE READ COMMAND
V
PP = VPP
L
DEVICE
PASSED
DEVICE
FAILED
Fig. 71 Programming/Erasing algorithm flow chart
72
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 22 DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
__
VCC = 5.5 V, CE = VIH
Unit
Min.
Max.
1
ISB1
mA
VCC supply current (at standby)
VCC supply current (at read)
VCC = 5.5 V,
__
ISB2
ICC1
100
15
µA
CE = VCC ± 0.2 V
__
VCC = 5.5 V, CE = VIL,
mA
tRC = 150 ns, IOUT = 0 mA
ICC2
ICC3
VCC supply current (at program)
VCC supply current (at erase)
VPP = VPPH
15
15
mA
mA
µA
µA
µA
mA
mA
V
VPP = VPPH
0≤VPP≤VCC
10
IPP1
VPP supply current (at read)
VCC<VPP≤VCC + 1.0 V
VPP = VPPH
100
100
30
IPP2
IPP3
VIL
VPP supply current (at program)
VPP supply current (at erase)
“L” input voltage
VPP = VPPH
VPP = VPPH
30
0
0.8
VIH
“H” input voltage
2.0
VCC
V
VOL
“L” output voltage
IOL = 2.1 mA
IOH = –400 µA
IOH = –100 µA
0.45
V
VOH1
VOH2
VPPL
VPPH
“H” output voltage
2.4
VCC –0.4
VCC
V
V
VPP supply voltage (read only)
VPP supply voltage (read/write)
V
CC + 1.0
V
11.7
12.0
12.6
V
AC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Table 23 Read-only mode
Limits
Symbol
Parameter
Unit
Min.
250
Max.
tRC
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
µs
ta(AD)
ta(CE)
ta(OE)
tCLZ
tOLZ
tDF
Address access time
250
250
100
__
CE access time
__
OE access time
__
Output enable time (after CE)
0
0
__
Output enable time (after OE)
__
Output floating time (after OE)
35
__ __
Output valid time (after CE, OE, address)
Write recovery time (before read)
tDH
0
6
tWRR
Table 24 Read/Write mode
Limits
Symbol
Parameter
Unit
Min.
150
0
Max.
tWC
tAS
Write cycle time
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
µs
ms
µs
Address set up time
Address hold time
Data setup time
tAH
60
50
10
6
tDS
tDH
Data hold time
tWRR
tRRW
tCS
Write recovery time (before read)
Read recovery time (before write)
0
__
CE setup time
__
20
0
tCH
CE hold time
tWP
tWPH
tDP
Write pulse width
Write pulse waiting time
Program time
60
20
10
9.5
1
tDE
Erase time
tVSC
VPP setup time
Note: Read timing of Read/Write mode is same as Read-only mode.
73
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Flash memory mode 2 (serial I/O mode)
The M38869FFAHP/GP has a function to serially input/output the
software commands, addresses, and data required for operation
on the internal flash memory (e. g., read, program, and erase) us-
ing only a few pins. This is called the serial I/O (input/output)
connecting wires as shown in Figures 72 and powering on the VCC
pin and then applying VPPH to the VPP pin.
In the serial I/O mode, the user can use six types of software com-
mands: read, program, program verify, erase, erase verify and
error check.
mode. This mode can be selected by driving the SDA (serial data
Serial input/output is accomplished synchronously with the clock,
beginning from the LSB (LSB first).
__
input/output), SCLK (serial clock input ), and OE pins high after
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
P31/PWM10
P30/PWM00
P87/DQ7
P86/DQ6
P85/DQ5
P84/DQ4
P83/DQ3
P82/DQ2
P81/DQ1
P80/DQ0
VCC
M38869FFAHP
M38869FFAGP
Vss
Vcc
VREF
AVSS
*
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P40/XCOUT
P41/XCIN
RESET
Vpp
CNVSS
P42/INT0/OBF00
P43/INT1/OBF01
P44/RXD
SDA
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
:Connect to the ceramic oscillation circuit.
indicates the flash memory pin.
*
Fig. 72 Pin connection of M38869FFAHP/GP when operating in serial I/O mode
74
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 25 Pin description (flash memory serial I/O mode)
Input
/Output
Pin
Name
Power supply
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
VCC, VSS
—
CNVSS
VPP input
Input
Input
Input
Output
—
Connect to 11.7 to 12.6 V.
_____
RESET
XIN
Reset input
Connect to VSS.
Clock input
Connect a ceramic resonator between XIN and XOUT.
XOUT
Clock output
AVSS
Analog supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
Connect to VSS.
VREF
Input
Input
Input
Input
Input
Input
Input
Input an arbitrary level between the range of VSS and VCC.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
P00–P07
P10–P17
P20–P27
Input “H” or “L”, or keep them open.
__
OE input pin
P30–P36
P37
Input port P3
Control signal input
Input port P4
P40–P43,
P45
Input “H” or “L” to P40 - P43, P45, or keep them open.
P44
SDA I/O
I/O
This pin is for serial data I/O.
This pin is for serial clock input.
P46
SCLK input
BUSY output
Input port P5
Input port P6
Input port P7
Input port P8
Input
P47
Output This pin is for BUSY signal output.
P50–P57
P60–P67
P70–P77
P80–P87
Input
Input
Input
Input
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
75
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Functional Outline (serial I/O mode)
Data is transferred in units of eight bits.
In the serial I/O mode, data is transferred synchronously with the
clock using serial input/output. The input data is read from the
SDA pin into the internal circuit synchronously with the rising edge
of the serial clock pulse; the output data is output from the SDA
pin synchronously with the falling edge of the serial clock pulse.
In the first transfer, the user inputs the command code. This is fol-
lowed by address input and data input/output according to the
contents of the command. Table 26 shows the software com-
mands used in the serial I/O mode. The following explains each
software command.
Table 26 Software command (serial I/O mode)
Number of transfers First command
Second
Third
Fourth
Command
Read
code input
0016
Read address L (Input)
Program address L (Input)
Verify data (Output)
2016 (Input)
Read address H (Input)
Program address H (Input)
—————
Read data (Output)
Program data (Input)
—————
Program
4016
Program verify
Erase
C016
2016
—————
—————
Erase verify
Error check
A016
Verify address L (Input)
Error code (Output)
Verify address H (Input)
—————
Verify data (Output)
—————
8016
__
● Read command
into the internal data latch. When the OE pin is released back high
and serial clock is input to the SCLK pin, the read data that has
been latched into the data latch is serially output from the SDA
pin.
Input command code 0016 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
__
pull the OE pin low. When this is done, the M38869FFAHP/GP
reads out the contents of the specified address, and then latchs it
tCH
tCH
SCLK
SDA
A
0
A
7
A
8
A
15
D
0
D7
0 0 0 0 0 0 0 0
Command code input (0016
)
Read address input (L)
Read address input (H)
Read data output
t
CR
tWR
tRC
OE
Read
“L”
BUSY
Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 73 Timings during reading
76
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Program command
Note : A programming operation is not completed by executing the
program command once. Always be sure to execute a pro-
gram verify command after executing the program command.
When the failure is found in the verification, the user must re-
peatedly execute the program command until the pass in the
verification. Refer to Figure 71 for the programming flowchart.
Input command code 4016 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
then program data. Programming is initiated at the last rising edge
of the serial clock during program data transfer. The BUSY pin is
driven high during program operation. Programming is completed
within 10 µs as measured by the internal timer, and the BUSY pin
is pulled low.
tCH
t
CH
tCH
SCLK
SDA
t
PC
D0
D7
A0
A7
A8
A15
0 0 0 0 0 0 1 0
Program data input
Command code input (4016
)
Program address input (L) Program address input (H)
OE
tWP
Program
BUSY
Fig. 74 Timings during programming
__
● Program verify command
the internal data latch. When the OE pin is released back high and
serial clock is input to the SCLK pin, the verify data that has been
latched into the data latch is serially output from the SDA pin.
Input command code C016 in the first transfer. Proceed and drive
__
the OE pin low. When this is done, The M38869FFAHP/GP verify-
reads the programmed address’s contents, and then latchs it into
SCLK
D0
D7
SDA
0 0 0 0 0 0 1 1
Command code input (C016
)
Verify data output
t
CRPV
tWR
tRC
OE
Verify read
BUSY
“L”
Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 75 Timings during program verify
77
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Erase command
tions before executing the erase command.
Input command code 2016 in the first transfer and command code
2016 again in the second transfer. When this is done, the
M38869FFAHP/GP executes an erase command. Erase is initi-
ated at the last rising edge of the serial clock. The BUSY pin is
driven high during the erase operation. Erase is completed within
9.5 ms as measured by the internal timer, and the BUSY pin is
pulled low. Note that data 0016 must be written to all memory loca-
Note: A erase operation is not completed by executing the erase
command once. Always be sure to execute a erase verify
command after executing the erase command. When the fail-
ure is found in the verification, the user must repeatedly ex-
ecute the erase command until the pass in the verification.
Refer to Figure 71 for the erase flowchart.
t
CH
SCLK
SDA
t
EC
0 0 0 0 0 1 0 0
Command code input (2016
0 0 0 0 0 1 0 0
Command code input (2016
)
)
“H”
OE
twE
BUSY
Erase
Fig. 76 Timings at erasing
● Erase verify command
the verify data that has been latched into the data latch is serially
output from the SDA pin.
The user must verify the contents of all addresses after complet-
ing the erase command. Input command code A016 in the first
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the op-
eration of “erase → erase verify” over again. In this case,
however, the user does not need to write data 0016 to memory
locations before erasing.
transfer. Proceed and input the low-order 8 bits and the high-order
__
8 bits of the address and pull the OE pin low. When this is done,
the M38869FFAHP/GP reads out the contents of the specified ad-
__
dress, and then latchs it into the internal data latch. When the OE
pin is released back high and serial clock is input to the SCLK pin,
tCH
tCH
SCLK
SDA
A
0
A
7
A
8
A
15
D
0
D7
0 0 0 0 0 1 0 1
Command code input (A016
)
Verify address input (L)
Verify address input (H)
Verify data output
t
CREV
tWR
tRC
OE
Verify read
“L”
BUSY
Note : When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
Fig. 77 Timings during erase verify
78
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Error check command
temporarily drop the VPP pin input to the VPPL level to terminate
the serial input/output mode. Then, place the M38869FFAHP/GP
into the serial I/O mode back again. The serial communication cir-
cuit is reset by this operation and is ready to accept commands.
The error flag alone is not cleared by this operation, so the user
can examine the serial communication circuit’s error conditions
before reset. This examination is done by the first execution of an
error check command after the reset. The error flag is cleared
when the user has executed the error check command. Because
the error flag is undefined immediately after power-on, always be
sure to execute the error check command.
Input command code 8016 in the first transfer, and the
M38869FFAHP/GP outputs error information from the SDA pin,
beginning at the next falling edge of the serial clock. If the LSB bit
of the 8-bit error information is 1, it indicates that a command error
has occurred. A command error means that some invalid com-
mands other than commands shown in Table 26 has been input.
When a command error occurs, the serial communication circuit
sets the corresponding flag and stops functioning to avoid an erro-
neous programming or erase. When being placed in this state, the
serial communication circuit does not accept the subsequent serial
clock and data (even including an error check command). There-
fore, if the user wants to execute an error check command,
t
CH
SCLK
E0
SDA
? ? ? ? ? ?
?
0 0 0 0 0 0 0 1
Command code input (8016
)
Error flag output
“H”
OE
BUSY
“L”
Note: When outputting the error flag, the SDA pin is switched for output at the first falling edge of the serial clock. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of the serial clock (at the 8th bit).
Fig. 78 Timings at error checking
Note: The programming/erasing algorithm flow chart of the serial
I/O mode is the same as that of the parallel I/O mode. Re-
fer to Figure 71.
79
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, unless otherwise noted)
ICC, IPP-relevant standards during read, program, and erase are the same as in the parallel input/output mode. VIH, VIL, VOH, VOL, IIH, and
__
IIL for the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes.
Table 27 AC Electrical characteristics
(Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, f(XIN) = 10 MHz, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Max.
(Note 1)
tCH
tCR
Serial transmission interval
Read waiting time after transmission
Read pulse width
500
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 2)
(Note 1)
500
400
500
tWR
tRC
Transfer waiting time after read
Waiting time before program verify
Programming time
tCRPV
tWP
6
10
(Note 1)
tPC
Transfer waiting time after programming
Waiting time before erase verify
Erase time
500
500
tCREV
tWE
6
9.5
(Note 1)
tEC
Transfer waiting time after erase
SCLK input cycle time
tc(CK)
tw(CKH)
tw(CKL)
tr(CK)
tf(CK)
td(C-Q)
th(C-Q)
th(C-E)
tsu(D-C)
th(C-D)
250
100
100
20
SCLK high-level pulse width
SCLK low-level pulse width
SCLK rise time
SCLK fall time
20
SDA output delay time
0
90
SDA output hold time
0
(Note 3)
(Note 4)
SDA output hold time (only the 8th bit)
SDA input set up time
150
250
30
90
SDA input hold time
Notes 1: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 1.
5000
f(XIN)
Formula 1 :
× 106
2: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 2.
4000
f(XIN)
Formula 2 :
× 106
3: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 3.
1500
f(XIN)
Formula 3 :
× 106
4: When f(XIN) = 10 MHz or less, calculate the minimum value according to formula 4
2500
f(XIN)
Formula 4 :
× 106
AC waveforms
tc(CK)
tr(CK)
tf(CK)
tw(CKL)
tw(CKH)
SCLK
th(C-Q)
td(C-Q)
th(C-E)
Test conditions for AC characteristics
SDA output
SDA input
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC
tsu(D-C)
th(C-D)
80
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(3) Flash memory mode 3 (CPU reprogramming
mode)
The M38869FFAHP/GP has the CPU reprogramming mode where
a built-in flash memory is handled by the central processing unit
(CPU).
Whether these operations have been completed or not is judged
by checking this flag after each command of erase and the pro-
gram is executed.
Bits 4, 5 of the flash memory control register are the erase/pro-
gram area select bits. These bits specify an area where erase and
program is operated. When the erase command is executed after
an area is specified by these bits, only the specified area is
erased. Only for the specified area, programming is enabled; for
the other areas, programming is disabled.
In CPU reprogramming mode, the flash memory is handled by
writing and reading to/from the flash memory control register (see
Figure 79) and the flash command register (see Figure 80).
The CNVSS pin is used as the VPP power supply pin in CPU repro-
gramming mode. It is necessary to apply the power-supply voltage
of VPPH from the external to this pin.
When CPU reprogramming mode is valid, the area where is not
specified by the erase/program area select bits cannot be read
out.
Functional Outline (CPU reprogramming mode)
Figure 79 shows the flash memory control register bit configura-
tion. Figure 80 shows the flash command register bit
configuration.
Transfer CPU reprogramming mode control program to internal
RAM before entering the CPU reprogramming mode, and then ex-
ecute this program on internal RAM.
If an interrupt occurs while this program is being executed, the
flash memory area is accessed, but normally operation cannot be
performed because the flash memory area cannot be read out.
During CPU reprogramming mode control program execution, ex-
ecute the processing such as interrupt disabled, etc.
Figure 81 shows the CPU mode register bit configuration in the
CPU reprogramming mode. Set bits 1 and 0 to “00” (single-chip
mode) in the CPU reprogramming mode.
Bit 0 of the flash memory control register is the CPU reprogram-
ming mode select bit. When this bit is set to “1” and VPPH is
applied to the CNVss/VPP pin, the CPU reprogramming mode is
selected. Whether the CPU reprogramming mode is realized or
not is judged by reading the CPU reprogramming mode monitor
flag (bit 2 of the flash memory control register).
Bit 1 is a busy flag which becomes “1” during erase and program
execution.
7
6
0
5
4
3
0
2
1
0
Flash memory control regsiter
(FCON : address 0FFE16
)
CPU reprogramming mode select bit (Note)
0 : CPU reprogramming mode is invalid. (Normal operation mode)
1 : When applying 0 V or VPPL to CNVSS/VPP pin, CPU reprogramming mode is
invalid. When applying VPPH to CNVSS/VPP pin, CPU reprogramming mode is valid.
Erase/Program busy flag
0 : Erase and program are completed or not have been executed.
1 : Erase/program is being executed.
CPU reprogramming mode monitor flag
0 : CPU reprogramming mode is invalid.
1 : CPU reprogramming mode is valid.
Fix this bit to “0.”
Erase/Program area select bits
0 0 : Addresses 100016 to FFFF16 (total 60 Kbytes)
0 1 : Addresses 100016 to 7FFF16 (total 28 Kbytes)
1 0 : Addresses 800016 to FFFF16 (total 32 Kbytes)
1 1 : Not available
Fix this bit to “0.”
Not used (returns "0" when read)
Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNVSS/VPP pin.
Fig. 79 Flash memory control register bit configuration
81
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● CPU reprogramming mode operation procedure
The operation procedure in CPU reprogramming mode is de-
scribed below.
< Release procedure >
➀Apply 0V to the CNVSS/VPP pin.
➁ Wait till CNVSS/VPP pin becomes 0V.
➂ Set the CPU reprogramming mode select bit to “0.”
< Beginning procedure >
➀Apply 0 V to the CNVss/VPP pin for reset release.
➁After CPU reprogramming mode control program is transferred to
internal RAM, jump to this control program on RAM. (The follow-
ing operations are controlled by this control program).
➂ Set “1" to the CPU reprogramming mode select bit.
➃Apply VPPH to the CNVSS/VPP pin.
Each software command is explained as follows.
● Read command
When “0016" is written to the flash command register, the
M38869FFAHP/GP enters the read mode. The contents of the
corresponding address can be read by reading the flash memory
(For instance, with the LDA instruction etc.) under this condition.
The read mode is maintained until another command code is written
to the flash command register. Accordingly, after setting the read
mode once, the contents of the flash memory can continuously be
read.
➄ Wait till CNVSS/VPP pin becomes 12 V.
➅ Read the CPU reprogramming mode monitor flag to confirm
whether the CPU reprogramming mode is valid.
➆ The operation of the flash memory is executed by software-com-
mand-writing to the flash command register .
Note: The following are necessary other than this:
•Control for data which is input from the external (serial I/O
etc.) and to be programmed to the flash memory
•Initial setting for ports etc.
After reset and after the reset command is executed, the read
mode is set.
•Writing to the watchdog timer
b7
b0
CPU mode register
7
6
5
4
3
2
1
0
0
0
(CPUM : address 003B16)
Flash command register
(FCMD : address 0FFF16
)
Processor mode bits
b1 b0
0
0
1
0
1
X
: Single-chip mode
: Not available
: Not available
Writing of software command
<Software command name>
• Read command
<Command code>
Stack page selection bit
0
1
: 0 page
: 1 page
“0016
”
”
• Program command
• Program verify command
• Erase command
“4016
Reserved
(Do not write “0” to this bit when using
XCIN–XCOUT oscillation function.)
“C016
“2016” + “2016
“A016
“FF16” + “FF16
”
”
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
• Erase verify command
• Reset command
”
”
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0
0
1
1
0
1
0
1
: φ = f(XIN)/2 (high-speed mode)
: φ = f(XIN)/8 (middle-speed mode)
: φ = f(XCIN)/2 (low-speed mode)
: Not available
Note: The flash command register is write-only register.
Fig. 80 Flash command register bit configuration
Fig. 81 CPU mode register bit configuration in CPU rewriting
mode
82
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● Program command
● Erase verify command
When “4016” is written to the flash command register, the
M38869FFAHP/GP enters the program mode.
When “A016” is written to the flash command register, the
M38869FFAHP/GP enters the erase verify mode. Subsequently to
this, if the instruction (for instance, LDA instruction) for reading
byte data from the address to be verified, the contents of the ad-
dress is read.
Subsequently to this, if the instruction (for instance, STA
instruction) for writing byte data in the address to be programmed
is executed, the control circuit of the flash memory executes the
program. The erase/program busy flag of the flash memory control
register is set to “1” when the program starts, and becomes “0”
when the program is completed. Accordingly, after the write in-
struction is executed, CPU can recognize the completion of the
program by polling this bit.
CPU must erase and verify to all erased areas in a unit of ad-
dress.
If the address of which data is not “FF16” (i.e., data is not erased)
is found, it is necessary to discontinue erasure verification there,
and execute the operation of “erase → erase verify” again.
Note: By executing the operation of “erase → erase verify” again
when the memory not erased is found. It is unnecessary to
write data “0016” before erasing in this case.
The programmed area must be specified beforehand by the erase/
program area select bits.
During programming, watchdog timer stops with “FFFF16” set.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a pro-
gram verify command after executing the program command.
When the failure is found in this verification, the user must re-
peatedly execute the program command until the pass. Refer
to Figure 82 for the flow chart of the programming.
● Reset command
The reset command is a command to discontinue the program or
erase command on the way. When “FF16” is written to the command
register two times continuously after “4016” or “2016” is written to the
flash command register, the program, or erase command becomes
invalid (reset), and the M38869FFAHP/GP enters the reset mode.
The contents of the memory does not change even if the reset com-
mand is executed.
● Program verify command
When “C016” is written to the flash command register, the
M38869FFAHP/GP enters the program verify mode. Subsequently
to this, if the instruction (for instance, LDA instruction) for reading
byte data from the address to be verified (i.e., previously pro-
grammed address), the contents which has been written to the
address actually is read.
DC Electric Characteristics
Note: The characteristic concerning the flash memory part are the
same as the characteristic of the parallel I/O mode.
CPU compares this read data with data which has been written by
the previous program command. In consequence of the compari-
son, if not agreeing, the operation of “program → program verify”
must be executed again.
AC Electric Characteristics
Note: The characteristics are the same as the characteristic of the
microcomputer mode.
● Erase command
When writing “2016” twice continuously to the flash command reg-
ister, the flash memory control circuit performs erase to the area
specified beforehand by the erase/program area select bits.
Erase/program busy flag of the flash memory control register be-
comes “1” when erase begins, and it becomes “0” when erase
completes. Accordingly, CPU can recognize the completion of
erase by polling this bit.
Data “0016” must be written to all areas to be erased by the pro-
gram and the program verify commands before the erase
command is executed.
During erasing, watchdog timer stops with “FFFF16” set.
Note: The erasing operation is not completed by executing the erase
command once. Always be sure to execute an erase verify
command after executing the erase command. When the fail-
ure is found in this verification, the user must repeatedly ex-
ecute the erase command until the pass. Refer to Figure 82 for
the erasing flowchart.
83
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Program
Erase
START
ADRS = first location
X = 0
START
ALL
YES
BYTES = 0016
?
NO
PROGRAM
WRITE PROGRAM
COMMAND
ALL BYTES = 0016
ADRS = first location
X = 0
4016
DIN
WRITE PROGRAM
DATA
WAIT 1µs
WRITE ERASE
COMMAND
2016
2016
NO
ERASE PROGRAM
BUSY FLAG = 0
WRITE ERASE
COMMAND
YES
X = X + 1
WAIT 1µs
WRITE PROGRAM-VERIFY
COMMAND
C016
NO
ERASE PROGRAM
BUSY FLAG = 0
DURATION = 6 µs
YES
X = X + 1
YES
X = 25 ?
WRITE ERASE-VERIFY
COMMAND
A016
NO
PASS
FAIL
DURATION = 6 µs
VERIFY BYTE ?
VERIFY BYTE ?
PASS
FAIL
YES
X = 1000 ?
NO
NO
INC ADRS
LAST ADRS ?
YES
PASS
FAIL
VERIFY BYTE ?
PASS
VERIFY BYTE ?
FAIL
0016
WRITE READ COMMAND
DEVICE
FAILED
NO
DEVICE
PASSED
INC ADRS
LAST ADRS ?
YES
0016
WRITE READ COMMAND
DEVICE
PASSED
DEVICE
FAILED
Fig. 82 Flowchart of program/erase operation at CPU reprogramming mode
84
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NOTES ON PROGRAMMING
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY1 signal, set the transmit
enable bit, the receive enable bit, and the SRDY1 output enable bit
to “1.”
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed. SOUT2 pin for serial I/O2 goes to high
impedance after transfer is completed.
When in serial I/O1 (clock-synchronous mode) or in serial I/O2, an
external clock is used as synchronous clock, write transmission
data to the transmit buffer register or serial I/O2 register, during
transfer clock is “H.”
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an
A-D conversion.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
D-A Converter
The accuracy of the D-A converter becomes rapidly poor under
the VCC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0 V
is recommended. When a D-A converter is not used, set all values
of D-Ai conversion registers (i=1, 2) to “0016.”
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
Instruction Execution Time
The instruction execution time is obtained by multiplying the pe-
riod of the internal clock φ by the number of cycles needed to
execute an instruction.
• The execution of these instructions does not change the con-
tents of the processor status register.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Ports
The period of the internal clock φ is half of the XIN period in high-
speed mode.
The contents of the port direction registers cannot be read. The
following cannot be used:
When the ONW function is used in modes other than single-chip
mode, the period of the internal clock φ may be four times that of
the XIN.
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The instruction with the addressing mode which uses the value
of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
85
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NOTES ON USAGE
Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin), between power
source pin (VCC pin) and analog power source input pin (AVSS
pin), and between program power source pin (CNVss/VPP) and
GND pin for flash memory version when on-board reprogramming
is executed. Besides, connect the capacitor to as close as pos-
sible. For bypass capacitor which should not be located too far
from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1
µF is recommended.
EPROM version/One Time PROM version/
Flash memory version
The CNVSS pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVSS
pin and VSS pin or VCC pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVSS pin has no operational in-
terference even if it is connected to Vss pin or Vcc pin via a
resistor.
Erasing of Flash memory version
Set addresses 0100016 to 0FFFF16 as memory area for erasing in
the parallel serial I/O mode and the serial I/O mode. If the memory
area for erasing is set to mistaken area, the product may be per-
manently damaged.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1.Mask ROM Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop-
ies)
DATA REQUIRED FOR One Time PROM
PROGRAMMING ORDERS
The following are necessary when ordering a PROM programming
service:
1.ROM Programming Confirmation Form
2.Mark Specification Form
3.Data to be programmed to PROM, in EPROM form (three identi-
cal copies)
86
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ELECTRICAL CHARACTERISTICS
Table 28 Absolute maximum ratings
Symbol
Parameter
Power source voltageS (Note 1)
Power source voltageS (Note 2)
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
–0.3 to 6.5
VCC
V
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
VI
–0.3 to VCC +0.3
V
P60–P67, P80–P87, VREF
VI
VI
VI
VI
VI
Input voltage P70–P77
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to 7
V
V
V
V
V
Input voltage RESET, XIN
Input voltage CNVSS (Note 3)
Input voltage CNVSS (Note 4)
All voltages are based on VSS.
Output transistors are cut off.
–0.3 to VCC +0.3
–0.3 to 13
Input voltage
CNVSS (Note 5)
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
VO
–0.3 to VCC +0.3
V
P60–P67, P80–P87, XOUT
VO
Output voltage P70–P77
Power dissipation
–0.3 to 5.8
500
V
mW
°C
Pd
Ta = 25 °C
Topr
Tstg
Operating temperature
Storage temperature
–20 to 85
–40 to 125
°C
Notes 1: M38867M8A, M38867E8A
2: M38869M8A, M38869MCA, M38869MFA, M38869FFA
3: M38867M8A
4: M38869M8A, M38869MCA, M38869MFA
5: M38867E8A, M38869FFA
87
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Table 29 Recommended operating conditions
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
5.0
5.0
5.0
0
Symbol
Parameter
Unit
V
Min.
2.7
4.0
4.0
Max.
5.5
f(XIN) ≤ 4.1 MHz
f(XIN) = 10 MHz
VCC
Power source voltage (except flash memory version)
5.5
VCC
VSS
V
V
Power source voltage (flash memory version)
Power source voltage
5.5
when A-D converter is used
when D-A converter is used
2.0
2.7
VCC
VCC
VREF
V
Analog reference voltage
AVSS
VIA
Analog power source voltage
V
V
0
A-D converter input voltage AN0–AN7
AVSS
VCC
VCC
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40, P41,
P47, P50–P57, P60–P67, P80–P87
V
0.8VCC
VIH
VIH
VIH
“H” input voltage
P76, P77
0.8VCC
0.7VCC
V
V
5.5
5.5
2
“H” input voltage (when I C-BUS input level is selected)
SDA, SCL
“H” input voltage (when SMBUS input level is selected)
SDA, SCL
“H” input voltage (when CMOS input level is selected)
VIH
VIH
VIH
VIH
V
V
V
V
1.4
0.8VCC
0.8VCC
2.0
5.5
VCC
5.5
P42–P46, DQ0–DQ7, W, R, S0, S1, A0
“H” input voltage (when CMOS input level is selected)
P70–P75
“H” input voltage (when TTL input level is selected)
VCC
P42–P46, DQ0–DQ7, W, R, S0, S1, A0 (Note)
“H” input voltage (when TTL input level is selected)
VIH
VIH
VIL
VIL
V
V
V
2.0
0.8VCC
0
5.5
VCC
P70–P75 (Note)
“H” input voltage
“L” input voltage
RESET, XIN, XCIN, CNVSS
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87
0.2VCC
2
“L” input voltage (when I C-BUS input level is selected)
SDA, SCL
V
V
V
V
0
0
0
0
0.3VCC
0.6
“L” input voltage (when SMBUS input level is selected)
SDA, SCL
VIL
VIL
VIL
“L” input voltage (when CMOS input level is selected)
0.2VCC
P42–P46, P70–P75, DQ0–DQ7, W, R, S0, S1, A0
“L” input voltage (when TTL input level is selected)
P42–P46, P70–P75, DQ0–DQ7, W, R, S0, S1, A0 (Note)
RESET, CNVSS
XIN, XCIN
0.8
VIL
VIL
0
0
0.2VCC
“L” input voltage
“L” input voltage
V
V
0.16
VCC
Note : When VCC is 4.0 to 5.5 V.
88
MITSUBISHI MICROCOMPUTERS
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Table 30 Recommended operating conditions
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
–80
–80
80
“H” total peak output current
“H” total peak output current
“L” total peak output current
P0
P40–P47, P50–P57, P60–P67 (Note)
P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3
In single-chip mode
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P8
, P8
0
0
–P8
–P8
7
7
(Note)
(Note)
mA
mA
mA
mA
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
0
7
0
7
0
3
0
7
80
“L” total peak output current
P24–P27 (Note)
ΣIOL(peak)
In memory expansion mode
In microprocessor mode
40
mA
“L” total peak output current
P40–P47,P50–P57, P60–P67, P70–P77 (Note)
80
–40
–40
40
mA
mA
mA
mA
mA
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
“H” total average output current P0
“H” total average output current P40–P47,P50–P57, P60–P67 (Note)
“L” total average output current P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3
In single-chip mode
“L” total average output current
P24–P27 (Note)
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0–P3
7
, P8
0
–P8
7
(Note)
(Note)
0
7
0
7
0
3
0
7
, P8
0
–P8
7
40
ΣIOL(avg)
ΣIOL(avg)
In memory expansion mode
In microprocessor mode
40
40
mA
mA
“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note)
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
89
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Table 31 Recommended operating conditions
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
mA
Min.
Max.
–10
“H” peak output current
“L” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 1)
IOH(peak)
IOL(peak)
P00–P07, P10–P17, P20–P23, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 1)
mA
mA
10
20
In single-chip mode
“L” peak output current
P24–P27 (Note 1)
IOL(peak)
In memory expansion mode
In microprocessor mode
mA
mA
10
–5
“H” average output current
“L” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 2)
IOH(avg)
IOL(avg)
P00–P07, P10–P17, P20–P23, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)
mA
mA
5
In single-chip mode
15
“L” peak output current
P24–P27 (Note 2)
IOL(avg)
In memory expansion mode
In microprocessor mode
mA
5
High-speed mode
4.0 V≤ VCC ≤ 5.5 V
MHz
10
High-speed mode
2.7 V≤ VCC ≤ 4.0 V
MHz
MHz
4.5 VCC–8
Main clock input oscillation
frequency (Note 3)
Middle-speed mode
4.0 V≤ VCC ≤ 5.5 V
f(XIN)
10
Middle-speed mode
2.7 V≤ VCC ≤ 4.0 V (Note 5)
MHz
10
Middle-speed mode
2.7 V≤ VCC ≤ 4.0 V (Note 5)
MHz
kHz
4.5 VCC–8
f(XCIN)
Sub-clock input oscillation frequency (Notes 3, 4)
32.768
50
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
4: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
5: When using the timer X/Y, timer 1/2, serial I/O1, serial I/O2, A-D converter, comparator, and PWM, set the main clock input oscillation frequency to
the max. 4.5VCC–8 (MHz).
90
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 32 Electrical characteristics
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
“H” output voltage
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P80–P87 (Note)
Unit
Test conditions
IOH = –10 mA
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 2.7–5.5 V
Min.
Typ.
Max.
VCC–2.0
VCC–1.0
V
V
VOH
VOL
“L” output voltage
IOL = 10 mA
VCC = 4.0–5.5 V
IOL = 1.6 mA
2.0
0.4
V
V
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
VCC = 2.7–5.5 V
Hysteresis
CNTR0, CNTR1, INT0, INT1
INT20–INT40, INT21–INT41
P30–P37
VT+–VT–
0.4
V
Hysteresis
RxD, SCLK1, SIN2, SCLK2
VT+–VT–
VT+–VT–
V
V
0.5
0.5
Hysteresis RESET
“H” input current
VI = VCC
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
IIH
(Pin floating. Pull-up
5.0
5.0
µA
transistors “off”)
“H” input current RESET, CNVSS
“H” input current XIN
VI = VCC
VI = VCC
µA
µA
IIH
IIH
4
“L” input current
VI = VSS
(Pin floating. Pull-up
transistors “off”)
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47, P50–P57
P60–P67, P70–P77, P80–P87
IIL
µA
–5.0
–5.0
IIL
IIL
µA
µA
“L” input current
“L” input current
RESET,CNVSS
XIN
VI = VSS
VI = VSS
–4
VI = VSS
VCC = 4.0–5.5 V
VI = VSS
–20
–60
–120
µA
“L” input current
P30–P37 (at Pull-up)
IIL
–10
2.0
µA
VCC = 2.7–5.5 V
5.5
V
When clock stopped
VRAM
RAM hold voltage
Note: P00–P03 are measured when the P00–P03 output structure selection bit of the port control register 1 (bit 0 of address 002E16) is “0”.
P04–P07 are measured when the P04–P07 output structure selection bit of the port control register 1 (bit 1 of address 002E16) is “0”.
P10–P13 are measured when the P10–P13 output structure selection bit of the port control register 1 (bit 2 of address 002E16) is “0”.
P14–P17 are measured when the P14–P17 output structure selection bit of the port control register 1 (bit 3 of address 002E16) is “0”.
P42, P43, P44, and P46 are measured when the P4 output structure selection bit of the port control register 2 (bit 2 of address 002F16) is “0”.
P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
91
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 33 Electrical characteristics
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
mA
Test conditions
High-speed mode
f(XIN) = 10 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
Typ.
Max.
15
Min.
8.0
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
mA
mA
µA
µA
µA
µA
mA
6.8
1.6
60
13
High-speed mode
f(XIN) = 10 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
200
40
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
20
ICC
Power source current
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
20
55
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
8.0
20.0
7.0
Middle-speed mode
f(XIN) = 10 MHz
f(XCIN) = stopped
Output transistors “off”
4.0
1.5
Middle-speed mode
f(XIN) = 10 MHz (in WIT state)
f(XCIN) = stopped
mA
Output transistors “off”
Increment when A-D conversion is
executed
f(XIN) = 10 MHz
800
0.1
µA
µA
µA
1.0
10
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
Ta = 85 °C
92
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 34 A-D converter characteristics (1)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VREF = 2.0 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless
otherwise noted)
10-bit A-D mode (when conversion mode selection bit (bit 7 of address 003816) is “0”)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
10
–
–
Resolution
bit
LSB
2tc(XIN)
kΩ
VCC = VREF = 5.0 V
Absolute accuracy (excluding quantization error)
Conversion time
±4
tCONV
61
RLADDER
Ladder resistor
12
50
35
100
200
5
VREF = 5.0 V
VREF = 5.0 V
at A-D converter operated
at A-D converter stopped
Reference power
150
µA
IVREF
source input current
µA
II(AD)
A-D port input current
µA
5.0
Table 35 A-D converter characteristics (2)
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VREF = 2.0 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless
otherwise noted)
8-bit A-D mode (when conversion mode selection bit (bit 7 of address 003816) is “1”)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
–
–
Resolution
bit
LSB
2tc(XIN)
kΩ
VCC = VREF = 5.0 V
Absolute accuracy (excluding quantization error)
Conversion time
±2
tCONV
50
RLADDER
Ladder resistor
12
50
35
100
200
5
VREF = 5.0 V
VREF = 5.0 V
at A-D converter operated
at A-D converter stopped
Reference power
150
µA
IVREF
source input current
µA
II(AD)
A-D port input current
µA
5.0
Table 36 D-A converter characteristics
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless
otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
–
–
Resolution
Bits
%
VCC = 4.0–5.5 V
VCC = 2.7–4.0 V
1.0
2.5
3
Absolute accuracy
%
tsu
Setting time
µs
RO
Output resistor
1
2.5
4
kΩ
mA
IVREF
Reference power source input current (Note 1)
3.2
Note 1: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”.
Table 37 Comparator characteristics
(VCC = 2.7 to 5.5 V, VCC = 4.0 to 5.5 V for flash memory version, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
–
Parameter
Test conditions
1LSB = VCC/16
Unit
Min.
Typ.
Max.
1/2
2.8
3.5
7
Absolute accuracy
Conversion time
LSB
µs
at 10 MHz operating
at 8 MHz operating
at 4 MHz operating
TCONV
µs
µs
Analog input voltage
Analog input current
Ladder resistor
VIA
0
VCC
5.0
50
V
IIA
µA
kΩ
RLADDER
20
40
29VCC
/32
Internal reference voltage
V
V
CMPREF
VCC/32
VCC
External reference input voltage
93
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 38 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
2
Typ.
Max.
µs
ns
ns
ns
µs
µs
µs
ns
ns
ns
tW(RESET)
tC(XIN)
Reset input “L” pulse width
Main clock input cycle time
100
40
40
20
5
tWH(XIN)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
5
200
80
80
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “H” pulse width
ns
ns
tWH(INT)
tWL(INT)
80
80
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “L” pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC(SCLK1)
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
800
370
370
220
100
1000
400
400
200
200
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Serial I/O2 input hold time
Note : When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
94
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 39 Timing requirements (2)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Typ.
Max.
Min.
µs
ns
ns
ns
µs
µs
µs
ns
ns
ns
tW(RESET)
tC(XIN)
Reset input “L” pulse width
Main clock input cycle time
2
1000/(4.5VCC–8)
tWH(XIN)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
400/(4.5VCC–8)
tWL(XIN)
400/(4.5VCC–8)
tC(XCIN)
20
5
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
5
500
230
230
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “H” pulse width
ns
ns
tWH(INT)
tWL(INT)
230
230
INT0, INT1, INT20, INT30, INT40, INT21, INT31, INT41
input “L” pulse width
tC(SCLK1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
2000
950
950
400
200
2000
950
950
400
300
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Serial I/O2 input hold time
Note : When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
95
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 40 Timing requirements for system bus interface
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
tsu (S-R)
Parameter
Min.
0
Typ.
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S0, S1 setup time
S0, S1 setup time
S0, S1 hold time
S0, S1 hold time
A0 setup time
tsu (S-W)
th (R-S)
th (W-S)
tsu (A-R)
tsu (A-W)
th (R-A)
th (W-A)
tw (R)
0
0
0
10
10
0
A0 setup time
A0 hold time
0
A0 hold time
Read pulse width
120
120
50
0
Write pulse width
tw (W)
Before write data input setup time
After write data input hold time
tsu (D-W)
th (W-D)
Table 41 Timing requirements for system bus interface
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
tsu (S-R)
Parameter
Unit
Min.
0
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S0, S1 setup time
S0, S1 setup time
S0, S1 hold time
S0, S1 hold time
A0 setup time
tsu (S-W)
th (R-S)
th (W-S)
tsu (A-R)
tsu (A-W)
th (R-A)
th (W-A)
tw (R)
0
0
0
30
30
0
A0 setup time
A0 hold time
0
A0 hold time
Read pulse width
Write pulse width
250
250
130
0
tw (W)
tsu (D-W)
th (W-D)
Before write data input setup time
After write data input hold time
96
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 42 Switching characteristics 1
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Test
conditions
Symbol
Parameter
Unit
Min.
Typ.
Max.
140
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tV (SCLK1-TXD)
tr (SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
tC(SCLK1)/2–30
tC(SCLK1)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig. 83
–30
30
30
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tC(SCLK2)/2–160
tC(SCLK2)/2–160
200
Fig. 84
Fig. 83
Serial I/O2 output valid time
0
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
30
30
30
tr (CMOS)
10
10
tf (CMOS)
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
Table 43 Switching characteristics 2
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Test
conditions
Symbol
Parameter
Unit
Min.
Typ.
Max.
350
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tV (SCLK1-TXD)
tr (SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
tC(SCLK1)/2–50
tC(SCLK1)/2–50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig. 83
–30
50
50
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tV (SCLK2-SOUT2)
tf (SCLK2)
tC(SCLK2)/2–240
tC(SCLK2)/2–240
400
Fig. 84
Fig. 83
Serial I/O2 output valid time
0
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
50
50
50
tr (CMOS)
20
20
tf (CMOS)
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
97
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 44 Switching characteristics for system bus interface
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
ta(R-D)
Parameter
After read data output enable time
Unit
Min.
0
Typ.
Max.
80
ns
ns
ns
tv(R-D)
After read data output disable time
30
tPLH(R-OBF)
After read OBF00, OBF01, OBF10 output propagation time
150
Table 45 Switching characteristics for system bus interface
(VCC =2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
ta(R-D)
Parameter
After read data output enable time
Unit
Min.
0
Max.
ns
ns
ns
130
85
After read data output disable time
tv(R-D)
After read OBF00, OBF01, OBF10 output propagation time
tPLH(R-OBF)
300
98
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 46 Timing requirements in memory expansion mode and microprocessor mode
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, in high-speed mode, unless otherwise noted)
Limits
Typ.
Symbol
tsu (ONW-φ)
Parameter
ONW input setup time
Unit
Min.
–20
–20
50
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ONW input hold time
Data bus setup time
Data bus hold time
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
th (φ-ONW)
tsu (DB-φ)
0
th (φ-DB)
–20
–20
50
tsu (ONW-RD), tsu (ONW-WR)
th (RD-ONW), th (WR-ONW)
tsu (DB-RD)
0
th (RD-DB)
Table 47 Switching characteristics in memory expansion mode and microprocessor mode
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, in high-speed mode, unless otherwise noted)
Limits
Test
conditions
Symbol
Parameter
φ clock cycle time
Unit
Min.
Typ.
Max.
tC(φ)
2tC(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
AD15–AD8 delay time
AD7–AD0 delay time
AD15–AD8 valid time
AD7–AD0 valid time
SYNC delay time
tC(XIN)–10
tC(XIN)–10
tWL(φ)
td(φ-AH)
td(φ-AL)
tV(φ-AH)
tV(φ-AL)
16
20
5
35
40
2
2
5
td(φ-SYNC)
tV(φ-SYNC)
td(φ-DB)
16
5
SYNC valid time
Fig. 83
30
Data bus delay time
Data bus valid time
15
tV(φ-DB)
10
tC(XIN)–10
3tC(XIN)–10
RD pulse width, WR pulse width
tWL(RD), tWL(WR)
RD pulse width, WR pulse width
(When one-wait is valid)
td(AH-RD), td(AH-WR)
td(AL-RD), td(AL-WR)
tV(RD-AH), tV(WR-AH)
tV(RD-AL), tV(WR-AL)
td(WR-DB)
AD15–AD8 delay time
AD7–AD0 delay time
tC(XIN)–35
tC(XIN)–16
ns
ns
ns
ns
ns
ns
ns
ns
tC(XIN)–40
tC(XIN)–20
AD15–AD8 valid time
2
2
5
5
AD7–AD0 valid time
Data bus delay time
15
30
tV(WR-DB)
Data bus valid time
10
0
td(RESET-RESETOUT)
tV(φ-RESETOUT)
RESETOUT output delay time
RESETOUT output valid time (Note)
200
100
Note: The RESETOUT output goes “H” in synchronized with the rise of the φ clock that is anywhere between a few cycles and 10-several cycles after RESET
input goes “H”.
99
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1kΩ
Measurement output pin
100pF
Measurement output pin
100pF
CMOS output
N-channel open–drain output
Fig. 83 Circuit for measuring output switching characteristics (1)
Fig. 84 Circuit for measuring output switching characteristics (2)
100
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing diagram in single-chip mode
t
C(CNTR)
t
WL(CNTR)
t
WH(CNTR)
0.8VCC
CNTR
0
, CNTR
1
0.2VCC
0.2VCC
t
WL(INT)
t
WH(INT)
INT0,INT
1
0.8VCC
INT20,INT30,INT40
INT21,INT31,INT41
t
W(RESET)
RESET
0.8VCC
0.2VCC
t
t
C(XIN)
t
t
WL(XIN)
t
WH(XIN)
0.8VCC
X
IN
0.2VCC
0.2VCC
C(XCIN
)
WL(XCIN
)
t
WH(XCIN)
0.8VCC
XCIN
t
C(SCLK1),
t
C(SCLK2
)
t
r
t
f
t
WL(SCLK1),
t
WL(SCLK2
)
tWH(SCLK1), tWH(SCLK2)
S
S
CLK1
CLK2
0.8VCC
0.2VCC
t
t
su(R
x
D
-
S
CLK1),
CLK2
th(SCLK1-
D), (SCLK2-
IN2)
su(SIN2-
S
)
R
S
x
th
RXD
0.8V
0.2VCCCC
S
IN2
t
t
v(SCLK1-T
X
D),
v(SCLK2-
S
OUT2
)
t
d(SCLK1-T
XD),td(SCLK2-SOUT2)
TXD
S
OUT2
Fig. 85 Timing diagram (1) (in single-chip mode)
101
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing diagram in memory expansion mode and microprocessor mode (1)
tC(φ)
tWL(φ)
tWH(φ)
φ
0.5VCC
tv(φ-AH)
td(φ-AH)
0.5VCC
0.5VCC
AD15–AD8
AD7–AD0
td(φ-AL)
tv(φ-AL)
tv(φ-SYNC)
td(φ-SYNC)
0.5VCC
SYNC
td(φ-WR)
tv(φ-WR)
0.5VCC
RD,WR
th(φ-ONW)
tSU(ONW-φ)
0.8VCC
0.2VCC
ONW
th(φ-DB)
tv(φ-DB)
tSU(DB-φ)
0.8VCC
0.2VCC
DB0–DB7
(At CPU reading)
td(φ-DB)
DB0–DB7
(At CPU writing)
0.5VCC
Timing diagram in microprocessor mode
0.8VCC
RESET
0.2VCC
φ
0.5VCC
td(RESET- RESETOUT)
tv(φ- RESETOUT)
0.5VCC
RESETOUT
Fig. 86 Timing diagram (2) (in memory expansion mode and microprocessor mode)
102
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing diagram in memory expansion mode and microprocessor mode (2)
t
t
WL(RD)
WL(WR)
RD,WR
0.5VCC
t
t
d(AH-RD)
d(AH-WR)
t
t
v(RD-AH)
v(WR-AH)
0.5VCC
AD15–AD
8
t
t
d(AL-RD)
d(AL-WR)
t
t
v(RD-AL)
v(WR-AL)
0.5VCC
AD
7
–AD
0
t
t
h(RD-ONW)
h(WR-ONW)
t
t
su(ONW-RD)
su(ONW-WR)
0.8VCC
0.2VCC
ONW
(At CPU reading)
RD
0.5VCC
t
SU(DB-RD)
t
h(RD-DB)
0.8VCC
0.2VCC
DB0–DB7
(At CPU writing)
WR
0.5VCC
t
v(WR-DB)
t
d(WR-DB)
0.5VCC
DB0–DB7
Fig. 87 Timing diagram (3) (in memory expansion mode and microprocessor mode)
103
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
System bus interface timing diagram
Read operation
t
su(A-R)
th(R-A)
A0
2.4 (0.8VCC
0.45 (0.2VCC
)
)
2.4 (0.8VCC
0.45 (0.2VCC
)
)
t
su(S-R)
th(R-S)
S0,S1
0.45 (0.2VCC
)
0.45 (0.2VCC
)
tw(R)
R
2.4 (0.8VCC
)
2.4 (0.8VCC
0.45 (0.2VCC
)
)
0.45 (0.2VCC
)
2.0 (0.8VCC
0.8 (0.2VCC
)
)
2.0 (0.8VCC
0.8 (0.2VCC
)
)
DQ0–DQ7
t
a(R-D)
tv(R-D)
t
PLH(R-OBF)
OBF00,OBF01,OBF10
0.8 (0.2VCC
)
Write operation
t
su(A-W)
th(W-A)
A0
2.4 (0.8VCC
0.45 (0.2VCC
)
)
2.4 (0.8VCC
0.45 (0.2VCC
)
)
t
su(S-W)
th(W-S)
S0,S1
0.45 (0.2VCC
)
0.45 (0.2VCC
)
tw(W)
W
2.4 (0.8VCC
0.45 (0.2VCC
)
2.4 (0.8VCC
)
0.45 (0.2VCC
)
)
th(W-D)
2.4 (0.8VCC
0.45 (0.2VCC
)
)
2.4 (0.8VCC
0.45 (0.2VCC
)
)
DQ0–DQ7
t
su(D-W)
Outside of parenthesis : TTL I/O
Inside of parenthesis : CMOS I/O
Fig. 88 Timing diagram (4) (system bus interface)
104
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2
Table 48 Multi-master I C-BUS bus line characteristics
Standard clock mode High-speed clock mode
Unit
Symbol
Parameter
Min.
4.7
Max.
Max.
Min.
1.3
tBUF
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
Bus free time
tHD;STA
tLOW
Hold time for START condition
Hold time for SCL clock = “0”
Rising time of both SCL and SDA signals
Data hold time
0.6
1.3
4.0
4.7
tR
20+0.1Cb
0
300
0.9
1000
300
tHD;DAT
tHIGH
tF
0
Hold time for SCL clock = “1”
Falling time of both SCL and SDA signals
Data setup time
0.6
4.0
20+0.1Cb
100
300
tSU;DAT
tSU;STA
tSU;STO
250
4.7
4.0
Setup time for repeated START condition
Setup time for STOP condition
0.6
0.6
Note: Cb = total capacitance of 1 bus line
S
DA
t
HD:STA
tsu:STO
t
BUF
t
LOW
t
R
t
F
S
P
Sr
P
S
CL
t
HD:STA
t
HD:DAT
t
HIGH
tsu:DAT
t
su:STA
S : START condition
Sr: RESTART condition
P : STOP condition
2
Fig. 89 Timing diagram of multi-master I C-BUS
105
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
80P6Q-A
Plastic 80pin 12✕12mm body LQFP
EIAJ Package Code
LQFP80-P-1212-0.5
JEDEC Code
–
Weight(g)
Lead Material
Cu Alloy
MD
HD
D
80
61
1
60
l2
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A
1
0
0.1
20
41
A
2
–
1.4
b
0.13
0.105
11.9
11.9
–
13.8
13.8
0.3
–
0.18
0.125
12.0
12.0
0.5
14.0
14.0
0.5
0.28
0.175
12.1
12.1
–
14.2
14.2
0.7
–
21
40
c
D
E
e
A
F
HD
L1
e
HE
L
1.0
L1
y
–
0°
–
1.0
–
–
–
0.1
10°
–
–
–
b
y
b2
0.225
–
12.4
12.4
L
I
2
M
M
D
E
Detail F
–
–
80D0
Glass seal 80pin QFN
EIAJ Package Code
–
JEDEC Code
–
Weight(g)
21.0±0.2
18.4±0.15
3.32MAX
1.78TYP
0.8TYP
0.6TYP
41
64
65
40
25
80
24 1.2TYP
1
INDEX
106
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6S-A
Plastic 80pin 14✕14mm body QFP
EIAJ Package Code
JEDEC Code
Weight(g)
1.11
Lead Material
Alloy 42
MD
QFP80-P-1414-0.65
HD
D
80
61
1
60
I2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.25
0.13
13.8
13.8
–
16.5
16.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.4
0.2
14.2
14.2
–
17.1
17.1
0.8
–
0.13
0.1
10°
–
A
A1
A2
b
c
D
0.1
2.8
0.3
0.15
14.0
14.0
0.65
16.8
16.8
0.6
1.4
–
20
41
E
e
A
21
40
HD
HE
L
L1
x
L1
F
M
y
–
–
b
e
x
b2
I2
MD
ME
0.35
–
14.6
14.6
y
L
–
–
–
Detail F
–
107
REVISION DESCRIPTION LIST
3886 GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
980216
980716
000114
2.0 The contents of flash memory version were added.
2.1 All pages; “PRELIMINARY Notice: This is...” eliminated.
Page 1; The second “In high-speed mode” of “Power dissipation” eliminated.
Page 1; “Memory expansion” is revised.
Page 1; Explanation of “<Flash memory mode>” is revised.
Page 1; Notes 2 is changed.
Page 1; Some words of “APPLICATION” are added.
Page 2; Figure 1 and Figure 2 are partly revised.
Page 3; Figure 3 is added.
Page 7; Figure 5 is partly revised.
Page 8; Figure 6 is partly revised.
Page 8; Some products are added into Table 3.
Page 9; Note into Figure 7 is revised.
Page 10; Note into Figure 8 is revised.
Page 11; Note into Figure 9 is added.
Page 41; Explanation of “I2C Data Shift Register” is partly revised.
Page 42; Explanation of “I2C Clock Control Regsiter” is partly revised.
Page 42; Note 1 into Table 10 is partly revised.
Page 50; (6) and (7) of “Precaution when using multi-master I2C BUS interface” are added.
Page 51; Figure 48 is partly revised.
Page 56; Explanation of “RESET CIRCUIT” is partly revised.
Page 56; Note into Figure 55 is revised.
Page 60; Figure 61 is partly revised.
Page 61; Explanation of “PROCESSOR MODE” is partly revised.
Page 61; Explanation into Figure 62 is eliminated partly.
Page 61; Note into Figure 63 is revised.
Page 66; Figure 66 is partly revised.
(1/2)
REVISION DESCRIPTION LIST
3886 GROUP DATA SHEET
Rev.
No.
Rev.
date
Revision Description
2.1 Page 73; Minimum limits of VPPH into Table 22 is revised.
Page 74; Figure 72 is partly revised.
000114
Page 81; Explanation of “Flash memory mode 3 (CPU reprogramming mode)” is added.
Page 81; Note into Figure 79 is eliminated partly.
Page 82; “CPU reprogramming mode operation procedure” is eliminated partly.
Page 82; Figure 81 is partly revised.
Page 86; Explanation of “Handling of Power Source Pins” is added.
Page 86; Explanation of “Erasing of Flash memory version” is added.
Page 87; Parameter into Table 28 is partly revised.
Page 88; Parameter into Table 29 is partly revised.
•Mask ROM confirmation forms are eliminated.
✽ Refer to the “Mitsubishi MCU Technical Information” Homepage (http://www.infomicom.
mesc.co.jp/indexe/htm). [38000 Series → Mask ROM Confirmation Forms]
•ROM programming confirmation form is eliminated.
✽ Refer to the “Mitsubishi MCU Technical Information” Homepage (http://www.infomicom.
mesc.co.jp/indexe/htm). [38000 Series → Mask ROM Confirmation Forms]
•Mark specification form is eliminated.
✽ Refer to the “Mitsubishi MCU Technical Information” Homepage (http://www.infomicom.
mesc.co.jp/indexe/htm). [38000 Series → Mask ROM Confirmation Forms → ROM
Ordering Method → Mark Specification Forms]
Page 107; Package outline for 80P6S-A is added.
(2/2)
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
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•
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2000 MITSUBISHI ELECTRIC CORP.
H-KI-0001 Printed in Japan (ROD) II
New publication, effective Jan. 2000.
Specifications subject to change without notice.
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