M38C31E2M [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38C31E2M |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总63页 (文件大小：928K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no ces whatsoever have been
made to the contents of the document, and these changes do not cony alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business opof high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●LCD drive control circuit
DESCRIPTION
Bias ............................................................................ 1/1, 1/2, 1/3
Duty .................................................................... 1/1, 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 32
●2 Clock generating circuit
The 38C3 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38C3 group has a LCD drive control circuit, a 10-channel A-D
converter, and a Serial I/O as additional functions.
The various microcomputers in the 38C3 group include variations of
internal memory size and packaging. For details, refer to the section
on part numbering.
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode .................................................... 4.0 to 5.5 V
In middle-speed mode ................................................2.5 to 5.5 V
In low-speed mode...................................................... 2.5 to 5.5 V
●Power dissipation
For details on availability of microcomputers in the 38C3 group, refer
to the section on group expansion.
FEATURES
In high-speed mode ...........................................................32 mW
(at 8 MHz oscillation frequency)
●Basic machine-language instructions ....................................... 71
●The minimum instruction execution time ............................. 0.5 µs
(at 8MHz oscillation frequency)
In low-speed mode..............................................................45 µW
(at 32 kHz oscillatiouency, at 3 V power source voltage)
●Operating temperatu............................... – 20 to 85°C
●Memory size
ROM ..................................................................4 K to 48 K bytes
RAM ................................................................. 192 to 1024 bytes
●Programmable input/output ports ............................................. 57
●Software pull-up/pull-down resistors
APPLICATI
Camera, hounces, consumer electronics, etc.
..................................................... (Ports P0–P8 except Port P51)
●Interrupts ................................................... 16 sources, 16 vectors
(includes key input interrupt)
●Timers ............................................................8-bit ✕ 6, 16-bit ✕ 1
●A-D converter ................................................. 10-bit ✕ 8 channels
●Serial I/O .......................................8-bit ✕ 1 (Clock-synchronized)
PIN CONFIGURATION (TOP VIEW)
P47/SRD
7
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P30/SEG24
P31/SEG25
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
COM0
COM1
COM2
COM3
VL1
P46/SC
P45/SOUT
P44/SIN
P43/φ
P42/T3OUT
P41/T1OUT
P40/SCLK2
M38C34M6AXXXFP
AVSS
VREF
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
VL2
VL3
P80
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1 M38C34M6AXXXFP pin configuration
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
K e y - o n w a k e - u p
O U T T 3 O U T T , 1
φ
2
– 0 I N T I N T
Fig. 2 Functional block diagram
2
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
VREF
Power source
• Apply voltage of 2.5 V to 5.5 V to VCC, and 0 V to VSS.
• Reference voltage input pin for A-D converter.
Analog reference
voltage
AVSS
Analog power
source
• GND input pin for A-D converter.
• Connect to VSS.
RESET
XIN
Reset input
Clock input
• Reset input pin for active “L.”
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
XOUT
Clock output
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
VL1 – VL3
LCD power
source
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
• Input 0 – VL3 voltage to LCD.
COM0 –
COM3
Common output
• LCD common output pins.
• COM1, COM2, and COM3 are not used at 1/1 duty ratio.
• COM2 and COM3 are not used at 1/2 duty ratio.
• COM3 is not used at 1/3 duty ratio.
P00/SEG9 – I/O port P0
P07/SEG15
• 8-bit I/O port.
• CMOS compatible input level.
• LCD segment pins
• CMOS 3-state output structure.
• I/O direction register allows each port ually
programmed as either input or output
• Pull-down control is enabled.
P10/SEG16 – I/O port P1
P17/SEG23
P20/SEG0 – I/O port P2
P27/SEG7
P30/SEG24 – Output port P3
P37/SEG31
• 8-bit output port.
• CMOS state output.
• Pull-down control
P40/SCLK2
P41/T1OUT
P42/T3OUT
P43/φ
I/O port P4
• 8-bit I/O port.
• Serial I/O function pin
• Timer output pin
• Timer output pin
• φ output pin
• CMOS comlevel.
• CMOS 3structure.
• I/O direr allows each pin to be individually
proeither input or output.
• Pl is enabled.
P44/SIN,
• Serial I/O function pins
P45/SOUT,
P46/SCLK1,
P47/SRDY
3
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Pin
Name
Function
Function except a port function
P51
Input port P5
• 1-bit input pin.
• CMOS compatible input level.
P50/TAOUT
P52/PWM1
I/O port P5
• 7-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
• Timer A output pin
• PWM1 output (timer output) pin
• External count I/O pins
P53/CNTR0,
P54/CNTR1
P55/INT0,
P56/INT1,
P57/INT2
• External interrupt input pins
• A-D conversion input pins
P60/AN0 –
P67/AN7
I/O port P6
I/O port P7
I/O port P8
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
P70/XCOUT,
P71/XCIN
• 2-bit I/O port.
ck generating circuit I/O pins
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individ
programmed as either input or output.
• Pull-up control is enabled.
P80 – P87
• 8-bit I/O port.
• TTL input level.
• Key input (Key-on wake-up) interrupt
input pins
• CMOS 3-state output structure.
• I/O direction register allows each ividually
programmed as either input or
• Pull-up control is enabled.
4
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M38C3
4
M
6
A
XXX FP
Package type
: 80P6N-A package
: 80D0 package
FP
FS
ROM number
Omitted in some types.
A : Standard(Note)
M : M version
ROM/PROM size
1
: 4096 bytes
2 : 8192 bytes
3 : 12288 bytbytes
s
tes
4
52 bytes
: 16384
5 : 2048
6 : 24
7
:
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M
: Mask ROM version
E
: EPROM or One Time PROM version
RAM size
0
: 192 bytes
1 : 256 bytes
2 : 384 bytes
3
: 512 bytes
4 : 640 bytes
5 : 768 bytes
6
: 896 bytes
7 : 1024 bytes
Note : Difference between standard and M version
• Standard : Port P5
0
/TAOUT pin remains set to the input mode until the direction
register is set to the output mode during reset and after
reset.
• M version : Port P50/TAOUT pin remains set to the output mode (“L” output) until
the direction register is set to the input mode during reset
and after reset.
Fig. 3 Part numbering
5
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 38C3 group as follows.
Packages
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions
Memory Size
ROM/PROM size ................................................ 16 K to 48 K bytes
RAM size............................................................. 512 to 1024 bytes
Memory Expansion Plan
Under development
M38C37ECA/ECM
ROM size (bytes)
48K
44K
40K
36K
32K
28K
24K
20K
16K
12K
8K
Under develop
6M
Planning
4K
192
384
512
640
768
896
1024
RAM size (bytes)
Products under deplanning : the development schedule and specification may be revised without notice.
Planning produpped the development.
Fig. 4 Memory expansion plan
Currently planning products are listed below.
Table 3 Support products
As of April 1998
(P) ROM size (bytes)
ROM size for User in ( )
RAM size
(bytes)
Remarks
Product name
Package
M38C34M6AXXXFP
M38C37ECAXXXFP
M38C37ECAFP
24576 (24446)
640
1024
640
Mask ROM version
80P6N-A
80D0
One Time PROM version
One Time PROM version (blank)
EPROM version
49152 (49022)
24576 (24446)
49152 (49022)
M38C37ECAFS
M38C34M6MXXXFP
M38C37ECMXXXFP
M38C37ECMFP
Mask ROM version
80P6N-A
80D0
One Time PROM version
One Time PROM version (blank)
EPROM version
1024
M38C37ECMFS
6
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 38C3 group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine instruc-
tions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the
internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mod
(CPUM s 003B16
)
mode bits
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : RAM in the zero page is used as stack area
1 : RAM in page 1 is used as stack area
Not used (returns “1” when read)
(Do not write “0” to this bit.)
Port XC switch bit
0 : I/O port
1 : XCIN, XCOUT
Main clock ( XIN–XOUT) stop bit
0 : Operating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN-XOUT selected (middle-/high-speed mode)
1 : XCIN-XCOUT selected (low-speed mode)
Fig. 5 Structure of CPU mode register
7
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control
registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special page
RAM is used for data storage and for stack area of subroutine calls
addressing mode.
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
000
RAM size
(bytes)
Address
XXXX16
SFR area 1
192
256
384
512
640
768
896
1024
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
LCD display RAM area
Zero page
ROM corrective RAM area
(Note 1)
05816
010016
XXXX16
Reserved area
044016
Not used
0F0016
0FFF16
ROM area
SFR area 2 (Note 1)
ROM size
(bytes)
Address
YYYY16
s
Z16
YYYY16
Reserved ROM area
(128 bytes)
4096
8192
F00
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
ZZZZ16
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Note 1 : This is valid only in mask ROM version.
Fig. 6 Memory map diagram
8
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0 (P0)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
002016
002116
002216
002316
002416
Timer 1 (T1)
Port P0 direction register (P0D)
Port P1 (P1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer 5 (T5)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
002516 Timer 6 (T6)
002616
Timer 6 PWM register (T6PWM)
002716
002816
002916
Port P4 (P4)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Port P4 direction register (P4D)
Port P5 (P5)
002A16 Timer 56 mode register (T56M)
φ output control register (CKOUT)
Port P5 direction register (P5D)
Port P6 (P6)
002B16
002C16 Timer A register (low) (TAL)
Timer A register (high) (TAH)
Port P6 direction register (P6D)
Port P7 (P7)
002D16
002E16 Compare register (low) AL)
002F16 Compare register (h)
003016 Timer A mode re
Port P7 direction register (P7D)
Port P8 (P8)
Timer A contrON)
A-D contrON)
001116 Port P8 direction register (P8D)
003116
003216
003316
003416
003516
003
0
16
3B16
003C16
003D16
003E16
003F16
001216
001316
A-D coer (low) (ADL)
A-D gister (high) (ADH)
001416
001516
001616 PULL register A (PULLA)
PULL register B (PULLB)
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P8 output selection register (P8SEL)
Serial I/O control register 1 (SIOCON1)
Serial I/O control register 2 (SIOCON2)
Serial I/O register (SIO)
ment output enable register (SEG)
CD mode register (LM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
ROM correct enable regis
0F0A16
0F0B16
0F0C16
0F0D16
0F0E16
0F0116
0F0216
0F0316
ROM correct high-order address register 5 (Note)
ROM correct low-order address register 5 (Note)
ROM correct high-order address register 6 (Note)
ROM correct low-order address register 6 (Note)
ROM correct high-order address register 7 (Note)
ROM correct high-ordster 1 (Note)
ROM correct low-ogister 1 (Note)
0F0416 ROM correct hiss register 2 (Note)
0F0516 ROM correcdress register 2 (Note)
ROM correct hir address register 3 (Note)
0F0F16 ROM correct low-order address register 7 (Note)
0F1016
0F0616
ROM correct low-oder address register 3 (Note)
ROM correct high-order address register 8 (Note)
0F1116 ROM correct low-order address register 8 (Note)
0F0716
ROM correct high-order address register 4 (Note)
ROM correct low-order address register 4 (Note)
0F0816
0F0916
Note: This register is valid only in mask ROM version.
Fig. 7 Memory map of special function register (SFR)
9
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
[Direction Registers (ports P2, P4, P50, P52–P57,
and P6–P8)]
b7
b0
PULL register A
(PULLA : address 001616
)
The I/O ports P2, P4, P50, P52–P57, and P6–P8 have direction reg-
isters which determine the input/output direction of each individual
pin. Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
P0
P1
P2
0
0
0
–P0
–P1
–P2
7
7
7
pull-down
pull-down
pull-down
Not used
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
P7
P8
0
, P7
1
pull-up
pull-up
0
–P8
7
Not used (return “0” when read)
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are float-
ing. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
b7
b0
PULL register B
(PULLB : address 001716
)
P4
P4
5
6
P6
0
4
0
0
4
–P4
–P4
, P5
–P5
, P6
–P6
3
7
2
7
3
7
pull-up
pull-up
[Direction Registers (ports P0 and P1)]
Ports P0 and P1 have direction registers which determine the input/
output direction of each individual port.
, P53 pull-up
pull-up
pull-up
pull-up
Each port in a direction register corresponds to one port, each port
can be set to be input or output.
Not used (return “0” when read)
0 : Disable
1 : Enable
When “0” is written to the bit 0 of a direction register, that port be-
comes an input port. When “1” is written to that port, that port be-
comes an output port. Bits 1 to 7 of ports P0 and P1 direction regis-
ters are not used.
contents of PULL register A and PULL register B
o not affect ports programmed as the output ports.
tructure of PULL register A and PULL register B
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL regis
B (address 001716), ports except for ports P3 and P51 can
either pull-down or pull-up (pins that are shared with the
output pins for LCD are pull-down; all other pins are p
program.
b7
b0
Port P8 output selection register
(P8SEL : address 001816)
However, the contents of PULL register A and r B do
not affect ports programmed as the output po
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
Port P8 Output Selection
Ports P80 to P87 can be switched to pen-drain output by
Fig. 9 Structure of port P8 output selection register
setting “1” to the port P8 output ister.
Table 4 List of I/O port function (1)
Pin
Name
Port P0
Input/Output
I/O format
Non-port function
Related SFRs
PULL register A
Segment output enable reg-
ister
Ref. No.
(1)
P00/SEG8 –
P07/SEG15
Input/Output,
port unit
CMOS compatible input LCD segment output
level
CMOS 3-state output
P10/SEG16 –
P17/SEG23
Port P1
Port P2
Port P3
Input/Output,
port unit
CMOS compatible input LCD segment output
level
CMOS 3-state output
PULL register A
Segment output enable reg-
ister
P20/SEG0 –
P27/SEG7
Input/Output,
individual bits
CMOS compatible input
CMOS 3-state output
LCD segment output
LCD segment output
PULL register A
Segment output enable reg-
ister
P30/SEG24 –
P37/SEG31
Output,
individual bits
CMOS 3-state output
Segment output enable reg-
ister
(2)
10
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 5 List of I/O port function (2)
Pin
Name
Port P4
Input/Output
I/O format
Non-port function
Related SFRs
Ref. No.
(3)
P40/SCLK2
Input/Output,
individual bits
CMOS compatible input Serial I/O function I/O Serial I/O control registers
level
1, 2
CMOS 3-state output
PULL register B
P41/T1OUT
P42/T3OUT
P43/φ
Timer output
Timer output
φ clock output
Timer 12 mode register
PULL register B
(4)
(4)
(5)
Timer 34 mode register
PULL register B
φ output control register
PULL register B
P44/SIN
Serial I/O function I/O Serial I/O control registers
(6)
(7)
P45/SOUT
P46/SCLK1
P47/SRDY
1, 2
PULL register B
(8)
(9)
P50/TAOUT
Port P5
Input/Output,
individual bits
CMOS compatible input Timer A output
level
CMOS 3-state output
imer A mode register
er A control reigster
register B
(10)
P51
Input
CMOS compatible input
level
(11)
(4)
P52/PWM1
Input/Output,
individual bits
CMOS compatible input PWM ou
level
Timer 56 mode register
PULL register B
CMOS 3-state output
P53/CNTR0
P54/CNTR1
nt I/O
Interrupt edge selection reg-
ister
PULL register B
(12)
(12)
(13)
P55/INT0
P56/INT1
P57/INT2
rnal interrupt in- Interrupt edge selection reg-
ut
ister
PULL register B
P60/AN0
–
P67/AN7
Port P6
Port P7
Port P8
Common
Input/Output,
individual bits
CMOS cot A-D converter input
A-D control register
PULL register B
level
CMOput
Input/Output,
individual bits
Cible input Sub-clock generating CPU mode register
P70/XCIN
(14)
circuit I/O
PULL register A
P71/XCOUT
P80 – P87
(15)
(17)
tate output
Input/Outp
individua
compatible input Key input (key-on Interrupt control register 2
l
wake-up) interrupt in- PULL register A
put
MOS 3-state output
COM
0
– COM
3
LCD common output
LCD mode register
(16)
Notes 1: Make sure that the input leveeither 0 V or VCC during execution of the STP instruction.
When an input level is at an potential, a current will flow from VCC to VSS through the input-stage gate.
2: For details of the functions of pto P3 in modes other than single-chip mode, and how to use double function ports as function I/O ports, refer to the
applicable sections.
11
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1)Ports P0, P1, P2
(2)Port P3
V
V
L2/VL3
L1/VSS
V
V
L2/VL3
L1/VSS
Segment output enable bit
(Note)
Segment output enable bit
Port latch
Direction register
Data bus
Port latch
Data bus
down control
tput enable bit
Pull-down control
Segment output enable bit
Note : Port P0, P1 direction registers are only bit 0.
(3)Port P4
0
(4)P, P52
Pull-up control
P-channel output disable bit
Pull-up control
output selection bit
3 output selection bit
er 6 output selection bit
Serial I/O mode selection bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Timer 1 output
Timer 3 output
Timer 6 output
Serial I/O clock output
(6)Port P4
4
(5)Port P4
3
Pull-up control
Pull-up control
Direction register
Port latch
Direction register
Port latch
Data bus
Data bus
φ output control bit
Serial I/O input
φ
Fig. 10 Port block diagram (1)
12
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(8)Port P4
6
(7)Port P4
5
Pull-up control
P-channel output disable bit
Pull-up control
P-channel output disable bit
Serial I/O port selection bit
Direction register
Serial I/O mode selection bit
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O output
Serial I/O clock output
l I/O clock input
(9)Port P4
7
(10)Port P5
0
Pull-up control
Pull-up control
S
RDY output enable bit
Direction register
ut enable bit
(Note)
rection register
Data bus
Port latch
Port latch
Serial I/O ready output
Timer A output
(12)Ports P53–P57
(11)Port P5
1
Pull-up control
Data bus
Direction register
Port latch
Data bus
INT
0
–INT
2
1
interrupt input
interrupt input
Note: The initihal value of M version becomes “1” (output).
CNTR ,CNTR
0
Fig. 11 Port block diagram (2)
13
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(14)Port P7
0
(13)Port P6
Port selection • pull-up control
Pull-up control
Port Xc switch bit
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
A-D conversion input
Analog input pin selection bit
Sub-cloing circuit input
(15)Port P7
1
(16)CO
Port selection • pull-up control
Port Xc switch bit
Direction register
V
V
L2
L1
The gate input signal of each
Port latch
Data bus
transistor is controlled by the
LCD duty ratio and the bias
value.
Oscillator
7
0
Port Xc switch bit
(17)Port P8
Pull-up control
P-channel output disable bit
Direction register
Data bus
Port latch
Key input (key-on wake-up) interrupt input
Fig. 12 Port block diagram (3)
14
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by sixteen sources: six external, nine internal, and
one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0”.
Interrupt enable bits can be set or cleared by software. Interrupt re-
quest bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. The interrupt jump destination address is read from the vector
table into the program counter.
■Notes on Interrupts
When the active edge of an external interrupt (INT0 – I
or CNTR1) is set or an vector interrupt source where upt
source is assigned to the same vector address ie cor-
responding interrupt request bit may also be , take fol-
lowing sequence:
(1) Disable the interrupt.
(2) Change the active edge in iselection register.
(3) Clear the set interrupt re0.”
(4) Enable the interrupt.
15
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Interrupt Source Priority
Remarks
High
Low
Reset (Note 2)
1
2
FFFD16
FFFB16
FFFC16
FFFA16
At reset
Non-maskable
INT0
At detection of either rising or falling edge of External interrupt
INT0 intput
(active edge selectable)
INT1
3
4
5
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
At detection of either rising or falling edge of External interrupt
INT1 input
(active edge selectable)
INT2
At detection of either rising or falling edge of External interrupt
INT2 input
(active edge selectable)
Serial I/O
At completion of serial I/O data transmit/re- Valid when serial I/O is selected
ceive
Timer A
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
CNTR0
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
At timer A underflow
At timer 1 underflow
8
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
STP release timer underflow
9
10
11
12
13
At detection of either rising or ff External interrupt
CNTR0 input
(active edge selectable)
CNTR1
14
15
16
17
FFE316
FFE116
FFDF16
FFDD16
FFE216
FFE016
FFDE16
FFDC16
At detection of either risidge of External interrupt
CNTR1 input
(active edge selectable)
Key input (Key-
on wake-up)
At falling of port P8 t logical level External interrupt
AND
(falling valid)
A-D conversion
At completioersion
Valid whenA-D conversion interrupt
is selected
BRK instruction
At BRK xecution
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination address
2: Reset function in the same way as an interrupt with the h
16
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
0
1
2
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
0 : Falling edge a
1 : Rising edge
Not used (return “0” when read)
CNTR
CNTR
0
active edge switch bit
active edge switch bit
0 : Falling ing edge count
1 : Risinfalling edge count
1
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
(IREQ1 : address 003C16
)
)
INT
INT
INT
0
1
2
interrupt requ
interrupt r
interru
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
Serial I/O st bit
Timer est bit
Timequest bit
t request bit
rupt request bit
CNTR
CNTR
0
interrupt request bit
interrupt request bit
1
Key input interrupt request bit
AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
INT
INT
INT
0
1
2
interrupt enable bit
interrupt enable bit
interrupt enable bit
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
Serial I/O interrupt enable bit
Timer A interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
CNTR
CNTR
0
interrupt enable bit
interrupt enable bit
1
Key input interrupt enable bit
AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
17
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
of using a key input interrupt is shown in Figure 15, where an inter-
rupt request is generated by pressing one of the keys consisted as
an active-low key matrix which inputs to ports P80–P83.
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by applying “L” level to any
pin of port P8 that have been set to input mode. In other words, it is
generated when AND of input level goes from “1” to “0”. An example
Port PXx
“L” level output
PULL register A
Bit 5 = “1”
Port P8
7
Key input interrupt request
direction register = “1”
✽
✽
✽
✽
✽ ✽
✽ ✽
✽ ✽
✽ ✽
Port P8
latch
7
6
5
P8
7
output
output
Port P8
direction register = “1”
6
Port P8
latch
P8
6
Port P8
directio
5
Port P8
latch
P8
5
output
output
P8
ction register = “1”
4
P84
Port P8
3
direction register = “0”
Port P8
Input reading circuit
✽ ✽
Port P8
latch
3
P8
3
input
input
input
input
Port P8
2
direction register = “0”
✽
✽ ✽
Port P8
latch
2
P8
2
Port P8
1
direction register = “0”
✽
✽ ✽
Port P8
latch
1
P81
Port P8
0
direction register = “0”
✽
✽ ✽
Port P8
latch
0
P80
✽P-channel transistor for pull-up
✽ ✽CMOS output buffer
Fig. 15 Connection example when using key input interrupt and port P8 block diagram
18
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
8-Bit Timer
The 38C3 group has six built-in timers : Timer 1, Timer 2, Timer 3,
Timer 4, Timer 5, and Timer 6.
b7
b7
b7
b0
Timer 12 mode register
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016,” an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is
set to “1.”
(T12M: address 002816
)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : f(XCIN
)
The count can be stopped by setting the stop bit of each timer to “1.”
The system clock φ can be set to either the high-speed mode or low-
speed mode with the CPU mode register. At the same time, timer
internal count source is switched to either f(XIN) or f(XCIN).
10 : f(XIN)/32 or f(XCIN)/32
11 : f(XIN)/128 or f(XCIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN
)
10 : External count input CNTR
11 : Not available
Timer 1 output selection bit (P4
0 : I/O port
Timer 1 output
sed (returns “0” when read)
ot write “1” to this bit.)
0
1)
●Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. Arectangular waveform of timer 1 under-
flow signal divided by 2 is output from the P41/T1OUT pin. The wave-
form polarity changes each time timer 1 overflows. The active edge
of the external clock CNTR0 can be switched with the bit 6 of the
interrupt edge selection register.
Timer 34 mode register
(T34M: address 002916
)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/32 or f(XCIN)/32
11 : f(XIN)/128 or f(XCIN)/128
Timer 4 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR
11 : Not available
Timer 3 output selection bit (P4
0 : I/O port
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2 is
set to “0116.”
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by
the timer 34 mode register. Arectangular waveform of time
flow signal divided by 2 is output from the P42/T3OUT pi
form polarity changes each time timer 3 overflows. ge
of the external clock CNTR1 can be switched of the
interrupt edge selection register.
1
2)
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b0
Timer 56 mode register
(T56M: address 002A16
)
●Timer 5, Timer 6
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
The count sources of timer 5 and tiselected by setting
the timer 56 mode register. Areceform of timer 6 under-
flow signal divided by 2 can be outm the P52/PWM1 pin.
Timer 5 count source selection bit
0 : f(XIN)/16 or f(XCIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
●Timer 6 PWM1 Mode
Timer 6 can output a rectangular waveform with “H” duty cycle n/
(n+m) from the P52/PWM1 pin by setting the timer 56 mode register
(refer to Figure 17). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P5
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
2)
Fig. 16 Structure of Timer Related Register
19
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
X
CIN
RESET
Timer 1 latch (8)
Timer 1 count source
selection bit
1/2
“01”
FF16
Internal system clock
selection bit
STP instruction
Timer 1 interrupt request
“1”
Timer 1 (8)
1/16
X
IN
“00”
“10”
“11”
Timer 1 count
stop bit
“0”
1/32
1/128
P41 latch
P41/T1OUT
1/2
Timer 1 output selection bit
Timer 2 latch (8)
Timer 2 count source
selection bit
“00”
“01”
0116
P41
direction register
Timer 2 interrupt request
Timer 2 (8)
Timer 2 count
stop bit
“10”
Rising/Falling
active edge switch
P53/CNTR0
(8)
Timer
sel
“01”
“00”
Timer 3 interrupt request
Timer 3 (8)
count
it
P42 latch
“
P42/T3OUT
1/2
Timer 3 output selection bi
Timer 4 latch (8)
Timer 4 count source
selection bit
“01”
P42
direction re
Timer 4 (8)
Timer 4 interrupt request
“00”
Timer 4 count
stop bit
“10”
ling
e switch
CNTR1 interrupt request
P54/CNTR1
Timer 5 latch (8)
Timer 5 count source
selection bit
“1”
“0”
Timer 5 interrupt request
Timer 5 (8)
Timer 5 count
stop bit
Timer 6 latch (8)
Timer 6 count source
selection bit
“01”
Timer 6 (8)
Timer 6 interrupt request
“00”
“10”
Timer 6 count
stop bit
Timer 6 PWM register (8)
P52 latch
P52/PWM1
PWM
1/2
“1”
“0”
Timer 6 output selection bit
Timer 6 operation
mode selection bit
P52 direction register
Fig. 17 Block diagram of timer
20
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
t
s
Timer 6
count source
Timer 6
PWM mode
n ✕ ts
m ✕ ts
(n+m) ✕ ts
Timer 6 interrupt request
interrupt request
Note: PWM waveform (duty : n/(n+m) and period : (n+m) ✕ ts) is ou
n: setting value of Timer 6
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
Fig. 18 Timing chart of timer 6 PWM1 mode
16-bit Timer
es of delay time by a delay circuit.
Timer A is a 16-bit timer that can be selected in one of four mo
When using this mode, set port P55 sharing the INT0 pin to input
mode and set port P50 sharing the TAOUT pin to output mode.
It is possible to force the timer A output to be “L” using pins INT1 and
INT2 by the timer A control register.
the timer A mode register and the timer A control register.
●Timer A
The timer A operates as down-count. When the ts reach
“000016”, an underflow occurs at the next cothe timer
latch contents are reloaded. After that, ttinues count-
down. When the timer underflows, the inst bit correspond-
ing to the timer A is set to “1”.
(4) PWM mode
IGBT dummy output, an external trigger with the INT0 pin and output
control with pins INT1 and INT2 are not used. Except for those, this
mode operates just as in the IGBT output mode.
The period of PWM waveform is specified by the timer A set value.
The “H” term is specified by the compare register set value.
When using this mode, set port P50 sharing the TAOUT pin to output
mode.
(1) Timer mode
The count source can be selected by setting the timer A mode regis-
ter.
(2) Pulse output mode
Pulses of which polarity is inverted each time the timer underflows
are output from the TAOUT pin. Except for that, this mode operates
just as in the timer mode.
When using this mode, set port P50 sharing the TAOUT pin to output
mode.
(3) IGBT output mode
After dummy output from the TAOUT pin, count starts with the INT0
pin input as a trigger. When the trigger is detected or the timer A
underflows, “H” is output from the the TAOUT pin.
When the count value corresponds with the compare register value,
the TAOUT output becomes “L”. When the INT0 signal becomes “H”,
the TAOUT output is forced to become “L”.
After noise is cleared by noise filters, judging continuous 4-time same
levels with sampling clocks to be signals, the INT0 signal can use 4
21
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
External trigger delay
time selection bit
0µs
“
“
00
”
”
Data bus
4/f(XIN
8/f(XIN
)
)
01
Noise filter
(4-time same levels judgement)
INT
0
“
“
10
”
”
16/f(XIN
)
11
Noise filter sampling
clock selection bit
Timer A
operating
“10”
mode bits
1/2
1/4
Internal trigger start
“00”, “01”, “11”
Timer A count
source selection bit
1/1
Timer A write control bit
1/2
1/4
1/8
X
IN
Timer A (high-order) latch (8)
Timer A (high-order) (8)
Timer A (low-order) latch (8)
Timer A (low-order) (8)
Timer A underflow
interrupt request
TAOUT output
control bit 1
“1”
INT
INT
1
2
“0”
Compare register (high-order) (8)
Compare reg
TAOUT output
control bit 2
“1”
“0”
Timer A operating
mode bits
“00”, “01”, “11”
TAOUT active
edge switch bit
“10”
“0”
T
Timer A start
signal
P50
/TAOUT
“
IGBT outp
PWM m
(Note)
P5
direction
register
0
Pulse output mode
P5
0 latch
S
Q
Q
Output selection bit
“1”
OUT active
dge switch bit
Note: The initial value of M version put).
Fig. 19 Block diagram of timer A
b7
b0
b7
b0
Timer A control register
(TACON : address 003116)
Tie register
(TAdress 003016)
Noise filter sampling clock selection bit
0 : f(XIN)/2
1 : f(XIN)/4
External trigger delay time selection bits
0 0 : No delay
0 1 : ( 4/f(XIN))µs
1 0 : ( 8/f(XIN))µs
1 1 : (16/f(XIN))µs
Timer A output control bit 1 (P56)
0 : Not used
Timer A operating mode bits
00 : Timer mode
01 : Pulse output mode
10 : IGBT output mode
11 : PWM mode
Timer A write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer A count source selection bits
0 0 : f(XIN)
0 1 : f(XIN)/2
1 0 : f(XIN)/4
1 1 : f(XIN)/8
Timer A output active edge switch bit
0 : Output starts with “L” level
1 : Output starts with “H” level
Timer A count stop bit
0 : Count operating
1 : INT1 interrupt used
Timer A output control bit 2 (P57)
0 : Not used
1 : INT2 interrupt used
Not used (returns “0” when read)
1 : Count stop
Timer A output selection bit (P50)
0 : I/O port
1 : Timer A output
Fig. 20 Structure of timer A related registers
22
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
t
s
Timer A count
source
Timer A
PWM mode
IGBT output mode
(n-m+1) ✕ ts
m ✕ ts
(n+1) ✕ ts
Note: PWM waveform (duty : (n-m+1)/(n+1) and period : (n+1) tput.
n : setting value of Timer A
m : setting value of compare register
ts : period of Timer A count source
Fig. 21 Timing chart of timer A PWM, IGBT output modes
■Notes on Timer A
mer A mode register
(1) Write order to timer A
write control bit to “1” (write to the latch only) when setting the
and PWM modes.
• In the timer and pulse output modes, write to the timer A registe
(low-order) first and to the timer A register (high-order) next. D
write to only one side.
utput waveform simultaneously reflects the contents of both regis-
ters at the next underflow after writing to the timer A register (high-
order).
• In the IGBT and PWM modes, write to the registers as
the compare register (high- and low-order)
the timer A register (low-order)
(5) Output control function of timer A
the timer A register (high-order).
When using the output control function (INT1 and INT2) in the IGBT
mode, set the levels of INT1 and INT2 to “H” in the falling edge active
or to “L” in the rising edge active before switching to the IGBT mode.
It is possible to use whichever order to writare register
(high- and low-order). However, write bre register and
the timer A register at the same tim
(2) Read order to timer A
• In all modes, read to the timer A regr (high-order) first and to the
timer A register (low-order) next. Read order to the compare regis-
ter is not specified.
• If reading to the timer A register during write operation or writing to
it during read operation, normal operation will not be performed.
(3) Write to timer A
• When writing a value to the timer A address to write to the latch
only, the value is set into the reload latch and the timer is updated
at the next underflow. Normally, when writing a value to the timer A
address, the value is set into the timer and the timer latch at the
same time, because they are written at the same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, an ex-
pected value may be set in the high-order counter.
• Do not switch the timer count source during timer count operation.
Stop the timer count before switching it. Additionally, when perform-
ing write to the latch and the timer at the same time, the timer count
value may change large.
23
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O pins of serial I/O also operate as I/O port P4, and their function is
selected by the serial I/O control register 1 (address 001916).
SERIAL I/O
The 38C3 group has a built-in 8-bit clock synchronous serial I/O. The
Internal synchronous
clock selection bits
Data bus
1/8
Internal
XCIN
system clock
1/16
1/32
1/64
“1”
selection bit
XIN
1/128
1/256
“0”
P47 latch
Synchronous clock
selection bit
“0”
“1”
P47/SRDY
SRDY
Synchronous
circuit
“1”
SRDY output selection bit
“0”
External clock
P46 latch
“0”
P46/SCLK1
Serial I/O
interrupt request
Serial I/O cou
“1”
Serial I/O port selection bit
P45 latch
“0”
P45/SOUT
P44/SIN
“1”
Serial I/O port selection bit
t register (8)
P40 latch
“0”
P40/SCLK2
“1”
Serial I/O port selection bit
Fig. 22 Block diagram of seria
24
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When internal clock is selected, serial I/O starts to transfer by a write
signal to the serial I/O register (address 001B16). After 8 bits have
been transferred, the SOUT pin goes to high impedance.
[Serial I/O Control Registers 1, 2 (SIOCON1,
SIOCON2)] 001916, 001A16
Each of the serial I/O control registers 1, 2 contains 8 bits that select
When external clock is selected, the clock must be controlled exter-
nally because the contents of the serial I/O register continue to shift
while the transfer clock is input. In this case, the SOUT pin does not
go to high impedance at the completion of data transfer.
various control parameters of serial I/O.
●Operation in serial I/O mode
Either an internal clock or an external clock can be selected as the
synchronous clock for serial I/O transfer. A dedicated divider is built-
in as the internal clock, giving a choice of six clocks.
The interrupt request bit is set at the end of the transfer of 8 bits,
regardless of whether the internal or external clock is selected.
b7
b0
b7
b0
Serial I/O control register 1
(SIOCON1 : address 001916
Serial I/O control register 2
(SIOCON2: address 001A16
)
)
Internal synchronous clock selection bits
b2 b1 b0
ynchronous clock output pin selection bit
: SCLK1
CLK2
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(XIN)/8 or f(XCIN)/8
1 : f(XIN)/16 or f(XCIN)/16
0 : f(XIN)32 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/64
0 : f(XIN)/128 or f(XCIN)/128
1 : f(XIN)/256 or f(XCIN)/256
d (returns “0” when read)
Serial I/O port selection bit (P4
0 : I/O port
0
, P4
5, P4
6
)
1 : SOUT, SCLK1, SCLK2 signal pin
S
RDY output selection bit (P4
0 : I/O port
7)
1 : SRDY signal pin
Transfer direction selection bit
0 : LSB first
1 : MSB first
Synchronous clock selection bit
0 : External clock
1 : Internal clock
P-channel output disable bit (
0 : CMOS output (in outp
1 : N-channel open-drode)
Fig. 23 Structure of serial I/O control regist
Synchronous clock
Transfer clock
Serial I/O register
write signal
(Note)
Serial I/O output
SOUT
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O input
SIN
Receive enable signal
SRDY
Note: When internal clock is selected, the SOUT pin goes to high impedance after
Interrupt request bit set
transfer ends.
Fig. 24 Serial I/O timing (for LSB first)
25
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Note that the comparator is constructed linked to a capacitor, so set
f(XIN) to at least 500 kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal system clock.
A-D CONVERTER
The 38C3 group has a 10-bit A-D converter. The A-D converter per-
forms successive approximation conversion.
[A-D Conversion Register (AD)] 003316, 003416
One of these registers is a high-order register, and the other is a low-
order register. The high-order 8 bits of a conversion result is stored in
the A-D conversion register (high-order) (address 003416), and the
low-order 2 bits of the same result are stored in bit 7 and bit 6 of the
A-D conversion register (low-order) (address 003316).
b7
b0
A-D control register
(ADCON: address 003216
)
Analog input pin selection bits
000: P6 /AN
001: P6 /AN
0
0
During A-D conversion, do not read these registers.
1
1
010: P6
011: P6
100: P6
101: P6
110: P6
111: P6
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
2
3
4
5
6
7
[A-D Control Register (ADCON)] 003216
This register controls A-D converter. Bits 2 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conver-
sion.
Not used (returns “0” when read)
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
A-D conversion is started by setting “0” in this bit.
Not used (returns “0” when read)
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
and VREF, and outputs the divided voltages.
b0
A-D conversion register (high-order)
(ADH: address 003416
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
)
AD conversion result stored bits
AN0 and inputs it to the comparator.
[Comparator and Control Circuit]
b7
b0
The comparator and control circuit compares an analog i
age with the comparison voltage and stores the resu
conversion register. When an A-D conversion is comon-
trol circuit sets the AD conversion completion bit onver-
sion interrupt request bit to “1.”
A-D conversion register (low-order)
(ADL: address 003316
)
Not used (returns “0” when read)
AD conversion result stored bits
Fig. 25 Structure of A-D control register
Data bus
b7
b0
A-D control register
3
P6
P6
P6
P6
P6
P6
P6
P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
A-D control circuit
A-D interrupt request
A-D conversion register (H)
Comparator
A-D conversion register (L)
(Address 003416
)
(Address 003316
)
Resistor ladder
AVSS
VREF
Fig. 26 Block diagram of A-D converter
26
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
segment output enable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, per-
forms the bias control and the duty ratio control, and displays the
data on the LCD panel.
LCD DRIVE CONTROL CIRCUIT
The 38C3 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
• LCD display RAM
• Segment output enable register
• LCD mode register
Table 7 Maximum number of display pixels at each duty ratio
• Selector
Duty ratio
1
Maximum number of display pixels
32 dots
or 8 segment LCD 4 digits
• Timing controller
• Common driver
• Segment driver
64 dots
or 8 segment LCD 8 digits
2
3
4
• Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
96 dots
or 8 segment LCD 12 digits
128 dots
or 8 segment LCD 16 digits
Up to 128 pixels can be controlled for a LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register, the
b7
b0
Segment output enable regis
(SEG : address 003816
)
Segment output e
0 : I/O ports
1 : Segme
Segment t 1
0 : I/
1 : t SEG
Senable bit 2
P0 –P0
nt output SEG
utput enable bit 3
O ports P0 –P0
–SEG
3
7
4–SEG
0
3
8–SEG11
4
7
Segment output SEG12–SEG15
gment output enable bit 4
0 : I/O ports P10–P13
1 : Segment output SEG16–SEG19
Segment output enable bit 5
0 : I/O ports P14–P17
1 : Segment output SEG20–SEG23
Segment output enable bit 6
0 : Output ports P30–P33
1 : Segment output SEG24–SEG27
Segment output enable bit 7
0 : Output ports P3
4–P37
1 : Segment output SEG28–SEG31
b
b0
LCD mode register
(LM : address 003916
)
Duty ratio selection bits
0 0 : 1 (use COM
0 1 : 2 (use COM
1 0 : 3 (use COM
1 1 : 4 (use COM
Bias control bit
0 : 1/3 bias
0
0
0
0
)
,COM1)
–COM
–COM
2
)
3)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit.)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
Fig. 27 Structure of LCD related registers
27
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 28 Block diagram of LCD controller/driver
28
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8 Bias control and applied voltage to VL1–VL3
Bias Control and Applied Voltage to LCD Power
Input Pins
Bias value
Voltage value
To the LCD power input pins (VL1–VL3), apply the voltage value shown
VL3=VLCD
1/3 bias
VL2=2/3 VLCD
VL1=1/3 VLCD
in Table 8 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
VL3=VLCD
VL2=VL1=1/2 VLCD
1/2 bias
1/1 bias
VL3=VLCD
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by duty
ratio.
(1-duty ratio) VL2=VL1=VSS
Note 1: VLCD is the maximum value of supplied voltage for the LCD panel.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
Table 9 Duty ratio control and common pins used
When selecting 1-duty ratio, 1/1 bias can be used.
Duty ratio selection bit
Duty
ratio
Common pins used
COM0 (Note 1)
Bit 1
Bit 0
1
2
3
4
0
0
1
1
0
1
COM0, COM1 (Note 2)
M0–COM2 (Note 3)
COM0–COM3
Notes 1:COM1, CM3 are open.
2:COMe open.
3:CO
Contrast control
trol
Contrast control
V
L3
V
L3
V
L3
R1
R4
R5
V
V
L2
L1
V
V
L2
L1
V
L2
R3
V
L1
R6
R4 = R5
R1 = R2 = R3
1/3 bias
1/2 bias
1/1 bias
Fig. 29 Example of circuit at each bias
29
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD Display RAM
LCD Drive Timing
Address 004016 to 004F16 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding seg-
ments of the LCD display panel are turned on.
The LCDCK timing frequency (LCD drive timing) is generated inter-
nally and the frame frequency can be determined with the following
equation;
(frequency of count source for LCDCK)
f(LCDCK)=
(divider division ratio for LCD)
f(LCDCK)
Frame frequency=
duty ratio
Bit
7
6
5
4
3
2
1
0
Address
004016
004116
004216
004316
004416
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG
S
SEG0
SEG2
SEG4
SEG6
SE
16
EG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
COM3 1 COM0 COM3 COM2 COM1 COM0
Fig. 30 LCD display RAM map
30
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal
signal
LCDCK
timing
1/4 duty
Voltage level
V
V
V
L3
L2=VL1
SS
COM
COM
COM
COM
0
1
2
3
V
V
L3
SEG
0
SS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
2
COM
1
1/3 duty
V
V
V
L3
L2=VL1
SS
COM
COM
COM
0
1
2
V
V
L3
SEG
0
SS
ON
OFF
ON
FF
ON
OFF
COM
COM
0
COM
2
COM
COM
2
COM
1
COM
0
2
1/2 duty
V
V
V
L3
L2=VL1
SS
COM
COM
0
1
V
V
L3
SEG
0
SS
ON
OFF
COM
ON
OFF
COM
ON
OFF
COM
ON
OFF
COM
COM
1
0
COM
1
0
COM
1
0
COM
1
0
1/1 duty (1/1 bias)
VL3
COM
0
V
L2=VL1=VSS
L3
V
SEG
0
VSS
OFF
ON
Fig. 31 LCD drive waveform (1/2 bias)
31
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal signal
LCDCK timing
1/4 duty
Voltage level
VL3
V
VL2
VSL1S
COM
0
COM
COM
COM
1
2
3
V
V
L3
SEG
0
SS
OFF
ON
ON
COM
3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
VL3
VL2
VSL1S
V
COM
COM
COM
0
1
2
V
V
L3
SEG
0
SS
O
FF
COM
ON
OFF
ON
OFF
COM
COM
COM
2
COM
1
COM
0
2
2
COM
1
COM0
1/2 duty
VL3
VL2
VSL1S
V
COM
COM
0
1
V
V
L3
SEG
0
SS
ON
OFF
COM
ON
COM
OFF
COM
ON
OFF
COM
ON
OFF
COM
COM
1
0
COM
1
0
COM
1
0
1
0
Fig. 32 LCD drive waveform (1/3 bias)
32
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
φ CLOCK OUTPUT FUNCTION
The internal system clock φ can be output from port P43 by setting
the φ output control register. Set “1” to bit 3 of the port P4 direction
register when outputting φ clock.
b7
b0
φ output control register
(CKOUT : address 002B16)
φ output control bit
0 : Port function
1 : φ clock output
Not used (return “0” wh
Fig. 33 Structure of φ output control register
33
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM CORRECTION FUNCTION
The 38C3 group has the ROM correction function correcting data at
ROM correct high-order address register 1
ROM correct low-order address register 1
ROM correct high-order address register 2
ROM correct low-order address register 2
ROM correct high-order address register 3
ROM correct low-order address register 3
ROM correct high-order address register 4
ROM correct low-order address register 4
ROM correct high-order address register 5
ROM correct low-order address register 5
ROM correct high-order address register 6
ROM correct low-order address register 6
ROM correct high-order address register 7
ROM correct low-order address register 7
ROM corrhigh-order address register 8
0F0216
0F0316
0F0416
0F0516
0F0616
0F0716
0F0816
0F0916
0F0A16
0F0B16
0F0C16
0F0D16
0F0E16
0F0F16
0F1016
the arbitrary addresses in the ROM area.
[ROM correct address register] 0F0216 – 0F1116
This is the register to store the address performing ROM correction.
There are two types of registers to correct up to 8 addresses: one is
the register to store the high-order address and the other is to store
the low-order address.
[ROM correct enable register (RC1)] 0F0116
This is the register to enable the ROM correction function. When set-
ting the bit corresponding to the ROM correction address to “1”, the
ROM correction function is enabled.
It becomes invalid to the addresses of which corresponding bit is “0”.
All bits are “0” at the initial state.
0F1116 ROM -order address register 8
[ROM correct data]
This is the register to store a correct data for the address specified by
Fig. 34 Structure rect address register
the ROM correct address register.
■Notes on ROM correction function
6
05116
005216
005316
005416
005516
005616
005716
ROM correct data 1
ROM correct data 2
ROM correct data 3
ROM correct data 4
ROM correct data 5
ROM correct data 6
ROM correct data 7
ROM correct data 8
1. To use the ROM correction function, transfer data to each ROM
correct data register in the initial setting.
2. Do not specify the same addresses in the ROM correct address
register.
Fig. 35 Structure of ROM correct data
b7
b0
ROM correct enable register 1(address 0F0116
RC1
)
ROM correct address 1 enable bit
0 : Disabled
1 : Enabled
ROM correct address 2 enable bit
0 : Disabled
1 : Enabled
ROM correct address 3 enable bit
0 : Disabled
1 : Enabled
ROM correct address 4 enable bit
0 : Disabled
1 : Enabled
ROM correct address 5 enable bit
0 : Disabled
1 : Enabled
ROM correct address 6 enable bit
0 : Disabled
1 : Enabled
ROM correct address 7 enable bit
0 : Disabled
1 : Enabled
ROM correct address 8 enable bit
0 : Disabled
1 : Enabled
Fig. 36 Structure of ROM correct enable register 1
34
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
Poweron
To reset the microcomputer, RESET pin should be held at an “L” level
for 2 µs or more. Then the RESET pin is returned to an “H” level (the
power source voltage should be between 2.5 V and 5.5 V, and the
oscillation should be stable), reset is released. After the reset is com-
pleted, the program starts from the address contained in address
FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make
sure that the reset input voltage is less than 0.5 V for VCC of 2.5 V
(switching to the high-speed mode, a power source voltage must be
between 4.0 V and 5.5 V).
(Note)
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; Vcc=2.5 V
RESET
V
CC
Power source
voltage detection
circuit
Ficircuit example
XIN
φ
RESET
Internal
reset
Reset address from
vector table
Address
Data
?
?
?
?
ADH, ADL
FFFC
FFFD
ADL
ADH
SYNC
XIN : about 8000 cycles
Note 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 38 Reset sequence
35
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
Address Register contents
002D16
FF16
000016
000116
000216
000316
(1)
(2)
(3)
(4)
0016
0016
0016
0016
(34)
(35)
(36)
(37)
(38)
Port P0
Timer A (high-order)
0016
0016
0016
0016
002E16
002F16
Port P0 direction register
Port P1
Compare register (low-order)
Compare register (high-order)
Timer A mode register
003016
003116
Port P1 direction register
Timer A control register
000416
000516
000616
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001616
001716
001816
0
6
002116
002216
002316
002416
002516
(5) Port P2
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0F
16
0016
FF16
003216
003816
(39)
(40)
A-D control register
(6) Port P2 direction register
1016
0016
0016
0016
Segment output enable register
Port P3
(7)
(8)
Port P4
LCD mode register
003916
003A16
(41)
(42)
(9)
Port P4 direction register
Port P5
Interrupt edge selection regi
CPU mode register
(10)
3B16
003C16
003D16
003E16
003F16
0F0116
(43)
(44)
(45)
(46)
(47)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
0 1 0 0 1 0 0 0
0016
(11) Port P5 direction register
(12) Port P6
Interrupt request
Interrupt re
Interruter 1
Iregister 2
ect enable register 1
0016
(13) Port P6 direction register
(14) Port P7
0016
0016
(15)
(16)
Port P7 direction register
Port P8
0016
correct high-order address
gister 1
ROM correct low-order address
register 1
0F0216
0F0316
FF16
(17) Port P8 direction register
FF16
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
PULL register A
PULL register B
Port P8 output selection register
Serial I/O control register 1
Serial I/O control register 2
Timer 1
ROM correct high-order address 0F0416
register 2
ROM correct low-order address 0F0516
register 2
FF16
FF16
ROM correct high-order address 0F0616
register 3
ROM correct low-order address 0F0716
register 3
ROM correct high-order address 0F0816
register 4
FF16
FF16
FF16
ROM correct low-order address
register 4
ROM correct high-order address
register 5
0F0916
FF16
Timer 2
0F0A16
FF16
0116
FF16
FF16
ROM correct low-order address 0F0B16
register 5
Timer 3
FF16
Timer 4
ROM correct high-order address 0F0C16
register 6
ROM correct low-order address 0F0D16
register 6
FF16
Timer 5
FF16
FF16
0016
0016
0016
0016
FF16
FF16
ROM correct high-order address
register 7
ROM correct low-order address
register 7
0F0E16
Timer 6
FF16
0F0F16
Timer 12 mode register
Timer 34 mode register
Timer 56 mode register
002816
002916
002A16
FF16
ROM correct high-order address 0F1016
register 8
FF16
ROM correct low-order address
register 8
0F1116
FF16
002B16
002C16
(PS) ✕ ✕ ✕ ✕ ✕
✕ ✕
1
Processor status register
(32)
(33)
φ output control register
(PCH)
(PCL)
FFFD16 contents
FFFC16 contents
Program counter
Timer A (low-order)
X: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
In the M version, bit 0 of the port P5 direction register becomes “1.”
Fig. 39 Internal status at reset
36
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Oscillation control
The 38C3 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No external re-
sistor is needed between XIN and XOUT since a feedback resistor
exists on-chip. However, an external feedback resistor is needed be-
tween XCIN and XCOUT.
(1) Stop mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116.”
Either XIN divided by 16 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0.” Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before execut-
ing the STP instruction. Oscillator restarts when an external interrupt
is received, but the internal system clock is not supplied to the CPU
until timer 2 underflows. This allows time for the clock circuit oscilla-
tion to stabilize.
Immediately after power on, only the XIN oscillation circuit starts os-
cillating, and XCIN and XCOUT pins function as I/O ports.
Frequency control
(1) Middle-speed mode
The internal system clock is the frequency of XIN divided by 8. After
reset, this mode is selected.
(2) Wait mode
If the WIT instruction is ex, the internal system clock stops at
an “H” level. The stateXCIN are the same as the state
before executing thtion. The internal system clock re-
starts at reset or errupt is received. Since the oscillator
does not stopration can be started immediately after the
clock is re
(2) High-speed mode
The internal system clock is the frequency of XIN divided by 2.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
■Notes on clock generating circuit
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode betwe
middle/high-speed and low-speed, set the frequency on co
that f(XIN) > 3f(XCIN).
XCIN
XCOUT
XIN
XOUT
Rf
Rd
COUT
CCIN
CCOUT
CIN
Fig. 40 Ceramic resonator circuit
X
CIN
X
COUT
X
IN
XOUT
Rf
open
External oscillation circuit
Rd
CCOUT
CCIN
VCC
V
SS
Fig. 41 External clock input circuit
37
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCOUT
XCIN
“1”
“0”
Port XC switch bit
Timer 1 count
source selection
bit
Timer 2 count
source selection
bit
Internal system clock selection bit
(Note)
XIN
XOUT
Low-speed mode
“1”
“1”
“0”
Timer 1
Timer 2
1/2
1/2
1/4
“0”
Middle-/High-speed mode
“0”
“1”
Main clock division ra
Middle-speed mod
“1”
Timing φ
(Internal system clock)
“0”
High-speed mode
or Low-speed mode
Main clock stop bit
Q
S
R
R
Q
S
R
W
STP instruction
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Note : When using the low-speed mode, set the port XC switch bit to “1” .
Fig. 42 Clock generating circuit block diagram
38
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
High-speed mode
(f( ) =4 MHz)
Middle-speed mode
(f(φ)=1 MHz)
CM
“1”
6
φ
CM
CM
CM
CM
7
6
5
4
=0(8 MHz selected)
=0(high-speed)
=0(8 MHz oscillating)
=0(32 kHz stopped)
“0”
CM7
CM6
CM5
CM4
=0(8 MHz selected)
=1(middle-speed)
=0(8 MHz oscillating)
=0(32 kHz stopped)
“0”
CM
4
“0”
6
4
“1”
CM
CM
“0”
“1”
6
CM
“1”
“1”
“0”
Middle-speed mode
((f(φ)=1 MHz)
High-speed mode
(f( ) =4 MHz)
CM
6
φ
“1”
“0”
CM
CM
CM
CM
7
=0(8 MHz selected)
=1(middle-speed)
=0(8 MHz oscillating)
=1(32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
=0(8 MHz selected)
=0(high-speed)
=0(8 MHz oscillating
=1(32 kHz oscillat
6
5
4
Low-speed mode
speed mode
((f(φ)=16 kHz)
(f(φ) =16 kHz)
CM
6
CM
CM
CM
CM
7
=1(32 kHz selected)
=1(middle-speed)
=0(8 MHz oscillating)
“1”
“0”
M
CM
CM
CM
7
6
5
4
=1(32 kHz selected)
=0(high-speed)
=0(8 MHz oscillating)
=1(32 kHz oscillating)
6
5
4
b7
b4
CPU mode register
=1(32 kHz oscillating)
(CPUM : address 003B16
)
CM
CM
CM
CM
4 : Port Xc switch bit
0: I/O port function
1: XCIN-XCOUT oscillating function
“0”
CM
5
“0
6
5
“1”
CM
5
: Main clock (XIN- XOUT) stop bit
“0”
“1”
6
“1”
0: Oscillating
1: Stopped
CM
“0”
“1”
6: Main clock division ratio selection bit
Low-speed mode
(f( ) =16 kHz)
Low-speed mode
((f(φ)=16 kHz)
0: f(XIN)/2(High-speed mode)
1: f(XIN)/8 (Middle-speed mode)
φ
CM
6
7: Internal system clock selection bit
CM
7
6
5
4
=1(32 kHz selected)
=1(middle-speed)
=1(8 MHz stopped)
CM
CM
CM
CM
7
=1(32 kHz selected)
=0(high-speed)
=1(8 MHz stopped)
“1”
“0”
0: XIN–XOUT selected (Middle-/High-speed mode)
1: XCIN–XCOUT selected (Low-speed mode)
CM
CM
CM
6
5
4
=1(32 kHz oscillating)
=1(32 kHz oscillating)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended.
3: Timer,LCD operate in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by connecting Timer 1 and Timer 2 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs in low-speed mode.
6: Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/high-speed mode.
7: The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal system clock.
Fig. 43 State transitions of system clock
39
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
A-D Converter
Processor Status Register
The comparator uses internal capacitors whose charge will be lost if
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D
conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
Instruction Execution Time
Interrupts
The instruction execution time is obtained by multiplying the frequency
of the internal system clock by the number of cycles needed to ex-
ecute an instruction.
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
The frequency of the internal system clock is the same half of the XIN
frequency in high-speed mode.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
At STP Instructiase
At the STP instructill bits of the timer 12 mode register
are cleared.
• In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
NOTES
Notelt-in EPROM Version
The e One Time PROM version or the EPROM version
he power source input pin of the internal EPROM.
, this pin is set at low input impedance, thereby being af-
easily by noise.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not
the MUL and DIV instruction.
prevent a malfunction due to noise, insert a resistor (approx. 5 kΩ)
in series with the P51 pin.
• The execution of these instructions does not change
of the processor status register.
Ports
The contents of the port direction registeread. The fol-
lowing cannot be used:
• The data transfer instruction (LDA
• The operation instruction when mode flag (T) is “1”
• The addressing mode which usealue of a direction register
as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
• Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
• Using an internal clock
When using an internal clock, set the synchronous clock to the in-
ternal clock, then clear the serial I/O interrupt request bit before
executing a serial I/O transfer and serial I/O automatic transfer.
40
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1. Mask ROM Order Confirmation Form
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-in
EPROM version can be read or programmed with a general-purpose
PROM programmer using a special programming adapter.
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical copies)
Table 10 Programming adapter
DATA REQUIRED FOR ROM WRITING ORDERS
The following are necessary when ordering a ROM writing:
1. ROM Writing Confirmation Form
Package
80P6N-A
80D0
Name of Programming Adapter
PCA4738F-80A
PCA4738L-80A
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical copies)
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 44 is recommended to verify programming.
mming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 44 Programming and testing of One Time PROM version
41
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 11 Absolute maximum ratings
Symbol
VCC
Unit
V
Parameter
Power source voltage
Conditions
Ratings
–0.3 to 7.0
VI
V
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67, P70,
P71, P80–P87
–0.3 to VCC+0.3
All voltages are based on
Vss. Output transistors
are cut off.
VI
VI
VI
VI
V
V
V
V
V
V
V
V
Input voltage
Input voltage
Input voltage
VL1
VL2
VL3
–0.3 to VL2
VL1 to VL3
VL2 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VL3+0.3
–0.3 to VL3+0.3
–0.3 to VCC+0.3
Input voltage RESET, XIN
At output port
VO
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37
At segment output
VO
VO
Output voltage COM0–COM3
Output voltage P40–P47, P50, P52–P57, P60–P67,
P70, P71, P80–P87
VO
V
Output voltage XOUT
Power dissipation
3 to VCC+0.3
300
Pd
mW
°C
Ta = 25°C
Topr
Tstg
Operating temperature
Storage temperature
–20 to 85
–40 to 125
°C
Table 12 Recommended operating conditions (Vcc = 2.5 to 5.5 V, Ta = –nless otherwise noted)
Limits
Typ.
5.0
5.0
5.0
0
Symbol
VCC
Parameter
Unit
Min.
4.0
2.5
2.5
Max.
5.5
Power source voltage
Power source voltage
High-speed mode f(XI
Middle-speed modHz
Low-speed mod
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
5.5
5.5
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIL
A-D converter reference voltage
Analog power source voltage
Analog input voltage AN0–AN
2.0
VCC
0
AVSS
VCC
VCC
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
P00–7, P20–P27
0.7VCC
PP57, P60–P67, P70, P71 (CM4 = 0)
0.8VCC
VCC
0.4VCC
VCC
0.8VCC
VCC
X
0.8VCC
VCC
P00–P07, P10–P17, P20–P27
0
0
0
0
0
0.3VCC
0.2VCC
0.16VCC
0.2VCC
0.2VCC
VIL
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
VIL
P80–P87
RESET
XIN
VIL
VIL
42
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 13 Recommended operating conditions (Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
mA
Min.
Max.
–60
“H” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
P80–P87, P50
ΣIOH(peak)
“H” total peak output current (Note 1)
–30
40
mA
mA
mA
mA
mA
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
P40–P47, P52–P57, P60–P67, P70, P71
“L” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“L” total peak output current (Note 1)
80
P80–P87, P50
“L” total peak output current (Note 1)
40
P40–P47, P52–P57, P60–P67, P70, P71
“H” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
P80–P87, P50
–30
“H” total average output current (Note 1)
–15
20
mA
mA
mA
mA
mA
mA
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
P40–P47, P52–P57, P60–P67, P70, P71
“L” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“L” total average output current (Note 1)
40
P80–P87, P50
“L” total average output current (Note 1)
20
P40–P47, P52–P57, P60–P67, P70, P71
“H” peak output current (Note 2)
–2.0
–10
P00–P07, P10–P17, P20–P27, P30–P37
“H” peak output current (Note 2)
P40–P47, P50, P52–P57, P60–P67, P70,
P80–P87
“L” peak output current (Note 2)
5.0
10
mA
mA
mA
mA
mA
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
P00–P07, P10–P17, P20–P27, P
“L” peak output current (Note 2)
P40–P47, P52–P57, P60–1
“L” peak output current (N
30
P80–P87, P50
“H” average output c3)
–2.0
–5.0
P00–P07, P127, P30–P37
“H” average o(Note 3)
P40–P4P57, P60–P67, P70, P71
P80–P
“L” average oucurrent (Note 3)
2.5
5.0
15
mA
mA
mA
IOL(avg)
IOL(avg)
IOL(avg)
P00–P07, P10–P17, P20–P27, P30–P37
“L” average output current (Note 3)
P40–P47, P52–P57, P60–P67, P70, P71
“L” average output current (Note 3)
P80–P87, P50
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over
100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
43
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Recommended operating conditions (Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Unit
Parameter
Min.
Max.
4.0
f(CNTR0)
f(CNTR1)
f(XIN)
Input frequency (duty cycle 50%)
(4.0 V ≤ VCC ≤ 5.5 V)
(VCC ≤ 4.0 V)
MHz
MHz
MHz
(2✕VCC)–4
8.0
Main clock input oscillation frequency (Note 4)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(4✕VCC)–8
MHz
(VCC ≤ 4.0 V)
Middle-speed mode
8.0
50
MHz
kHz
f(XCIN)
Sub-clock input oscillation frequency (Notes 4, 5)
32.768
Notes 4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
44
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 15 Electrical characteristics (Vcc = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol Parameter Test conditions
IOH = –2.0 mA
Limits
Typ.
Unit
Min.
Max.
VOH
“H” output voltage
VCC–2.0
VCC–1.0
V
V
P00–P07, P10–P17, P20–P27,
P30–P37
IOH = –0.6 mA
VCC = 2.5 V
VOH
VOL
VOL
“H” output voltage
P40–P47, P50, P52–P57,
P60–P67, P70, P71,
P80–P87
IOH = –5 mA
VCC–2.0
VCC–0.5
VCC–1.0
V
V
V
IOH = –1.25 mA
(Note) IOH = –1.25 mA
VCC = 2.5 V
“L” output voltage
P00–P07, P10–P17, P20–P27,
P30–P37
IOL = 2.5 mA
2.0
0.5
1.0
V
V
V
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
“L” output voltage
P40–P47, P52–P57, P60–P67,
P70, P71
IOL = 5.0 mA
2.0
0.5
1.0
V
V
V
IOL = 2.5 mA
(Note) IOL = 2.5 mA
VCC = 2.5 V
VOL
“L” output voltage P80–P87, P50
Hysteresis
IOL = 15 mA
2.0
V
V
VT+–VT-
0.5
INT0–INT2, CNTR0, CNTR1, P80–P87
Hysteresis SCLK1, SIN
Hysteresis RESET
VT+–VT-
VT+–VT-
0.5
0.5
V
V
RES
V5.5 V
IIH
“H” input current
5.0
140
45
µA
µA
µA
µA
P00–P07, P10–P17, P20–P27
wn “off”
= 5.0 V, VI = VCC
Pull-down “on”
VCC = 3.0 V, VI = VCC
Pull-down “on”
VI = VCC
30
70
25
6.0
IIH
“H” input current
5.0
P40–P47, P50–P57, P
P70, P71, P80–P8
IIH
IIH
IIL
“H” input current
“H” input curren
“L” input current
VI = VCC
VI = VCC
5.0
–5.0
–5.0
–140
–45
–5
µA
µA
µA
4.0
P00–P07, P10–7, P20–P27, P51
“L” input current
IIL
VI = VSS
µA
µA
µA
P40–P47, P50, P52–P57,
P60–P67, P70, P71, P80–P87
Pull-up “off”
VCC = 5.0 V, VI = VSS
Pull-up “on”
–30
–6
–70
–25
VCC = 3.0 V, VI = VSS
Pull-up “on”
IIL
IIL
“L” input current RESET
“L” input current XIN
VI = VSS
µA
µA
VI = VSS
–4
Note: When “1” is set to the port XC switch bit (bit 4 of address 003B16) of the CPU mode register, the drive ability of Port P70 is different from the value above
mentioned.
45
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 16 Electrical characteristics (Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
2.0
Max.
5.5
VRAM
ICC
RAM hold voltage
When clock is stopped
V
Power source current
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter in operating
6.4
1.6
15
13
mA
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter stopped
3.2
22
mA
µA
µA
Low-speed mode, VCC = 3 V,
Ta ≤ 55 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode, VCC = 3 V,
Ta = 25 °C
4.5
9.0
f(XIN) = stopped
f(XCIN) = 32.768 kHz
(in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
0.1
1.0
10
µA
µA
Ta
C
Output transistors “off”
46
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 17 A-D converter characteristics
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-speed/high-speed mode)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
10
—
—
Resolution
Bits
LSB
tc(φ)
µA
Absolute accuracy (excluding quantization error)
Conversion time
VCC = VREF = 5.12 V
VREF = 5 V
±1
±2.5
62
Tconv
61
50
IVREF
IIA
Reference input current
Analog port input current
Ladder resistor
150
0.5
35
200
5.0
µA
RLADDER
kΩ
47
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18 Timing requirements 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
250
105
105
80
twL(INT)
80
tc(SCLK)
800
370
370
2
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
Serial I/O input hold time
Table 19 Timing requirements 2 (Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, ise noted)
Limits
Symbol
Parameter
Reset input “L” pulse width
Unit
Min.
Typ.
Max.
tw(RESET)
tc(XIN)
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse wi
CNTR0, CNTR1 input “L” pulse
INT0–INT2 input “H” pulse w
INT0–INT2 input “L” puls
Serial I/O clock inpu
Serial I/O clock inwidth
Serial I/O cloclse width
Serial I/O ime
125
twH(XIN)
45
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
500/(VCC–2)
250/(VCC–2)–20
250/(VCC–2)–20
230
230
2000
950
950
400
200
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
Serial I/O inptime
48
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20 Switching characteristics 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
twH(SCLK)
Parameter
Unit
Min.
Typ.
Max.
140
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tc(SCLK)/2–30
tc(SCLK)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
(Note 1)
(Note 1)
Serial I/O output valid time
–30
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
30
30
30
30
tf(SCLK)
tr(CMOS)
tf(CMOS)
(Note 2)
(Note 2)
10
10
CMOS output falling time
Notes 1: When the P-channel output disable bit (bit 7 of address 001916) is “0.”
2: The XOUT, XCOUT pins are excluded.
Table 21 Switching characteristics 2 (Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otheoted)
mits
Symbol
twH(SCLK)
Parameter
Unit
Typ.
Max.
350
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
50
/2–50
ns
ns
ns
ns
ns
ns
ns
ns
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
(Note
(No
Serial I/O output valid time
–30
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
50
50
50
50
tf(SCLK)
tr(CMOS)
tf(CMOS)
2)
ote 2)
20
20
CMOS output falling time
Notes 1: When the P-channel output disable bit (bit 7 of address 001
2: The XOUT, XCOUT pins are excluded.
1 kΩ
Measurement output pin
Measurement output pin
100 pF
100 pF
N-channel open-drain output
CMOS output
Note: When bit 7 of the serial I/O control register 1 (address 0019 16) is “ 1.”
(N-channel open-drain output mode)
Fig. 45 Circuit for measuring output switching characteristics
49
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR)
tWL(CNTR)
0.2VCC
tWH(CNTR)
0.8VCC
CNTR0,CNTR1
twL(INT)
0.2VCC
twH(INT)
INT0 – INT3
0.8VCC
tW(RESET)
0.8VCC
RESET
0.2VCC
tC(XIN)
tWL(XIN)
0.2VCC
IN)
XIN
tC(SCLK)
tr
tf
tWL(SCLK)
tWH(SCLK)
0.8VCC
SCLK
SIN
0.2VCC
tsu(SIN-SCLK)
th(SCLK-SIN)
0.8VCC
0.2VCC
td(SCLK-SOUT)
tv(SCLK-SOUT)
SOUT
Fig. 46 Timing diagram
50
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-95B<85A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38C34M6AXXXFP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROed.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain idewe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask Rthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer,
EPROM address
000016
Eess
the internal ROM area is from address A08016
to FFFD16. The reset vector is stored in
addresses FFFC16 and FFFD16.
Product name
ASCII code :
‘M38C34M6A’
Product name
ASCII code :
‘M38C34M6A’
0F16
001016
000F16
001016
A07F16
A08016
207F16
208016
Data
Data
ROM 24K-130 bytes
ROM 24K-130 bytes
FFFD16
FFFE16
FFFF16
7FFD16
7FFE16
7FFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
Address
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘4’ = 3416
‘M’ = 4D16
‘6’ = 3616
‘ A ’ =4116
FF16
(2) The ASCII codes of the product name “M38C34M6A” must
be entered in addresses 000016 to 000816. And set data
“FF16” in addresses 000916 to 000F16. The ASCII codes
and addresses are listed to the right in hesadecimal
notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
51
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-95B<85A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6AXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27256
27512
*=∆$8000
.BYTE∆‘M38C34M6A’
*=∆$0000
.BYTE∆‘M38C34M6A’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the M confirmation form, the ROM
will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the pacordered. Fill out the appropriate mark
specification form (80P6N) and attach it to the mask ROM confirmati
❈ 3. Usage conditions
Please answer the following questions about usage for use ict inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz c
Othe
)
At what frequency?
(2) Which function will you use the P70/XCIN anpins?
Port P70 and P71 function
f(XIN
MHz
N-XCOUT function (external resonator)
❈ 4. Comments
(2/2)
52
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-96B<85A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M38C34M6MXXXFP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROed.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain idewe will produce masks based on this data. We
shall assume the responsibility for errors only if the mask Rthe products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
In the address space of the microcomputer,
EPROM address
000016
Eess
the internal ROM area is from address A08016
to FFFD16. The reset vector is stored in
addresses FFFC16 and FFFD16.
Product name
ASCII code :
‘M38C34M6M’
Product name
ASCII code :
‘M38C34M6M’
0F16
001016
000F16
001016
A07F16
A08016
207F16
208016
Data
Data
ROM 24K-130 bytes
ROM 24K-130 bytes
FFFD16
FFFE16
FFFF16
7FFD16
7FFE16
7FFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
Address
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘4’ = 3416
‘M’ = 4D16
‘6’ = 3616
‘ M ’ =4D16
FF16
(2) The ASCII codes of the product name “M38C34M6M” must
be entered in addresses 000016 to 000816. And set data
“FF16” in addresses 000916 to 000F16. The ASCII codes
and addresses are listed to the right in hesadecimal
notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
53
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH52-96B<85A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6MXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27256
27512
*=∆$8000
.BYTE∆‘M38C34M6M’
*=∆$0000
.BYTE∆‘M38C34M6M’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the M confirmation form, the ROM
will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the pacordered. Fill out the appropriate mark
specification form (80P6N) and attach it to the mask ROM confirmati
❈ 3. Usage conditions
Please answer the following questions about usage for use ict inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz c
Othe
)
At what frequency?
(2) Which function will you use the P70/XCIN anpins?
Port P70 and P71 function
f(XIN
MHz
N-XCOUT function (external resonator)
❈ 4. Comments
(2/2)
54
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH52-97B<85A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C37ECAXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROed.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain idewe will produce ROM programming based on
this data. We shall assume the responsibility for errors only programming data on the products we produce
differs from this data. Thus, extreme care must be taken tdata in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
ddress space of the microcomputer,
nternal ROM area is from address 408016
FFFD16. The reset vector is stored in
addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
ASCII code :
‘M38C37ECA’
000F16
001016
407F16
408016
Data
ROM 48K-132 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘7’ = 3716
‘E’ = 4516
‘C’ = 4316
‘ A ’ =4116
FF16
(2) The ASCII codes of the product name “M38C37ECA” must
be entered in addresses 000016 to 000816. And set data
“FF16” in addresses 000916 to 000F16. The ASCII codes
and addresses are listed to the right in hesadecimal
notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
55
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH52-97B<85A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C37ECAXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
*=∆$0000
.BYTE∆‘M38C37ECA’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the gramming confirmation form,
the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the pacordered. Fill out the appropriate mark
specification form (80P6N) and attach it to the ROM programming coform.
❈ 3. Usage conditions
Please answer the following questions about usage for use ict inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz c
Othe
)
At what frequency?
(2) Which function will you use the P70/XCIN anpins?
Port P70 and P71 function
f(XIN
MHz
N-XCOUT function (external resonator)
❈ 4. Comments
(2/2)
56
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH52-98B<85A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C37ECMXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROed.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain idewe will produce ROM programming based on
this data. We shall assume the responsibility for errors only programming data on the products we produce
differs from this data. Thus, extreme care must be taken tdata in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
ddress space of the microcomputer,
ternal ROM area is from address 408016
FFFD16. The reset vector is stored in
addresses FFFC16 and FFFD16.
EPROM address
000016
Product name
ASCII code :
‘M38C37ECM’
000F16
001016
407F16
408016
Data
ROM 48K-132 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘7’ = 3716
‘E’ = 4516
‘C’ = 4316
‘ M ’ =4D16
FF16
(2) The ASCII codes of the product name “M38C37ECM” must
be entered in addresses 000016 to 000816. And set data
“FF16” in addresses 000916 to 000F16. The ASCII codes
and addresses are listed to the right in hesadecimal
notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
57
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH52-98B<85A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C37ECMXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
*=∆$0000
.BYTE∆‘M38C37ECM’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the gramming confirmation form,
the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the pacordered. Fill out the appropriate mark
specification form (80P6N) and attach it to the ROM programming coform.
❈ 3. Usage conditions
Please answer the following questions about usage for use ict inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz c
Othe
)
At what frequency?
(2) Which function will you use the P70/XCIN anpins?
Port P70 and P71 function
f(XIN
MHz
N-XCOUT function (external resonator)
❈ 4. Comments
(2/2)
58
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6N (80-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
64
41
40
65
Mitsubishi IC catalog name
Mitsubishi product number
(6-digit, or 7-digit)
80
25
1
24
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
64
41
40
65
mer’s Parts Number
ote : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Notes 1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
80
1
C. Special Mark Required
Notes1 :If special mark is to be printed, indicate the desired lay-
out of the mark in the left figure. The layout will be
duplicated technically as close as possible.
Mitsubishi product number (6-digit, or 7-digit) and Mask
ROM number (3-digit) are always marked for sorting the
products.
64
41
40
65
2 : If special character fonts (e,g., customer’s trade mark
logo) must be used in Special Mark, check the box be-
low.
80
25
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
1
24
Special character fonts required
59
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6N-A
Plastic 80pin 14✕20mm body QFP
EIAJ Package Code
QFP80-P-1420-0.80
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
M
D
HD
D
80
65
1
64
I2
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
0
–
0.3
0.13
13.8
19.8
–
16.5
22.5
0.4
–
Nom
–
Max
3.05
0.2
–
0.45
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.1
10°
–
A1
0.1
2.8
0.35
0.15
14.0
20.0
0.8
16.8
22.8
0.6
1.4
–
–
0.5
–
14.6
20.6
c
D
E
e
24
41
25
40
A
H
H
D
E
L
L1
y
–
0°
–
1.3
–
F
e
b
L
b2
ail F
I2
–
–
y
M
M
D
E
–
–
80D0
Glass seal 80pin QFN
EIAJ Package Code
JEDEC Code
–
–
21.
18.4±0.15
3.32MAX
1.78TYP
0.8TYP
0.6TYP
41
64
65
40
25
80
1
24 1.2TYP
INDEX
60
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
•
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
•
•
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1998 MITSUBISHI ELECTRIC CORP.
New publication, effective Jun. 1998.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
38C3 GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
980602
(1/1)
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