M38C31M4AXXXFP [RENESAS]
8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES; 8位单片机系列740 / 38000系列
| 型号： | M38C31M4AXXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES |
| 文件： | 总224页 (文件大小：1865K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no ces whatsoever have been
made to the contents of the document, and these changes do not cony alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business opof high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
38C3
Group
User’s M
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
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or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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infringement of any third-party’s rights, originating in thof any product
data, diagrams, charts or circuit application examples conthese materials.
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and charts, represent information on products e of publication of these
materials, and are subject to change by MitElectric Corporation without
notice due to product improvements or oths. It is therefore recommended
that customers contact Mitsubishi Electration or an authorized Mitsubishi
Semiconductor product distributor latest product information before
purchasing a product listed here
● Mitsubishi Electric Corporationductors are not designed or manufactured
for use in a device or syt is used under circumstances in which human
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REVISION DESCRIPTION LIST
38C3 Group User’s Manual
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
990412
(1/1)
Preface
This user’s manual describes Mitsubishi’s CMOS 8-
bit microcomputers 38C3 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 38C3 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with applin examples.
For details of srefer to the “740 Family
Software Man
For details ment support tools, refer to the
“DEVELT SUPPORT TOOLS FOR
MICRTERS” data book.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes a list of registers, and necessary information fsystems development using
the microcomputer, the mask ROM confirmation (for mask ROM versioprogramming confirmation,
and the mark specifications which are to be submitted when or
2. Structure of Register
The figure of each register structure describes its functions, at reset, and attributes as follows:
(Note 2)
Bit attributes
Bits
(Note 1)
Cmediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode PUM) [Address : 3B 16
]
At reset
b
Name
Functions
R W
b1 b0
0 0 : Single-chip mode
0 1 :
sor mode bits
0
0
0
Not available
1 0 :
1 1 :
0 : 0 page
1 : 1 page
Stack page selection bit
3
4
5
✕
✕
0
0
0
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.”
b7 b6
0 0 : φ = XIN/2 (High-speed mode)
0 1 : φ = XIN/8 (Middle-speed mode)
1 0 : φ = XIN/8 (Middle-speed mode)
1 1 : φ = XIN (Double-speed mode)
Main clock division ratio selection
bits
1
0
6
7
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Notes 1: Contents immediately after reset release
0••••••“0” at reset release
1••••••“1” at reset release
Undefined••••••Undefined or reset release
✻
••••••Contents determined by option at reset release
2: Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
W••••••Write
••••••Read enabled
✕••••••Read disabled
••••••Write enabled
✕ ••••••Write disabled
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES.................................................................................................................................... 1-2
APPLICATION ................................................................................................................................ 1-2
PIN CONFIGURATION .................................................................................................................. 1-2
FUNCTIONAL BLOCK .................................................................................................................. 1-3
PIN DESCRIPTION ........................................................................................................................ 1-4
PART NUMBERING ....................................................................................................................... 1-6
GROUP EXPANSION .................................................................................................................... 1-7
Memory Type ............................................................................................................................ 1-7
Memory Size ............................................................................................................................. 1-7
Package ................................................................................................................................ 1-7
FUNCTIONAL DESCRIPTION ........................................................................................ 1-8
Central Processing Unit (CPU) .............................................................................. 1-8
Memory .................................................................................................................... 1-12
I/O Ports .................................................................................................................. 1-14
Interrupts .................................................................................................................1-19
Timers ...................................................................................................................... 1-23
Serial I/O .................................................................................................................1-28
A-D Converter ......................................................................................................... 1-30
LCD Drive control circuit ....................................................................................... 1-31
φ Clock Output Function ....................................................................................... 1-37
ROM Correction Function (Mversion only)........................................................ 1-38
Reset Circuit ...........................................................................................................1-39
Clock Generating Circui.......................................................................................... 1-41
NOTES ON PROGRAM.............................................................................................. 1-44
NOTES ON USE ..........................................................................................................1-44
DATA REQUIRED SK ORDERS ................................................................................ 1-45
DATA REQUIREROM WRITING ORDERS................................................................. 1-45
ROM PROGRMETHOD .............................................................................................. 1-45
FUNCTIONACRIPTION SUPPLEMENT ......................................................................... 1-46
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map ................................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-3
2.1.3 Terminate unused pins .................................................................................................. 2-7
2.1.4 Notes on I/O port ........................................................................................................... 2-8
2.1.5 Termination of unused pins .......................................................................................... 2-9
2.2 Timer.......................................................................................................................................2-10
2.2.1 Memory map ................................................................................................................. 2-10
2.2.2 Relevant registers ........................................................................................................2-11
2.2.3 Timer application examples ........................................................................................ 2-19
2.2.4 Notes on timer A (PWM mode and IGBT output mode) ...................................... 2-31
2.3 Serial I/O ................................................................................................................................ 2-33
2.3.1 Memory map ................................................................................................................. 2-33
2.3.2 Relevant registers ........................................................................................................2-33
2.3.3 Serial I/O connection examples ................................................................................. 2-36
38C3 Group User’s Manual
1
Table of contents
2.3.4 Serial I/O’s modes ....................................................................................................... 2-38
2.3.5 Serial I/O application examples ................................................................................. 2-38
2.3.6 Notes on serial I/O ...................................................................................................... 2-51
2.4 LCD controller ...................................................................................................................... 2-52
2.4.1 Memory map ................................................................................................................. 2-52
2.4.2 Relevant registers ........................................................................................................ 2-53
2.4.3 LCD controller application examples ......................................................................... 2-54
2.4.4 Notes on LCD controller ............................................................................................. 2-58
2.5 A-D converter ....................................................................................................................... 2-59
2.5.1 Memory map ................................................................................................................. 2-59
2.5.2 Relevant registers ........................................................................................................ 2-59
2.5.3 A-D converter application examples .......................................................................... 2-62
2.5.4 Notes on A-D converter .............................................................................................. 2-64
2.6 ROM correct function ......................................................................................................... 2-65
2.6.1 Memory map ................................................................................................................. 2-65
2.6.2 Relevant registers ...................................................................................................... 2-66
2.6.3 ROM correct function application examples ................................................. 2-67
2.7 Reset circuit ......................................................................................................... 2-69
2.7.1 Connection example of reset IC ................................................................ 2-69
2.7.2 Notes on reset circuit .................................................................................. 2-70
2.8 Clock generating circuit .................................................................................... 2-71
2.8.1 Relevant register .......................................................................................... 2-71
2.8.2 Clock generating circuit application s ......................................................... 2-72
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ...................................................................................... 3-2
3.1.1 Absolute maximum rati................................................................................... 3-2
3.1.2 Recommended operditions............................................................................ 3-2
3.1.3 Electrical charact............................................................................................. 3-5
3.1.4 A-D converter istics ....................................................................................... 3-7
3.1.5 Timing requand switching characteristics ................................................... 3-8
3.1.6 Absolute ratings (M version)..................................................................... 3-10
3.1.7 Recomoperating conditions (M version)..................................................... 3-10
3.1.8 Elearacteristics (M version)......................................................................... 3-14
3.1.9 A-D rter characteristics (M version) ................................................................ 3-16
3.1.10 Timinrequirements and switching characteristics (M version).......................... 3-17
3.2 Standard characteristics .................................................................................................... 3-20
3.2.1 Power source current standard characteristics ........................................................ 3-20
3.2.2 Port standard characteristics ...................................................................................... 3-21
3.3 Notes on use ........................................................................................................................ 3-26
3.3.1 Notes on interrupts ...................................................................................................... 3-26
3.3.2 Notes on timer A (PWM mode and IGBT output mode) ...................................... 3-27
3.3.3 Notes on serial I/O ...................................................................................................... 3-29
3.3.4 Notes on LCD controller ............................................................................................. 3-29
3.3.5 Notes on A-D converter .............................................................................................. 3-30
3.3.6 Notes on reset circuit .................................................................................................. 3-30
3.4 Countermeasures against noise ...................................................................................... 3-31
3.4.1 Shortest wiring length .................................................................................................. 3-31
3.4.2 Connection of bypass capacitor across VSS line and VCC line............................... 3-33
3.4.3 Wiring to analog input pins ........................................................................................ 3-34
3.4.4 Oscillator concerns....................................................................................................... 3-34
3.4.5 Setup for I/O ports....................................................................................................... 3-36
38C3 Group User’s Manual
2
Table of contents
3.4.6 Providing of watchdog timer function by software .................................................. 3-37
3.5 Control registers..................................................................................................................3-38
3.6 Mask ROM confirmation form........................................................................................... 3-58
3.7 ROM programming confirmation form............................................................................ 3-62
3.8 Mark specification form .....................................................................................................3-66
3.9 Package outline ................................................................................................................... 3-67
3.10 Machine instructions ........................................................................................................3-68
3.11 List of instruction code ...................................................................................................3-79
3.12 SFR memory map..............................................................................................................3-80
3.13 Pin configuration ...............................................................................................................3-81
38C3 Group User’s Manual
3
List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. 1 M38C34M6AXXXFP pin configuration.............................................................................. 1-2
Fig. 2 Functional block diagram................................................................................................... 1-3
Fig. 3 Part numbering.................................................................................................................... 1-6
Fig. 4 Memory expansion plan ..................................................................................................... 1-7
Fig. 5 740 Family CPU register structure................................................................................... 1-8
Fig. 6 Register push and pop at interrupt generation and subroutine call ........................... 1-9
Fig. 7 Structure of CPU mode register ..................................................................................... 1-11
Fig. 8 Memory map diagram ...................................................................................................... 1-12
Fig. 9 Memory map of special function register (SFR) .......................................................... 1-13
Fig. 10 Structure of PULL register A and PULL register B................................................... 1-14
Fig. 11 Structure of port P8 output selection register ....................................................... 1-14
Fig. 12 Port block diagram (1) .................................................................................... 1-16
Fig. 13 Port block diagram (2) ................................................................................... 1-17
Fig. 14 Port block diagram (3) .................................................................................... 1-18
Fig. 15 Interrupt control............................................................................................... 1-21
Fig. 16 Structure of interrupt-related registers......................................................... 1-21
Fig. 17 Connection example when using key irrupt and port P8 block diagram 1-22
Fig. 18 Structure of timer related register ................................................................ 1-23
Fig. 19 Block diagram of timer .................................................................................. 1-24
Fig. 20 Timing chart of timer 6 PWM ....................................................................... 1-25
Fig. 21 Block diagram of timer A .............................................................................. 1-26
Fig. 22 Structure of timer A relaers .......................................................................... 1-26
Fig. 23 Timing chart of timer IGBT output modes .................................................. 1-27
Fig. 24 Block diagram of s.......................................................................................... 1-28
Fig. 25 Structure of seritrol register......................................................................... 1-29
Fig. 26 Serial I/O timiSB first) .................................................................................... 1-29
Fig. 27 Structure ontrol register .................................................................................. 1-30
Fig. 28 Black diA-D converter ................................................................................... 1-30
Fig. 29 StructD related registers ............................................................................... 1-31
Fig. 30 Blocm of LCD controller/driver ....................................................................... 1-32
Fig. 31 Examplof circuit at each bias.................................................................................... 1-33
Fig. 32 LCD display RAM map .................................................................................................. 1-34
Fig. 33 LCD drive waveform (1/2 bias) .................................................................................... 1-35
Fig. 34 LCD drive waveform (1/3 bias) .................................................................................... 1-36
Fig. 35 Structure of φ output control register .......................................................................... 1-37
Fig. 36 Structure of ROM correct address register................................................................. 1-38
Fig. 37 Structure of ROM correct data .................................................................................... 1-38
Fig. 38 Structure of ROM correct enable register 1 ............................................................... 1-38
Fig. 39 Reset circuit example .................................................................................................... 1-39
Fig. 40 Reset sequence .............................................................................................................. 1-39
Fig. 41 Internal status at reset .................................................................................................. 1-40
Fig. 42 Ceramic resonator circuit .............................................................................................. 1-41
Fig. 43 External clock input circuit ............................................................................................ 1-41
Fig. 44 Clock generating circuit block diagram ....................................................................... 1-42
Fig. 45 State transitions of system clock ................................................................................. 1-43
Fig. 46 Programming and testing of One Time PROM version ............................................ 1-45
Fig. 47 Timing chart after interrupt occurs............................................................................... 1-47
38C3 Group User’s Manual
4
List of figures
Fig. 48 Time up to execution of interrupt processing routine ............................................... 1-47
Fig. 49 A-D conversion equivalent circuit................................................................................. 1-49
Fig. 50 A-D conversion timing chart.......................................................................................... 1-49
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of I/O port relevant registers .............................................................. 2-2
Fig. 2.1.2 Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 6, 8) ........................................................ 2-3
Fig. 2.1.3 Structure of port P7 ..................................................................................................... 2-3
Fig. 2.1.4 Structure of Port P0 direction register and port P1 direction register ................. 2-4
Fig. 2.1.5 Structure of Port Pi direction register (i = 2, 4, 5, 6, 8) ....................................... 2-4
Fig. 2.1.6 Structure of Port P7 direction register ...................................................................... 2-5
Fig. 2.1.7 Structure of PULL register A ...................................................................................... 2-5
Fig. 2.1.8 Structure of PULL register B ...................................................................................... 2-6
Fig. 2.1.9 Structure of Port P8 output selection register ......................................................... 2-6
Fig. 2.2.1 Memory map of registers relevant to timers .......................................................... 2-10
Fig. 2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6) ................................................................ 2-11
Fig. 2.2.3 Structure of Timer 2 ..................................................................................2-11
Fig. 2.2.4 Structure of Timer 6 PWM register ......................................................... 2-12
Fig. 2.2.5 Structure of Timer 12 mode register ....................................................... 2-12
Fig. 2.2.6 Structure of Timer 34 mode register ....................................................... 2-13
Fig. 2.2.7 Structure of Timer 56 mode register ....................................................... 2-13
Fig. 2.2.8 Structure of Timer A register (low-oh-order) ........................................... 2-14
Fig. 2.2.9 Structure of Compare register (lhigh-order).......................................... 2-14
Fig. 2.2.10 Structure of Timer A mode r................................................................... 2-15
Fig. 2.2.11 Structure of Timer A conter .................................................................... 2-15
Fig. 2.2.12 Structure of Interrupt register 1 ............................................................... 2-16
Fig. 2.2.13 Structure of Interrupregister 2 ............................................................... 2-17
Fig. 2.2.14 Structure of Interrol register 1 ................................................................ 2-18
Fig. 2.2.15 Structure of Intntrol register 2 ................................................................ 2-18
Fig. 2.2.16 Timers connd setting of division ratios ................................................. 2-20
Fig. 2.2.17 Relevant setting ....................................................................................... 2-21
Fig. 2.2.18 Controre..................................................................................................... 2-22
Fig. 2.2.19 Pericuit example....................................................................................... 2-23
Fig. 2.2.20 Tnection and setting of division ratios ................................................. 2-23
Fig. 2.2.21 Rt registers setting ....................................................................................... 2-24
Fig. 2.2.22 Conol procedure..................................................................................................... 2-24
Fig. 2.2.23 Judgment method of valid/invalid of input pulses ............................................... 2-25
Fig. 2.2.24 Relevant registers setting ....................................................................................... 2-26
Fig. 2.2.25 Control procedure..................................................................................................... 2-27
Fig. 2.2.26 Timers connection and setting of division ratios ................................................. 2-28
Fig. 2.2.27 Relevant registers setting ....................................................................................... 2-29
Fig. 2.2.28 Control procedure..................................................................................................... 2-30
Fig. 2.2.29 PWM output and IGBT output (1) ......................................................................... 2-31
Fig. 2.2.30 PWM output and IGBT output (2) ......................................................................... 2-31
Fig. 2.2.31 PWM output and IGBT output (3) ......................................................................... 2-32
Fig. 2.3.1 Memory map of registers relevant to Serial I/O .................................................... 2-33
Fig. 2.3.2 Structure of Serial I/O control register 1 ................................................................ 2-33
Fig. 2.3.3 Structure of Serial I/O control register 2 ................................................................ 2-34
Fig. 2.3.4 Structure of Interrupt request register 1 ................................................................. 2-34
Fig. 2.3.5 Structure of Interrupt control register 1 .................................................................. 2-35
Fig. 2.3.6 Serial I/O connection examples (1) ......................................................................... 2-36
Fig. 2.3.7 Serial I/O connection examples (2) ......................................................................... 2-37
38C3 Group User’s Manual
5
List of figures
Fig. 2.3.8 Serial I/O’s modes ..................................................................................................... 2-38
Fig. 2.3.9 Connection diagram ................................................................................................... 2-38
Fig. 2.3.10 Timing chart .............................................................................................................. 2-39
Fig. 2.3.11 Registers setting relevant to transmission side ................................................... 2-40
Fig. 2.3.12 Registers setting relevant to reception side......................................................... 2-41
Fig. 2.3.13 Control procedure of transmission side ................................................................ 2-41
Fig. 2.3.14 Control procedure of reception side ...................................................................... 2-42
Fig. 2.3.15 Connection diagram ................................................................................................. 2-43
Fig. 2.3.16 Timing chart .............................................................................................................. 2-43
Fig. 2.3.17 Relevant registers setting ....................................................................................... 2-44
Fig. 2.3.18 Setting of transmission data ................................................................................... 2-44
Fig. 2.3.19 Control procedure..................................................................................................... 2-45
Fig. 2.3.20 Connection diagram ................................................................................................. 2-46
Fig. 2.3.21 Timing chart .............................................................................................................. 2-47
Fig. 2.3.22 Relevant registers setting in master unit .............................................................. 2-48
Fig. 2.3.23 Relevant registers setting in slave unit ............................................................ 2-48
Fig. 2.3.24 Control procedure of master unit............................................................. 2-49
Fig. 2.3.25 Control procedure of slave unit ............................................................. 2-50
Fig. 2.4.1 Memory map of registers relevant to LCD co........................................ 2-52
Fig. 2.4.2 Structure of Segment output enable regist............................................ 2-53
Fig. 2.4.3 Structure of LCD mode register ............................................................... 2-53
Fig. 2.4.4 LCD panel ................................................................................................... 2-54
Fig. 2.4.5 Segment allocation example ..................................................................... 2-54
Fig. 2.4.6 LCD display RAM map .............................................................................. 2-55
Fig. 2.4.7 LCD display RAM setting .......................................................................... 2-55
Fig. 2.4.8 Relevant registers setting ......................................................................... 2-56
Fig. 2.4.9 Control procedure....................................................................................... 2-57
Fig. 2.5.1 Memory map of A-D relevant registers ................................................. 2-59
Fig. 2.5.2 Structure of A-D cister.............................................................................. 2-59
Fig. 2.5.3 Structure of A-D ion register (low-order)................................................... 2-60
Fig. 2.5.4 Structure of ersion register (high-order) ................................................. 2-60
Fig. 2.5.5 Structure pt request register 2 ................................................................. 2-61
Fig. 2.5.6 Structurrrupt control register 2 .................................................................. 2-61
Fig. 2.5.7 Connagram ................................................................................................... 2-62
Fig. 2.5.8 Settelevant registers ..................................................................................... 2-62
Fig. 2.5.9 Controprocedure....................................................................................................... 2-63
Fig. 2.6.1 Memory map of ROM correct function relevant registers .................................... 2-65
Fig. 2.6.2 Structure of ROM correct enable register 1........................................................... 2-66
Fig. 2.6.3 Connection diagram ................................................................................................... 2-67
Fig. 2.6.4 Setting of relevant registers ..................................................................................... 2-67
Fig. 2.6.5 Control procedure....................................................................................................... 2-68
Fig. 2.7.1 Example of power-on reset circuit ........................................................................... 2-69
Fig. 2.7.2 RAM backup system example .................................................................................. 2-69
Fig. 2.8.1 Structure of CPU mode register .............................................................................. 2-71
Fig. 2.8.2 Connection diagram ................................................................................................... 2-72
Fig. 2.8.3 Status transition diagram during power failure ...................................................... 2-73
Fig. 2.8.4 Setting of relevant registers ..................................................................................... 2-74
Fig. 2.8.5 Control procedure....................................................................................................... 2-75
Fig. 2.8.6 Structure of clock counter......................................................................................... 2-76
Fig. 2.8.7 Initial setting of relevant registers ........................................................................... 2-77
Fig. 2.8.8 Setting of relevant registers after detecting power failure ................................... 2-78
Fig. 2.8.9 Control procedure....................................................................................................... 2-79
38C3 Group User’s Manual
6
List of figures
CHAPTER 3 APPENDIX
Fig. 3.1.1 Circuit for measuring output switching characteristics .......................................... 3-18
Fig. 3.1.2 Timing chart ................................................................................................................3-19
Fig. 3.2.1 Power source current standard characteristics ...................................................... 3-20
Fig. 3.2.2 Power source current standard characteristics (in wait mode) ........................... 3-20
Fig. 3.2.3 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (25 °C).... 3-21
Fig. 3.2.4 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (90 °C).... 3-21
Fig. 3.2.5 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (25 °C).... 3-22
Fig. 3.2.6 CMOS output port (P0, P1, P2, P3) N-channel side characteristics (90 °C) ... 3-22
Fig. 3.2.7 CMOS output port (P4, P5
(25 °C) ..........................................................................................................................3-23
Fig. 3.2.8 CMOS output port (P4, P5 , P5 –P5 , P6, P7 , P7 , P8) P-channel side characteristics
(90 °C) ..........................................................................................................................3-23
Fig. 3.2.9 CMOS output port (P4, P5 –P5 , P6, P7 , P7 ) N-channel side characteristics (25 °C)
........................................................................................................................................................ 3-24
Fig. 3.2.10 CMOS output port (P4, P5 –P5 , P6, P7 , P7 ) Nnel side characteristics
(90 °C)....................................................................................................... 3-24
0
, P5
2
–P5
7
, P6, P7
0
, P7
1
, P8) P-channel side characteristics
0
2
7
0
1
2
7
0
1
2
7
0
1
Fig. 3.2.11 CMOS output port (P5
Fig. 3.2.12 CMOS output port (P5
0
, P8) N-channel side ristics (25 °C) ............... 3-25
, P8) N-channel scteristics (90 °C) ............... 3-25
0
Fig. 3.3.1 Sequence of switch detection edge.......................................................... 3-26
Fig. 3.3.2 Sequence of check of interrupt reque...................................................... 3-26
Fig. 3.3.3 Structure of interrupt control regis........................................................... 3-27
Fig. 3.3.4 PWM output and IGBT output (................................................................ 3-27
Fig. 3.3.5 PWM output and IGBT outpu.................................................................... 3-28
Fig. 3.3.6 PWM output and IGBT ou......................................................................... 3-28
Fig. 3.4.1 Selection of packages ............................................................................... 3-31
Fig. 3.4.2 Wiring for the RESE.................................................................................. 3-31
Fig. 3.4.3 Wiring for clock I/....................................................................................... 3-32
Fig. 3.4.4 Wiring for the the One Time PROM and the EPROM version ......... 3-33
Fig. 3.4.5 Bypass capass the VSS line and the VCC line ........................................ 3-33
Fig. 3.4.6 Analog siand a resistor and a capacitor ................................................ 3-34
Fig. 3.4.7 Wiring e current signal line ...................................................................... 3-34
Fig. 3.4.8 Wirinal lines where potential levels change frequently ......................... 3-35
Fig. 3.4.9 Von the underside of an oscillator ........................................................ 3-35
Fig. 3.4.10 Seor I/O ports................................................................................................... 3-36
Fig. 3.4.11 Watchdog timer by software ................................................................................... 3-37
Fig. 3.5.1 Structure of Port Pi .................................................................................................... 3-38
Fig. 3.5.2 Structure of Port P0 direction register and Port P1 direction register ............... 3-38
Fig. 3.5.3 Structure of Port Pi direction register ..................................................................... 3-39
Fig. 3.5.4 Structure of Port P7................................................................................................... 3-39
Fig. 3.5.5 Structure of Port P7 direction register .................................................................... 3-40
Fig. 3.5.6 Structure of PULL register A .................................................................................... 3-40
Fig. 3.5.7 Structure of PULL register B .................................................................................... 3-41
Fig. 3.5.8 Structure of Port P8 output selection register ....................................................... 3-42
Fig. 3.5.9 Structure of Serial I/O control register 1 ................................................................ 3-43
Fig. 3.5.10 Structure of Serial I/O control register 2 .............................................................. 3-44
Fig. 3.5.11 Structure of Serial I/O register............................................................................... 3-44
Fig. 3.5.12 Structure of Timer i ................................................................................................. 3-45
Fig. 3.5.13 Structure of Timer 2 ................................................................................................ 3-45
Fig. 3.5.14 Structure of Timer 6 PWM register ....................................................................... 3-46
Fig. 3.5.15 Structure of Timer 12 mode register ..................................................................... 3-46
38C3 Group User’s Manual
7
List of figures
Fig. 3.5.16 Structure of Timer 34 mode register ..................................................................... 3-47
Fig. 3.5.17 Structure of Timer 56 mode register ..................................................................... 3-47
Fig. 3.5.18 Structure of φ output control register .................................................................... 3-48
Fig. 3.5.19 Structure of Timer A register (low-order, high-order) ......................................... 3-48
Fig. 3.5.20 Structure of Compare register (low-order, high-order)........................................ 3-49
Fig. 3.5.21 Structure of Timer A mode register ...................................................................... 3-49
Fig. 3.5.22 Structure of Timer A control register .................................................................... 3-50
Fig. 3.5.23 Structure of A-D control register............................................................................ 3-50
Fig. 3.5.24 Structure of A-D conversion register (low-order)................................................. 3-51
Fig. 3.5.25 Structure of A-D conversion register (high-order) ............................................... 3-51
Fig. 3.5.26 Structure of Segment output enable register ....................................................... 3-52
Fig. 3.5.27 Structure of LCD mode register ............................................................................. 3-52
Fig. 3.5.28 Structure of Interrupt edge selection register ...................................................... 3-53
Fig. 3.5.29 Structure of CPU mode register ............................................................................ 3-53
Fig. 3.5.30 Structure of Interrupt reqeust register 1 ............................................................... 3-54
Fig. 3.5.31 Structure of Interrupt request register 2 ............................................................. 3-55
Fig. 3.5.32 Structure of Interrupt control register 1 ..................................................... 3-56
Fig. 3.5.33 Structure of Interrupt control register 2 ................................................ 3-56
Fig. 3.5.34 Structure of ROM correct enable register 1......................................... 3-57
38C3 Group User’s Manual
8
List of tables
List of tables
CHAPTER 1 HARDWARE
Table 1 Pin description (1) ........................................................................................................... 1-4
Table 2 Pin description (2) ........................................................................................................... 1-5
Table 3 Support products ............................................................................................................. 1-7
Table 4 Push and pop instructions of accumulator or processor status register ................. 1-9
Table 5 Set and clear instructions of each bit of processor status register ....................... 1-10
Table 6 List of I/O port function (1) .......................................................................................... 1-14
Table 7 List of I/O port function (2) .......................................................................................... 1-15
Table 8 Interrupt vector addresses and priority ...................................................................... 1-20
Table 9 Function of P4
6
/SCLK1 and P4 /SCLK2 ..................................................................................................................................... 1-28
0
Table 10 Maximum number of display pixels at each duty ratio .......................................... 1-31
Table 11 Bias control and applied voltage to Vl1–VL3 ............................................................................................. 1-33
Table 12 Duty ratio control and common pins used................................................ 1-33
Table 13 Programming adapter..................................................................................1-45
Table 14 Interrupt sources, vector addresses and interity..................................... 1-46
Table 15 Relative formula for a reference voltage D converter and Vref ..................... 1-48
Table 16 Change of A-D conversion register duronversion .................................. 1-48
CHAPTER 2 APPLICATION
Table 2.1.1 Termination of unused pins ....................................................................... 2-7
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maxigs ....................................................................................... 3-2
Table 3.1.2 Recommenting conditions ....................................................................... 3-2
Table 3.1.3 Recommerating conditions ....................................................................... 3-3
Table 3.1.4 Recomoperating conditions ....................................................................... 3-4
Table 3.1.5 Elearacteristics ........................................................................................... 3-5
Table 3.1.6 Echaracteristics ........................................................................................... 3-6
Table 3.1.7 Anverter characteristics .................................................................................. 3-7
Table 3.1.8 Timng requirements 1.............................................................................................. 3-8
Table 3.1.9 Timing requirements 2.............................................................................................. 3-8
Table 3.1.10 Switching characteristics 1 .................................................................................... 3-9
Table 3.1.11 Switching characteristics 2 .................................................................................... 3-9
Table 3.1.12 Absolute maximum ratings (M version) ............................................................. 3-10
Table 3.1.13 Recommended operating conditions (M version) ............................................. 3-10
Table 3.1.14 Recommended operating conditions (M version) ............................................. 3-11
Table 3.1.15 Recommended operating conditions (M version) ............................................. 3-11
Table 3.1.16 Recommended operating conditions (M version) ............................................. 3-12
Table 3.1.17 Recommended operating conditions (M version) ............................................. 3-13
Table 3.1.18 Electrical characteristics (M version).................................................................. 3-14
Table 3.1.19 Electrical characteristics (M version).................................................................. 3-15
Table 3.1.20 A-D converter characteristics (M version) ......................................................... 3-16
Table 3.1.21 Timing requirements 1 (M version) .................................................................... 3-17
Table 3.1.22 Timing requirements 2 (M version) .................................................................... 3-17
Table 3.1.23 Switching characteristics 1 (M version) ............................................................. 3-18
Table 3.1.24 Switching characteristics 2 (M version) ............................................................. 3-18
38C3 Group User’s Manual
9
CHAPTER 1
HARDWARE
DTION
RES
LICATION
IN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USE
DATA REQUIRED FOR MASK
ORDERS
DATA REQUIRED FOR ROM WRITING
ORDERS
ROM PROGRAMMING METHOD
F U N C T I O N A L D E S C R I P T I O N
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
●LCD drive control circuit
The 38C3 group is the 8-bit microcomputer based on the 740 family
Bias ............................................................................ 1/1, 1/2, 1/3
Duty .................................................................... 1/1, 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 32
●2 Clock generating circuit
core technology.
The 38C3 group has a LCD drive control circuit, a 10-channel A-D
converter, and a Serial I/O as additional functions.
The various microcomputers in the 38C3 group include variations of
internal memory size and packaging. For details, refer to the section
on part numbering.
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
For details on availability of microcomputers in the 38C3 group, refer
to the section on group expansion.
In high-speed mode .................................................... 4.0 to 5.5 V
In middle-speed mode ................................................ 2.5 to 5.5 V
(M version is 2.2✽ to 5.5 V)
FEATURES
In low-speed mode ..................................................... 2.5 to 5.5 V
(M version is 2.2✽ to 5.5 V)
●Basic machine-language instructions ....................................... 71
●The minimum instruction execution time ............................. 0.5 µs
(at 8MHz oscillation frequency)
●Power dissipation
In high-speed mode ........................................................... 32 mW
(at 8 MHz oscillation frequency)
●Memory size
ROM ..................................................................4 K to 48 K bytes
RAM ................................................................. 192 to 1024 bytes
●Programmable input/output ports ............................................. 57
●Software pull-up/pull-down resistors
In low-speed mode..............................................................45 µW
(at 32 kHz oscillation quency, at 3 V power source voltage)
●Operating temperature ................................ – 20 to 85°C
✽Mask ROM version
..................................................... (Ports P0–P8 except Port P51)
●Interrupts ................................................... 16 sources, 16 vectors
(includes key input interrupt)
APPLICAT
Camera, holiances, consumer electronics, etc.
●Timers ............................................................8-bit ✕ 6, 16-bit ✕ 1
●A-D converter ................................................. 10-bit ✕ 8 channels
●Serial I/O ....................................... 8-bit ✕ 1 (Clock-synchronized)
PIN CONFIGURATION (TOP VIEW)
P4
P4
P4
7
/SRDY
/SCLK1
/SOU
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P3
P3
P3
P3
P3
P3
P3
P3
COM
COM
COM
COM
0
1
2
3
4
5
6
7
/SEG24
/SEG25
/SEG26
/SEG27
/SEG28
/SEG29
/SEG30
/SEG31
0
1
2
3
6
5
P4
4
/
P4
P4
P4
2
/T
/T1OU
/SCLK2
1
0
M38C34M6AXXXFP
AVSS
V
REF
P6
P6
P6
P6
P6
P6
7
6
5
4
3
2
/AN
/AN
/AN
/AN
/AN
/AN
7
6
5
4
3
2
VL1
VL2
VL3
P80
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1 M38C34M6AXXXFP pin configuration
38C3 Group User’s Manual
1-2
HARDWARE
FUNCTIONAL BLOCK
K e y - o n w a k e - u p
O U T T 3 O U T T , 1
φ
2
– 0 I N T I N T
Fig. 2 Functional block diagram
38C3 Group User’s Manual
1-3
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
VREF
Power source
• Apply voltage of 2.5✽ V to 5.5 V to VCC, and 0 V to VSS.
• Reference voltage input pin for A-D converter.
Analog reference
voltage
AVSS
Analog power
source
• GND input pin for A-D converter.
• Connect to VSS.
RESET
XIN
Reset input
Clock input
• Reset input pin for active “L.”
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
XOUT
Clock output
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
VL1 – VL3
LCD power
source
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
• Input 0 – VL3 voltage to LCD.
COM0 –
COM3
Common output
• LCD common output pins.
• COM1, COM2, and COM3 are not used at 1/1 duty ratio.
• COM2 and COM3 are not used at 1/2 duty ratio.
• COM3 is not used at 1/3 duty ratio.
P00/SEG8 – I/O port P0
P07/SEG15
• 8-bit I/O port.
• CMOS compatible input level.
egment pins
• CMOS 3-state output structure.
• I/O direction register allows each port to be in
programmed as either input or output.
• Pull-down control is enabled.
P10/SEG16 – I/O port P1
P17/SEG23
P20/SEG0 – I/O port P2
P27/SEG7
P30/SEG24 – Output port P3
P37/SEG31
• 8-bit output port.
• CMOS state output.
• Pull-down control is enab
P40/SCLK2
P41/T1OUT
P42/T3OUT
P43/φ
I/O port P4
• 8-bit I/O port.
• Serial I/O function pin
• Timer output pin
• Timer output pin
• φ output pin
• CMOS compatible i
• CMOS 3-state oe.
• I/O direction rs each pin to be individually
programmeput or output.
• Pull-up cled.
P44/SIN,
• Serial I/O function pins
P45/SOUT,
P46/SCLK1,
P47/SRDY
✽ Mask ROM version of M version .5 V.
38C3 Group User’s Manual
1-4
HARDWARE
PIN DESCRIPTION
Table 2 Pin description (2)
Pin
Name
Function
Function except a port function
P51
Input port P5
• 1-bit input pin.
• CMOS compatible input level.
P50/TAOUT
P52/PWM1
I/O port P5
• 7-bit I/O port.
• Timer A output pin
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
• PWM1 output (timer output) pin
• External count I/O pins
P53/CNTR0,
P54/CNTR1
P55/INT0,
P56/INT1,
P57/INT2
• External interrupt input pins
• A-D conversion input pins
P60/AN0 –
P67/AN7
I/O port P6
I/O port P7
I/O port P8
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
P70/XCIN,
P71/XCOUT
• 2-bit I/O port.
• Su-clock generating circuit I/O pins
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
P80 – P87
• 8-bit I/O port.
• TTL input level.
Key input (Key-on wake-up) interrupt
input pins
• CMOS 3-state output structure.
• I/O direction register allows each pin to y
programmed as either input or output.
• Pull-up control is enabled.
38C3 Group User’s Manual
1-5
HARDWARE
PART NUMBERING
PART NUMBERING
Product
M38C3
4
M
6
A
XXX FP
Package type
: 80P6N-A package
: 80D0 package
FP
FS
ROM number
Omitted in One Time PROM
version shipped in blank and
EPROM version.
A : Standard(Note)
M : M version
ROM/PROM size
1
: 4096 bytes
: 3686ytes
: 40s
:
s
9
2 : 8192 bytes
3 : 12288 bytes
4
A
B
: 16384 bytes
5 : 20480 bytes
6 : 24576 byt
7
: 28672
8 : 3276
28 bytes and the last 2 bytes of ROM
erved areas ; they cannot be used.
Memory type
M
: Mask ROM version
E
: EPROM or One Time PROM version
RAM size
0
: 192 bytes
1 : 256 bytes
2 : 384 bytes
3
: 512 bytes
4 : 640 bytes
5 : 768 bytes
6
: 896 bytes
7 : 1024 bytes
Note : Difference between standard and M version
• Standard : Port P5
0
/TAOUT pin remains set to the input mode until the direction
register is set to the output mode during reset and after
reset.
• M version : Port P50/TAOUT pin remains set to the output mode (“L” output) until
the direction register is set to the input mode during reset
and after reset.
Fig. 3 Part numbering
38C3 Group User’s Manual
1-6
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 38C3 group as follows.
Packages
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions
Memory Size
ROM/PROM size ................................................ 16 K to 48 K bytes
RAM size ............................................................. 512 to 1024 bytes
Memory Expansion Plan
ROM size (bytes)
48K
M38C37ECA/ECM
44K
40K
Under development
36K
32K
28K
24K
20K
16K
12K
8K
M38C34M8
M38C34M6A
Planning
M38C33M
4K
192 256
512
640
768
896
1024
M size (bytes)
Products under development e development schedule and specification may be revised without notice.
Planning products may be velopment.
Fig. 4 Memory expansion plan
Currently supported products are listbelow.
As of December 1998
Remarks
Table 3 Support products
(P) ROM size (bytes)
ROM size for User in ( )
RAM size
(bytes)
Product name
Package
M38C34M6AXXXFP
M38C37ECAXXXFP
M38C37ECAFP
24576 (24446)
640
1024
640
Mask ROM version
One Time PROM version
80P6N-A
80D0
49152 (49022)
24576 (24446)
49152 (49022)
One Time PROM version (blank)
EPROM version
M38C37ECAFS
M38C34M6MXXXFP
M38C37ECMXXXFP
M38C37ECMFP
Mask ROM version
80P6N-A
80D0
One Time PROM version
One Time PROM version (blank)
EPROM version
1024
M38C37ECMFS
38C3 Group User’s Manual
1-7
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
Central Processing Unit (CPU)
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the con-
tents of the stack pointer. The high-order 8 bits of the stack address
are determined by the stack page selection bit. If the stack page
selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack
page selection bit is “1”, the high-order 8 bits becomes “0116”.
The operations of pushing register contents onto the stack and pop-
ping them from the stack are shown in Figure 6.
The 38C3 group uses the standard 740 Family instruction set. Refer
to the table of 740 Family addressing modes and machine instruc-
tions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
Store registers other than those described in Figure 6 with program
when the user needs them during interrupts or subroutine calls.
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
[Program Counter (PC)]
The index register X is an 8-bit register. In the index addressing modes,
the value of the OPERAND is added to the contents of register X and
specifies the real address.
The program counter is a 16-bit counter consisting of two 8-bit regis-
ters PCH and PCL. It is used to indicate the address of the next in-
struction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b0
b0
b0
b0
b7
A
umulator
b7
Index register X
Index register Y
b7
Y
S
Stack pointer
b15
b7
b7
PCH
PC
L
Program counter
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
38C3 Group User’s Manual
1-8
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
Push return address
on stack
Push contents of processor
status register on stack
Interrupt
Service R
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTS
(S) (S) + 1
Exe
+ 1
POP return
POP contents of
processor status
register from stack
address from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
M (S)
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
POP return
address
from stack
Note: Condition for e of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
38C3 Group User’s Manual
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5 flags
which indicate the status of the processor after an arithmetic operation
and 3 flags which decide MCU operation. Branch operations can be
performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V)
flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not
valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the rsult of an arithmetic operation or data
transfer is negative. WBIT instruction is executed, bit 7 of
the memory location by the BIT instruction is stored
in the negative
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 5 Set and clear instructions of each bit of processor str
C flag
Z flag
D flag
B flag
T flag
V flag
_
N flag
_
_
_
_
_
_
Set instruction
SEC
CLC
LI
SED
CLD
SET
CLT
Clear instruction
CLV
38C3 Group User’s Manual
1-10
HARDWARE
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the
internal system clock selection bit etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : RAM in the zero page is d as stack area
1 : RAM in page 1 is used k area
Not used (returns “1” whe
(Do not write “0” to this
Port XC switch bit
0 : I/O port
1 : XCIN, XC
Main clock ( bit
0 : Ope
1 : S
Main atio selection bit
h-speed mode)
middle-speed mode)
em clock selection bit
-XOUT selected (middle-/high-speed mode)
CIN-XCOUT selected (low-speed mode)
Fig. 7 Structure of CPU mode register
38C3 Group User’s Manual
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control
registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special page
RAM is used for data storage and for stack area of subroutine calls
addressing mode.
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
000016
RAM size
(bytes)
Address
XXXX16
rea 1
0040
192
256
384
512
640
768
896
1024
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
splay RAM area
Zero page
0
corrective RAM area
(Note 1)
RAM
16
XXXX16
Reserved area
044016
Not used
0F0016
0FFF16
ROM area
SFR area 2 (Note 1)
ROM size
(bytes)
Address
YYYY16
A
YYYY16
Reserved ROM area
(128 bytes)
4096
8192
F00016
E00016
D00
C0
B00016
A00016
900016
800016
700016
600016
500016
400016
16
08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
ZZZZ16
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Note 1 : This is valid only in mask ROM version.
Fig. 8 Memory map diagram
38C3 Group User’s Manual
1-12
HARDWARE
FUNCTIONAL DESCRIPTION
Port P0 (P0)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
002016
002116
002216
002316
002416
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer 5 (T5)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
002516 Timer 6 (T6)
002616
Timer 6 PWM register (T6PWM)
002716
002816
002916
Port P4 (P4)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Port P4 direction register (P4D)
Port P5 (P5)
002A16 Timer 56 mode register (T56M)
φ output control register (CKOUT)
Port P5 direction register (P5D)
Port P6 (P6)
002B16
002C16 Timer A register (low) (TAL)
Timer A register (high) (TAH)
Port P6 direction register (P6D)
Port P7 (P7)
002D16
002E16 Compare register (low) (CONAL)
002F16 Compare register (high) (CONAH)
003016 Timer A mode register (TAM)
Port P7 direction register (P7D)
Port P8 (P8)
Timer A control register CON)
A-D control register
001116 Port P8 direction register (P8D)
003116
003216
003316
003416
003516
003616
003716
003816
003
16
03E16
003F16
001216
001316
A-D conversion ADL)
A-D conversih) (ADH)
001416
001516
001616 PULL register A (PULLA)
PULL register B (PULLB)
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P8 output selection register (P8SEL)
Serial I/O control register 1 (SIOCON1)
Serial I/O control register 2 (SIOCON2)
Serial I/O register (SIO)
ut enable register (SEG)
register (LM)
t edge selection register (INTEDGE)
U mode register (CPUM)
nterrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
ROM correct enable register 1 (Not
0F0A16
0F0B16
0F0C16
0F0D16
0F0E16
0F0116
0F0216
0F0316
ROM correct high-order address register 5 (Note)
ROM correct low-order address register 5 (Note)
ROM correct high-order address register 6 (Note)
ROM correct low-order address register 6 (Note)
ROM correct high-order address register 7 (Note)
ROM correct high-order address te)
ROM correct low-order addrNote)
0F0416 ROM correct high-order r 2 (Note)
0F0516 ROM correct low-ordster 2 (Note)
ROM correct high-register 3 (Note)
0F0F16 ROM correct low-order address register 7 (Note)
0F1016
0F0616
ROM correct loss register 3 (Note)
ROM correct high-order address register 8 (Note)
0F1116 ROM correct low-order address register 8 (Note)
0F0716
ROM correddress register 4 (Note)
ROM correct r address register 4 (Note)
0F0816
0F0916
Note: This register is valid only in mask ROM version.
Fig. 9 Memory map of special function register (SFR)
38C3 Group User’s Manual
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
I/O PORTS
b7
b0
[Direction Registers (ports P2, P4, P50, P52–P57,
and P6–P8)]
PULL register A
(PULLA : address 001616)
P00–P07 pull-down
P10–P17 pull-down
P20–P27 pull-down
Not used
The I/O ports P2, P4, P50, P52–P57, and P6–P8 have direction reg-
isters which determine the input/output direction of each individual
pin. Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
P70, P71 pull-up
P80–P87 pull-up
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
Not used (return “0” when read)
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are float-
ing. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
b7
b0
PULL register B
(PULLB : address 001716)
P40–P43 pull-up
P44–P47 pull-up
P50, P52, P53 pull-up
P54–P57 pull-up
[Direction Registers (ports P0 and P1)]
Ports P0 and P1 have direction registers which determine the input/
output direction of each individual port.
P60–P63 pull-up
4–P67 pull-up
Each port in a direction register corresponds to one port, each port
can be set to be input or output.
sed (return “0” when read)
le
able
When “0” is written to the bit 0 of a direction register, that port be-
comes an input port. When “1” is written to that port, that port be-
comes an output port. Bits 1 to 7 of ports P0 and P1 direction regis-
ters are not used.
Note: TPULL register A and PULL register B
ports programmed as the output ports.
Figre of PULL register A and PULL register B
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL register
B (address 001716), ports except for ports P3 and P51 can control
either pull-down or pull-up (pins that are shared with the segme
output pins for LCD are pull-down; all other pins are pull-up) w
program.
b7
b0
Port P8 output selection register
(P8SEL : address 001816
)
However, the contents of PULL register A and PULL re
not affect ports programmed as the output ports.
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
Port P8 Output Selection
Ports P80 to P87 can be switched to N-chanin output by
Fig. 11 Structure of port P8 output selection register
setting “1” to the port P8 output selectio
Table 6 List of I/O port functio
Pin
Name
Port P0
IOutput
I/O format
Non-port function
Related SFRs
Ref. No.
(1)
P00/SEG8 –
P07/SEG15
Input/Output,
port unit
CMOS compatible input LCD segment output PULL register A
level
Segment output enable reg-
ister
CMOS 3-state output
P10/SEG16 –
P17/SEG23
Port P1
Port P2
Port P3
Input/Output,
port unit
CMOS compatible input LCD segment output PULL register A
level
Segment output enable reg-
CMOS 3-state output
ister
P20/SEG0 –
P27/SEG7
Input/Output,
individual bits
CMOS compatible input
CMOS 3-state output
LCD segment output PULL register A
Segment output enable reg-
ister
P30/SEG24 –
P37/SEG31
Output,
individual bits
CMOS 3-state output
LCD segment output Segment output enable reg-
ister
(2)
38C3 Group User’s Manual
1-14
HARDWARE
FUNCTIONAL DESCRIPTION
Table 7 List of I/O port function (2)
Pin
Name
Port P4
Input/Output
I/O format
Non-port function
Related SFRs
Ref. No.
(3)
P40/SCLK2
Input/Output,
individual bits
CMOS compatible input Serial I/O function I/O Serial I/O control registers
level
1, 2
CMOS 3-state output
PULL register B
P41/T1OUT
P42/T3OUT
P43/φ
Timer output
Timer output
φ clock output
Timer 12 mode register
PULL register B
(4)
(4)
(5)
Timer 34 mode register
PULL register B
φ output control register
PULL register B
P44/SIN
Serial I/O function I/O Serial I/O control registers
(6)
(7)
P45/SOUT
P46/SCLK1
P47/SRDY
1, 2
PULL register B
(8)
(9)
P50/TAOUT
Port P5
Input/Output,
individual bits
CMOS compatible input Timer A output
level
CMOS 3-state output
Timer A mode register
Timer A control register
PULL register B
(10)
P51
Input
CMOS compatible input
level
(11)
(4)
P52/PWM1
Input/Output,
individual bits
CMOS compatible input PWM output
level
r 56 mode register
ULL register B
CMOS 3-state output
P53/CNTR0
P54/CNTR1
Extern
Interrupt edge selection reg-
ister
PULL register B
(12)
(12)
(13)
P55/INT0
P56/INT1
P57/INT2
errupt in- Interrupt edge selection reg-
ister
PULL register B
P60/AN0
–
P67/AN7
Port P6
Port P7
Port P8
Common
Input/Output,
individual bits
CMOS compatiblconverter input
A-D control register
PULL register B
level
CMOS 3-stat
Input/Output,
individual bits
CMOS cout Sub-clock generating CPU mode register
P70/XCIN
(14)
level
circuit I/O
PULL register A
P71/XCOUT
P80 – P87
(15)
(17)
CMOtput
Input/Output,
individual bits
Ctible input Key input (key-on Interrupt control register 2
wake-up) interrupt in- PULL register A
put
state output
COM
0
– COM
3
Output
ommon output
LCD mode register
(16)
Notes 1: Make sure that the input level at each V or VCC during execution of the STP instruction.
When an input level is at an intermal, a current will flow from VCC to VSS through the input-stage gate.
2: For details of how to use doublas function I/O ports, refer to the applicable sections.
38C3 Group User’s Manual
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
(1)Ports P0, P1, P2
(2)Port P3
V
V
L2/VL3
L1/VSS
V
V
L2/VL3
L1/VSS
Segment output enable bit
(Note)
Segment output enable bit
Port latch
Direction register
Data bus
Port latch
Data bus
Pull-down control
Segmetput enable bit
Pull-down control
Segment output enable bit
Note : Port P0, P1 direction registers are only bit 0.
(3)Port P4
0
(4)Ports P41,
Pull-up control
P-channel output disable bit
Pull-up control
Timction bit
Telection bit
t selection bit
Serial I/O mode selection bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Timer 1 output
Timer 3 output
Timer 6 output
Serial I/O clock output
(6)Port P4
4
(5)Port P4
3
Pull-up control
Pull-up control
Direction register
Port latch
Direction register
Port latch
Data bus
Data bus
φ output control bit
Serial I/O input
φ
Fig. 12 Port block diagram (1)
38C3 Group User’s Manual
1-16
HARDWARE
FUNCTIONAL DESCRIPTION
(8)Port P46
(7)Port P45
Pull-up control
P-channel output disable bit
Pull-up control
P-channel output disable bit
Serial I/O port selection bit
Direction register
Serial I/O mode selection bit
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O output
Serial I/O clock output
Serial I/O clock input
(9)Port P47
(10)Port P50
Pull-up control
Pull-up control
SRDY output enable bit
Timer A it
Direction register
er
Data bus
Port latch
Data
ort latch
Serial I/O ready output
Timer A output
(12)Ports P53–P57
(11)Port P51
Pull-up control
Data b
Direction register
Port latch
Data bus
INT0–INT2 interrupt input
CNTR0,CNTR1 interrupt input
Note: The initial value of M version becomes “1” (output).
Fig. 13 Port block diagram (2)
38C3 Group User’s Manual
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
(14)Port P7
0
(13)Port P6
Port selection • pull-up control
Pull-up control
Port Xc switch bit
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
(15)Port P7
Data bus
A-D conversion input
Analog input pin selection bit
Sub-clock generating circuit input
1
(16)COM0–COM3
Port selection • pull-up control
Port Xc switch bit
V
Direction register
The gate input signal of each
Port latch
transistor is controlled by the
LCD duty ratio and the bias
value.
Por
switch bit
(17)Port P8
Pull-up control
P-channel output disable b
Direction register
Data bus
Port latch
Key input (key-on wake-up) interrupt input
Fig. 14 Port block diagram (3)
38C3 Group User’s Manual
1-18
HARDWARE
FUNCTIONAL DESCRIPTION
INTERRUPTS
Interrupts occur by sixteen sources: six external, nine internal, and
one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0”.
Interrupt enable bits can be set or cleared by software. Interrupt re-
quest bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit.The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. The interrupt jump destination address is read from the vector
table into the program counter.
■Notes on Interrupts
When the active edge of an external interrupt (INT0 – INT2, C
or CNTR1) is set or an vector interrupt source where several
source is assigned to the same vector address is switch
responding interrupt request bit may also be set. Thel-
lowing sequence:
(1) Disable the interrupt.
(2) Change the active edge in interrupt on register.
(3) Clear the set interrupt request bi
(4) Enable the interrupt.
38C3 Group User’s Manual
1-19
HARDWARE
FUNCTIONAL DESCRIPTION
Table 8 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Interrupt Source Priority
Remarks
High
Low
Reset (Note 2)
1
2
FFFD16
FFFB16
FFFC16
FFFA16
At reset
Non-maskable
INT0
At detection of either rising or falling edge of External interrupt
INT0 input
(active edge selectable)
INT1
3
4
5
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
At detection of either rising or falling edge of External interrupt
INT1 input
(active edge selectable)
INT2
At detection of either rising or falling edge of External interrupt
INT2 input
(active edge selectable)
Serial I/O
At completion of serial I/O data transmit/re- Valid when serial I/O is selected
ceive
Timer A
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
CNTR0
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
At timer A underflow
At timer 1 underflow
8
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
STP release timer underflow
9
10
11
12
13
At detection of either rising or falling eernal interrupt
CNTR0 input
active edge selectable)
CNTR1
14
15
16
17
FFE316
FFE116
FFDF16
FFDD16
FFE216
FFE016
FFDE16
FFDC16
At detection of either rising or faExternal interrupt
CNTR1 input
(active edge selectable)
Key input (Key-
on wake-up)
At falling of port P8 (at inpulevel External interrupt
AND
(falling valid)
A-D conversion
At completion of A-D
Valid when A-D conversion interrupt
is selected
BRK instruction
At BRK instrucn
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest p
38C3 Group User’s Manual
1-20
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 15 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
0
1
2
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (return “0” when read)
CNTR
CNTR
0
active edge switch bit
active edge switch bit
0 : Falling edge active, nt
1 : Rising edge activount
1
b7
b0
b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
(IREQ1 : address 003C16
)
)
INT
INT
INT
0
1
2
interrupt request bit
interrupt request bit
interrupt request bit
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
Serial I/O interrupt req
Timer A interrupt re
Timer 1 interrup
Timer 2 interr
Timer 3 inbit
CNTR
CNTR
0
interrupt request bit
interrupt request bit
1
Key input interrupt request bit
AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Intecontrol register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
INT
INT
INT
0
1
2
interrupt enable bit
interrupt enable bit
interrupt enable bit
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
Serial I/O interrupt enable bit
Timer A interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
CNTR
CNTR
0
interrupt enable bit
interrupt enable bit
1
Key input interrupt enable bit
AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers
38C3 Group User’s Manual
1-21
HARDWARE
FUNCTIONAL DESCRIPTION
of using a key input interrupt is shown in Figure 17, where an inter-
rupt request is generated by pressing one of the keys consisted as
an active-low key matrix which inputs to ports P80–P83.
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by applying “L” level to any
pin of port P8 that have been set to input mode. In other words, it is
generated when AND of input level goes from “1” to “0”. An example
Port PXx
“L” level output
PULL register A
Bit 5 = “1”
Port P8
7
Key input interrupt request
direction register = “1”
✽
✽
✽
✽
✽ ✽
✽ ✽
✽ ✽
✽ ✽
Port P8
latch
7
6
5
4
P8
7
output
output
Port P8
direction register = “1”
6
Port P8
latch
P8
6
Port P8
direction register = “1
5
Port P8
latch
P8
5
output
output
Po
d= “1”
Port P8
latch
P84
Port P8
3
direction register = “0”
Port P8
Input reading circuit
✽
P8
ch
3
P8
3
input
input
input
input
Port P8
2
direction register = “0”
✽ ✽
Port P8
latch
2
P8
2
Port P8
1
direction register = “0”
✽
✽ ✽
Port P8
latch
1
P81
Port P8
0
direction register = “0”
✽
✽ ✽
Port P8
latch
0
P80
✽P-channel transistor for pull-up
✽ ✽CMOS output buffer
Fig. 17 Connection example when using key input interrupt and port P8 block diagram
38C3 Group User’s Manual
1-22
HARDWARE
FUNCTIONAL DESCRIPTION
TIMERS
8-Bit Timer
The 38C3 group has six built-in timers : Timer 1, Timer 2, Timer 3,
b7
b7
b7
b0
Timer 4, Timer 5, and Timer 6.
Timer 12 mode register
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016,” an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is
set to “1.”
(T12M: address 002816
)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : f(XCIN
)
10 : f(XIN)/32 or f(XCIN)/32
The count can be stopped by setting the stop bit of each timer to “1.”
The system clock φ can be set to either the high-speed mode or low-
speed mode with the CPU mode register. At the same time, timer
internal count source is switched to either f(XIN) or f(XCIN).
11 : f(XIN)/128 or f(XCIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN
)
10 : External count input CNTR
11 : Not available
Timer 1 output selection bit (P4
0 : I/O port
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0
1)
●Timer 1,Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 under-
flow signal divided by 2 is output from the P41/T1OUT pin. The wave-
form polarity changes each time timer 1 overflows. The active edge
of the external clock CNTR0 can be switched with the bit 6 of the
interrupt edge selection register.
b
ode register
ress 002916
)
er 3 count stop bit
: Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/32 or f(XCIN)/32
11 : f(XIN)/128 or f(XCIN)/128
Timer 4 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR
11 : Not available
Timer 3 output selection bit (P4
0 : I/O port
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2 is
set to “0116.”
●Timer 3,Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 unde
flow signal divided by 2 is output from the P42/T3OUT pin. The w
form polarity changes each time timer 3 overflows. The acti
of the external clock CNTR1 can be switched with the
interrupt edge selection register.
1
2)
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b0
Timer 56 mode register
(T56M: address 002A16
)
●Timer 5,Timer 6
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
The count sources of timer 5 and timer 6 cd by setting
the timer 56 mode register. A rectangulatimer 6 under-
flow signal divided by 2 can be outpu2/PWM1 pin.
Timer 5 count source selection bit
0 : f(XIN)/16 or f(XCIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
●Timer 6 PWM1 Mode
Timer 6 can output a rectangular wform with “H” duty cycle n/
(n+m) from the P52/PWM1 pin by setting the timer 56 mode register
(refer to Figure 20). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P5
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
2)
Fig. 18 Structure of timer related register
38C3 Group User’s Manual
1-23
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
X
CIN
RESET
Timer 1 latch (8)
Timer 1 count source
selection bit
1/2
“01”
FF16
Internal system clock
selection bit
STP instruction
Timer 1 interrupt request
“1”
Timer 1 (8)
1/16
X
IN
“00”
“10”
“11”
Timer 1 count
stop bit
“0”
1/32
1/128
P41 latch
P41/T1OUT
1/2
Timer 1 output selection bit
Timer 2 latch (8)
Timer 2 count source
selection bit
“00”
“01”
0116
P41
direction register
Timer 2 interrupt request
Timer 2 (8)
Timer 2 count
stop bit
“10”
Rising/Falling
active edge switch
P53/CNTR0
CNTR0 interrupt request
Timer 3 latch (
Timer 3 count source
selection bit
“01”
“00”
Timer 3 interrupt request
Ti
Timer 3 co
stop bit
P42 latch
“10”
“11”
P42/T3OUT
1/2
Timer 3 output selection bit
Timer 4 latch (8)
source
P42
direction register
Timer 4 (8)
Timer 4 interrupt request
Timer 4 count
stop bit
Rising/Fallin
active edge
CNTR1 interrupt request
P54/CNTR1
Timer 5 latch (8)
Timer 5 count source
selection bit
“1”
“0”
Timer 5 interrupt request
Timer 5 (8)
Timer 5 count
stop bit
Timer 6 latch (8)
Timer 6 count source
selection bit
“01”
Timer 6 (8)
Timer 6 interrupt request
“00”
“10”
Timer 6 count
stop bit
Timer 6 PWM register (8)
P52 latch
P52/PWM1
PWM
1/2
“1”
“0”
Timer 6 output selection bit
Timer 6 operation
mode selection bit
P52 direction register
Fig. 19 Block diagram of timer
38C3 Group User’s Manual
1-24
HARDWARE
FUNCTIONAL DESCRIPTION
t
s
Timer 6
count source
Timer 6
PWM mode
n ✕ ts
m ✕ ts
(n+m) ✕ ts
Timer 6 interrupt request
Timinterrupt request
Note: PWM waveform (duty : n/(n+m) and period : (n+m) ✕ ts) is output.
n: setting value of Timer 6
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
Fig. 20 Timing chart of timer 6 PWM1 mode
16-bit Timer
ay time by a delay circuit.
Timer A is a 16-bit timer that can be selected in one of four modes by
ing this mode, set port P55 sharing the INT0 pin to input
and set port P50 sharing the TAOUT pin to output mode.
s possible to force the timer A output to be “L” using pins INT1 and
INT2 by the timer A control register.
the timer A mode register and the timer A control register.
●Timer A
The timer A operates as down-count. When the timer con
“000016”, an underflow occurs at the next count pulse r
latch contents are reloaded. After that, the timer unt-
down.When the timer underflows, the interrupt reespond-
ing to the timer A is set to “1”.
(4) PWM mode
IGBT dummy output, an external trigger with the INT0 pin and output
control with pins INT1 and INT2 are not used. Except for those, this
mode operates just as in the IGBT output mode.
The period of PWM waveform is specified by the timer A set value.
The “H” term is specified by the compare register set value.
When using this mode, set port P50 sharing the TAOUT pin to output
mode.
(1) Timer mode
The count source can be selected e timer A mode regis-
ter.
(2) Pulse output mode
Pulses of which polarity is inverted each time the timer underflows
are output from the TAOUT pin. Except for that, this mode operates
just as in the timer mode.
When using this mode, set port P50 sharing the TAOUT pin to output
mode.
(3) IGBT output mode
After dummy output from the TAOUT pin, count starts with the INT0
pin input as a trigger. When the trigger is detected or the timer A
underflows, “H” is output from the the TAOUT pin.
When the count value corresponds with the compare register value,
the TAOUT output becomes “L”. When the INT0 signal becomes “H”,
the TAOUT output is forced to become “L”.
After noise is cleared by noise filters, judging continuous 4-time same
levels with sampling clocks to be signals, the INT0 signal can use 4
38C3 Group User’s Manual
1-25
HARDWARE
FUNCTIONAL DESCRIPTION
External trigger delay
time selection bits
0µs
“00”
“01”
“10”
Data bus
4/f(XIN
)
)
Noise filter
(4-time same levels judgement)
INT0
8/f(XIN
16/f(XIN
)
“11”
Noise filter sampling
clock selection bit
Timer A
operating
“10”
mode bits
1/2
1/4
Internal trigger start
“00”, “01”, “11”
Timer A count source
selection bits
1/1
Timer A write control bit
1/2
1/4
1/8
XIN
Timer A (high-order) latch (8)
Timer A (high-order) (8)
Timer A (low-order) latch (8)
Timer A (low-order) (8)
Timer A underflow
interrupt request
Timer A output
control bit 1
“1”
INT1
INT2
Match
“0”
Compare register (high-order) (8)
Compare register (low-order
Timer A output
control bit 2
“1”
“0”
Timer A operating
mode bits
“00”, “01”, “11”
Timer A output
active edge
swi“tc0h”bit
“10”
R
Q
Q
D
Timer A start
signal
P50/TAOUT
“1”
IGBT output mode
PWM mode
(Note)
P50
direction
register
tput mode
P50 latch
“0”
Output selection bit
Note: The initial value of M version becomes “1”
Fig. 21 Block diagram of timer A
b7
b0
b7
b0
Timer A control register
(TACON : address 003116
Timer A mo
(TAM : a6
)
)
Noise filter sampling clock selection bit
0 : f(XIN)/2
1 : f(XIN)/4
External trigger delay time selection bits
0 0 : No delay
0 1 : ( 4/f(XIN))µs
Timg mode bits
00 : Tde
01 : Pulutput mode
10 : IGBT output mode
11 : PWM mode
Timer A write control bit
0 : Write data to both timer latch and timer
1 0 : ( 8/f(XIN))µs
1 : Write data to timer latch onl
Timer A count source selection bits
0 0 : f(XIN
0 1 : f(XIN)/2
1 0 : f(XIN)/4
y
1 1 : (16/f(XIN))µs
Timer A output control bit 1 (P5
0 : Not used
1 : INT1 interrupt used
Timer A output control bit 2 (P5
0 : Not used
6
7
)
)
)
1 1 : f(XIN)/8
Timer A output active edge switch bit
0 : Output starts with “L” level
1 : Output starts with “H” level
Timer A count stop bit
0 : Count operating
1 : Count stop
1 : INT2 interrupt used
Not used (returns “0” when read)
Timer A output selection bit (P5
0 : I/O port
0)
1 : Timer A output
Fig. 22 Structure of timer A related registers
38C3 Group User’s Manual
1-26
HARDWARE
FUNCTIONAL DESCRIPTION
t
s
Timer A count
source
Timer A
PWM mode
IGBT output mode
(n-m+1) ✕ ts
m ✕ ts
(n+1) ✕ ts
Note: PWM waveform (duty : (n-m+1)/(n+1) and period : (n+1) ✕ ts) is output.
n : setting value of Timer A
m : setting value of compare register
ts : period of Timer A count source
Fig. 23 Timing chart of timer A PWM, IGBT output modes
■Notes on Timer A
(4) Set ode register
(1) Write order to timer A
Set rol bit to “1” (write to the latch only) when setting the
IM modes.
• In the timer and pulse output modes, write to the timer A register
(low-order) first and to the timer A register (high-order) next. Do not
write to only one side.
veform simultaneously reflects the contents of both regis-
the next underflow after writing to the timer A register (high-
r).
• In the IGBT and PWM modes, write to the registers as follows:
the compare register (high- and low-order)
the timer A register (low-order)
(5) Output control function of timer A
the timer A register (high-order).
When using the output control function (INT1 and INT2) in the IGBT
mode, set the levels of INT1 and INT2 to “H” in the falling edge active
or to “L” in the rising edge active before switching to the IGBT mode.
It is possible to use whichever order to write to the cter
(high- and low-order). However, write both the coer and
the timer A register at the same time.
(2) Read order to timer A
• In all modes, read to the timer A reder) first and to the
timer A register (low-order) nexto the compare regis-
ter is not specified.
• If reading to the timer A register durig write operation or writing to
it during read operation, normal operation will not be performed.
(3) Write to timer A
• When writing a value to the timer A address to write to the latch
only, the value is set into the reload latch and the timer is updated
at the next underflow. Normally, when writing a value to the timer A
address, the value is set into the timer and the timer latch at the
same time, because they are written at the same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, an ex-
pected value may be set in the high-order counter.
• Do not switch the timer count source during timer count operation.
Stop the timer count before switching it. Additionally, when perform-
ing write to the latch and the timer at the same time, the timer count
value may change large.
38C3 Group User’s Manual
1-27
HARDWARE
FUNCTIONAL DESCRIPTION
SERIAL I/O
I/O pins of serial I/O also operate as I/O port P4, and their function is
selected by the serial I/O control register 1 (address 001916).
The 38C3 group has a built-in 8-bit clock synchronous serial I/O.The
Internal synchronous
clock selection bits
Data bus
1/8
Internal
system clock
selection bit
X
CIN
1/16
1/32
1/64
“1”
“0”
X
IN
1/128
1/256
P47 latch
Synchronous clock
selection bit
“0”
“1”
P4
7
/SRDY
S
RDY
Synchronous
circuit
“1”
S
RDY output selection bit
“0”
External clock
P4
“0”
6 latch
P4
6
/SCLK1
Serial I/O
interrupt request
Serial I/O counter (3)
“1”
Serial I/O port selection bit
P4
“0”
5 latch
P45/SOUT
“1”
Serial I/O port selection bit
Serial r (8)
P44/SIN
P4
“0”
0 latch
P40/SCLK2
“1”
Serial I/O port selection bit
Fig. 24 Block diagram of serial I/O
[Serial I/O Control Re, 2 (SIOCON1,
SIOCON2)] 001916, 001
When selecting internal clock and setting “1” to SIOCON20, the P40
pin can be also used as synchronous clock output pin SCLK2. At this
time, the SCLK1 pin can be used as I/O port.
Each of the serial I/O control register, 2 contains 8 bits that select
various control parameters of serial I/O.
Table 9 Function of P46/SCLK1 and P40/SCLK2
●Operation in serial I/O mode
SIOCON16 SIOCON13
SIOCON20 P46/SCLK1 P40/SCLK2
Either an internal clock or an external clock can be selected as the
synchronous clock for serial I/O transfer. A dedicated divider is built-
in as the internal clock, giving a choice of six clocks.
0
1
SCLK1
P46
P40
1
1
SCLK2
SIOCON13: Serial I/O port selection bit
When internal clock is selected, serial I/O starts to transfer by a write
signal to the serial I/O register (address 001B16). After 8 bits have
been transferred, the SOUT pin goes to high impedance.
When external clock is selected, the clock must be controlled exter-
nally because the contents of the serial I/O register continue to shift
while the transfer clock is input. In this case, the SOUT pin does not
go to high impedance at the completion of data transfer.
The interrupt request bit is set at the end of the transfer of 8 bits,
regardless of whether the internal or external clock is selected.
SIOCON16: Synchronous clock selection bit
SIOCON20: Synchronous clock output pin selection bit
38C3 Group User’s Manual
1-28
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
b7
b0
Serial I/O control register 1
(SIOCON1 : address 001916)
Internal synchronous clock selection bits
b2 b1 b0
Serial I/O control register 2
(SIOCON2: address 001A16)
Synchronous clock output pin selection bit
0 : SCLK1
1 : SCLK2
Not used (returns “0” when read)
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(XIN)/8 or f(XCIN)/8
1 : f(XIN)/16 or f(XCIN)/16
0 : f(XIN)32 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/64
0 : f(XIN)/128 or f(XCIN)/128
1 : f(XIN)/256 or f(XCIN)/256
Serial I/O port selection bit (P40, P45, P46)
0 : I/O port
1 : SOUT, SCLK1, SCLK2 signal pin
SRDY output selection bit (P47)
0 : I/O port
1 : SRDY signal pin
Transfer direction selection bit
0 : LSB first
1 : MSB first
Synchronous clock selection bit
0 : External clock
1 : Internal clock
P-channel output disable bit (P40, P45, P46)
0 : CMOS output (in output mode)
1 : N-channel open-drain (in output mode)
Fig. 25 Structure of serial I/O control register
Synchronous clock
Transfer clock
Serial I/O register
write signal
(Note)
Serial I/O output
D
1
D2
D3
D4
D5
D
6
D7
SOUT
Serial I/O input
SIN
Receive enable signal
SRDY
Note: When internaelected, the SOUT pin goes to high impedance after
Interrupt request bit set
transfer ends.
Fig. 26 Serial I/O timing (for LSB first)
38C3 Group User’s Manual
1-29
HARDWARE
FUNCTIONAL DESCRIPTION
A-D CONVERTER
Note that the comparator is constructed linked to a capacitor, so set
f(XIN) to at least 500 kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal system clock.
The 38C3 group has a 10-bit A-D converter. The A-D converter per-
forms successive approximation conversion.
[A-D Conversion Register (AD)] 003316, 003416
One of these registers is a high-order register, and the other is a low-
order register.The high-order 8 bits of a conversion result is stored in
the A-D conversion register (high-order) (address 003416), and the
low-order 2 bits of the same result are stored in bit 7 and bit 6 of the
A-D conversion register (low-order) (address 003316).
b7
b0
A-D control register
(ADCON: address 003216
)
Analog input pin selection bits
000: P6 /AN
001: P6 /AN
0
0
During A-D conversion, do not read these registers.
1
1
010: P6
011: P6
100: P6
101: P6
110: P6
111: P6
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
2
3
4
5
6
7
[A-D Control Register (ADCON)] 003216
This register controls A-D converter. Bits 2 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conver-
sion.
Not used (returns “0” when read)
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
A-D conversion is started by setting “0” in this bit.
Not used (returns “0” when read)
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
and VREF, and outputs the divided voltages.
b7
b0
A-D conversion register (high-order)
(ADH: address 003416
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
)
AD conversion result stored bits
AN0 and inputs it to the comparator.
[Comparator and Control Circuit]
b7
b0
The comparator and control circuit compares an analog input vol
age with the comparison voltage and stores the result in the
conversion register. When an A-D conversion is completed,
trol circuit sets the AD conversion completion bit and the
sion interrupt request bit to “1.”
A-D conversion register (low-order)
(ADL: address 003316
)
Not used (returns “0” when read)
AD conversion result stored bits
Fig. 27 Structure of A-D control register
Data bus
b7
b0
A-D control register
3
P6
P6
P6
P6
P6
P6
P6
P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
A-D control circuit
A-D interrupt request
A-D conversion register (H)
Comparator
A-D conversion register (L)
(Address 003416
)
(Address 003316
)
Resistor ladder
AVSS
VREF
Fig. 28 Block diagram of A-D converter
38C3 Group User’s Manual
1-30
HARDWARE
FUNCTIONAL DESCRIPTION
LCD DRIVE CONTROL CIRCUIT
The 38C3 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
• LCD display RAM
segment output enable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, per-
forms the bias control and the duty ratio control, and displays the
data on the LCD panel.
• Segment output enable register
• LCD mode register
Table 10 Maximum number of display pixels at each duty ratio
• Selector
Duty ratio
1
Maximum number of display pixels
32 dots
or 8 segment LCD 4 digits
• Timing controller
• Common driver
• Segment driver
64 dots
or 8 segment LCD 8 digits
2
3
4
• Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
96 dots
or 8 segment LCD 12 digits
Up to 128 pixels can be controlled for a LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register, the
128 dots
or 8 segment LCD 16 digits
b7
b0
Segment output enable register
(SEG : address 003816
)
Segment output enab
0 : I/O ports P2
1 : Segment o
Segment outp
0 : I/O po
1 : SeG
Segme bit 2
0 P0
utput SEG
ut enable bit 3
rts P0 –P0
0
G
3
7
4–SEG
3
8–SEG11
4
7
ment output SEG12–SEG15
ent output enable bit 4
: I/O ports P10–P13
1 : Segment output SEG16–SEG19
Segment output enable bit 5
0 : I/O ports P14–P17
1 : Segment output SEG20–SEG23
Segment output enable bit 6
0 : Output ports P30–P33
1 : Segment output SEG24–SEG27
Segment output enable bit 7
0 : Output ports P3
4–P37
1 : Segment output SEG28–SEG31
b0
LCD mode register
(LM : address 003916
)
Duty ratio selection bits
0 0 : 1 (use COM
0 1 : 2 (use COM
1 0 : 3 (use COM
1 1 : 4 (use COM
Bias control bit
0 : 1/3 bias
0
0
0
0
)
,COM1)
–COM
–COM
2
)
3)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit.)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
Fig. 29 Structure of LCD related registers
38C3 Group User’s Manual
1-31
HARDWARE
FUNCTIONAL DESCRIPTION
Fig. 30 Block diagram of LCD controller/driver
38C3 Group User’s Manual
1-32
HARDWARE
FUNCTIONAL DESCRIPTION
Bias Control and AppliedVoltage to LCD Power
Input Pins
Table 11 Bias control and applied voltage to VL1–VL3
Bias value
Voltage value
To the LCD power input pins (VL1–VL3), apply the voltage value shown
VL3=VLCD
in Table 11 according to the bias value.
1/3 bias
VL2=2/3 VLCD
VL1=1/3 VLCD
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
VL3=VLCD
VL2=VL1=1/2 VLCD
1/2 bias
1/1 bias
VL3=VLCD
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by duty
ratio.
(1-duty ratio) VL2=VL1=VSS
Note 1: VLCD is the maximum value of supplied voltage for the LCD panel.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
Table 12 Duty ratio control and common pins used
When selecting 1-duty ratio, 1/1 bias can be used.
Duty ratio selection bit
Duty
ratio
Common pins used
COM0 (Note 1)
Bit 1
Bit 0
1
2
3
4
0
0
1
1
0
1
0
1
COM0, COM1 (Note 2)
COM0–COM2 (Note 3)
COM0–COM3
Notes 1:COM1, COM2, apen.
2:COM2 and CO
3:COM3 is op
Contrast control
Contras
Contrast control
V
L3
V
L3
R1
R4
R5
V
V
L2
L1
V
V
L2
L1
V
L2
R2
V
L1
R6
R4 = R5
R1 = R2 = R3
1/3 bias
1/2 bias
1/1 bias
Fig. 31 Example of circuit at each bias
38C3 Group User’s Manual
1-33
HARDWARE
FUNCTIONAL DESCRIPTION
LCD Display RAM
LCD Drive Timing
Address 004016 to 004F16 is the designated RAM for the LCD dis-
play.When “1” are written to these addresses, the corresponding seg-
ments of the LCD display panel are turned on.
The LCDCK timing frequency (LCD drive timing) is generated inter-
nally and the frame frequency can be determined with the following
equation;
(frequency of count source for LCDCK)
f(LCDCK)=
(divider division ratio for LCD)
f(LCDCK)
Frame frequency=
duty ratio
Bit
7
6
5
4
3
2
1
0
Address
004016
004116
004216
004316
004416
SEG
SEG
SEG
SEG
SEG
1
3
5
7
9
SEG
SEG
SEG
SEG
SEG
0
2
4
6
8
004516
004616
004716
004816
SEG11
SEG10
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG
SEG
S
0
G22
SEG24
SEG26
SEG28
SEG30
004916
004A16
004B16
004C16
004D16
004E16
004F16
COM
3
COM
0
COM
3
COM
2
COM
1
COM0
Fig. 32 LCD display RAM map
38C3 Group User’s Manual
1-34
HARDWARE
FUNCTIONAL DESCRIPTION
Internal
signal
LCDCK
timing
1/4 duty
Voltage level
V
V
V
L3
L2=VL1
SS
COM
COM
COM
COM
0
1
2
3
V
V
L3
SEG
0
SS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
2
COM
1
C
1/3 duty
V
V
V
L3
L2=VL1
SS
COM
COM
COM
0
1
2
V
V
L3
SEG
0
SS
ON
OFF
ON
ON
OFF
COM
C
COM
0
COM
2
COM
1
COM
1
COM
0
2
1/2 duty
V
V
V
L3
L2=VL1
SS
COM
COM
0
1
V
V
L3
SEG
0
SS
O
OM
ON
OFF
COM
ON
OFF
COM
ON
OFF
COM
0
COM
1
0
COM
1
0
COM
1
0
1/1 duty (1/1 bias)
VL3
COM
0
V
L2=VL1=VSS
L3
V
SEG
0
VSS
OFF
ON
Fig. 33 LCD drive waveform (1/2 bias)
38C3 Group User’s Manual
1-35
HARDWARE
FUNCTIONAL DESCRIPTION
Internal signal
LCDCK timing
1/4 duty
Voltage level
VL3
VL2
VL1
VSS
COM0
COM1
COM2
COM3
SEG0
VL3
VSS
OFF
ON
O
ON
COM3
COM
COM2
COM1
COM0
COM1
COM0
1/3 duty
COM0
COM1
COM2
VL3
VL2
VL1
VSS
VL3
SEG0
VSS
ON
ON
OFF
ON
OFF
CO
COM2
COM1
COM0
COM2
2
COM1
COM0
1/2 duty
VL3
VL2
VL1
VSS
COM0
COM1
SEG0
VL3
VSS
ON
OFF
ON
COM1
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM0
Fig. 34 LCD drive waveform (1/3 bias)
38C3 Group User’s Manual
1-36
HARDWARE
FUNCTIONAL DESCRIPTION
φ CLOCK OUTPUT FUNCTION
The internal system clock φ can be output from port P43 by setting
the φ output control register. Set “1” to bit 3 of the port P4 direction
register when outputting φ clock.
b7
b0
φ output control register
(CKOUT : address 002B16
)
φ output control bit
0 : Port function
1 : φ clock output
Not used (return “0” when read)
Fig. 35 Structure of φ output control register
38C3 Group User’s Manual
1-37
HARDWARE
FUNCTIONAL DESCRIPTION
ROM CORRECTION FUNCTION (Mask ROM
version only)
ROM correct high-order address register 1
ROM correct low-order address register 1
ROM correct high-order address register 2
ROM correct low-order address register 2
ROM correct high-order address register 3
ROM correct low-order address register 3
ROM correct high-order address register 4
ROM correct low-order address register 4
ROM correct high-order address register 5
ROM correct low-order address register 5
ROM correct high-order address register 6
ROM correct low-order address register 6
ROM correct high-order address register 7
ROM correct low-order address register 7
ROM correct high-order address register 8
ROM correct low-order address register 8
0F0216
0F0316
0F0416
0F0516
0F0616
0F0716
0F0816
0F0916
0F0A16
0F0B16
0F0C16
0F0D16
0F0E16
0F0F16
0F1016
0F1116
The 38C3 group has the ROM correction function correcting data at
the arbitrary addresses in the ROM area.
[ROM correct address register] 0F0216 – 0F1116
This is the register to store the address performing ROM correction.
There are two types of registers to correct up to 8 addresses: one is
the register to store the high-order address and the other is to store
the low-order address.
[ROM correct enable register 1 (RC1)] 0F0116
This is the register to enable the ROM correction function. When set-
ting the bit corresponding to the ROM correction address to “1”, the
ROM correction function is enabled.
It becomes invalid to the addresses of which corresponding bit is “0”.
All bits are “0” at the initial state.
Fig. 36 Structure of ROM rect address register
[ROM correct data]
This is the register to store a correct data for the address specified by
the ROM correct address register.
00
416
005516
005616
005716
ROM correct data 1
ROM correct data 2
ROM correct data 3
ROM correct data 4
ROM correct data 5
ROM correct data 6
ROM correct data 7
ROM correct data 8
■Notes on ROM correction function
1. To use the ROM correction function, transfer data to each ROM
correct data register in the initial setting.
2. Do not specify the same addresses in the ROM correct address
register.
Fig. 37 Structure of ROM correct data
b7
ROM correct enable register 1(address 0F0116
RC1
)
ROM correct address 1 enable bit
0 : Disabled
1 : Enabled
ROM correct address 2 enable bit
0 : Disabled
1 : Enabled
ROM correct address 3 enable bit
0 : Disabled
1 : Enabled
ROM correct address 4 enable bit
0 : Disabled
1 : Enabled
ROM correct address 5 enable bit
0 : Disabled
1 : Enabled
ROM correct address 6 enable bit
0 : Disabled
1 : Enabled
ROM correct address 7 enable bit
0 : Disabled
1 : Enabled
ROM correct address 8 enable bit
0 : Disabled
1 : Enabled
Fig. 38 Structure of ROM correct enable register 1
38C3 Group User’s Manual
1-38
HARDWARE
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
______
Poweron
To reset the microcomputer, RESET pin should be held at an “L” level
______
(Note)
for 2 µs or more. Then the RESET pin is returned to an “H” level (the
power source voltage should be between 2.5 V and 5.5 V (M version:
2.2✽ V to 5.5 V), and the oscillation should be stable), reset is re-
leased. After the reset is completed, the program starts from the ad-
dress contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.5 V for VCC of 2.5 V (M version: less than 0.44 V for Vcc
of 2.2✽ V) when switching to the high-speed mode, a power source
voltage must be between 4.0 V and 5.5 V.
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; Vcc=2.5 V
(M version is 2.2 V.)
RESET
V
CC
Power source
voltage detection
circuit
Fig. 39 Resample
X
IN
φ
RESET
Internal
reset
Reset address from
vector table
Address
Data
?
?
?
?
ADH, AD
L
FFFC
FFFD
AD
L
ADH
SYNC
X
IN : about 8000 cycles
Note 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 40 Reset sequence
38C3 Group User’s Manual
1-39
HARDWARE
FUNCTIONAL DESCRIPTION
Address Register contents
Address Register contents
002D16
FF16
000016
000116
000216
000316
(1)
(2)
(3)
(4)
0016
0016
0016
0016
(34)
(35)
(36)
(37)
(38)
Port P0
Timer A register (high-order)
Compare register (low-order)
Compare register (high-order)
Timer A mode register
0016
0016
0016
0016
002E16
002F16
Port P0 direction register
Port P1
003016
003116
Port P1 direction register
Timer A control register
000416
000516
000616
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001616
001716
001816
001916
001A16
002
2316
002416
002516
(5) Port P2
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0F16
0016
0016
6
003216
003816
(39)
(40)
A-D control register
(6) Port P2 direction register
(7) Port P3
1016
0016
0016
0016
Segment output enable register
(8)
Port P4
LCD mode register
003916
003A16
(41)
(42)
(9)
Port P4 direction register
Port P5
Interrupt edge selection register
CPU mode register
(10)
003B16
03C16
16
003E16
003F16
0F0116
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(5
53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
0 1 0 0 1 0 0 0
0016
(11) Port P5 direction register
(12) Port P6
Interrupt request register 1
Interrupt request registe
Interrupt control re
Interrupt cont
ROM cogister 1
0016
(13) Port P6 direction register
0016
(14)
(15)
(16)
Port P7
0016
Port P7 direction register
Port P8
0016
RO-order address
t low-order address
0F0216
0F0316
FF16
(17) Port P8 direction register
FF16
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
PULL register A
PULL register B
Port P8 output selection register
Serial I/O control register 1
Serial I/O control register 2
Timer 1
orrect high-order address 0F0416
ster 2
OM correct low-order address 0F0516
register 2
FF16
FF16
ROM correct high-order address 0F0616
register 3
ROM correct low-order address 0F0716
register 3
ROM correct high-order address 0F0816
register 4
FF16
FF16
FF16
ROM correct low-order address
register 4
ROM correct high-order address
register 5
0F0916
FF16
Timer 2
0F0A16
FF16
0116
FF16
FF16
ROM correct low-order address 0F0B16
register 5
Timer 3
FF16
Timer 4
ROM correct high-order address 0F0C16
register 6
ROM correct low-order address 0F0D16
register 6
ROM correct high-order address 0F0E16
register 7
ROM correct low-order address 0F0F16
register 7
FF16
Timer 5
FF16
FF16
0016
0016
0016
0016
FF16
FF16
Timer 6
FF16
Timer 12 mode register
Timer 34 mode register
Timer 56 mode register
002816
002916
002A16
FF16
ROM correct high-order address 0F1016
register 8
FF16
ROM correct low-order address
register 8
0F1116
FF16
002B16
002C16
(PS) ✕ ✕ ✕ ✕ ✕
✕ ✕
1
Processor status register
(32)
(33)
φ output control register
(PC
H
)
)
FFFD16 contents
FFFC16 contents
Program counter
Timer A register (low-order)
(PC
L
X: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
In the M version, bit 0 of the port P5 direction register becomes “1.”
Fig. 41 Internal status at reset
38C3 Group User’s Manual
1-40
HARDWARE
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
Oscillation control
The 38C3 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No external re-
sistor is needed between XIN and XOUT since a feedback resistor
exists on-chip. However, an external feedback resistor is needed be-
tween XCIN and XCOUT.
(1) Stop mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and XIN and XCIN oscillators stop.Timer 1 is set to “FF16”
and timer 2 is set to “0116.”
Either XIN divided by 16 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0.” Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before execut-
ing the STP instruction. Oscillator restarts when an external interrupt
is received, but the internal system clock is not supplied to the CPU
until timer 2 underflows. This allows time for the clock circuit oscilla-
tion to stabilize.
Immediately after power on, only the XIN oscillation circuit starts os-
cillating, and XCIN and XCOUT pins function as I/O ports.
Frequency control
(1) Middle-speed mode
The internal system clock is the frequency of XIN divided by 8. After
reset, this mode is selected.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops at
an “H” level. The states of XIN and XCIN are the same as the state
before executing the WIT inuction. The internal system clock re-
starts at reset or when at is received. Since the oscillator
does not stop, normal n be started immediately after the
clock is restarted.
(2) High-speed mode
The internal system clock is the frequency of XIN divided by 2.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
■Notes on clock generating circuit
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations.The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode.When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(XIN) > 3f(XCIN).
XCIN
XCOUT
XIN
XOUT
Rf
Rd
COUT
CCIN
CCOUT
CIN
Fig. 42 Ceramic resonator circuit
X
CIN
X
COUT
X
IN
XOUT
Rf
open
External oscillation circuit
Rd
CCOUT
CCIN
V
CC
SS
V
Fig. 43 External clock input circuit
38C3 Group User’s Manual
1-41
HARDWARE
FUNCTIONAL DESCRIPTION
X
COUT
X
CIN
“1”
“0”
Port X
C
switch bit
Internal system clock selection bit
X
IN
X
OUT
(Note)
Low-speed mode
“1”
Timer 2
Timer 1
1/2
1/2
1/4
“0”
Middle-/High-speed mode
Main clock division rati
Middle-speed mode
“1”
Timing φ
(Internal system clock)
“0”
High-speed mode
or Low-speed mode
Main clock stop bit
Q
S
R
Q
S
R
WI
i
STP instruction
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Note : When using ted mode, set the port X
C
switch bit to “1” .
Fig. 44 Clock generating circuit block diagram
38C3 Group User’s Manual
1-42
HARDWARE
FUNCTIONAL DESCRIPTION
Reset
High-speed mode
(f( ) =4 MHz)
Middle-speed mode
(f(φ)=1 MHz)
CM
“1”
6
φ
CM
CM
CM
CM
7
6
5
4
=0(8 MHz selected)
=0(high-speed)
=0(8 MHz oscillating)
=0(32 kHz stopped)
“0”
CM7
CM6
CM5
CM4
=0(8 MHz selected)
=1(middle-speed)
=0(8 MHz oscillating)
=0(32 kHz stopped)
“0”
CM
4
“0”
6
4
“1”
CM
CM
“0”
“1”
6
CM
“1”
“1”
“0”
Middle-speed mode
((f(φ)=1 MHz)
High-speed mode
(f( ) =4 MHz)
CM
6
φ
“1”
“0”
CM
CM
CM
CM
7
=0(8 MHz selected)
=1(middle-speed)
=0(8 MHz oscillating)
=1(32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
=0(8 MHz selected)
=0(high-speed)
=0(8 MHz oscillating)
=1(32 kHz oscillating)
6
5
4
Low-speed mode
Low
((f(φ)=16 kHz)
CM
6
CM
CM
CM
CM
7
=1(32 kHz selected)
=1(middle-speed)
=0(8 MHz oscillating)
“1”
“0”
cted)
ed)
oscillating)
kHz oscillating)
6
5
4
b7
b4
CPU mode register
=1(32 kHz oscillating)
(CPUM : address 003B16
)
CM
CM
CM
CM
4 : Port Xc switch bit
0: I/O port function
1: XCIN-XCOUT oscillating function
“0”
6
CM
“1”
5
: Main clock (XIN- XOUT) stop bit
“0”
“1”
0: Oscillating
1: Stopped
CM
“1”
“0”
6: Main clock division ratio selection bit
Low-speed mode
(f( ) =16 kHz)
Low-speed mode
((f(φ)=16 kHz)
0: f(XIN)/2(High-speed mode)
1: f(XIN)/8 (Middle-speed mode)
φ
M
6
7: Internal system clock selection bit
CM
7
6
5
4
=1(32 kHz selected)
=1(middle-speed)
=1(8 MHz stopped)
CM
CM
CM
CM
7
=1(32 kHz selected)
=0(high-speed)
=1(8 MHz stopped)
“1”
“0”
0: XIN–XOUT selected (Middle-/High-speed mode)
1: XCIN–XCOUT selected (Low-speed mode)
CM
CM
CM
6
5
4
=1(32 kHz oscillating)
=1(32 kHz oscillating)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended.
3: Timer,LCD operate in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by connecting Timer 1 and Timer 2 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs in low-speed mode.
6: Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/high-speed mode.
7: The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal system clock.
Fig. 45 State transitions of system clock
38C3 Group User’s Manual
1-43
HARDWARE
NOTES ON PROGRAMMING/NOTES ON USE
NOTES ON PROGRAMMING
A-D Converter
Processor Status Register
The comparator uses internal capacitors whose charge will be lost if
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D
conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
Instruction Execution Time
Interrupts
The instruction execution time is obtained by multiplying the frequency
of the internal system clock by the number of cycles needed to ex-
ecute an instruction.
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
The frequency of the internal system clock is the same half of the XIN
frequency in high-speed mode.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
At STP Instruction Release
At the STP instruction releaall bits of the timer 12 mode register
are cleared.
• In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
NOTES ON U
Notes on PROM Version
The P51 pin Time PROM version or the EPROM version
functioner source input pin of the internal EPROM.
Thern is set at low input impedance, thereby being af-
fey noise.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
a malfunction due to noise, insert a resistor (approx. 5 kΩ)
with the P51 pin.
• The execution of these instructions does not change the con
of the processor status register.
Ports
The contents of the port direction registers cannoe fol-
lowing cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the indag (T) is “1”
• The addressing mode which uses direction register
as an index
• The bit-test instruction (BBC or ) to a direction register
• The read-modify-write instructions OR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
• Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
• Using an internal clock
When using an internal clock, set the synchronous clock to the in-
ternal clock, then clear the serial I/O interrupt request bit before
executing a serial I/O transfer and serial I/O automatic transfer.
38C3 Group User’s Manual
1-44
HARDWARE
DATA REQUIRED FOR MASK ORDERS AND ROM WRITING ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1. Mask ROM Order Confirmation Form
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-in
EPROM version can be read or programmed with a general-purpose
PROM programmer using a special programming adapter.
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical copies)
Table 13 Programming adapter
DATA REQUIRED FOR ROMWRITING ORDERS
The following are necessary when ordering a ROM writing:
1. ROM Writing Confirmation Form
Package
80P6N-A
80D0
Name of Programming Adapter
PCA4738F-80A
PCA4738L-80A
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical copies)
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 46 is recommended to verify programming.
Pwith PROM
ammer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 46 Programming and testing of One Time PROM version
38C3 Group User’s Manual
1-45
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
higher-priority interrupt is accepted first. This priority is determined
by hardware, but various priority processing can be performed by
software, using an interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to
Table 14.
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt
38C3 group permits interrupts on the basis of 16 sources.
It is vector interrupts with a fixed priority system. Accordingly, when
two or more interrupt requests occur during the same sampling, the
Table 14 Interrupt sources, vector addresses and interrupt priority
Vector Addresses (Note 1)
Interrupt Request
Remarks
Interrupt Source Priority
Generating Conditions
High
Low
Reset (Note 2)
1
2
FFFD16
FFFB16
FFFC16
FFFA16
At reset
Non-maskable
INT0
At detection of either rising or falling edge External interrupt
of INT0 input
(active edge selectable)
INT1
3
4
5
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
At detection of either rising or falling edge External interrupt
of INT1 input
(active edge selectable)
INT2
At detection of either rising or falling edge External interrupt
of INT2 input
(active edge selectable)
Serial I/O
At completion of serial I/O data transmit/re- Valid when serial I/O is selected
ceive
Timer A
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
CNTR0
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
At timer A underflow
At timer 1 underflow
8
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
STP release timer underflow
9
10
11
12
13
At detection of eir falling edge External interrupt
of CNTR0 input
(active edge selectable)
CNTR1
14
15
16
17
FFE316
FFE116
FFDF16
FFDD16
FFE216
FFE016
FFDE16
FFDC1
At detectioing or falling edge External interrupt
of CNTR
(active edge selectable)
Key input (Key-
on wake-up)
At fall8 (at input) input logical External interrupt
lev
(falling valid)
A-D conversion
n of A-D conversion
Valid when A-D conversion interrupt is
selected
BRK instruction
instruction execution
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump dessses.
2: Reset function in the same way as an inthighest priority.
38C3 Group User’s Manual
1-46
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
The interrupt processing routine begins with the machine cycle fol-
lowing the completion of the instruction that is currently in execution.
Figure 47 shows a timing chart after an interrupt occurs, and Figure
48 shows the time up to execution of the interrupt processing routine.
φ
SYNC
RD
WR
Address bus
S, SPS S-1, SPS S-2, SPS
BL
B
H
AL, AH
PC
Data bus
Not used
PC
H
PC
L
PS
AL
AH
SYNC
: CPU operation code fetch cycle
(This is an internal signal which cannved from the external unit.)
: Vector address of each interrupt
: Jump destination address of eat
B
A
L
L
, B
, A
H
H
SPS
: “0016” or “0116
”
Fig. 47 Timing chart after interrupt occurs
Interrupt request occu
Main routine
Interrupt operation starts
Push onto
stack vector
fetch
Waiting time for
pipeline post-
processing
Interrupt processing routine
0 to 16 cycles
2 cycles
5 cycles
7 to 23 cycles (4 MHz, 1.75 µs to 5.75 µs)
Fig. 48 Time up to execution of interrupt processing routine
38C3 Group User’s Manual
1-47
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
By repeating the above operations up to the lowest-order bit of the
A-D conversion register, an analog value converts into a digital value.
A-D conversion completes at 61 clock cycles (15.25 µs at f(XIN) = 8
MHz) after it is started, and the result of the conversion is stored into
the A-D conversion register.
A-D conversion is started by setting AD conversion completion bit to
“0.” During A-D conversion, internal operations are performed as fol-
lows.
1. After the start of A-D conversion, A-D conversion register goes to
“0016.”
Concurrently with the completion of A-D conversion, A-D conversion
interrupt request occurs, so that the AD conversion interrupt request
bit is set to “1.”
2. The highest-order bit of A-D conversion register is set to “1,” and
the comparison voltage Vref is input to the comparator. Then, Vref
is compared with analog input voltage VIN.
3. As a result of comparison, when Vref < VIN, the highest-order bit of
A-D conversion register becomes “1.” When Vref > VIN, the high-
est-order bit becomes “0.”
Table 15 Relative formula for a reference voltage VREF of A-D
converter and Vref
When n = 0
Vref = 0
VREF
1024
When n = 1 to 1023
Vref =
✕ n
n: Value of A-D converter (decimal numeral)
Table 16 Change of A-D conversion register during A-D conversion
Change of A-D conversion register
Value of comparison voltage (Vref)
At start of conversion
First comparison
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VREF
2
VREF
2
VREF
±
Second comparison
Third comparison
✽1
4
VREF
2
VREF
8
VREF
4
±
±
±
✽1 ✽2
0
0
0
1
~
~
~
~
After completion of tenth
comparison
A result osion
✽1 ✽✽5 ✽6 ✽7 ✽8
VREF
2
VREF
1024
VREF
4
±
±
• • • •
✽9 ✽10
✽1–✽10: A result of the first comparisocomparison
38C3 Group User’s Manual
1-48
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 49 shows the A-D conversion equivalent circuit, and Figure
50 shows the A-D conversion timing chart.
V
CC
V
SS
V
CC
VSS
About 2 kΩ
V
IN
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
Sampling
clock
C
Chopper
amplifier
A-D conversion register (high-order)
A-n register
b1
b2
b0
A-D control
register
conversion interrupt request
V
r
V
REF
Built-in
ce
D-A conve
AVSS
Fig. 49 A-D conversion equivalent cir
φ
Write signal for A-D
control register
61 cycles
AD conversion
completion bit
Sampling clock
Fig. 50 A-D conversion timing chart
38C3 Group User’s Manual
1-49
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
MEMORANDUM
38C3 Group User’s Manual
1-50
CHAPTER 2
APPLICATION
2.ort
mer
Serial I/O
.4 LCD controller
2.5 A-D converter
2.6 ROM correct function
2.7 Reset circuit
2.8 Clock generating circuit
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph describes the setting method of I/O port relevant registers, notes etc.
2.1.1 Memory map
Address
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
000416 Port P2 (P2)
000516 Port P2 direction register (P
000616 Port P3 (P3)
000716
000816 Port P4 (P4)
000916 Port P4 direcster (P4D)
000A16 Port P5 (
000B16 Port Pion register (P5D)
000C16 P6)
000D16 6 direction register (P6D)
000Ert P7 (P7)
0Port P7 direction register (P7D)
0016 Port P8 (P8)
001116 Port P8 direction register (P8D)
001616 PULL register A (PULLA)
PULL register B (PULLB)
001716
001816
Port P8 output selection register (P8SEL)
Fig. 2.1.1 Memory map of I/O port relevant registers
38C3 Group User’s Manual
2-2
APPLICATION
2.1 I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 8)
(Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 1016
)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
7
Port Pi
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
●In output mode
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
Fig. 2.1.2 Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 6, 8)
Port P7
b7 b6 b5 b4 b3 b2 b1 b0
Port P7
(P7: address 0E16)
b
0
Name
Port P70
Functions
At reset R W
0
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
1
0
Po
ng is arranged for these bits. When these
are read out, the contents are undefined.
5
6
7
0
0
0
0
0
0
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
Fig. 2.1.3 Structure of port P7
38C3 Group User’s Manual
2-3
APPLICATION
2.1 I/O port
Port P0 direction register, Port P1 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 direction register (P0D: address 0116
Port P1 direction register (P1D: address 0316
)
)
b
0
Name
Ports P0/P1
direction register
Functions
At reset R W
0
✕
0 : All bits of ports P0/P1
input mode
1 : All bits of ports P0/P1
output mode
1
2
3
4
5
6
7
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
0
0
0
0
0
0
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
0
Note: Ports P0 and P1 are switched to input by each port.
When b0 of corresponding port direcr is set to “0”, all
8 bits of port become input port. Wcorresponding port
direction register is set to “1”, aort become output
port. Nothing is arranged for port P0 and port P1
direction registers. These isabled bits.
Fig. 2.1.4 Structure of Port P0 direction register an1 direction register
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Poregister (i = 2, 4, 5, 6, 8)
ses 0516, 0916, 0B16, 0D16, 1116
)
Name
Port Pi direction
register
Functions
At reset R W
0
0 : Port Pi
0
input mode
output mode
1 : Port Pi
0
0 : Port Pi
1 : Port Pi
(Note)
1
input mode
output mode
0
1
1
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
0
0
0
0
0
0
2
3
4
5
6
7
0 : Port Pi
1 : Port Pi
3
3
input mode
output mode
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
input mode
output mode
0 : Port Pi
1 : Port Pi
7
7
input mode
output mode
Note: Bit 1 of the port P5 direction register (address 0B16) does not have
direction register function, because P5 is an input port. When writing to
1
bit 1 of the port P5 direction register, write “0” to the bit.
Fig. 2.1.5 Structure of Port Pi direction register (i = 2, 4, 5, 6, 8)
38C3 Group User’s Manual
2-4
APPLICATION
2.1 I/O port
Port P7 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P7 direction register
(P7D: address 0F16
)
b
0
Name
Port P7 direction
register
Functions
At reset R W
0 : Port P7
0
0
input mode
output mode
0
✕
1 : Port P7
0 : Port P7
1 : Port P7
1
1
input mode
output mode
0
✕
1
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
0
0
0
0
0
0
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
2
3
4
5
6
7
Fig. 2.1.6 Structure of Port P7 direction register
PULL register A
b7 b6 b5 b4 b3 b2 b1 b0
PULL register A
(PULLA: address 161
b
0
Na
Functions
0: No pull-down control
1: Pull-down control
At reset R W
1
Port P0
pull-ol
P
control
2 –P2
down control
1
1
1
0: No pull-down control
1: Pull-down control
7
1
0: No pull-down control
1: Pull-down control
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
Port P7
0
, P7
pull-up control
Port P8 –P8
pull-up control
1
0: No pull-up control
1: Pull-up control
0
0
4
5
6
0
7
0: No pull-up control
1: Pull-up control
0
0
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
7
Note: The pin which is set to output port is cut off from pull-up control.
Fig. 2.1.7 Structure of PULL register A
38C3 Group User’s Manual
2-5
APPLICATION
2.1 I/O port
PULL register B
b7 b6 b5 b4 b3 b2 b1 b0
PULL register B
(PULLB: address 1716
)
b
0
Name
Functions
0: No pull-up control
1: Pull-up control
At reset R W
0
Port P40–P43
pull-up control
Port P44–P47
pull-up control
Port P50, P52, P53
pull-up control
Port P54–P57
pull-up control
Port P60–P63
pull-up control
Port P64–P67
pull-up control
0
0
0
0: No pull-up control
1: Pull-up control
1
2
3
4
5
6
0: No pull-up control
1: Pull-up control
0: No pull-up control
1: Pull-up control
0: No pull-up control
1: Pull-up control
0
0
0: No pull-up control
1: Pull-up control
0
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Nothing is arranged for this bit. This is
disabled bit. When this bit is read o
contents are “0”.
7
Note: The pin which is set to outpt off from pull-up control.
Fig. 2.1.8 Structure of PULL register B
Port P8 output selection register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8 outpuister (P8SEL: address 1816
)
b
utput
on register
Functions
At reset R W
0
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
0
0
0
0
0
0
2
3
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
4
5
6
7
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
Fig. 2.1.9 Structure of Port P8 output selection register
38C3 Group User’s Manual
2-6
APPLICATION
2.1 I/O port
2.1.3 Terminate unused pins
Table 2.1.1 Termination of unused pins
Pins
Termination
P3
Open at “H” output state.
P0, P1, P2, P4, • Set to the input mode and connect each to VCC or VSS through a resistor of 1 kΩ to
P5
0
, P5
2
–P5
7
, P6, 10 kΩ.
• Set to the output mode and open at “L” or “H” output state.
P7, P8
P5
VL
1
1
Connect to VCC or VSS through a resistor of 1 kΩ to 10 kΩ.
–VL
3
Connect to Vss (GND).
COM
0
–COM
3
Open
V
X
REF
Open
OUT
Open (only when using external clock)
Connect to VSS (GND).
AVSS
38C3 Group User’s Manual
2-7
APPLICATION
2.1 I/O port
2.1.4 Notes on I/O port
(1) Notes in standby state
In standby state]1 for low-power dissipation, do not make input levels of an input port and an I/O port
“undefined”.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
l Reason
The potential which is input to the input buffer in a microcomputer table in the state that input
levels of a input port and an I/O port are “undefined”. This mpower source current.
]1 standby state: stop mode by executing STP instructi
wait mode by executing WIT instru
(2) Modifying port latch of I/O port with bit managuction
When the port latch of an I/O port is modified it managing instruction]2, the value of the
unspecified bit may be changed.
l Reason
The bit managing instructions are rfy-write form instructions for reading and writing data
by a byte unit. Accordingly, whenstructions are executed on a bit of the port latch of an
I/O port, the following is exeall bits of the port latch.
•As for bit which is set for rt:
The pin state is read iU, and is written to this bit after bit managing.
•As for bit which is sput port:
The bit value is re CPU, and is written to this bit after bit managing.
Note the following
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
]2 Bit managing instructions: SEB and CLB instructions
(3) Pull-up/Pull-down control
When each port which has built-in pull-up/pull-down resistor (P0, P1, P2, P4, P5
0
, P5
2
–P5 , P6, P7,
7
P8) is set to output port, pull-up/pull-down control of corresponding port become invalid. (Pull-up/Pull-
down cannot be set.)
l Reason
Pull-up control is valid only when each direction register is set to the input mode.
38C3 Group User’s Manual
2-8
APPLICATION
2.1 I/O port
2.1.5 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pin INT or others, select the VCC
pin or the VSS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the
I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the ial status remains until the
mode of the ports is switched over to the output mode by tam after reset. Thus, the
potential at these pins is undefined and the power sourct may increase in the input
mode. With regard to an effects on the system, thoroughsystem evaluation on the user
side.
• Since the direction register setup may be changed of a program runaway or noise, set
direction registers by program periodically to ine reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current rease depending on the first-stage circuit.
• An effect due to noise asily produced as compared with proper termination ➁ and
➂ shown on the abo
➁ I/O ports :
When setting for mode, do not connect to VCC or VSS directly.
● Reason
If the direction rgister setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and VCC (or VSS).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
38C3 Group User’s Manual
2-9
APPLICATION
2.2 Timer
2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.2.1 Memory map
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer 5 (T5)
Timer 6 (T6)
002016
002116
002216
002316
002416
002516
Timer 6 PWM register (T6PWM)
Timer 12 mode register (T12M
Timer 34 mode register (T
Timer 56 mode registe)
002716
002816
002916
002A16
Timer A registerder) (TAL)
Timer A regh-order) (TAH)
Compaer (low-order) (CONAL)
Cogister (high-order) (CONAH)
mode register (TAM)
002C16
002D16
002E16
002F16
003016
0031
er A control register (TACON)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
003C16
003D16
003E16
003F16
Fig. 2.2.1 Memory map of registers relevant to timers
38C3 Group User’s Manual
2-10
APPLICATION
2.2 Timer
2.2.2 Relevant registers
(1) 8-bit timer
Timer i
b7 b6 b5 b4 b3 b2 b1 b0
Timer i (i = 1, 3, 4, 5, 6)
(Ti: addresses 2016, 2216, 2316, 2416, 2516
)
b
Functions
• Set timer i count value.
• The value set in this register is written to both
the timer i and the timer i latch at one time.
• When the timer i is read out, the count value
of the timer i is read out.
At reset R W
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
Fig. 2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6)
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: addre
b
Functions
At reset R W
0
5
6
7
1
0
0
0
0
0
0
0
r 2 count value.
value set in this register is written to both
e timer 2 and the timer 2 latch at one time.
When the timer 2 is read out, the count value
of the timer 2 is read out.
Fig. 2.2.3 Structure of Timer 2
38C3 Group User’s Manual
2-11
APPLICATION
2.2 Timer
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 6 PWM register
(T6PWM: address 2716
)
b
Functions
At reset R W
• In timer 6 PWM1 mode
Undefined
0
1
2
3
4
“L” level width of PWM rectangular waveform is set.
• Duty of PWM rectangular waveform: n/(n + m)
Period: (n + m) × ts
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
n = timer 6 set value
m = timer 6 PWM register set value
ts = timer 6 count source period
At n = 0, all PWM output “L”.
At m = 0, all PWM output “H”.
(However, n = 0 has priority.)
5
6
• Selection of timer 6 PWM
Set “1” to the timer 6 operation mode sele
1 mode
7
Fig. 2.2.4 Structure of Timer 6 PWM register
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer ister
(T12816)
Name
mer 1 count stop
bit
Functions
0: Count operation
1: Count stop
At reset R W
0
Timer 2 count stop
bit
Timer 1 count
source selection
bits
0: Count operation
1: Count stop
0
0
0
0
1
2
3
4
b3 b2
0 0: f(XIN)/16 or f(XCIN)/16
0 1: f(XCIN)
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/128 or f(XCIN)/128
b5 b4
0 0: Timer 1 underflow
0 1: f(XCIN)
Timer 2 count
source selection
bits
1 0: External count input
CNTR0
0
5
1 1: Not available
0: I/O port
1: Timer 1 output
Timer 1 output
selection bit (P41)
0
0
6
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Fig. 2.2.5 Structure of Timer 12 mode register
38C3 Group User’s Manual
2-12
APPLICATION
2.2 Timer
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register
(T34M: address 2916
)
b
0
Name
Timer 3 count stop
bit
Functions
0: Count operation
1: Count stop
At reset R W
0
Timer 4 count stop
bit
Timer 3 count
source selection
bits
0: Count operation
1: Count stop
0
0
1
2
3
4
b3 b2
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 2 underflow
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/128 or f(XCIN)/128
b5 b4
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 3 underflo
1 0: External coun
Timer 4 count
source selection
bits
0
0
5
CNTR
1
1 1: Not avail
0: I/O port
1: Timer
Timer 3 output
selection bit (P42)
0
0
6
7
Nothing is arranged for thia write
disabled bit. When this ut, the
contents are “0”.
Fig. 2.2.6 Structure of Timer 34 mode register
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
mode register
: address 2A16)
b
0
Name
Timer 5 count stop
Functions
0: Count operation
1: Count stop
At reset R W
0
bit
Timer 6 count stop
bit
Timer 5 count
0: Count operation
1: Count stop
0
0
0
0
0
0
1
2
3
4
0: f(XIN)/16 or f(XCIN)/16
1: Timer 4 underflow
source selection bit
Timer 6 operation
mode selection bit
0: Timer mode
1: PWM mode
b5 b4
Timer 6 count
source selection
bits
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 5 underflow
1 0: Timer 4 underflow
1 1: Not available
0: I/O port
1: Timer 6 output
5
6
Timer 6 (PWM)
output selection bit
(P52)
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
7
Fig. 2.2.7 Structure of Timer 56 mode register
38C3 Group User’s Manual
2-13
APPLICATION
2.2 Timer
(2) 16-bit timer
Timer A register (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer A register (low-order, high-order)
(TAL, TAH: addresses 2C16, 2D16
)
b
Functions
At reset R W
• Set timer A count value.
1
1
1
1
1
1
1
1
0
1
2
3
• When the timer A write control bit of the timer
A mode register is “0”, the value is written to
timer A and the latch at one time.
When the timer A write control bit of the timer
A mode register is “1”, the value is written only
to the latch.
4
5
6
7
• The timer A count value is read out by
this register.
Notes 1: When reading and writinghem to both the high-
order and low-order b
2: Read both registerTAH and TAL following.
3: Write both regisr of TAL and TAH following.
4: Do not read brs during a write, and do not write to
both regisa read.
Fig. 2.2.8 Structure of Timer A register (lohigh-order)
Compare register (lohigh-order)
b7 b6 b5 b4 b3 b2 b1
mpare register (low-order, high-order)
CONAL, CONAH: addresses 2E16, 2F16
)
b
Functions
At reset R W
• Set compare register value.
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Note: Write registers in order of CONAH, CONAL, TAL, and TAH
following.
Fig. 2.2.9 Structure of Compare register (low-order, high-order)
38C3 Group User’s Manual
2-14
APPLICATION
2.2 Timer
Timer A mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer A mode register
(TAM: address 3016
)
b
0
Name
Functions
At reset R W
0
b1b0
Timer A operating
mode bits
0 0: Timer mode
0 1: Pulse output mode
1 0: IGBT output mode
1 1: PWM mode
1
2
0
0
Timer A write control
bit
0: Write data to both timer
latch and timer
1: Write data to timer latch
b4b3
Timer A count source
selection bits
3
4
5
6
7
0
0
0
0
0
0 0: f(XIN
)
0 1: f(XIN)/2
1 0: f(XIN)/4
1 1: f(XIN)/8
Timer A output active
edge switch bit
0: Output starts wit
1: Output starts l
Timer A count stop bit 0: Count op
1: Count
Timer A output
selection bit (P5
0: I/O
1: ut
0)
Fig. 2.2.10 Structure of Timer A mode register
Timer A control register
b7 b6 b5 b4 b3 b2 b1 b0
Tiregister
dress 3116
)
Name
Functions
At reset R W
0
Noise filter sampling
clock selection bit
0: f(XIN)/2
1: f(XIN)/4
b2b1
1
2
3
0
0
0
0
External trigger delay
time selection bits
0 0: No delay
0 1: (4/f(XIN))µs
1 0: (8/f(XIN))µs
1 1: (16/f(XIN))µs
Timer A output control
0: Not used
1: INT1 interrupt used
bit 1 (P5
6)
Timer A output control
bit 2 (P57)
0: Not used
1: INT2 interrupt used
4
0
0
0
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
5
6
7
Fig. 2.2.11 Structure of Timer A control register
38C3 Group User’s Manual
2-15
APPLICATION
2.2 Timer
(3) 8-bit timer, 16-bit timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16
)
b
0
Name
interrupt
request bit
Functions
At reset R W
INT
0
✽
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
0
0 : No interrupt request
issued
1 : Interrupt request issued
INT
1
interrupt
request bit
1
0 : No interrupt request
issued
1 : Interrupt request issued
2 INT
request bit
2 interrupt
0 : No interrupt request
issued
1 : Interrupt reques
3
4
5
6
7
0 : No interrupt
issued
1 : Interrupsued
Serial I/O interrupt
request bit
Timer A interrupt
request bit
0 : No quest
i
1 equest issued
Timer 1 interrupt
request bit
errupt request
ed
terrupt request issued
Timer 2 inte
request
: No interrupt request
issued
1 : Interrupt request issued
Timpt
0 : No interrupt request
issued
1 : Interrupt request issued
be set by software, but “1” cannot be set.
Fig. 2.2.12 Structure of Interuest register 1
38C3 Group User’s Manual
2-16
APPLICATION
2.2 Timer
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16
)
b
0
Name
Timer 4 interrupt
request bit
Timer 5 interrupt
request bit
Timer 6 interrupt
request bit
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
0
0 : No interrupt request issued
1 : Interrupt request issued
1
2
3
4
5
6
7
0 : No interrupt request issued
1 : Interrupt request issued
CNTR interrupt
0
0 : No interrupt request issued
1 : Interrupt request issued
request bit
CNTR1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issu
Key input interrupt 0 : No interrupt request
request bit
1 : Interrupt reque
AD conversion
interrupt request bit
Nothing is arranged for this bit. Th
disabled bit. When this bit is reontents
are “0”.
0 : No interrupt rd
1 : Interrupt red
✽: “0” can be set by softwcannot be set.
Fig. 2.2.13 Structure of Interrupt request regis
38C3 Group User’s Manual
2-17
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16
)
b
0
Name
Functions
At reset R W
0
INT
0
interrupt
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
1 INT
interrupt
enable bit
0
1
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
2 INT
2
interrupt
enable bit
Serial I/O interrupt
enable bit
Timer A interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
3
4
Timer 1 interrupt
enable bit
0 : Interrupt disab
1 : Interrupt en
5
6
7
Timer 2 interrupt
enable bit
0 : Interrupt
1 : Interru
0
0
Timer 3 interrupt
enable bit
0 : Intled
1 : Iabled
Fig. 2.2.14 Structure of Interrupt control register
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
ntrol register 2
: address 3F16
)
0
Name
Timer 4 interrupt
enable bit
Functions
At reset R W
0
0 : Interrupt disabled
1 : Interrupt enabled
Timer 5 interrupt
enable bit
Timer 6 interrupt
enable bit
0
0
0
0
0
0
0
1
2
3
4
5
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
CNTR
enable bit
CNTR interrupt
0
interrupt
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
1
enable bit
Key input interrupt
enable bit
0 : interrupt disabled
1 : Interrupt enabled
6 AD conversion
interrupt enable bit
7
0 : interrupt disabled
1 : Interrupt enabled
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
Fig. 2.2.15 Structure of Interrupt control register 2
38C3 Group User’s Manual
2-18
APPLICATION
2.2 Timer
2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of event interval (Timer 1 to Timer 6, Timer A: timer mode)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs.
<Use>
•Generating of an output signal timing
•Generating of a wait time
[Function 2] Control of cyclic operation (Timer 1 to Timer 6, Timer A: timer mode)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generating of cyclic interrupts
•Clock function (measurement of 1 s); see “(2) Timer application eample 1”
•Control of a main routine cycle
[Function 3] Output of rectangular waveform
(Timer 1, Timer 3, Timer 6, Timer A: pulsmode)
The output level of the T1OUT pin, T3OUT pin, PWM pin pin is inverted each time the timer
1
underflows.
<Use>
•Piezoelectric buzzer output; see “(3) Timer n example 2”
•Generating of the remote control carrier s
[Function 4] Count of external pulse2, Timer 4)
External pulses input to the CNTR
event counter mode).
<Use>
TR pin are counted as the timer count source (in the
1
•Frequency measurement; Timer application example 3”
•Division of external pu
•Generating of interrupa cycle using external pulses as the count source; count of a reel pulse
[Function 5] OutWM signal (Timer 6)
“H” interval and “terval are specified, respectively, and the output of pulses from P52/PWM1
pin is repeated.
<Use>
•Control of electric volume
[Function 6] Output of IGBT control signal (Timer A: IGBT output mode)
The external signal which is input to INT pin is used as trigger, and the period and “H” interval
0
are specified, respectively, and the output of pulses from P50/TAOUT pin is repeated.
<Use>
•IGBT control of IH heat equipment; see “(5) Timer application example 4”
•IGBT control to magnetron
[Function 7] Output of PWM signal (Timer A: PWM mode)
The cycle and “H” interval are specified, respectively, and the output of pulses from P50/TAOUT pin
is repeated.
<Use>
•Control of electric volume
•IGBT control of IH heat equipment
38C3 Group User’s Manual
2-19
APPLICATION
2.2 Timer
(2) Timer application example 1: Clock function (measurement of 1 s)
Outline: The input clock is divided by the timer so that the clock can count up at 1 s intervals.
Specifications: •The clock f(XIN) = 4.19 MHz (222 Hz) is divided by the timer.
•The timer 3 interrupt request bit is checked in main routine, and if the interrupt
request is issued, the clock is counted up.
• The timer 1 interrupt occurs every 244 µs to execute processing of other interrupts.
Figure 2.2.16 shows the timers connection and setting of division ratios; Figure 2.2.17 shows the
relevant registers setting; Figure 2.2.18 shows the control procedure.
Timer 1 count
source selection bit
Timer 3 interrupt request bit
Timer 1
1/64
Timer 2
1/256
Timer 3
1/16
f(XIN
)
0/1
1/16
4.19 MHz
1 nd
0/1
244 µs
pt request issued
pt request issued
Timer 1 interrupt
request bit
Fig. 2.2.16 Timers connection and setting of divisio
38C3 Group User’s Manual
2-20
APPLICATION
2.2 Timer
Timer 12 mode register (address 2816
)
b7
0
b0
1
0
0 0 0 0 0
T12M
Timer 1 count stop; Clear to “0” when starting count.
Timer 2 count: In progress
Timer 1 count source: f(XIN)/16
Timer 2 count source: Timer 1’s underflow
Timer 1 output selection: I/O port
Timer 34 mode register (address 2916
)
b7
b0
T34M
0
0
0 1
0
Timer 3 count: In progress
Timer 3 count source: Timer 2’s unde
Timer 3 output selection: I/O port
Timer 1 (address 2016
)
b7
b0
T1
T2
T3
3F16
Timer 2 (address 2116
)
b0
b7
sion ratio – 1”.
63 (3F16), T2 = 255 (FF16), T3 = 15 (0F16) ]
FF16
Timer 3 (address 2216
)
b7
0F16
Interrupt register 1 (address 3E16
)
b7
b0
ICON1
0
0
1
Timer 1 interrupt: Enabled
Timer 2 interrupt: Disabled
Timer 3 interrupt: Disabled
Interrupt request register 1 (address 3C16
)
b7
b0
IREQ1
Timer 1 interrupt request (becomes “1” at 244 µs intervals)
Timer 2 interrupt request
Timer 3 interrupt request (becomes “1” at 1 s intervals)
Fig. 2.2.17 Relevant registers setting
38C3 Group User’s Manual
2-21
APPLICATION
2.2 Timer
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
T12M
T34M
(address 2816
(address 2916
)
)
00000001
00XX01X0
2
•Connection of Timers 1 to 3
2
•Setting of Interrupt request bits of Timers 1 to 3 to “0”
•Timer 1 interrupt enabled, Timers 2 and 3 interrupts disabled
IREQ1 (address 3C16
)
000XXXXX
001XXXXX
2
2
ICON1 (address 3E16
)
(address 2016
(address 2116
(address 2216
)
)
)
3F16
FF16
0F16
T1
T2
T3
•Setting “Division ratio – 1” to Timers 1 to 3
(address 2816), bit0
0
T12M
CLI
•Timer count start
•Interrupts enabled
Y
0
Clock is stopped ?
N
•Judgment ws not set or time is being set
ation that 1 sec. has passed
ck of Timer 3 interrupt request bit)
IREQ1 (address 3C16), bit7 ?
1
•Interrupt request bit cleared
(Clear it by software when not using the interrupt.)
0
IREQ1 (address 3C16), bit7
✽
Clock count
Second to
•Clock count up
Main processing
•Adjust the main processing so that all processing in the loop ✽will
be processed within 1 second period.
<Procedure for end of clock setting> (Note)
T2
T3
IREQ1
(address 2116
(address 2216
(address 3C16), bit7
)
)
FF16
0F16
0
•Set Timers again when starting clock from 0 second after
end of clock setting.
The procedure is Timer 2 setting followed by Timer 3 setting.
•Do not set Timer 1 again because Timer 1 is used to
generate the interrupt at 244 µs intervals.
Note : Perform procedure for end of clock setting only when end of
clock setting.
Fig. 2.2.18 Control procedure
38C3 Group User’s Manual
2-22
APPLICATION
2.2 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 4.19 MHz (222 Hz) into about
2 kHz (2048 Hz), is output from the P4 /T3OUT pin.
2
•The level of the P4
stops.
2
/T3OUT pin is fixed to “H” while a piezoelectric buzzer output
Figure 2.2.19 shows a peripheral circuit example, and Figure 2.2.20 shows the timers connection and
setting of division ratios. Figures 2.2.21 shows the relevant registers setting, and Figure 2.2.22
shows the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
T3OUT output
T3OUT
PiPiPi.....
244 µs 244 µs
Set a division ratio so thlow
output period of the ti244 µs.
38C3 Group
Fig. 2.2.19 Peripheral circuit example
count source
selection bit
Timer 3
1/64
Fixed
1/2
f(
4
T3OUT
1/16
Fig. 2.2.20 Timers connection and setting of division ratios
38C3 Group User’s Manual
2-23
APPLICATION
2.2 Timer
Timer 34 mode register (address 2916
)
b7
b0
T34M
0
1
0 0
0
Timer 3 count: In progress
Timer 3 count source: f(XIN)/16
Timer 3 output selection: Buzzer output in progress = “1”
Buzzer output stopped = “0”
Timer 3 (address 2216
)
b7
b0
Set “division ratio – 1”; 63 (3F16).
3F16
T3
Interrupt control register 1 (address 3E16
)
b7
b0
ICON1
0
Timer 3 interrupt: Disabled
Fig. 2.2.21 Relevant registers setting
RESET
bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
•Port state setting at buzzer output stopped; “H” level output
P4D
P4
(address 0916), bit
(address 0816),
ICON1 (address
0
•Timer 3 interrupt disabled
•T3OUT output stopped; Buzzer output stopped
T34M (addre
00XX00X0
3F16
2
T3
(ad
•Interrupts enabled
CLI
Main processing
•Processing buzzer request, generated during main
processing, in output unit
Output unit
Yes
Buzzer request ?
No
T34M
T3
(address 2916), bit 6
0
3F16
T34M (address 2916), bit 6
1
(address 2216
)
Start of piezoelectric buzzer output
Stop of piezoelectric buzzer
output
Fig. 2.2.22 Control procedure
38C3 Group User’s Manual
2-24
APPLICATION
2.2 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P5
•A reference value
4
/CNTR
1
pin with the timer.
Specifications: •The pulse is input to the P5
4
/CNTR
1
pin and counted by the timer 4.
•A count value of timer 4 is read out at about 2 ms intervals, the timer 1 interrupt
interval. When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid count.
Figure 2.2.23 shows the judgment method of valid/invalid of input pulses; Figure 2.2.24 shows the
relevant registers setting; Figure 2.2.25 shows the control procedure
@
@
@
@
@
@
@
@
@
@
@
@
Input pulse
71.4 µs or more
71.4 µs
50 µs
50 µs or less
(less than 14 kHz)
(14 kHz)
(20 kHz)
(20 kHz or more)
d
Invalid
Invalid
2 ms
71.4 µs
2 ms
50 µs
= 2
= 40 counts
Fig. 2.2.23 Judgment method/invalid of input pulses
38C3 Group User’s Manual
2-25
APPLICATION
2.2 Timer
Timer 12 mode register (address 2816
)
b7
b0
0
0
0 0
1
T12M
Timer 1 count stop; Clear to “0” when starting count.
Timer 1 count source: f(XIN)/16
Timer 1 output selection: I/O port
Timer 34 mode register (address 2916
)
b7
b0
0
1
0
0
T34M
Timer 4 count: In progress
Timer 4 count source: External count input CNTR
1
Timer 1 (address 2016
)
b7
b0
Set “division ratio – 1”;
T1
T4
3F16
Timer 4 (address 2316
)
b0
b7
Set 255 (efore counting pulses.
(After a e has passed, the number of
inpuecreased from this value.)
FF16
Interrupt control registe3E16
)
b7
ICON1
1
Timer 1 interrupt: Enabled
Intetrol register 2 (address 3F16
)
b7
b0
0
ICON2
Timer 4 interrupt: Disabled
Interrupt request register 2 (address 3D16
)
b7
b0
IREQ2
0
Timer 4 interrupt request
( “1” of this bit when reading the count value
indicates the 256 or more pulses input in the
condition of Timer 4 = 255)
Fig. 2.2.24 Relevant registers setting
38C3 Group User’s Manual
2-26
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
RESET
Initialization
SEI
•All interrupts disabled
00XX00X1
3F16
0X10XX0X
FF16
1
0
2
•Set division ratio so that Timer 1 interrupt will occur at 244 µs intervals.
(address 2816
(address 2016
(address 2916
(address 2316
(address 3E16), bit 5
(address 3F16), bit 0
)
)
)
)
T12M
T1
T34M
T4
ICON1
ICON2
2
•External pulses input from CNTR
•Setting Timer 4 count value
•Timer 1 interrupt enabled
•Timer 4 interrupt disabled
1 pin selected as Timer 4’s count source
T12M (address 2816), bit 0
CLI
0
•Timer 1 count start
•Interrupts enabled
Timer 1 interrupt process routine
1/8
•Set so that pulse juds will be performed once each time
Timer 1 interrupt os, at 2 ms intervals.
CLT (Note 1)
CLD (Note 2)
Noteing Index X mode flag (T)
using Decimal mode flag (D)
Push registers to stack
isters used in interrupt process routine
1
Processing as out of range when the count value is 256 or more
IREQ2 (address 3D16), bit 0 ?
•Count value read
•Storing count value into Accumulator (A)
(A)
T4 (a
In range
214 < (A) < 28
•Compare the read value with
reference value.
•Store the comparison result to flag Fpulse.
Out of range
0
1
Fpulse
Fpulse
•Initialization of counter value
•Timer 4 interrupt request bit cleared
T4
(address 2316
)
FF16
0
IREQ2 (address 3D16), bit 0
Process judgment result
Pop registers
•Popping registers pushed to stack
RTI
Fig. 2.2.25 Control procedure
38C3 Group User’s Manual
2-27
APPLICATION
2.2 Timer
(5) Timer application example 4: Output of IGBT control signal
Outline: Synchronized variable PWM signal is output in “H” term.
When a signal is input to INT pin before timer underflow during “L” output, timer restarts.
0
Specifications: •The signal, of which “H” level width is 5 µs and cycle is 20 µs, is output from the
P5
However, if “H” is input to INT
0
/TAOUT pin.
0
pin during “L” output, timer restarts from “H” output.
<Example>
When f(XIN) = 8 MHz, the count source is 125 ns.
Figure 2.2.26 shows the timers connection and setting of division ratio; Figure 2.2.27 shows the
relevant registers setting; Figure 2.2.28 shows the control procedure.
Timer A count source
selection bit
Tirupt
it
Timer A
1/160
1/1
A restart
f(XIN) = 8 MHz
20 µs
125 ns
Fig. 2.2.26 Timers connection and setting of divisio
38C3 Group User’s Manual
2-28
APPLICATION
2.2 Timer
Timer A mode register (address 3016)
b7
b0
TAM
1
1
0 0 0 1 1
0
IGBT output mode
Writing of latch only
Timer A count source: f(XIN)
Timer A output active edge: Starting from “L” output ✽1
Timer A count stop; Clear to “0” when count starts
Timer A output selection: Timer A output
Timer A control register (address 3116)
b7
b0
TACON
0 0
0
Noise filter: f(XIN)/2
External trigger delayed: No delay
Compare register (low-order) (address 2E16)
b7
b0
7716
CONAL
CONAH
(007716)” before start of timer A.
Compare register (high-order) (address 2F16)
b7
b0
0016
Timer A register (low-order) (address
b7
b0
TAL
TAH
9F16
Timer A register (high-orde2D16)
Set “159 (009F16)” before start of timer A.
b7
b0
0016
Interrupt contro(address 3E16)
b7
ICON1
IREQ1
0
0
INT0 interrupt: Disabled
Timer A interrupt: Disabled
Interrupt request register 1 (address 3C16)
b7
b0
Timer A interrupt request (becomes “1” when Timer A underflows) ✽2
✽1 Use this bit with “0” (start from “L” output) in the IGBT output mode.
✽2 This bit becomes “1” even when a signal is input from the INT0 pin in the IGBT output mode.
Fig. 2.2.27 Relevant registers setting
38C3 Group User’s Manual
2-29
APPLICATION
2.2 Timer
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
•All interrupts disabled
•Timer A: IGBT output mode
•Noise filter: f(XIN); External trigger delayed: No delay
•Setting compare register value
TAM
(address 3016)
110001102
XXXXX0002
7716
0016
9F16
TACON (address 3116)
CONAL (address 2E16)
CONAH (address 2F16)
TAL
TAH
“H” width 5 µs
[
]
Cycle 20 µs setting
•Setting timer A count value
(address 2C16)
(address 2D16)
(address 3E16)
0016
XXX0XXX02
•Timer A, INT0 interrupt: Disabled
ICON1
•Interrupts enabled
•Timer A count sta
CLI
TAM
(address 3016), bit 6
0
009F16
007716
000016
P50/TAOUT
Timer A start
c
regi
Timer A
underflow
Input from
INT pin
0
Fig. 2.2.28 Control procedure
38C3 Group User’s Manual
2-30
APPLICATION
2.2 Timer
2.2.4 Notes on timer A (PWM mode and IGBT output mode)
(1) When timer starts first or last value of compare register is “000016
”
After “L” level (timer A output active edge switch bit is “0”; when starting from “L” output) is output
during 2 cycles (until timer underflows two times), PWM output or IGBT output starts.
Reason: When data is written to timer A and compare register, value of timer A and value of
compare register are renewed at timer underflow. In case of this, compare register value
and timer value are compared before renewal, so that they are judged to be equal, and
TAOUT output becomes “L”. (Timer A output active edge switch bit = “0”: when starting from
“L” output)
Timer A underflow should cause “H” output, but the match have the priority. (see “Figure
2.2.29”)
Compare register value is
“000016
Compare register value is value which is written t ➀
”
(last value or initial value)
➀
Timer A start
Timer A underflow
Timer
Timer A underflow
Timer A value
compare register value
writing
Fig. 2.2.29 PWM output and IGBT output (1)
(2) When compare register is set to (last value is except “000016”)
Next 1 cycle of the cycle in whiwritten to timer A and compare register is output “H”, and
“L” is output from the next cyr A output active edge switch bit = “0”: when starting from “L”
output)
(see “Figure 2.2.30”)
Compare register value is
last value
Compare register value is “000016”
Timer A underflow
Timer A underflow
Timer A underflow
Timer A underflow
Timer A value
compare register value
writing
Fig. 2.2.30 PWM output and IGBT output (2)
38C3 Group User’s Manual
2-31
APPLICATION
2.2 Timer
(3) When timer A and compare register have same value
TAOUT output becomes “H” with underflow immediately after data is written to timer A and compare
register. TAOUT output becomes “L” when timer A is reloaded and the value matches with compare
register. This “H” output width becomes 1 count of timer A count source. (timer A output active edge
switch bit =“0”: when starting from “L” output) (see “Figure 2.2.31”)
Timer A count source
Timer A value–compare register value
1 count width
Timer A underflow
Timer A value
Timer A underflow
compare register value
writing
Fig. 2.2.31 PWM output and IGBT output (3)
38C3 Group User’s Manual
2-32
APPLICATION
2.3 Serial I/O
2.3 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the serial I/O.
2.3.1 Memory map
Serial I/O control register 1 (SIOCON1)
Serial I/O control register 2 (SIOCON2)
Serial I/O register (SIO)
001916
001A16
001B16
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
003C16
003D16
003E16
Fig. 2.3.1 Memory map of registers relevant to Serial
2.3.2 Relevant registers
Serial I/O control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Seol register 1
address 1916)
Name
Internal
synchronous clock
selection bits
Functions
At reset R W
0
b2b1b0
0 0 0: f(XIN)/8 or f(XCIN)/8
0 0 1: f(XIN)/16 or f(XCIN)/16
0 1 0: f(XIN)/32 or f(XCIN)/32
0 1 1: f(XIN)/64 or f(XCIN)/64
1 1 0: f(XIN)/128 or f(XCIN)/128
1 1 1: f(XIN)/256 or f(XCIN)/256
0
0
0
1
2
3
Serial I/O port
selection bit
0: I/O port
1: SOUT, SCLK1, SCLK2
(P4
RDY output
selection bit (P4
0, P45, P4
6)
signal pin
S
0: I/O port
1: SRDY signal pin
0
0
0
0
4
5
6
7)
Transfer direction
selection bit
0: LSB first
1: MSB first
0: External clock
1: Internal clock
Synchronous clock
selection bit
P-channel output
disable bit
0: CMOS output
7
(in output mode)
(P40, P45, P46)
1: N-channel open-drain
output (in output mode)
Fig. 2.3.2 Structure of Serial I/O control register 1
38C3 Group User’s Manual
2-33
APPLICATION
2.3 Serial I/O
Serial I/O control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register 2
(SIOCON2: address 1A16
)
b
0
Name
Functions
At reset R W
0: SCLK1
1: SCLK2
0
Synchronous clock
output pin selection
bit
1
2
3
4
5
6
7
✕
✕
✕
✕
✕
✕
✕
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
0
0
0
0
0
0
Fig. 2.3.3 Structure of Serial I/O control register 2
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16
)
b
0
Name
inter
request
Functions
At reset R W
INT
0
✽
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
0
0 : No interrupt request
issued
1 : Interrupt request issued
I
t
t
1
0 : No interrupt request
issued
1 : Interrupt request issued
equest bit
2 interrupt
0 : No interrupt request
issued
1 : Interrupt request issued
3
4
5
6
7
0 : No interrupt request
issued
1 : Interrupt request issued
Serial I/O interrupt
request bit
Timer A interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.3.4 Structure of Interrupt request register 1
38C3 Group User’s Manual
2-34
APPLICATION
2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16
)
b
0
Name
Functions
At reset R W
0
INT
0
interrupt
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
1 INT
interrupt
enable bit
0
1
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
2 INT
2
interrupt
enable bit
Serial I/O interrupt
enable bit
Timer A interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
3
4
Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enable
5
6
7
Timer 2 interrupt
enable bit
0 : Interrupt disa
1 : Interrupt e
0
0
Timer 3 interrupt
enable bit
0 : Interrup
1 : Interd
Fig. 2.3.5 Structure of Interrupt control register
38C3 Group User’s Manual
2-35
APPLICATION
2.3 Serial I/O
2.3.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.6 shows connection examples with peripheral ICs equipped with the CS pin.
(1) Only transmission
(2) Transmission and reception
(Using SIN pin as I/O port)
Port
CS
Port
CS
S
CLK1
CLK
DATA
S
CLK1
OUT
IN
CLK
IN
OUT
S
S
OUT
Peripheral IC
38C3 group
38C3 group
Peripheral IC
(EEPROM etc.)
(3) Transmission and reception
(When connecting SIN1 with SOUT1
(When connecting IN with OUT in
peripheral IC)
)
ection of plural IC
Port
Port
CS
CS
S
CLK1
OUT
IN
S
CLK1
OUT
IN
CLK
IN
CLK
IN
S
S
S
S
OUT
OUT
Port
✽2
✽1
Peripheral IC 1
Peripheral IC
38C3 group
(EEPROM etc.)
38C3 group
CS
✽1: Select an N-channel open-drafor SOUT pin
output control.
✽2: Use the OUT pin of peC which is an N-
channel open-drain obecomes high impe-
dance during recei
CLK
IN
OUT
Peripheral IC 2
Note: “Port” means an output port controlled by software.
Fig. 2.3.6 Serial I/O connection examples (1)
38C3 Group User’s Manual
2-36
APPLICATION
2.3 Serial I/O
(2) Connection with microcomputer
Figure 2.3.7 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
S
CLK1
OUT
IN
CLK
IN
S
CLK1
OUT
IN
CLK
IN
S
S
S
OUT
S
OUT
38C3 group
Microcomputer
38C3 group
Microcomputer
(3) Using SRDY signal output function
(Selecting external clock)
(4) Using swion of CLK signal output
pins, Scting internal clock)
UT
IN
CLK2
S
RDY
CLK1
OUT
IN
RDY
CLK
IN
CLK
IN
S
S
S
OUT
S
S
OUT
Microcomputer
38C3 group
Microcomputer
38C3 group
CLK
IN
OUT
Peripheral IC
Fig. 2.3.7 Serial I/O connecion examples (2)
38C3 Group User’s Manual
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APPLICATION
2.3 Serial I/O
2.3.4 Serial I/O’s modes
38C3 Group can use clock synchronous serial I/O.
Figure 2.3.8 shows the serial I/O’s modes.
Select SCLK1 as synchronous clock output pin
Internal clock
Select SCLK2 as synchronous clock output pin
Output SRDY signal
Serial I/O
Clock synchronous serial I/O
External clock
Not output SRDY signal
Fig. 2.3.8 Serial I/O’s modes
2.3.5 Serial I/O application examples
(1) Communication (transmission/reception) using clock syns serial I/O
Outline : 2-byte data is transmitted and received, usclock synchronous serial I/O.
The SRDY signal is used for communication c
Figure 2.3.9 shows a connection diagram, and Fi10 shows a timing chart.
P5
5
/INT
0
S
S
S
RDY
CLK1
IN
S
CL
oup
38C3 group
Fig. 2.3.9 Connection diagram
Specifications : • Use of serial I/O in clock synchronous serial I/O
• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
• Use of SRDY (receivable signal)
• The reception side outputs the SRDY signal at intervals of 2 ms (generated by the
timer), and 2-byte data is transferred from the transmission side to the reception
side.
38C3 Group User’s Manual
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APPLICATION
2.3 Serial I/O
• • •
S
RDY
S
CLK1
• • •
• • •
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
S
OUT
2 ms
Fig. 2.3.10 Timing chart
38C3 Group User’s Manual
2-39
APPLICATION
2.3 Serial I/O
Figure 2.3.11 shows the registers setting relevant to the transmission side, and Figure 2.3.12 shows
the registers setting relevant to the reception side.
Transmission side
Serial I/O control register 1 (address 001916
)
SIOCON1
0 1
0 0 1 0 1 0
Internal synchronous clock: f(XIN)/32
S
S
OUT, SCLK1, SCLK2 selected
RDY output not used
LSB first
Internal clock
CMOS output
Serial I/O control register 2 (address 001A
0
SIOCON2
Ss clock output pin selection bit: SCLK1 selected
(“0” at reading)
Interrupt edge seister (address 003A16
)
INTEDGE
0
INT
0
falling edge active
Fig. 2.3.11 Registers setting relevant to transmission side
38C3 Group User’s Manual
2-40
APPLICATION
2.3 Serial I/O
Reception side
Serial I/O control register 1 (address 001916
)
SIOCON1
0
0
1
S
RDY output used
LSB first
External clock
Fig. 2.3.12 Registers setting relevant to reception side
Figure 2.3.13 shows a control procedure of the transmission side, and Figure 2.3.14 shows a control
procedure of the reception side.
RESET
● X: This bit is not used her“0” or “1” arbitrarily.
Initialization
SIOCON1 (address 001916
SIOCON2 (address 001A16
INTEDGE (address 003A16), bit 0
)
)
01001010
XXXXXXX0
0
2
Serial I/O
2
0
0
NT0 falling edge detection
IREQ1 (address 003C16), bit 0 ?
1
IREQ1 (address 003C16), bit
smission of the
st byte data
Transmission data write
SIO (address 001
Connection of completion of transmitting
(Serial I/O interrupt request flag)
IREQ1 (address 003C16), bit 3 ?
1
IREQ1 (address 003C16), bit 3
0
Transmission of the
second byte data
Transmission data write
SIO (address 001B16
)
Judgment of completion of transmitting
(Serial I/O interrupt request flag)
IREQ1 (address 003C16), bit 3 ?
1
Fig. 2.3.13 Control procedure of transmission side
38C3 Group User’s Manual
2-41
APPLICATION
2.3 Serial I/O
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SIOCON1 (address 001916
)
X0011XXX
2
• Serial I/O setting
0
0
0
• An interval of 2 ms generated by Timer.
• SRDY output
2ms has passed ?
1
SRDY signal is oriting data to
SIO (address 001B16
)
Dummy data
SIO.
When usint SRDY output
selectioof SIOCON1 to “1.”
• of completion of receiving
O interrupt request)
IREQ1 (address 003C16), bit 3 ?
1
Read out reception data from
• Reception of data
SIO (address 001B16
)
• Judgment of completion of receiving
(Serial I/O interrupt request)
IREQ1 (address 003
Read oudata from
• Reception of data
SIO (addreB16
)
Fig. 2.3.14 Control procedure of reception side
38C3 Group User’s Manual
2-42
APPLICATION
2.3 Serial I/O
(2) Output of serial data (control of peripheral IC)
Outline : Serial communication is performed, connecting port P5
7
with the CS pin of a peripheral IC.
Figure 2.3.15 shows a connection diagram, and Figure 2.3.16 shows a timing chart.
CS
P57
CS
CLK
S
CLK1
CLK
DATA
DATA
S
OUT
38C3 group
Peripheral IC
Fig. 2.3.15 Connection diagram
Specifications : • Use of serial I/O in clock synchronou/O
• Synchronous clock frequency : 12XIN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• Not use of serial I/O interrup
• Port P5
7
is connected with t(“L” active) of the peripheral IC for transmission
is controlled by software.
control; the output leveP5
7
CS
CLK
DATA
DO
0
DO
1
DO
2
DO
3
Fig. 2.3.16 Timing chart
38C3 Group User’s Manual
2-43
APPLICATION
2.3 Serial I/O
Figure 2.3.17 shows the relevant registers setting and Figure 2.3.18 shows the setting of transmission
data.
Serial I/O control register 1 (address 001916
)
0 1 0 0 1 0 1 0
SIOCON1
Synchronous clock: f(XIN)/32
S
S
OUT, SCLK1, SCLK2 signal pin
RDY output not used
LSB first
Internal clock
CMOS output
Serial I/O control register 2 (address 001
0
SIOCON2
us clock output pin: SCLK1
Interrupt control regisress 003E16
)
0
ICON1
Serial I/O interrupt: Disabled
request register 1 (address 003C16
0
)
IREQ
Serial I/O interrupt request cleared
Confirm transmission completion of 1-byte unit.
Fig. 2.3.17 Relevant registers setting
Serial I/O register (001B16
SIO
)
Set a transmission data.
Confirm that transmission of the previous data is
completed, where bit 3, the serial I/O interrupt
request bit of the interrupt request register, is “1”;
before writing data.
Fig. 2.3.18 Setting of transmission data
38C3 Group User’s Manual
2-44
APPLICATION
2.3 Serial I/O
Figure 2.3.19 shows a control procedure.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
Serial I/O setting
SIOCON1 (address 001916
)
01001010
2
SIOCON2 (address 001A16
)
XXXXXXX0
2
Serial I/O interrupt: Disabled
CS signal output level to “H” setting
CS signal output port setting
ICON1 (address 003E16), bit 3
P5 (address 000A16), bit 7
P5D (address 000B16), bit 7
0
1
1
P5 (address 000A16), bit 7
0
CS signal ou“L” setting
IREQ1 (address 003C16), bit 3
0
terrupt request bit to “0” setting
nsmission data write
Start of 1-byte data transmission)
Transmission dat
SIO (address 001B16
)
0
Judgment of completion of transmitting 1-byte
data
IREQ1 (address 003C16)
Use any of RAM area as a counter for counting
the number of transmitted bytes.
Judgment of completion of transmitting the target
number of bytes
N
All data ansmitted ?
Y
Returning CS signal output level to “H” when
transmission of the target number of bytes is
completed
P5 (address 000A16), bit 7
1
Fig. 2.3.19 Control procedure
38C3 Group User’s Manual
2-45
APPLICATION
2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.3.20 shows a connection diagram.
S
CLK1
S
S
S
CLK1
OUT
IN
S
IN
S
OUT
group
ve side)
38C3 group
(master side)
Fig. 2.3.20 Connection diagram
Specifications: • Synchronous clock fre131 kHz (f(XIN) = 4.19 MHz is divided by 32.)
• Byte cycle: 488 µs
• Number of bytes mission or reception : 8 bytes/block each
• Block transfer 6 ms
• Block trans3.5 ms
• Interval blocks : 12.5 ms
• Headiment time : 8 ms
• Traction : LSB first
Limitations of the fications:
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O interrupt
request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
38C3 Group User’s Manual
2-46
APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown in Figure 2.3.21. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjusment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 bytes) is received, the clock is ignored.
Figure 2.3.22 shows the relevant registers setting in the master unit and Figure 2.3.23 shows the
relevant registers setting in the slave unit.
D
0
D1
D
2
D
7
D
0
Byte cycle
Interval between blocks
Block transfer term
Block transfer cycle
Heading adjustme
Processing for hustment
Fig. 2.3.21 Timing chart
38C3 Group User’s Manual
2-47
APPLICATION
2.3 Serial I/O
Master unit
Serial I/O control register 1 (address 001916
0 1 0 0 1 0 1 0
)
SIOCON1
Synchronous clock : f(XIN)/32
S
S
OUT, SCLK1, SCLK2 signal pin
RDY output not used
LSB first
Internal clock
CMOS output
Serial I/O control register 2 (address 00
SIOCON2
0
chronous clock output pin: SCLK1
Fig. 2.3.22 Relevant registers setting in maste
Slave unit
ontrol register 1 (address 001916
0 0 1
)
SIOC
S
S
OUT, SCLK1, SCLK2 signal pin
RDY output not used
LSB first
Synchronous clock: External clock
CMOS output
Serial I/O control register 2 (address 001A16
0
)
SIOCON2
Synchronous clock input pin: SCLK1
Fig. 2.3.23 Relevant registers setting in slave unit
38C3 Group User’s Manual
2-48
APPLICATION
2.3 Serial I/O
Control procedure by software:
● Control in the master unit
After setting the relevant registers shown in Figure 2.3.22, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the serial I/O register.
To perform the communication in the timing shown in Figure 2.3.21, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O interrupt
request bit is set to “1,” or before the next transmission data is written to the serial I/O register.
Figure 2.3.24 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 488 µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
Note 1: When using the Index X mod
Note 2: When using the Decimal m).
Pushing the register used in the
processing routine into the sta
●
●
Generating a certterval by
using a timer otions
N
Within a block transfer
period?
Y
●
Check of the block interval counter and
determination to start a block transfer
Cointerval counter
Read a reception data
N
Y
Complete to transfer
a block?
Start a block transfer?
Y
N
Write the first transmission data
(first byte) in a block
Write a transmissio
●
Pop registers
RTI
Popping registers which is pushed to stack
Fig. 2.3.24 Control procedure of master unit
38C3 Group User’s Manual
2-49
APPLICATION
2.3 Serial I/O
● Control in the slave unit
After setting the relevant registers as shown in Figure 2.3.23, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O interrupt occurs each
time an 8-bit synchronous clock is received.
In the serial I/O interrupt processing routine, the data to be transmitted next is written to the serial
I/O register after the received data is read out.
However, if no serial I/O interrupt occurs for a certain time (heading adjustment time or more), the
following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the serial I/O register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.3.25 shows a control procedure of the slave unit using the serial I/O interrupt and any
timer interrupt (for heading adjustment).
Serial I/O reception interrupt
processing routine
Timer interrupt processing
routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
CLT (Note 1
CLD (Not
Push rk
●
●
Pushing the register used in
the interrupt processing
routine into the stack
Pushing the register used
in the interrupt processing
routine into the stack.
●
Confirmation of the received
byte counter to judge the
block transfer term
djustment
nter – 1
N
Within a block transfer
term?
Y
N
Heading adjustment
counter = 0?
Read a reception data
Y
Write the first transmission
data (first byte) in a block
A received byte counter +1
A received byte counter
0
N
A received byte
counter ≥ 8?
Y
●
Popping registers which is
pushed to stack
Pop registers
RTI
Write a transmission data
Write dummy data (FF16)
Initial
value
(Note 3)
Heading
adjustment
counter
●
Popping registers which is
pushed to stack
Pop registers
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
RTI
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set
8 as the initial value.
Fig. 2.3.25 Control procedure of slave unit
38C3 Group User’s Manual
2-50
APPLICATION
2.3 Serial I/O
2.3.6 Notes on serial I/O
(1) Selecting external synchronous clock
When an external synchronous clock is selected, the contents of serial I/O register are being shifted
continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control the clock
externally.
(2) Transmission data wiritng
When an external clock is used as the synchronous clock, write the transmit data to the serial I/O
shift register at “H” level of transfer clock input.
38C3 Group User’s Manual
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APPLICATION
2.4 LCD controller
2.4 LCD controller
This paragraph explains the registers setting method and the notes relevant to the LCD controller.
2.4.1 Memory map
Segment output enable register (SEG)
LCD mode register (LM)
003816
003916
Fig. 2.4.1 Memory map of registers relevant to LCD controller
38C3 Group User’s Manual
2-52
APPLICATION
2.4 LCD controller
2.4.2 Relevant registers
Segment output enable register
b7 b6 b5 b4 b3 b2 b1 b0
Segment output enable register
(SEG: address 3816
)
b
0
Name
Segment output
enable bit 0
Segment output
enable bit 1
Segment output
enable bit 2
Segment output
enable bit 3
Segment output
enable bit 4
Segment output
enable bit 5
Segment output
enable bit 6
Functions
–P2
1: Segment output SEG
At reset R W
0
0: I/O ports P2
0
3
0
–SEG
–SEG
3
7
0: I/O ports P2
4
–P2
7
0
0
0
0
0
0
0
1
2
3
4
1: Segment output SEG
4
0: I/O ports P0
0
–P0
3
1: Segment output SEG –SEG11
8
0: I/O ports P0
4
–P0
7
1: Segment output SEG12–S
0: I/O ports P1
0
–P1
3
1: Segment output SE
0: I/O ports P1
5
6
7
1: Segment ouEG23
0: Output
P3
3
1: SegmG24–SEG27
Segment output
enable bit 7
0: OP3
4–P3
7
1tput SEG28–SEG31
Fig. 2.4.2 Structure of Segment output enable
LCD mode register
b7 b6 b5 b4 b3 b2 b1 b0
e register
0
dress 3916
)
0
Name
Functions
At reset R W
0
b1b0
Duty ratio selection
bits
0 0: 1 (use COM
0 1: 2 (use COM
1 0: 3 (use COM
1 1: 4 (use COM
0
0
0
0
)
, COM
–COM
–COM
1)
2)
3)
1
2
3
0
0
0
Bias control bit
LCD enable bit
0: 1/3 bias
1: 1/2 bias
0: LCD OFF
1: LCD ON
4
5
0
0
Fix “0” to this bit.
LCD circuit divider
division ratio selection
bits
b6b5
0 0: Clock input
0 1: 2 division of clock input
1 0: 4 division of clock input
1 1: 8 division of clock input
6
7
0
0
0: f(XCIN)/32
1: f(XIN)/8192 (f(XCIN)/8192 in
low-speed mode)
LCDCK count source
selection bit (Note)
Note: LCDCK is a clock for a LCD timing controller.
Fig. 2.4.3 Structure of LCD mode register
38C3 Group User’s Manual
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APPLICATION
2.4 LCD controller
2.4.3 LCD controller application examples
Outline: A LCD panel display data by using the LCD controller.
’
AUTO
SLOW
PRINT
Fig. 2.4.4 LCD panel
Specifications: •Use of segment output SEG to SEG13
0
•Setting of port P1 to I/O port, setting of port P3 to
•Frame frequency = 61 Hz
•Duty ratio number = 4, Bias value = 1/3
Figure 2.4.5 shows the segment allocation example.
2
6
1
3
4
5
’
AUTO
SLOW
7
PRINT
Fig. 2.4.5 Segment allocation example
38C3 Group User’s Manual
2-54
APPLICATION
2.4 LCD controller
Setting of LCD display RAM:
7
6
5
4
3
2
1
0
Bit
Address
COM
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM0
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
SEG
SEG
SEG
SEG
SEG
1
3
5
7
9
SEG
SEG
SEG
SEG
SEG
0
2
4
6
8
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG10
SEG12
SEG14
SEG16
SEG1
SE
G26
SEG28
SEG30
Fig. 2.4.6 LCD display RAM map
a
7
6
4
3
2
1
0
Bit
b
c
g
f
COM
3
COM
1 COM0
COM
3
COM
2
COM
1
COM0
Address
004016
e
g
g
g
g
f
f
f
f
f
f
e
e
e
e
e
e
d
d
d
d
d
d
c
c
c
c
c
c
b
b
b
b
b
b
a
a
a
a
a
a
1
2
3
4
5
d
’
004116
004216
004316
004416
004516
004616
6
7
PRINT
SLOW AUTO
Fig. 2.4.7 LCD display RAM setting
38C3 Group User’s Manual
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APPLICATION
2.4 LCD controller
Figure 2.4.8 shows the relevant registers setting.
Segment output enable register (address 003816
)
SEG
0 0 0 0 1 1 1 1
Segment output: SEG
Segment output: SEG
0
4
–SEG
–SEG
3
7
Segment output: SEG
8
–SEG11
Segment output: SEG12–SEG15
I/O port: P1
I/O port: P1
0
–P1
3
4–P1
7
Output port: P3
Output port: P3
0
4
–P3
–P3
3
7
LCD mode register (address 003916
1 1 0 0 0 0 1 1
)
LM
4 (use COM
1/3 bias
0
–COM )
3
LCD OFF (after ta to LCDRAM, turn on)
Not used (A0”.)
4 (Note)
f(XIN)e)
Note: Frame frequency = division ratio
f(LCDCK) = counequency for LCDCK/LCD circuit division ratio
From the above frequency at f(XIN) = 8 MHz is as follows:
Frame fr{(8 ✕ 106/8192)/4}/4 61.035 Hz
Fig. 2.4.8 Relevant registesetting
38C3 Group User’s Manual
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APPLICATION
2.4 LCD controller
Control procedure: Figure 2.4.9 shows the control procedure of relevant registers to turn on all the LCD
display in Figure 2.4.4.
RESET
Initialization
CLT
CLD
SEI
•All interrupts disabled
•Setting of segment output/port
•Setting of LCD mode register
SEG
LM
(address 003816
(address 003916
)
)
00001111
11000011
2
2
•Setting of value to LCDRAM
(Set “1” to turn on bit and “0” to turn off bit.)
(address 004016
(address 004116
(address 004216
(address 004316
(address 004416
(address 004516
(address 004616
)
)
)
)
)
)
)
LCDRAM0
LCDRAM1
LCDRAM2
LCDRAM3
LCDRAM4
LCDRAM5
LCDRAM6
11111111
11111111
11111111
11111111
01111111
01111111
11111111
2
2
2
2
2
2
2
•LCD tu
1
(address 003916), bit 3
LM
•Ined
CLI
When switching LCD turn on
(turn off) segment
•Rewriting of bits corresponding to LCD turn on (turn off)
segments
LCDRAMX (address 004X16
)
XXX
Fig. 2.4.9 Control proce
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APPLICATION
2.4 LCD controller
2.4.4 Notes on LCD controller
●When switching from the high-speed or middle-speed mode to the low-speed mode, switch the mode in
the following order:
(1) 32 kHz oscillation selected (bit 4 of CPU mode register (address 003B16) = “1”)
(2) Count source for LCDCK = f(XCIN)/32 (bit 7 of LCD mode register (address 003916) = “0”)
(3) Internal system clock: XCIN-XCOUT selected (bit 7 of CPU mode register (address 003B16) = “1”)
(4) Main clock XIN–XOUT stopped (bit 5 of CPU mode register (address 003B16) = “1”)
Execute the setting (2) after the oscillation at 32 kHz (setting (1)) becomes completely stable.
●If the STP instruction is executed while the LCD is turned on by setting bit 3 of the LCD mode register
(address 003916) to “1”, a DC voltage is applied to the LCD. For this reason, do not execute the STP
instruction while the LCD is lighting.
●When the LCD is not used, open the segment and the common pins.
Connect VL1–VL3 to VSS
.
●For the following products, if the LCD enable bit of the LCD mode regbit 3 of address 003916) is
set to “0”, all LCDs cannot be turned off. To turn off all LCDs, set “0) to all corresponding LCD
display RAM.
Corresponding products: M38C34M6AXXXFP, M38CXXFP, M38C37ECAXXXFP,
M38C37ECMXXXFP, M38C3M38C37ECMFP, M38C37ECAFS,
M38C3ECMFS, M38C37RC37RMFS
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APPLICATION
2.5 A-D converter
2.5 A-D converter
This paragraph describes the setting method of A-D converter relevant registers, notes etc.
2.5.1 Memory map
Address
003216 A-D control register (ADCON)
003316
A-D conversion register (low-order) (ADL)
003416 A-D conversion register (high-order) (ADH)
003D16
003F16
Interrupt request register 2 (IREQ2)
Interrupt control register 2 (IC
Fig. 2.5.1 Memory map of A-D converter relevant re
2.5.2 Relevant registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
register
address 3216
)
0
Name
Analog input pin
selection bits
Functions
At reset R W
0
b2 b1 b0
0 0 0: P6
0 0 1: P6
0 1 0: P6
0 1 1: P6
1 0 0: P6
1 0 1: P6
1 1 0: P6
1 1 1: P6
0/AN
1/AN
2/AN
3/AN
4/AN
5/AN
6/AN
7/AN
0
1
2
3
4
5
6
7
1
0
0
2
3
4
Nothing is arranged for this bit. This is write
disabled bit. When this bit is read out, the
contents are “0”.
0
1
0: Conversion in progress
1: Conversion completed
AD conversion
completion bit
0
0
0
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
Fig. 2.5.2 Structure of A-D control register
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APPLICATION
2.5 A-D converter
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3316)
b
Functions
At reset R W
Undefined
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
These are A-D conversion result (low-order 2 bits)
stored bits. This is read exclusive register.
Undefined
Note: Do not read this register during A-D conversion.
Fig. 2.5.3 Structure of A-D conversion register (low-order)
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion regder)
(ADH: address 3
b
Functions
At reset R W
Undefined
0
1
2
7
Thiersion result (high-order 8 bits) stored
bad exclusive register.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Note: Do not read this register during A-D conversion.
Fig. 2.5.4 Structure of A-D conversion register (high-order)
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APPLICATION
2.5 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16
)
b
0
Name
Timer 4 interrupt
request bit
Timer 5 interrupt
request bit
Timer 6 interrupt
request bit
CNTR0 interrupt
request bit
CNTR1 interrupt
request bit
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
0
0 : No interrupt request issued
1 : Interrupt request issued
1
2
3
4
5
6
7
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issu
Key input interrupt 0 : No interrupt request
request bit
1 : Interrupt reques
AD conversion
interrupt request bit
Nothing is arranged for this bit. Th
disabled bit. When this bit is reontents
are “0”.
0 : No interrupt r
1 : Interrupt red
✽: “0” can be set by so“1” cannot be set.
Fig. 2.5.5 Structure of Interrupt request regis
Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
control register 2
2 : address 3F16)
b
0
Name
Timer 4 interrupt
enable bit
Functions
At reset R W
0
0 : Interrupt disabled
1 : Interrupt enabled
Timer 5 interrupt
enable bit
Timer 6 interrupt
enable bit
CNTR0 interrupt
enable bit
CNTR1 interrupt
enable bit
0
0
0
0
0
0
0
1
2
3
4
5
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
Key input interrupt
enable bit
0 : interrupt disabled
1 : Interrupt enabled
6 AD conversion
interrupt enable bit
7
0 : interrupt disabled
1 : Interrupt enabled
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
Fig. 2.5.6 Structure of Interrupt control register 2
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APPLICATION
2.5 A-D converter
2.5.3 A-D converter application examples
(1) Read-in of analog signal
Outline: The analog input voltage from a sensor is converted to digital values.
Figure 2.5.7 shows a connection diagram, and Figure 2.5.8 shows the setting of relevant registers.
P60
/AN
0
Sensor
38C3 Group
Fig. 2.5.7 Connection diagram
Specifications: •Conversion of analog input voltage input sor to digital values
•Use of P6 /AN pin as analog input pi
0
0
A-D control register (address 003216
)
ADCON
0
0 0 0
og input pin : P6
0
/AN selected
0
A-D conversion start
A-D conversi(high-order) (address 003416
(Read-only)
)
ADH
ADL
A result of A-D conversion is stored (Note).
A-D conversion register (low-order) (address 003316
(Read-only)
)
A result of A-D conversion is stored (Note).
Note: After bit 4 of ADCON is set to “1”, read out both registers in order of ADH (address
003416) and ADL (address 003316) following.
Fig. 2.5.8 Setting of relevant registers
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APPLICATION
2.5 A-D converter
Control procedure: A-D converter is started by performing register setting shown Figure 2.5.8.
Figure 2.5.9 shows the control procedure.
• P60/AN0 pin selected as analog input pin
• A-D conversion start
← 0002
← 0
ADCON (address 003216), bit 0–bit 2
ADCON (address 003216), bit 4
0
• Judgment of A-D cion completion
ADCON (address 003216), bit 4 ?
1
Read out ADH (address 003416)
• Reigh-order (b9–b2) conversion result
ead out of low-order (b1, b0) conversion result
Read out ADL (address 003316)
Fig. 2.5.9 Control procedure
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APPLICATION
2.5 A-D converter
2.5.4 Notes on A-D converter
(1) Analog input pin
■ Make the signal source impedance for analog input low, or equip an analog input pin with an
external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application
products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the VSS line.
● Reason
If the AVSS pin is opened, the microcomputer may have a cause of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a f the capacity will be lost if the clock
frequency is too low. Thus, make sure the followinan A-D conversion.
• f(XIN) is 500 kHz or more.
• Use clock divided by main clock (f(XIN)) as iystem clock.
• Do not execute the STP instruction and uction.
38C3 Group User’s Manual
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APPLICATION
2.6 ROM correct function
2.6 ROM correct function
This paragraph describes the setting method of ROM correct function relevant registers, notes etc.
2.6.1 Memory map
Address
005016
005116
ROM correct data 1
ROM correct data 2
ROM correct data 3
ROM correct data 4
005216
005316
005416
ROM correct data 5
ROM correct data 6
ROM correct data 7
ROM correct data 8
005516
005616
005716
0F0116 ROM correct enable register 1 e)
0F0216
ROM correct high-order addr1 (Note)
0F0316 ROM correct low-order ater 1 (Note)
0F0416 ROM correct high-orregister 2 (Note)
0F0516
ROM correct loess register 2 (Note)
0F0616 ROM correaddress register 3 (Note)
0F0716
0F0816
ROM cder address register 3 (Note)
ROgh-order address register 4 (Note)
0F0916 ct low-order address register 4 (Note)
orrect high-order address register 5 (Note)
OM correct low-order address register 5 (Note)
0F0
ROM correct high-order address register 6 (Note)
ROM correct low-order address register 6 (Note)
ROM correct high-order address register 7 (Note)
0FD16
0F0E16
0F0F16
ROM correct low-order address register 7 (Note)
ROM correct high-order address register 8 (Note)
ROM correct low-order address register 8 (Note)
0F1016
0F1116
Note: This register is valid only in mask ROM version.
Fig. 2.6.1 Memory map of ROM correct function relevant registers
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APPLICATION
2.6 ROM correct function
2.6.2 Relevant registers
ROM correct enable register 1
b7 b6 b5 b4 b3 b2 b1 b0
ROM correct enable register 1
(RC1: address 0F0116
)
b
0
Name
ROM correct
address 1 enable bit 1: Enabled
Functions
0: Disabled
At reset R W
0
ROM correct
0: Disabled
address 2 enable bit 1: Enabled
ROM correct
0
0
0
0
0
0
0
1
2
3
0: Disabled
address 3 enable bit 1: Enabled
ROM correct
0: Disabled
address 4 enable bit 1: Enabled
4 ROM correct
address 5 enable bit 1: Enabled
ROM correct
0: Disabled
0: Disabled
address 6 enable bit 1: Enabled
ROM correct
address 7 enable bit 1: En
ROM correct
address 8 enable bit
5
6
7
0: Disa
0:
Fig. 2.6.2 Structure of ROM correct enable re
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APPLICATION
2.6 ROM correct function
2.6.3 ROM correct function application examples
Outline: When the contents of ROM would be corrected, the contents of ROM can be changed artificially
by connecting E2PROM to the externals and storing the contents (correct address, correct data)
to the ROM correct function relevant registers.
CLK
P4
P4
P4
6
S
CLK1
CLK
OUT
CS
DATA
CS
4
SIN
7
P47
E2PROM
P51
P51
38C3 group
38C3 group
●When ROM correct is unnecessary
●When ROM correct is necessary
Fig. 2.6.3 Connection diagram
Specifications: ●If ROM correct is necessary, make P5
1
pull-up. If rect is unnecessary, make P5
1
pull-down.
●Use of serial I/O as communication with E
●Connection of clock and SCLK1, connectipin and P4
7
Port P4 direction register (ad
)
P4D
1
1
1
Set P44, P4
6
, P4 to output ports.
7
When ROM correct is unnece
When ROM correct is necessary
Port P4 (address 000
Serial I/O control register 1 (address 001916
)
P4
SIOCON1
0
0
0
1
0 1
Set “L” output as
termination of
unused pins
S
OUT, SCLK1, SCLK2
signal pins
I/O port
Internal clock
Serial I/O control register 2 (address 001A16
)
0
SIOCON2
S
CLK1
Port P4 (address 000816
)
P4
Set CS signal
to E2PROM
Fig. 2.6.4 Setting of relevant registers
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APPLICATION
2.6 ROM correct function
Control procedure:
RESET
Initialization
Setting of port direction register
“L” output as termination of unused pins
P4D (address 000916
)
11X1XXXX
00X0XXXX
2
2
P4 (address 000816
)
N
E2PROM is connected ?
(P5
1
= “H” ?)
Y
Setting of serial I/O
SIOCON1 (address 001916
SIOCON2 (address 001A16
)
)
X1X01XXX2
S
CLK1 selected
XXXXXXX0
2
CS signal out
1
P4 (address 000816), bit 7
Data corresponding to the following
registers, which have been set to
E2PROM beforehand, is read and the data
is stored to each register:
•ROM correct enable register 1
•ROM correct address registers 1–8
•ROM correct data 1–8
0
P4 (address 000816), bit 7
Main process
✽ (Note)
N
ROM correct is enabled ?
(RC1, X = “H” ?)
Y
ROM correct
address X
Correct data X
Note: ✽ shows the internal operation of microcomputer.
Fig. 2.6.5 Control procedure
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APPLICATION
2.7 Reset circuit
2.7 Reset circuit
____________
The reset state is caused by applying an “L” level to the RESET pin. After that, the reset state is released
____________
by applying an “H” level to the RESET pin, so that the program is executed in the middle-speed mode from
the contents of the reset vector address.
2.7.1 Connection example of reset IC
Figure 2.7.1 shows the example of power-on reset circuit. Figure 2.7.2 shows the system example which
switches to the RAM backup mode by detecting a drop of the system power source voltage with the INT
interrupt.
V
Power source
Output
M62022L
GND
ESET
Delay capacity
0.1µF
VSS
38C3 Group
Fig. 2.7.1 Example of power-on res
System power
source voltage
+ 5V
V
CC
VCC1
RESET
RESET
INT
INT
Cd
VCC
2
V
SS
V1
GND
38C3 Group
M62009L, M62009P, M62009FP
Fig. 2.7.2 RAM backup system example
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APPLICATION
2.7 Reset circuit
2.7.2 Notes on reset circuit
(1) Reset input voltage control
Make sure that the reset input voltage is 0.5 V or less for Vcc of 2.5 V (Note).
Perform switch to the high-speed mode when power source voltage is within 4.0 to 5.5 V.
Note: M version of mask ROM version is 2.2 V.
(2) Countermeasure when RESET signal rise time is long
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
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APPLICATION
2.8 Clock generating circuit
2.8 Clock generating circuit
This paragraph describes the setting method of clock generating circuit relevant registers, application examples
etc.
2.8.1 Relevant register
Figure 2.8.1 shows the structure of the CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM, CM: address 3B16
)
b
0
Name
Function
At reset R W
0
b1 b0
Processor mode
bits
00 : Single-ch
01 :
0
0
1
0
1
2
3
4
10 :
11 :
0 :
le
Stack page
selection bit
Nothing is arranged hen this bit is read
out, the contents ot write “0” to this bit.
Port Xc switc
/O port function
1: XCIN-XCOUT oscillation
function
Main
0: Oscillating
1: Stopped
0: f(XIN)/2 (high-speed
mode)
1: f(XIN)/8 (middle-speed
mode)
0
1
5
6
Xt
k division
lection bit
0: XIN–XOUT selection
(middle-/high-speed
mode)
0
Internal system
clock selection bit
1: XCIN–XCOUT selection
(low-speed mode)
Fig. 2.8.1 Structure of CPU mode register
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APPLICATION
2.8 Clock generating circuit
2.8.2 Clock generating circuit application examples
(1) Status transition during power failure
Outline: The clock is counted up every one second by using the timer interrupt during a power
failure.
Input port
Power failure detection signal
(Note)
38C3 Group
Note: Signal is detected by inputting to each input port,
interrupt input pin, and analog input pin.
Fig. 2.8.2 Connection diagram
Specifications: •Reducing power dissipation as low as possible aintaining clock function
•Clock: f(XIN) = 8 MHz, f(XCIN) = 32.768 kHz
•Port processing
Input port: Fixed to “H” or “L” level ternal
Output port: Fixed to output level tnot cause current flow to the external
(Example) When a rns on LED at “L” output level, fix the
outp“H”.
I/O port: Input port → Fixor “L” level on the external
Output port → of data that does not consume current
V
REF: Stop to supply nce voltage input pin by external circuit
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APPLICATION
2.8 Clock generating circuit
Figure 2.8.3 shows the status transition diagram during power failure and Figure 2.8.4 shows the
setting of relevant registers.
Reset released
Power failure detected
XIN
XCIN
Internal
system clock
Middle-speed
mode
High-speed mode
Low-speed mode
After detecting, changstem clock to
low-speed mode alating XIN-XOUT
Change internal system
clock to high-speed
mode
XCIN-XCOUT oscillation function selected
Fig. 2.8.3 Status transition diagram during power fail
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APPLICATION
2.8 Clock generating circuit
CPU mode register (address 003B16
)
CPUM
0 0 0 0
0 0
Main clock: High-speed mode (f(XIN)) (Note 1)
CPU mode register (address 003B16
)
CPUM
CPUM
0 0 0 1
0 0
(Note 2)
Port X : XCIN-XCOUT oscillation function
C
CPU mode register (address 003B16
)
1
0 0 1
0 0
(Note 2)
Internal systew-speed mode (f(XCIN))
CPU mode register (address 003B16
)
CPUM
1
0 1 1
0 0
(Note 2)
ain clock f(XIN): Stopped
Notes 1: This necessary only when selecting the high-
se.
2lecting the middle-speed mode, bit 6 is “1”.
Fig. 2.8.4 Setting of relevant registers
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APPLICATION
2.8 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
CPUM (address 003B16), bit 6
CPUM (address 003B16), bit 4
0
1
When selecting main clock f(XIN) (high-speed mode)
Port XC: XCIN-XCOUT oscillation function
N
Detect power failure ?
≈
Y
Inm clock: f(XCIN) (low-speed mode)
f(XIN) oscillation stopped
1 (Note)
1 (Note)
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
Set so that timer interrupt occurs every o
second
Execute WIT instruction
At a power failure, clock count is performed during
timer interrupt processing (every second).
N
Return condition failure
co
Return processing from power failure
Note: Do not switch at one time.
≈
Fig. 2.8.5 Control procedure
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APPLICATION
2.8 Clock generating circuit
(2) Counting without clock error during power failure
Outline: It keeps counting without clock error during a power failure.
Specifications: •Reducing power consumption as low as possible while maintaining clock function
•Clock: f(XIN) = 4.19 MHz
•Sub clock: f(XCIN) = 32.768 kHz
•Use of Timer 3 interrupt
For the peripheral circuit and the status transition during a power failure, refer to “Figures 2.8.2 and
2.8.3”.
Figure 2.8.6 shows the structure of clock counter, Figures 2.8.7 and 2.8.8 show the setting of
relevant registers.
Timer 1 interrupt
Timer 3 interrupt
minute counter
Timer 1
1/64
Base counter
244 µs
1 second cou
1/
cond
f(XIN) = 4.19 MHz
1/16
1/256
1/60
Minute/Time/Day/
Month/Year
When the system a
power failure taken
for the swssing for the
return
Timer 1
1/8
2
1/256
Timer 3
1/16
<At power failure>
f(XCIN) = 32.768 kHz
: Software timer
: Hardware timer
Fig. 2.8.6 Structure of clocr
38C3 Group User’s Manual
2-76
APPLICATION
2.8 Clock generating circuit
CPU mode register (address 003B16
)
CPUM
CPUM
0
0
0
1
0 0
Port X : XCIN-XCOUT oscillation function
C
CPU mode register (address 003B16
)
1
0 0
1
0 0
Internal system clock: f(XIN) (high-speed mode)
Timer 1 (address 002016
)
Set (Division ratio -1); 63 (3F16
)
T1
3F16
Timer 12 mode register (address 002816
)
T12M
0
0
0 0
0 0 0 0
Timer 1 coug
Timer 2 cating
Timer urce: f(XIN)/16
Tisource: Timer 1 underflow
rt
Timer 34 mode register 2916
)
T34M
0
0
0
1
Timer 3 count: Operating
Timer 3 count source: Timer 2 underflow
P4 I/O port
2
Interrupt request register 1 (address 003C16
)
IREQ1
0
0
Set “0” to timer 1 interrupt request bit
Set “0” to timer 3 interrupt request bit
Interrupt control register 1 (address 003E16
)
ICON1
1
Timer 1 interrupt: Enabled
Fig. 2.8.7 Initial setting of relevant registers
38C3 Group User’s Manual
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APPLICATION
2.8 Clock generating circuit
Timer 12 mode register (address 002816
)
T12M
CPUM
CPUM
ICON1
0 1
Timer 1 count source: f(XCIN
)
CPU mode register (address 003B16
)
1
0 0 1 0 0
Internal system clock: f(XCIN) (low-speed mode)
CPU mode register (address 003B16
)
1
0 1 0 0
1
Main clock: f(XIN):
Interrupt control register 1 (address 003
1
0
r 1 interrupt: Disabled
mer 3 interrupt: Enabled
Timer 1 (addre
)
)
T1
T2
T3
Timer 2 (address 002116
FF16
Set (Division ratio – 1)
(T1 = 7 (0716), T2 = 255 (FF16), T3 = 15 (0F16))
Timer 3 (address 002216
0F16
Fig. 2.8.8 Setting of relevant registers after detecting power failure
38C3 Group User’s Manual
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APPLICATION
2.8 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
Port XC: XCIN-XCOUT oscillation function
CPUM (address 003B16), bit 4
CPUM (address 003B16), bit 6
T1 (address 002016)
T12M (address 002816)
T34M (address 002916)
IREQ1 (address 003C16), bit 7, bit 5
Base counter (internal RAM)
1 second counter (internal RAM)
ICON1 (address 003E16), bit 5
1
0
3F16
000010002
00XX01X02
0,0
FF16
0F16
When selecting main clock f(XIN) (high-speed mode)
Setting for making base and one second counters activate during
timer 1 interrupt
In the normal power state, these software counters generate one
second.
1
N
Detect power failure ?
Y
≈
Timer 3 interrupt routine
T12M (address 002816), bit 3, bit 2
ICON1 (address 003E16), bit 5
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
IREQ1 (address 003C16), bit 7, bit 5
T1 (address 002016)
0, 1
0
1 (Note)
1 (Note)
0, 0
Timer 1 count source: f(XCIN)
Timer 1 interrupt: Disabled
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN): Oscillation stopped
Setting for generating timer 3 interrupt every
Generation of one second by hardware tim
power failure
Push registers to stack etc.
0716
3F16
T2 (address 002116)
T3 (address 002216)
0F16
Count 1 minute (internal RAM) counter
1 minute counter overflow ?
Timer 3 interrupt: Enabl
1
ICON1 (address 003E16), bit 7
N
Timer 3 inteecond
(return fro
Execute WIT instruction
Y
Modify time, day, month, year
N
Return condition for power failure is
satisfied ?
Y
≈
Return processing from powe
RTI
Note: Do not switch at one time.
≈
Fig. 2.8.9 Control procedure
38C3 Group User’s Manual
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APPLICATION
2.8 Clock generating circuit
MEMORANDUM
38C3 Group User’s Manual
2-80
CHAPTER 3
APPENDIX
3.ical characteristics
andard characteristics
Notes on use
.4 Countermeasures against noise
3.5 Control registers
3.6 Mask ROM confirmation form
3.7 ROM programming confirmation form
3.8 Mark specification form
3.9 Package outline
3.10 Machine instructions
3.11 List of instruction code
3.12 SFR memory map
3.13 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
Parameter
Conditions
Ratings
–0.3 to 7.0
Unit
V
VCC
Power source voltage
VI
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67, P70,
P71, P80–P87
–0.3 to VCC+0.3
V
All voltages are based on
Vss. Output transistors
are cut off.
VI
VI
VI
VI
Input voltage VL1
–0.3 to VL2
VL1 to VL3
V
V
V
V
V
V
V
V
Input voltage VL2
Input voltage VL3
VL2 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VL3+0.3
–0.3 to VL3+0.3
.3 to VCC+0.3
Input voltage RESET, XIN
At output port
VO
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37
At segment output
VO
VO
Output voltage COM0–COM3
Output voltage P40–P47, P50, P52–P57, P60–P67,
P70, P71, P80–P87
VO
Output voltage XOUT
Power dissipation
–0.3 to VCC+0.3
300
V
mW
°C
Pd
Ta = 25°C
Topr
Tstg
Operating temperature
Storage temperature
–20 to 85
–40 to 125
°C
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditi
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
5.0
Symbol
VCC
Parame
Unit
Min.
4.0
2.5
2.5
Max.
5.5
Power source voltage
Power source voltage
High-speN) = 8 MHz
Middlee f(XIN) = 8 MHz
Loe
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
5.0
5.5
5.0
5.5
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIL
0
A-D converter reference
Analog power sourc
Analog input volta7
2.0
VCC
0
AVSS
VCC
VCC
VCC
VCC
VCC
VCC
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
P07, P10–P17, P20–P27
0.7VCC
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
0.8VCC
P80–P87
0.4VCC
RESET
0.8VCC
XIN
0.8VCC
P00–P07, P10–P17, P20–P27
0
0
0
0
0
0.3VCC
0.2VCC
0.16VCC
0.2VCC
0.2VCC
VIL
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
VIL
P80–P87
RESET
XIN
VIL
VIL
38C3 Group User’s Manual
3-2
APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
–60
“H” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
P80–P87, P50
mA
ΣIOH(peak)
“H” total peak output current (Note 1)
–30
40
mA
mA
mA
mA
mA
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
P40–P47, P52–P57, P60–P67, P70, P71
“L” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“L” total peak output current (Note 1)
80
P80–P87, P50
“L” total peak output current (Note 1)
40
P40–P47, P52–P57, P60–P67, P70, P71
“H” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
P80–P87, P50
–30
“H” total average output current (Note 1)
–15
20
mA
mA
mA
mA
mA
mA
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
P40–P47, P52–P57, P60–P67, P70, P71
“L” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“L” total average output current (Note 1)
40
P80–P87, P50
“L” total average output current (Note 1)
20
P40–P47, P52–P57, P60–P67, P70, P71
“H” peak output current (Note 2)
–4.0
–10
P00–P07, P10–P17, P20–P27, P30–P37
“H” peak output current (Note 2)
P40–P47, P50, P52–P57, P60–P67, P70, P71
P80–P87
“L” peak output current (Note 2)
5.0
10
mA
mA
mA
mA
mA
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
P00–P07, P10–P17, P20–P27, P30–
“L” peak output current (Note 2)
P40–P47, P52–P57, P60–P67,
“L” peak output current (Note
30
P80–P87, P50
“H” average output curre
–2.0
–5.0
P00–P07, P10–P130–P37
“H” average output e 3)
P40–P47, P5P60–P67, P70, P71
P80–P87
“L” averagent (Note 3)
2.5
5.0
15
mA
mA
mA
IOL(avg)
IOL(avg)
IOL(avg)
P00–P017, P20–P27, P30–P37
“L” average out current (Note 3)
P40–P47, P52–P57, P60–P67, P70, P71
“L” average output current (Note 3)
P80–P87, P50
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value mea-
sured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
38C3 Group User’s Manual
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.4 Recommended operating conditions
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Unit
Parameter
Input frequency (duty cycle 50%)
Min.
Max.
4.0
f(CNTR0)
f(CNTR1)
f(XIN)
(4.0 V ≤ VCC ≤ 5.5 V)
(VCC ≤ 4.0 V)
MHz
MHz
MHz
(2✕VCC)–4
8.0
Main clock input oscillation frequency (Note 4)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(4✕VCC)–8
MHz
(VCC ≤ 4.0 V)
Middle-speed mode
8.0
50
MHz
kHz
Sub-clock input oscillation frequency (Notes 4, 5)
f(XCIN)
32.768
Notes 4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
38C3 Group User’s Manual
3-4
APPENDIX
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.5 Electrical characteristics
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test conditions
IOH = –2.0 mA
Min.
Typ.
Max.
VOH
“H” output voltage
VCC–2.0
VCC–1.0
V
V
P00–P07, P10–P17, P20–P27,
P30–P37
IOH = –0.6 mA
VCC = 2.5 V
VOH
VOL
VOL
“H” output voltage
P40–P47, P50, P52–P57,
P60–P67, P70, P71,
P80–P87
IOH = –5 mA
VCC–2.0
VCC–0.5
VCC–1.0
V
V
V
IOH = –1.25 mA
(Note) IOH = –1.25 mA
VCC = 2.5 V
“L” output voltage
P00–P07, P10–P17, P20–P27,
P30–P37
IOL = 2.5 mA
2.0
0.5
1.0
V
V
V
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
“L” output voltage
P40–P47, P52–P57, P60–P67,
P70, P71
IOL = 5.0 mA
2.0
0.5
1.0
V
V
V
IOL = 2.5 mA
(Note) IOL = 2.5 mA
VCC = 2.5 V
VOL
“L” output voltage P80–P87, P50
Hysteresis
IOL = 15 mA
2.0
V
V
VT+–VT-
0.5
INT0–INT2, CNTR0, CNTR1, P80–P87
Hysteresis SCLK1, SIN
Hysteresis RESET
VT+–VT-
VT+–VT-
0.5
0.5
V
V
R
– 5.5 V
C
IIH
“H” input current
5.0
140
45
µA
µA
µA
µA
P00–P07, P10–P17, P20–P27
down “off”
CC = 5.0 V, VI = VCC
Pull-down “on”
VCC = 3.0 V, VI = VCC
Pull-down “on”
VI = VCC
30
70
25
6.0
IIH
“H” input current
5.0
P40–P47, P50–P57,
P70, P71, P80–P
IIH
IIH
IIL
“H” input current
“H” input curre
“L” input current
VI = VCC
VI = VCC
5.0
–5.0
–5.0
–140
–45
–5
µA
µA
µA
4.0
P00–P07, P10–P17, P20–P27, P51
“L” input current
IIL
VI = VSS
µA
µA
µA
P40–P47, P50, P52–P57,
P60–P67, P70, P71, P80–P87
Pull-up “off”
VCC = 5.0 V, VI = VSS
Pull-up “on”
–30
–6
–70
–25
VCC = 3.0 V, VI = VSS
Pull-up “on”
IIL
IIL
“L” input current RESET
“L” input current XIN
VI = VSS
µA
µA
VI = VSS
–4
Note: When “1” is set to the port XC switch bit (bit 4 of address 003B16) of the CPU mode register, the drive ability of Port P71 is different from the value above
mentioned.
38C3 Group User’s Manual
3-5
APPENDIX
3.1 Electrical characteristics
Table 3.1.6 Electrical characteristics
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
2.0
Max.
5.5
VRAM
ICC
RAM hold voltage
When clock is stopped
V
Power source current
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter in operating
6.4
1.6
15
13
mA
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter stopped
3.2
22
mA
µA
µA
Low-speed mode, VCC = 3 V,
Ta ≤ 55 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode, VCC = 3 V,
Ta = 25 °C
4.5
9.0
f(XIN) = stopped
f(XCIN) = 32.768 kHz
(in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
0.1
1.0
10
µA
µA
Ta = 25
Ta
Output transistors “off”
38C3 Group User’s Manual
3-6
APPENDIX
3.1 Electrical characteristics
3.1.4 A-D converter characteristics
Table 3.1.7 A-D converter characteristics
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-speed/high-speed mode)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
10
—
—
Resolution
Bits
LSB
tc(φ)
µA
Absolute accuracy (excluding quantization error) VCC = VREF = 5.12 V
Conversion time
±1
±2.5
62
Tconv
61
50
IVREF
IIA
Reference input current
Analog port input current
Ladder resistor
VREF = 5 V
150
0.5
35
200
5.0
µA
RLADDER
kΩ
38C3 Group User’s Manual
3-7
APPENDIX
3.1 Electrical characteristics
3.1.5 Timing requirements and switching characteristics
Table 3.1.8 Timing requirements 1
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
250
105
105
80
twL(INT)
80
tc(SCLK)
800
370
37
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
Serial I/O input hold time
Table 3.1.9 Timing requirements 2
(Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Reset input “L” pulse width
Unit
Min.
Typ.
Max.
tw(RESET)
tc(XIN)
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse
CNTR0, CNTR1 input “L” pul
INT0–INT2 input “H” puls
INT0–INT2 input “L” p
Serial I/O clock inp
Serial I/O clock lse width
Serial I/O clpulse width
Serial I/O itime
125
twH(XIN)
45
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
500/(VCC–2)
250/(VCC–2)–20
250/(VCC–2)–20
230
230
2000
950
950
400
200
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
Serial I/O inpuld time
38C3 Group User’s Manual
3-8
APPENDIX
3.1 Electrical characteristics
Table 3.1.10 Switching characteristics 1
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
twH(SCLK)
Parameter
Unit
Min.
Typ.
Max.
140
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tc(SCLK)/2–30
tc(SCLK)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
(Note 1)
(Note 1)
Serial I/O output valid time
–30
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
30
30
30
30
tf(SCLK)
tr(CMOS)
tf(CMOS)
(Note 2)
(Note 2)
10
10
CMOS output falling time
Notes 1: When the P-channel output disable bit (bit 7 of address 001916) is “0.”
2: The XOUT, XCOUT pins are excluded.
Table 3.1.11 Switching characteristics 2
(Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
mits
Symbol
Parameter
Unit
Mi
Typ.
Max.
350
twH(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tC(S
t0
ns
ns
ns
ns
ns
ns
ns
ns
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
(Note 1)
(Note 1)
Serial I/O output valid time
30
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
50
50
50
50
tf(SCLK)
tr(CMOS)
tf(CMOS)
)
20
20
CMOS output falling time
Notes 1: When the P-channel output disable bit (bit 7 of address 001916)
2: The XOUT, XCOUT pins are excluded.
38C3 Group User’s Manual
3-9
APPENDIX
3.1 Electrical characteristics
3.1.6 Absolute maximum ratings (M version)
Table 3.1.12 Absolute maximum ratings (M version)
Symbol
VCC
Parameter
Power source voltage
Conditions
Ratings
–0.3 to 7.0
Unit
V
VI
Input voltage P00–P07, P10–P17, P20–P27,
P40–P47, P50–P57, P60–P67, P70,
P71, P80–P87
–0.3 to VCC+0.3
V
All voltages are based on
Vss. Output transistors
are cut off.
VI
VI
VI
VI
Input voltage VL1
–0.3 to VL2
VL1 to VL3
V
V
V
V
V
V
V
V
Input voltage VL2
Input voltage VL3
VL2 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VL3+0.3
–0.3 to VL3+0.3
–0.3 to VCC+0.3
Input voltage RESET, XIN
At output port
VO
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37
At segment output
VO
VO
Output voltage COM0–COM3
Output voltage P40–P47, P50, P52–P57, P60–P67,
P70, P71, P80–P87
VO
Output voltage XOUT
Power dissipation
–0.3 to VCC+0.3
300
V
mW
°C
Pd
Ta = 25°C
Topr
Tstg
Operating temperature
Storage temperature
–20 to 85
–40 to 125
°C
3.1.7 Recommended operating conditions (M version)
Table 3.1.13 Recommended operating conditions on)
(Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
5.0
Symbol
VCC
Parameter
Unit
Min.
4.0
2.2
2.2
Max.
5.5
Power source voltage
Power source voltage
High-speed modHz
Middle-speed = 8 MHz
Low-speed
V
V
V
V
V
V
V
5.0
5.5
5.0
5.5
VSS
0
VREF
AVSS
VIA
A-D converter reference voltag
Analog power source voltag
Analog input voltage AN
2.0
VCC
VCC
0
AVSS
38C3 Group User’s Manual
3-10
APPENDIX
3.1 Electrical characteristics
Table 3.1.14 Recommended operating conditions (M version)
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
Typ.
Max.
VCC
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
P00–P07, P10–P17, P20–P27
V
V
V
V
V
V
V
V
V
V
0.7VCC
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
0.8VCC
VCC
P80–P87
0.4VCC
VCC
RESET
0.8VCC
VCC
XIN
0.8VCC
VCC
P00–P07, P10–P17, P20–P27
0
0
0
0
0
0.3VCC
0.2VCC
0.16VCC
0.2VCC
0.2VCC
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
P80–P87
RESET
XIN
Table 3.1.15 Recommended operating conditions (M version)
(Vcc = 2.2 to 2.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Max.
VCC
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
P00–P07, P10–P17, P20–P27
V
V
V
V
V
V
V
V
V
V
CC
P40–P47, P50–P57, P60–P67, P70, P71 (CM4 = 0)
95VCC
VCC
P80–P87
0.5VCC
VCC
RESET
0.95VCC
VCC
XIN
0.95VCC
VCC
P00–P07, P10–P17, P20–P27
0
0
0
0
0
0.2VCC
0.05VCC
0.1VCC
0.05VCC
0.05VCC
P40–P47, P50–P57, P60–P67, P70, 0)
P80–P87
RESET
XIN
38C3 Group User’s Manual
3-11
APPENDIX
3.1 Electrical characteristics
Table 3.1.16 Recommended operating conditions (M version)
(Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
mA
Min.
Max.
–60
“H” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
P80–P87, P50
ΣIOH(peak)
“H” total peak output current (Note 1)
–30
40
mA
mA
mA
mA
mA
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
P40–P47, P52–P57, P60–P67, P70, P71
“L” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“L” total peak output current (Note 1)
80
P80–P87, P50
“L” total peak output current (Note 1)
40
P40–P47, P52–P57, P60–P67, P70, P71
“H” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
P80–P87, P50
–30
“H” total average output current (Note 1)
–15
20
mA
mA
mA
mA
mA
mA
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
P40–P47, P52–P57, P60–P67, P70, P71
“L” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“L” total average output current (Note 1)
40
P80–P87, P50
“L” total average output current (Note 1)
20
P40–P47, P52–P57, P60–P67, P70, P71
“H” peak output current (Note 2)
–4.0
–10
P00–P07, P10–P17, P20–P27, P30–P37
“H” peak output current (Note 2)
P40–P47, P50, P52–P57, P60–P67, P70, P71
P80–P87
“L” peak output current (Note 2)
5.0
10
mA
mA
mA
mA
mA
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
P00–P07, P10–P17, P20–P27, P30–
“L” peak output current (Note 2)
P40–P47, P52–P57, P60–P67,
“L” peak output current (Note
30
P80–P87, P50
“H” average output curre
–2.0
–5.0
P00–P07, P10–P130–P37
“H” average output e 3)
P40–P47, P5P60–P67, P70, P71
P80–P87
“L” averagent (Note 3)
2.5
5.0
15
mA
mA
mA
IOL(avg)
IOL(avg)
IOL(avg)
P00–P017, P20–P27, P30–P37
“L” average out current (Note 3)
P40–P47, P52–P57, P60–P67, P70, P71
“L” average output current (Note 3)
P80–P87, P50
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value mea-
sured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
38C3 Group User’s Manual
3-12
APPENDIX
3.1 Electrical characteristics
Table 3.1.17 Recommended operating conditions (M version)
(Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Input frequency (duty cycle 50%)
Max.
4.0
Min.
Typ.
f(CNTR0)
f(CNTR1)
f(XIN)
(4.0 V ≤ VCC ≤ 5.5 V)
(2.2 V ≤ VCC ≤ 4.0 V)
MHz
MHz
MHz
(2✕VCC)–4
8.0
Main clock input oscillation frequency (Note 4)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
(4✕VCC)–8
High-speed mode
MHz
(2.2 V ≤ VCC ≤ 4.0 V)
8.0
50
Middle-speed mode
MHz
kHz
Sub-clock input oscillation frequency (Notes 4, 5)
f(XCIN)
32.768
Notes 4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
38C3 Group User’s Manual
3-13
APPENDIX
3.1 Electrical characteristics
3.1.8 Electrical characteristics (M version)
Table 3.1.18 Electrical characteristics (M version)
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –2.0 mA
Unit
Min.
Max.
VOH
“H” output voltage
VCC–2.0
VCC–1.0
V
V
P00–P07, P10–P17, P20–P27,
P30–P37
IOH = –0.6 mA
VCC = 2.5 V
VOH
VOL
VOL
“H” output voltage
P40–P47, P50, P52–P57,
P60–P67, P70, P71,
P80–P87
IOH = –5 mA
VCC–2.0
VCC–0.5
VCC–1.0
V
V
V
IOH = –1.25 mA
(Note) IOH = –1.25 mA
VCC = 2.5 V
“L” output voltage
P00–P07, P10–P17, P20–P27,
P30–P37
IOL = 2.5 mA
2.0
0.5
1.0
V
V
V
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
“L” output voltage
P40–P47, P52–P57, P60–P67,
P70, P71
IOL = 5.0 mA
2.0
0.5
1.0
V
V
V
IOL = 2.5 mA
(Note) IOL = 2.5 mA
VCC = 2.5 V
VOL
“L” output voltage P80–P87, P50
Hysteresis
IOL = 15 mA
2.0
V
V
VT+–VT-
0.5
INT0–INT2, CNTR0, CNTR1, P80–P87
Hysteresis SCLK1, SIN
Hysteresis RESET
VT+–VT-
VT+–VT-
0.5
0.5
V
V
R
– 5.5 V
C
IIH
“H” input current
5.0
140
45
µA
µA
µA
µA
P00–P07, P10–P17, P20–P27
down “off”
CC = 5.0 V, VI = VCC
Pull-down “on”
VCC = 3.0 V, VI = VCC
Pull-down “on”
VI = VCC
30
70
25
6.0
IIH
“H” input current
5.0
P40–P47, P50–P57,
P70, P71, P80–
IIH
IIH
IIL
“H” input current
“H” input curre
“L” input current
VI = VCC
VI = VCC
5.0
–5.0
–5.0
–140
–45
–5
µA
µA
µA
4.0
P00–P07, P10–P17, P20–P27, P51
“L” input current
IIL
VI = VSS
µA
µA
µA
P40–P47, P50, P52–P57,
P60–P67, P70, P71, P80–P87
Pull-up “off”
VCC = 5.0 V, VI = VSS
Pull-up “on”
–30
–6
–70
–25
VCC = 3.0 V, VI = VSS
Pull-up “on”
IIL
IIL
“L” input current RESET
“L” input current XIN
VI = VSS
µA
µA
VI = VSS
–4
Note: When “1” is set to the port XC switch bit (bit 4 of address 003B16) of the CPU mode register, the drive ability of Port P71 is different from the value above
mentioned.
38C3 Group User’s Manual
3-14
APPENDIX
3.1 Electrical characteristics
Table 3.1.19 Electrical characteristics (M version)
(Vcc = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
2.0
Typ.
Max.
5.5
VRAM
ICC
RAM hold voltage
When clock is stopped
V
Power source current
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz
6.4
13
mA
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter in operating
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter stopped
1.6
15
3.2
22
mA
µA
µA
Low-speed mode, VCC = 3 V,
Ta ≤ 55 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode, VCC = 3 V,
Ta = 25 °C
4.5
9.0
f(XIN) = stopped
f(XCIN) = 32.768 kHz
(in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
0.1
1.0
10
µA
µA
Ta = 25
Ta
Output transistors “off”
38C3 Group User’s Manual
3-15
APPENDIX
3.1 Electrical characteristics
3.1.9 A-D converter characteristics (M version)
Table 3.1.20 A-D converter characteristics (M version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-speed/high-speed mode)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
10
—
—
Resolution
Bits
LSB
tc(φ)
µA
Absolute accuracy (excluding quantization error) VCC = VREF = 5.12 V
Conversion time
±1
±2.5
62
Tconv
61
50
IVREF
IIA
Reference input current
Analog port input current
Ladder resistor
VREF = 5 V
150
0.5
35
200
5.0
µA
RLADDER
kΩ
38C3 Group User’s Manual
3-16
APPENDIX
3.1 Electrical characteristics
3.1.10 Timing requirements and switching characteristics (M version)
Table 3.1.21 Timing requirements 1 (M version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
250
105
105
80
twL(INT)
80
tc(SCLK)
800
370
37
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
Serial I/O input hold time
Table 3.1.22 Timing requirements 2 (M version)
(Vcc = 2.2 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Reset input “L” pulse width
Unit
Min.
Typ.
Max.
tw(RESET)
tc(XIN)
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse
CNTR0, CNTR1 input “L” pu
INT0–INT2 input “H” puls
INT0–INT2 input “L” p
Serial I/O clock ine
Serial I/O clock lse width
Serial I/O clpulse width
Serial I/O itime
125
twH(XIN)
45
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
500/(VCC–2)
250/(VCC–2)–20
250/(VCC–2)–20
230
230
2000
950
950
400
200
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(SIN-SCLK)
th(SCLK-SIN)
Serial I/O inpuld time
38C3 Group User’s Manual
3-17
APPENDIX
3.1 Electrical characteristics
Table 3.1.23 Switching characteristics 1 (M version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
twH(SCLK)
Parameter
Unit
Min.
Typ.
Max.
140
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tc(SCLK)/2–30
tc(SCLK)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
(Note 1)
(Note 1)
Serial I/O output valid time
–30
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
30
30
30
30
tf(SCLK)
tr(CMOS)
tf(CMOS)
(Note 2)
(Note 2)
10
10
CMOS output falling time
Notes 1: When the P-channel output disable bit (bit 7 of address 001916) is “0.”
2: The XOUT, XCOUT pins are excluded.
Table 3.1.24 Switching characteristics 2 (M version)
(Vcc = 2.2 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
mits
Symbol
Parameter
Unit
Mi
Typ.
Max.
350
twH(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tC(S
t0
ns
ns
ns
ns
ns
ns
ns
ns
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
(Note 1)
(Note 1)
Serial I/O output valid time
30
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
50
50
50
50
tf(SCLK)
tr(CMOS)
tf(CMOS)
)
20
20
CMOS output falling time
Notes 1: When the P-channel output disable bit (bit 7 of address 001916)
2: The XOUT, XCOUT pins are excluded.
1 kΩ
Measurement output pin
Measurement output pin
pF
100 pF
N-channel open-drain output
CMOS output
Note: When bit 7 of the serial I/O control register 1 (address 0019 16) is “ 1.”
(N-channel open-drain output mode)
Fig. 3.1.1 Circuit for measuring output switching characteristics
38C3 Group User’s Manual
3-18
APPENDIX
3.1 Electrical characteristics
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0,CNTR1
0.8VCC
0.2VCC
twL(INT)
twH(INT)
INT0 – INT2
0.8VCC
0.2VCC
tW(RESET)
0.8VCC
RESET
0.2VCC
(XIN)
tWL(XIN)
t
0.8
XIN
0.2VCC
tC
(SCLK
)
tr
tf
tWL(SCLK
)
tWH(SCLK)
0.8VCC
S
S
S
CLK
0.2VCC
t
su(SIN-SCLK
)
th(SCLK-SIN)
0.8VCC
0.2VCC
IN
t
d
(SCLK-SOUT
)
tv(SCLK-SOUT)
OUT
Fig. 3.1.2 Timing chart
38C3 Group User’s Manual
3-19
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current standard characteristics
Measuring conditions: 25 °C, f(XCIN) = 32.768 kHz, at A-D converter operating, in high-speed mode
Power source current (mA)
10.0
Rectangular waveform input
Vcc = 5.5 V
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
Vcc = 5.0 V
Vcc = 4.0 V
0.0
0
2
4
8
10
12
Frequency f(XIN) (MHz)
Fig. 3.2.1 Power source current standard ristics
Measuring conditions: 25 32.768 kHz, at A-D conversion completed, in high-speed mode
Power source current (mA)
Rectangular waveform input
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Vcc = 5.5 V
Vcc = 5.0 V
Vcc = 4.0 V
0
2
4
6
8
10
12
Frequency f(XIN) (MHz)
Fig. 3.2.2 Power source current standard characteristics (in wait mode)
38C3 Group User's Manual
3-20
APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristics
Port P00 IOH–VOH characteristics (25 °C)
(Same characteristics pins: P00–P07, P10–P17, P20–P27, P30–P37)
I
OH (mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
5.5 V
Vcc = 2.5 V
2
Vcc = 5
0
1
3
4
5
6
VOH (V)
Fig. 3.2.3 CMOS output port (P0, P1, P2, P3) el side characteristics (25 °C)
Port P00 IOH–ristics (90 °C)
(Same chains: P0
0–P07, P10–P17, P20–P27, P30–P37)
I
OH (mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Vcc = 5.5 V
Vcc = 2.5 V
2
Vcc = 5.0 V
0
1
3
4
5
6
V
OH (V)
Fig. 3.2.4 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (90 °C)
38C3 Group User's Manual
3-21
APPENDIX
3.2 Standard characteristics
Port P0
0 IOL–VOL characteristics (25 °C)
I
OL (mA)
100
(Same characteristics pins: P0
0–P07, P10–P17, P20–P27, P30–P37)
90
80
70
60
50
40
30
20
10
0
Vcc = 5.5 V
Vcc = 5.0 V
Vcc = 2.5 V
0
1
2
3
5
6
V
OL (V)
Fig. 3.2.5 CMOS output port (P0, P1, P2, P3) P-side characteristics (25 °C)
Port P00 IOL–Vistics (90 °C)
(Same charns: P0
0–P07, P10–P17, P20–P27, P30–P37)
I
OL (mA)
100
90
80
70
60
50
40
30
20
10
0
Vcc = 5.5 V
Vcc = 5.0 V
Vcc = 2.5 V
0
1
2
3
4
5
6
V
OL (V)
Fig. 3.2.6 CMOS output port (P0, P1, P2, P3) N-channel side characteristics (90 °C)
38C3 Group User's Manual
3-22
APPENDIX
3.2 Standard characteristics
Port P40 IOH–VOH characteristics (25 °C)
(Same characteristics pins: P40–P47, P50, P52–P57, P60–P67, P70, P71, P80–P87)
IOH (mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
c = 5.5 V
Vcc = 5.0 V
Vcc = 2.5 V
0
1
2
3
4
5
6
VOH (V)
Fig. 3.2.7 CMOS output port (P4, P50, P52–P57, P71, P8) P-channel side characteristics (25 °C)
Port P4
0
I
OH–VOH cha(90 °C)
–P4 , P5
I
OH (mA)
-100
(Same characteris
0
7
0, P52–P57, P60–P67, P70, P71, P80–P87)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Vcc = 5.0 V
Vcc = 5.5 V
Vcc = 2.5 V
0
1
2
3
4
5
6
VOH (V)
Fig. 3.2.8 CMOS output port (P4, P50, P52–P57, P6, P70, P71, P8) P-channel side characteristics (90 °C)
38C3 Group User's Manual
3-23
APPENDIX
3.2 Standard characteristics
Port P40 IOL–VOL characteristics (25 °C)
(Same characteristics pins: P40–P47, P52–P57, P60–P67, P70, P71)
I
OL (mA)
100
90
80
70
60
50
40
30
20
10
0
Vcc = 5.5 V
Vcc = 5.0 V
Vcc = 2.5 V
0
1
2
3
4
5
6
V
OL (V)
Fig. 3.2.9 CMOS output port (P4, P52–P57, P6, P-channel side characteristics (25 °C)
Port P40 IOLeristics (90 °C)
I
OL (mA)
100
(Same chpins: P40–P47, P52–P57, P60–P67, P70, P71)
90
80
70
60
50
40
30
20
10
0
Vcc = 5.5 V
Vcc = 5.0 V
Vcc = 2.5 V
0
1
2
3
4
5
6
V
OL (V)
Fig. 3.2.10 CMOS output port (P4, P52–P57, P6, P70, P71) N-channel side characteristics (90 °C)
38C3 Group User's Manual
3-24
APPENDIX
3.2 Standard characteristics
Port P80 IOL–VOL characteristics (25 °C)
(Same characteristics pins: P8
0–P87, P50)
I
OL (mA)
100
90
80
70
60
50
40
30
20
10
0
Vcc = 5.5 V
Vcc = 5.0 V
Vcc = 2.5 V
0
1
2
3
5
6
VOL (V)
Fig. 3.2.11 CMOS output port (P50, P8) N-channaracteristics (25 °C)
POL characteristics (90 °C)
I
OL (mA)
100
acteristics pins: P8
0–P8
7, P50)
90
80
70
60
50
40
30
20
10
0
Vcc = 5.5 V
Vcc = 5.0 V
Vcc = 2.5 V
0
1
2
3
4
5
6
V
OL (V)
Fig. 3.2.12 CMOS output port (P50, P8) N-channel side characteristics (90 °C)
38C3 Group User's Manual
3-25
APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Switching external interrupt detection edge
For the products able to switch the external interrupt detection edge, switch it as the following
sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Switch the detection edge
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrud)
Fig. 3.3.1 Sequence of switch detection edge
■ Reason
The interrupt circuit recognizes the switchindetection edge as the change of external input
signals. This may cause an unnecessapt.
(2) Check of interrupt request bit
● When executing the BBC or Buction to an interrupt request bit of an interrupt request
register immediately after thit to “0” by using a data transfer instruction, execute one or
more instructions before the BBC or BBS instruction.
■ Reason
If the BBC or BBon is executed immediately after an interrupt request bit of an interrupt
request register d to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.2 Sequence of check of interrupt request bit
38C3 Group User’s Manual
3-26
APPENDIX
3.3 Notes on use
(3) Structure of interrupt control register 2
Fix the bit 7 of the interrupt control register 2
to “0”. Figure 3.3.3 shows the structure of the
interrupt control register 2.
b7
b0
Interrupt control register 2
Address 003F16
0
Interrupt enable bits
Not used
Fix this bit to “0”.
Fig. 3.3.3 Structure of interrupt control register 2
3.3.2 Notes on timer A (PWM mode and IGBT output mode)
(1) When timer starts first or last value of compare register is “000016
”
After “L” level (timer A output active edge switch bit is “0”; when starting from “L” output) is output
during 2 cycles (until timer underflows two times), start PWM output or IGBT output.
Reason: When data is written to timer A and compare register, value of timer A and value of
compare register are renewed at timer underflow. In case his, compare register value
and timer value are compared before renewal so that judged to be equal, and
TAOUT output becomes “L”. (Timer A output switch bit hen starting from “L” output)
Timer A underflow should be “H” output, but the ave the priority. (see “Figure
3.3.4”)
Compare register value is
“000016
Compars value which is written at ➀
”
(last value or initial value)
➀
Timer A start
rflow
Timer A underflow
Timer A underflow
ster value
Fig. 3.3.4 PWM output aT output (1)
38C3 Group User’s Manual
3-27
APPENDIX
3.3 Notes on use
(2) When compare register is set to “000016” (last value is except “000016”)
Next 1 cycle of the cycle which data is written to timer A and compare register is output “H”, and
“L” is output from the next cycle. (timer A output switch bit = “0”: when starting from “L” output)
(see “Figure 3.3.5”)
Compare register value is
last value
Compare register value is “000016”
Timer A underflow
Timer A underflow
Timer A underflow
Timer A underflow
Timer A value
compare register value
writing
Fig. 3.3.5 PWM output and IGBT output (2)
(3) When timer A and compare register are same value
TAOUT output becomes “H” with underflow immediately a is written to timer A and compare
register. And TAOUT output becomes “L” when timeloaded and the value matches with
compare register. This “H” output width becomes of timer A count source. (timer A output
switch bit =“0”: when starting from “L” output) gure 3.3.6”)
Timer A count source
Timer A value–compare regi
1 count width
Timer A underflow
Timer A value
Timer A underflow
compare register value
writing
Fig. 3.3.6 PWM output and IGBT output (3)
38C3 Group User’s Manual
3-28
APPENDIX
3.3 Notes on use
3.3.3 Notes on serial I/O
(1) Selecting external synchronous clock
When an external synchronous clock is selected, the contents of serial I/O register are being shifted
continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control the clock
externally.
(2) Transmission data writing
When an external clock is used as the synchronous clock, write the transmit data to the serial I/O
shift register at “H” level of transfer clock input.
3.3.4 Notes on LCD controller
●When switching from the high-speed or middle-speed mode to the low-speed mode, switch the mode in
the following order:
(1) 32 kHz oscillation selected (bit 4 of CPU mode register (address 003B16) = “1”)
(2) Count source for LCDCK = f(XCIN)/32 (bit 7 of LCD mode register (address 003916) = “0”)
(3) Internal system clock: XCIN-XCOUT selected (bit 7 of CPU mode reter (address 003B16) = “1”)
(4) Main clock XIN–XOUT stopped (bit 5 of CPU mode register (add3B16) = “1”)
Execute the setting (2) after the oscillation at 32 kHz (setting mes completely stable.
●If the STP instruction is executed while the LCD is turned on g bit 3 of the LCD mode register
(address 003916) to “1”, a DC voltage is applied to the LCis reason, do not execute the STP
instruction while the LCD is lighting.
●When the LCD is not used, open the segment and mon pins.
Connect VL1 to VL3 to VSS
.
●For the following products, if the LCD enathe LCD mode register (bit 3 of address 003916) is
set to “0”, all LCDs cannot be turned off. CDs are turned off, set “0” (turn off) to all corresponding
LCD display RAM.
Corresponding products: M3AXXXFP, M38C34M6MXXXFP, M38C37ECAXXXFP,
CMXXXFP, M38C37ECAFP, M38C37ECMFP, M38C37ECAFS,
ECMFS, M38C37RFS, M38C37RMFS
38C3 Group User’s Manual
3-29
APPENDIX
3.3 Notes on use
3.3.5 Notes on A-D converter
(1) Analog input pin
■ Make the signal source impedance for analog input low, or equip an analog input pin with an
external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application
products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
(2) A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the VSS line.
● Reason
If the AVSS pin is opened, the microcomputer may have a ecause of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a of the capacity will be lost if the clock
frequency is too low. Thus, make sure the followian A-D conversion.
• f(XIN) is 500 kHz or more.
• Use clock divided by main clock (f(XIN)) as system clock.
• Do not execute the STP instruction and uction.
3.3.6 Notes on reset circuit
(1) Reset input voltage control
Make sure that the reset input s 0.5 V or less for Vcc of 2.5 V (Note).
Perform switch to the high-sde when power source voltage is within 4.0 to 5.5 V.
Note: M version of mask sion is 2.2 V.
(2) Countermeasure wET signal rise time is long
In case where the signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
38C3 Group User’s Manual
3-30
APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Package
Select the smallest possible package to make the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.4.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is cto the RESET pin as short as possible. Especially,
connect a capacitor across the REnd the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse inhe RESET pin is determined by the timing necessary conditions.
If noise having a she width than the standard is input to the RESET pin, the reset is
released before thstate of the microcomputer is completely initialized. This may cause
a program runa
Noise
Reset
RESET
circuit
V
SS
V
SS
N.G.
Reset
circuit
RESET
V
SS
V
SS
O.K.
Fig. 3.4.2 Wiring for the RESET pin
38C3 Group User’s Manual
3-31
APPENDIX
3.4 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is
connected to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the VSS
level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
X
X
V
IN
X
X
V
IN
OUT
SS
OUT
SS
O.K.
N.G.
Fig. 3.4.3 Wiring for clock I/O pins
38C3 Group User’s Manual
3-32
APPENDIX
3.4 Countermeasures against noise
(4) Wiring to VPP pin of One Time PROM version and EPROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series. When not
connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest
possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The VPP pin of the One Time PROM and the EPROM version is the power source input pin for
the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low
to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily.
If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM,
which may cause a program runaway.
Approximately
5 kΩ
P51/VPP
RESET
Fig. 3.4.4 Wiring for the VPP pin of the One Tiand the EPROM version
3.4.2 Connection of bypass capacitor acline and VCC line
Connect an approximately 0.1 µF bypasor across the VSS line and the VCC line as follows:
• Connect a bypass capacitor across pin and the VCC pin at equal length.
• Connect a bypass capacitor acroS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diamether signal lines for VSS line and VCC line.
• Connect the power source a bypass capacitor to the VSS pin and the VCC pin.
V
CC
V
CC
V
SS
V
SS
N.G.
O.K.
Fig. 3.4.5 Bypass capacitor across the VSS line and the VCC line
38C3 Group User’s Manual
3-33
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the VSS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from
the VSS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microco
pin
Thermistor
N.G.
VSS
Notstor is used for dividing
ance with a thermistor.
Fig. 3.4.6 Analog signal line and a and a capacitor
3.4.4 Oscillator concerns
Take care to prevent an oscilgenerates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator y from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
X
X
IN
Large
current
OUT
V
SS
GND
Fig. 3.4.7 Wiring for a large current signal line
38C3 Group User’s Manual
3-34
APPENDIX
3.4 Countermeasures against noise
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
CNTR
Do not cross
X
X
V
IN
OUT
SS
Fig. 3.4.8 Wiring of signal lines where potential levels chquently
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a ern on the underside (soldering side) of the
position (on the component side) where an is mounted.
Connect the VSS pattern to the microcoS pin with the shortest possible wiring. Besides,
separate this VSS pattern from other rns.
ample of VSS patterns on the
erside of a printed circuit board
or wiring
n example
XIN
XOUT
V
SS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.9 VSS pattern on the underside of an oscillator
38C3 Group User’s Manual
3-35
APPENDIX
3.4 Countermeasures against noise
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
Noise
Data bus
Noise
Direction register
N.G.
Port latc
I/O port
pins
Fig. 3.4.10 Setup for I/O ports
38C3 Group User’s Manual
3-36
APPENDIX
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by cothe SWDT contents with
counts of interrupt processing after the initial value N has
• Detects that the interrupt processing routine has failed annes to branch to the program
initialization routine for recovery processing in the folle:
If the SWDT contents do not change after interrupt ng.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at eapt processing.
• Determines that the main routine operately when the SWDT contents are reset to the
initial value N at almost fixed cycles (ed interrupt processing count).
• Detects that the main routine has fdetermines to branch to the program initialization
routine for recovery processing iwing case:
If the SWDT contents are not to the initial value N but continued to decrement and if
they reach 0 or less.
Intessing routine
Main routine
(T) ← (SWDT)—1
(SWDT)← N
CLI
Interrupt processing
Main processing
>0
(SWDT)
≤0?
RTI
≠N
≤0
(SWDT)
=N?
Return
N
Interrupt processing
routine errors
Main routine
errors
Fig. 3.4.11 Watchdog timer by software
38C3 Group User’s Manual
3-37
APPENDIX
3.5 Control registers
3.5 Control registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 8)
(Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0C16, 1016
)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
7
Port Pi
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
●In output mode
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
Fig. 3.5.1 Structure of Port Pi
Port P0 direction register, Port P1 dirgister
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 directioD: address 0116
Port P1 direcP1D: address 0316
)
)
b
0
1
n register
Functions
At reset R W
0
✕
0 : All bits of ports P0/P1
input mode
1 : All bits of ports P0/P1
output mode
2
3
4
5
6
7
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
0
0
0
0
0
0
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
0
Note: Ports P0 and P1 are switched to input and output by each port.
When b0 of corresponding port direction register is set to “0”, all
8 bits of port become input port. When b0 of corresponding port
direction register is set to “1”, all 8 bits of port become output
port. Nothing is arranged for b1 to b7 of port P0 and port P1
direction registers. These are write disabled bits.
Fig. 3.5.2 Structure of Port P0 direction register and Port P1 direction register
38C3 Group User’s Manual
3-38
APPENDIX
3.5 Control registers
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 2, 4, 5, 6, 8)
(PiD: addresses 0516, 0916, 0B16, 0D16, 1116)
b
0
Name
Port Pi direction
register
Functions
0 : Port Pi0 input mode
1 : Port Pi0 output mode
At reset R W
0
0 : Port Pi1 input mode
1 : Port Pi1 output mode
(Note)
0
1
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0
0
0
0
0
0
2
3
4
5
6
7
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output m
0 : Port Pi5 input
1 : Port Pi5 out
0 : Port Pi6
1 : Port Pode
0 : Pomode
1 : put mode
Note: Bit 1 of the port P5 dirr (address 0B16) does not have
direction register fuse P51 is an input port. When writing to
bit 1 of the port Pgister, write “0” to the bit.
Fig. 3.5.3 Structure of Port Pi direction re
Port P7
b7 b6 b5 b4 b3 b2 b1 b
address 0E16)
b
0
Name
Port P70
Functions
At reset R W
0
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
1
0
Port P71
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
2
3
4
5
6
7
0
0
0
0
0
0
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
Fig. 3.5.4 Structure of Port P7
38C3 Group User’s Manual
3-39
APPENDIX
3.5 Control registers
Port P7 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P7 direction register
(P7D: address 0F16
)
b
0
Name
Port P7 direction
register
Functions
At reset R W
0 : Port P7
0
0
input mode
output mode
0
✕
1 : Port P7
0 : Port P7
1 : Port P7
1
1
input mode
output mode
0
✕
1
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
0
0
0
0
0
0
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
✕ ✕
2
3
4
5
6
7
Fig. 3.5.5 Structure of Port P7 direction register
PULL register A
b7 b6 b5 b4 b3 b2 b1 b0
PULL register A
(PULLA: address
b
0
Functions
0: No pull-down control
1: Pull-down control
At reset R W
1
Por
ontrol
–P1
own control
rt P2 –P2
pull-down control
1
1
1
0: No pull-down control
1: Pull-down control
7
0: No pull-down control
1: Pull-down control
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
3
Port P7
0
, P7
pull-up control
Port P8 –P8
pull-up control
1
0: No pull-up control
1: Pull-up control
0
0
4
5
6
0
7
0: No pull-up control
1: Pull-up control
0
0
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
7
Note: The pin which is set to output port is cut off from pull-up control.
Fig. 3.5.6 Structure of PULL register A
38C3 Group User’s Manual
3-40
APPENDIX
3.5 Control registers
PULL register B
b7 b6 b5 b4 b3 b2 b1 b0
PULL register B
(PULLB: address 1716
)
b
0
Name
Functions
0: No pull-up control
1: Pull-up control
At reset R W
0
Port P4
pull-up control
Port P4 –P4
pull-up control
2 Port P5 , P5 , P5
pull-up control
3 Port P5 –P5
pull-up control
Port P6 –P6
pull-up control
Port P6 –P6
pull-up control
0
–P4
3
0
0
0
0: No pull-up control
1: Pull-up control
4
7
1
0: No pull-up control
1: Pull-up control
0
2
3
4
7
0: No pull-up control
1: Pull-up control
0: No pull-up control
1: Pull-up control
0
3
0
0
4
5
6
4
7
0: No pull-up control
1: Pull-up control
0
0
Nothing is arranged for this bit. This is
disabled bit. When this bit is read o
contents are “0”.
Nothing is arranged for this bwrite
disabled bit. When this bit the
contents are “0”.
7
Note: The pin which is sport is cut off from pull-up control.
Fig. 3.5.7 Structure of PULL register B
38C3 Group User’s Manual
3-41
APPENDIX
3.5 Control registers
Port P8 output selection register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8 output selection register (P8SEL: address 1816)
b
0
Name
Port P8 output
selection register
Functions
At reset R W
0
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0
0
0
0
0
0
0
1
2
3
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
0: CMOS output (in output m
1: N-channel open-d
output (in outpu
0: CMOS output (e)
1: N-channen
output ode)
4
5
6
7
0: CMutput mode)
1: Npen-drain
output mode)
output (in output mode)
hannel open-drain
utput (in output mode)
0: CMOS output (in output mode)
1: N-channel open-drain
output (in output mode)
Fig. 3.5.8 Structure of Port P8 election register
38C3 Group User’s Manual
3-42
APPENDIX
3.5 Control registers
Serial I/O control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register 1
(SIOCON1: address 1916
)
b
0
Name
Internal
synchronous clock
selection bits
Functions
At reset R W
0
b2b1b0
0 0 0: f(XIN)/8 or f(XCIN)/8
0 0 1: f(XIN)/16 or f(XCIN)/16
0 1 0: f(XIN)/32 or f(XCIN)/32
0 1 1: f(XIN)/64 or f(XCIN)/64
1 1 0: f(XIN)/128 or f(XCIN)/128
1 1 1: f(XIN)/256 or f(XCIN)/256
0
0
0
1
2
3
Serial I/O port
selection bit
0: I/O port
1: SOUT, SCLK1, SCLK2
signal pin
(P4
RDY output
selection bit (P4
0
, P45, P4
6)
S
0: I/O port
1: SRDY signal pin
0
0
0
0
4
5
6
7)
Transfer direction
selection bit
0: LSB first
1: MSB first
0: External
1: Intern
Synchronous clock
selection bit
P-channel output
disable bit
0: CM
7
(ode)
(P40, P45, P46)
1l open-drain
(in output mode)
Fig. 3.5.9 Structure of Serial I/O control re
38C3 Group User’s Manual
3-43
APPENDIX
3.5 Control registers
Serial I/O control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register 2
(SIOCON2: address 1A16
)
b
0
Name
Functions
At reset R W
0: SCLK1
1: SCLK2
0
Synchronous clock
output pin selection
bit
1
2
3
4
5
6
7
✕
✕
✕
✕
✕
✕
✕
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
0
0
0
0
0
0
Fig. 3.5.10 Structure of Serial I/O control register 2
Serial I/O register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O register
(SIO: address 1B
b
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
1
2
7
Serir
This register becomes shift
register.
Set transmit data to this
register.
The serial transfer is started
by writing the transmit data.
Fig. 3.5.11 Structure of Serial I/O register
38C3 Group User’s Manual
3-44
APPENDIX
3.5 Control registers
Timer i
b7 b6 b5 b4 b3 b2 b1 b0
Timer i (i = 1, 3, 4, 5, 6)
(Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
• Set timer i count value.
• The value set in this register is written to both
the timer i and the timer i latch at one time.
• When the timer i is read out, the count value
of the timer i is read out.
Fig. 3.5.12 Structure of Timer i
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2116)
b
ions
At reset R W
0
1
2
3
4
1
0
0
0
0
0
0
0
• Set timelue.
• The vthis register is written to both
the d the timer 2 latch at one time.
• mer 2 is read out, the count value
mer 2 is read out.
Fig. 3.5.13 Structure of T2
38C3 Group User’s Manual
3-45
APPENDIX
3.5 Control registers
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 6 PWM register
(T6PWM: address 2716
)
b
Functions
At reset R W
• In timer 6 PWM1 mode
Undefined
0
1
2
3
4
“L” level width of PWM rectangular waveform is set.
• Duty of PWM rectangular waveform: n/(n + m)
Period: (n + m) × ts
Undefined
Undefined
Undefined
Undefined
Undefined
ndefined
ndefined
n = timer 6 set value
m = timer 6 PWM register set value
ts = timer 6 count source period
At n = 0, all PWM output “L”.
At m = 0, all PWM output “H”.
(However, n = 0 has priority.)
5
6
• Selection of timer 6 PWM
Set “1” to the timer 6 operation mode selection
1 mode
7
Fig. 3.5.14 Structure of Timer 6 PWM register
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 m
(T12M:
)
b
me
1 count stop
Functions
0: Count operation
1: Count stop
At reset R W
0
imer 2 count stop
bit
Timer 1 count
source selection
bits
0: Count operation
1: Count stop
0
0
0
0
2
3
4
b3 b2
0 0: f(XIN)/16 or f(XCIN)/16
0 1: f(XCIN
)
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/128 or f(XCIN)/128
b5 b4
Timer 2 count
source selection
bits
0 0: Timer 1 underflow
0 1: f(XCIN
1 0: External count input
CNTR
)
0
5
0
1 1: Not available
0: I/O port
1: Timer 1 output
Timer 1 output
selection bit (P41)
0
0
6
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Fig. 3.5.15 Structure of Timer 12 mode register
38C3 Group User’s Manual
3-46
APPENDIX
3.5 Control registers
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register
(T34M: address 2916
)
b
0
Name
Timer 3 count stop
bit
Functions
0: Count operation
1: Count stop
At reset R W
0
Timer 4 count stop
bit
Timer 3 count
source selection
bits
0: Count operation
1: Count stop
0
0
1
2
3
4
b3 b2
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 2 underflow
1 0: f(XIN)/32 or f(XCIN)/32
1 1: f(XIN)/128 or f(XCIN)/128
b5 b4
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 3 underflow
1 0: External count in
Timer 4 count
source selection
bits
0
0
5
CNTR
1
1 1: Not availab
0: I/O port
1: Timer 3
Timer 3 output
selection bit (P42)
0
0
6
7
Nothing is arranged for this bwrite
disabled bit. When this bit , the
contents are “0”.
Fig. 3.5.16 Structure of Timer 34 mode regist
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
ode register
ddress 2A16)
0
Name
Timer 5 count stop
Functions
0: Count operation
1: Count stop
At reset R W
0
bit
Timer 6 count stop
bit
Timer 5 count
0: Count operation
1: Count stop
0
0
0
0
0
0
1
2
3
4
0: f(XIN)/16 or f(XCIN)/16
1: Timer 4 underflow
source selection bit
Timer 6 operation
mode selection bit
0: Timer mode
1: PWM mode
b5 b4
Timer 6 count
source selection
bits
0 0: f(XIN)/16 or f(XCIN)/16
0 1: Timer 5 underflow
1 0: Timer 4 underflow
1 1: Not available
0: I/O port
1: Timer 6 output
5
6
Timer 6 (PWM)
output selection bit
(P52)
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
7
Fig. 3.5.17 Structure of Timer 56 mode register
38C3 Group User’s Manual
3-47
APPENDIX
3.5 Control registers
φ output control register
b7 b6 b5 b4 b3 b2 b1 b0
φ output control register
(CKOUT: address 2B16
)
Name
b
0
Functions
At reset R W
φ output control bit
0: Port function
1: φ clock output
1 Nothing is arranged for these bits. These are
0
(P4 )
3
0
0
0
0
0
0
0
write disabled bits. When these bits are read out,
the contents are “0”.
2
3
4
5
6
7
Fig. 3.5.18 Structure of φ output control register
Timer A register (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer A register (low-oer)
(TAL, TAH: address6
)
b
unctions
At reset R W
• Set nt value.
1
1
1
1
1
1
1
1
0
1
2
• Wmer A write control bit of the timer
egister is “0”, the value is written to
and the latch at one time.
n the timer A write control bit of the timer
mode register is “1”, the value is written only
to the latch.
6
7
• The timer A count value is read out by reading
this register.
Notes 1: When reading and writing, perform them to both the high-
order and low-order bytes.
2: Read both registers in order of TAH and TAL following.
3: Write both registers in order of TAL and TAH following.
4: Do not read both registers during a write, and do not write to
both registers during a read.
Fig. 3.5.19 Structure of Timer A register (low-order, high-order)
38C3 Group User’s Manual
3-48
APPENDIX
3.5 Control registers
Compare register (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Compare register (low-order, high-order)
(CONAL, CONAH: addresses 2E16, 2F16
)
b
Functions
At reset R W
• Set compare register value.
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Note: Write registers in order of CONAH, C, and TAH
following.
Fig. 3.5.20 Structure of Compare register (low-order, hig
Timer A mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer A m
(TAM:
)
b
ame
Functions
At reset R W
0
b1b0
A operating
e bits
0 0: Timer mode
0 1: Pulse output mode
1 0: IGBT output mode
1 1: PWM mode
2
0
0
Timer A write control
bit
0: Write data to both timer
latch and timer
1: Write data to timer latch
b4b3
Timer A count source
selection bits
3
4
5
6
7
0
0
0
0
0
0 0: f(XIN
)
0 1: f(XIN)/2
1 0: f(XIN)/4
1 1: f(XIN)/8
Timer A output active
edge switch bit
0: Output starts with “L” level
1: Output starts with “H” level
Timer A count stop bit 0: Count operating
1: Count stop
Timer A output
selection bit (P5
0: I/O port
1: Timer A output
0)
Fig. 3.5.21 Structure of Timer A mode register
38C3 Group User’s Manual
3-49
APPENDIX
3.5 Control registers
Timer A control register
b7 b6 b5 b4 b3 b2 b1 b0
Timer A control register
(TACON: address 3116
)
b
0
Name
Functions
At reset R W
0
Noise filter sampling
clock selection bit
0: f(XIN)/2
1: f(XIN)/4
b2b1
1
2
3
0
0
0
0
External trigger delay
time selection bits
0 0: No delay
0 1: (4/f(XIN))µs
1 0: (8/f(XIN))µs
1 1: (16/f(XIN))µs
Timer A output control
0: Not used
1: INT1 interrupt used
bit 1 (P5
6)
Timer A output control
bit 2 (P57)
0: Not used
1: INT2 interrupt used
4
0
0
0
Nothing is arranged for these bits. These are
disabled bits. When these bits are read out
contents are “0”.
5
6
7
Fig. 3.5.22 Structure of Timer A control register
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D contr
(ADCO216)
b
me
g input pin
ection bits
Functions
At reset R W
0
b2 b1 b0
0 0 0: P60/AN0
0 0 1: P61/AN1
0 1 0: P62/AN2
0 1 1: P63/AN3
1 0 0: P64/AN4
1 0 1: P65/AN5
1 1 0: P66/AN6
1 1 1: P67/AN7
1
0
0
2
3
4
Nothing is arranged for this bit. This is write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0: Conversion in progress
1: Conversion completed
AD conversion
completion bit
0
0
0
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
Fig. 3.5.23 Structure of A-D control register
38C3 Group User’s Manual
3-50
APPENDIX
3.5 Control registers
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3316)
b
Functions
At reset R W
Undefined
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
These are A-D conversion result (low-order 2 bits)
stored bits. This is read exclusive register.
Undefined
Note: Do not read this register during A-D conversion.
Fig. 3.5.24 Structure of A-D conversion register (low-order)
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (h
(ADH: address 3416)
b
ctions
At reset R W
Undefined
0
1
2
3
4
This is A-result (high-order 8 bits) stored
bits. Thclusive register.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
ote: Do not read this register during A-D conversion.
Fig. 3.5.25 Structure of A-D conversion register (high-order)
38C3 Group User’s Manual
3-51
APPENDIX
3.5 Control registers
Segment output enable register
b7 b6 b5 b4 b3 b2 b1 b0
Segment output enable register
(SEG: address 3816)
b
0
Name
Segment output
enable bit 0
Segment output
enable bit 1
Segment output
enable bit 2
Segment output
enable bit 3
Segment output
enable bit 4
Segment output
enable bit 5
Segment output
enable bit 6
Functions
At reset R W
0
0: I/O ports P20–P2
3
1: Segment output SEG
0
–SEG
–SEG
3
7
0: I/O ports P24–P2
7
0
0
0
0
0
0
0
1
2
3
4
1: Segment output SEG
4
0: I/O ports P00–P0
3
1: Segment output SEG –SEG11
8
0: I/O ports P04–P0
7
1: Segment output SEG12–SEG15
0: I/O ports P10–P1
3
1: Segment output SEG16–SE
0: I/O ports P14–P1
7
5
6
7
1: Segment output SEG
0: Output ports P
1: Segment outpG27
Segment output
enable bit 7
0: Output p3
7
1: Segme28–SEG31
Fig. 3.5.26 Structure of Segment output enable regis
LCD mode register
b7 b6 b5 b4 b3 b2 b1 b0
LCD m
0
(LM16
)
Name
Functions
At reset R W
0
b1b0
ty ratio selection
bits
0 0: 1 (use COM
0 1: 2 (use COM
1 0: 3 (use COM
1 1: 4 (use COM
0
0
0
0
)
, COM
–COM
–COM
1)
2)
3)
1
2
3
0
0
0
Bias control bit
LCD enable bit
0: 1/3 bias
1: 1/2 bias
0: LCD OFF
1: LCD ON
4
5
0
0
Fix “0” to this bit.
LCD circuit divider
division ratio selection
bits
b6b5
0 0: Clock input
0 1: 2 division of clock input
1 0: 4 division of clock input
1 1: 8 division of clock input
6
7
0
0
0: f(XCIN)/32
1: f(XIN)/8192 (f(XCIN)/8192 in
low-speed mode)
LCDCK count source
selection bit (Note)
Note: LCDCK is a clock for a LCD timing controller.
Fig. 3.5.27 Structure of LCD mode register
38C3 Group User’s Manual
3-52
APPENDIX
3.5 Control registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE: address 3A16
)
b
0
Name
Functions
0: Falling edge active
1: Rising edge active
At reset R W
0
INT
selection bit
INT interrupt edge
0
interrupt edge
1
0: I/O ports P2
4–P2
7
0
0
1
2
selection bit
INT interrupt edge
selection bit
1: Segment output SEG
4
–SEG
7
2
0: I/O ports P0
0–P0
3
1: Segment output SEG –SEG11
8
0
0
0
0
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read out,
the contents are “0”.
3
4
5
6
CNTR
0
active edge
0: Falling edge active,
rising edge count
switch bit
1: Rising edge active,
falling edge count
CNTR active edge
switch bit
1
0
7
0: Falling edge a
rising edge
1: Rising e
falling
Fig. 3.5.28 Structure of Interrupt edge selection regi
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode
(CPUM, 3B16
)
b
me
Functions
At reset R W
0
b1 b0
ssor mode
00 : Single-chip mode
01 :
0
0
1
2
3
10 :
11 :
0 : Page 0
1 : Page 1
Not available
Stack page
selection bit
Nothing is arranged for this bit. When this bit is
read out, the contents is “1”. Do not write “0” to
this bit.
Port Xc switch bit
0
4
0: I/O port function
1: XCIN-XCOUT oscillation
function
Main clock (XIN
-
0: Oscillating
1: Stopped
0
1
5
6
XOUT) stop bit
Main clock division
ratio selection bit
0: f(XIN)/2 (high-speed
mode)
1: f(XIN)/8 (middle-speed
mode)
0: XIN–XOUT selection
(middle-/high-speed
mode)
0
7
Internal system
clock selection bit
1: XCIN–XCOUT selection
(low-speed mode)
Fig. 3.5.29 Structure of CPU mode register
38C3 Group User’s Manual
3-53
APPENDIX
3.5 Control registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16
)
b
0
Name
interrupt
request bit
Functions
At reset R W
INT
0
✽
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
0
0 : No interrupt request
issued
1 : Interrupt request issued
INT
1
interrupt
request bit
1
0 : No interrupt request
issued
1 : Interrupt request issued
2 INT
request bit
2 interrupt
0 : No interrupt request
issued
1 : Interrupt request issued
3
4
5
6
7
0 : No interrupt request
issued
1 : Interrupt reques
Serial I/O interrupt
request bit
Timer A interrupt
request bit
0 : No interrupt
issued
1 : Interrusued
Timer 1 interrupt
request bit
0 : No quest
i
1 equest issued
Timer 2 interrupt
request bit
errupt request
ed
terrupt request issued
Timer 3 inte
request
: No interrupt request
issued
1 : Interrupt request issued
✽: “0” by software, but “1” cannot be set.
Fig. 3.5.30 Structure of Interrupregister 1
38C3 Group User’s Manual
3-54
APPENDIX
3.5 Control registers
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16
)
b
0
Name
Timer 4 interrupt
request bit
Timer 5 interrupt
request bit
Timer 6 interrupt
request bit
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
✽
✽
✽
✽
✽
✽
✽
0
0
0
0
0
0
0
0
0 : No interrupt request issued
1 : Interrupt request issued
1
2
3
4
5
6
7
0 : No interrupt request issued
1 : Interrupt request issued
CNTR
request bit
CNTR interrupt
request bit
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
1
0 : No interrupt request issued
1 : Interrupt request issue
Key input interrupt 0 : No interrupt request i
request bit
1 : Interrupt request
AD conversion
interrupt request bit
Nothing is arranged for this bit. Thi
disabled bit. When this bit is reantents
are “0”.
0 : No interrupt re
1 : Interrupt red
✽: “0” can be set by sof1” cannot be set.
Fig. 3.5.31 Structure of Interrupt request regis
38C3 Group User’s Manual
3-55
APPENDIX
3.5 Control registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16
)
b
0
Name
Functions
At reset R W
0
INT
0
interrupt
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
1 INT
interrupt
enable bit
0
1
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
2 INT
2
interrupt
enable bit
Serial I/O interrupt
enable bit
Timer A interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
3
4
Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabl
5
6
7
Timer 2 interrupt
enable bit
0 : Interrupt dis
1 : Interrupt
0
0
Timer 3 interrupt
enable bit
0 : Interru
1 : Inteed
Fig. 3.5.32 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Inl register 2
dress 3F16)
Name
Timer 4 interrupt
enable bit
Functions
At reset R W
0
0 : Interrupt disabled
1 : Interrupt enabled
Timer 5 interrupt
enable bit
Timer 6 interrupt
enable bit
CNTR0 interrupt
enable bit
CNTR1 interrupt
enable bit
0
0
0
0
0
0
0
1
2
3
4
5
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
Key input interrupt
enable bit
0 : interrupt disabled
1 : Interrupt enabled
6 AD conversion
interrupt enable bit
7
0 : interrupt disabled
1 : Interrupt enabled
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
Fig. 3.5.33 Structure of Interrupt control register 2
38C3 Group User’s Manual
3-56
APPENDIX
3.5 Control registers
ROM correct enable register 1
b7 b6 b5 b4 b3 b2 b1 b0
ROM correct enable register 1
(RC1: address 0F0116)
b
0
Name
ROM correct
address 1 enable bit 1: Enabled
Functions
0: Disabled
At reset R W
0
ROM correct
0: Disabled
address 2 enable bit 1: Enabled
ROM correct
0
0
0
0
0
0
0
1
2
3
0: Disabled
address 3 enable bit 1: Enabled
ROM correct
0: Disabled
address 4 enable bit 1: Enabled
4 ROM correct
address 5 enable bit 1: Enabled
ROM correct
0: Disabled
0: Disabled
address 6 enable bit 1: Enabled
ROM correct
address 7 enable bit 1: Enabled
ROM correct
address 8 enable bit 1: En
5
6
7
0: Disabled
0: Disab
Fig. 3.5.34 Structure of ROM correct enable regis
38C3 Group User’s Manual
3-57
APPENDIX
3.6 Mask ROM confirmation form
3.6 Mask ROM confirmation form
GZZ-SH56-24B<91A0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6AXXXFP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
❈ Customer
Date
issued
Date:
❈ 1. Confirmation
Three EPROMs are required for each pattern if this order is performOMs.
One floppy disk is required for each pattern if this order is perforppy disk.
Microcomputer name:
Ordering by EPROMs
M38C34M6AXXXFP
Specify the type of EPROMs submitted.
If at least two of the three sets of EPROMs sontain identical data, we will produce masks based on this data.
We shall assume the responsibility for erthe mask ROM data on the products we produce differs from this
data. Thus, extreme care must be takehe data in the submitted EPROMs.
Checfor entire EPROM
EPROM type (indicate the typ
(hexadecimal notation)
27256
27512
In the address space of the microcomputer, the internal
ROM area is from address A08016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
EPROM address
ROM address
000016
000016
Product name
ASCII code :
‘M38C34M6A’
Product name
ASCII code :
‘M38C34M6A’
000F16
001016
000F16
001016
207F16
208016
A07F16
A08016
data
data
ROM (24K-130) bytes
ROM (24K-130) bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘A’ = 4116
FF16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘4’ = 3416
‘M’ = 4D16
‘6’ = 3616
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
FF16
FF16
FF16
FF16
FF16
FF16
(2) The ASCII codes of the product name “M38C34M6A”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
38C3 Group User’s Manual
3-58
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH56-24B<91A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6AXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
27256
27512
EPROM type
*= $8000
.BYTE ‘M38C34M6A’
*= $0000
.BYTE ‘M38C34M6A’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
Ordering by floppy disk
We will produce masks based on the mask files generated by the nerating utility. We shall assume the
responsibility for errors only if the mask ROM data on the producuce differs from this mask file. Thus, ex-
treme care must be taken to verify the mask file in the submittek.
The submitted floppy disk must be 3.5-inch 2HD type and at. And the number of the mask files must be
1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
❈ 2. Mark specification
Mark specification must be subg the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P634M6AXXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the followuestions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) Which function will you use the pins P70/XCIN and P71/XCOUT as P70 and P71, or XCIN and XCOUT ?
Ports P70 and P71 function
XCIN and XCOUT function (external resonator)
❈4. Comments
(2/2)
38C3 Group User’s Manual
3-59
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH56-25B<91A0>
Mask ROM number
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6MXXXFP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
❈ Customer
Date
issued
Date:
❈ 1. Confirmation
Three EPROMs are required for each pattern if this order is performed b.
One floppy disk is required for each pattern if this order is performed disk.
Microcomputer name:
Ordering by EPROMs
M38C34M6MXXXFP
Specify the type of EPROMs submitted.
If at least two of the three sets of EPROMs submn identical data, we will produce masks based on this data.
We shall assume the responsibility for errors mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to ata in the submitted EPROMs.
Checksuentire EPROM
EPROM type (indicate the type us
(hexadecimal notation)
27256
27512
In the address space of the microcomputer, the internal
ROM area is from address A08016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
EPROM address
address
000016
0016
Product name
ASCII code :
‘M38C34M6M’
Product name
ASCII code :
‘M38C34M6M’
000F16
001016
000F16
001016
207F16
208016
A07F16
A08016
data
data
ROM (24K-130) bytes
ROM (24K-130) bytes
7FFD16
7FFE16
7FFF16
FFFD16
FFFE16
FFFF16
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘4’ = 3416
‘M’ = 4D16
‘6’ = 3616
‘M’ = 4D16
FF16
(2) The ASCII codes of the product name “M38C34M6M”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
38C3 Group User’s Manual
3-60
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH56-25B<91A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6MXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
27256
27512
EPROM type
*= $8000
.BYTE ‘M38C34M6M’
*= $0000
.BYTE ‘M38C34M6M’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
Ordering by floppy disk
We will produce masks based on the mask files generated by the nerating utility. We shall assume the
responsibility for errors only if the mask ROM data on the producuce differs from this mask file. Thus, ex-
treme care must be taken to verify the mask file in the submittek.
The submitted floppy disk must be 3.5-inch 2HD type and at. And the number of the mask files must be
1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
❈ 2. Mark specification
Mark specification must be subg the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P634M6MXXXFP) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the followuestions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) Which function will you use the pins P70/XCIN and P71/XCOUT as P70 and P71, or XCIN and XCOUT ?
Ports P70 and P71 function
XCIN and XCOUT function (external resonator)
❈4. Comments
(2/2)
38C3 Group User’s Manual
3-61
APPENDIX
3.7 ROM programming confirmation form
3.7 ROM programming confirmation form
GZZ-SH56-29B<91A0>
ROM number
Date:
740 FAMILY WRITING TO PROM CONFIRMATION FORM
SINGLE-CHIP 8-BIT MICROCOMPUTER M38C37ECAXXXFP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Supervisor
Submitted by
TEL
(
Company
name
)
❈ Customer
Date
issued
Date:
❈ 1. Confirmation
Three EPROMs are required for each pattern if this order is performOMs.
One floppy disk is required for each pattern if this order is perforoppy disk.
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted tical data, we will produce writing to PROM based on
this data. We shall assume the responsibility for errthe written PROM data on the products we produce dif-
fers from this data. Thus, extreme care must be tify the data in the submitted EPROMs.
Checksum coEPROM
(hexadecimal notation)
EPROM address
EPROM type (indicate the type used)
27512
EPROM address
000016
Product name
ASCII cod
000F16
‘M38C37EC
001016
407F16
408016
Data
ROM 48K-130 bytes
FFFD16
FFFE16
FFFF16
In the address space of the microcomputer, the internal ROM area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘7’ = 3716
‘E’ = 4516
‘C’ = 4316
‘ A ’ =4116
FF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
FF16
FF16
FF16
FF16
FF16
FF16
(2) The ASCII codes of the product name “M38C37ECA”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
38C3 Group User’s Manual
3-62
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH56-29B<91A0>
ROM number
740 FAMILY WRITING TO PROM CONFIRMATION FORM
SINGLE-CHIP 8-BIT MICROCOMPUTER M38C37ECAXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
*= $0000
.BYTE ‘M38C37ECA’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the writing to PROM confirmation
form, the ROM will not be processed.
Ordering by floppy disk
We will produce writing to PROM based on the mask files generatesk file generating utility. We shall as-
sume the responsibility for errors only if the written PROM data octs we produce differs from this mask file.
Thus, extreme care must be taken to verify the mask file in the loppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and at. And the number of the mask files must be
1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
❈ 2. Mark specification
Mark specification must be subg the correct form for the package being ordered. Fill out the appropriate
80P6N mark specification forh it to the writing to PROM confirmation form.
❈ 3. Usage conditions
Please answer the followiquestions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) Which function will you use the pins P70/XCIN and P71/XCOUT as P70 and P71, or XCIN and XCOUT ?
Ports P70 and P71 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
38C3 Group User’s Manual
3-63
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH56-30B<91A0>
ROM number
Date:
740 FAMILY WRITING TO PROM CONFIRMATION FORM
SINGLE-CHIP 8-BIT MICROCOMPUTER M38C37ECMXXXFP
MITSUBISHI ELECTRIC
Section head Supervisor
signature signature
Note : Please fill in all items marked ❈.
Submitted by Supervisor
TEL
(
Company
name
)
❈ Customer
Date
issued
Date:
❈ 1. Confirmation
Three EPROMs are required for each pattern if this order is performed b.
One floppy disk is required for each pattern if this order is performed disk.
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted contadata, we will produce writing to PROM based on
this data. We shall assume the responsibility for errors written PROM data on the products we produce dif-
fers from this data. Thus, extreme care must be taken e data in the submitted EPROMs.
Checksum code foROM
(hexadecimal notation)
EPROM address
EPROM type (indicate the type used)
27512
EPROM address
000016
Product name
ASCII code :
000F16
‘M38C37ECM’
001016
407F16
408016
Data
ROM 48K-130 bytes
FFFD16
FFFE16
FFFF16
In the address space of the microcomputer, the internal ROM area is from address 408016 to FFFD16. The reset vector is
stored in addresses FFFC16 and FFFD16.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘7’ = 3716
‘E’ = 4516
‘C’ = 4316
‘ M ’ =4D16
FF16
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
FF16
FF16
FF16
FF16
FF16
FF16
(2) The ASCII codes of the product name “M38C37ECM”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
(1/2)
38C3 Group User’s Manual
3-64
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH56-30B<91A0>
ROM number
740 FAMILY WRITING TO PROM CONFIRMATION FORM
SINGLE-CHIP 8-BIT MICROCOMPUTER M38C37ECMXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
*= $0000
.BYTE ‘M38C37ECM’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the writing to PROM confirmation
form, the ROM will not be processed.
Ordering by floppy disk
We will produce writing to PROM based on the mask files generatesk file generating utility. We shall as-
sume the responsibility for errors only if the written PROM data octs we produce differs from this mask file.
Thus, extreme care must be taken to verify the mask file in the loppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and at. And the number of the mask files must be
1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
❈ 2. Mark specification
Mark specification must be subg the correct form for the package being ordered. Fill out the appropriate
80P6N mark specification forh it to the writing to PROM confirmation form.
❈ 3. Usage conditions
Please answer the followiquestions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
External clock input
Quartz crystal
Other (
)
At what frequency?
f(XIN) =
MHz
(2) Which function will you use the pins P70/XCIN and P71/XCOUT as P70 and P71, or XCIN and XCOUT ?
Ports P70 and P71 function
XCIN and XCOUT function (external resonator)
❈ 4. Comments
(2/2)
38C3 Group User’s Manual
3-65
APPENDIX
3.8 Mark specification form
3.8 Mark specification form
80P6N (80-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
64
41
40
65
Mitsubishi IC catalog name
Mitsubishi product number
(6-digit, or 7-digit)
80
25
1
24
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
64
41
40
65
er’s Parts Number
: The fonts and size of characters are standard Mitsubishi type.
itsubishi IC catalog name
Notes 1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s parts number can be up to 14 alphanumeric char-
acters for capital letters, hyphens, commas, periods and so on.
80
1
4 : If the Mitsubishi logo
is not required, check the box below.
Mitsubishi logo is not required
C. Special Mark Required
Notes1 :If special mark is to be printed, indicate the desired lay-
out of the mark in the left figure. The layout will be
duplicated technically as close as possible.
Mitsubishi product number (6-digit, or 7-digit) and Mask
ROM number (3-digit) are always marked for sorting the
products.
64
41
40
65
2 : If special character fonts (e,g., customer’s trade mark
logo) must be used in Special Mark, check the box be-
low.
80
25
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
1
24
Special character fonts required
38C3 Group User’s Manual
3-66
APPENDIX
3.9 Package outline
3.9 Package outline
80P6N-A
Plastic 80pin 14✕20mm body QFP
EIAJ Package Code
QFP80-P-1420-0.80
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
MD
HD
D
80
65
1
64
I2
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
0
–
0.3
0.13
13.8
19.8
–
16.5
22.5
0.4
–
Nom
–
Max
3.05
0.2
–
0.45
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.1
10°
–
A
1
0.1
2.8
0.35
0.15
14.0
20.0
0.8
16.8
22.8
0.6
1.4
–
–
0.5
–
14.6
20.6
A2
D
E
e
24
41
25
40
A
L1
H
H
D
E
L
L1
y
–
0°
–
1.3
–
F
e
b
L
b2
F
I2
–
–
y
M
M
D
E
–
–
80D0
Glass seal 80pin QFN
EIAJ Package Code
–
JEDEC Code
–
W
21.0±
18.4±0.15
3.32MAX
1.78TYP
0.8TYP
0.6TYP
41
64
65
40
25
80
1
24 1.2TYP
INDEX
38C3 Group User’s Manual
3-67
APPENDIX
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
OP
69
A
n
BIT,A, R
ZP
n
BIT,ZP, R
ZP, X
ZP, Y
OP
ABS
ABS, X
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
#
n
# OP
2
#
OP
n
# OP
65
#
2
OP
n
#
OP
75
n
4
#
2
n
#
OP
6D
n
4
#
3
OP
7D
n
5
#
OP
79
n
5
#
3
OP
#
n
#
OP
61
n
6
#
OP
71
n
6
#
OP
#
OP
#
N
N
V
V
ADC
(Note 1)
(Note 5)
When T = 0
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A re-
main unchanged, but the contents of status
flags are changed.
2
3
3
2
2
•
←
A
A + M + C
When T = 1
←
M(X)
M(X) + M + C
M(X) represents the contents of memory
where is indicated by X.
AND
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the con-
tents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1, the contents of A
remain unchanged, but status flags are
changed.
29
2
2
25
3
2
35
4
2
2D
4
3
3D
5
3
39
5
3
21
6
2
31
6
2
N
•
•
•
•
•
Z
•
V
←
A
A
M
When T = 1
V
←
M(X)
M(X)
M
M(X) represents the contents of memory
where is indicated by X.
7
0
ASL
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A
2
1
06
5
2
0E
6
3
1E
7
3
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
C
•
←
←
0
C
BBC
(Note 4)
Ai or Mi = 0?
Ai or Mi = 1?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative ad-
dress. If the bit is 1, next instruction is
executed.
13
+
4
2
17
+
5
5
3
3
20i
20i
BBS
(Note 4)
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative ad-
dress. If the bit is 0, next instruction is
executed.
03
+
4
2
07
+
•
•
•
•
•
•
•
•
20i
20i
C = 0?
C = 1?
BCC
(Note 4)
This instruction takes a branch to the ap-
pointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
2
2
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90
B0
F0
BCS
(Note 4)
This instruction takes a branch to the ap-
pointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
Z = 1?
BEQ
(Note 4)
This instruction takes a branch to the ap-
pointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
•
V
A
M
BIT
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
24
3
2
M7 M6
Z
2C
4
3
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
N = 1?
Z = 0?
30
2
2
2
2
BMI
(Note 4)
This instruction takes a branch to the ap-
pointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D0
BNE
(Note 4)
This instruction takes a branch to the ap-
pointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
38C3 Group User’s Manual
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APPENDIX
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n
ZP, X
ZP, Y
OP
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
#
n
# OP
#
n
# OP
#
#
OP
n
#
n
#
OP
#
OP
n
#
OP
#
n
#
#
#
OP
10
#
2
OP
#
N
•
V
•
T
•
B
•
D
•
I
Z
•
C
•
BPL
(Note 4)
N = 0?
This instruction takes a branch to the ap-
pointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
2
•
←
80
BRA
BRK
PC
PC ± offset
This instruction branches to the appointed ad-
dress. The branch address is specified by a
relative address.
4
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
←
B
1
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
1
1
00
7
1
←
←
(PC)
M(S)
(PC) + 2
PCH
←
S
S – 1
←
M(S)
PCL
←
S
S – 1
←
PS
S – 1
M(S)
←
S
←
I
1
←
←
PCL
PCH
ADL
ADH
50
70
2
2
2
2
BVC
(Note 4)
V = 0?
V = 1?
Ai or Mi
This instruction takes a branch to the ap-
pointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
BVS
(Note 4)
This instruction takes a branch to the ap-
pointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
1B
+
2
1
1F
+
5
2
←
CLB
CLC
CLD
CLI
0
This instruction clears the designated bit i of A
or M.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
20i
20i
18
D8
58
12
B8
2
2
2
2
2
1
1
1
1
1
←
←
C
D
0
0
This instruction clears C.
This instruction clears D.
This instruction clears I.
This instruction clears T.
This instruction clears V.
•
•
•
0
•
•
•
←
I
0
•
•
•
0
•
•
•
←
←
CLT
CLV
T
V
0
0
•
•
0
•
•
•
•
•
0
•
•
•
•
•
C9
2
2
3
2
D5
4
2
CD
4
3
DD
5
3
D9
5
3
C1
6
2
D1
6
2
CMP
(Note 3)
When T = 0
A – M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the con-
tents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
N
•
•
•
Z
C
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
__
44
E4
5
3
2
2
←
COM
CPX
M
M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
E0
C0
2
2
2
EC
CC
CE
4
4
6
3
3
3
X – M
Y – M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
C
2
C4
C6
3
5
2
2
CPY
DEC
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
C
•
1A
2
1
←
←
D6
6
2
DE
7
3
A
M
A – 1 or
M – 1
This instruction subtracts 1 from the contents
of A or M.
38C3 Group User’s Manual
38C3 Group User’s Manual
3-70
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APPENDIX
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
OP n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP
ZP, X
ZP, Y
OP n
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
CA
#
1
# OP
#
n
# OP
#
n
#
OP
n
#
#
OP
#
OP
n
#
OP
#
OP
n
#
#
#
OP
#
OP
#
N
N
V
•
T
•
B
•
D
•
I
Z
Z
C
•
←
←
←
2
•
DEX
DEY
DIV
X
Y
A
X – 1
This instruction subtracts one from the current
contents of X.
88
1
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
2
Y – 1
This instruction subtracts one from the current
contents of Y.
(M(zz + X + 1),
M(zz + X )) / A
This instruction divides the 16-bit data in
M(zz+(X)) (low-order byte) and M(zz+(X)+1)
(high-order byte) by the contents of A. The
quotient is stored in A and the one's comple-
ment of the remainder is pushed onto the stack.
E2 16
2
2
←
M(S)
one's comple-
ment of Remainder
←
S
S – 1
2
2
45
3
2
4
55
4D
4
3
5D
5
3
59
5
3
41
6
2
51
6
2
49
N
•
•
•
•
•
Z
•
EOR
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bit-
wise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
–
←
A
A V M
When T = 1
–
←
M(X)
M(X) V M
M(X) represents the contents of memory
where is indicated by X.
E6
5
2
EE
4C
6
3
3
FE
7
3
←
←
3A
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
•
2
1
INC
INX
A
M
A + 1 or
M + 1
This instruction adds one to the contents of A
or M.
E8
C8
1
1
←
2
2
X
X + 1
Y + 1
This instruction adds one to the contents of X.
This instruction adds one to the contents of Y.
←
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
INY
Y
3
6C
5
3
B2
4
2
JMP
If addressing mode is ABS
PCL
PCH
This instruction jumps to the address desig-
nated by the following three addressing
modes:
←
←
ADL
ADH
If addressing mode is IND
Absolute
←
←
PCL
PC
M (ADH, ADL)
M (AD , AD + 1)
Indirect Absolute
Zero Page Indirect Absolute
H
H
L
If addressing mode is ZP, IND
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
←
20
6
3
02
7
2
22
5
2
•
•
•
•
•
•
•
•
JSR
M(S)
PCH
S – 1
This instruction stores the contents of the PC
in the stack, then jumps to the address desig-
nated by the following addressing modes:
Absolute
←
S
←
PCL
S – 1
M(S)
←
S
After executing the above,
Special Page
if addressing mode is ABS,
Zero Page Indirect Absolute
←
←
PCL
PCH
ADL
ADH
if addressing mode is SP,
←
←
PCL
PCH
ADL
FF
If addressing mode is ZP, IND,
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
A9
2
2
A5
3C
3
4
2
3
B5
4
2
AD
4
3
BD
5
3
B9
5
3
A1
6
2
B1
6
2
N
•
•
•
•
•
•
•
•
•
•
Z
•
•
LDA
(Note 2)
When T = 0
When T = 0, this instruction transfers the con-
tents of M to A.
←
A
M
When T = 1
When T = 1, this instruction transfers the con-
tents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
←
M(X)
M
←
•
•
LDM
M
nn
This instruction loads the immediate value in
M.
←
←
A2
A0
2
2
2
2
A6
A4
3
3
2
2
B6
4
2
AE
AC
4
4
3
3
BE
5
3
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
•
LDX
LDY
X
Y
M
M
This instruction loads the contents of M in X.
This instruction loads the contents of M in Y.
B4
4
2
BC
5
3
38C3 Group User’s Manual
38C3 Group User’s Manual
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APPENDIX
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
LSR
Function
Details
IMP
n
IMM
OP n
A
n
2
BIT, A
OP
ZP
n
BIT, ZP
OP
ZP, X
ZP, Y
OP
ABS
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
#
# OP
4A
#
1
n
# OP
46
#
2
n
#
OP
56
n
6
#
2
n
#
OP
4E
n
6
#
3
OP
5E
n
7
#
OP
#
n
#
#
#
OP
#
OP
#
N
0
V
•
T
•
B
•
D
•
I
Z
Z
C
C
5
3
•
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
7
0
→
C
→
0
←
MUL
M(S) • A A ✽M(zz + X) This instruction multiply Accumulator with the
62 15
2
•
•
•
•
•
•
•
•
←
S
S – 1
memory specified by the Zero Page X address
mode and stores the high-order byte of the re-
sult on the Stack and the low-order byte in A.
←
EA
2
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
NOP
PC
PC + 1
This instruction adds one to the PC but does
no otheroperation.
09
2
2
3
2
01
6
2
11
6
2
N
Z
ORA
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the con-
tents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
05
15
4
2
0D
4
3
1D
5
3
5
3
19
←
A
A V M
When T = 1
←
M(X)
M(X) V M
M(X) represents the contents of memory
where is indicated by X.
←
S – 1
PHA
PHP
PLA
PLP
ROL
M(S)
A
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
48
08
68
28
3
3
4
4
1
1
1
1
←
S
←
S – 1
M(S)
PS
This instruction pushes the contents of PS to
the memory location designated by S and dec-
rements the contents of S by one.
←
S
←
←
S
A
S + 1
M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
N
Z
←
S
S + 1
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
(Value saved in stack)
←
PS
M(S)
2A
6A
2
2
1
1
26
6
5
8
2
2
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
•
C
C
•
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
7
←
0
←
36
76
6
6
2
2
2E
6E
6
6
3
3
3E
7E
7
7
3
3
←
C
ROR
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
7
0
→
→
C
RRF
RTI
This instruction rotates 4 bits of the M content
to the right.
7
0
→
→
←
S
S + 1
←
M(S)
S + 1
←
M(S)
S + 1
←
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PCL. S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
(Value saved in stack)
40
60
6
6
1
1
PS
←
S
PCL
←
S
PCH
M(S)
←
RTS
S
S + 1
←
This instruction increments S by one and
stores the contents of the memory location
•
•
•
•
•
•
•
•
PCL
M(S)
←
S
S + 1
designated by S in PCL. S is again
←
←
PCH
(PC)
M(S)
(PC) + 1
incremented by one and the contents of the
memory location is stored in PCH. PC is
incremented by 1.
38C3 Group User’s Manual
38C3 Group User’s Manual
3-74
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APPENDIX
APPENDIX
3.10 Machine instructions
3.10 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n
ZP, X
ZP, Y
OP n
ABS
ABS, X
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
#
OP
E9
n
2
# OP
2
#
n
# OP
E5
#
2
#
OP
n
4
#
2
#
OP
ED
n
4
#
3
OP
FD
n
5
#
OP
F9
n
5
#
3
OP
#
n
#
OP
E1
n
6
#
OP
F1
n
6
#
OP
#
OP
#
N
N
V
V
T
•
B
•
D
•
I
Z
Z
C
C
3
F5
3
2
2
SBC
(Note 1)
(Note 5)
When T = 0
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the con-
tents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
•
_
←
A
A – M – C
When T = 1
_
←
M(X)
M(X) – M – C
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
←
SEB
SEC
SED
SEI
Ai or Mi
1
This instruction sets the designated bit i of A
or M.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
0B
+
2
1
0F
+
5
2
20i
20i
←
←
C
D
1
1
This instruction sets C.
This instruction set D.
This instruction set I.
This instruction set T.
38
F8
78
32
2
2
2
2
1
1
1
1
•
1
•
•
←
I
1
•
1
•
•
←
←
SET
STA
STP
T
M
1
1
•
•
•
A
This instruction stores the contents of A in M.
The contents of A does not change.
85
4
2
2
8D
5
3
9D
6
3
99
6
3
81
7
2
91
7
2
•
•
•
This instruction resets the oscillation control F/ 42
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
2
1
•
•
•
•
←
←
←
←
5
2
STX
STY
TAX
TAY
TST
TSX
TXA
TXS
TYA
WIT
M
M
X
X
Y
This instruction stores the contents of X in M.
The contents of X does not change.
86
84
4
4
2
2
96
8E
8C
5
5
3
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
This instruction stores the contents of Y in M.
The contents of Y does not change.
94
5
2
•
A
This instruction stores the contents of A in X. AA
The contents of A does not change.
2
2
1
1
N
N
N
N
N
•
Z
Z
Z
Z
Z
•
Y
A
This instruction stores the contents of A in Y. A8
The contents of A does not change.
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
←
←
←
←
X
A
S
A
S
X
X
Y
This instruction transfers the contents of S in BA
X.
2
2
2
2
2
1
1
1
1
1
This instruction stores the contents of X in A.
This instruction stores the contents of X in S.
This instruction stores the contents of Y in A.
8A
9A
98
N
•
Z
•
The WIT instruction stops the internal clock C2
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All regis-
ters or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : N, V, and Z flags are invalid in decimal operation mode.
38C3 Group User’s Manual
38C3 Group User’s Manual
3-76
3-77
APPENDIX
3.10 Machine instructions
Symbol
Contents
Symbol
Contents
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
Implied addressing mode
Immediate addressing mode
+
–
✽
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
/
V
V
–
V
–
←
X
Y
ZP, Y
ABS
ABS, X
ABS, Y
IND
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
S
Stack pointer
Program counter
PC
PS
PCH
PCL
ADH
ADL
FF
nn
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate e
Zero pa
Memby address designation of any ad-
dr
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
zz
M
Z
Zero flag
I
D
B
T
V
N
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
M(X)
M(S)
ddress indicated by contents of index
of address indicated by contents of stack
er
ontents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-or-
der bits.
M(ADH,
Negative flag
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
#
Number of bytes
38C3 Group User's Manual
3-78
APPENDIX
3.11 List of instruction code
3.11 List of instruction code
D3 – D0
0000
0001
0010
0011
0100
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
C
1101
D
1110
E
1111
F
Hexadecimal
notation
0
1
2
3
4
D7 – D4
0000
ORA
JSR
BBS
ORA
ZP
ASL
ZP
BBS
0, ZP
ORA
IMM
ASL
A
SEB
0, A
ORA
ABS
ASL
ABS
SEB
0, ZP
BRK
—
PHP
CLC
PLP
SEC
PHA
CLI
—
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IND, X ZP, IND 0, A
ORA
IND, Y
BBC
0, A
ORA
ASL
BBC
ORA
ABS, Y
DEC
A
CLB
0, A
ORA
ASL
CLB
BPL
JSR
CLT
—
—
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ZP, X ZP, X 0, ZP
ABS, X ABS, X 0, ZP
AND
ABS IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
AND
ABS
ROL
ABS
SEB
1, ZP
AND
BMI
BBC
1, A
AND
ROL
BBC
AND
ABS, Y
INC
A
CLB
1, A
LDM
AND
ROL
CLB
SET
STP
—
IND, Y
ZP, X ZP, X 1, ZP
ZP ABS, X ABS, X 1, ZP
EOR
RTI
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
EOR
IMM
LSR
A
SEB
A
JMP
ABS
EOR
ABS
LSR
ABS
SEB
2, ZP
IND, X
EOR
BVC
BBC
2, A
EOR
LSR
BBC
EOR
ABS, Y
EOR
LSR
CLB
—
—
—
IND, Y
ZP, X ZP, X 2, ZP
ABS, X ABS, X 2, ZP
ADC
RTS
MUL
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
A
SEB
3, A
JMP
IND
ADC
ABS
ROR
ABS
SEB
3, ZP
PLA
IND, X ZP, X
ADC
—
BBC
3, A
ADC
ROR
BBC
Y
CLB
3, A
ADC
ROR
CLB
BVS
BRA
—
—
TXA
TXS
TAX
TSX
DEX
—
—
IND, Y
ZP, X ZP, X 3, ZP
ABS, X ABS, X 3, ZP
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
B
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
TYA
TAY
CLV
INY
—
STA
IND, Y
BBC
4, A
STY
STA
S
STA
ABS, Y
CLB
4, A
STA
ABS, X
CLB
4, ZP
BCC
LDY
—
—
—
ZP, X ZP, X
LDA
LDX
BBS
5, A
LDY
ZP
L
BBS
5, ZP
LDA
IMM
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
IMM IND, X IMM
LDA
JMP
BBC
LDX
BBC
LDA
ABS, Y
CLB
LDY
LDA
LDX
CLB
BCS
IND, Y ZP, IND 5, A
ZP, Y 5, ZP
5, A ABS, X ABS, X ABS, Y 5, ZP
CPY
CMP
IMM IND, X
CMP
ZP
DEC
ZP
BBS
6, ZP
CMP
IMM
SEB
6, A
CPY
ABS
CMP
ABS
DEC
ABS
SEB
6, ZP
WIT
CMP
BNE
CMP
DEC
BBC
CMP
ABS, Y
CLB
6, A
CMP
DEC
CLB
—
CLD
INX
—
IND, Y
ZP, X ZP, X 6, ZP
ABS, X ABS, X 6, ZP
CPX
SB
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
SBC
IMM
SEB
7, A
CPX
ABS
SBC
ABS
INC
ABS
SEB
7, ZP
NOP
—
IMM IND, X X
SBC
IND, Y
BBC
7, A
SBC
INC
BBC
SBC
ABS, Y
CLB
7, A
SBC
INC
CLB
BEQ
—
—
SED
—
ZP, X ZP, X 7, ZP
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
38C3 Group User’s Manual
3-79
APPENDIX
3.12 SFR memory map
3.12 SFR memory map
Port P0 (P0)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
002016
002116
002216
002316
002416
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer 5 (T5)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
002516 Timer 6 (T6)
002616
Timer 6 PWM register (T6PWM)
002716
002816
002916
Port P4 (P4)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Port P4 direction register (P4D)
Port P5 (P5)
002A16 Timer 56 mode register (T56M)
φ output control register (CKOUT)
Port P5 direction register (P5D)
Port P6 (P6)
002B16
002C16 Timer A register ) (TAL)
Timer A regisTAH)
Port P6 direction register (P6D)
Port P7 (P7)
002D16
002E16 Compare ) (CONAL)
002F16 Comphigh) (CONAH)
003016 Timegister (TAM)
Port P7 direction register (P7D)
Port P8 (P8)
trol register (TACON)
rol register (ADCON)
001116 Port P8 direction register (P8D)
003116
003
0
6
3616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
001216
001316
conversion register (low) (ADL)
-D conversion register (high) (ADH)
001416
001516
001616 PULL register A (PULLA)
PULL register B (PULLB)
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P8 output selection register (P8SEL)
Serial I/O control register 1 (SIOCON1)
Serial I/O control register 2 (SIOCO
Serial I/O register (SIO)
Segment output enable register (SEG)
LCD mode register (LM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
ROM correct enable register 1 (Note)
0F0A16
0F0B16
0F0C16
0F0D16
0F0E16
0F0116
0F0216
0F0316
ROM correct high-order address register 5 (Note)
ROM correct low-order address register 5 (Note)
ROM correct high-order address register 6 (Note)
ROM correct low-order address register 6 (Note)
ROM correct high-order address register 7 (Note)
ROM correct high-order address register 1 (Note)
ROM correct low-order address register 1 (Note)
0F0416 ROM correct high-order address register 2 (Note)
0F0516 ROM correct low-order address register 2 (Note)
ROM correct high-order address register 3 (Note)
0F0F16 ROM correct low-order address register 7 (Note)
0F1016
0F0616
ROM correct low-order address register 3 (Note)
ROM correct high-order address register 8 (Note)
0F1116 ROM correct low-order address register 8 (Note)
0F0716
ROM correct high-order address register 4 (Note)
ROM correct low-order address register 4 (Note)
0F0816
0F0916
Note: This register is valid only in mask ROM version.
38C3 Group User’s Manual
3-80
APPENDIX
3.13 Pin configuration
3.13 Pin configuration
P4
P4
P4
7
/SRDY
/SCLK1
/SOUT
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
7
26
25
P3
P3
P3
P3
P3
P3
P3
P3
COM
COM
COM
COM
0
1
2
3
4
5
6
7
/SEG24
/SEG25
/SEG26
/SEG27
/SEG28
/SEG29
/SEG30
/SEG31
0
1
2
3
6
5
P4
4
/SIN
P4
3/φ
P42
P41
P40
/T3OUT
/T1OUT
/SCLK2
M38C34M6AXXXFP
AVSS
V
REF
P6
P6
P6
P6
P6
P6
7
6
5
4
3
2
/AN
/AN
/AN
/AN
/AN
/AN
7
6
5
4
3
2
VL1
VL2
VL3
P80
(Top view)
ge type: 80P6N-A
n plastic molded QFP
38C3 Group User’s Manual
3-81
APPENDIX
3.13 Pin configuration
MEMORANDUM
38C3 Group User’s Manual
3-82
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
38C3 Group
Apr. First Edition 1999
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1999 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
38C3 Group
New publication, effective Apr. 1999.
© 1999 MITSUBISHI ELECTRIC CORPORATION.
Specifications subject to change without notice.
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