M38K02F1-XXXFP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38K02F1-XXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总133页 (文件大小：1358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
38K0 Group
REJ03B0192-0300
Rev.3.00
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Oct 05, 2006
DESCRIPTION
Timers ............................................................................. 8-bit ✻ 3
Watchdog timer ............................................................. 16-bit ✻ 1
Serial Interface
•
•
•
The 38K0 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 38K0 group has the USB function, an 8-bit bus interface, a
Serial Interface, three 8-bit timers, and an 8-channel 10-bit A/D
converter, which are available for the PC peripheral I/O device.
The various microcomputers in the 38K0 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
Serial I/O (UART or Clock-synchronized) ...................... 8-bit ✻ 1
A/D converter ................................................ 10-bit ✻ 8 channels
(8-bit reading available)
•
LED direct drive port ................................................................... 4
Clock generating circuit
•
•
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage (L version)
•
FEATURES
System clock/Internal clock division mode
Basic machine-language instructions ....................................... 71
At 12 MHz/2-divide mode(φ = 6 MHz) ................... 4.00 to 5.25 V
At 8 MHz/Through mode (φ = 8 MHz) ................... 4.00 to 5.25 V
At 6 MHz/Through mode (φ = 6 MHz) ................... 3.00 to 5.25 V
Power dissipation
•
•
The minimum instruction execution time .......................... 0.25 µs
✻
(at 8 MHz system clock )
✻
System clock : Reference frequency to internal circuit except
•
USB function
At 5 V power source voltage.................................. 125 mW (typ.)
(at 8 MHz system clock, in through mode)
Memory size
•
ROM ................................................................ 16 K to 32 K bytes
RAM ............................................................... 1024 to 2048 bytes
At 3.3 V power source voltage ................................ 30 mW (typ.)
(at 6 MHz system clock, in through mode)
Programmable input/output ports ............................................. 48
Operating temperature range .................................... –20 to 85°C
Packages
•
•
•
Software pull-up resistors
•
Interrupts .................................................. 15 sources, 15 vectors
FP ............................ PLQP0064GA-A (64-pin 14 ✻ 14 mm LQFP)
HP ............................ PLQP0064KB-A (64-pin 10 ✻ 10 mm LQFP)
•
USB function (Full-Speed USB2.0 specification) ...... 4 endpoints
•
External bus interface ....................................... 8-bit ✻ 1 channel
•
PIN CONFIGURATION (TOP VIEW)
P0
6
7
P2
P2
P2
P2
P2
P2
5
4
3
2
1
0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P0
P4
0
/E
/E
P4
P4
X
DREQ/R
X
D
P4
1
X
DACK/TX
D
2
/E
X
TC/SCLK
3
/E
XA1/SRDY
D0-
P30
P31
P32
M38K07M4L-XXXFP/HP
M38K09F8LFP/HP
D0+
TrON
USBVREF
DVCC
PVCC
PVSS
P3
P3
3
/E
/E
/E
/E
/E
XINT
4
X
CS
P3
5
X
WR
P3
6
X
RD
A0
P3
7
X
P6
P6
P6
3
2
1
(LED
(LED
(LED
3
2
1
)
)
)
P1
0
/DQ
0
/AN
/AN
0
P1
1
/DQ
1
1
Package type : PLQP0064GA-A (64P6U-A)/PLQP0064KB-A (64P6Q-A)
Fig. 1 Pin configuration of 38K0 group
Rev.3.00 Oct 05, 2006 page 1 of 129
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38K0 Group
Fig. 2 Functional block diagram
Rev.3.00 Oct 05, 2006 page 2 of 129
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PIN DESCRIPTION
Table 1. Pin description
Pin
Name
Function
Function except a port function
VCC, VSS
VCCE
• Apply voltage of 3.0 V – 5.25 V (L version) to VCC, and 0 V to VSS.
Power source
• Power source pin for ports P1, P3, P4 and analog circuit. Connect this pin to VCC.
Analog power
source
CNVSS
• This pin controls the operation mode of the chip. Connect this pin to VSS. In the flash memory
CNVSS
mode, this pin becoems VPP power source input pin.
CNVSS2
VREF
• This pin controls the operation mode of the chip. Connect this pin to VSS.
• Reference voltage input pin for A/D converter.
CNVSS2
Analog reference
voltage input
DVCC
PVCC, PVSS
• Power source pin for analog circuit.
• Connect the DVCC and PVCC pins to VCC, and the PVSS pin to VSS.
Analog power
source
RESET
XIN
• Reset input pin for active “L”
Reset input
Clock input
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
USBVREF
• Power source pin for USB port circuit.
USB reference
power source
In Vcc = 4.00 to 5.25 V use the built-in USB reference voltage circuit. In Vcc = 3.60 to 4.00 V apply
3.3 V power supply from the external because use of the built-in USB reference voltage circuit is
prohibited in this voltage range. In Vcc = 3.00 to 3.60 V connect this pin to VCC because use of the
built-in USB reference voltage circuit is prohibited in this voltage range.
TrON
• Output pin to pull-up D0+ by 1.5 kΩ external resistor.
USB reference
voltage output
D0+, D0-
• USB upstream I/O port
• USB input level
USB upstream
I/O
• USB output level output structure
P00–P07
• 8-bit I/O port
• Key input pins (key-on wake up interrupt)
I/O port P0
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Pull-up control is enabled.
P1
P1
0
/DQ
/DQ
0
7
/AN
0
–
• 8-bit I/O port
• A/D converter input pins
• External bus interface function pins
I/O port P1
7
/AN7
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
P20–P27
P30–P32
• 8-bit I/O port
I/O port P2
I/O port P3
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit I/O port
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
P33/ExINT
P34/ExCS
P35/ExWR
P36/ExRD
P37/ExA0
• External bus interface function pins
• CMOS 3-state output structure
P4
P4
P4
0
1
/ExDREQ/RxD
/ExDACK/TxD
/ExTC/SCLK
• 4-bit I/O port
• Serial I/O function pins
• External bus interface function pins
I/O port P4
I/O port P5
I/O port P6
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
2
P4
3/ExA1/SRDY
• CMOS 3-state output structure
P50/INT0
P51/CNTR0
P52/INT1
P53–P57
P60–P63
• 8-bit I/O port
• Interrupt input pin
• Timer X funciton pin
• Interrupt input pin
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• 4-bit I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Output large current for LED drive is enabled.
Rev.3.00 Oct 05, 2006 page 3 of 129
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38K0 Group
PART NUMBERING
Product
M38K0 7 M 4 - XXX FP
Package type
FP : PLQP0064GA-A package
HP : PLQP0064KB-A package
ROM number
Omitted in the flash memory version.
– : Standard
Omitted in the flash memory version.
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used as a
user’s ROM area.
However, they can be programmed or erased in
the flash memory version, so that users can
use them.
Memory type
M : Mask ROM version
F : Flash memory version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 3 Part numbering
Rev.3.00 Oct 05, 2006 page 4 of 129
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38K0 Group
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 38K0 group as follows.
PLQP0064GA-A ...................... 0.8 mm-pitch plastic molded LQFP
PLQP0064KB-A....................... 0.5 mm-pitch plastic molded LQFP
100D0M ........................... 0.65 mm-pitch metal seal PIGGY BACK
Memory Type
Support for mask ROM and flash memory versions.
Memory Size
Flash memory size .......................................................... 32 Kbytes
Mask ROM size ............................................................... 16 Kbytes
RAM size .......................................................... 1024 to 2048 bytes
Memory Expansion Plan
ROM size
(bytes)
: Mass Production
60K
M38K09F8L
32K
16K
8K
M38K07M4L
256
512
1,024
2,048
RAM size (bytes)
Fig. 4 Memory expansion plan
Currently products are listed below.
As of October 2006
Remarks
Table 2. List of 38K0 group products (L version)
ROM size (bytes)
ROM size for User in (
RAM size (bytes)
1024
Package
Product
)
M38K07M4L-XXXFP
M38K07M4L-XXXHP
M38K09F8LFP
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
100D0M
16384
(16254)
Mask ROM version
32768
2048
2048
Flash memory version
(32638)
M38K09F8LHP
M38K09RFS
—
Rev.3.00 Oct 05, 2006 page 5 of 129
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FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 38K0 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The CPU has the 6 registers. The register structure is shown in
Figure 5.
Figure 6 shows the store and the return movement into the stack.
If there are registers other than those described in Figure 5, the
users need to store them with the program.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b0
b0
b0
b0
b7
X
Index register X
Index register Y
b7
Y
b7
S
Stack pointer
b15
b7
PCH
PC
L
Program counter
b7
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
Rev.3.00 Oct 05, 2006 page 6 of 129
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On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PC
(S) (S) – 1
M (S) (PC
H
)
Push return address
on stack
M (S) (PC
(S) (S) – 1
M (S) (PC
H)
L
)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
Push contents of processor
status register on stack
L
)
(S) (S)– 1
Subroutine
Interrupt
Service Routine
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PC
(S) (S) + 1
(PC M (S)
L)
M (S)
(PS)
(S) (S) + 1
(PC M (S)
(S) (S) + 1
(PC M (S)
M (S)
H)
L)
POP return
address
from stack
H)
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
Rev.3.00 Oct 05, 2006 page 7 of 129
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38K0 Group
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
Table 4 Set and clear instructions of each bit of processor status register
N flag
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
–
–
Set instruction
CLI
CLV
Clear instruction
Rev.3.00 Oct 05, 2006 page 8 of 129
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38K0 Group
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16
0 1
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Not used (returns “0” when read)
(Do not write “1” to this bit)
System clock selection bit
0 : Main clock (XIN
)
1 : fSYN
System clock division ratio selection bits
b7 b6
0
0
1
0 : φ = f(system clock)/8 (8-divide mode)
1 : φ = f(system clock)/4 (4-divide mode)
0 : φ = f(system clock)/2 (2-divide mode)
1 : φ = f(system clock) (Through mode)
1
Fig. 7 Structure of CPU mode register
Rev.3.00 Oct 05, 2006 page 9 of 129
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38K0 Group
MEMORY
Interrupt Vector Area
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs. In
the flash memory version, program and erase can be performed in
the reserved area.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
RAM area
000016
RAM size
(bytes)
Address
XXXX16
SFR area
Zero page
004016
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
192
256
010016
384
RAM
512
640
768
XXXX16
896
1024
1536
2048
Not used
SFR area
0FE016
0FFF16
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
YYYY16
ZZZZ16
Reserved ROM area
(128 bytes)
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. 8 Memory map diagram
Rev.3.00 Oct 05, 2006 page 10 of 129
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38K0 Group
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
Port P0 (P0)
Prescaler 12 (PRE12)
Timer 1 (T1)
Port P0 direction register (P0D)
Timer 2 (T2)
Port P1 (P1)
Timer X mode register (TM)
Prescaler X (PREX)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Timer X (TX)
Transmit/Receive buffer register (TB/RB)
Serial I/O status register (SIOSTS)
Port P3 direction register (P3D)
Port P4 (P4)
Reserved (Note)
Port P4 direction register (P4D)
Port P5 (P5)
Reserved (Note)
Reserved (Note)
Port P5 direction register (P5D)
Port P6 (P6)
Reserved (Note)
Reserved (Note)
Port P6 direction register (P6D)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
EXB interrupt source enable register (EXBICON)
USB control register (USBCON)
USB address enable register (USBAE)
USB address 0 register (USBA0)
USB address 1 register (USBA1)
Frame number register Low (FNUML)
Frame number register High (FNUMH)
USB interrupt source enable register (USBICON)
USB interrupt source register (USBIREQ)
Endpoint index register (USBINDEX)
Endpoint field register 1 (EPXXREG1)
Endpoint field register 2 (EPXXREG2)
Endpoint field register 3 (EPXXREG3)
Endpoint field register 4 (EPXXREG4)
Endpoint field register 5 (EPXXREG5)
Endpoint field register 6 (EPXXREG6)
Endpoint field register 7 (EPXXREG7)
003116
003216
003316
EXB interrupt source register (EXBIREQ)
Reserved (Note)
EXB index register (EXBINDEX)
EXB field register 1 (EXBREG1)
003416
003516
003616
003716
EXB field register 2 (EXBREG2)
AD control register (ADCON)
AD conversion register 1 (AD1)
AD conversion register 2 (AD2)
Watchdog timer control register (WDTCON)
Reserved (Note)
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
Serial I/O control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
Reserved (Note)
Port P0 pull-up control register (PULL0)
Reserved (Note)
Port P5 pull-up control register (PULL5)
Interrupt edge selection register (INTEDGE)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
PLL control register (PLLCON)
Reserved (Note)
Reserved (Note)
MISRG
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Endpoint field register 8 (EPXXREG8)
Endpoint field register 9 (EPXXREG9)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Flash memory control register (FMCR)
Reserved (Note)
Note: Do not write any data to these addresses, because these areas are reserved.
Fig. 9 Memory map of special function register (SFR)
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I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Table 5 I/O ports functions
Related SFRs
Pin
Name
Port P0
Input/Output
I/O Format
Non-Port Function
Key-on wake up
Diagram No.
Port P0 pull-up control
register
P00–P07
Input/output,
individual bits
CMOS compatible
input level
(1)
CMOS 3-state output
AD control register
EXB control register
P10–P17
P20–P27
Port P1
CMOS compatible
input level
CMOS 3-state output
(Power source is
VCCE)
A/D conversion input
External bus interface
funciton I/O
(2)
(3)
Port P2
Port P3
CMOS compatible
input level
CMOS 3-state output
P30–P32
CMOS/TTL compat-
ible input level
CMOS 3-state output
(Power source is
VccE)
(4)
(5)
EXB control register
EXB control register
P33/ExINT
External bus interface
funciton output
P34/ExCS
P35/ExWR
P36/ExRD
P37/ExA0
External bus interface
funciton input
(6)
Serial I/O control
register
EXB control register
P40/RxD/
ExDREQ
Port P4
Serial I/O input
External bus interface
funciton output
(7)
(8)
Serial I/O control
register
EXB control register
P41/TxD/
ExDACK
Serial I/O output
External bus interface
funciton input
Serial I/O control
register
EXB control register
P42/SCLK/
ExTC
Serial I/O I/O
External bus interface
funciton input
(9)
Serial I/O control
register
EXB control register
P43/SRDY/
ExA1
Serial I/O output
External bus interface
funciton input
(10)
(11)
Port P5 pull-up control
register
Interrupt edge selection
register
P50/INT0
P52/INT1
Port P5
Port P6
CMOS compatible
input level
CMOS 3-state output
External interrupt input
Timer X mode register
P51/CNTR0
P53–P57
Timer X function I/O
(12)
(13)
(14)
P60–P63
Note: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate poten-
tial, a current will flow from VCC to VSS through the input-stage gate.
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(4) Ports P30–P32
(1) Port P0
VCCE
Pull-up control bit
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
Key-on wake-up input
(5) Port P33
(2) Port P1
VCCE
EXOE
VCCE
External bus interface enable bit
Direction register
External bus interface enable bit
Direction register
Port latch
Data bus
Port latch
Data bus
EXINT output
EXB data output
EXB data input
Output buffer
Input buffer
(6) Ports P34, P35, P36, P37
VCCE
External bus interface enable bit
Direction register
A/D conversion input
Analog input pin selection bit
Data bus
Port latch
(3) Port P2
Direction register
Port latch
EXCS(P34)
EXWR(P35)
EXRD(P36)
EXA0(P37)
External bus interface enable bit
Data bus
Fig. 10 Port block diagram (1)
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(11) Ports P50, P5
2
(7) Port P4
0
Pull-up control bit
Serial I/O enable bit
Receive enable bit
V
CCE
Direction register
Port latch
External bus interface enable bit
Direction register
Data bus
Data bus
Port latch
INT0 (P50), INT1 (P52) interrupt input
E
XDreq output
Serial I/O input
(8) Port P4
1
(12) Port P5
1
Serial I/O enable bit
Receive enable bit
V
CCE
Direction register
Port latch
External bus interface enable bit
Direction register
Port latch
Data bus
Data bus
Pulse output mode
Timer output
Serial I/O output
Dack
CNTR0 interrupt input
E
X
External bus interface enable bit
(13) Ports P53–P57
(9) Port P4
2
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O synchronous clock selection bit
Serial I/O enable bit
Direction register
Port latch
V
CCE
External bus interface enable bit
Direction register
Data bus
Data bus
Port latch
Serial I/O clock output
(14) Port P6
Serial I/O external clock input
Direction register
Port latch
Serial I/O synchronous clock selection bit
External bus interface enable bit
EXTC
Data bus
(10) Port P4
3
Serial I/O mode selection bit
Serial I/O enable bit
S
RDY output enable bit
V
CCE
External bus interface enable bit
Direction register
Data bus
Port latch
Serial I/O output
EXA1
External bus interface enable bit
Fig. 11 Port block diagram (2)
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b7
b0
Port P0 pull-up control register
(PULL0 : address 0FF016
)
P0
P0
P0
P0
P0
P0
P0
P0
0 pull-up control bit
0 : No pull-up
1 : Pull-up
1
pull-up control bit
0 : No pull-up
1 : Pull-up
2
pull-up control bit
0 : No pull-up
1 : Pull-up
3
pull-up control bit
0 : No pull-up
1 : Pull-up
4
pull-up control bit
0 : No pull-up
1 : Pull-up
5
pull-up control bit
0 : No pull-up
1 : Pull-up
6
pull-up control bit
0 : No pull-up
1 : Pull-up
7
pull-up control bit
0 : No pull-up
1 : Pull-up
b7
b0
Port P5 pull-up control register
(PULL5 : address 0FF216
)
P5 pull-up control bit
0
0 : No pull-up
1 : Pull-up
Nothing is arranged for this bit. This is a write disabled bit.
When this bit is read out, the contents are “0”.
P52 pull-up control bit
0 : No pull-up
1 : Pull-up
Nothing is arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0”.
Fig. 12 Structure of port I/O-related registers
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✻Notes on interrupts
INTERRUPTS
When setting the followings, the interrupt request bit may be set to
“1”.
Interrupts occur by fifteen sources: four external, ten internal, and
one software.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address
0FF316), Timer X mode register (address
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
002316
)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
✻Set the corresponding interrupt enable bit to “0” (disabled).
✻Set the interrupt edge select bit (active edge switch bit).
✻Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
✻Set the corresponding interrupt enable bit to “1” (enabled).
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Table 6 Interrupt vector addresses and priority
Interrupt Request
Vector Addresses (Note 1)
Interrupt Source
Priority
High
Low
Generating Conditions
Reset (Note 2)
USB bus reset
USB SOF
1
2
3
4
FFFD16
FFFB16
FFF916
FFF716
FFFC16
FFFA16
FFF816
FFF616
At reset
At detection of USB bus reset signal (2.5 µs interval SE0)
At detection of USB SOF signal
USB device
At detection of resume signal (K state or SE0) or suspend signal (3
ms interval bus idle), or at completion of transaction
External bus
5
FFF416
At completion of reception or transmission or at completion of DMA
transmission
FFF516
INT0
6
7
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
At detection of either rising or falling edge of INT0 input
At timer X underflow
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
Timer X
Timer 1
Timer 2
INT1
8
At timer 1 underflow
9
At timer 2 underflow
10
—
11
At detection of either rising or falling edge of INT1 input
(Note 4)
(Note 3)
Serial I/O
reception
At completion of serial I/O data reception
Serial I/O
transmission
12
FFE416
At completion of serial I/O data transmission
FFE516
CNTR0
13
14
15
16
FFE216
FFE016
FFDE16
FFDC16
At detection of either rising or falling edge of CNTR0 input
At falling of conjunction of input level for port P0 (at input mode)
At completion of A/D conversion
FFE316
FFE116
FFDF16
FFDD16
Key-on wake up
A/D conversion
BRK instruction
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: Nothing is arranged in these vector addresses.
4: Fix bit 1 of interrupt control register 2 (address 003F16) to “0”.
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38K0 Group
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 0FF316
)
INT
Not used (return “0” when read)
INT interrupt edge selection bit
0 interrupt edge selection bit
1
Not used (return “0” when read)
0 : Falling edge active
1 : Rising edge active
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
)
(IREQ1 : address 003C16
)
USB bus reset interrupt request bit
USB SOF interrupt request bit
USB device interrupt request bit
EXB interrupt request bit
INT1 interrupt request bit
Nothing is arranged for this bit. This is a
write disabled bit. When this bit is read
out, the contents are “0”.
INT0 interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
CNTR0 interrupt request bit
Key-on wake-up interrupt request bit
A/D conversion interrupt request bit
Nothing is arranged for this bit. This is a
write disabled bit. When this bit is read
out, the contents are “0”.
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
✻ “0” can be set by software, but “1”
cannot be set.
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
USB bus reset interrupt enable bit
USB SOF interrupt enable bit
USB device interrupt enable bit
EXB interrupt enable bit
INT
1 interrupt enable bit
Fix this bit to “0”.
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
INT0 interrupt enable bit
CNTR0 interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Key-on wake-up interrupt enable bit
A/D conversion interrupt enable bit
Fix this bit to “0”.
✻ “0” can be set by software, but “1”
cannot be set.
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
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38K0 Group
Key Input Interrupt (Key-on Wake Up)
“1” to “0”. An example of using a key input interrupt is shown in
Figure 15, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P00–P03.
A Key-on wake up interrupt request is generated by applying a
falling edge to any pin of port P0 that have been set to input mode.
In other words, it is generated when AND of input level goes from
Port PXx
“L” level output
PULL 0 register
Port P0
direction register = “1”
7
Key input interrupt request
Bit 7 = “0”
✻
✻
✻✻✻
Port P0
latch
7
6
5
4
P0
7
output
output
PULL 0 register
Bit 6 = “0”
Port P0
direction register = “1”
6
✻
✻✻✻
Port P0
latch
P0
6
PULL 0 register
Port P0
direction register = “1”
5
Bit 5 = “0”
✻
✻
✻✻✻
Port P0
latch
P0
P0
5
output
output
PULL 0 register
Port P0
direction register = “1”
4
Bit 4 = “0”
✻
✻
✻✻✻
Port P0
latch
4
PULL 0 register
Bit 3 = “1”
Port P0
direction register = “0”
3
Port P0
Input reading circuit
✻
✻✻✻
Port P0
latch
3
P0
3
input
input
input
input
PULL 0 register
Bit 2 = “1”
Port P0
direction register = “0”
2
✻
✻
✻✻✻
Port P0
latch
2
P0
2
PULL 0 register
Bit 1 = “1”
Port P0
direction register = “0”
1
✻
✻✻✻
Port P0
latch
1
P0
P0
1
PULL 0 register
Bit 0 = “1”
Port P0
0
direction register = “0”
✻
✻
✻✻✻
Port P0
latch
0
0
✻
✻
P-channel transistor for pull-up
✻✻✻ CMOS output buffer
Fig. 15 Connection example when using key input interrupt and port P0 block diagram
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38K0 Group
TIMERS
Timer 1 and Timer 2
The 38K0 group has three timers: timer X, timer 1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is contin-
ued. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1”.
The count source of prescaler 12 is the system clock divided by
16. The output of prescaler 12 is counted by timer 1 and timer 2,
and a timer underflow periodically sets the interrupt request bit.
Timer X
Timer X can each select in one of four operating modes by setting
the timer X mode register.
(1) Timer Mode
The timer counts the count source selected by timer count source
selection bit.
b7
b0
Timer X mode register
(TM : address 002316
)
(2) Pulse Output Mode
The timer counts the system clock divided by 16. Whenever the
contents of the timer reach “0016”, the signal output from the
CNTR0 pin is inverted. If the CNTR0 active edge selection bit is
“0”, output begins at “ H”.
Timer X operating mode bits
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P51 direction register to output mode.
CNTR
0 : Falling edge active for CNTR
Count at rising edge in event counter mode
1 : Rising edge active for CNTR interrupt
0 active edge switch bit
0
interrupt
0
Count at falling edge in event counter mode
Timer X count stop bit
0 : Count start
1 : Count stop
Not used (return “0” when read)
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 pin.
When the CNTR0 active edge selection bit is “0”, the rising edge of
the CNTR0 pin is counted.
When the CNTR0 active edge selection bit is “1”, the falling edge
of the CNTR0 pin is counted.
Fig. 16 Structure of timer X mode register
(4) Pulse Width Measurement Mode
If the CNTR0 active edge selection bit is “0”, the timer counts the
system clock divided by 16 while the CNTR0 pin is at “H”. If the
CNTR0 active edge selection bit is “1”, the timer counts it while the
CNTR0 pin is at “L”.
The count can be stopped by setting “1” to the timer X count stop
bit in any mode. The corresponding interrupt request bit is set
each time a timer underflows.
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38K0 Group
Data bus
Divider
1/16
Prescaler X latch (8)
Prescaler X (8)
Timer X latch (8)
Timer X (8)
System clock
Timer mode
Pulse output
mode
Pulse width
measurement
mode
Timer X interrupt
request bit
CNTR0 active
edge selection bit
Event
counter
mode
Timer X count stop bit
“0”
P51/CNTR0
CNTR0 interrupt
request bit
“1”
CNTR
edge selection bit
0 active
“1”
Q
Q
Toggle
flip-flop
R
T
“0”
Port P5
latch
1
Timer X latch write
Pulse output mode
Port P5
direction
register
1
Pulse output mode
Data bus
Prescaler 12 latch (8)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Divider
1/16
Timer 2 interrupt
request bit
System clock
Timer 1 interrupt
request bit
Fig. 17 Timer block diagram
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SERIAL INTERFACE
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register (bit 6 of ad-
dress 0FE016) to “1”.
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the Trancemit/Receive buffer register.
Data bus
Serial I/O control register
Address 0FE016
Address 002616
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P40/EXDREQ/RxD
Shift clock
Clock control circuit
P42/EXTC/SCLK
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
System clock
Baud rate generator
Address 0FE216
1/4
Clock control circuit
P43/EXA1/SRDY
Falling-edge detector
F/F
Shift clock
Transmit shift register
Transmit buffer register
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
P41/EXDACK/TxD
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 002716
Serial I/O status register
Address 002616
Data bus
Fig. 18 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
D
0
0
D
1
D
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
Serial input RXD
D
D1
D
D
D
D
D
D
2
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 002616
)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Notes
1 : The transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the T
XD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 19 Operation of clock synchronous serial I/O function
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38K0 Group
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O control
register to “0”.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 002616
Address 0FE016
Serial I/O1 control register
OE
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Character length selection bit
7 bits
P40/EXDREQ/RxD
STdetector
Receive shift register
1/16
8 bits
UART control register
SP detector
PE FE
Address 0FE116
Clock control circuit
Serial I/O synchronous clock selection bit
P42/EXTC/SCLK
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
System clock
Baud rate generator
Address 0FE216
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
Transmit interrupt source selection bit
Transmit shift register
P41/EXDACK/TxD
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Address 002716
Serial I/O status register
Address 002616
Data bus
Fig. 20 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0
TBE=0
TSC=0
TSC=1✻
SP
TBE=1
TBE=1
ST
ST
D
0
D1
Serial output T
X
D
D
0
D
1
SP
1 start bit
✻ Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
D
0
D
1
ST
D
0
D1
Serial input RXD
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
Notes
2 : The transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 21 Operation of UART serial I/O function
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[Serial I/O Control Register (SIOCON)] 0FE016
The serial I/O control register contains eight control bits for the se-
rial I/O function.
[UART Control Register (UARTCON)] 0FE116
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer.
[Serial I/O Status Register (SIOSTS)] 002716
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 002616
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is write-
only and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer regis-
ter is “0”.
[Baud Rate Generator (BRG)] 0FE216
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
✻Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
✻Set the serial I/O transmit interrupt enable bit to “0” (disabled).
✻Set the transmit enable bit to “1”.
✻Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
✻Set the serial I/O transmit interrupt enable bit to “1” (enabled).
Rev.3.00 Oct 05, 2006 page 23 of 129
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b7
b0
b7
b0
Serial I/O status register
(SIOSTS : address 002716
Serial I/O control register
(SIOCON : address 0FE016
)
)
BRG count source selection bit (CSS)
0: System clock
1: System clock/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
3
pin operates as ordinary I/O pin
pin operates as SRDY output pin
3
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
b7
b0
UART control register
(UARTCON : address 0FE116
(pins P4
1: Serial I/O enabled
(pins P4 –P4 can operate as serial I/O pins)
0–P43 operate as ordinary I/O pins)
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
0
3
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
Not used (return “0” when read)
(This is a write disabled bit.)
Not used (return “1” when read)
Fig. 22 Structure of serial I/O control registers
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USB FUNCTION
The data buffer of each endpoint can be assigned to any area in
the multi-channel RAM. This feature offers highly efficient memory
usage by avoiding re-buffering and enabling simple data modifica-
tion.
38K0 Group is equipped with a USB function control circuit
(USBFCC) that enables effective interfacing with the host-PC.
This circuit is in compliance with USB2.0’s Full-Speed Transfer
Mode (12 Mbps, equivalent to USB1.1). This circuit also supports
all four transfer-types specified in the standard USB specification.
The USBFCC has four endpoints that can select its transfer type.
Although Endpoint 0 is fixed to Control Transfer, the Endpoints 1
to 3 can be set to Interrupt Transfer, Bulk Transfer, or Isochronous
Transfer.
The transmit/receive data is directly transferred to the data buffer
via the control circuit (direct RAM access type) without disturbing
the CPU operation. This mechanism enables the CPU to transfer
data smoothly with no drop in performance. In addition to this
buffer function, a double-buffer setting will keep a re-buffering stall
at a minimum and increase the overall data throughput (max. 64
bytes X 2 channels).
A dedicated circuit automatically performs stage management for
Control Transfer and packet management for transactions, which
are necessary for matching of data transmit/receive timing, error
detection, and retry after error. This dedicated control circuit en-
ables the user to develop a program or timing design very easily.
Each endpoint can be programmed for data transfer conditions so
that the endpoints are adaptive for all USB device class transfer
systems.
As other special signals control, the endpoints have detection
functions for the USB bus reset signal, resume signal, suspend
signal, and SOF signal, and also have a remote wake-up signal
transmit function.
When completing data transfer or receiving a special signal, the
endpoint generates the corresponding interrupt to the CPU (3 vec-
tors/18 factors).
With all this essential yet comprehensive built-in hardware, your
system using the 38K0 group will be ready for any USB applica-
tion that comes its way.
38K0 Group MCU
Built-in Peripheral
Functions
CPU
Program ROM
Interrupt request
USB Bus
(USB-Host)
External Bus Interface
(EXB)
Multi-channel RAM
USB
Data transmit/Receive path
[Direct RAM Access Type]
Fig. 23 USB function overview
transfer is performed every 5 to 6 cycles and access for a bit-stuff-
ing transfer is performed in up to 7 cycles.
USB Data Transfer
The USB specification promises 12 Mbps data transfer in the full-
speed mode, that is equivalent to 1.5 M bytes per second of data
transactions.
If the EXB function is enabled in the above conditions, this func-
tion generates a maximum wait of 1 clock cycle, so that the
access is performed every 4 to 8 cycles.
However, in USB data transfer, bit-stuffing may be executed de-
pending on the bit patterns of the transfer data, possibly resulting
in 1-byte data (normally 8 bits) handled as up to 10 bits.
Because USB uses asynchronous transfers, the clock cycle of the
USB internal reference clock may change to adjust to the clock
phase. Therefore, the access timing of the USBFCC for the multi-
channel RAM will change owing to the frequency of internal clock φ:
When the USBFCC is operating at φ =8 MHZ, access for a normal
When operating at φ = 6MHZ, a normal access is performed every
4 cycles. If the clock-phase correction of the reference clock oc-
curs, access is performed every 3 to 5 cycles.
If bit stuffing occurs at this clock rate, the access cycle will be ex-
tended to up to 6 cycles. When the EXB function that generates a
maximum 1-wait cycle is used in this condition, the access cycle
will be 2 (min.) to 7 (max.) cycles.
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USB Function Control Circuit (USBFCC)
Block Diagram
The following diagram shows the USBFCC block diagram. The cir-
cuit comprises:
(1) Serial Interface Engine (SIE)
(2) Device Control Unit (DCU)
(3) Internal Memory Interface (MIF)
(4) CPU Interface (CIF)
USB Function Control Circuit
DCU control
DCU status
MIF control
SIE control
SIE status
D0+
D0-
Transmit/Receive
data
Multi-Channel RAM
Fig. 24 USB Function Control Circuit (USBFCC) block diagram
(1) Serial Interface Engine (SIE)
(3) Memory Interface (MIF)
The SIE performs the following USB lower-layer protocols (pack-
ets, transactions):
The MIF controls the flow of data transfer between the SIE and the
multi-channel RAM under the management of the DCU.
•Sampling of receive data and clock, generation of transmit clock
•Serial-to-parallel conversion of transmit/receive data
•NRZI (Non Return Zero Invert) encode/decode
•Bit stuffing/unstuffing
(4) CPU Interface (CIF)
The CIF performs the following functions:
•Mode setting via registers, DCU control signal generation, DCU
status signal reading
•SYNC (Synchronization Pattern) detection, EOP (End of
Packet) detection
•Interrupt signal generation
•USB address detection, endpoint detection
•CRC (Cyclic Redundancy Check) generation and checking
•Internal bus interface control.
(2) Device Control Unit (DCU)
The DCU manages the following USB upper-layer protocols (ad-
dress/endpoint and control-transfer sequence):
•Status control for each endpoint
•Control-transfer sequence control
•Memory interface status control
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USB Port External Circuit Configuration
The operation mode of the USB port driver circuit can be config-
ured by USB control register (address 001016).
Figure 25 and Figure 26 show the USB port external circuit block
diagram.
VREFCON
0
1
Hiz
DVCC
0
Hiz
3.3V output
3.3V output
Normal mode Low-power mode
1
USBVREF status
V
REFE
USBVREF
USB Reference
Voltage Circuit
2.2 µF
0.1 µF
VREFCON
TRON
D0+
TRONCON
TRONE
1.5 kΩ
27 Ω
Full
Speed
X
OUT
“1”
VCO
f
PLL
fUSB
USB
Module
USBE
“0”
UCLKCON
+
-
USBDIFE
USBE
27 Ω
D0-
Full
Speed
USBE
Fig. 25 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (4.0V ≤ VCC ≤ 5.25V)
3.0V to 3.6V
(Note)
USBVREF
0.1 µF
TRON
TRONCON
TRONE
1.5 kΩ
27 Ω
D0+
Full
Speed
X
OUT
“1”
fVCO
PLL
fUSB
USB
Module
USBE
“0”
UCLKCON
+
-
USBDIFE
USBE
27 Ω
D0-
Full
Speed
Note: In Vcc = 3.0 V to 3.6 V connect this pin to Vcc.
USBE
Fig. 26 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (3.0V ≤ VCC ≤ 4.0V)
Rev.3.00 Oct 05, 2006 page 27 of 129
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Endpoint Buffer Area Setting
Memory
000016
0FED16
00
The buffer area used in data transfer can be assigned to any area
0FED16 = 15h
0010 1010 0000
of the multi-channel RAM for each endpoint.
Disabled to be used
SFR
002016
004016
006016
01
02
03
0000
✻Buffer area beginning address
The buffer area configuration register (address 0FED16) defines
the beginning address of the buffer area (every 32 bytes) for each
Endpoint. However, the only RAM area is configurable.
•00h [Address 000016], 01h [Address 002016]: Not configurable
•02h [Address 004016] to 1Fh [Address 03E016]: Configurable
RAM
15
1F
02A016
03E016
✻Interrupt-source dependant buffer area offset address
An offset value is added to the beginning address of each source,
which is specified by the interrupt source register (address
001D16), for each endpoint.
Fig. 27 Example setting of buffer area beginning address
This section describes in detail the beginning address specified by
the buffer area set register as offset address 00h, according to
each endpoint.
•In double buffer mode (DBLB01 = “1”):
Endpoint 01 has two kinds of interrupt sources for accessing the
buffer.
B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h
B1RDY01 (Buffer 1 Ready Interrupt):
(1) Endpoint 00
Endpoint 00 has two kinds of interrupt sources for accessing the
buffer. The respective address offsets are:
•BSRDY00 (SETUP Buffer Ready Interrupt): Offset address = 00h
•BRDY00 (OUT or IN Buffer Ready Interrupt):
Offset address = 08h
The offset address varies according to the double buffer begin-
ning address set bit (BSIZ01).
-Offset address = 08h when BSIZ01 = 00
-Offset address = 10h when BSIZ01 = 01
-Offset address = 40h when BSIZ01 = 10
-Offset address = 80h when BSIZ01 = 11
(2) Endpoint 01
The buffer area offset address for each interrupt source for of End-
point 01 varies according to the contents of the EP01 set register
(address 001916).
(3) Endpoints 02 and 03
Same as Endpoint 01.
•In single buffer mode (DBLB01 = “0”):
Endpoint 01 has only one interrupt source for accessing the
buffer.
Notes
The selected RAM area must be within addresses 004016 to
B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h
03FF16.
Make sure the buffer area beginning address is set in agreement
with the offset address and the number of transmit/receive data
bytes.
This is particularly important when in the double buffer mode or
when handling 64-byte data.
(a) When selecting Endpoint 00
(b) When selecting Single Buffer Mode
(c) When selecting Double Buffer Mode
(when BSIZ01 = 11)
Offset
Offset
00
Offset
Memory
02A016
Memory
02A016
Memory
02A016
h
00
h
h
00h
BSRDY00
BRDY00
B0RDY01
B1RDY01
02A816
08h
B0RDY01
032016
80
Fig. 28 Examples of interrupt source dependant buffer area offset address
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38K0 Group
USB Interrupt Function
USB Interrupt Control Circuit (USBINTCON) has 3 requests and
16 USB-device interrupt request sources. Each interrupt source
register enables the user to easily determine which interrupt has
occurred.
Table 7 shows the list of USB interrupt sources.
Table 7 USB interrupt sources
Interrupt request bit
USB interrupt bit
(USBIREQ: Address 001716)
—
Interrupt source
At USB bus reset signal detection:
(IREQ1: Address 003C16
)
USB bus reset
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 2.5 µs SE0 state is detected in D0+/D0- port.
(Equivalent to 120-clock length when fUSB = 48 MHz)
At SOF packet receive:
USB SOF
—
After enabling the USB module (USBE = “1”), an interrupt request occurs
when SOF packet is detected in D0+/D0- port.
Its occurrence does not depend on frame-time or CRC value after SOF
packet is transferred.
(Normally, SOF packet detection occurs only when fUSB = 48 MHz)
At Endpoint 00 data transfer complete:
•Buffer ready (read/write enabled state)
•Control transfer completed
USB device
EP00
•Status stage transition
•SETUP buffer ready (read enabled state)
•Control transfer error
At Endpoint 01 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
EP01
EP02
At Endpoint 02 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At Endpoint 03 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
EP03
At suspend signal detection:
SUS
RSM
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 3 ms J state is detected in D0+/D0- port.
(Equivalent to 144,000 clock-length when fUSB = 48MHz)
At resume signal detection:
After enabling the USB module (USBE = “1”) and resume interrupt (RSME
= “1”), an interrupt request occurs when a bus state change (J state to
SE0 or K state) is detected in D0- port.
Rev.3.00 Oct 05, 2006 page 29 of 129
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[EPXXREG5]
[USBIREQ]
[USBICON]
EP00E
[EP00REQ]
BRDY00
CTEND00
CTSTS00
BSYDY00
ERR00
USB device
interrupt request
EP00
[EP01REQ]
EP01E
EP02E
EP03E
B0RDY01
B1RDY01
ERR01
EP01
EP02
EP03
[EP02REQ]
B0RDY02
B1RDY02
ERR02
[EP03REQ]
B0RDY03
B1RDY03
ERR03
SUSE
RSME
SUS
RSM
Fig. 29 USB device interrupt control
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USB Register List
The USB register list is shown below.
USB SFR
Address
Register Name
SYMBOL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
USB control register
USBCON
USBE
UCLKCON
USBDIFE
VREFE
VREFCON
TRONE
TRONCON
WKUP
AD0E
USB Function enable register
USB function address register
USBAE
USBA0
USBADD0[6:0]
Frame number register Low
Frame number register High
USB interrupt source enable register
USB interrupt source register
Endpoint index register
FNUML
FNUM[7:0]
FNUMH
FNUM[10:8]
EP01E
USBICON
USBIREQ
RSME
RSM
SUSE
SUS
EP03E
EP03
EP02E
EP02
EP00E
EP00
EP01
USBINDEX
EPXXREG1
EPXXREG2
EPXXREG3
EPXXREG4
EPXXREG5
EPXXREG6
EPXXREG7
EPXXREG8
EPXXREG9
EPIDX[1:0]
Endpoint field register 1
Endpoint field register 2
Endpoint field register 3
001C16 Endpoint field register 4
001D16 Endpoint field register 5
001E16
001F16
Endpoint field register 6
Endpoint field register 7
0FEC16 Endpoint field register 8
0FED16 Endpoint field register 9
(1) Endpoint 00
001916
EP00 stage register
EP00STG
EP00CON1
EP00CON2
EP00CON3
EP00REQ
EP00BYT
SETUP00
PID00[1:0]
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
EP00 control register 1
EP00 control register 2
EP00 control register 3
EP00 interrupt source register
EP00 byte number register
BVAL00
CTENDE00
BRDY00
ERR00
BSRDY00
CTSTS00
CTEND00
BBYT00[3:0]
EP00 buffer area set register
EP00BUF
BADD00[4:0]
DBLB01
(2) Endpoint 01
001916
001A16
001B16
EP01 set register
EP01CFG
EP01CON1
EP01CON2
EP01CON3
EP01REQ
EP01BYT0
EP01BYT1
EP01MAX
EP01BUF
TYP01[1:0]
DIR01
ITMD01
SQCL01
BSIZ01[1:0]
PID01[1:0]
B0VAL01
EP01 control register 1
EP01 control register 2
001C16 EP01 control register 3
B1VAL01
B0RDY01
001D16 EP01 interrupt source register
ERR01
B1RDY01
001E16
001F16
EP01 byte number register 0
EP01 byte number register 1
B0BYT01[6:0]
B1BYT01[6:0]
MXPS01[6:0]
0FEC16 EP01 MAX. packet size register
0FED16 EP01 buffer area set register
BADD01[4:0]
DBLB02
(3) Endpoint 02
001916
EP02 set register
EP02CFG
EP02CON1
EP02CON2
EP02CON3
EP02REQ
EP02BYT0
EP02BYT1
EP02MAX
EP02BUF
TYP02[1:0]
DIR02
ITMD02
SQCL02
BSIZ02[1:0]
PID02[1:0]
B0VAL02
001A16
001B16
001C16
001D16
001E16
001F16
EP02 control register 1
EP02 control register 2
EP02 control register 3
EP02 interrupt source register
EP02 byte number register 0
EP02 byte number register 1
B1VAL02
B0RDY02
ERR02
B1RDY02
B0BYT02[6:0]
B1BYT02[6:0]
MXPS02[6:0]
0FEC16 EP02 MAX. packet size register
0FED16 EP02 buffer area set register
BADD02[4:0]
DBLB03
(4) Endpoint 03
001916
EP03 set register
EP03CFG
EP03CON1
EP03CON2
EP03CON3
EP03REQ
EP03BYT0
EP03BYT1
EP03MAX
EP03BUF
TYP03[1:0]
DIR03
ITMD03
SQCL03
BSIZ03[1:0]
PID03[1:0]
B0VAL03
001A16
001B16
EP03 control register 1
EP03 control register 2
001C16 EP03 control register 3
B1VAL03
B0RDY03
001D16 EP03 interrupt source register
ERR03
B1RDY03
001E16
001F16
EP03 byte number register 0
EP03 byte number register 1
B0BYT03[6:0]
B1BYT03[6:0]
MXPS03[6:0]
0FEC16 EP03 MAX. packet size register
0FED16 EP03 buffer area set register
BADD03[4:0]
: Not used
Fig. 30 USB related registers
Rev.3.00 Oct 05, 2006 page 31 of 129
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USB Related Registers
The USB related registers are shown below.
b0
b7
USB control register (USBCON) [address 001016
]
At reset
H/W S/W
Bit name
Function
R W
O O
Bit symbol
WKUP
Remote wakeup bit
0 : Returning to BUS idle state by writing “1” first and
then “0”. (Remote wakeup signal)
0
–
1 : K-state output
TRONCON TrON output control bit
TRONE TrON output enable bit
0 : “L” output mode (valid in TRONE = “1”)
1 : “H” output mode (valid in TRONE = “1”)
0 : TrON port output disabled (Hi-Z state)
1 : TrON port output enabled
0
0
0
0
0
0
0
–
–
–
–
–
–
–
O O
O O
O O
O O
O O
O O
O O
VREFCON USB reference voltage control bit 0 : Normal mode (valid in VREFE = “1”)
1 : Low current mode (valid in VREFE = “1”)
VREFE
USB reference voltage enable bit 0 : USB reference voltage circuit operation disabled
1 : USB reference voltage circuit operation enabled
USBDIFE
USB difference input enable bit 0 : Upstream-port difference input circuit operation disabled
1 : Upstream--port difference input circuit operation enabled
UCLKCON USB clock select bit
0 : External oscillating clock f(XIN
)
1 : PLL circuit output clock fVCO
USBE
USB module operation enable bit 0 : USB module reset
1 : USB module operation enabled
–: State remaining
Fig. 31 Structure of USB control register
b0
b7
0
USB function enable register (USBAE) [address 001116
]
0
0
0
0
0
0
At reset
R W
Bit symbol
AD0E
Function
Bit name
H/W S/W
USB function enable bit
0: USB function address register invalidated
1: USB function address register validated
Write “0” when writing.
0
–
O O
O O
b7:b1
Not used
–
–
“0” is read when reading.
–: State remaining
Fig. 32 Structure of USB function enable register
Rev.3.00 Oct 05, 2006 page 32 of 129
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38K0 Group
b0
b7
0
USB function address register (USBA0) [address 001216
]
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
USBADD0 USB function address bit
[6:0]
In AD0E = “0”, this value changes after writing.
In AD0E = “1”, this value changes after completion of
SET_ADDRESS control transferring.
Write “0” when writing.
0
0
b7
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 33 Structure of USB function address register
b0
b7
Frame number register Low (FNUML) [address 001416
]
At reset
R W
Bit symbol
Function
The frame number is updated at SOF reception.
Bit name
H/W S/W
FNUM
[7:0]
Frame number low bit
In-
In-
O ✻
definite definite
Fig. 34 Structure of Frame number register Low
b0
b7
0
0
0
0
0
Frame number register High (FNUMH) [address 001516]
At reset
H/W S/W
Bit symbol
Function
R W
Bit name
In-
In-
FNUM
[10:8]
b7:b3
Frame number high bit
The frame number is updated at SOF reception.
O
✻
definite definite
–
–
Not used
Write “0” when writing.
O O
“0” is read when reading.
–: State remaining
Fig. 35 Structure of Frame number register High
Rev.3.00 Oct 05, 2006 page 33 of 129
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38K0 Group
b0
b7
USB interrupt source enable register (USBICON) [address 001616
]
0
0
At reset
H/W S/W
Bit symbol
EP00E
Function
Bit name
R W
O O
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Write “0” when writing.
0
0
0
0
–
0
0
0
0
0
0
–
0
0
USB function/Endpoint 0 interrupt
enable bit
EP01E
EP02E
EP03E
b5:b4
USB function/Endpoint 1 interrupt
enable bit
O O
O O
O O
O O
O O
O O
USB function/Endpoint 2 interrupt
enable bit
USB function/Endpoint 3 interrupt
enable bit
Not used
“0” is read when reading.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
SUSE
RSME
Suspend interrupt enable bit
Resume interrupt enable bit
–: State remaining
Fig. 36 Structure of USB interrupt source enable register
Rev.3.00 Oct 05, 2006 page 34 of 129
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38K0 Group
b0
b7
USB interrupt source register (USBIREQ) [address 001716
]
0
0
At reset
H/W S/W
R W
Bit symbol
Bit name
Function
EP00
EP01
EP02
EP03
USB function/Endpoint 0
interrupt bit
This bit is set to “1” when any one of EP00 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP00 interrupt
source register to “0016”.
0
0
0
0
0
0
0
0
O
O
O
O
✻
✻
✻
✻
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP01 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP01 interrupt
source register to “0016”.
USB function/Endpoint 1
interrupt bit
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP02 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP02 interrupt
source register to “0016”.
USB function/Endpoint 2
interrupt bit
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP03 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP03 interrupt
source register to “0016”.
USB function/Endpoint 3
interrupt bit
Writing to this bit causes no state change.
Write “0” when writing.
b5:b4
SUS
Not used
–
–
O O
O O
“0” is read when reading.
Suspend interrupt bit
0 : No interrupt request issued
0
0
1 : Interrupt request issued
This bit is set to “1” when detecting 3 ms or more of J-
state, using USB clock (fUSB) at 48 MHz.
“0” can be set by software, but “1” cannot be set.
This bit is set to “1” when the USB bus state changes
from J-state to K-state or SE0 in the resume interrupt
enable bit = “1”. It is also “1” in the condition of internal
clock stopped.
RSM
Resume interrupt bit
0
0
O
✻
This bit is cleared to “0” by clearing the resume
interrupt enable bit.
Writing to this bit causes no state change.
–: State remaining
Fig.37 Structure of USB interrupt source register
b0
b7
0
Endpoint index register (USBINDEX) [address 001816
]
0
0
0
0
0
At reset
R W
Bit symbol
EPIDX [1:0] Endpoint index bit
Function
Bit name
H/W S/W
b1 b0
0
–
O O
0
0
1
1
0 : Endpoint 0
1 : Endpoint 1
0 : Endpoint 2
1 : Endpoint 3
b7:b3
Not used
Write “0” when writing.
“0” is read when reading.
–
–
O O
–: State remaining
Fig. 38 Structure of Endpoint index register
Rev.3.00 Oct 05, 2006 page 35 of 129
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38K0 Group
(1) Endpoint 00
b0
b7
EP00 stage register (EP00STG) [address 001916
]
0
0
0
0
0
0
0
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
SETUP00
b7:b1
SETUP packet detection bit
This bit is set to “1” at reception of SETUP packet.
Writing “0” to this bit clears this bit if the next SETUP
token does not occur.
1
1
Writing “1” to this bit causes no state change of the
status flags.
Not used
Write “0” when writing.
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 39 Structure of EP00 stage register
b0
b7
0
EP00 control register 1 (EP00CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID00 [1:0] Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 40 Structure of EP00 control register 1
b0
b7
0
0
0
0
0
0
0
EP00 control register 2 (EP00CON2) [address 001B16]
At reset
R W
Bit symbol
BVAL00
Function
Bit name
Buffer enable bit
H/W S/W
O O
0
–
0 : NAK transmission (SIE is disabled to read a buffer.)
1 : Transmitting/receiving data set state (SIE is possible
to read from/write to a buffer.)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
O O
b7:b1
Not used
–
–
“0” is read when reading.
–: State remaining
Fig. 41 Structure of EP00 control register 2
Rev.3.00 Oct 05, 2006 page 36 of 129
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38K0 Group
b0
b7
EP00 control register 3 (EP00CON3) [address 001C16
]
0
0
0
0
0
0
0
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
CTENDE00 Control transfer completion
enable bit
0
–
0 : NAK transmission in the status stage
1 : Control transfer completion enabled (SIE transmits
NULL/ACK.) (valid in PID00 = “012”)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
b7:b1
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 42 Structure of EP00 control register 3
b0
b7
0
EP00 interrupt source register (EP00REQ) [address 001D16
]
0
0
At reset
R W
Bit symbol
BRDY00
Function
USB function/Endpoint 0 buffer 0: No interrupt request issued
Bit name
H/W S/W
0
0
O O
ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
CTEND00
CTSTS00
USB function/Endpoint 0 control 0: No interrupt request issued
transfer completion interrupt bit 1: Interrupt request issued
0
0
O O
This bit is set to “1” when control transfer is completed
(NULL/ACK transmission in the status stage) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 0 status 0: No interrupt request issued
0
0
O O
stage transition interrupt bit
1: Interrupt request issued
This bit is set to “1” when transition to status stage
occurs in CTENDE00 = “0” (control transfer completion
disabled) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
<Transition to status stage occurrence factor>
At transfer of control write:
When receiving IN-token in data stage (OUT)
At transfer of control read:
When receiving OUT-token in data stage (IN)
At no data transfer:
Nothing occurs.
BSRDY00
ERR00
USB function/Endpoint 0 SETUP 0: No interrupt request issued
0
0
0
0
O O
buffer ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the exclusive buffer for
SETUP is ready state (enabled to be read) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
USB function/Endpoint 0 error
interrupt bit
O O
1: Interrupt request issued
This bit is set to “1” when control transfer error occurs
on USB function/Endpoint 0.
This bit is cleared to “0” by the hardware when
receiving SETUP token.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
b7:b5
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 43 Structure of EP00 interrupt source register
Rev.3.00 Oct 05, 2006 page 37 of 129
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38K0 Group
b0
b7
EP00 byte number register (EP00BYT) [address 001E16
]
0
0
0
0
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
BBYT00
[3:0]
OUT : The received byte number is automatically set.
IN : Set the transmitting byte number.
Write 0 when writing.
0
—
—
Transmit/receive byte number bit
Not used
b7:b4
—
O O
0 is read when reading.
—: State remaining
Fig. 44 Structure of EP00 byte number register
b0
b7
0
EP00 buffer area set register (EP00BUF) [address 0FED16
]
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
BADD00
[4:0]
EP00 beginning address set bit Set the beginning address of EP00’s buffer area.
0
–
O O
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
b7:b5
Not used
Write “0” when writing.
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 45 Structure of EP00 buffer area set register
Rev.3.00 Oct 05, 2006 page 38 of 129
REJ03B0192-0300
38K0 Group
(2) Endpoint 01
b0
b7
EP01 set register (EP01CFG) [address 001916
]
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
BSIZ01
[1:0]
Double buffer beginning address set In double buffer mode set the beginning address of
0
–
bit
buffer 1 area, using a relative value for the beginning
address of buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
DBLB01
SQCL01
Buffer mode select bit
0 : Single buffer mode
0
0
–
–
O O
O O
1 : Double buffer mode
Sequence toggle bit clear bit
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
ITMD01
DIR01
Interrupt toggle mode select bit 0 : Normal mode
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0
0
0
–
–
–
O O
O O
O O
Transfer direction bit
0 : OUT (Data is received from the host.)
1 : IN (Data is transmitted to the host.)
b7b6
TYP01
[1:0]
Transfer type bite
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
–: State remaining
Fig. 46 Structure of EP01 set register
b0
b7
0
EP01 control register 1 (EP01CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID01
[1:0]
Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 47 Structure of EP01 control register 1
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38K0 Group
b0
b7
0
0
0
0
0
0
0
EP01 control register 2 (EP01CON2) [address 001B16
]
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
B0VAL01
0
–
Buffer 0 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
b7:b1
–
–
O O
Not used
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 48 Structure of EP01 control register 2
b0
b7
0
EP01 control register 3 (EP01CON3) [address 001C16
]
0
0
0
0 0 0
At reset
R W
Bit symbol
B1VAL01
Function
Bit name
Buffer 1 enable bit
H/W S/W
0
–
O O
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
Write “0” when writing.
b7:b1
–
–
O O
Not used
“0” is read when reading.
–: State remaining
Fig. 49 Structure of EP01 control register 3
b0
b7
0
EP01 interrupt source register (EP01REQ) [address 001D16
]
0
0
0
0
At reset
R W
Bit symbol
B0RDY01
Function
Bit name
H/W S/W
0
0
USB function/Endpoint 1 buffer 0
ready interrupt bit
O O
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
B1RDY01
0
0
USB function/Endpoint 1 buffer 1
ready interrupt bit
O O
1: Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 1
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
ERR01
b7:b3
0
0
USB function/Endpoint 1 error
interrupt bit
O O
O O
1: Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
–
–
Not used
“0” is read when reading.
Fig. 50 Structure of EP01 interrupt source register
Rev.3.00 Oct 05, 2006 page 40 of 129
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38K0 Group
b0
b7
0
EP01 byte number register 0 (EP01BYT0) [address 001E16
]
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
0
–
IN : Transmit byte number bit
B0BYT01
[6:0]
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
0
–
OUT : Receive byte number bit
O ✻
Single buffer mode : The received byte number is
automatically set.
Double buffer mode :The received byte number of buffer 0
is automatically set.
–
–
Not used
O O
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 51 Structure of EP01 byte number register 0
b0
b7
0
EP01 byte number register 1 (EP01BYT1) [address 001F16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
0
–
–
–
–
IN : Transmit byte number bit
O O
B1BYT01
[6:0]
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
OUT : Receive byte number bit
Not used
O ✻
Single buffer mode: These bits are invalid.
Double buffer mode :The received byte number of buffer 1
is automatically set.
b7
O O
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 52 Structure of EP01 byte number register 1
b0
b7
0
EP01 MAX. packet size register (EP01MAX) [address 0FEC16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
–
MXPS01
[6:0]
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
Max. packet size bit
O O
O O
–
–
b7
Not used
“0” is read when reading.
–: State remaining
Fig. 53 Structure of EP01 MAX. packet size register
Rev.3.00 Oct 05, 2006 page 41 of 129
REJ03B0192-0300
38K0 Group
b0
b7
EP01 buffer area set register (EP01BUF) [address 0FED16
]
0
0
0
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
BADD01
[4:0]
EP01 beginning address set bit Set the beginning address of EP01’s buffer area.
0
–
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 54 Structure of EP01 buffer area set register
Rev.3.00 Oct 05, 2006 page 42 of 129
REJ03B0192-0300
38K0 Group
(3) Endpoint 02
b0
b7
EP02 set register (EP02CFG) [address 001916
]
At reset
Bit symbol
Bit name
R W
O O
Function
H/W S/W
BSIZ02
[1:0]
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1
0
–
bit
area, using a relative value for the beginning address of
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
DBLB02
SQCL02
Buffer mode select bit
0 : Single buffer mode
1 : Double buffer mode
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
0
0
–
–
O O
O O
Sequence toggle bit clear bit
“0” is always read when reading.
ITMD02
DIR02
Interrupt toggle mode select bit 0 : Normal mode
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0
0
0
–
–
–
O O
O O
O O
Transfer direction bit
0 : OUT (Data is received from the host.)
1 : IN (Data is transmitted to the host.)
b7b6
TYP02
[1:0]
Transfer type bite
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
–: State remaining
Fig. 55 Structure of EP02 set register
b0
b7
0
EP02 control register 1 (EP02CON1) [address 001A16
]
0
0
0
0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID02
[1: 0]
Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 56 Structure of EP02 control register 1
Rev.3.00 Oct 05, 2006 page 43 of 129
REJ03B0192-0300
38K0 Group
b0
b7
EP02 control register 2 (EP02CON2) [address 001B16
]
0
0
0
0
0
0
0
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
B0VAL02
0
–
Buffer 0 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
b7:b1
–
–
O O
Not used
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 57 Structure of EP02 control register 2
b0
b7
0
0
0
0
0
0
0
EP02 control register 3 (EP02CON3) [address 001C16
]
At reset
R W
Bit symbol
B1VAL02
Function
Bit name
Buffer 1 enable bit
H/W S/W
0
–
O O
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
Write “0” when writing.
b7:b1
–
–
O O
Not used
“0” is read when reading.
–: State remaining
Fig. 58 Structure of EP02 control register 3
b0
b7
0
EP02 interrupt source register (EP02REQ) [address 001D16
]
0
0
0
0
At reset
R W
Bit symbol
B0RDY02
Function
Bit name
H/W S/W
0
0
USB function/Endpoint 2 buffer 0
ready interrupt bit
O O
0 : No interrupt request issued
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
B1RDY02
0
0
USB function/Endpoint 2 buffer 1
ready interrupt bit
O O
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 2
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
ERR02
0
0
USB function/Endpoint 2 error
interrupt bit
O O
O O
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
b7 to b3
–
–
Not used
“0” is read when reading.
Fig. 59 Structure of EP02 interrupt source register
Rev.3.00 Oct 05, 2006 page 44 of 129
REJ03B0192-0300
38K0 Group
b0
b7
0
EP02 byte number register 0 (EP02BYT0) [address 001E16
]
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
0
–
IN : Transmit byte number bit
B0BYT02
[6:0]
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
0
–
OUT : Receive byte number bit
O ✻
Single buffer mode: The received byte number is
automatically set.
Double buffer mode :The received byte number of buffer 0
is automatically set.
–
–
Not used
O O
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 60 Structure of EP02 byte number register 0
b0
b7
0
EP02 byte number register 1 (EP02BYT1) [address 001F16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
0
–
–
–
–
IN : Transmit byte number bit
O O
O ✻
O O
B1BYT02
[6:0]
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
OUT : Receive byte number bit
Not used
Single buffer mode: These bits are invalid.
Double buffer mode :The received byte number of buffer 1
is automatically set.
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 61 Structure of EP02 byte number register 1
b0
b7
0
EP02 MAX. packet size register (EP02MAX) [address 0FEC16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
–
MXPS02
[6:0]
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
Max. packet size bit
O O
O O
–
–
b7
Not used
“0” is read when reading.
–: State remaining
Fig. 62 Structure of EP02 MAX. packet size register
Rev.3.00 Oct 05, 2006 page 45 of 129
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38K0 Group
b0
b7
EP02 buffer area set register (EP02BUF) [address 0FED16
]
0
0
0
At reset
R W
O O
Bit symbol
Bit name
Function
H/W S/W
BADD02
[4:0]
EP02 beginning address set bit
Set the beginning address of EP02’s buffer area.
(32-byte unit)
0
–
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 63 Structure of EP02 buffer area set register
Rev.3.00 Oct 05, 2006 page 46 of 129
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38K0 Group
(4) Endpoint 03
b0
b7
EP03 set register (EP03CFG) [address 001916
]
At reset
Bit symbol
Bit name
R W
O O
Function
H/W S/W
BSIZ03
[1:0]
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1
0
–
bit
area, using a relative value for the beginning address of
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
DBLB03
SQCL03
Buffer mode select bit
0 : Single buffer mode
1 : Double buffer mode
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
0
0
–
–
O O
O O
Sequence toggle bit clear bit
“0” is always read when reading.
ITMD03
DIR03
Interrupt toggle mode select bit 0 : Normal mode
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0
0
0
–
–
–
O O
O O
O O
Transfer direction bit
0 : OUT (Data is received from the host.)
1 : IN (Data is transmitted to the host.)
b7b6
TYP03
[1:0]
Transfer type bit
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
–: State remaining
Fig. 64 Structure of EP03 set register
b0
b7
0
EP03 control register 1 (EP03CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID03
[1:0]
Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 65 Structure of EP03 control register 1
Rev.3.00 Oct 05, 2006 page 47 of 129
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38K0 Group
b0
b7
0
0
0
0
0
0
0
EP03 control register 2 (EP03CON2) [address 001B16
]
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
B0VAL03
0
–
Buffer 0 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
b7:b1
–
–
O O
Not used
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 66 Structure of EP03 control register 2
b0
b7
0
EP03 control register 3 (EP03CON3) [address 001C16
]
0
0
0
0 0 0
At reset
R W
Bit symbol
B1VAL03
Function
Bit name
Buffer 1 enable bit
H/W S/W
0
–
O O
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
Write “0” when writing.
b7:b1
–
–
O O
Not used
“0” is read when reading.
–: State remaining
Fig. 67 Structure of EP03 control register 3
b0
b7
0
EP03 interrupt source register (EP03REQ) [address 001D16
]
0
0
0
0
At reset
R W
Bit symbol
B0RDY03
Function
Bit name
H/W S/W
0
0
USB function/Endpoint 3 buffer 0
ready interrupt bit
O O
0 : No interrupt request issued
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
B1RDY03
0
0
USB function/Endpoint 3 buffer 1
ready interrupt bit
O O
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 3
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
ERR03
b7:b3
0
0
USB function/Endpoint 3 error
interrupt bit
O O
O O
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
–
–
Not used
“0” is read when reading.
Fig. 68 Structure of EP03 interrupt source register
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38K0 Group
b0
b7
0
EP03 byte number register 0 (EP03BYT0) [address 001E16
]
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
0
–
IN : Transmit byte number bit
B0BYT03
[6:0]
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
0
–
OUT : Receive byte number bit
O ✻
Single buffer mode: The received byte number is
automatically set.
Double buffer mode :The received byte number of buffer 0
is automatically set.
–
–
Not used
O O
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 69 Structure of EP03 byte number register 0
b0
b7
0
EP03 byte number register 1 (EP03BYT1) [address 001F16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
0
–
–
–
–
IN : Transmit byte number bit
O O
O ✻
O O
B1BYT03
[6:0]
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
OUT : Receive byte number bit
Not used
Single buffer mode: These bits are invalid.
Double buffer mode :The received byte number of buffer 1
is automatically set.
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 70 Structure of EP03 byte number register 1
b0
b7
0
EP03 MAX. packet size register (EP03MAX) [address 0FEC16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
–
MXPS03
[6:0]
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
Max. packet size bit
O O
O O
–
–
b7
Not used
“0” is read when reading.
–: State remaining
Fig. 71 Structure of EP03 MAX. packet size register
Rev.3.00 Oct 05, 2006 page 49 of 129
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38K0 Group
b0
b7
EP03 buffer area set register (EP03BUF) [address 0FED16
]
0
0
0
At reset
Bit symbol
Bit name
R W
O O
Function
H/W S/W
BADD03
[4:0]
EP03 beginning address set bit
Set the beginning address of EP03’s buffer area.
(32-byte unit)
0
–
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 72 Structure of EP03 buffer area set register
Rev.3.00 Oct 05, 2006 page 50 of 129
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38K0 Group
EXTERNAL BUS INTERFACE (EXB)
The external bus interface (EXB) controls the data transfer be-
memory (multichannel RAM). The external bus interface is shown
below.
tween the external MCU and the 38K0 group’s CPU or its
38K0 group
CPU
Program ROM
Peripheral functions
CPU channel
[Interrupt type]
USB bus
External bus interface
(EXB)
Multichannel RAM
USB
(USB host)
Memory channel
[Direct RAM access type]
Fig. 73 External bus interface
✻CPU channel
✻Data transfer of memory channel
It is a data transfer course by the interrupt processing between the
external MCU and the 38K0 group’s CPU.
When the burst mode is selected with the burst bit of the memory
channel operation mode register, data transfer can be carried out
at the highest speed. After the external bus interface detects a rise
of external read signal/write signal and synchronizes it with the in-
ternal clock φ, it completes the data transfer between the transmit/
receive buffer and the multichannel RAM in two clocks.
However, the waiting time of two clocks at a maximum is gener-
ated to access the multichannel RAM in USB being operating
because the USB has priority to access.
✻Memory channel
It is a data transfer course by direct RAM access of the memory
channel controller between the external MCU and the 38K0
group’s memory (multichannel RAM)
Therefore, it is necessary to set up the access interval which fills
the following timing with the external MCU bus side.
In φ = 8 MHz, data transfer at about 2 Mbytes/second is possible
at a maximum. When there is access simultaneously from the
USB, it is about 1.3 Mbytes/second.
In φ = 6 MHz, data transfer at about 1.5 Mbytes/second is possible
at a maximum. When there is access simultaneously from the
USB, it is about 1 Mbytes/second.
Address
CS, RD, WR,
DMA acknowledge
Access cycle time from externals:
•3 clocks or more of φ + Signal delay time + Data setup
time of external MCU in USB inactive
•5 clocks or more of φ + Signal delay time + Data setup
time of external MCU in USB active
Fig. 74 Data transfer timing of memory channel
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38K0 Group
EXB Pin Assignment
The external bus interface (EXB) pins are shown bellow.
The 38K0 group can transmit/receive a data to/from an external
MCU, using the following signals:
•Control input signal ................ 4 (ExCS, ExA0, ExRD, ExWR)
•Data input/output pin .............. 8 (DQ0 to DQ7)
•Interrupt output signal ............ 1 (ExINT)
Additionally, the DMA interface signal and the buffer status read
select signal of 38K0 group can be set up per one by the program.
•Control input signal ................ 3 (ExTC, ExDACK, ExRD, ExA1)
•Interrupt output signal ............ 1 (ExDREQ)
38K0 group
External bus interface
(EXB)
External pins
External chip select
External address
External read
P34
P37
P36
P35
P10
P33
/ExCS [ L ]
CPU
/ExA0 [address]
/ExRD [ L ]
External write
/ExWR [ L ]
8
External data
/DQ
0/AN0—P17/DQ7/AN7 [data]
External interrupt
/ExINT [ L ]
DMA request
Terminal count
P40
P42
P41
/ExDREQ/RxD [ L ]
/ExTC/SCLK [ L ]
DMA acknowledge
/ExDACK/TxD [ L ]
Multichannel RAM
Status read select
P43/ExA
1/SRDY [ H ]
: Functions as normal ports
just after reset.
Fig. 75 External bus interface (EXB) pin assignment
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38K0 Group
EXB Block Diagram
The block diagram of external bus interface (EXB) is shown below.
The external bus interface (EXB) consists of:
(1) External I/O interface part
(2) CPU interface part
(3) Internal memory interface part
(4) Transmit/Receive data buffer part
External I/O interface
Configuration
CPU interface
signal
Index register
EXB interrupt
External I/O
configuration
register
Cch_WR
source enable register
External MCU bus
Cch_RD
P34/ExCS
CPU channel
controller
Decoder data selector
TxB_RDY
RxB_RDY
P3
7
/ExA0
/ExRD
Memory channel
control
Memory channel
status
P36
P35/ExWR
Mch_RD
Mch_WR
Internal memory
Mch_TC
interface
P4
1
/ExDACK/TxD
mRX_enb
mTX_enb
Memory channel
operation mode register
P4
2
/ExTC/SCLK
/ExA1/SRDY
P4
3
Memory address
Memory address
counter
P33/ExINT
End address register
Mch_req
FIFO_stt
Request acknowledge
P40/ExDREQ/RxD
Memory channel
controller
MRDsel
Memory channel
transmit buffer control
stt_sel
Buf_WR
Transmit/Receive data
buffer
ExOE
Memory read data
Memory write data
P10/DQ
0/AN0–
Transmit buffer register
P17/DQ
7/AN
7
Receive buffer register
: Functions as normal ports just after reset.
Fig. 76 Block diagram of external bus interface (EXB)
Rev.3.00 Oct 05, 2006 page 53 of 129
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38K0 Group
(1) External I/O Interface Part
(2) CPU Interface Part
The external I/O interface part consists of a command decoder
and an output selector. A command decoder generates the follow-
ing signals to each unit.
The CPU interface part consists of the decoder/data selector of
the CPU channel, the CPU write register and CPU channel con-
troller
✻CPU interface part
✻Decoder/data selector of CPU channel
•CPU channel read (Cch_RD)
•CPU channel write (Cch_WR)
A write operation to the CPU register is performed by generating a
write signal for each register with an address decode signal and a
write signal.
✻Internal memory interface part
•Memory channel read (Mch_RD)
•Memory channel write (Mch_WR)
•Memory channel terminal count (Mch_TC)
A read operation from the CPU register is performed by generat-
ing an output enable signal of the internal data bus with an module
select signal and a read signal and generating a select signal for
each register with an address decode signal.
✻Transmit/receive data buffer part
•Buffer write (Buf_WR)
✻CPU write register
There are three CPU write registers as follows:
•EXB interrupt source enable register
•Index register
✻External I/O interface part
•Status selection (stt_sel)
•Output enable (ExOE)
•External I/O configuration register
The EXB interrupt source register is a read-only register.
A status signal of the CPU channel controller and a status signal
of the memory channel controller in the internal memory interface
part are generated.
Access to the CPU channel can be controlled only by setup of
external signals.
Access to the memory channel can be controlled by the value of
the external I/O configuration register and the state (mRX_enb,
mTX_enb signals) of the internal memory interface part.
✻CPU channel controller
The CPU channel controller generates the following signals, using
bits 0 and 1 (RXB_ENB, TXB_ENB) of EXB interrupt source en-
able register.
The output selector has the function which selects from the state
of CPU channel (TxB_RDY and RxD_RDY) and the state of
memory channel (Mch_req) as the signal assigned to P33/
ExINT pin and P40/ExDREQ/RxD pin.
•Memory channel transmitting buffer control signal (MRD_sel),
generated in the internal memory interface part
•CPU channel command signal (Cch_RD, Cch_WR), generated
in the external I/O interface part
•Signals RxB_RDY/RxB_full and TxB_RDY/TxB_empty, gener-
ated with read/write signals from the CPU channel
Rev.3.00 Oct 05, 2006 page 54 of 129
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38K0 Group
(3) Internal Memory Interface Part
The internal memory interface part consists of the CPU register
and the memory channel controller.
(5) External Pin
The external bus interface has the following pins to connect with
an external MCU bus.
•Chip select ........................... P34/ExCS
•Address ................................ P37/ExA0
•Data...................................... P10/DQ0/AN0 to P17/DQ7/AN7
•Read .................................... P36/ExRD
•Write ..................................... P35/ExWR
•Interrupt request .................. P33/ExINT
✻CPU register
The CPU register consists of the follows:
•Memory channel operation mode register
•Memory address counter
•End address register
The CPU can set the beginning address into the memory address
counter when the memory channel operation enable bit
(MC_ENB) of EXB interrupt source enable register is “0”. When
this bit is “1”, the write operation from the CPU is invalid and each
access from the external bus causes count-up operation.
It also has the following pins to connect with an external DMAC.
Each pin can be programmed for an ordinary port function or a
DMA interface pin function.
•DMA request ........................ P40/ExDREQ/RxD
•DMA acknowledgment ......... P41/ExDACK/TxD
•Terminal count ..................... P42/ExTC/SCLK
✻Memory channel controller
The CPU register consists of the follows:
•Main sequencer
It also has the status read select pin (P43/ExA1/SRDY pin) to con-
firm a ready status of the data buffer from an external MCU bus
This pin functions as a port just after reset. The status read select
function can be set by a program.
•Internal memory request signal generating circuit
•External memory channel request signal generating circuit
•Address end detection circuit
•Terminal end input processing circuit
•Status read select ................ P43/ExA1/SRDY
(4) Transmit/Receive Data Buffer Part
The transmit/receive data buffer part consists of the 8-bit transmit
buffer register (TXBUF) and the 8-bit receive buffer register
(RXBUF).
✻CPU channel: Communication with 38K0 group CPU
When a read/write operation is performed from an external MCU
bus in address signal ExA0 = “H”, the interrupt is generated and
the 38K0 group CPU can confirm its access. The 38K0 group CPU
judges the interrupt source and it starts a data transmission/recep-
tion with an external MCU bus.
Both CPU channel and memory channel use the same transmit
buffer register/receive buffer register to transfer a data to an exter-
nal MCU bus.
✻Memory channel: Communication with 38K0 group memory
multichannel RAM
When a read/write operation is performed from an external MCU
bus in address signal ExA0 = “L”, access to the multichannel RAM
is performed. Then an address of the multichannel RAM is made
by the external bus interface and it is increased at each access
completion. Consequently, FIFO access is performed.
Even if a read/write operation is performed in DACK = “L” instead
of ExCS = “L” and ExA0 = “L”, FIFO access to the multichannel
RAM is performed.
The beginning address and the end address must be set by the
CPU in advance.
Rev.3.00 Oct 05, 2006 page 55 of 129
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38K0 Group
✻P33/ExINT pin
✻P42/ExTC/SCLK pin
Any one of the following signals for this pin can be selected:
•TxB_RDY (transmit buffer ready) output
•RxB_RDY (receive buffer ready) output
•Mch_req (memory channel request) output
This pin is a port at the initial state. The terminal count signal can
be set by program.
If the terminal count signal is set at one bus cycle while a memory
channel operation write is being performed, the 38K0 group con-
firms that its bus cycle is the write cycle of the last data and sets
the memory channel status bits to “112”, and the interrupt is gener-
ated and the memory channel operation ends even if the memory
address counter has not reached the end address.
The CPU can obtain the last address where the data is written by
reading out the value of memory address counter. (See Figure
96.)
Either TxB_RDY or RxB_RDY is normally selected. The memory
channel request is for an access request signal to the memory
channel.
In a small system, a data transfer processing to the internal
memory is performed in the interrupt routine. According to that
situation, the 38K0 group has the function automatically to switch
an interrupt factor attached on the interrupt pin by program.
✻P40/ExDREQ/RxD pin
This pin is a port at the initial state. Which signal can be set by
program.
•RxB_RDY (receive buffer ready) output
•Mch_req (memory channel request) output
Mch_req of DMAC is normally selected. The output method of the
memory channel request signal depends on the burst bit (BURST)
of memory channel operation mode register. When the burst bit is
“0”, this signal is periodically output at each 1-byte transfer. (See
Figures 94 and 97.)
When the burst bit is “1”, this signal is continuously output while
the memory address counter is counting from the beginning ad-
dress to the end address (See Figures 95 and 98.)
✻P41/ExDACK/TxD pin
This pin is a port at the initial state. The DMA acknowledge signal
can be set by program.
The DMA acknowledge signal DACK = “L” is the same state as
that of CS = “L” and A0 = “L”. Access to multichannel RAM is
started by a rise of read signal or write signal which is set during
this term.
Note: If the DMA acknowledge signal and the chip select signal
are simultaneously active (DACK = “L” and CS = “L”), also
set the address signal A0 to “L”. If A0 is “H”, the memory
channel and the CPU channel are activated simultaneously
and it might cause some error.
Rev.3.00 Oct 05, 2006 page 56 of 129
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38K0 Group
EXB Register List
The EXB register list is shown below.
EXB SFR
Address
SYMBOL
Register Name
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
003016
003116
EXB interrupt source enable register
EXB interrupt source register
TXB_ENB
RXB_EMB
RXB_FULL
EXBICON
MC_ENB
MC_STS[1:0]
TXB_EMPTY
EXBIREQ
003316
003416
003516
EXB index register
0
0
0
0
0
INDEX[2:0]
EXBINDEX
EXBREG1
EXBREG2
LOW_WIN[7:0]
HIGH_WIN[7:0]
Register window 1 (low)
Register window 2 (high)
:
Not used
0 : “0” fixed
Fig. 77 EXB related registers (1)
•EXB interrupt source enable register
•EXB index register/Register windows 1, 2
This register enables/disables access from an external bus and an
internal interrupt.
The accessible register is switched by treating addresses 003416
and 003516 as a register window depending on the value of EXB
index register at address 003316.
•EXB interrupt source register
This register indicates the state of CPU channel’s transmit/receive
buffer register and the memory channel. The same value can be
read out from the external MCU bus by using the buffer status
read select signal (A1 pin = “H”).
EXB SFR
low
high
Index
0016
Register Name
SYMBOL
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
External I/O configu-
ration register
low
EXBCFGL
EXBCFGH
A1_CTR
INT_CTR[2:0]
EXB_CTR
high
TC_CTR
DAK_CTR[1:0]
DRQ_CTR[1:0]
At CPU read : RXBUF[7:0]
At CPU write : TXBUF[7:0]
0116
0216
0316
0416
low Transmit/Receive
buffer register
RXBUF/TXBUF
—
high
low
BURST
MC_DIR[1:0]
Memory channel ope-
ration mode register
MCHMOD
—
high
low Memory address
counter
MEMADL
MEMADH
ENDADL
ENDADH
IM_A[7:0]
0
0
0
0
0
0
0
0
0
0
high
IM_A[10:8]
low
END_A[7:0]
End address
register
high
END_A[10:8]
: Not used
0 : “0” fixed
Fig. 78 EXB related registers (2)
•External I/O configuration register
•Memory address counter
This register selects the function of each pin.
This is a counter to set the beginning address which FIFO ac-
cesses. This register is increased by access from the external
MCU bus.
•Transmit/Receive buffer register
This register consists of the receive buffer register (RXBUF) and
the transmit buffer register (TXBUF)
•End address register
This register is to set the end address which FIFO accesses.
•Memory channel operation mode register
This register sets the operation mode of the memory channel.
Rev.3.00 Oct 05, 2006 page 57 of 129
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38K0 Group
EXB Related Registers
The EXB related registers are shown below.
b0
b7
0
EXB interrupt source enable register (EXBICON) [address 003016
]
0
0
0
0
(Note)
At reset
H/W S/W
R W
O O
Bit symbol
Function
Bit name
RXB_ENB CPU channel receive enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Receive buffer full interrupt enabled)
0
0
0
–
–
–
TXB_ENB
CPU channel transmit enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Transmit buffer empty interrupt enabled)
O O
O O
MC_ENB
Memory channel operation
enable bit
0 : Operation disabled (Memory channel operation end
interrupt disabled)
1 : Operation enabled (Memory channel operation end
interrupt disabled)
b7:b3
Not used
Write “0” when writing.
–
–
O O
“0” is read when reading.
–: State remaining
Note: Do not set each bit simultaneously.
Fig. 79 Structure of EXB interrupt source enable register
b0
b7
0
0
0
0
EXB interrupt source register (EXBIREQ) [address 003116] (Note 1)
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0 : Receive buffer empty
1 : Receive buffer full
0 : Transmit buffer full
1 : Transmit buffer empty
b3b2
RXB_FULL Receive buffer full bit
0
0
0
0
(Note 3)
0
O –
O –
O –
TXB_EMPTY Transmit buffer empty bit
(Note 4)
MC_STS
[1:0]
Memory channel status bits
0
0 0 : Memory channel operation stopped
0 1 : Memory channel being operating;
No external access
(Note 2)
1 0 : Memory channel being operating;
External accessing
1 1 : Memory channel operation end; Memory
channel operation end interrupt generated
Write “0” when writing.
b7:b4
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Notes 1: When the the ExA1 pin control bit of external I/O configuration register is “1”, the external MCU bus can read this
register contents by setting the ExA1 pin to “H”.
2: The memory channel status bits indicate the status of memory channel. In MC_ENB = “0” these bits are always
“00
2”. When the memory channel operation ends, these bits are set to “112” and the memory channel operation
end interrupt is generated.
These bits can be read out during operation, so that it will show that whether the external MCU bus is accessing
or not.
3: This bit is cleared to “0” when reading the transmit/receive buffer register in the CPU channel receive enable bit =
“1” or when the CPU channel receive enable bit is “0”.
4: This bit is cleared to “0” when writing to the transmit/receive buffer register in the CPU channel transmit enable bit
= “1” or when the CPU channel transmit enable bit is “0”.
Fig. 80 Structure of EXB interrupt source register
Rev.3.00 Oct 05, 2006 page 58 of 129
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38K0 Group
b0
b7
EXB index register (EXBINDEX) [address 003316
]
0
0
0
0 0
At reset
H/W S/W
R W
O O
Bit symbol
Bit name
Function
INDEX
[2:0]
The accessible register, using the register window,
depends on these index bits contents as follows:
b2b1b0
0
–
Index bits
0 0 0 : External I/O configuration register
0 0 1 : Transmit/Receive buffer register
0 1 0 : Memory channel operation mode register
0 1 1 : Memory address counter
1 0 0 : End address register
1 0 1 : Do not set.
1 1 0 : Do not set.
1 1 1 : Do not set.
b7:b3
Write “0” when writing.
–
–
Not used
O O
“0” is read when reading.
–: State remaining
Fig. 81 Structure of EXB index register
b0
b7
Register window 1 (EXBREG1) [address 003416
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
LOW_WIN
[7:0]
The accessible register, using this register window, In-
In-
–
O O
depends on the EXB index register contents as definite definite
follows:
Index value
“0016
“0116
“0216
“0316
“0416
”
”
”
”
”
: External I/O configuration register
: Transmit/Receive buffer register
: Memory channel operation mode register
: Memory address counter
: End address register
Fig. 82 Structure of Register window 1
b0
b7
Register window 2 (EXBREG2) [address 003516
]
At reset
H/W S/W
R W
O O
Bit symbol
Bit name
Function
HIGH_WIN
[7:0]
The accessible register, using this register window, In-
In-
–
depends on the EXB index register contents as definite definite
follows:
Index value
“0016”
“0116”
“0216”
“0316”
“0416”
: External I/O configuration register
: Transmit/Receive buffer register
: Memory channel operation mode register
: Memory address counter
: End address register
Fig. 83 Structure of Register window 2
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38K0 Group
b0
b7
Index = 0016 : External I/O configuration register (EXBCFGL) [address 003416
]
0
0
0
At reset
H/W S/W
R W
O O
Bit symbol
EXB_CTR
Function
Bit name
0 : Port
EXB pin control bit
0
0
–
–
1 : EXB function pin
Selects a signal of P3
(Pins P1
0 to P17, P30 to P34)
3
/ExINT pin.
INT_CTR
[2:0]
P3 /ExINT pin control bit
3
O O
ON/OFF is programmed by each bit. An output logical
sum of P3 /ExINT pins set for ON are performed and it
3
is output as an “L” active signal.
b3b2b1
0 0 1 : RxB_RDY (RxBuf ready) output
0 1 0 : TxB_RDY (TxBuf ready) output
1 0 0 : Mch_req (Memory channel request) output
Others : Do not set.
0 : Port
A1_CTR
b7:b5
P4
3/ExA1 pin control bit
0
–
–
O O
O O
1 : A1 input (used to read status)
Write “0” when writing.
Not used
–
“0” is read when reading.
–: State remaining
Fig. 84 Index00[low]; Structure of External I/O configuration register
b0
b7
0
Index = 0016 : External I/O configuration register (EXBCFGH) [address 003516
]
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
b1b0
DRQ_CTR P4
0/ExDREQ/RxD pin control
0
–
O O
bit
0 0 : Port
0 1 : Do not set.
[1:0]
1 0 : ExDREQ function; RxB_RDY (RxBuf ready) output
1 1 : ExDREQ function; Mch_req (Memory channel
request) output
Specifies P41/ExDACK/TxD pin function.
DAK_CTR
[1:0]
P4
1/ExDACK/TxD pin control
0
–
O O
Selects which mode; requiring read or write signal, or
not requiring it for use of DMA acknowledge function.
bit
b3b2
0 0 : Port
0 1 : Do not set.
1 0 : ExDACK function; DMA acknowledge input
(Mode for read and write signals used together)
1 1 :ExDACK function; DMA acknowledge input
(Mode for read and write signals not required)
0 : Port
TC_CTR
b7:b5
P4
2
/ExTC/SCLK pin control bit
0
–
–
O O
O O
1 : ExTC (terminal count) input
Write “0” when writing.
Not used
–
“0” is read when reading.
–: State remaining
Fig. 85 Index00[high]; Structure of External I/O configuration register
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b0
b7
Index =0116 : Transmit/Receive buffer register (RXBUF/TXBUF) [address 003416
]
At reset
H/W S/W
R W
O O
Bit symbol
Function
Bit name
RXBUF/
TXBUF
–
0
–
The data received from an external bus is written here
at the rise timing of external write signal.
The data transmitted to an external bus is written here
at the timing of internal CPU write or memory write.
The receive buffer register (RXBUF) contents can be read out by reading to this address with the CPU. The data which the
CPU has written to this address is stored in the transmit buffer register (TXBUF).
However, do not perform write operation with the CPU to this address if the memory channel direction control bits of
memory channel operation mode register is “10
2” (transmit mode) and the memory channel status bits of EXB interrupt
source register are “01 ” or “10 ” (memory channel being operating).
2
2
Fig. 86 Index01[low]; Structure of Transmit/Receive buffer register
b0
b7
0
Index =0216 : Memory channel operation mode register (MCHMOD) [address 003416
]
0
0
0
0
At reset
H/W S/W
R W
O O
Bit symbol
Function
Bit name
MC_DIR
[1:0]
Memory channel direction
control bit
b1b0
0
–
0 0 : Operation disabled
0 1 : Receive mode
1 0 : Transmit mode
1 1 : Do not set.
BURST
b7:b3
Burst bit
Not used
0 : Cycle mode (each byte transfer according to
assertion or negation)
0
–
–
O O
O O
1 : Burst mode (continuous transfer till the terminal
count)
Write “0” when writing.
–
“0” is read when reading.
–: State remaining
Fig. 87 Index02[low]; Structure of Memory channel operation mode register
b0
b7
Index = 0316 : Memory address counter (MEMADL) [address 003416]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
IM_A
[7:0]
Register to set the low-order address of memory
channel operation beginning.
0
–
–
This contents are increased each time one memory
access ends.
Fig. 88 Index03[low]; Structure of Memory address counter
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b0
b7
Index = 0316 : Memory address counter (MEMADH) [address 003516
]
0
0
0
0
0
At reset
H/W S/W
Bit symbol
Function
R W
O O
Bit name
IM_A
[10:8]
Register to set the high-order address of memory
channel operation start.
0
–
–
This contents are increased each time one memory
access ends.
O O
b7:b3
Write “0” when writing.
–
–
Not used
“0” is read when reading.
–: State remaining
Fig. 89 Index03[high]; Structure of Memory address counter
b0
b7
Index = 0416 : End address register (ENDADL) [address 003416
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
END_A
[7:0]
Register to set the low-order address of memory
channel operation end.
0
–
–
–: State remaining
Fig. 90 Index04[low]; Structure of End address register
b0
b7
0
Index = 0416 : End address register (ENDADH) [address 003516
]
0
0
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
O O
END_A
[10:8]
Register to set the high-order address of memory
channel operation end.
0
–
–
b7:b3
Write “0” when writing.
–
–
Not used
“0” is read when reading.
–: State remaining
Fig. 91 Index04[high]; Structure of End address register
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38K0 Group
EXB Operation Timing Diagram
(1) CPU Channel Receiving Operation
CPU channel receiving operation is shown bellow.
✻
✻
✻
✻
Address ExA0
Chip select ExCS
Read ExRD
A0 = “1”
CS = “0”
A0 = “1”
CS = “0”
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
Interrupt request ExINT
[RxB_RDY]
RxB_RDY
RxB_RDY
Receive buffer full bit RXB_FULL
Receive buffer RXBUF
#0
#1
Transmit buffer TXBUF
✻
CPU channel receive enable bit
RXB_ENB
Receive buffer read
✻
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P3
3
/ExINT pin control) = 001
2
(RxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
RXB_ENB (CPU channel receive enable) = “1” (Receive buffer full interrupt enabled)
✻
Writing the command for enabling operation makes RXB_RDY assertion and the P33/ExINT pin goes to “L”.
If the CPU channel receive enable bit (RXB_ENB) is “0”, both the receive buffer full bit (RXB_FULL) and the receive buffer ready signal (RxB_RDY) to an
external are inactive.
✻
When a write operation is performed from an external MCU bus in the condition of ExCS = “L” and WxA0 = “H”, it will result in as follows:
• The data is written into the receive buffer (RXBUF)
• Negation of the receive buffer ready signal (RxB_RDY) to an external is made
• The RXB_FULL interrupt is generated.
✻ When the CPU reads out the receive buffer (RXBUF) with an interrupt processing program, the receive buffer full bit (RXB_FULL) is cleared to “0”.
Fig. 92 CPU channel receiving operation
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(2) CPU Channel Transmitting Operation
CPU channel transmitting operation is shown bellow.
✻
✻
✻
✻’
Address ExA0
Chip select ExCS
Read ExRD
A0 = “1”
A0 = “1”
CS = “0”
CS = “0”
✻
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
Interrupt request ExINT
[TxB_RDY]
TxB_RDY
TxB_RDY
Transmit buffer empty bit
TXB_EMPTY
Receive buffer RXBUF
Transmit buffer TXBUF
#0
#1
✻
CPU channel transmit enable bit
TXB_ENB
Transmit data write
✻’
✻
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P33/ExINT pin control) = 0102 (TxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
TXB_ENB (CPU channel transmit enable) = “1” (Transmit buffer empty interrupt enabled)
✻
Writing the command for enabling operation generates TXB_EMPTY interrupt.
If the CPU channel transmit enable bit (TXB_ENB) is “0”, both the transmit buffer empty bit (TXB_EMPTY) and the transmit buffer ready signal (TxB_RDY) to
an external are inactive.
✻
When the CPU writes the data into the transmit buffer (TXBUF) with an interrupt processing program, the transmit buffer empty bit (TXB_EMPTY) is cleared
to “0” and assertion of the transmit buffer ready signal (TxB_RDY) to an external is made.
✻
When a read operation is performed from an external MCU bus in the condition of ExCS = “L” and ExA0 = “H”, it will result in as follows:
• The contents of the transmit buffer (TXBUF) is read out
• The transmit buffer empty bit (TXB_EMPTY) is set to “1”
• Negation of the transmit buffer ready signal (TxB_RDY) to an external is made.
Fig. 93 CPU channel tranmitting operation
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(3) Memory Channel Receiving Operation (1)-
Cycle Mode
Memory channel receiving operation (1) is shown bellow.
✻
✻
✻
✻
✻’
✻’
✻
A0 = “0”
A0 = “0”
Address ExA0
CS = “0”
CS = “0”
Chip select ExCS
DMA acknowledge
ExDACK
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
DMA request
ExDREQ
Mch_req
Mch_req
mWR
mWR
detection
detection
Receive buffer RXBUF
#0
#1
✻
Operation enabled
Main sequencer
0
1
2
3
5
Memory channel operation
end interrupt
Internal memory access
req
req
Memory address
Counter end
010016
010116
010216
Acknowledgment of
internal memory access
ack
ack
✻
✻
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “0” (Cycle mode)
Memory address counter
End address register
(Example) 010016
(Example) 010116
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
✻
✻
✻
In the memory channel receive mode when the command for enabling operation is written, operation starts (main sequencer starts) and assertion of the
memory channel request which synchronized with a rise of φ is made.
When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExWR is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of φ is made.
When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
✻ The memory address counter is increased simultaneously at write completion and assertion of the next memory channel request is made.
✻
When the write operation to the end address has been completed, the memory address counter is increased, but assertion of the next memory channel
request is not made and the memory channel operation end interrupt is generated.
Fig. 94 Memory channel receiving operation (1)
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(4) Memory Channel Receiving Operation (2)-
Burst Mode
Memory channel receiving operation (2) is shown bellow.
✻
✻
✻
✻
✻’
✻’
✻
✻
Address ExA0
A0 = “x”
A0 = “x”
A0 = “x”
CS = “1”
Dack = “0”
Chip select ExCS
CS = “1”
CS = “1”
Dack = “0”
DMA acknowledge
ExDACK
Dack = “0”
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
#2
Internal clock φ
DMA request
ExDREQ
Mch_req
mWR
mWR
detection
detection
Receive buffer RXBUF
#0
#1
#2
Operation enabled
Main sequencer
✻
0
1
2
3
5
Memory channel operation
end interrupt
Internal memory access
req
req
req
Memory address
Counter end
Burst end
010016
010116
010216
010316
Acknowledgment of
internal memory access
ack
ack
ack
✻
✻
✻
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
End address register
(Example) 010016
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
✻
In the memory channel receive mode when the command for enabling operation is written, assertion of the memory channel request which synchronized
with a rise of φ is made.
✻
When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
✻ The memory address counter is increased simultaneously at the former data write completion.
✻
When the memory address counter reaches the end address, the detection circuit of external write signal (ExWR) operation is enabled and negation of the
memory channel request which synchronized with the following φ is made.
✻
When the write operation to the end address has been completed, the memory address counter is increased and the memory channel operation end
interrupt is generated.
Fig. 95 Memory channel receiving operation (2)
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(5) Memory Channel Receiving Operation (3)-
Burst Mode (Terminal Count)
Memory channel receiving operation (3) is shown bellow.
✻’
✻’
✻
✻
✻
A0 = “x”
A0 = “x”
CS = “1”
Address ExA0
Chip select ExCS
CS = “1”
DMA acknowledge
ExDACK
Dack = “0”
Dack = “0”
✻’
Terminal count ExTC
Write ExWR
TC
Data DQ0 to DQ7
#0
#1
Internal clock φ
DMA request
ExDREQ
Mch_req
mWR
mWR
detection
detection
Receive buffer RxBuf
mTC detection
#0
#1
TC synchronizing
TC end
✻
✻’
✻’
✻’
Operation enabled
Main sequencer
0
1
2
3
(5)
5
Memory channel operation
end interrupt
req
Internal memory access
✻
✻’
Memory address
Counter end
Burst end
010016
010116
010216
Acknowledgment of
internal memory access
ack
ack
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
End address register
(Example) 010016
(Example) 010716
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
✻ When a rise of TC is detected, negation of the memory channel request which synchronized with a rise of φ is made.
✻ When the write operation to the end address has been completed, the memory channel operation end interrupt is generated.
Fig. 96 Memory channel receiving operation (3)
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(6) Memory Channel Transmitting Operation
(1)-Cycle Mode
Memory channel transmitting operation (1) is shown bellow.
✻
✻
✻
✻
✻
✻
✻’
✻
✻
Address ExA0
A0 = “x”
CS = “1”
A0 = “x”
CS = “1”
Chip select ExCS
DMA acknowledge
ExDACK
Dack = “0”
Dack = “0”
✻
✻’
Read ExRD
Write ExWR
#0
#1
Data DQ0 to DQ7
Internal clock φ
DMA request
ExDREQ
Mch_req
Mch_req
mRD
mRD
detection
detection
Transmission completed
Transmit buffer TXBUF
#0
#1
4
✻
Operation enabled
Main sequencer
0
1
2
3
5
Memory channel operation
end interrupt
req
req
Internal memory access
Memory address
Counter end
010016
010116
010216
Acknowledgment of
internal memory access
ack
ack
✻
✻
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “0” (Cycle mode)
Memory address counter
End address register
(Example) 010016
(Example) 010116
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
✻
In the memory channel transmit mode when the command for enabling operation is written, operation starts (main sequencer starts) and an internal
memory access sequence which synchronized with a rise of φ is activated.
✻
✻
A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExRD is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of φ is made.
✻ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
✻
A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
When the read operation from the end address has been completed, the transition to the status to wait the memory channel operation end occurs.
✻ When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Fig. 97 Memory channel tranmitting operation (1)
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(7) Memory Channel Transmitting Operation
(2)-Burst Mode
Memory channel transmitting operation (2) is shown bellow.
✻
✻
✻
✻
✻
✻’
✻’
✻
✻
✻
Address ExA0
A0 = “x”
A0 = “x”
A0 = “x”
CS = “1”
Dack = “0”
CS = “1”
Dack = “0”
CS = “1”
Dack = “0”
Chip select ExCS
DMA acknowledge
ExDACK
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
#2
Internal clock φ
DMA request
ExDREQ
Mch_req
mRD
mRD
detection
detection
Transmission completed
Transmit buffer TXBUF
Operation enabled
Main sequencer
#0
#1
#2
4
✻
0
1
2
3
5
Memory channel operation
end interrupt
Internal memory access
req
req
req
Memory address
Counter end
010016
010116
010216
010316
Burst end
Acknowledgment of
internal memory access
ack
ack
ack
✻
✻
✻
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
End address register
(Example) 010016
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
✻
✻
In the memory channel transmit mode when the command for enabling operation is written, an internal memory access sequence which synchronized with
a rise of φ is activated.
A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
✻ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
✻
A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased.
✻
✻
When the read operation from the end address has been completed, the detection circuit of external read signal (ExRD) operation is enabled and negation
of the memory channel request which synchronized with the following φ is made.
When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Fig. 98 Memory channel tranmitting operation (2)
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38K0 Group
MULTICHANNEL RAM
The one wait function (ONW function) of 38000 series CPU is
used internally to control access with the CPU. When receiving an
access request from the USB or the EXB, the multichannel RAM
outputs ONW signal to wait the CPU for one clock, and access of
the USB or the EXB is performed.
The 38K0 group has the built-in multichannel RAM including the
small logic circuit (RAM I/F) instead of ordinary RAM.
The multichannel RAM has the USB channel and the EXB channel
in addition to the CPU channel.
The multichannel RAM controls access from CPU, USB and EXB,
synchronizing control with φ. The USB transfer rate is about 1.5
Mbytes/second. Access to the multichannel RAM is performed at
every about 5.3 clocks in φ = 8 MHz, or at every about 4 clocks in
φ = 6 MHz. The USB’s access has priority to the EXB’s.
If the multichannel RAM is outputting ONW signal while the CPU
is in the state of reading/writing for the RAM area, the CPU read
cycle or write cycle is extended by 1 period of φ.
No wait
No wait
No wait
ONW = “H”
Except RAM
No RD/WR
φ
RAM area
Except RAM
RAM area
CPU AD
RD/WR
CPU bus cycle
USB REQ
EXB REQ
ONW
Multichannel RAM
CPU
USB
CPU
RAM access right
RAM RD/WR
RAM bus cycle
Fig. 99 Multichannel RAM timing diagram (no wait)
One wait
One wait
One wait
One wait
Prohibiting continuous access of
USB/EXB
USB having priority of USB/EXB
simultaneous access
CPU accessing RAM at the latter part
2-cycle wait (max.) for EXB
Prior CPU
Prior CPU
Prior USB
Prior CPU
φ
RAM area
RAM area
RAM area
RAM area
CPU AD
RD/WR
CPU bus cycle
USB REQ
EXB REQ
ONW
Multichannel RAM
EXB
CPU
USB
CPU
USB
CPU
EXB
CPU
RAM access right
RAM RD/WR
RAM bus cycle
Fig. 100 Multichannel RAM timing diagram (one wait)
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38K0 Group
Multichannel RAM Operation Example
The multichannel RAM operation example is shown below.
This example shows the case that an external MCU uses the
38K0 group as a peripheral LSI (USB controller).
The following explains that the external MCU reads out the data
which is received via the USB.
✻ The data which is received via the USB is written into the multi-
channel RAM.
✻ Receive completion is propagated to the CPU.
✻ The external bus interface is activated owing to the CPU.
✻ (1) The external bus interface sets the data which is read from
the multichannel RAM into the internal data buffer.
(2) The external MCU reads out the data bus buffer of the exter-
nal bus interface.
(3) The above operation is repeated by the number of the re-
ceived bytes. After that, the data transfer is completed.
Program ROM
Peripheral functions
CPU
✻
Notice of receive completion
Multichannel RAM
✻
Activating
External MCU bus
USB bus
External bus interface
USB
(USB host)
✻
FIFO read of received data
by External bus interface
✻
FIFO write of received data
by USB
Fig. 101 Multichannel RAM operation example
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38K0 Group
Comparator and Control Circuit
A/D CONVERTER
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, and then stores the result in the
AD conversion registers 1, 2. When an A/D conversion is com-
pleted, the control circuit sets the AD conversion completion bit
and the AD interrupt request bit to “1”.
The functional blocks of the A/D converter are described below.
[AD Conversion Register 1, 2 (AD1, AD2)]
003716, 003816
The AD conversion register is a read-only register that stores the
result of an A/D conversion. When reading this register during an
A/D conversion, the previous conversion result is read.
Bit 7 of the AD conversion register 2 must be set to “0”. Not only
10-bit reading but also only high-order 8-bit reading of conversion
result can be performed by selecting the reading procedure of the
AD conversion registers 1, 2 after A/D conversion is completed (in
Figure 103).
Note that because the comparator consists of a capacitor cou-
pling, set f(system clock) to 500 kHz or more during an A/D
conversion.
b7
b0
AD control register
The 8-bit reading inclined to MSB is performed when reading the
AD converter register 1 after A/D conversion is started or reset;
and when the AD converter register 1 is read after reading the AD
converter register 2, the 8-bit reading inclined to LSB is per-
formed.
(ADCON : address 003616
)
Analog input pin selection bits
0 0 0 : P1
0 0 1 : P1
0 1 0 : P1
0 1 1 : P1
1 0 0 : P1
1 0 1 : P1
1 1 0 : P1
1 1 1 : P1
0/DQ
1/DQ
2/DQ
3/DQ
4/DQ
5/DQ
6/DQ
7/DQ
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
[AD Control Register (ADCON)] 003616
The AD control register controls the A/D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 3 signals the comple-
tion of an A/D conversion. The value of this bit remains at “0”
during an A/D conversion, and changes to “1” when an A/D con-
version ends. Writing “0” to this bit starts the A/D conversion.
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (indefinite at read)
(These bits are write disabled bits.)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
VREF and AVSS into 1024, and that outputs the comparison volt-
age.
Fig. 102 Structure of AD control register
The A/D converter successively compares the comparison voltage
Vref in each mode, dividing the VREF voltage (see below), with the
input voltage.
10-bit reading
(Read address 003816 before 003716)
b7
b0
b9 b8
b0
• 10-bit reading
(address 003816)
0
VREF
Vref =✻✻✻✻✻✻✻✻✻✻✻✻✻n (n = 0–1023)
1024
b7
b7 b6 b5 b4 b3 b2 b1 b0
(address 003716)
• 8-bit reading
Note : Bits 2 to 7 of address 003816 become “0”
VREF
Vref =✻✻✻✻✻✻✻✻✻✻✻✻✻n (n = 0–255)
at reading.
256
8-bit reading
(Read only address 003716)
b7
Channel Selector
The channel selector selects one of the input ports P17/AN7–P10/
b0
b9 b8 b7 b6 b5 b4 b3 b2
(address 003716)
AN0.
Fig. 103 10-bit A/D mode reading
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Data bus
b7
b0
AD control register
(address 003616
)
3
A/D interrupt request
A/D control circuit
P1
P1
P1
P1
P1
P1
P1
P1
0
1
2
3
4
5
6
7
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
0/AN
1/AN
2/AN
3/AN
4/AN
5/AN
6/AN
7/AN
0
1
2
3
4
5
6
7
(address 003816
)
AD conversion register 2
AD conversion register 1
Comparator
(address 003716
)
10
Resistor ladder
V
REF
V
SS
Fig. 104 A/D converter block diagram
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38K0 Group
WATCHDOG TIMER
✻Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) per-
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at sys-
tem clock 8 MHz frequency.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 003916) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watch-
dog timer H.
When this bit is set to “1”, the count source becomes the system
clock divided by 16. The detection time in this case is set to 512
µs at system clock 8 MHz frequency. This bit is cleared to “0” after
resetting.
✻Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003916) may be
started before an underflow. When the watchdog timer control reg-
ister (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit (bit 6), and
watchdog timer H count source selection bit (bit 7) are read.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
Once the STP instruction is executed, an internal reset occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L is set to “FF16.”
Data bus
“FF16” is set when
watchdog timer
control register is
written to.
“FF16” is set when
watchdog timer
control register is
written to.
“0”
Watchdog timer L (8)
System clock
Watchdog timer H (8)
1/16
“1”
Watchdog timer H count
source selection bit
STP instruction disable bit
STP instruction
Reset circuit
Internal reset
RESET
Fig. 105 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 003916
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: System clock/16
Fig. 106 Structure of Watchdog timer control register
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38K0 Group
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 16 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage should be between 3.0 V
and 5.25 V for L version, and the oscillation should be stable), re-
set is released. After the reset is completed, the program starts
from the address contained in address FFFD16 (high-order byte)
and address FFFC16 (low-order byte). Make sure that the reset in-
put voltage is under 0.6 V for VCC of 3.0 V (L version).
Poweron
(Note)
Power source
voltage
RESET
VCC
0 V
Reset input
0.2VCC
voltage
0 V
Note : Reset release voltage ;
Vcc = 3.0 V (L version)
RESET
VCC
Power source
voltage detection
circuit
Fig. 107 Example of reset circuit
XIN
φ
RESET
Internal
reset
Address
ADH,L
?
?
?
?
FFFC
FFFD
Reset address from the vector table.
ADH
Data
?
?
?
ADL
?
SYNC
XIN: 10.5 to 18.5 clock cycles
Notes1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 108 Reset sequence
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38K0 Group
PLL CIRCUIT (FREQUENCY SYNTHESIZER)
The PLL circuit generates fVCO (PLL output clock), which is re-
quired for fUSB (USB clock) and fSYN (fUSB division clock), from
f(XIN) (external input reference clock). Figure 109 shows the PLL
circuit block diagram.
It is possible to input 6 or 12 MHz clock from the externals as a
standard clock input. When using the USB function, set the PLL
operation mode selection bit so that fvco may be set to 48 MHz.
The PLL circuit operates by setting the PLL operation enable bit to
“1”. When supplying fVCO to the USB block, wait for the oscillation
stable time (1ms or less) of PLL before selecting fVCO with the
USB clock selection bit.
According to the setting of the USB clock division ratio selection
bit, the division clock of fUSB is supplied to fSYN. When using this
clock as system clock, set the USB clock division ratio selection
bit so that it may be set to 6 MHz, 8 MHz or 12 MHz. (However,
using it only when fUSB is 48MHz is recommended).
f
USB
SYN
f(XIN
)
f
VCO
PLL
Division circuit
f
PLLCON
USBCON
(address 0FF816
)
(address 001016)
Fig. 109 Block diagram of PLL circuit
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38K0 Group
b7
b0
PLL control register
(PLLCON: address 0FF816
)
Not used (return “0” when read)
USB clock division ratio selection bits
b4b3
0 0: Divided by 8 (fSYN = fUSB/8)
0 1: Divided by 6 (fSYN = fUSB/6)
1 0: Divided by 4 (fSYN = fUSB/4)
1 1: Not selected
PLL operation mode selection bits
b6b5
0 0: Not multiplied (fVCO = fXIN
)
0 1: Double (fVCO = fXIN ✻ 2)
1 0: Quadruple (fVCO = fXIN ✻ 4)
1 1: Multiplied by 8 (fVCO = fXIN ✻ 8)
PLL Enable Bit
0: Disabled
1: Enabled
Fig. 110 Structure of PLL control register
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38K0 Group
CLOCK GENERATING CIRCUIT
Oscillation Control
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT. Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No external
resistor is needed between XIN and XOUT since a feed-back resis-
tor exists on-chip. (An external feed-back resistor may be needed
depending on conditions.)
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and the XIN oscillator stops. When the oscillation stabi-
lizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1. XIN
divided by 16 is compulsorily connected to the input of the
prescaler 12. Oscillator restarts when an external interrupt (includ-
ing USB resume interrupt) is received, but the internal clock φ
remains at “H” until timer 1 underflows. The internal clock φ is not
supplied until timer 1 underflows. Because the sufficient time is re-
quired for the oscillation to stabilize when a ceramic resonator etc.
is used. When the oscillator is restarted by reset, apply “L” level to
the RESET pin until the oscillation is stable since a wait time will
not be generated automatically.
Frequency Control
Either fSYN or f(XIN) can be selected as an internal system clock.
Furthermore, the frequency of internal clock φ can be selected by
the system clock division ratio selection bit.
(1) fSYN clock
fSYN clock is generated by the PLL circuit. f(XIN) or fVCO can be
selected as an input clock. When using as an internal system
clock, there is restriction on use. Refer to the clause of “PLL CIR-
CUIT”.
(2) f(XIN) clock
The frequency applied to the XIN pin is used as an internal system
(2) Wait mode
clock frequency.
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before ex-
ecuting of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruc-
tion.
✻Note
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
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38K0 Group
b7
b0
MISRG
(MISRG: address 0FFB16
)
XIN
XOUT
Oscillation stabilizing time set after STP instruction
released bit
Rd (Note)
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
Not used (indefinite at read)
CIN
COUT
Notes : Insert a damping resistor if required.
The resistance will vary depending on the oscillator
and the oscillation drive capacity setting.
Use the value recommended by the maker of the
oscillator.
Fig. 113 Structure of MISRG
Also, if the oscillator manufacturer's data sheet
specifies that a feedback resistor be added
external to the chip though a feedback resistor
exists on-chip, insert a feedback resistor between
XIN and XOUT following the instruction.
Fig. 111 Ceramic resonator or quartz-crystal oscilltor circuit
X
IN
X
OUT
Open
External oscillation circuit
V
CC
SS
V
Fig. 112 External clock input circuit
XIN
XOUT
fvco
USB clock selection bit
PLL
fUSB
1/4
1/6
1/8
USB clock division
ration selection bits
fSYN
System clock selection bit
fsio
fAD
1/2
1/4
1/2
1/2
1/2
1/8
1/2
Prescaler 12
FF16
Timer 1
Reset or STP
instruction
0116
1/1
System clock division
ration selection bits
Timing φ (internal clock)
Reset
Q
S
Q
Q
S
R
S
R
WIT
instruction
STP instruction
STP instruction
R
Reset
Interrupt disable flag l
Interrupt request
Fig. 114 System clock generating circuit block diagram (single-chip mode)
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38K0 Group
Reset
CM6
“0”←→“1”
X
IN 8-divide mode
X
IN 4-divide mode
f(φ) = 1.5 MHz
CM7 = 0
f(φ) = 0.75 MHz
CM7 = 0
CM6 = 0
CM5 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = 00
PLLCON [4:3] = xx
(arbitrary)
CM6
“0”←→“1”
X
IN 2-divide mode
f(φ) = 3.0 MHz
CM7 = 1
X
IN through mode
f(φ) = 1.5 MHz
CM7 = 0
CM6 = 0
CM5 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
PLLCON [4:3] = xx
(arbitrary)
Note:
Set PLLCON [4:3] = 10 before
switching the system clock from XIN
to fSYN
.
CM6
“0”←→“1”
f(SYN) through mode
f(φ) = 12.0 MHz
CM7 = 1
f(SYN) 2-divide mode
f(φ) = 6.0 MHz
CM7 = 1
CM6 = 1
CM6 = 0
CM5 = 1
CM5 = 1
PLLCON [4:3] = 10
PLLCON [4:3] = 10
Under planning
CM5
“0”←→“1”
CM6
“0”←→“1”
f(SYN) through mode
f(φ) = 6.0 MHz
CM7 = 1
CM5
“0”←→“1”
CM6 = 1
CM5 = 1
PLLCON [4:3] = 00
Note:
Set PLLCON [4:3] = 00 before switching
Note:
Set PLLCON [4:3] = 00 before switching
the system clock from XIN to fSYN.
the system clock from XIN to fSYN
.
CM5
“0”←→“1”
CM6
“0”←→“1”
f(SYN) through mode
f(φ) = 8.0 MHz
CM7 = 1
CM5
“0”←→“1”
CM6 = 1
CM5 = 1
PLLCON [4:3] = 01
Note:
Note:
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN
.
.
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly
without an allow.)
2 : Set the USB clock (fUSB) to 48 MHz when switching the system clock to fSYN
.
3 : Do not change a division ratio of USB clock when using fSYN as the system clock.
4 : See section “PLL CIRCUIT” in details for enabling/disabling PLL operation and usage notes of fSYN
5 : Set the system clock to XIN when entering STOP mode.
.
6 : In all modes, switching to WAIT mode is possible. When it is released, the MCU returns to the original mode. In
WAIT mode the timers can operate.
Remarks : This diagram assumes that the 6 MHz signals are applied to XIN pin.
Fig. 115 State transitions of clock
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38K0 Group
FLASH MEMORY MODE
Summary
The 38K0 group’s flash memory version has an internal new
DINOR (DIvided bit line NOR) flash memory that can be rewritten
with a single power source when VCC is 4.5 to 5.25 V, and 2 power
sources when VCC is 3.0 to 4.5 V.
Table 8 lists the summary of the 38K0 group’s flash memory ver-
sion.
This flash memory version has some blocks on the flash memory
as shown in Figure 116 and each block can be erased. The flash
memory is divided into User ROM area and Boot ROM area.
In addition to the ordinary User ROM area to store the MCU op-
eration control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user’s application sys-
tem. This Boot ROM area can be rewritten in only parallel I/O
mode.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
Table 8 Summary of 38K0 group’s flash memory version
Item
Specifications
Power source voltage (Vcc)
3.00 – 5.25 V (L version) (Program and erase in 4.00 to 5.25 V of Vcc.)
3.00 – 4.00 V (L version) (Program and erase in 3.00 to 5.25 V of Vcc.)
Program/Erase VPP voltage (VPP)
Flash memory mode
4.50 – 5.25 V
3 modes; Flash memory can be manipulated as follows:
•CPU rewrite mode: Manipulated by the Central Processing Unit (CPU).
•Parallel I/O mode: Manipulated using an external programmer (Note 1)
•Standard serial I/O mode: Manipulated using an external programmer (Note 1)
Erase block division
User ROM area
Boot ROM area
1 block (32 Kbytes)
1 block (4 Kbytes) (Note 2)
Program method
Erase method
Byte program
Batch erasing
Program/Erase control method
Number of commands
Program/Erase control by software command
6 commands
Number of program/Erase times
Data retention period
100 times
10 years
ROM code protection
Available in parallel I/O mode and standard serial I/O mode
Notes 1: In the parallel I/O mode or the standard serial I/O mode, use the exclusive external equipment flash programmer which supports the 38K0 Group
(flash memory version).
2: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be re-
written in only parallel I/O mode.
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38K0 Group
(1) CPU Rewrite Mode
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode beforehand.
(If the control program is written into the Boot ROM area, the stan-
dard serial I/O mode becomes unusable.)
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central Process-
ing Unit (CPU).
In CPU rewrite mode, only the User ROM area shown in Figure
116 can be rewritten; the Boot ROM area cannot be rewritten.
Make sure the program and block erase commands are issued for
only the User ROM area and each block area.
See Figure 116 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer
is reset with pulling CNVSS pin low. In this case, the CPU starts
operating using the control program in the User ROM area.
When the microcomputer is reset by pulling the P16 (CE) pin high,
the CNVSS pin high, the CPU starts operating using the control
program in the Boot ROM area. This mode is called the “Boot”
mode.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite con-
trol program must be transferred to internal RAM area to be
executed before it can be executed.
Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command.
User ROM area
800016
Block 1 : 32 Kbytes
Boot ROM area
F00016
FFFF16
4 Kbytes
FFFF16
Notes 1: The Boot ROM area can be rewritten in only parallel I/O mode. (Access to any other
areas is inhibited.)
2: To specify a block, use the maximum address in the block.
Fig. 116 Block diagram of built-in flash memory
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38K0 Group
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten in CPU rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory as instructed by software commands. This
rewrite control program must be transferred to a memory such as
the internal RAM before it can be executed.
CPU becomes unable to access the internal flash memory directly.
Therefore, use the control program in a memory other than inter-
nal flash memory for write to bit 1. To set this bit to “1”, it is
necessary to write “0” and then write “1” in succession. The bit can
be set to “0” by only writing “0”.
Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in
CPU rewrite mode, so that reading this flag can check whether
CPU rewrite mode has been entered or not.
The MCU enters CPU rewrite mode by applying 4.50 V to 5.25 V
to the CNVSS pin and setting “1” to the CPU Rewrite Mode Select
Bit (bit 1 of address 0FFE16). Software commands are accepted
once the mode is entered.
Bit 3 is the flash memory reset bit used to reset the control circuit
of internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the
control circuit. To set this bit to “1”, it is necessary to write “0” and
then write “1” in succession. To release the reset, it is necessary
to set this bit to “0”.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 117 shows the flash memory control register.
Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In Boot mode, this bit is set to “1” auto-
matically. Reprogramming of this bit must be in a memory other
than internal flash memory.
Bit 0 is the RY/BY status flag used exclusively to read the operat-
ing status of the flash memory. During programming and erase
operations, it is “0” (busy). Otherwise, it is “1” (ready). This is
equivalent to the RY/BY pin function in parallel I/O mode.
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
“1”, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
Figure 118 shows a flowchart for setting/releasing CPU rewrite
mode.
b7
b0
Flash memory control register (address 0FFE16
)
FMCR (Note 1)
RY/BY status flag
0: Busy (being written or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode (Software commands invalid)
1: CPU rewrite mode
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User area / Boot area select bit (Note 4)
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (indefinite at read/ “0” at write)
Notes 1: The contents of flash memory control register are “XXX00001” just after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not
this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt
will be generated during that interval.
Use the control program in the area except the built-in flash memory for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after
setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory for write to this bit.
Fig. 117 Structure of flash memory control register
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Start
Single-chip mode or Boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control program to
memory other than internal flash memory
Jump to control program transferred in memory
other than internal flash memory
(Subsequent operations are executed by control
program in this memory)
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
Write “0” to CPU rewrite mode select bit
End
Notes 1: When starting the MCU in the single-chip mode or memory expansion mode, supply
4.5 V to 5.25 V to the CNVss pin until checking the CPU rewrite mode entry flag.
2: Set the system clock division ration selection bits of CPU mode register (bits 6 and
7 at address 003B16).
3: Before exiting the CPU rewrite mode after completing erase or program operation,
always be sure to execute the read array command or reset the flash memory.
Fig. 118 CPU rewrite mode set/release flowchart
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Notes on CPU Rewrite Mode
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
✻Operation speed
During CPU rewrite mode, set the internal clock φ to 1.5 MHz or
less using the system clock division ratio selection bits (bits 6 and
7 of address 003B16).
✻Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
✻Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
✻Watchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely cleared during program or erase.
✻Reset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNVss = “H”, so that the pro-
gram will begin at the address which is stored in addresses
FFFC16 and FFFD16 of the boot ROM area.
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____
Software Commands
During the program movement, The RY/BY Status Flag of flash
Table 9 lists the software commands.
memory control register is set to “0”. When the program com-
pletes, it becomes “1”.
After setting the CPU Rewrite Mode Select Bit to “1”, write a soft-
ware command to specify an erase or program operation.
Each software command is explained below.
At program end, program results can be checked by reading the
status register.
✻Read Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified ad-
dress are read out at the data bus (D0 to D7).
Start
Write 4016
The read array mode is retained intact until another command is
written.
Write address
Write
✻Read Status Register Command (7016)
Write data
When the command code “7016” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D0
to D7) by a read in the second bus cycle.
Status register
read
The status register is explained in the next section.
SR7 = 1 ?
NO
✻Clear Status Register Command (5016)
or
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that opera-
tion has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
RY/BY = 1 ?
YES
NO
Program
error
SR4 = 0 ?
YES
✻Program Command (4016)
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, the control circuit of flash memory
(data programming and verification) will start a program.
Whether the write operation is completed can be confirmed by
reading the status register or the RY/_B__Y__ Status Flag. When the
program starts, the read status register mode is entered automati-
cally and the contents of the status register is read at the data bus
(DB0 to DB7). The status register bit 7 (SR7) is set to “0” at the
same time the write operation starts and is returned to “1” upon
completion of the write operation. In this case, the read status reg-
ister mode remains active until the read array command (FF16) is
written.
Program
completed
Fig. 119 Program flowchart
Table 9 List of software commands (CPU rewrite mode)
First bus cycle
Data
Second bus cycle
Command
Cycle number
Data
to D7)
Mode
Address
Mode
Address
(D0 to D7)
(D
0
(Note 4)
Read array
1
2
1
Write
Write
Write
X
FF16
7016
5016
(Note 1)
Read status register
Clear status register
X
X
Read
X
SRD
(Note 2)
(Note 2)
Program
2
2
2
Write
Write
Write
X
X
X
4016
2016
2016
Write
Write
Write
WA
WD
Erase all blocks
X
2016
D016
(Note 3)
Block erase
BA
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address to be erased (Input the maximum address of each block.)
4: X denotes a given address in the User ROM area .
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✻Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that
follows, the operation of erase all blocks (erase and erase verify)
starts.
Start
Write 2016
Whether the erase all blocks command is terminated can be con-
____
firmed by reading the status register or the RY/BY Status Flag of
flash memory control register. When the erase all blocks operation
starts, the read status register mode is entered automatically and
the contents of the status register can be read out at the data bus
(D0 to D7). The status register bit 7 (SR7) is set to “0” at the same
time the erase operation starts and is returned to “1” upon comple-
tion of the erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is writ-
2016/D016
Block address
2016:Erase all blocks
D016:Block erase
Write
Status register
read
ten.
____
SR7 = 1 ?
or
RY/BY = 1 ?
NO
NO
The RY/BY Status Flag is “0” during erase operation and “1” when
the erase operation is completed as is the status register bit 7.
After the erase all blocks end, erase results can be checked by
reading the status register. For details, refer to the section where
the status register is detailed.
YES
Erase error
SR5 = 0 ?
✻Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the block address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
YES
Erase completed
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY Status Flag of flash
memory control register. At the same time the block erase opera-
tion starts, the read status register mode is automatically entered,
so that the contents of the status register can be read out. The
status register bit 7 (SR7) is set to “0” at the same time the block
erase operation starts and is returned to “1” upon completion of
the block erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is writ-
Fig. 120 Erase flowchart
ten.
____
The RY/BY Status Flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status reg-
ister bit 7.
After the block erase ends, erase results can be checked by read-
ing the status register. For details, refer to the section where the
status register is detailed.
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Status Register (SRD)
•Erase status (SR5)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to “1”.
The program status is set to “0” when it is cleared.
Also, the status register can be cleared by writing the clear status
register command (5016).
If “1” is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status regis-
ter command (5016) and clear the status register.
After reset, the status register is set to “8016”.
Table 10 shows the status register. Each bit in this register is ex-
plained below.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
Table 10 Definition of each bit in status register
Definition
Each bit of
SRD0 bits
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
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Full Status Check
By performing full status check, it is possible to know the execu-
tion results of erase and program operations. Figure 121 shows a
full status check flowchart and the action to be taken when each
error occurs.
Read status register
YES
SR4 = 1 and
SR5 = 1 ?
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
operation one more time after confirming that the
command is entered correctly.
NO
NO
NO
Should an erase error occur, the block in error
cannot be used.
Erase error
SR5 = 0 ?
YES
Should a program error occur, the block in error
cannot be used.
Program error
SR4 = 0 ?
YES
End (block erase, program)
Note: When one of SR5 and SR4 is set to “1”, none of the program, erase all blocks,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 121 Full status check flowchart and remedial procedure for errors
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Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check func-
tion for use in standard serial I/O mode.
If one or both of the pair of ROM Code Protect Bits is set to “0”,
the ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is se-
lected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM Code Protect Reset Bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be read out or modified. Once the ROM code
protect is turned on, the contents of the ROM Code Protect Reset
Bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM Code Pro-
tect Reset Bits.
✻ROM Code Protect Function
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control register (address FFDB16) in paral-
lel I/O mode. Figure 122 shows the ROM code protect control
register (address FFDB16). (This address exists in the User ROM
area.)
b7
b0
ROM code protect control register (address FFDB16
)
ROMCP
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (Note 3)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 1)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
Notes 1: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite
mode.
Fig. 122 Structure of ROM code protect control register
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ID Code Check Function
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the pro-
grammer is compared with the ID code written in the flash memory
to see if they match. If the ID codes do not match, the commands
sent from the programmer are not accepted. The ID code consists
of 8-bit data, and its areas are FFD416 to FFDA16. Write a pro-
gram which has had the ID code preset at these addresses to the
flash memory.
Address
FFD416
FFD516
FFD616
ID1
ID2
ID3
ID4
ID5
ID6
FFD716
FFD816
FFD916
ID7
FFDA16
FFDB16
ROM cord protect control
Interrupt vector area
Fig. 123 ID code store addresses
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(2) Parallel I/O Mode
Parallel I/O mode is the mode which parallel output and input soft-
ware command, address, and data required for the operations
(read, program, erase, etc.) to a built-in flash memory. Use the ex-
clusive external equipment flash programmer which supports the
38K0 Group (flash memory version). Refer to each programmer
maker’s handling manual for the details of the usage.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Fig-
ure 116 can be rewritten. Both areas of flash memory can be operated
on in the same way.
The boot ROM area is 4 Kbytes in size. It is located at addresses
F00016 through FFFF16. Make sure program and block erase opera-
tions are always performed within this address range. (Access to any
location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block.
The boot ROM area has had a standard serial I/O mode control pro-
gram stored in it when shipped from the Mitsubishi factory. There-
fore, using the device in standard serial I/O mode, you must perform
program and block erase in the user ROM area.
Rev.3.00 Oct 05, 2006 page 92 of 129
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(3) Standard Serial I/O Mode
Outline Performance (Standard Serial I/O
Mode)
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, pro-
gram, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires a purpose-specific pe-
ripheral unit.The standard serial I/O mode is different from the
parallel I/O mode in that the CPU controls flash memory rewrite
(uses the CPU rewrite mode), rewrite data input and so forth. The
standard serial I/O mode is started by connecting “H” to the P16
(CE) pin and “H” to the P42 (SCLK) pin and “H” to the CNVSS (VPP)
pin (apply 4.5 V to 5.25 V to Vpp from an external source), and re-
leasing the reset operation. (In the ordinary microcomputer mode,
set CNVss pin to “L” level.)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programer, etc.) using 4-wire clock-synchronized serial I/O.
In reception, software commands, addresses and program data
are synchronized with the rise of the transfer clock that is input to
the SCLK pin, and are then input to the MCU via the RxD pin. In
transmission, the read data and status are synchronized with the
fall of the transfer clock, and output from the TxD pin.
The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB
first.
When busy, such as during transmission, reception, erasing or
program execution, the SRDY (BUSY) pin is “H” level. Accordingly,
always start the next transfer after the SRDY (BUSY) pin is “L”
level.
This control program is written in the Boot ROM area when the
product is shipped from Renesas Technology Corp.. Accordingly,
make note of the fact that the standard serial I/O mode cannot be
used if the Boot ROM area is rewritten in parallel I/O mode. Figure
124 shows the pin connections for the standard serial I/O mode.
In standard serial I/O mode, serial data I/O uses the four serial I/O
pins SCLK, RxD, TxD and SRDY (BUSY). The SCLK pin is the trans-
fer clock input pin through which an external transfer clock is
input. The TxD pin is for CMOS output. The SRDY (BUSY) pin out-
puts “L” level when ready for reception and “H” level when
reception starts.
Also, data and status registers in a memory can be read after in-
putting software commands. Status, such as the operating state of
the flash memory or whether a program or erase operation ended
successfully or not, can be checked by reading the status register.
Here following explains software commands, status registers, etc.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in
Figure 116 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, commands sent from the peripheral
unit (programmer) are not accepted unless the ID code matches.
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Table 11 Description of pin function (Standard Serial I/O Mode)
Pin name
VCC,VSS
VCCE
Signal name
Power supply
I/O
Function
Apply 3.00 to 5.25 V (L version) to the Vcc pin and 0 V to the Vss pin.
Connect this pin to Vcc.
Power supply
VPP
CNVSS
I
I
I
Connect this pin to VPP (VPP = 4.50 to 5.25 V).
Connect this pin to Vss.
CNVSS2
VREF
CNVSS2
Analog reference voltage
Analog power supply
Analog power supply
Reset input
Connect this pin to Vcc when not using.
Connect this pin to Vcc.
DVCC, PVCC
PVSS
Connect this pin to Vss.
____________
RESET
I
To reset, input “L” level for 20 cycles or longer clocks of φ.
XIN
XOUT
Clock input
Clock output
I
O
Connect a ceramic or crystal resonator between the XIN and XOUT pins. When
entering an externally drived clock, enter it from XIN and leave XOUT open.
USBVREF
TrON
USB reference voltage input
USB reference voltage output
USB upstream input
Input port P0
Connect this pin to Vcc when not using.
Leave this pin open when not using.
Input “L” level when not using.
O
D0+,D0-
P00 to P07
P10 to P15
P16
I/O
I
I
Input “L” or “H” level, or keep open.
Input port P1
Input “L” or “H” level, or keep open.
Input port P1
I
Input “L” or “H” level, or keep open. Input “H” level only at release of reset.
Input “L” or “H” level, or keep open.
P17
Input port P1
I
P20 to P27
P30 to P37
P40
Input port P2
I
Input “L” or “H” level, or keep open.
Input port P3
I
Input “L” or “H” level, or keep open.
RxD input
I
This is a serial data input pin.
P41
TxD output
O
I
This is a serial data output pin.
P42
SCLK input
This is a serial clock input pin.Input “H” level only at release of reset.
This is a BUSY output pin.
P43
BUSY output
O
I
P50 to P57
P60 to P63
Input port P5
Input “L” or “H” level, or keep open.
Input port P6
I
Input “L” or “H” level, or keep open.
Rev.3.00 Oct 05, 2006 page 94 of 129
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38K0 Group
Vcc
Vss
32
31
30
29
28
P2
P2
P2
P2
P2
P2
D0-
D0+
TrON
5
49
50
51
52
53
54
55
56
57
58
59
60
P0
P0
6
7
4
3
RXD
P4
P4
P4
P4
0
/E
/E
2
X
DREQ/R
DACK/T
/E TC/SCLK
/E
XD
2
TXD
1
X
XD
X
1
S
CLK
27
26
25
24
23
22
21
20
0
BUSY
3
X
A
1
/SRDY
P30
P31
P32
M38K09F8LFP/HP
USBVREF
DVCC
PVCC
P3
3/E
X
INT
CS
WR
RD
A0
/AN
/AN
P3
4
/E
/E
/E
/E
/DQ
/DQ
X
P3
P3
P3
0
5
X
61
62
63
64
PVSS
6
X
19
18
17
7
X
P6
3
(LED
(LED
3)
P6
2
2)
P1
P1
0
0
P61(LED1)
1
1
1
Mode setup method
Signal
Value
CNVss
4.5 to 5.25 V
Vcc (Note 2)
Vss → Vcc
Connect to oscillator circuit.
S
CLK
(Note 1)
RESET
CE
Vcc (Note 2)
Notes 1: Connect to Vcc in the case of Vcc = 4.5 V to 5.25 V.
Connect to VPP (= 4.5 V to 5.25 V) in the case of Vcc = 3.0 V to 4.5 V.
2: Supply Vcc at releasimg Reset.
Package outline: PLQP0064GA-A, PLQP0064KB-A
Fig. 124 Pin connection diagram in standard serial I/O mode (1)
Rev.3.00 Oct 05, 2006 page 95 of 129
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Software Commands
here below. Basically, the software commands of the standard se-
rial I/O mode are the same as that of the parallel I/O mode, but the
block erase function is excluded, and 4 commands are added: ID
check, download, version data output and Boot ROM area output
functions.
Table 12 lists software commands. In standard serial I/O mode,
erase, program and read are controlled by transferring software
commands via the RxD pin. Software commands are explained
Table 12 Software commands (Standard serial I/O mode)
Control command
1st byte 2nd byte
transfer
3rd byte
4th byte
5th byte
6th byte
.....
When ID is
not verified
FF16
1
Page read
Address
(middle)
Address
(high)
Data
Data
Data
Data
output to
259th byte
Not
acceptable
output
output
output
Data input
to 259th
byte
2
3
Page program
4116
A716
Address
(middle)
Address
(high)
Data
input
Data
input
Data
input
Not
acceptable
Erase all blocks
D016
Not
acceptable
SRD1
output
Acceptable
SRD
output
4
5
Read status register
Clear status register
7016
5016
Not
acceptable
6
7
ID check function
Download function
F516
FA16
Address
(low)
Address
(middle)
Address
(high)
ID size
ID1
To ID7
Acceptable
Check-
sum
Size
(low)
Size
(high)
Data
input
To
Not
acceptable
required
number
of times
8
9
Version data output function
FB16
FC16
Version
data
output
Version
data
output
Version
data
output
Version
data
output
Version
data
output
Version
data output
to 9th byte
Acceptable
Address
(middle)
Address
(high)
Data
Data
Data
Data
output to
259th byte
Boot ROM area output
function
Not
acceptable
output
output
output
Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from a programmer to the in-
ternal flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted when the flash memory is totally blank.
4: Address low is A0 to A7; Address middle is A8 to A15; Address high is A16 to A23. Address-high A16 to A23 are always “0016”.
Rev.3.00 Oct 05, 2006 page 96 of 129
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The contents of software commands are explained as follows.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
✻Page Read Command
This command reads the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page read
command as explained here following.
(3) From the 4th byte onward, data (D0 to D7) for the page (256
bytes) specified with addresses A8 to A23 will be output se-
quentially from the smallest address first synchronized with the
fall of the clock.
S
CLK
A
8
to
A
16 to
RxD
TxD
FF16
A
15
A23
data0
data255
S
RDY (BUSY)
Fig. 125 Timing for page read
✻Read Status Register Command
This command reads status information. When the “7016” com-
mand code is transferred with the 1st byte, the contents of the
status register (SRD) with the 2nd byte and the contents of status
register 1 (SRD1) with the 3rd byte are read.
S
CLK
RxD
TxD
7016
SRD
output
SRD1
output
S
RDY (BUSY)
Fig. 126 Timing for reading status register
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✻Clear Status Register Command
This command clears the bits (SR3 to SR5) which are set when
the status register operation ends in error. When the “5016” com-
mand code is sent with the 1st byte, the aforementioned bits are
cleared. When the clear status register operation ends, the SRDY
(BUSY) signal changes from “H” to “L” level.
SCLK
RxD
5016
TxD
SRDY (BUSY)
Fig. 127 Timing for clear status register
✻Page Program Command
(3) From the 4th byte onward, as write data (D0 to D7) for the
page (256 bytes) specified with addresses A8 to A23 is input
sequentially from the smallest address first, that page is auto-
matically written.
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page pro-
gram command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
When reception setup for the next 256 bytes ends, the SRDY
(BUSY) signal changes from “H” to “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
S
CLK
A
8
A
to
15
A
16 to
4116
data0
RxD
TxD
data255
A23
S
RDY (BUSY)
Fig. 128 Timing for page program
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✻Erase All Blocks Command
When erase all blocks end, the SRDY (BUSY) signal changes from
“H” to “L” level. The result of the erase operation can be known by
reading the status register.
This command erases the contents of all blocks. Execute the
erase all blocks command as explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte.
With the verify command code, the erase operation will start
and continue for all blocks in the flash memory.
S
CLK
A716
D016
RxD
TxD
S
RDY (BUSY)
Fig. 129 Timing for erase all blocks
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✻Download Command
This command downloads a program to the RAM for execution.
Execute the download command as explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is
added to all data sent with the 5th byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches,
the downloaded program is executed. The size of the program will
vary according to the internal RAM.
S
CLK
Data size Data size
(low) (high)
Program
data
Check
sum
RxD
TxD
FA16
Program
data
S
RDY (BUSY)
Fig. 130 Timing for download
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(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte on-
ward.
✻Version Information Output Command
This command outputs the version information of the control pro-
gram stored in the Boot ROM area. Execute the version
information output command as explained here following.
This data is composed of 8 ASCII code characters.
S
CLK
RxD
TxD
FB16
‘V’
‘E’
‘R’
‘X’
S
RDY (BUSY)
Fig. 131 Timing for version information output
✻Boot ROM Area Output Command
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
This command reads the control program stored in the Boot ROM
area in page (256 bytes) unit. Execute the Boot ROM area output
command as explained here following.
(3) From the 4th byte onward, data (D0 to D7) for the page (256
bytes) specified with addresses A8 to A23 will be output se-
quentially from the smallest address first synchronized with the
fall of the clock.
S
CLK
RxD
TxD
FC16
A8
to A15
A16 to A23
data0
data255
S
RDY (BUSY)
Fig. 132 Timing for Boot ROM area output
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(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”)
of the 1st byte of the ID code with the 2nd, 3rd and 4th respec-
tively.
✻ID Check
This command checks the ID code. Execute the boot ID check
command as explained here following.
(3) Transfer the number of data sets of the ID code with the 5th
byte.
(4) Transfer the ID code with the 6th byte onward, starting with the
1st byte of the code.
S
CLK
ID size
ID1
ID7
RxD
TxD
F516
D416
FF16
0016
S
RDY (BUSY)
Fig. 133 Timing for ID check
✻ID Code
When the flash memory is not blank, the ID code sent from the se-
rial programmer and the ID code written in the flash memory are
compared to see if they match. If the codes do not match, the
command sent from the serial programmer is not accepted. An ID
code contains 8 bits of data. Area is, from the 1st byte, addresses
FFD416 to FFDA16. Write a program into the flash memory, which
already has the ID code set for these addresses.
Address
FFD416
ID1
FFD516
FFD616
FFD716
FFD816
FFD916
FFDA16
ID2
ID3
ID4
ID5
ID6
ID7
FFDB16
ROM code protect control
Interrupt vector area
Fig. 134 ID code storage addresses
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✻Status Register (SRD)
•Sequencer status (SR7)
The status register indicates operating status of the flash memory
and status such as whether an erase operation or a program
ended successfully or in error. It can be read by writing the read
status register command (7016). Also, the status register is
cleared by writing the clear status register command (5016).
Table 13 lists the definition of each status register bit. After releas-
ing the reset, the status register becomes “8016”.
The sequencer status indicates the operating status of the the
flash memory.
After power-on and recover from deep power down mode, the se-
quencer status is set to “1” (ready).
This status bit is set to “0” (busy) during write or erase operation
and is set to “1” upon completion of these operations.
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write opera-
tion. If a write error occurs, it is set to “1”. When the program
status is cleared, it is set to “0”.
Table 13 Status register (SRD)
Definition
SRD0 bits
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
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•Boot update completed bit (SR15)
✻Status Register 1 (SRD1)
This flag indicates whether the control program was downloaded
to the RAM or not, using the download function.
The status register 1 indicates the status of serial communica-
tions, results from ID checks and results from check sum
comparisons. It can be read after the SRD by writing the read sta-
tus register command (7016). Also, status register 1 is cleared by
writing the clear status register command (5016).
•Check sum consistency bit (SR12)
This flag indicates whether the check sum matches or not when a
program, is downloaded for execution using the download func-
tion.
Table 14 lists the definition of each status register 1 bit. This regis-
ter becomes “0016” when power is turned on and the flag status is
maintained even after the reset.
•ID check completed bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands
cannot be accepted without an ID check.
•Data reception time out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the re-
ceived data is discarded and the MCU returns to the command
wait state.
Table 14 Status register 1 (SRD1)
Definition
SRD1 bits
Status name
“1”
“0”
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
Boot update completed bit
Reserved
Update completed
Not Update
-
-
-
Reserved
-
Checksum match bit
ID check completed bits
Match
00
Mismatch
Not verified
01
Verification mismatch
Reserved
10
11
Verified
SR9 (bit1)
SR8 (bit0)
Data reception time out
Reserved
Time out
-
Normal operation
-
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Full Status Check
Results from executed erase and program operations can be
known by running a full status check. Figure 135 shows a flow-
chart of the full status check and explains how to remedy errors
which occur.
Read status register
YES
SR4 = 1 and
SR5 = 1 ?
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
operation one more time after confirming that the
command is entered correctly.
NO
NO
NO
Should an erase error occur, the block in error
cannot be used.
Erase error
SR5 = 0 ?
YES
Should a program error occur, the block in error
cannot be used.
Program error
SR4 = 0 ?
YES
End (Erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 135 Full status check flowchart and remedial procedure for errors
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Example Circuit Application for Standard
Serial I/O Mode
Figure 136 shows a circuit application for the standard serial I/O
mode. Control pins will vary according to a programmer, therefore
see a programmer manual for more information.
V
CC
VCC
S
CLK
Clock input
P16 (CE)
BUSY output
S
RDY (BUSY)
Data input
RxD
TxD
Data output
M38K09F8L
V
PP power
CNVss
source input
Notes 1: Control pins and external circuitry will vary according to a programmer. For more
information, see the programmer manual.
2: In this example, the VPP power supply is supplied from an external source (programmer).
To use the user’s power source, connect to 4.5 V to 5.25 V.
Fig. 136 Example circuit application for standard serial I/O mode
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NOTES ON PROGRAMMING
Instruction Execution Time
Processor Status Register
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction. However, When using the USB function or
EXB function, an occurrence of one-wait due to the multichannel
RAM will double an internal clock φ cycle.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
• When n (0 to 255) is written to a timer latch, the frequency divi-
sion ratio is 1/(n+1).
• When a count source of timer X is switched, stop a count of timer
X.
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
• The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
A/D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(system clock) in the middle/high-
speed mode is at least on 500 kHz during an A/D conversion.
Do not execute the STP or WIT instruction during an A/D conver-
sion.
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Definition of A/D Conversion Accuracy
The A/D conversion accuracy is defined below (refer to Figure
137).
✻ Non-linearity error
This means a deviation from the line between VOT and VFST of
a converted value between VOT and VFST.
✻ Differential non-linearity error
•Relative accuracy
This means a deviation from the input potential difference re-
quired to change a converted value between VOT and VFST by 1
LSB of the 1 LSB at the relative accuracy.
✻ Zero transition voltage (VOT)
This means an analog input voltage when the actual A/D con-
version output data changes from “0” to “1.”
✻ Full-scale transition voltage (VFST)
•Absolute accuracy
This means an analog input voltage when the actual A/D con-
version output data changes from “1023” to “1022.”
This means a deviation from the ideal characteristics between 0 to
VREF of actual A/D conversion characteristics.
Output data
Full-scale transition voltage (VFST
)
1023
1022
b-a
a
Differential non-linearity error=
c
[LSB]
Non-linearity error=
[LSB]
b
a
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB at relative accuracy
b: Vn+1-V
n
c: Difference between
the ideal Vn and actual Vn
Ideal line of A/D
conversion between
V0 to V1022
1
0
Vn
Vn+1
V0
V1
V1022
VREF
Analog voltage
Zero transition voltage (V0T
)
Fig. 137 Definition of A/D conversion accuracy
Vn: Analog input voltage when the output data changes from “n” to “n + 1” (n = 0 to 1022)
V
FST – VOT
1022
• 1 LSB at relative accuracy →
• 1 LSB at absolute accuracy →
(V)
(V)
V
REF
1024
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NOTES ON USAGE
USB Communication
Power Source Voltage
In applications requiring high-reliability, we recommend providing
the system with protective measures such as USB function initial-
ization by software or USB reset by the host to prevent USB
communication from being terminated unexpectedly, for example
due to external causes such as noise.
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less than
the recommended operating conditions and design a system not
to cause errors to the system by this unstable operation.
Flash Memory Version
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational in-
terference even if it is connected to Vss pin or Vcc pin via a
resistor.
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ce-
ramic or electrolytic capacitor of 1.0 µF is recommended.
Electric Characteristic Differences Between
Mask ROM and Flash Memory Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between Mask ROM and
Flash Memory version MCUs due to the difference in the manufac-
turing processes.
USB Port Pins (D0+, D0-) Treatment
•The USB specification requires a driver-impedance 28 to 44 Ω. In
order to meet the USB specification impedance requirements,
connect a resistor (27 Ω recommended) in series to the USB port
pins.
When manufacturing an application system with the Flash
Memory version and then switching to use of the Mask ROM ver-
sion, please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
In addition, in order to reduce the ringing and control the falling/
rising timing and a crossover point, connect a capacitor between
the USB port pins and the Vss pin if necessary.
The values and structure of those peripheral elements depend on
the impedance characteristics and the layout of the printed circuit
board. Accordingly, evaluate your system and observe waveforms
before actual use and decide use of elements and the values of
resistors and capacitors.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
✻
1. Mask ROM Order Confirmation Form
✻
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
•Make sure the USB D+/D- lines do not cross any other wires.
Keep a large GND area to protect the USB lines. Also, make sure
you use a USB specification compliant connecter for the connec-
tion.
✻ For the mask ROM confirmation and the mark specifications, re-
fer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com).
USBVREF pin Treatment (Noise Elimination)
•Connect a capacitor between the USBVREF pin and the Vss pin.
The capacitor should have a 2.2 µF capacitor (electrolytic capaci-
tor) and a 0.1 µF capacitor (ceramic type capacitor) connected in
parallel.
•In Vcc = 3.0 to 3.6 V operation, connect the USBVREF pin directly
to the Vcc pin in order to supply power to the USB port circuit. In
addition, you will need to disable the built-in USB reference volt-
age circuit in this operation (set bit 4 of the USB control register
to “0”.) If you are using the bus powered supply in this condition,
the DC-DC converter must be placed outside the MCU.
•In Vcc = 4.00 to 5.25 V operation, do not connect the external
DC-DC converter to the USBVREF pin. Use the built-in USB refer-
ence voltage circuit.
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 15 Absolute maximum ratings
Parameter
Unit
V
Symbol
VCC
Conditions
Ratings
–0.3 to 6.5
Power source voltage
AVCC
Analog power source voltage VCCE, VREF, PVCC, DVCC,
USBVREF
–0.3 to VCC + 0.3
V
All voltages are
based on VSS.
Output transistors
are cut off.
VI
Input voltage
P00–P07, P10–P17, P20–P27, P30–
P37, P40–P43, P50–P57, P60–P63
–0.3 to VCC + 0.3
V
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to 6.5
V
V
V
V
V
Input voltage
Input voltage
RESET, XIN, CNVSS2
VI
VI
CNVSS
Mask ROM version
Flash memory version
–0.5 to 3.8
Input voltage
D0+, D0-
VI
–0.3 to VCC + 0.3
Output voltage
P00–P07, P10–P17, P20–P27, P30–
P37, P40–P43, P50–P57, P60–P63,
XOUT
VO
–0.5 to 3.8
500
Output voltage
D0+, D0-, TrON
V
mW
°C
VO
Pd
Ta = 25°C
Power dissipation
(Note)
–20 to 85
25±5
Topr
MCU operating
Operating temperature
°C
In flash memory mode
(For flash memory ver-
sion)
°C
Tstg
–40 to 125
Storage temperature
Note: The maximum rating value depends on not only the MCU’s power dissipation but the heat consumption characteristics of the package.
Rev.3.00 Oct 05, 2006 page 110 of 129
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Recommended Operating Conditions
Table 16 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
V
Min.
4.00
Typ.
5.00
Max.
5.25
VCC
Power source voltage
VCC
System clock 12 MHz
(2-/4-/8-divide mode)
System clock 8 MHz
System clock 6 MHz
4.00
3.00
5.00
5.00
VCC
VCC
5.25
5.25
V
V
V
V
V
V
V
V
V
AVCC
AVCC
VREF
VREF
Analog power source voltage PVCC, DVCC
Analog power source voltage VCCE
VCC
3.6
Analog reference voltage
Analog reference voltage
VREF
2.0
3.0
3.0
USBVREF
Vcc = 3.6 to 4.0 V
Vcc = 3.0 to 3.6 V
VCC
VSS
AVSS
VIH
Power source voltage
VSS
0
0
Analog power source voltage PVSS
“H” input voltage
P00–P07, P20–P27, P50–P57,
P60–P63
VCC
V
V
0.8VCC
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P10–P17, P30–P37, P40–P43
RESET, XIN, CNVSS, CNVSS2
D0+, D0-
VCCE
VCC
V
V
V
V
VIH
VIH
0.8VCCE
0.8VCC
2.0
3.6
VIH
VIL
P00–P07, P20–P27, P50–P57,
P60–P63
0.2VCC
0
VIL
VIL
VIL
“L” input voltage
“L” input voltage
“L” input voltage
P10–P17, P30–P37, P40–P43
RESET, XIN, CNVSS, CNVSS2
D0+, D0-
V
V
V
0
0
0
0.2VCCE
0.2VCC
0.8
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Table 17 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
“H” total peak output current (Note 1)
Unit
mA
Min.
Typ.
Max.
∑IOH(peak)
P00–P07, P20–P27, P50–P57,
P60–P63
–80
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
“H” total peak output current (Note 1)
“L” total peak output current (Note 1)
“L” total peak output current (Note 1)
P10–P17, P30–P37, P40–P43
P00–P07, P20–P27, P50–P57
P60–P63
–80
80
mA
mA
mA
mA
mA
80
80
“L” total peak output current (Note 1)
“H” total average output current (Note 1)
P10–P17, P30–P37, P40–P43
–40
P00–P07, P20–P27, P50–P57,
P60–P63
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
∑IOL(avg)
IOH(peak)
–40
40
mA
mA
mA
mA
mA
“H” total average output current (Note 1)
“L” total average output current (Note 1)
“L” total average output current (Note 1)
“L” total average output current (Note 1)
“H” peak output current (Note 2)
P10–P17, P30–P37, P40–P43
P00–P07, P20–P27, P50–P57
P60–P63
40
40
P10–P17, P30–P37, P40–P43
–10
P00–P07, P20–P27, P50–P57,
P60–P63
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
mA
mA
mA
mA
mA
–10
10
20
10
–5
“H” peak output current (Note 2)
“L” peak output current (Note 2)
“L” peak output current (Note 2)
“L” peak output current (Note 2)
“H” average output current (Note 3)
P10–P17, P30–P37, P40–P43
P00–P07, P20–P27, P50–P57
P60–P63
P10–P17, P30–P37, P40–P43
P00–P07, P20–P27, P50–P57,
P60–P63
IOH(avg)
IOL(avg)
IOL(avg)
IOL(avg)
f(XIN)
–5
5
mA
mA
“H” average output current (Note 3)
“L” average output current (Note 3)
“L” average output current (Note 3)
“L” average output current (Note 3)
Main clock input oscillation frequency
(Note 4)
P10–P17, P30–P37, P40–P43
P00–P07, P20–P27, P50–P57
P60–P63
10
5
mA
mA
P10–P17, P30–P37, P40–P43
Vcc = 4.00 to 5.25 V
Vcc = 3.00 to 4.00 V
Vcc = 4.00 to 5.25 V
Vcc = 3.00 to 4.00 V
Vcc = 4.00 to 5.25 V
Vcc = 3.00 to 4.00 V
12
6
MHz
MHz
MHz
MHz
MHz
MHz
6
6
6
6
f(XIN) or
f(SYN)
f(φ)
12
6
System clock frequency
8
φ frequency
6
Notes 1: The total peak output current is the absolute value of the peak currents flowing through all the applicable ports. The total average output current is
the average value of the absolute value of the currents measured over 100 ms flowing through all the applicable ports.
2: The peak output current is the absolute value of the peak current flowing in each port.
3: The average output current is the average value of the absolute value of the currents measured over 100 ms.
4: The duty of oscillation frequency is 50 %. 6 MHz or 12 MHz is usable.
Rev.3.00 Oct 05, 2006 page 112 of 129
REJ03B0192-0300
38K0 Group (L Ver.)
Electrical Characteristics
Table 18 Electrical characteristics (1) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
IOH = –10 mA
Unit
V
Min.
Typ.
Max.
“H” output voltage
VCC–2.0
VOH
P00–P07, P20–P27, P50–P57, P60–P63
(Vcc = 4.00 to 5.25 V)
VCC–1.0
VCCE–2.0
V
V
IOH = –1 mA
“H” output voltage
IOH = –10 mA (VCCE =
4.00 to 5.25 V)
VOH
VOH
VOL
P10–P17, P30–P37, P40–P43
VCCE–1.0
V
V
IOH = –1 mA
D+ and D- pins pull-
down with 0 V via a
resistor of 15 kΩ ± 5 %
“H” output voltage
3.6
2.0
2.8
D0+, D0-
IOL = 10 mA
(Vcc = 4.00 to 5.25 V)
V
“L” output voltage
P00–P07, P20–P27, P50–P57
IOL = 1 mA
V
V
1.0
2.0
IOL = 20 mA
(Vcc = 4.00 to 5.25 V)
VOL
VOL
“L” output voltage
P60–P63
IOL = 1 mA
V
V
1.0
2.0
IOL = 10 mA (VCCE =
4.00 to 5.25 V)
“L” output voltage
P10–P17, P30–P37, P40–P43
IOL = 1 mA (VCCE =
3.00 to 5.25 V)
1.0
0.3
V
V
VOL
“L” output voltage
0
D+ and D- pins pull-up
with 3.6 V via a resistor
of 1.5 kΩ ± 5 %
D0+, D0-
Hysteresis
VT+–VT-
VT+–VT-
0.6
0.6
V
V
CNTR0, INT0, INT1
Hysteresis
P10/DQ0–P17/DQ7, P30–P32, P33/ExINT,
P34/ExCS, P35/ExWR, P36/ExRD, P37/
ExA0, P40/ExDREQ/RxD, P41/ExDACK/
TxD, P42/ExTC/SCLK, P43/ExA1/SRDY
VT+–VT
0.25
0.5
Hysteresis
D0+, D0-
V
Hysteresis RESET
VT+–VT-
V
“H” input current
VI = VCC (Pull-ups “off”)
5.0
IIH
µA
P00–P07, P20–P27, P50–P57, P60–P63
“H” input current
VI = VCCE
IIH
µA
5.0
5.0
P10–P17, P30–P37, P40–P43
“H” input current RESET, CNVSS
“H” input current XIN
IIH
IIH
IIL
µA
µA
µA
VI = VCC
VI = VCC
4.0
“L” input current
VI = VSS (Pull-ups “off”)
–5.0
–5.0
P00–P07, P20–P27, P50–P57, P60–P63
“L” input current
IIL
VI = VSS
µA
P10–P17, P30–P37, P40–P43
“L” input current RESET, CNVSS, CNVSS2
“L” input current XIN
µA
µA
µA
VI = VSS
VI = VSS
–5.0
IIL
IIL
IIL
–4.0
“L” input current P00–P07, P50, P52
(Pull-ups “on”)
VI = VSS
(Vcc = 4.00 to 5.25 V)
–60.0
–20.0
–120.0
VI = VSS
–10.0
µA
RAM hold voltage
When clock is stopped
2.00
5.25
V
VRAM
Rev.3.00 Oct 05, 2006 page 113 of 129
REJ03B0192-0300
38K0 Group (L Ver.)
Table 19 Electrical characteristics (2) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
ICC
Test conditions
Parameter
Unit
mA
Max.
60
Min.
f(XIN) = system clock = 12 MHz,
φ = 6 MHz,
USB reference voltage circuit enabled
Normal
mode
(Note 1)
21.0
Power source current
Vcc = 4.00
to 5.25 V
(Output transistor is
isolated.)
f(XIN) = 12 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
22.5
22.0
21.0
60
60
mA
mA
f(XIN) = 6 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit enabled
60
35
30
mA
mA
mA
mA
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
Vcc = 3.00
to 4.00 V
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
9.0
6.0
Vcc = 3.00
to 3.60 V
f(XIN) = 12 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
Vcc = 4.00
to 5.25 V
Wait
mode
(Note 2)
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
Vcc = 3.00
to 4.00 V
2.0
125.0
0.1
mA
µA
µA
µA
Stop
mode
(Note 3)
USB reference voltage circuit enabled
Low current mode
Vcc = 4.00
to 5.25 V
250
10
USB reference voltage circuit disabled
Ta = 25 °C
Vcc = 3.00
to 5.25 V
USB reference voltage circuit disabled
Ta = 85 °C
<Test conditions>
Notes 1: Operating in single-chip mode
Clock input from XIN pin (XOUT oscillator stopped)
fUSB = 48 MHz
All USB difference-input circuits enabled
Leaving I/O pins open
Operating functions: PLL circuit, CPU, Timers
2: Operating in single-chip mode with Wait mode
Clock input from XIN pin (XOUT oscillator stopped)
fUSB = 48 MHz
All USB difference-input circuits enabled
Leaving I/O pins open
Operating functions: PLL circuit, Timers, USB receiving
Disabled functions: CPU
3: Operating in single-chip mode with Stop mode
Oscillation stopped
All USB difference-input circuits disabled
Leaving I/O pins open
Rev.3.00 Oct 05, 2006 page 114 of 129
REJ03B0192-0300
38K0 Group (L Ver.)
Table 20 A/D Converter characteristics (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Bits
Min.
Typ.
Max.
10
—
—
—
Resolution
Linearity error
±3
LSB
LSB
Ta = 25 °C
±1.5
Differential nonlinear error
Zero transition voltage
Full scale transition voltage
Conversion time
Ta = 25 °C
0
15
35
mV
mV
VOT
VCC = VREF = 5.12 V
VCC = VREF = 5.12 V
VFST
5105
5125
5150
122
tCONV
tc(XIN)
or
tc(fSYN)
RLADDER
IVREF
35
kΩ
Ladder resistor
A/D converter operating; VREF = 5.0 V
A/D converter not operating; VREF = 5.0 V
µA
150
200
50
Reference power source input current
5
5.0
A/D port input current
II(AD)
µA
Rev.3.00 Oct 05, 2006 page 115 of 129
REJ03B0192-0300
38K0 Group (L Ver.)
Timing Requirements
Table 21 Timing requirements (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
tW(RESET)
Parameter
Unit
Min.
2
Max.
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC(XIN)
Main clock input cycle time
83
tWH(XIN)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0 input cycle time
35
tWL(XIN)
35
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
200
80
CNTR0 input “H” pulse width
CNTR0 input “L” pulse width
80
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
80
tWL(INT)
80
tC(SCLK)
800
370
370
220
100
tWH(SCLK)
tWL(SCLK)
tsu(RxD–SCLK)
th(SCLK–RxD)
Serial I/O input hold time
Note: These limits are the rating values in the clock synchronous mode, bit 6 of address 0FE016 = “1”. In the UART mode, bit 6 of address 0FE016 = “0”; the
rating values are set to one fourth.
Table 22 Timing requirements (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2
Typ.
Max.
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tW(RESET)
Main clock input cycle time
166
70
tC(XIN)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0 input cycle time
tWH(XIN)
70
tWL(XIN)
500
230
230
230
230
2000
950
950
400
200
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
CNTR0 input “H” pulse width
CNTR0 input “L” pulse width
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
tWL(INT)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(RxD–SCLK)
th(SCLK–RxD)
Serial I/O input hold time
Note: These limits are the rating values in the clock synchronous mode, bit 6 of address 0FE016 = “1”. In the UART mode, bit 6 of address 0FE016 = “0”; the
rating values are set to one fourth.
Rev.3.00 Oct 05, 2006 page 116 of 129
REJ03B0192-0300
38K0 Group (L Ver.)
Table 23 Timing requirements of external bus interface (EXB) (1)
(VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
tsu(S-R)
Parameter
Unit
Min.
Max.
ExCS setup time for read
ExCS setup time for write
ExCS hold time for read
ExCS hold time for write
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
tsu(S-W)
th(R-S)
0
0
th(W-S)
ExA0, ExA1 setup time for read
ExA0, ExA1 setup time for write
ExA0, ExA1 hold time for read
ExA0, ExA1 hold time for write
ExDACK setup time for read
ExDACK setup time for write
ExDACK hold time for read
ExDACK hold time for write
Read “H” pulse width
10
tsu(A-R)
tsu(A-W)
th(R-A)
10
0
0
th(W-A)
10
tsu(ACK-R)
tsu(ACK-W)
th(R-ACK)
th(W-ACK)
tWH(R)
10
0
0
80
Read “L” pulse width
80
tWL(R)
Write “H” pulse width
80
tWH(W)
Write “L” pulse width
80
tWL(W)
ExDACK “H” pulse width
120
tWH(ACK)
tWL(ACK)
tsu(D-W)
th(W-D)
ExDACK “L” pulse width
120
Data input setup time before write
Data input hold time after write
Data input setup time before ExDACK
Data input hold time after ExDACK
CPU clock cycle time
40
0
60
tsu(D-ACK)
th(ACK-W)
tC(φ)
5
125
Burst mode access cycle time
USB function not operating tC(φ)•3+10
tW(cycle)
USB function operating
tC(φ)•5+10
Rev.3.00 Oct 05, 2006 page 117 of 129
REJ03B0192-0300
38K0 Group (L Ver.)
Table 24 Timing requirements of external bus interface (EXB) (2)
(VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
tsu(S-R)
Parameter
Unit
Min.
Max.
ExCS setup time for read
ExCS setup time for write
ExCS hold time for read
ExCS hold time for write
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
tsu(S-W)
th(R-S)
0
0
th(W-S)
ExA0, ExA1 setup time for read
ExA0, ExA1 setup time for write
ExA0, ExA1 hold time for read
ExA0, ExA1 hold time for write
ExDACK setup time for read
ExDACK setup time for write
ExDACK hold time for read
ExDACK hold time for write
Read “H” pulse width
30
tsu(A-R)
tsu(A-W)
th(R-A)
30
0
0
th(W-A)
30
tsu(ACK-R)
tsu(ACK-W)
th(R-ACK)
th(W-ACK)
tWH(R)
30
0
0
120
Read “L” pulse width
120
tWL(R)
Write “H” pulse width
120
tWH(W)
Write “L” pulse width
120
tWL(W)
ExDACK “H” pulse width
160
tWH(ACK)
tWL(ACK)
tsu(D-W)
th(W-D)
ExDACK “L” pulse width
160
Data input setup time before write
Data input hold time after write
Data input setup time before ExDACK
Data input hold time after ExDACK
CPU clock cycle time
60
0
80
tsu(D-ACK)
th(ACK-W)
tC(φ)
10
166
Burst mode access cycle time
USB function not operating tC(φ)•3+30
tW(cycle)
USB function operating
tC(φ)•5+30
Rev.3.00 Oct 05, 2006 page 118 of 129
REJ03B0192-0300
38K0 Group (L Ver.)
Switching Characteristics
Table 25 Switching characteristics (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
tWH(SCLK)
Parameter
Unit
Min.
Typ.
Max.
140
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tC(SCLK)/2–30
tC(SCLK)/2–30
tWL(SCLK)
td(SCLK–TxD)
tv(SCLK–TxD)
tr(SCLK)
–30
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note)
CMOS output falling time (Note)
30
30
30
30
tf(SCLK)
tr(CMOS)
tf(CMOS)
Notes: Pins XOUT, D0+, D0- are excluded.
Table 26 Switching characteristics (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
tWH(SCLK)
Parameter
Unit
Min.
Typ.
Max.
350
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tC(SCLK)/2–50
tC(SCLK)/2–50
tWL(SCLK)
td(SCLK–TxD)
tv(SCLK–TxD)
tr(SCLK)
–30
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note)
CMOS output falling time (Note)
50
50
50
50
tf(SCLK)
tr(CMOS)
tf(CMOS)
Notes: Pins XOUT, D0+, D0- are excluded.
Measured output pin
100 pF
CMOS output
Fig. 138 Output switching characteristics measurement circuit
Rev.3.00 Oct 05, 2006 page 119 of 129
REJ03B0192-0300
38K0 Group (L Ver.)
Table 27 Switching characteristics of external bus interface (EXB) (1)
(VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Data output enable time after read
Unit
Max.
60
Min.
0
ns
ns
ns
ns
ns
ta(R-D)
Data output disable time after read
Data output enable time after ExDACK
Data output disable time after ExDACK
tv(R-D)
ta(ACK-D)
tv(ACK-D)
td(R-Mdis)
80
0
In cycle mode
Mch_req disable output delay time after read
tC(φ)+10
In cycle mode
Mch_req disable output delay time after write
td(W-Mdis)
td(R-Men)
td(W-Men)
ns
tC(φ)+10
ns
ns
USB function not operating
tC(φ)•3+10
tC(φ)•5+10
In cycle mode
Mch_req enable output delay time after read
USB function operating
USB function not operating
ns
ns
In cycle mode
Mch_req enable output delay time after write
tC(φ)•3+10
tC(φ)•5+10
USB function operating
Table 28 Switching characteristics of external bus interface (EXB) (2)
(VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Data output enable time after read
Unit
Max.
80
Min.
0
ns
ns
ns
ns
ns
ta(R-D)
Data output disable time after read
Data output enable time after ExDACK
Data output disable time after ExDACK
tv(R-D)
ta(ACK-D)
tv(ACK-D)
td(R-Mdis)
120
0
In cycle mode
Mch_req disable output delay time after read
tC(φ)+30
In cycle mode
Mch_req disable output delay time after write
td(W-Mdis)
td(R-Men)
td(W-Men)
ns
tC(φ)+30
ns
ns
ns
ns
USB function not operating
tC(φ)•3+30
tC(φ)•5+30
In cycle mode
Mch_req enable output delay time after read
USB function operating
USB function not operating
In cycle mode
Mch_req enable output delay time after write
tC(φ)•3+30
tC(φ)•5+30
USB function operating
Rev.3.00 Oct 05, 2006 page 120 of 129
REJ03B0192-0300
38K0 Group (L Ver.)
Table 29 Switching characteristics (USB ports) (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
USB full-speed output rising time
Unit
Typ.
Min.
4
Max.
20
ns
ns
%
V
tfr(D+/D-)
CL = 50 pF
tff(D+/D-)
USB full-speed output rising time
USB full-speed ports rising/falling ratio
USB output signal cross-over voltage
CL = 50 pF
4
20
tfrfm(D+/D-)
Vcrs(D+/D-)
tfr(D+/D-)/tff(D+/D-)
90
1.3
111.11
2.0
TrON
RL = 27 Ω
R
L
= 1.5 kΩ
Measured output pin
RL = 27 Ω
Measured output pin
C
L
RL = 15 kΩ
CL
RL = 15 kΩ
USB port output
USB port output
Fig. 139 USB output switching characteristics measurement circuit
(1) for D0-
Fig. 140 USB output switching characteristics measurement circuit
(2) for D0+
Rev.3.00 Oct 05, 2006 page 121 of 129
REJ03B0192-0300
38K0 Group
tC(CNTR)
t
WL(CNTR)
t
WH(CNTR)
0.8VCC
CNTR
0
0.2VCC
t
WL(INT)
t
WH(INT)
0.8VCC
INT
0/INT
1
0.2VCC
tW(RESET)
0.8
RESET
0.2VCC
VCC
t
C
(XIN)
t
WL(XIN)
t
WH(XIN)
0.8VCC
XIN
0.2VCC
[Serial I/O]
t
C
(SCLK
)
tr
tf
t
WL(SCLK
)
tWH(SCLK)
0.8VCC
E
SCLK
0.2VCC
E
t
su(RxD-SCLK
)
th(SCLK-RxD)
0.8VCC
E
E
RxD(at receive)
0.2VCC
td(SCLK-TxD)
tv(SCLK-TxD)
TxD (at transmit)
Fig. 141 Timing chart (1)
Rev.3.00 Oct 05, 2006 page 122 of 129
REJ03B0192-0300
38K0 Group
ꢀꢀTiming chart
[ EXB <CPU channel mode> ]
< Read >
t
su(A-R)
t
h(R-A)
0.8VCC
0.2VCC
ExA0, ExA1
t
su(S-R)
t
h(R-S)
0.2VCC
ExCS
ExRD
t
wL(R)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ
7
t
a(R-D)
t
v(R-D)
< Write >
t
su(A-W)
t
h(W-A)
0.8VCC
0.2VCC
ExA0, ExA1
t
su(S-W)
t
h(W-S)
0.2VCC
ExCS
t
wL(W)
0.8VCC
0.2VCC
ExWR
t
h(W-D)
t
su(D-W)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ
7
Fig. 142 Timing chart (2)
Rev.3.00 Oct 05, 2006 page 123 of 129
REJ03B0192-0300
38K0 Group
ꢀꢀTiming chart
[ EXB <Memory channel mode, Normal port function> ]
< Read >
t
su(A-R)
t
h(R-A)
0.8VCC
0.2VCC
ExA0, ExA1
t
su(S-R)
t
h(R-S)
0.2VCC
ExCS
ExRD
t
wL(R)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ
7
t
a(R-D)
t
v(R-D)
td(R-Men)
t
d(R-Mdis)
ExINT(Mch_req)
0.2VCC
0.2VCC
< Write >
t
su(A-W)
t
h(W-A)
0.8VCC
0.2VCC
ExA0, ExA1
t
su(S-W)
t
h(W-S)
0.2VCC
ExCS
t
wL(W)
0.8VCC
0.2VCC
ExWR
t
h(W-D)
t
su(D-W)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ
7
td(W-Men)
td(W-Mdis)
0.2VCC
ExINT(Mch_req)
0.2VCC
Fig. 143 Timing chart (3)
Rev.3.00 Oct 05, 2006 page 124 of 129
REJ03B0192-0300
38K0 Group
ꢀ Timing chart
[ EXB <Memory channel mode, DMA interface pin function,
Read and write signals used together mode> ]
< Read >
tsu(ACK-R)
th(R-ACK)
ExDACK
ExRD
0.2VCC
twL(R)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(R-D)
tv(R-D)
td(R-Mdis)
td(R-Men)
ExDREQ(Mch_req)
0.2VCC
0.2VCC
< Write >
ExDACK
tsu(ACK-W)
th(W-ACK)
0.2VCC
twL(W)
0.8VCC
0.2VCC
ExWR
th(W-D)
tsu(D-W)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
td(W-Mdis)
td(W-Men)
ExDREQ(Mch_req)
0.2VCC
0.2VCC
Fig. 144 Timing chart (4)
Rev.3.00 Oct 05, 2006 page 125 of 129
REJ03B0192-0300
38K0 Group
ꢀ Timing chart
[ EXB <Memory channel mode, DMA interface pin function,
Read and write signals not required mode> ]
< Read >
twL(ACK)
0.8VCC
0.2VCC
ExDACK
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(ACK-D)
tv(ACK-D)
td(ACK-Men)
td(ACK-Mdis)
ExDREQ(Mch_req)
0.2VCC
0.2VCC
twL(ACK)
< Write >
ExDACK
0.8VCC
0.2VCC
th(ACK-D)
tsu(D-ACK)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
td(ACK-Mdis)
td(ACK-Men)
ExDREQ(Mch_req)
0.2VCC
0.2VCC
Fig. 145 Timing chart (5)
Rev.3.00 Oct 05, 2006 page 126 of 129
REJ03B0192-0300
38K0 Group
ꢀ Timing chart
[ EXB <Memory channel mode, Burst transfer> ]
< Read >
ExDACK
twH(R)
0.8VCC
twL(R)
ExRD
0.2VCC
tw(cycle)
DQ0 to DQ7
tv(R-D)
ta(R-D)
td(R-Mdis)
ExDREQ(Mch_req)
0.2VCC
< Write >
ExDACK
twH(W)
0.8VCC
twL(W)
ExWR
0.2VCC
tw(cycle)
DQ0 to DQ7
th(W-D)
tsu(D-W)
td(W-Mdis)
ExDREQ(Mch_req)
0.2VCC
Fig. 146 Timing chart (6)
Rev.3.00 Oct 05, 2006 page 127 of 129
REJ03B0192-0300
38K0 Group
PACKAGE OUTLINE
PLQP0064GA-A
JEITA Package Code
RENESAS Code
Previous Code
64P6U-A
MASS[Typ.]
0.7g
P-LQFP64-14x14-0.80
PLQP0064GA-A
HD
*1
D
33
48
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
49
32
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
Terminal cross section
D
E
13.9 14.0 14.1
13.9 14.0 14.1
1.4
A2
HD
HE
A
15.8 16.0 16.2
15.8 16.0 16.2
1.7
64
17
A1
bp
b1
c
0.1 0.2
0
1
16
ZD
0.32 0.37 0.42
0.35
Index mark
F
0.145
0.125
0.09
0.20
c1
L
L1
0°
8°
e
x
0.8
y
Detail F
0.20
0.10
*3
e
bp
y
x
ZD
ZE
L
1.0
1.0
0.3 0.5 0.7
1.0
L1
Rev.3.00 Oct 05, 2006 page 128 of 129
REJ03B0192-0300
38K0 Group
PLQP0064KB-A
JEITA Package Code
RENESAS Code
PLQP0064KB-A
Previous Code
MASS[Typ.]
0.3g
P-LQFP64-10x10-0.50
64P6Q-A / FP-64K / FP-64KV
HD
D
*1
48
33
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
49
32
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
10.0 10.1
10.0 10.1
1.4
9.9
9.9
64
17
Terminal cross section
A2
HD
HE
A
11.8 12.0 12.2
11.8 12.0 12.2
1.7
1
16
Index mark
ZD
A1
bp
b1
c
0.05
0.15
0.1
0.15 0.20 0.25
0.18
F
0.09
0.20
0.145
0.125
c1
0°
8°
y
e
0.5
*3
L
bp
e
x
0.08
0.08
x
L1
y
Detail F
ZD
ZE
L
1.25
1.25
0.5
0.35
0.65
L1
1.0
Rev.3.00 Oct 05, 2006 page 129 of 129
REJ03B0192-0300
REVISION HISTORY
38K0 GROUP DATA SHEET
Rev.
Date
Description
Summary
Page
1.0
2.0
7/19/01
First edition issued
3/05/02 All pages The symbol “PRELIMINARY” is deleted from the header.
P. 1
Some Features are revised: Power source voltage, Power dissipation, Operating
temperature range.
Fig.1: The design of top view is revised.
Table 1: The Function of Vcc, VccE and USBVREF is revised.
100D0M package is added.
P. 3
P. 5
Table 2: The product M38K09RFS is added.
Fig. 7: The description of system clock division ratio selection bits is revised.
The explanations from pages 25 to 30 are added.
Fig. 31: The Function is revised.
P. 9
P. 25–30
P. 32
P. 49
P. 57
P. 58
Fig. 69: The Function is revised.
Fig. 76: Bit name of EXBIREQ. is revised:
Fig. 78: Note is added.
Fig. 79: Bit attributes are revised.
Fig. 84: Register symbol is revised.
P. 60
P. 72
P. 75
P. 76
P. 80
P. 81
P. 82
The explanations of A-D converter are revised.
The voltages regarding RESET is revised.
Some explanations of PLL CIRCUIT including the clock frequency is revised.
Fig. 114 is added.
The explanations of FLASH MEMORY MODE and Table 8 are revised.
The explanations of Microcomputer Mode and Boot Mode, and Fig.115 are re-
vised.
The explanations of Operation speed are revised.
P. 85
The explanations of (2) Parallel I/O Mode are revised.
The explanations of (3) Standard Serial I/O Mode are revised.
Table 11: The Function of Vcc, VccE, CNVss, P10 to P15, P16 and P17 is revised.
Fig. 123: The descriptions of CE and SCLK are added.
Fig. 135: P16 (CE) is added.
P. 92
P. 93
P. 94
P. 95
P. 106
P. 107
P. 108
P. 109
The explanations of Instruction Execution Time are revised.
The explanations of Definition of A-D Conversion Accuracy is added.
The explanations are added: USB Port Pins, USBVREF pin Treatment and Electric
Characteristic Differences Between Mask ROM and Flash Memory Version MCUs.
(1/3)
REVISION HISTORY
38K0 GROUP DATA SHEET
Rev.
2.0
Date
Description
Summary
Page
3/05/02 P. 110
P. 111
Table 15: Operating temperature is revised.
Table 16: Measuring conditions, Power source voltage Vcc and Analog power
source voltage VccE are revised. Analog power source voltage USBVREF
is added.
P. 112
P. 113
Table 17: Measuring conditions, f(XIN) and Notes 1 and 2 are revised. [f(XIN) or
f(SYN)] and f(φ) are added.
Table 18: Measuring conditions and some of VOH, VOL, VT+–VT- and IIL are re-
vised or added.
Table 19: The information are revised.
P. 114
P. 115
Table 20: Measuring conditions and IVREF are revised.
Tables 21 to 25: The information are revised or added.
P. 116 to
118
Figures 138 and 139 are added.
Fig. 140 is revised.
P. 118
P. 119
P. 1
2.1
10/09/02
FEATURES: USB specification ver.1.1→ Full-Speed USB2.0 specification
Power source voltage: Standard and L version are indicated respectively.
Power dissipation(at 3.3V): 45mW→ 30mW
2. of Notes is deleted.
Fig. 1: Product name of L version is added.
P. 3
P. 5
Table 1: Vcc and USBREF are revised.
Fig. 4: L version is added.
Table 3 is added. Subsequent table numbers are changed.
P. 16
P.25
Table 7: Key-on wake up is revised.
4th line: USB specification ver.1.1→ USB2.0 specification,
Ver1.1→ USB1.1 specification
Fig. 25: Tytle: Vcc condition is added. Capacitors are added.
Fig. 26 is added. Subsequent figure numbers are changed.
P. 27
P. 31
P. 38
P. 75
Fig. 30: EP00 transmit/receive byte number register→EP00 byte number register
Fig. 44: EP00 transmit/receive byte number register→EP00 byte number register
Power source voltage and reset input voltage of Standard and L version are indi-
cated.
Fig. 107:Reset release voltage of Standard and L version are indicated.
Table 9: Vcc of Standard and L version are indicated.
P. 81
P. 94
Table 12:Vcc of Standard and L version are indicated.
I/O of USBVREF: Input → empty, I/O of TrON: Empty → Output
P. 95
Fig.124: Product name of L version is added. Vcc when connect to Vpp is revised.
(2/3)
REVISION HISTORY
38K0 GROUP DATA SHEET
Rev.
2.1
Date
Description
Summary
Electrical characteristics of Standard and L version are indicated respectively (Those
Page
10/09/02
P. 111 --
of L version are indicated from page 119).
Table
17 to Tbale 21: Tytle: Vcc=3.00 to 5.25 V →Vcc=4.00 to 5.25 V, Vcc when system
clock 6MHz is deleted, 2,4-divide mode when system clock 12MHz is deleted.
Table 7: Vcc when system clock 8MHz→Vcc when system clock ≤ 8MHz
P. 111
P. 112
P. 113
P. 114
P. 116
P. 117
USBVREF is deleted.
Table 18:Vcc conditions of f(XIN), f(XIN) or f(SYN), and f(φ) are deleted. Data when
Vcc=3.00 to 4.00 V is deleted. Notes 4 is revised.
Table 19: Indications of Vcc and VccE in Test conditions are deleted. Data when
VI=VSS in IIL pull-up is deleted.
Table 20: Ranges of Vcc in Test conditions are deleted. Data when Vcc= 3.00 to
4.00 V is deleted. Typ. in normal mode are revised.
Timing requirements table when Vcc= 3.00 to 4.00 V is deleted.
Table 23 is added.
Switching characteristics table when Vcc= 3.00 to 4.00 V is deleted.
Table 25 is added.
Table 26: Tytle: Vcc=3.00 to 5.25 V→Vcc 4.00 to 5.25V
Electrical characteristics and switching characteristics of L version are added.
Timing chart (2) to (6) are added.
P. 118
P. 119 --
P. 131 --
3.0
10/05/06 All pages Package names “64P6U-A” → “PLQP0064GA-A” revised
Package names “64P6Q-A” → “PLQP0064KB-A” revised
P. 78
CLOCK GENERATING CIRCUIT; “No external resistor is needed .... resistor
exists on-chip.” → “No external resistor is needed .... depending on conditions.)
P. 79
Fig. 111; Pulled up added, NOTE added
P. 109
NOTES ON USAGE; Power Source Voltage, USB Communication added
P. 136,137 PACKAGE OUTLINE revised
(3/3)
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
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7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
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Tel: <852> 2265-6688, Fax: <852> 2730-6071
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Tel: <65> 6213-0200, Fax: <65> 6278-8001
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Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .6.0
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