M38K29FCLFP [RENESAS]
RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES; 瑞萨8位单片机740族/ 38000系列
| 型号： | M38K29FCLFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES |
| 文件： | 总358页 (文件大小：2605K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REJ09B0338-0200
38K2 Group
User's Manual
8
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev. 2.00
Revision date: Oct 15, 2006
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the
products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General
Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description
in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register settings and pins
are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are
not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
When the clock signal is generated with an external resonator (or from an external oscillator) during
a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,
when switching to a clock signal produced with an external resonator (or by an external oscillator)
while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm that the
change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different type numbers, implement a system-evaluation test for each of the products.
BEFORE USING THIS MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. Chapter 3 also includes necessary information for
systems development. You must refer to that chapter.
1. Organization
ꢀ CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
ꢀ CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
ꢀ CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the list of registers.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B 16
]
At reset
B
0
1
2
3
4
5
6
7
Name
Function
R
W
0b1 b00 : Single-chip mode
0 1 :
Processor mode bits
0
0
0
0
0
1
1 0 :
1 1 :
0 : 0 page
1 : 1 page
Not available
Stack page selection bit
ꢀ
ꢀ
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.”
0 : Operating
ꢀ
ꢀ
Main clock (XIN-XOUT) stop bit
1 : Stopped
0 : X -XOUT selected
1 : XICNIN-XCOUT selected
Internal system clock selection bit
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Note 1:. Contents immediately after reset release
0....... “0” at reset release
1....... “1” at reset release
?....... Undefined at reset release
ꢀ.......Contents determined by option at reset release
Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, write-
only and read and write. In the figure, these attributes are represented as follows :
R.......Read
...... Read enabled
ꢀ.......Read disabled
W......Write
..... Write enabled
ꢀ...... Write disabled
ꢀ.......“0” write
3. Supplementation
For details of software, refer to the “740 FAMILY SOFTWARE MANUAL.”
For details of development support tools, refer to the “Renesas Technology” Homepage (http://www.renesas.com).
Table of contents
38K2 Group
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................... 2
FEATURES......................................................................................................................................... 2
PIN CONFIGURATION ..................................................................................................................... 2
FUNCTIONAL BLOCK ..................................................................................................................... 3
PIN DESCRIPTION ........................................................................................................................... 4
PART NUMBERING .......................................................................................................................... 5
GROUP EXPANSION ....................................................................................................................... 6
Memory Type ............................................................................................................................... 6
Memory Size ................................................................................................................................ 6
Packages ...................................................................................................................................... 6
FUNCTIONAL DESCRIPTION ......................................................................................................... 7
Central Processing Unit (CPU) ................................................................................................. 7
Memory ....................................................................................................................................... 11
I/O Ports ..................................................................................................................................... 13
Interrupts .................................................................................................................................... 17
Timers ......................................................................................................................................... 20
Serial Interface .......................................................................................................................... 22
USB Function............................................................................................................................. 26
HUB Function............................................................................................................................. 58
External Bus Interface (EXB) .................................................................................................. 70
Multichannel RAM ..................................................................................................................... 89
A/D Converter ............................................................................................................................ 91
Watchdog Timer ........................................................................................................................ 93
Reset Circuit .............................................................................................................................. 94
PLL Circuit (Frequency Synthesizer) ...................................................................................... 95
Clock Generating Circuit .......................................................................................................... 97
Flash Memory Mode ............................................................................................................... 100
NOTES ON PROGRAMMING ...................................................................................................... 126
NOTES ON USAGE ...................................................................................................................... 128
DATA REQUIRED FOR MASK ORDERS ................................................................................. 128
FUNCTIONAL DESCRIPTION SUPPLEMENT .......................................................................... 129
CHAPTER 2 APPLICATION
2.1 I/O port ........................................................................................................................................ 2
2.1.1 Memory map ...................................................................................................................... 2
2.1.2 Related registers ............................................................................................................... 3
2.1.3 Handling of unused pins .................................................................................................. 5
2.1.4 Notes on input and output pins ...................................................................................... 6
2.1.5 Termination of unused pins ............................................................................................. 7
2.2 Interrupt ...................................................................................................................................... 8
2.2.1 Memory map ...................................................................................................................... 8
2.2.2 Related registers ............................................................................................................... 8
2.2.3 Interrupt source ............................................................................................................... 11
2.2.4 Interrupt operation........................................................................................................... 12
2.2.5 Interrupt control ............................................................................................................... 15
2.2.6 INT interrupt..................................................................................................................... 18
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2.2.7 Key input interrupt .......................................................................................................... 19
2.2.8 Notes on interrupts ......................................................................................................... 21
2.3 Timer.......................................................................................................................................... 23
2.3.1 Memory map .................................................................................................................... 23
2.3.2 Related registers ............................................................................................................. 23
2.3.3 Timer application examples ........................................................................................... 28
2.3.4 Notes on timer ................................................................................................................. 39
2.4 Serial I/O ................................................................................................................................... 40
2.4.1 Memory map .................................................................................................................... 40
2.4.2 Related registers ............................................................................................................. 41
2.4.3 Serial I/O connection examples .................................................................................... 45
2.4.4 Setting of serial I/O transfer data format .................................................................... 47
2.4.5 Serial I/O application examples .................................................................................... 48
2.4.6 Notes on serial I/O ......................................................................................................... 66
2.5 USB function ........................................................................................................................... 69
2.6 HUB function ........................................................................................................................... 70
2.7 External bus interface(EXB) ................................................................................................. 71
2.8 A/D converter .......................................................................................................................... 72
2.8.1 Memory map .................................................................................................................... 72
2.8.2 Related registers ............................................................................................................. 72
2.8.3 A/D converter application examples ............................................................................. 75
2.8.4 Notes on A/D converter ................................................................................................. 77
2.9 Watchdog timer ....................................................................................................................... 78
2.9.1 Memory map .................................................................................................................... 78
2.9.2 Related registers ............................................................................................................. 78
2.9.3 Watchdog timer application examples ........................................................................ 80
2.9.4 Notes on watchdog timer ............................................................................................... 81
2.10 Reset ....................................................................................................................................... 82
2.10.1 Connection example of reset IC ................................................................................. 82
____________
2.10.2 Notes on RESET pin .................................................................................................... 83
2.11 Frequency synthesizer (PLL) ............................................................................................. 84
2.11.1 Memory map .................................................................................................................. 84
2.11.2 Related registers ........................................................................................................... 84
2.11.3 Functional description ................................................................................................... 86
2.11.4 Notes on PLL ................................................................................................................ 89
2.12 Clock generating circuit ..................................................................................................... 90
2.12.1 Memory map .................................................................................................................. 90
2.12.2 Related registers ........................................................................................................... 90
2.12.3 Oscillation control.......................................................................................................... 92
2.13 Standby function .................................................................................................................. 95
2.13.1 Memory map .................................................................................................................. 95
2.13.2 Related registers ........................................................................................................... 95
2.13.3 Stop mode...................................................................................................................... 96
2.13.4 Wait mode .................................................................................................................... 100
2.13.5 Notes on stand-by function........................................................................................ 102
2.14 Flash memory...................................................................................................................... 103
2.14.1 Overview....................................................................................................................... 103
2.14.2 Memory map ................................................................................................................ 103
2.14.3 Related registers ......................................................................................................... 104
2.14.4 Parallel I/O mode ........................................................................................................ 105
2.14.5 Standard serial I/O mode........................................................................................... 105
2.14.6 CPU rewrite mode ...................................................................................................... 106
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38K2 Group
2.14.7 Flash memory mode application examples ............................................................. 107
2.14.8 Notes on CPU rewrite mode ..................................................................................... 112
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ........................................................................................................ 2
3.1.1 Absolute maximum ratings ............................................................................................... 2
3.1.2 Recommended operating conditions (L.Ver) ................................................................. 3
3.1.3 Electrical characteristics (L.Ver)...................................................................................... 5
3.1.4 A/D converter characteristics (L.Ver) ............................................................................. 7
3.1.5 Timing requirements (L.Ver) ............................................................................................ 8
3.1.6 Switching characteristics (L.Ver) ................................................................................... 11
3.2 Notes on use ........................................................................................................................... 20
3.2.1 Notes on input and output ports................................................................................... 20
3.2.2 Termination of unused pins ........................................................................................... 21
3.2.3 Notes on interrupts ......................................................................................................... 22
3.2.4 Notes on timer ................................................................................................................. 23
3.2.5 Notes on serial I/O ......................................................................................................... 24
3.2.6 Notes on USB function................................................................................................... 26
3.2.7 Notes on A/D converter ................................................................................................. 27
3.2.8 Notes on watchdog timer ............................................................................................... 27
_____________
3.2.9 Notes on RESET pin ...................................................................................................... 27
3.2.10 Notes onPLL .................................................................................................................. 27
3.2.11 Notes on stand-by function.......................................................................................... 28
3.2.12 Notes on CPU rewrite mode ....................................................................................... 28
3.2.13 Notes on programming ................................................................................................. 29
3.2.14 Notes on flash memory version .................................................................................. 31
3.2.15 Electric Characteristic Differences Between Mask ROM and Flash Memory Version
MCUs .............................................................................................................................. 31
3.3 Countermeasures against noise ......................................................................................... 32
3.3.1 Shortest wiring length ..................................................................................................... 32
3.3.2 Connection of bypass capacitor across VSS line and VCC line.................................. 34
3.3.3 Wiring to analog input pins ........................................................................................... 35
3.3.4 Oscillator concerns.......................................................................................................... 36
3.3.5 Setup for I/O ports.......................................................................................................... 37
3.3.6 Providing of watchdog timer function by software ..................................................... 38
3.4 List of registers ...................................................................................................................... 39
3.5 Package outline ...................................................................................................................... 83
3.6 Machine instructions ............................................................................................................. 86
3.7 List of instruction code ........................................................................................................ 97
3.8 SFR memory map ................................................................................................................... 98
3.9 Pin configurations .................................................................................................................. 99
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List of figures
38K2 Group
List of figures
CHAPTER 1 HARDWARE
Fig. 1 Pin configuration of 38K2 group ........................................................................................ 2
Fig. 2 Functional block diagram .................................................................................................... 3
Fig. 3 Part numbering ..................................................................................................................... 5
Fig. 4 Memory expansion plan ...................................................................................................... 6
Fig. 5 740 Family CPU register structure .................................................................................... 7
Fig. 6 Register push and pop at interrupt generation and subroutine call ............................. 8
Fig. 7 Structure of CPU mode register ...................................................................................... 10
Fig. 8 Memory map diagram........................................................................................................ 11
Fig. 9 Memory map of special function register (SFR)............................................................ 12
Fig. 10 Port block diagram (1) .................................................................................................... 14
Fig. 11 Port block diagram (2) .................................................................................................... 15
Fig. 12 Structure of port I/O-related registers ........................................................................... 16
Fig. 13 Interrupt control ................................................................................................................ 18
Fig. 14 Structure of interrupt-related registers .......................................................................... 18
Fig. 15 Connection example when using key input interrupt and port P0 block diagram .. 19
Fig. 16 Structure of timer X mode register ............................................................................... 20
Fig. 17 Timer block diagram ........................................................................................................ 21
Fig. 18 Block diagram of clock synchronous serial I/O ........................................................... 22
Fig. 19 Operation of clock synchronous serial I/O function .................................................... 22
Fig. 20 Block diagram of UART serial I/O................................................................................. 23
Fig. 21 Operation of UART serial I/O function.......................................................................... 23
Fig. 22 Structure of serial I/O control registers ........................................................................ 25
Fig. 23 USB function overview .................................................................................................... 26
Fig. 24 USB Function Control Circuit (USBFCC) block diagram............................................ 27
Fig. 25 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (4.0V ≤ VCC
≤ 5.25V) ........................................................................................................................... 28
Fig. 26 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (3.0V ≤ VCC
≤ 4.0V) ............................................................................................................................. 28
Fig. 27 Example setting of buffer area beginning address ..................................................... 29
Fig. 28 Examples of interrupt source dependant buffer area offset address ....................... 29
Fig. 29 USB device interrupt control .......................................................................................... 31
Fig. 30 USB related registers ...................................................................................................... 32
Fig. 31 Structure of USB control register .................................................................................. 33
Fig. 32 Structure of USB function/HUB enable register .......................................................... 33
Fig. 33 Structure of USB function address register ................................................................. 34
Fig. 34 Structure of USB HUB address register ....................................................................... 34
Fig. 35 Structure of Frame number register Low ..................................................................... 34
Fig. 36 Structure of Frame number register High .................................................................... 34
Fig. 37 Structure of USB interrupt source enable register...................................................... 35
Fig. 38 Structure of USB interrupt source register................................................................... 36
Fig. 39 Structure of Endpoint index register ............................................................................. 37
Fig. 40 Structure of EP00 stage register ................................................................................... 38
Fig. 41 Structure of EP00 control register 1 ............................................................................. 38
Fig. 42 Structure of EP00 control register 2 ............................................................................. 38
Fig. 43 Structure of EP00 control register 3 ............................................................................. 39
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38K2 Group
Fig. 44 Structure of EP00 interrupt source register ................................................................. 39
Fig. 45 Structure of EP00 byte number register....................................................................... 40
Fig. 46 Structure of EP00 buffer area set register................................................................... 40
Fig. 47 Structure of EP01 set register ....................................................................................... 41
Fig. 48 Structure of EP01 control register 1 ............................................................................. 41
Fig. 49 Structure of EP01 control register 2 ............................................................................. 42
Fig. 50 Structure of EP01 control register 3 ............................................................................. 42
Fig. 51 Structure of EP01 interrupt source register ................................................................. 42
Fig. 52 Structure of EP01 byte number register 0 ................................................................... 43
Fig. 53 Structure of EP01 byte number register 1 ................................................................... 43
Fig. 54 Structure of EP01 MAX. packet size register .............................................................. 43
Fig. 55 Structure of EP01 buffer area set register................................................................... 44
Fig. 56 Structure of EP02 set register ....................................................................................... 45
Fig. 57 Structure of EP02 control register 1 ............................................................................. 45
Fig. 58 Structure of EP02 control register 2 ............................................................................. 46
Fig. 59 Structure of EP02 control register 3 ............................................................................. 46
Fig. 60 Structure of EP02 interrupt source register ................................................................. 46
Fig. 61 Structure of EP02 byte number register 0 ................................................................... 47
Fig. 62 Structure of EP02 byte number register 1 ................................................................... 47
Fig. 63 Structure of EP02 MAX. packet size register .............................................................. 47
Fig. 64 Structure of EP02 buffer area set register................................................................... 48
Fig. 65 Structure of EP03 set register ....................................................................................... 49
Fig. 66 Structure of EP03 control register 1 ............................................................................. 49
Fig. 67 Structure of EP03 control register 2 ............................................................................. 50
Fig. 68 Structure of EP03 control register 3 ............................................................................. 50
Fig. 69 Structure of EP03 interrupt source register ................................................................. 50
Fig. 70 Structure of EP03 byte number register 0 ................................................................... 51
Fig. 71 Structure of EP03 byte number register 1 ................................................................... 51
Fig. 72 Structure of EP03 MAX. packet size register .............................................................. 51
Fig. 73 Structure of EP03 buffer area set register................................................................... 52
Fig. 74 Structure of EP10 stage register ................................................................................... 53
Fig. 75 Structure of EP10 control register 1 ............................................................................. 53
Fig. 76 Structure of EP10 control register 2 ............................................................................. 53
Fig. 77 Structure of EP10 control register 3 ............................................................................. 54
Fig. 78 Structure of EP10 interrupt source register ................................................................. 54
Fig. 79 Structure of EP10 byte number register....................................................................... 55
Fig. 80 Structure of EP10 buffer area set register................................................................... 55
Fig. 81 Structure of EP11 set register ....................................................................................... 56
Fig. 82 Structure of EP11 control register 1 ............................................................................. 56
Fig. 83 Structure of EP11 control register 2 ............................................................................. 56
Fig. 84 Structure of EP11 interrupt source register ................................................................. 57
Fig. 85 Structure of EP11 byte number register....................................................................... 57
Fig. 86 Structure of EP11 buffer area set register................................................................... 57
Fig. 87 HUB functions................................................................................................................... 58
Fig. 88 HUB function control circuit block diagram .................................................................. 59
Fig. 89 Block diagram of USB down-port peripheral circuits (D1+, D1-) .............................. 60
Fig. 90 Block diagram of USB down-port peripheral circuits (D2+, D2-) .............................. 60
Fig. 91 USB HUB interrupt control ............................................................................................. 61
Fig. 92 HUB related registers ...................................................................................................... 62
Fig. 93 Structure of HUB interrupt source enable register ..................................................... 63
Fig. 94 Structure of HUB interrupt source register .................................................................. 63
Fig. 95 Structure of HUB downstream port index register ...................................................... 64
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List of figures
38K2 Group
Fig. 96 Structure of DP1 interrupt source register ................................................................... 65
Fig. 97 Structure of DP1 control register................................................................................... 66
Fig. 98 Structure of DP1 status register .................................................................................... 66
Fig. 99 Structure of DP2 interrupt source register ................................................................... 67
Fig. 100 Structure of DP2 control register................................................................................. 68
Fig. 101 Structure of DP2 status register .................................................................................. 68
Fig. 102 Structure of Downstream port control register .......................................................... 69
Fig. 103 External bus interface ................................................................................................... 70
Fig. 104 Data transfer timing of memory channel .................................................................... 70
Fig. 105 External bus interface (EXB) pin assignment ............................................................ 71
Fig. 106 Block diagram of external bus interface (EXB) ......................................................... 72
Fig. 107 EXB related registers (1) .............................................................................................. 76
Fig. 108 EXB related registers (2) .............................................................................................. 76
Fig. 109 Structure of EXB interrupt source enable register .................................................... 77
Fig. 110 Structure of EXB interrupt source register ................................................................. 77
Fig. 111 Structure of EXB index register ................................................................................... 78
Fig. 112 Structure of Register window 1 ................................................................................... 78
Fig. 113 Structure of Register window 2 ................................................................................... 78
Fig. 114 Index00[low]; Structure of External I/O configuration register................................. 79
Fig. 115 Index00[high]; Structure of External I/O configuration register.............................. 79
Fig. 116 Index01[low]; Structure of Transmit/Receive buffer register .................................... 80
Fig. 117 Index02[low]; Structure of Memory channel operation mode register .................... 80
Fig. 118 Index03[low]; Structure of Memory address counter ................................................ 80
Fig. 119 Index03[high]; Structure of Memory address counter ............................................... 81
Fig. 120 Index04[low]; Structure of End address register ....................................................... 81
Fig. 121 Index04[high]; Structure of End address register...................................................... 81
Fig. 122 CPU channel receiving operation ................................................................................ 82
Fig. 123 CPU channel tranmitting operation ............................................................................. 83
Fig. 124 Memory channel receiving operation (1) .................................................................... 84
Fig. 125 Memory channel receiving operation (2) .................................................................... 85
Fig. 126 Memory channel receiving operation (3) .................................................................... 86
Fig. 127 Memory channel tranmitting operation (1) ................................................................. 87
Fig. 128 Memory channel tranmitting operation (2) ................................................................. 88
Fig. 129 Multichannel RAM timing diagram (no wait) .............................................................. 89
Fig. 130 Multichannel RAM timing diagram (one wait) ............................................................ 89
Fig. 131 Multichannel RAM operation example......................................................................... 90
Fig. 132 Structure of AD control register................................................................................... 91
Fig. 133 10-bit A/D mode reading .............................................................................................. 91
Fig. 134 A/D converter block diagram........................................................................................ 92
Fig. 135 Block diagram of Watchdog timer ............................................................................... 93
Fig. 136 Structure of Watchdog timer control register............................................................. 93
Fig. 137 Example of reset circuit ................................................................................................ 94
Fig. 138 Reset sequence ............................................................................................................. 94
Fig. 139 Block diagram of PLL circuit ........................................................................................ 95
Fig. 140 Structure of PLL control register ................................................................................. 96
Fig. 141 Ceramic resonator or quartz-crystal oscilltor circuit ................................................. 98
Fig. 142 External clock input circuit ........................................................................................... 98
Fig. 143 Structure of MISRG ....................................................................................................... 98
Fig. 144 System clock generating circuit block diagram (single-chip mode) ........................ 98
Fig. 145 State transitions of clock .............................................................................................. 99
Fig. 146 Block diagram of built-in flash memory .................................................................... 101
Fig. 147 Structure of flash memory control register............................................................... 102
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List of figures
38K2 Group
Fig. 148 CPU rewrite mode set/release flowchart .................................................................. 103
Fig. 149 Program flowchart ........................................................................................................ 105
Fig. 150 Erase flowchart ............................................................................................................ 106
Fig. 151 Full status check flowchart and remedial procedure for errors ............................ 108
Fig. 152 Structure of ROM code protect control register ...................................................... 109
Fig. 153 ID code store addresses ............................................................................................ 110
Fig. 154 Pin connection diagram in standard serial I/O mode (1)....................................... 114
Fig. 155 Timing for page read................................................................................................... 116
Fig. 156 Timing for reading status register ............................................................................. 116
Fig. 157 Timing for clear status register.................................................................................. 117
Fig. 158 Timing for page program ............................................................................................ 117
Fig. 159 Timing for erase all blocks ......................................................................................... 118
Fig. 160 Timing for download .................................................................................................... 119
Fig. 161 Timing for version information output ....................................................................... 120
Fig. 162 Timing for Boot ROM area output............................................................................. 120
Fig. 163 Timing for ID check ..................................................................................................... 121
Fig. 164 ID code storage addresses ........................................................................................ 121
Fig. 165 Full status check flowchart and remedial procedure for errors ............................ 124
Fig. 166 Example circuit application for standard serial I/O mode ...................................... 125
Fig. 167 Definition of A/D conversion accuracy ...................................................................... 127
Fig. 168 A/D conversion equivalent circuit .............................................................................. 130
Fig. 169 A/D conversion timing chart ....................................................................................... 130
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of registers related to I/O port .............................................................. 2
Fig. 2.1.2 Structure of Port Pi (i = 0 to 6).................................................................................... 3
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6) ..................................................... 3
Fig. 2.1.4 Structure of Port P0 pull-up control register ............................................................... 4
Fig. 2.1.5 Structure of Port P5 pull-up control register ............................................................... 4
Fig. 2.2.1 Memory map of registers related to interrupt ............................................................. 8
Fig. 2.2.2 Structure of Interrupt request register 1 ...................................................................... 8
Fig. 2.2.3 Structure of Interrupt request register 2 ...................................................................... 9
Fig. 2.2.4 Structure of Interrupt control register 1 ....................................................................... 9
Fig. 2.2.5 Structure of Interrupt control register 2 ..................................................................... 10
Fig. 2.2.6 Structure of Interrupt edge selection register ........................................................... 10
Fig. 2.2.7 Interrupt operation diagram.......................................................................................... 12
Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
........................................................................................................................................ 13
Fig. 2.2.9 Time up to execution of interrupt processing routine .............................................. 14
Fig. 2.2.10 Timing chart after acceptance of interrupt request .............................................. 14
Fig. 2.2.11 Interrupt control diagram ............................................................................................ 15
Fig. 2.2.12 Example of multiple interrupts................................................................................... 17
Fig. 2.2.13 Connection example and port P0 block diagram when using key input interrupt .
...................................................................................................................................... 19
Fig. 2.2.14 Registers setting related to key input interrupt (corresponding to Figure 2.2.13).
...................................................................................................................................... 20
Fig. 2.2.15 Sequence of changing relevant register .................................................................. 21
Fig. 2.2.16 Sequence of check of interrupt request bit............................................................. 22
Fig. 2.3.1 Memory map of registers related to timers ............................................................... 23
Fig. 2.3.2 Structure of Prescaler 12, Prescaler X ...................................................................... 23
Fig. 2.3.3 Structure of Timer 1 ..................................................................................................... 24
Fig. 2.3.4 Structure of Timer 2, Timer X ..................................................................................... 24
Rev.2.00 Oct 15, 2006 page 7 of 14
REJ09B0338-0200
List of figures
38K2 Group
Fig. 2.3.5 Structure of Timer X mode register............................................................................ 25
Fig. 2.3.6 Structure of Interrupt request register 1 .................................................................... 26
Fig. 2.3.7 Structure of Interrupt request register 2 .................................................................... 26
Fig. 2.3.8 Structure of Interrupt control register 1 ..................................................................... 27
Fig. 2.3.9 Structure of Interrupt control register 2 ..................................................................... 27
Fig. 2.3.10 Timers connection and setting of division ratios .................................................... 29
Fig. 2.3.11 Related registers setting ............................................................................................ 29
Fig. 2.3.12 Control procedure........................................................................................................ 30
Fig. 2.3.13 Peripheral circuit example.......................................................................................... 31
Fig. 2.3.14 Timers connection and setting of division ratios .................................................... 31
Fig. 2.3.15 Related registers setting ............................................................................................ 32
Fig. 2.3.16 Control procedure........................................................................................................ 32
Fig. 2.3.17 Judgment method of valid/invalid of input pulses .................................................. 33
Fig. 2.3.18 Related registers setting ............................................................................................ 34
Fig. 2.3.19 Control procedure........................................................................................................ 35
Fig. 2.3.20 Timers connection and setting of division ratios .................................................... 36
Fig. 2.3.21 Related registers setting ............................................................................................ 37
Fig. 2.3.22 Control procedure........................................................................................................ 38
Fig. 2.4.1 Memory map of registers related to Serial I/O ......................................................... 40
Fig. 2.4.2 Structure of Transmit/Receive buffer register ........................................................... 41
Fig. 2.4.3 Structure of Serial I/O status register ........................................................................ 41
Fig. 2.4.4 Structure of Serial I/O control register ....................................................................... 42
Fig. 2.4.5 Structure of UART control register ............................................................................. 42
Fig. 2.4.6 Structure of Baud rate generator ................................................................................ 43
Fig. 2.4.7 Structure of Interrupt edge selection register ........................................................... 43
Fig. 2.4.8 Structure of Interrupt request register 2 .................................................................... 44
Fig. 2.4.9 Structure of Interrupt control register 2 ..................................................................... 44
Fig. 2.4.10 Serial I/O connection examples (1) .......................................................................... 45
Fig. 2.4.11 Serial I/O connection examples (2) .......................................................................... 46
Fig. 2.4.12 Serial I/O transfer data format .................................................................................. 47
Fig. 2.4.13 Connection diagram .................................................................................................... 48
Fig. 2.4.14 Timing chart ................................................................................................................. 48
Fig. 2.4.15 Registers setting related to transmitting side ......................................................... 49
Fig. 2.4.16 Registers setting related to receiving side .............................................................. 50
Fig. 2.4.17 Control procedure of transmitting side..................................................................... 51
Fig. 2.4.18 Control procedure of receiving side ......................................................................... 52
Fig. 2.4.19 Connection diagram .................................................................................................... 53
Fig. 2.4.20 Timing chart ................................................................................................................. 53
Fig. 2.4.21 Registers setting related to Serial I/O ..................................................................... 54
Fig. 2.4.22 Setting of serial I/O transmission data .................................................................... 54
Fig. 2.4.23 Control procedure of Serial I/O................................................................................. 55
Fig. 2.4.24 Connection diagram .................................................................................................... 56
Fig. 2.4.25 Timing chart ................................................................................................................. 57
Fig. 2.4.26 Related registers setting ............................................................................................ 57
Fig. 2.4.27 Control procedure of master unit .............................................................................. 58
Fig. 2.4.28 Control procedure of slave unit ................................................................................ 59
Fig. 2.4.29 Connection diagram (Communication using UART) ............................................... 60
Fig. 2.4.30 Timing chart (using UART) ........................................................................................ 60
Fig. 2.4.31 Registers setting related to transmitting side ......................................................... 62
Fig. 2.4.32 Registers setting related to receiving side .............................................................. 63
Fig. 2.4.33 Control procedure of transmitting side..................................................................... 64
Fig. 2.4.34 Control procedure of receiving side ......................................................................... 65
Fig. 2.4.35 Sequence of setting serial I/O control register again ............................................ 67
Rev.2.00 Oct 15, 2006 page 8 of 14
REJ09B0338-0200
List of figures
38K2 Group
Fig. 2.8.1 Memory map of registers related to A/D converter.................................................. 72
Fig. 2.8.2 Structure of AD control register .................................................................................. 72
Fig. 2.8.3 Structure of AD conversion register 1 ....................................................................... 73
Fig. 2.8.4 Structure of AD conversion register 2 ....................................................................... 73
Fig. 2.8.5 Structure of Interrupt request register 2 .................................................................... 74
Fig. 2.8.6 Structure of Interrupt control register 2 ..................................................................... 74
Fig. 2.8.7 Connection diagram ...................................................................................................... 75
Fig. 2.8.8 Related registers setting .............................................................................................. 75
Fig. 2.8.9 Control procedure for 8-bit read ................................................................................. 76
Fig. 2.8.10 Control procedure for 10-bit read ............................................................................. 76
Fig. 2.9.1 Memory map of registers related to watchdog timer ............................................... 78
Fig. 2.9.2 Structure of Watchdog timer control register ............................................................ 78
Fig. 2.9.3 Structure of CPU mode register ................................................................................. 79
Fig. 2.9.4 Watchdog timer connection and division ratio setting ............................................. 80
Fig. 2.9.5 Related registers setting .............................................................................................. 81
Fig. 2.9.6 Control procedure.......................................................................................................... 81
Fig. 2.10.1 Example of poweron reset circuit ............................................................................. 82
Fig. 2.10.2 RAM backup system ................................................................................................... 82
Fig. 2.11.1 Memory map of registers related to PLL................................................................. 84
Fig. 2.11.2 Structure of USB control register ............................................................................. 84
Fig. 2.11.3 Structure of CPU mode register ............................................................................... 85
Fig. 2.11.4 Structure of PLL control register .............................................................................. 85
Fig. 2.11.5 Block diagram for frequency synthesizer circuit ..................................................... 86
Fig. 2.11.6 Related registers setting when hardware reset ...................................................... 87
Fig. 2.11.7 Related registers setting when stop mode .............................................................. 88
Fig. 2.11.8 Related registers setting when recovery from stop mode .................................... 89
Fig. 2.12.1 Memory map of registers related to clock generating circuit ............................... 90
Fig. 2.12.2 Structure of USB control register ............................................................................. 90
Fig. 2.12.3 Structure of CPU mode register ............................................................................... 91
Fig. 2.12.4 Structure of PLL control register .............................................................................. 91
Fig. 2.12.5 Related registers setting ............................................................................................ 92
Fig. 2.12.6 Related registers setting ............................................................................................ 94
Fig. 2.13.1 Memory map of registers related to standby function ........................................... 95
Fig. 2.13.2 Structure of MISRG .................................................................................................... 95
Fig. 2.13.3 Oscillation stabilizing time at restoration by reset input ....................................... 97
Fig. 2.13.4 Execution sequence example at restoration by occurrence of INT interrupt request
0
...................................................................................................................................... 99
Fig. 2.13.5 Reset input time ........................................................................................................ 101
Fig. 2.14.1 Memory map of flash memory version for 38K2 Group ...................................... 103
Fig. 2.14.2 Memory map of registers related to flash memory .............................................. 104
Fig. 2.14.3 Structure of Flash memory control register........................................................... 104
Fig. 2.14.4 Rewrite example of built-in flash memory in standard serial I/O mode............ 107
Fig. 2.14.5 Connection example in standard serial I/O mode (1).......................................... 108
Fig. 2.14.6 Connection example in standard serial I/O mode (2).......................................... 108
Fig. 2.14.7 Connection example in standard serial I/O mode (3).......................................... 109
Fig. 2.14.8 Example of rewrite system for built-in flash memory in CPU rewrite mode .... 110
Fig. 2.14.9 CPU rewrite mode beginning/release flowchart .................................................... 111
CHAPTER 3 APPENDIX
Fig. 3.1.1 Output switching characteristics measurement circuit ............................................. 11
Fig. 3.1.2 USB output switching characteristics measurement circuit (1) for D0-, D1+/D2+ (low-speed),
D1-/D2- (full-speed) ....... 13
Rev.2.00 Oct 15, 2006 page 9 of 14
REJ09B0338-0200
List of figures
38K2 Group
Fig. 3.1.3 SB output switching characteristics measurement circuit (2) for D0+, D1+/D2+ (full-speed),
D1-/D2- (low-speed) ...... 13
Fig. 3.1.4 Timing chart (1) ............................................................................................................. 14
Fig. 3.1.5 Timing chart (2) ............................................................................................................. 15
Fig. 3.1.6 Timing chart (3) ............................................................................................................. 16
Fig. 3.1.7 Timing chart (4) ............................................................................................................. 17
Fig. 3.1.8 Timing chart (5) ............................................................................................................. 18
Fig. 3.1.9 Timing chart (6) ............................................................................................................. 19
Fig. 3.2.1 Sequence of changing relevant register .................................................................... 22
Fig. 3.2.2 Sequence of check of interrupt request bit ............................................................... 23
Fig. 3.2.3 Sequence of setting serial I/O control register again .............................................. 25
Fig. 3.2.4 Initialization of processor status register ................................................................... 29
Fig. 3.2.5 Sequence of PLP instruction execution ..................................................................... 29
Fig. 3.2.6 Stack memory contents after PHP instruction execution ........................................ 29
Fig. 3.2.7 Status flag at decimal calculations ............................................................................. 30
Fig. 3.3.1 Selection of packages .................................................................................................. 32
_____________
Fig. 3.3.2 Wiring for the RESET pin ............................................................................................ 32
Fig. 3.3.3 Wiring for clock I/O pins .............................................................................................. 33
Fig. 3.3.4 Wiring for CNVSS pin..................................................................................................... 33
Fig. 3.3.5 Wiring for the VPP pin of the flash memory version................................................. 34
Fig. 3.3.6 Bypass capacitor across the VSS line and the VCC line ........................................... 34
Fig. 3.3.7 Analog signal line and a resistor and a capacitor ................................................... 35
Fig. 3.3.8 Wiring for a large current signal line ......................................................................... 36
___________
Fig. 3.3.9 Wiring of RESET pin .................................................................................................... 36
Fig. 3.3.10 VSS pattern on the underside of an oscillator ......................................................... 37
Fig. 3.3.11 Setup for I/O ports ...................................................................................................... 37
Fig. 3.3.12 Watchdog timer by software ...................................................................................... 38
Fig. 3.4.1 Structure of Port Pi ....................................................................................................... 39
Fig. 3.4.2 Structure of Port Pi direction register ........................................................................ 39
Fig. 3.4.3 Structure of USB control register................................................................................ 40
Fig. 3.4.4 Structure of USB function/HUB enable register........................................................ 40
Fig. 3.4.5 Structure of USB function address register............................................................... 40
Fig. 3.4.6 Structure of USB HUB address register .................................................................... 41
Fig. 3.4.7 Structure of Frame number register Low................................................................... 41
Fig. 3.4.8 Structure of Frame number register High.................................................................. 41
Fig. 3.4.9 Structure of USB interrupt source enable register ................................................... 41
Fig. 3.4.10 Structure of USB interrupt source register .............................................................. 42
Fig. 3.4.11 Structure of Endpoint index register......................................................................... 42
Fig. 3.4.12 Structure of EP00 stage register .............................................................................. 43
Fig. 3.4.13 Structure of EP01 set register .................................................................................. 43
Fig. 3.4.14 Structure of EP02 set register .................................................................................. 44
Fig. 3.4.15 Structure of EP03 set register .................................................................................. 44
Fig. 3.4.16 Structure of EP10 stage register .............................................................................. 45
Fig. 3.4.17 Structure of EP11 set register .................................................................................. 45
Fig. 3.4.18 Structure of EP00 control register 1 ........................................................................ 45
Fig. 3.4.19 Structure of EP01 control register 1 ........................................................................ 46
Fig. 3.4.20 Structure of EP02 control register 1 ........................................................................ 46
Fig. 3.4.21 Structure of EP03 control register 1 ........................................................................ 46
Fig. 3.4.22 Structure of EP10 control register 1 ........................................................................ 47
Fig. 3.4.23 Structure of EP11 control register 1 ........................................................................ 47
Fig. 3.4.24 Structure of EP00 control register 2 ........................................................................ 47
Fig. 3.4.25 Structure of EP01 control register 2 ........................................................................ 48
Fig. 3.4.26 Structure of EP02 control register 2 ........................................................................ 48
Rev.2.00 Oct 15, 2006 page 10 of 14
REJ09B0338-0200
List of figures
38K2 Group
Fig. 3.4.27 Structure of EP03 control register 2 ........................................................................ 48
Fig. 3.4.28 Structure of EP10 control register 2 ........................................................................ 49
Fig. 3.4.29 Structure of EP11 control register 2 ........................................................................ 49
Fig. 3.4.30 Structure of EP00 control register 3 ........................................................................ 49
Fig. 3.4.31 Structure of EP01 control register 3 ........................................................................ 50
Fig. 3.4.32 Structure of EP02 control register 3 ........................................................................ 50
Fig. 3.4.33 Structure of EP03 control register 3 ........................................................................ 50
Fig. 3.4.34 Structure of EP10 control register 3 ........................................................................ 51
Fig. 3.4.35 Structure of EP00 interrupt source register ............................................................ 51
Fig. 3.4.36 Structure of EP01 interrupt source register ............................................................ 52
Fig. 3.4.37 Structure of EP02 interrupt source register ............................................................ 52
Fig. 3.4.38 Structure of EP03 interrupt source register ............................................................ 53
Fig. 3.4.39 Structure of EP10 interrupt source register ............................................................ 54
Fig. 3.4.40 Structure of EP11 interrupt source register ............................................................ 54
Fig. 3.4.41 Structure of EP00 byte number register .................................................................. 55
Fig. 3.4.42 Structure of EP01 byte number register 0 .............................................................. 55
Fig. 3.4.43 Structure of EP02 byte number register 0 .............................................................. 55
Fig. 3.4.44 Structure of EP03 byte number register 0 .............................................................. 56
Fig. 3.4.45 Structure of EP10 byte number register .................................................................. 56
Fig. 3.4.46 Structure of EP11 byte number register 0 .............................................................. 56
Fig. 3.4.47 Structure of EP01 byte number register 1 .............................................................. 57
Fig. 3.4.48 Structure of EP02 byte number register 1 .............................................................. 57
Fig. 3.4.49 Structure of EP03 byte number register 1 .............................................................. 57
Fig. 3.4.50 Structure of Prescaler12, Prescaler X ..................................................................... 58
Fig. 3.4.51 Structure of Timer 1 ................................................................................................... 58
Fig. 3.4.52 Structure of Timer 2, Timer X ................................................................................... 59
Fig. 3.4.53 Structure of Timer X mode register ......................................................................... 59
Fig. 3.4.54 Structure of Transmit/Receive buffer register ......................................................... 60
Fig. 3.4.55 Structure of Serial I/O status register ...................................................................... 60
Fig. 3.4.56 Structure of HUB interrupt source enable register................................................. 61
Fig. 3.4.57 Structure of HUB interrupt source register.............................................................. 61
Fig. 3.4.58 Structure of HUB downstream port index register ................................................. 61
Fig. 3.4.59 Structure of DP1 interrupt source register .............................................................. 62
Fig. 3.4.60 Structure of DP2 interrupt source register .............................................................. 63
Fig. 3.4.61 Structure of DP1 control register .............................................................................. 64
Fig. 3.4.62 Structure of DP2 control register .............................................................................. 64
Fig. 3.4.63 Structure of DP1 status register ............................................................................... 65
Fig. 3.4.64 Structure of DP2 status register ............................................................................... 65
Fig. 3.4.65 Structure of EXB interrupt source enable register ................................................. 65
Fig. 3.4.66 Structure of EXB interrupt source register .............................................................. 66
Fig. 3.4.67 Structure of EXB index register ................................................................................ 66
Fig. 3.4.68 Structure of Register window 1................................................................................. 67
Fig. 3.4.69 Index00[low]; Structure of External I/O configuration register ............................ 67
Fig. 3.4.70 Index01[low]; Structure of Transmit/Receive buffer register ................................. 68
Fig. 3.4.71 Index02[low]; Structure of Memory channel operation mode register ................. 68
Fig. 3.4.72 Index03[low]; Structure of Memory address counter.............................................. 68
Fig. 3.4.73 Index04[low]; Structure of End address register .................................................... 69
Fig. 3.4.74 Structure of Register window 2................................................................................. 69
Fig. 3.4.75 Index00[high]; Structure of External I/O configuration register ........................... 69
Fig. 3.4.76 Index03[high]; Structure of Memory address counter ............................................ 70
Fig. 3.4.77 Index04[high]; Structure of End address register ................................................... 70
Fig. 3.4.78 Structure of AD control register ................................................................................ 70
Fig. 3.4.79 Structure of AD conversion register 1 ..................................................................... 71
Rev.2.00 Oct 15, 2006 page 11 of 14
REJ09B0338-0200
List of figures
38K2 Group
Fig. 3.4.80 Structure of AD conversion register 2 ..................................................................... 71
Fig. 3.4.81 Structure of Watchdog timer control register .......................................................... 72
Fig. 3.4.82 Structure of CPU mode register ............................................................................... 72
Fig. 3.4.83 Structure of Interrupt request register 1 .................................................................. 73
Fig. 3.4.84 Structure of Interrupt request register 2 .................................................................. 73
Fig. 3.4.85 Structure of Interrupt control register 1 ................................................................... 74
Fig. 3.4.86 Structure of Interrupt control register 2 ................................................................... 74
Fig. 3.4.87 Structure of Serial I/O control register..................................................................... 75
Fig. 3.4.88 Structure of UART control register ........................................................................... 75
Fig. 3.4.89 Structure of Baud rate generator.............................................................................. 76
Fig. 3.4.90 Structure of EP01 MAX. packet size register ......................................................... 76
Fig. 3.4.91 Structure of EP02 MAX. packet size register ......................................................... 76
Fig. 3.4.92 Structure of EP03 MAX. packet size register ......................................................... 77
Fig. 3.4.93 Structure of EP00 buffer area set register .............................................................. 77
Fig. 3.4.94 Structure of EP01 buffer area set register .............................................................. 77
Fig. 3.4.95 Structure of EP02 buffer area set register .............................................................. 78
Fig. 3.4.96 Structure of EP03 buffer area set register .............................................................. 78
Fig. 3.4.97 Structure of EP10 buffer area set register .............................................................. 78
Fig. 3.4.98 Structure of EP11 buffer area set register .............................................................. 79
Fig. 3.4.99 Structure of Port P0 pull-up control register ........................................................... 79
Fig. 3.4.100 Structure of Port P5 pull-up control register ......................................................... 80
Fig. 3.4.101 Structure of Interrupt edge selection register ....................................................... 80
Fig. 3.4.102 Structure of PLL control register ............................................................................ 81
Fig. 3.4.103 Structure of Downstream port control register...................................................... 81
Fig. 3.4.104 Structure of MISRG .................................................................................................. 82
Fig. 3.4.105 Structure of Flash memory control register........................................................... 82
Rev.2.00 Oct 15, 2006 page 12 of 14
REJ09B0338-0200
List of tables
38K2 Group
List of tables
CHAPTER 1 HARDWARE
Table 1 Pin description ................................................................................................................... 4
Table 2 List of 38K2 group products (L version) ....................................................................... 6
Table 3 Push and pop instructions of accumulator or processor status register .................. 8
Table 4 Set and clear instructions of each bit of processor status register .......................... 9
Table 5 I/O ports functions .......................................................................................................... 13
Table 6 Interrupt vector addresses and priority ........................................................................ 17
Table 7 USB interrupt sources .................................................................................................... 30
Table 8 HUBinterrupt sources ..................................................................................................... 61
Table 9 Summary of 38K2 group’s flash memory version .................................................... 100
Table 10 List of software commands (CPU rewrite mode) ................................................... 105
Table 11 Definition of each bit in status register ................................................................... 107
Table 12 Description of pin function (Standard Serial I/O Mode) ........................................ 113
Table 13 Software commands (Standard serial I/O mode) ................................................... 115
Table 14 Status register (SRD) ................................................................................................. 122
Table 15 Status register 1 (SRD1) ........................................................................................... 123
Table 16 Relative formula for a reference voltage VREF of A/D converter and Vref ...... 129
Table 17 Change of AD conversion register during A/D conversion ................................... 129
CHAPTER 2 APPLICATION
Table 2.1.1 Handling of unused pins ............................................................................................. 5
Table 2.2.1 Interrupt sources, vector addresses and priority of 38K2 group......................... 11
Table 2.2.2 List of interrupt bits according to interrupt source ................................................ 16
Table 2.3.1 CNTR active edge selection bit function ............................................................... 25
0
Table 2.4.1 Setting examples of Baud rate generator values and transfer bit rate values . 61
Table 2.11.1 PLL operation mode selection bits setting example ........................................... 86
Table 2.11.2 USB clock division ratio selection bits setting example ..................................... 87
Table 2.12.1 Example of internal clock f(f) generation using main clock f(XIN)..................... 92
Table 2.12.2 Example of internal clock f(f) generation using fSYN ........................................ 93
Table 2.13.1 State in stop mode .................................................................................................. 96
Table 2.13.2 State in wait mode................................................................................................. 100
Table 2.14.1 Setting of programmers when parallel programming ........................................ 105
Table 2.14.2 Connection example to flash programmer when serial programming (4 wires)..
................................................................................................................................ 105
Table 2.14.3 Setting condition in serial I/O mode .................................................................. 107
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings .......................................................................................... 2
Table 3.1.2 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20
to 85°C, unless otherwise noted) ............................................................................ 3
Table 3.1.3 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20
to 85°C, unless otherwise noted) ............................................................................ 4
Table 3.1.4 Electrical characteristics (1) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C,
unless otherwise noted) ............................................................................................ 5
Table 3.1.5 Electrical characteristics (2) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C,
unless otherwise noted) ............................................................................................ 6
Rev.2.00 Oct 15, 2006 page 13 of 14
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List of tables
38K2 Group
Table 3.1.6 A/D Converter characteristics (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85°C,
unless otherwise noted) ............................................................................................ 7
Table 3.1.7 Timing requirements (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless
otherwise noted)......................................................................................................... 8
Table 3.1.8 Timing requirements (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless
otherwise noted)......................................................................................................... 8
Table 3.1.9 Timing requirements of external bus interface (EXB) (1) (VCC = 4.00 to 5.25 V, VSS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted) ............................................ 9
Table 3.1.10 Timing requirements of external bus interface (EXB) (2) (VCC = 3.00 to 4.00 V, VSS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted) .......................................... 10
Table 3.1.11 Switching characteristics (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C,
unless otherwise noted) .......................................................................................... 11
Table 3.1.12 Switching characteristics (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C,
unless otherwise noted) .......................................................................................... 11
Table 3.1.13 Switching characteristics of external bus interface (EXB) (1) (VCC = 4.00 to 5.25
V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) .............................. 12
Table 3.1.14 Switching characteristics of external bus interface (EXB) (2) (VCC = 3.00 to 4.00
V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) .............................. 12
Table 3.1.15 Switching characteristics (USB ports) (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = –20
to 85 °C, unless otherwise noted) ........................................................................ 13
Rev.2.00 Oct 15, 2006 page 14 of 14
REJ09B0338-0200
THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USAGE
DATA REQUIRED FOR MASK ORDERS
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
38K2 Group
DESCRIPTION/FEATURES/PIN CONFIGURATION
Timers ............................................................................. 8-bit ꢀ 3
Watchdog timer ............................................................. 16-bit ꢀ 1
Serial Interface
DESCRIPTION
•
•
•
The 38K2 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
Serial I/O ...................... 8-bit ꢀ 1 (UART or Clock-synchronized)
A/D converter ................................................ 10-bit ꢀ 8 channels
(8-bit reading available)
The 38K2 group has the USB function, an 8-bit bus interface, a
Serial Interface, three 8-bit timers, and an 8-channel 10-bit A/D
converter, which are available for the PC peripheral I/O device.
The various microcomputers in the 38K2 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
•
LED direct drive port ................................................................... 4
Clock generating circuit
•
•
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage (L version)
•
•
System clock/Internal clock division mode
FEATURES
At 12 MHz/2-divide mode(φ = 6 MHz) ................... 4.00 to 5.25 V
At 8 MHz/Through mode (φ = 8 MHz) ................... 4.00 to 5.25 V
At 6 MHz/Through mode (φ = 6 MHz) ................... 3.00 to 5.25 V
Basic machine-language instructions ....................................... 71
•
•
The minimum instruction execution time .......................... 0.25 µs
ꢀ
(at 8 MHz system clock )
ꢀ
System clock : Reference frequency to internal circuit except
Power dissipation
USB function
At 5 V power source voltage.................................. 125 mW (typ.)
(at 8 MHz system clock, in through mode)
At 3.3 V power source voltage ................................ 30 mW (typ.)
(at 6 MHz system clock, in through mode)
Operating temperature range .................................... –20 to 85°C
Packages
Memory size
•
ROM ................................................................ 16 K to 32 K bytes
RAM ............................................................... 1024 to 2048 bytes
Programmable input/output ports ............................................. 44
•
•
•
Software pull-up resistors
•
Interrupts .................................................. 16 sources, 16 vectors
•
FP ............................ PLQP0064GA-A (64-pin 14 ꢀ 14 mm LQFP)
HP ............................ PLQP0064KB-A (64-pin 10 ꢀ 10 mm LQFP)
USB function (Full-Speed USB2.0 specification) ...... 4 endpoints
•
USB HUB function (Full-Speed USB2.0 specification) .... 2 down ports
•
External bus interface ....................................... 8-bit ꢀ 1 channel
•
PIN CONFIGURATION (TOP VIEW)
P0
6
7
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
P2
5
4
P0
P2
P4
0
/E
/E
P4
P4
X
DREQ/R
X
D
D2+
P4
1
X
DACK/T
XD
D2-
29
28
27
D1+
2
/E
X
TC/SCLK
D1-
3
/E
XA1/SRDY
26
25
24
23
22
21
20
19
18
17
D0-
P30
P31
P32
M38K27M4L-XXXFP/HP
M38K29F8LFP/HP
D0+
TrON
USBVREF
DVCC
PVCC
PVSS
P3
P3
3
/E
/E
/E
/E
/E
XINT
4
X
CS
P3
5
X
WR
P3
6
X
RD
A0
P3
7
X
P6
P6
P6
3
2
1
(LED
(LED
(LED
3
2
1
)
)
)
P1
P1
0
/DQ
0
/AN
/AN
0
1
/DQ
1
1
Package type : PLQP0064GA-A (64P6U-A)/PLQP0064KB-A (64P6Q-A)
Fig. 1 Pin configuration of 38K2 group
Rev.2.00 Oct 15, 2006 page 2 of 130
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HARDWARE
38K2 Group
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
Rev.2.00 Oct 15, 2006 page 3 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
PIN DESCRIPTION
PIN DESCRIPTION
Table 1. Pin description
Pin
Function
Name
Function except a port function
VCC, VSS
VCCE
• Apply voltage of 3.0 V – 5.25 V (L version) to VCC, and 0 V to VSS.
Power source
• Power source pin for ports P1, P3, P4 and analog circuit. Connect this pin to VCC.
Analog power
source
CNVSS
• This pin controls the operation mode of the chip. Connect this pin to VSS. In the flash memory
CNVSS
mode, this pin becoems VPP power source input pin.
CNVSS2
VREF
• This pin controls the operation mode of the chip. Connect this pin to VSS.
• Reference voltage input pin for A/D converter.
CNVSS2
Analog reference
voltage input
DVCC
PVCC, PVSS
• Power source pin for analog circuit.
• Connect the DVCC and PVCC pins to VCC, and the PVSS pin to VSS.
Analog power
source
RESET
XIN
• Reset input pin for active “L”
Reset input
Clock input
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
USBVREF
• Power source pin for USB port circuit.
USB reference
power source
In Vcc = 4.00 to 5.25 V use the built-in USB reference voltage circuit. In Vcc = 3.60 to 4.00 V apply
3.3 V power supply from the external because use of the built-in USB reference voltage circuit is
prohibited in this voltage range. In Vcc = 3.00 to 3.60 V connect this pin to VCC because use of the
built-in USB reference voltage circuit is prohibited in this voltage range.
TrON
• Output pin to pull-up D0+ by 1.5 kΩ external resistor.
USB reference
voltage output
D0+, D0-
• USB upstream I/O port
• USB input level
USB upstream
I/O
• USB output level output structure
D1+, D1-,
D2+, D2-
• USB downstream I/O port
• USB input level
USB down-
stream I/O
• USB output level output structure
• 8-bit I/O port
• Key input pins (key-on wake up interrupt)
P00–P07
I/O port P0
I/O port P1
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Pull-up control is enabled.
• 8-bit I/O port
• A/D converter input pins
• External bus interface function pins
P1
P1
0
/DQ
/DQ
0
/AN
/AN
0
7
–
7
7
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
P24–P27
P30–P32
• 4-bit I/O port
I/O port P2
I/O port P3
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit I/O port
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• External bus interface function pins
P33/ExINT
P34/ExCS
P35/ExWR
P36/ExRD
P37/ExA0
• CMOS 3-state output structure
• 4-bit I/O port
• Serial I/O function pins
• External bus interface function pins
P4
P4
P4
0
1
/ExDREQ/RxD
/ExDACK/TxD
/ExTC/SCLK
I/O port P4
I/O port P5
I/O port P6
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
2
P4
3/ExA1/SRDY
• CMOS 3-state output structure
• 8-bit I/O port
• Interrupt input pin
• Timer X funciton pin
• Interrupt input pin
P50/INT0
P51/CNTR0
P52/INT1
P53–P57
P60–P63
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• 4-bit I/O port; • I/O direction register allows each pin to be individually programmed as either input
or output.; • CMOS compatible input level• CMOS 3-state output structure;
• Output large current for LED drive is enabled.
Rev.2.00 Oct 15, 2006 page 4 of 130
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HARDWARE
38K2 Group
PART NUMBERING
PART NUMBERING
M38K2 7 M 4 L - XXX FP
Product
Package type
FP : PLQP0064GA-A package
HP : PLQP0064KB-A package
ROM number
Omitted in the flash memory version.
Omitted in the flash memory version.
L : L version
ROM/PROM size
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used as a
user’s ROM area.
However, they can be programmed or erased
in the flash memory version, so that users can
use them.
Memory type
M : Mask ROM version
F : Flash memory version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 3 Part numbering
Rev.2.00 Oct 15, 2006 page 5 of 130
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HARDWARE
38K2 Group
GROUP EXPANSION
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 38K2 group as follows.
PLQP0064GA-A ...................... 0.8 mm-pitch plastic molded LQFP
PLQP0064KB-A....................... 0.5 mm-pitch plastic molded LQFP
100D0M ...........................0.65 mm-pitch metal seal PIGGY BACK
Memory Type
Support for mask ROM and flash memory versions.
Memory Size
Flash memory size .......................................................... 32 Kbytes
Mask ROM size ............................................................... 16 Kbytes
RAM size .......................................................... 1024 to 2048 bytes
Memory Expansion Plan
ROM size
(bytes)
: Mass Production
60K
M38K29F8L
32K
16K
8K
M38K27M4L
256
512
1,024
2,048
RAM size (bytes)
Fig. 4 Memory expansion plan
Currently products are listed below.
Table 2. List of 38K2 group products (L version)
As of October 2006
Remarks
ROM size (bytes)
ROM size for User in (
Product
RAM size (bytes)
1024
Package
)
M38K27M4L-XXXFP
M38K27M4L-XXXHP
M38K29F8LFP
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
100D0M
16384
(16254)
Mask ROM version
32768
2048
2048
Flash memory version
(32638)
M38K29F8LHP
M38K29RFS
—
Rev.2.00 Oct 15, 2006 page 6 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 38K2 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The CPU has the 6 registers. The register structure is shown in
Figure 5.
Figure 6 shows the store and the return movement into the stack.
If there are registers other than those described in Figure 5, the
users need to store them with the program.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b0
b0
b0
b0
b7
X
Index register X
Index register Y
b7
Y
b7
S
Stack pointer
b15
b7
b7
PCH
PC
L
Program counter
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PC
(S) (S) – 1
M (S) (PC
H
)
Push return address
on stack
M (S) (PC
(S) (S) – 1
M (S) (PC
H)
L
)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
Push contents of processor
status register on stack
L
)
(S) (S)– 1
Subroutine
Interrupt
Service Routine
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PC
(S) (S) + 1
(PC M (S)
L)
M (S)
(PS)
(S) (S) + 1
(PC M (S)
(S) (S) + 1
(PC M (S)
M (S)
H)
L)
POP return
address
from stack
H)
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
Rev.2.00 Oct 15, 2006 page 8 of 130
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38K2 Group
FUNCTIONAL DESCRIPTION
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can execute decimal arithmetic.
Table 4 Set and clear instructions of each bit of processor status register
N flag
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
–
–
Set instruction
CLI
CLV
Clear instruction
Rev.2.00 Oct 15, 2006 page 9 of 130
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38K2 Group
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16
0 1
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Not used (returns “0” when read)
(Do not write “1” to this bit)
System clock selection bit
0 : Main clock (XIN
)
1 : fSYN
System clock division ratio selection bits
b7 b6
0
0
1
0 : φ = f(system clock)/8 (8-divide mode)
1 : φ = f(system clock)/4 (4-divide mode)
0 : φ = f(system clock)/2 (2-divide mode)
1 : φ = f(system clock) (Through mode)
1
Fig. 7 Structure of CPU mode register
Rev.2.00 Oct 15, 2006 page 10 of 130
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38K2 Group
FUNCTIONAL DESCRIPTION
MEMORY
Interrupt Vector Area
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs. In
the flash memory version, program and erase can be performed in
the reserved area.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
RAM area
000016
RAM size
(bytes)
Address
XXXX16
SFR area
Zero page
004016
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
192
256
010016
RAM
384
512
640
768
XXXX16
896
1024
1536
2048
Not used
0FE016
SFR area
0FFF16
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
YYYY16
Reserved ROM area
(128 bytes)
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
ZZZZ16
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
FFFE16
Reserved ROM area
FFFF16
Fig. 8 Memory map diagram
Rev.2.00 Oct 15, 2006 page 11 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
Prescaler 12 (PRE12)
Timer 1 (T1)
Port P0 (P0)
Port P0 direction register (P0D)
Timer 2 (T2)
Port P1 (P1)
Timer X mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Transmit/Receive buffer register (TB/RB)
Serial I/O status register (SIOSTS)
Port P3 direction register (P3D)
Port P4 (P4)
HUB interrupt source enable register (HUBICON)
HUB interrupt source register (HUBIREQ)
HUB down stream port index register (HUBINDEX)
Port P4 direction register (P4D)
Port P5 (P5)
002B16
002C16
002D16
Port P5 direction register (P5D)
Port P6 (P6)
HUB port field register 1 (DPXREG1)
HUB port field register 2 (DPXREG2)
HUB port field register 3 (DPXREG3)
Reserved (Note)
Port P6 direction register (P6D)
Reserved (Note)
002E16
002F16
003016
003116
Reserved (Note)
Reserved (Note)
EXB interrupt source enable register (EXBICON)
USB control register (USBCON)
USB function/Hub enable register (USBAE)
EXB interrupt source register (EXBIREQ)
Reserved (Note)
003216
003316
003416
USB function address register (USBA0)
EXB index register (EXBINDEX)
Register window 1 (EXBREG1)
USB HUB address register (USBA1)
Frame number register Low (FNUML)
Frame number register High (FNUMH)
USB interrupt source enable register (USBICON)
003516
003616
003716
Register window 2 (EXBREG2)
AD control register (ADCON)
AD conversion register 1 (AD1)
AD conversion register 2 (AD2)
USB interrupt source register (USBIREQ)
Endpoint index register (USBINDEX)
Endpoint field register 1 (EPXXREG1)
Endpoint field register 2 (EPXXREG2)
Endpoint field register 3 (EPXXREG3)
Endpoint field register 4 (EPXXREG4)
Endpoint field register 5 (EPXXREG5)
Endpoint field register 6 (EPXXREG6)
Endpoint field register 7 (EPXXREG7)
003816
003916 Watchdog timer control register (WDTCON)
003A16
003B16
Reserved (Note)
CPU mode register (CPUM)
003C16 Interrupt request register 1(IREQ1)
003D16 Interrupt request register 2(IREQ2)
003E16
003F16
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
Serial I/O control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
Reserved (Note)
Port P0 pull-up control register (PULL0)
Reserved (Note)
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
Port P5 pull-up control register (PULL5)
Interrupt edge selection register (INTEDGE)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
0FE616 Reserved (Note)
Reserved (Note)
0FE716
Reserved (Note)
Reserved (Note)
0FE816
0FE916
0FEA16
Reserved (Note)
PLL control register (PLLCON)
Downstream port control register (DPCTL)
Reserved (Note)
Reserved (Note)
0FFA16 Reserved (Note)
Reserved (Note)
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FFB16 MISRG
Endpoint field register 8 (EPXXREG8)
Endpoint field register 9 (EPXXREG9)
Reserved (Note)
0FFC16
Reserved (Note)
0FFD16
0FFE16
Flash memory control register (FMCR)
Reserved (Note)
Reserved (Note)
Reserved (Note)
0FFF16
Note: Do not write any data to these addresses, because these areas are reserved.
Fig. 9 Memory map of special function register (SFR)
Rev.2.00 Oct 15, 2006 page 12 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Table 5 I/O ports functions
Related SFRs
Pin
Name
Port P0
Input/Output
I/O Format
Non-Port Function
Key-on wake up
Diagram No.
Port P0 pull-up control
register
P00–P07
Input/output,
individual bits
CMOS compatible
input level
(1)
CMOS 3-state output
AD control register
EXB control register
P10–P17
P24–P27
Port P1
CMOS compatible
input level
CMOS 3-state output
(Power source is
VCCE)
A/D conversion input
External bus interface
funciton I/O
(2)
(3)
Port P2
Port P3
CMOS compatible
input level
CMOS 3-state output
P30–P32
CMOS compatible
input level
CMOS 3-state output
(Power source is
VccE)
(4)
(5)
EXB control register
EXB control register
P33/ExINT
External bus interface
funciton output
P34/ExCS
P35/ExWR
P36/ExRD
P37/ExA0
External bus interface
funciton input
(6)
Serial I/O control
register
EXB control register
P40/RxD/
ExDREQ
Port P4
Serial I/O input
External bus interface
funciton output
(7)
(8)
Serial I/O control
register
EXB control register
P41/TxD/
ExDACK
Serial I/O output
External bus interface
funciton input
Serial I/O control
register
EXB control register
P42/SCLK/
ExTC
Serial I/O I/O
External bus interface
funciton input
(9)
Serial I/O control
register
EXB control register
P43/SRDY/
ExA1
Serial I/O output
External bus interface
funciton input
(10)
(11)
Port P5 pull-up control
register
Interrupt edge selection
register
P50/INT0
P52/INT1
Port P5
Port P6
CMOS compatible
input level
CMOS 3-state output
External interrupt input
Timer X mode register
P51/CNTR0
P53–P57
Timer X function I/O
(12)
(13)
(14)
P60–P63
Note: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate poten-
tial, a current will flow from VCC to VSS through the input-stage gate.
Rev.2.00 Oct 15, 2006 page 13 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(4) Ports P30–P32
(1) Port P0
VCCE
Pull-up control bit
Direction register
Port latch
Direction register
Data bus
Data bus
Port latch
Key-on wake-up input
(5) Port P3
3
(2) Port P1
V
CCE
EXOE
V
CCE
External bus interface enable bit
Direction register
External bus interface enable bit
Direction register
Port latch
Data bus
Port latch
Data bus
E
XINT output
EXB data output
EXB data input
Output buffer
Input buffer
(6) Ports P3
4
, P3
5
, P3
6, P3
7
V
CCE
External bus interface enable bit
A/D conversion input
Direction register
Analog input pin selection bit
Data bus
Port latch
(3) Port P2
Direction register
Port latch
EX
EX
EX
EX
CS(P3
WR(P3
RD(P3
A0(P3
4)
5
)
External bus interface enable bit
6
)
7)
Data bus
Fig. 10 Port block diagram (1)
Rev.2.00 Oct 15, 2006 page 14 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(11) Ports P50, P5
2
(7) Port P4
0
Pull-up control bit
Serial I/O enable bit
Receive enable bit
V
CCE
Direction register
Port latch
External bus interface enable bit
Direction register
Data bus
Data bus
Port latch
INT0 (P50), INT1 (P52) interrupt input
E
X
Dreq output
Serial I/O input
(8) Port P4
1
(12) Port P5
1
Serial I/O enable bit
Receive enable bit
V
CCE
Direction register
Port latch
External bus interface enable bit
Direction register
Data bus
Data bus
Port latch
Pulse output mode
Timer output
Serial I/O output
Dack
CNTR0 interrupt input
E
X
External bus interface enable bit
(13) Ports P53–P57
(9) Port P4
2
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O synchronous clock selection bit
Serial I/O enable bit
Direction register
Port latch
V
CCE
External bus interface enable bit
Direction register
Data bus
Data bus
Port latch
Serial I/O clock output
(14) Port P6
Serial I/O external clock input
Direction register
Port latch
Serial I/O synchronous clock selection bit
External bus interface enable bit
EXTC
Data bus
(10) Port P4
3
Serial I/O mode selection bit
Serial I/O enable bit
S
RDY output enable bit
V
CCE
External bus interface enable bit
Direction register
Data bus
Port latch
Serial I/O output
EXA1
External bus interface enable bit
Fig. 11 Port block diagram (2)
Rev.2.00 Oct 15, 2006 page 15 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b7
b0
Port P0 pull-up control register
(PULL0 : address 0FF016
)
P0
P0
P0
P0
P0
P0
P0
P0
0 pull-up control bit
0 : No pull-up
1 : Pull-up
1
pull-up control bit
0 : No pull-up
1 : Pull-up
2
pull-up control bit
0 : No pull-up
1 : Pull-up
3
pull-up control bit
0 : No pull-up
1 : Pull-up
4
pull-up control bit
0 : No pull-up
1 : Pull-up
5
pull-up control bit
0 : No pull-up
1 : Pull-up
6
pull-up control bit
0 : No pull-up
1 : Pull-up
7
pull-up control bit
0 : No pull-up
1 : Pull-up
b7
b0
Port P5 pull-up control register
(PULL5 : address 0FF216
)
P5 pull-up control bit
0
0 : No pull-up
1 : Pull-up
Nothing is arranged for this bit. This is a write disabled bit.
When this bit is read out, the contents are “0”.
P52 pull-up control bit
0 : No pull-up
1 : Pull-up
Nothing is arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0”.
Fig. 12 Structure of port I/O-related registers
Rev.2.00 Oct 15, 2006 page 16 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
ꢀNotes on interrupts
INTERRUPTS
When setting the followings, the interrupt request bit may be set to
“1”.
Interrupts occur by sixteen sources: four external, eleven internal,
and one software.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address
0FF316), Timer X mode register (address
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
002316
)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
ꢀSet the corresponding interrupt enable bit to “0” (disabled).
ꢀSet the interrupt edge select bit (active edge switch bit).
ꢀSet the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
ꢀSet the corresponding interrupt enable bit to “1” (enabled).
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Table 6 Interrupt vector addresses and priority
Interrupt Request
Vector Addresses (Note 1)
Interrupt Source
Priority
High
Low
Generating Conditions
Reset (Note 2)
USB bus reset
USB SOF
1
2
3
4
FFFD16
FFFB16
FFF916
FFF716
FFFC16
FFFA16
FFF816
FFF616
At reset
At detection of USB bus reset signal (2.5 µs interval SE0)
At detection of USB SOF signal
USB device
At detection of resume signal (K state or SE0) or suspend signal (3
ms interval bus idle), or at completion of transaction
External bus
5
FFF416
At completion of reception or transmission or at completion of DMA
transmission
FFF516
INT0
6
7
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
At detection of either rising or falling edge of INT0 input
At timer X underflow
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
Timer X
Timer 1
Timer 2
INT1
8
At timer 1 underflow
9
At timer 2 underflow
10
11
12
At detection of either rising or falling edge of INT1 input
At detection of USB HUB downport’s state switch
At completion of serial I/O data reception
USB HUB
Serial I/O
reception
Serial I/O
transmission
13
FFE416
At completion of serial I/O data transmission
FFE516
CNTR0
14
15
16
17
FFE216
FFE016
FFDE16
FFDC16
At detection of either rising or falling edge of CNTR0 input
At falling of conjunction of input level for port P0 (at input mode)
At completion of A/D conversion
FFE316
FFE116
FFDF16
FFDD16
Key-on wake up
A/D conversion
BRK instruction
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.2.00 Oct 15, 2006 page 17 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 0FF316
)
INT
Not used (return “0” when read)
INT interrupt edge selection bit
0 interrupt edge selection bit
1
Not used (return “0” when read)
0 : Falling edge active
1 : Rising edge active
b7
b0
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
)
(IREQ1 : address 003C16
)
USB bus reset interrupt request bit
USB SOF interrupt request bit
USB device interrupt request bit
EXB interrupt request bit
INT1 interrupt request bit
USB HUB interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
INT0 interrupt request bit
CNTR0 interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Key-on wake-up interrupt request bit
A/D conversion interrupt request bit
Nothing is arranged for this bit. This is a
write disabled bit. When this bit is read
out, the contents are “0”.
ꢀ “0” can be set by software, but “1”
cannot be set.
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
INT interrupt enable bit
USB HUB interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
1
USB bus reset interrupt enable bit
USB SOF interrupt enable bit
USB device interrupt enable bit
EXB interrupt enable bit
CNTR0 interrupt enable bit
INT0 interrupt enable bit
Key-on wake-up interrupt enable bit
A/D conversion interrupt enable bit
Fix this bit to “0”.
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
ꢀ “0” can be set by software, but “1”
cannot be set.
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
Rev.2.00 Oct 15, 2006 page 18 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
Key Input Interrupt (Key-on Wake Up)
“1” to “0”. An example of using a key input interrupt is shown in
Figure 15, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P00–P03.
A Key-on wake up interrupt request is generated by applying a
falling edge to any pin of port P0 that have been set to input mode.
In other words, it is generated when AND of input level goes from
Port PXx
“L” level output
PULL 0 register
Port P0
7
Key input interrupt request
Bit 7 = “0”
direction register = “1”
ꢀ
ꢀꢀꢀ
Port P0
latch
7
6
5
4
P0
7
output
output
PULL 0 register
Bit 6 = “0”
Port P0
direction register = “1”
6
ꢀ
ꢀꢀꢀ
Port P0
latch
P0
6
PULL 0 register
Port P0
direction register = “1”
5
Bit 5 = “0”
ꢀꢀꢀ
ꢀ
Port P0
latch
P0
5
output
output
PULL 0 register
Bit 4 = “0”
Port P0
direction register = “1”
4
ꢀ
ꢀꢀꢀ
Port P0
latch
P04
PULL 0 register
Bit 3 = “1”
ꢀꢀꢀ
Port P0
direction register = “0”
3
Port P0
Input reading circuit
ꢀ
Port P0
latch
3
P03
input
PULL 0 register
Bit 2 = “1”
Port P0
direction register = “0”
2
ꢀ
ꢀꢀꢀ
Port P0
latch
2
P0
P0
2
input
input
PULL 0 register
Bit 1 = “1”
Port P0
direction register = “0”
1
ꢀ
ꢀꢀꢀ
Port P0
latch
1
1
PULL 0 register
Port P0
0
Bit 0 = “1”
direction register = “0”
ꢀ
ꢀꢀꢀ
Port P0
latch
0
P00
input
ꢀ
P-channel transistor for pull-up
ꢀꢀCMOS output buffer
Fig. 15 Connection example when using key input interrupt and port P0 block diagram
Rev.2.00 Oct 15, 2006 page 19 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
TIMERS
Timer 1 and Timer 2
The 38K2 group has three timers: timer X, timer 1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is contin-
ued. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1”.
The count source of prescaler 12 is the system clock divided by
16. The output of prescaler 12 is counted by timer 1 and timer 2,
and a timer underflow periodically sets the interrupt request bit.
Timer X
Timer X can each select in one of four operating modes by setting
the timer X mode register.
(1) Timer Mode
The timer counts the count source selected by timer count source
selection bit.
b7
b0
Timer X mode register
(TM : address 002316
)
(2) Pulse Output Mode
The timer counts the system clock divided by 16. Whenever the
contents of the timer reach “0016”, the signal output from the
CNTR0 pin is inverted. If the CNTR0 active edge selection bit is
“0”, output begins at “ H”.
Timer X operating mode bits
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P51 direction register to output mode.
CNTR
0 : Falling edge active for CNTR
Count at rising edge in event counter mode
1 : Rising edge active for CNTR interrupt
0 active edge switch bit
0
interrupt
0
Count at falling edge in event counter mode
Timer X count stop bit
0 : Count start
1 : Count stop
Not used (return “0” when read)
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 pin.
When the CNTR0 active edge selection bit is “0”, the rising edge of
the CNTR0 pin is counted.
When the CNTR0 active edge selection bit is “1”, the falling edge
of the CNTR0 pin is counted.
Fig. 16 Structure of timer X mode register
(4) Pulse Width Measurement Mode
If the CNTR0 active edge selection bit is “0”, the timer counts the
system clock divided by 16 while the CNTR0 pin is at “H”. If the
CNTR0 active edge selection bit is “1”, the timer counts it while the
CNTR0 pin is at “L”.
The count can be stopped by setting “1” to the timer X count stop
bit in any mode. The corresponding interrupt request bit is set
each time a timer underflows.
Rev.2.00 Oct 15, 2006 page 20 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
Data bus
Divider
1/16
Prescaler X latch (8)
Prescaler X (8)
Timer X latch (8)
System clock
Timer mode
Pulse output
mode
Pulse width
measurement
mode
Timer X interrupt
request bit
Timer X (8)
CNTR0 active
edge selection bit
“0”
Event
counter
mode
Timer X count stop bit
P51/CNTR0
CNTR0 interrupt
request bit
“1”
CNTR0 active
edge selection bit
“1”
Q
Q
Toggle
flip-flop
R
T
“0”
Port P51
latch
Timer X latch write
Pulse output mode
Port P51
direction
register
Pulse output mode
Data bus
Prescaler 12 latch (8)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Divider
1/16
Timer 2 interrupt
request bit
System clock
Timer 1 interrupt
request bit
Fig. 17 Timer block diagram
Rev.2.00 Oct 15, 2006 page 21 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
(1) Clock Synchronous Serial I/O Mode
Serial I/O
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register (bit 6 of ad-
dress 0FE016) to “1”.
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the Trancemit/Receive buffer register.
Data bus
Serial I/O control register
Address 0FE016
Address 002616
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P40/EXDREQ/RxD
Shift clock
Clock control circuit
P42/EXTC/SCLK
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
System clock
Baud rate generator
Address 0FE216
1/4
Clock control circuit
P43/EXA1/SRDY
Falling-edge detector
F/F
Shift clock
Transmit shift register
Transmit buffer register
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
P41/EXDACK/TxD
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 002716
Serial I/O status register
Address 002616
Data bus
Fig. 18 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output
TXD
D
0
0
D
1
1
D
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
Serial input
RXD
D
D
D
D
D
D
D
D
2
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 002616
)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Notes
1 : The transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the T
XD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 19 Operation of clock synchronous serial I/O function
Rev.2.00 Oct 15, 2006 page 22 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O control
register to “0”.
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Data bus
Address 002616
Address 0FE016
Serial I/O1 control register
OE
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Character length selection bit
7 bits
P40/EXDREQ/RxD
STdetector
Receive shift register
1/16
8 bits
UART control register
SP detector
PE FE
Address 0FE116
Clock control circuit
Serial I/O synchronous clock selection bit
P42/EXTC/SCLK
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
System clock
Baud rate generator
Address 0FE216
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
Transmit interrupt source selection bit
Transmit shift register
P41/EXDACK/TxD
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Address 002716
Serial I/O status register
Address 002616
Data bus
Fig. 20 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0
TBE=0
TSC=0
TSC=1ꢀ
SP
TBE=1
TBE=1
ST
ST
D
0
D1
Serial output T
X
D
D
0
D
1
SP
1 start bit
ꢀ Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
D
0
D
1
ST
D
0
D1
Serial input RXD
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
Notes
2 : The transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 21 Operation of UART serial I/O function
Rev.2.00 Oct 15, 2006 page 23 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
[Serial I/O Control Register (SIOCON)] 0FE016
The serial I/O control register contains eight control bits for the se-
rial I/O function.
[UART Control Register (UARTCON)] 0FE116
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer.
[Serial I/O Status Register (SIOSTS)] 002716
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 002616
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is write-
only and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer regis-
ter is “0”.
[Baud Rate Generator (BRG)] 0FE216
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
ꢀNotes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
ꢀSet the serial I/O transmit interrupt enable bit to “0” (disabled).
ꢀSet the transmit enable bit to “1”.
ꢀSet the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
ꢀSet the serial I/O transmit interrupt enable bit to “1” (enabled).
Rev.2.00 Oct 15, 2006 page 24 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b7
b0
b7
b0
Serial I/O status register
(SIOSTS : address 002716
Serial I/O control register
(SIOCON : address 0FE016
)
)
BRG count source selection bit (CSS)
0: System clock
1: System clock/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
3
pin operates as ordinary I/O pin
pin operates as SRDY output pin
3
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
b7
b0
UART control register
(UARTCON : address 0FE116
(pins P4
1: Serial I/O enabled
(pins P4 –P4 can operate as serial I/O pins)
0–P43 operate as ordinary I/O pins)
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
0
3
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
Not used (return “0” when read)
(This is a write disabled bit.)
Not used (return “1” when read)
Fig. 22 Structure of serial I/O control registers
Rev.2.00 Oct 15, 2006 page 25 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
USB FUNCTION
The data buffer of each endpoint can be assigned to any area in
the multi-channel RAM. This feature offers highly efficient memory
usage by avoiding re-buffering and enabling simple data modifica-
tion.
38K2 Group is equipped with a USB function control circuit
(USBFCC) that enables effective interfacing with the host-PC.
This circuit is in compliance with USB2.0's Full-Speed Transfer
Mode (12 Mbps, equivalent to USB1.1). This circuit also supports
all four transfer-types specified in the standard USB specification.
The USBFCC has two USB addresses and 6 endpoints, enabling
separate control of the HUB functions and peripheral functions.
The USB address for HUB functions is equipped with two end-
points. Each endpoint is fixed to a specified transfer type:
Endpoint 0 is fixed to Control Transfer and Endpoint 1 is fixed to
Interrupt Transfer.
The transmit/receive data is directly transferred to the data buffer
via the control circuit (direct RAM access type) without disturbing
the CPU operation. This mechanism enables the CPU to transfer
data smoothly with no drop in performance. In addition to this
buffer function, a double-buffer setting will keep a re-buffering stall
at a minimum and increase the overall data throughput (max. 64
bytes X 2 channels).
As other special signals control, the endpoints have detection
functions for the USB bus reset signal, resume signal, suspend
signal, and SOF signal, and also have a remote wake-up signal
transmit function.
The USB address for peripheral functions is equipped with four
endpoints that can select its transfer type. Although Endpoint 0 is
fixed to Control Transfer, the Endpoints 1 to 3 can be set to Inter-
rupt Transfer, Bulk Transfer, or Isochronous Transfer.
When completing data transfer or receiving a special signal, the
endpoint generates the corresponding interrupt to the CPU (3 vec-
tors/24 factors).
A dedicated circuit automatically performs stage management for
Control Transfer and packet management for transactions, which
are necessary for matching of data transmit/receive timing, error
detection, and retry after error. This dedicated control circuit en-
ables the user to develop a program or timing design very easily.
Each endpoint can be programmed for data transfer conditions so
that the endpoints are adaptive for all USB device class transfer
systems.
With all this essential yet comprehensive built-in hardware, your
system using the 38K2 group will be ready for any USB applica-
tion that comes its way.
38K2 Group MCU
Built-in Peripheral
Functions
CPU
Program ROM
Interrupt request
USB Bus
(USB-Host)
External Bus Interface
(EXB)
Multi-channel RAM
USB
Data transmit/Receive path
[Direct RAM Access Type]
Fig. 23 USB function overview
USB Data Transfer
transfer is performed every 5 to 6 cycles and access for a bit-stuff-
ing transfer is performed in up to 7 cycles.
The USB specification promises 12 Mbps data transfer in the full-
speed mode, that is equivalent to 1.5 M bytes per second of data
transactions.
If the EXB function is enabled in the above conditions, this func-
tion generates a maximum wait of 1 clock cycle, so that the
access is performed every 4 to 8 cycles.
However, in USB data transfer, bit-stuffing may be executed de-
pending on the bit patterns of the transfer data, possibly resulting
in 1-byte data (normally 8 bits) handled as up to 10 bits.
Because USB uses asynchronous transfers, the clock cycle of the
USB internal reference clock may change to adjust to the clock
phase. Therefore, the access timing of the USBFCC for the multi-
channel RAM will change owing to the frequency of internal clock φ:
When the USBFCC is operating at φ =8 MHZ, access for a normal
When operating at φ = 6MHZ, a normal access is performed every
4 cycles. If the clock-phase correction of the reference clock oc-
curs, access is performed every 3 to 5 cycles.
If bit stuffing occurs at this clock rate, the access cycle will be ex-
tended to up to 6 cycles. When the EXB function that generates a
maximum 1-wait cycle is used in this condition, the access cycle
will be 2 (min.) to 7 (max.) cycles.
Rev.2.00 Oct 15, 2006 page 26 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
USB Function Control Circuit (USBFCC) Block
Diagram
The following diagram shows the USBFCC block diagram. The cir-
cuit comprises:
(1) Serial Interface Engine (SIE)
(2) Device Control Unit (DCU)
(3) Internal Memory Interface (MIF)
(4) CPU Interface (CIF)
USB Function Control Circuit
DCU control
DCU status
MIF control
SIE control
SIE status
D0+
D0-
Transmit/Receive
data
Multi-Channel RAM
Fig. 24 USB Function Control Circuit (USBFCC) block diagram
(1) Serial Interface Engine (SIE)
(3) Memory Interface (MIF)
The SIE performs the following USB lower-layer protocols (pack-
ets, transactions):
The MIF controls the flow of data transfer between the SIE and the
multi-channel RAM under the management of the DCU.
•Sampling of receive data and clock, generation of transmit clock
•Serial-to-parallel conversion of transmit/receive data
•NRZI (Non Return Zero Invert) encode/decode
•Bit stuffing/unstuffing
(4) CPU Interface (CIF)
The CIF performs the following functions:
•Mode setting via registers, DCU control signal generation, DCU
status signal reading
•SYNC (Synchronization Pattern) detection, EOP (End of
Packet) detection
•Interrupt signal generation
•USB address detection, endpoint detection
•CRC (Cyclic Redundancy Check) generation and checking
•Internal bus interface control.
(2) Device Control Unit (DCU)
The DCU manages the following USB upper-layer protocols (ad-
dress/endpoint and control-transfer sequence):
•Status control for each endpoint
•Control-transfer sequence control
•Memory interface status control
Rev.2.00 Oct 15, 2006 page 27 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
USB Port External Circuit Configuration
The operation mode of the USB port driver circuit can be config-
ured by USB control register (address 001016).
Figure 25 and Figure 26 show the USB port external circuit block
diagram.
VREFCON
0
1
Hiz
DVCC
0
1
Hiz
3.3V output
3.3V output
Normal mode Low-power mode
USBVREF status
V
REFE
USBVREF
USB Reference
Voltage Circuit
2.2 µF
0.1 µF
VREFCON
TRON
TRONCON
TRONE
1.5 kΩ
27 Ω
D0+
Full
Speed
X
OUT
“1”
VCO
f
PLL
fUSB
USB
Module
USBE
“0”
UCLKCON
+
-
USBDIFE
USBE
27 Ω
D0-
Full
Speed
USBE
Fig. 25 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (4.0V ≤ VCC ≤ 5.25V)
3.0V to 3.6V
(Note)
USBVREF
0.1 µF
TRON
D0+
TRONCON
TRONE
1.5 kΩ
27 Ω
Full
Speed
X
OUT
“1”
VCO
f
PLL
f
USB
USB
Module
USBE
USBDIFE
USBE
“0”
UCLKCON
+
-
27 Ω
D0-
Full
Speed
Note: In Vcc = 3.0 V to 3.6 V connect this pin to Vcc.
USBE
Fig. 26 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (3.0V ≤ VCC ≤ 4.0V)
Rev.2.00 Oct 15, 2006 page 28 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
Endpoint Buffer Area Setting
Memory
000016
The buffer area used in data transfer can be assigned to any area
0FED16
of the multi-channel RAM for each endpoint.
00
0FED16 = 15h
0010 1010 0000
0000
Disabled to be used
SFR
002016
004016
006016
01
ꢀBuffer area beginning address
02
03
The buffer area configuration register (address 0FED16) defines
the beginning address of the buffer area (every 32 bytes) for each
Endpoint. However, the only RAM area is configurable.
•00h [Address 000016], 01h [Address 002016]: Not configurable
•02h [Address 004016] to 1Fh [Address 03E016]: Configurable
RAM
15
02A016
03E016
1F
ꢀInterrupt-source dependant buffer area offset address
An offset value is added to the beginning address of each source,
which is specified by the interrupt source register (address
001D16), for each endpoint.
Fig. 27 Example setting of buffer area beginning address
This section describes in detail the beginning address specified by
the buffer area set register as offset address 00h, according to
each endpoint.
B1RDY01 (Buffer 1 Ready Interrupt):
The offset address varies according to the double buffer begin-
ning address set bit (BSIZ01).
-Offset address = 08h when BSIZ01 = 00
-Offset address = 10h when BSIZ01 = 01
-Offset address = 40h when BSIZ01 = 10
-Offset address = 80h when BSIZ01 = 11
(1) Endpoint 00
Endpoint 00 has two kinds of interrupt sources for accessing the
buffer. The respective address offsets are:
•BSRDY00 (SETUP Buffer Ready Interrupt): Offset address = 00h
•BRDY00 (OUT or IN Buffer Ready Interrupt):
Offset address = 08h
(3) Endpoints 02 and 03
Same as Endpoint 01.
(2) Endpoint 01
The buffer area offset address for each interrupt source for of End-
point 01 varies according to the contents of the EP01 set register
(address 001916).
(4) Endpoint 10
Same as Endpoint 00.
•In single buffer mode (DBLB01 = “0”):
Endpoint 01 has only one interrupt source for accessing the
buffer.
(5) Endpoint 11
Endpoint 11 has only one interrupt source for accessing the buffer.
B0RDY11 (Buffer 0 Ready Interrupt): Offset address = 00h
B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h
•In double buffer mode (DBLB01 = “1”):
Endpoint 01 has two kinds of interrupt sources for accessing the
buffer.
Notes
The selected RAM area must be within addresses 004016 to
03FF16.
B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h
Make sure the buffer area beginning address is set in agreement
with the offset address and the number of transmit/receive data
bytes.
This is particularly important when in the double buffer mode or
when handling 64-byte data.
(d) When selecting Endpoint 11
(a) When selecting Endpoint 00
(b) When selecting Single Buffer Mode
(c) When selecting Double Buffer Mode
(when BSIZ01 = 11)
Offset
Offset
00
Offset
Offset
00
Memory
02A016
Memory
02A016
Memory
02A016
Memory
02A016
h
00
h
h
h
00h
BSRDY00
BRDY00
B0RDY01
B1RDY01
02A816
08h
B0RDY11
B0RDY01
032016
80
Fig. 28 Examples of interrupt source dependant buffer area offset address
Rev.2.00 Oct 15, 2006 page 29 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
USB Interrupt Function
USB Interrupt Control Circuit (USBINTCON) has 3 requests and
22 USB-device interrupt request sources. Each interrupt source
register enables the user to easily determine which interrupt has
occurred.
Table 7 shows the list of USB interrupt sources.
Table 7 USB interrupt sources
Interrupt request bit
USB interrupt bit
(USBIREQ: Address 001716)
—
Interrupt source
At USB bus reset signal detection:
(IREQ1: Address 003C16
)
USB bus reset
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 2.5 µs SE0 state is detected in D0+/D0- port.
(Equivalent to 120-clock length when fUSB = 48 MHz)
At SOF packet receive:
USB SOF
—
After enabling the USB module (USBE = “1”), an interrupt request occurs
when SOF packet is detected in D0+/D0- port.
Its occurrence does not depend on frame-time or CRC value after SOF
packet is transferred.
(Normally, SOF packet detection occurs only when fUSB = 48 MHz)
At Endpoint 00 data transfer complete:
•Buffer ready (read/write enabled state)
•Control transfer completed
USB device
EP00
•Status stage transition
•SETUP buffer ready (read enabled state)
•Control transfer error
At Endpoint 01 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
EP01
EP02
At Endpoint 02 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At Endpoint 03 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
EP03
EP10
At Endpoint 10 data transfer complete:
•Buffer ready (read/write enabled state)
•Control transfer completed
•Status stage transition
•SETUP buffer ready (read enabled state)
•Control transfer error
At Endpoin 11 data transfer complete:
•Buffer 0 ready (write enabled state)
At suspend signal detection:
EP11
SUS
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 3 ms J state is detected in D0+/D0- port.
(Equivalent to 144,000 clock-length when fUSB = 48MHz)
At resume signal detection:
RSM
After enabling the USB module (USBE = “1”) and resume interrupt (RSME
= “1”), an interrupt request occurs when a bus state change (J state to
SE0 or K state) is detected in D0- port.
Rev.2.00 Oct 15, 2006 page 30 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
[EPXXREG5]
[USBIREQ]
[USBICON]
EP00E
[EP00REQ]
BRDY00
CTEND00
CTSTS00
BSYDY00
ERR00
USB device
interrupt request
EP00
[EP01REQ]
EP01E
EP02E
EP03E
B0RDY01
B1RDY01
ERR01
EP01
EP02
EP03
[EP02REQ]
B0RDY02
B1RDY02
ERR02
[EP03REQ]
B0RDY03
B1RDY03
ERR03
[EP10REQ]
BRDY10
CTEND10
CTSTS10
BSYDY10
ERR10
EP10E
EP11E
EP10
EP11
[EP11REQ]
B0RDY11
SUSE
RSME
SUS
RSM
Fig. 29 USB device interrupt control
Rev.2.00 Oct 15, 2006 page 31 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
USB Register List
The USB register list is shown below.
USB SFR
Address
Register Name
SYMBOL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
USB control register
USBCON
USBE
UCLKCON
USBDIFE
VREFE
VREFCON
TRONE
TRONCON
AD1E
WKUP
AD0E
USB Function/Hub enable register
USB function address register
USB HUB address register
Frame number register Low
Frame number register High
USB interrupt source enable register
USB interrupt source register
Endpoint index register
USBAE
USBA0
USBADD0[6:0]
USBADD1[6:0]
USBA1
FNUML
FNUM[7:0]
FNUMH
FNUM[10:8]
EP01E
USBICON
USBIREQ
USBINDEX
EPXXREG1
EPXXREG2
EPXXREG3
EPXXREG4
EPXXREG5
EPXXREG6
EPXXREG7
EPXXREG8
EPXXREG9
RSME
RSM
SUSE
SUS
EP11E
EP11
EP10E
EP10
EP03E
EP03
EP02E
EP02
EP00E
EP00
EP01
ADIDX
EPIDX[1:0]
Endpoint field register 1
Endpoint field register 2
Endpoint field register 3
001C16 Endpoint field register 4
001D16 Endpoint field register 5
001E16
001F16
Endpoint field register 6
Endpoint field register 7
0FEC16 Endpoint field register 8
0FED16 Endpoint field register 9
(1) Endpoint 00
001916
EP00 stage register
EP00STG
EP00CON1
EP00CON2
EP00CON3
EP00REQ
EP00BYT
SETUP00
PID00[1:0]
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
EP00 control register 1
EP00 control register 2
EP00 control register 3
EP00 interrupt source register
EP00 byte number register
BVAL00
CTENDE00
BRDY00
ERR00
BSRDY00
CTSTS00
CTEND00
BBYT00[3:0]
EP00 buffer area set register
EP00BUF
BADD00[4:0]
DBLB01
(2) Endpoint 01
001916
001A16
001B16
EP01 set register
EP01CFG
EP01CON1
EP01CON2
EP01CON3
EP01REQ
EP01BYT0
EP01BYT1
EP01MAX
EP01BUF
TYP01[1:0]
DIR01
ITMD01
SQCL01
BSIZ01[1:0]
PID01[1:0]
B0VAL01
EP01 control register 1
EP01 control register 2
001C16 EP01 control register 3
B1VAL01
B0RDY01
001D16 EP01 interrupt source register
ERR01
B1RDY01
001E16
001F16
EP01 byte number register 0
EP01 byte number register 1
B0BYT01[6:0]
B1BYT01[6:0]
MXPS01[6:0]
0FEC16 EP01 MAX. packet size register
0FED16 EP01 buffer area set register
BADD01[4:0]
DBLB02
(3) Endpoint 02
001916
EP02 set register
EP02CFG
EP02CON1
EP02CON2
EP02CON3
EP02REQ
EP02BYT0
EP02BYT1
EP02MAX
EP02BUF
TYP02[1:0]
DIR02
ITMD02
SQCL02
BSIZ02[1:0]
PID02[1:0]
B0VAL02
001A16
001B16
001C16
001D16
001E16
001F16
EP02 control register 1
EP02 control register 2
EP02 control register 3
EP02 interrupt source register
EP02 byte number register 0
EP02 byte number register 1
B1VAL02
B0RDY02
ERR02
B1RDY02
B0BYT02[6:0]
B1BYT02[6:0]
MXPS02[6:0]
0FEC16 EP02 MAX. packet size register
0FED16 EP02 buffer area set register
BADD02[4:0]
DBLB03
(4) Endpoint 03
001916
EP03 set register
EP03CFG
EP03CON1
EP03CON2
EP03CON3
EP03REQ
EP03BYT0
EP03BYT1
EP03MAX
EP03BUF
TYP03[1:0]
DIR03
ITMD03
SQCL03
BSIZ03[1:0]
PID03[1:0]
B0VAL03
001A16
001B16
EP03 control register 1
EP03 control register 2
001C16 EP03 control register 3
B1VAL03
B0RDY03
001D16 EP03 interrupt source register
ERR03
B1RDY03
001E16
001F16
EP03 byte number register 0
EP03 byte number register 1
B0BYT03[6:0]
B1BYT03[6:0]
MXPS03[6:0]
0FEC16 EP03 MAX. packet size register
0FED16 EP03 buffer area set register
BADD03[4:0]
(5) Endpoint 10
001916
EP10 set register
EP10STG
EP10CON1
EP10CON2
EP10CON3
EP10REQ
EP10BYT
SETUP10
001A16
001B16
EP10 control register 1
EP10 control register 2
PID10[1:0]
BVAL10
CTENDE10
BRDY10
001C16 EP10 control register 3
001D16 EP10 interrupt source register
ERR10
BSRDY10
CTSTS10
CTEND10
001E16
001F16
0FEC16
EP10 byte number register
BBYT10[3:0]
0FED16 EP10 buffer area set register
(6) Endpoint 11
001916
EP10BUF
BADD10[4:0]
EP11 set register
EP11CFG
EP11CON1
EP11CON2
TYP11
DIR11
SQCL11
001A16
001B16
001C16
EP11 control register 1
EP11 control register 2
PID11[1:0]
B0VAL11
001D16 EP11 interrupt source register
EP11REQ
EP11BYT0
B0RDY11
B0BYT11
001E16
001F16
0FEC16
EP11 byte number register
0FED16 EP11 buffer area set register
EP11BUF
BADD11[4:0]
: Not used
Fig. 30 USB related registers
Rev.2.00 Oct 15, 2006 page 32 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
USB Related Registers
The USB related registers are shown below.
b0
b7
USB control register (USBCON) [address 001016
]
At reset
R W
Bit name
Function
Bit symbol
WKUP
H/W S/W
Remote wakeup bit
0 : Returning to BUS idle state by writing “1” first and
then “0”. (Remote wakeup signal)
0
–
O O
1 : K-state output
TRONCON TrON output control bit
TRONE TrON output enable bit
0 : “L” output mode (valid in TRONE = “1”)
1 : “H” output mode (valid in TRONE = “1”)
0 : TrON port output disabled (Hi-Z state)
1 : TrON port output enabled
0
0
0
0
0
0
0
–
–
–
–
–
–
–
O O
O O
O O
O O
O O
O O
O O
VREFCON USB reference voltage control bit 0 : Normal mode (valid in VREFE = “1”)
1 : Low current mode (valid in VREFE = “1”)
VREFE
USB reference voltage enable bit 0 : USB reference voltage circuit operation disabled
1 : USB reference voltage circuit operation enabled
USBDIFE
USB difference input enable bit 0 : Upstream-port difference input circuit operation disabled
1 : Upstream--port difference input circuit operation enabled
UCLKCON USB clock select bit
0 : External oscillating clock f(XIN
1 : PLL circuit output clock (fVCO
USB module operation enable bit 0 : USB module reset
1 : USB module operation enabled
)
)
USBE
–: State remaining
Fig. 31 Structure of USB control register
b0
b7
0
USB function/HUB enable register (USBAE) [address 001116
]
0
0
0 0 0
At reset
R W
Bit symbol
AD0E
Function
Bit name
H/W S/W
USB function enable bit
0: USB function address register invalidated
1: USB function address register validated
0: USB HUB address register invalidated
1: USB HUB address register validated
Write “0” when writing.
0
0
–
–
–
–
O O
O O
O O
AD1E
b7:b2
USB HUB enable bit
Not used
“0” is read when reading.
–: State remaining
Fig. 32 Structure of USB function/HUB enable register
Rev.2.00 Oct 15, 2006 page 33 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
USB function address register (USBA0) [address 001216
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
USBADD0 USB function address bit
[6:0]
In AD0E = “0”, this value changes after writing.
In AD0E = “1”, this value changes after completion of
SET_ADDRESS control transferring.
Write “0” when writing.
0
0
O O
b7
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 33 Structure of USB function address register
b0
b7
0
USB HUB address register (USBA1) [address 001316
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
USBADD1 USB HUB address bit
[6:0]
In AD1E = “0”, this value changes after writing.
In AD1E = “1”, this value changes after completion of
SET_ADDRESS control transferring.
Write “0” when writing.
0
0
O O
b7
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 34 Structure of USB HUB address register
b0
b7
Frame number register Low (FNUML) [address 001416
]
At reset
R W
Bit symbol
Function
The frame number is updated at SOF reception.
Bit name
H/W S/W
FNUM
[7:0]
Frame number low bit
In-
In-
O ꢀ
definite definite
Fig. 35 Structure of Frame number register Low
b0
b7
0
0
0
0
0
Frame number register High (FNUMH) [address 001516]
At reset
H/W S/W
Bit symbol
Function
R W
Bit name
In-
In-
FNUM
[10:8]
b7:b3
Frame number high bit
The frame number is updated at SOF reception.
O
ꢀ
definite definite
–
–
Not used
Write “0” when writing.
O O
“0” is read when reading.
–: State remaining
Fig. 36 Structure of Frame number register High
Rev.2.00 Oct 15, 2006 page 34 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
USB interrupt source enable register (USBICON) [address 001616
]
At reset
R W
Bit symbol
EP00E
Function
Bit name
H/W S/W
USB function/Endpoint 0 interrupt 0 : Interrupt disabled
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O O
O O
O O
O O
O O
O O
O O
O O
enable bit
USB function/Endpoint 1 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
USB function/Endpoint 2 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
USB function/Endpoint 3 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
USB HUB/Endpoint 0 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
USB HUB/Endpoint 1 interrupt 0 : Interrupt disabled
1 : Interrupt enabled
EP01E
EP02E
EP03E
EP10E
EP11E
SUSE
enable bit
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Suspend interrupt enable bit
RSME
Resume interrupt enable bit
Fig. 37 Structure of USB interrupt source enable register
Rev.2.00 Oct 15, 2006 page 35 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
USB interrupt source register (USBIREQ) [address 001716
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
EP00
EP01
EP02
EP03
EP10
EP11
SUS
USB function/Endpoint 0
interrupt bit
This bit is set to “1” when any one of EP00 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP00 interrupt
source register to “0016”.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
O
O
O
O
O
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP01 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP01 interrupt
source register to “0016”.
USB function/Endpoint 1
interrupt bit
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP02 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP02 interrupt
source register to “0016”.
USB function/Endpoint 2
interrupt bit
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP03 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP03 interrupt
source register to “0016”.
USB function/Endpoint 3
interrupt bit
Writing to this bit causes no state change.
USB HUB/Endpoint 0 interrupt This bit is set to “1” when any one of EP10 interrupt
bit
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP10 interrupt
source register to “0016”.
Writing to this bit causes no state change.
USB HUB/Endpoint 1 interrupt This bit is set to “1” when any one of EP11 interrupt
bit
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP11 interrupt
source register to “0016”.
Writing to this bit causes no state change.
0 : No interrupt request issued
Suspend interrupt bit
O O
1 : Interrupt request issued
This bit is set to “1” when detecting 3 ms or more of J-
state, using USB clock (fUSB) at 48 MHz.
“0” can be set by software, but “1” cannot be set.
This bit is set to “1” when the USB bus state changes
from J-state to K-state or SE0 in the resume interrupt
enable bit = “1”. It is also “1” in the condition of internal
clock stopped.
RSM
Resume interrupt bit
O
ꢀ
This bit is cleared to “0” by clearing the resume
interrupt enable bit.
Writing to this bit causes no state change.
Fig.38 Structure of USB interrupt source register
Rev.2.00 Oct 15, 2006 page 36 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
Endpoint index register (USBINDEX) [address 001816
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
EPIDX [1:0] Endpoint index bit
b1 b0
0
–
O O
0
0
1
1
0 : Endpoint 0
1 : Endpoint 1
0 : Endpoint 2
1 : Endpoint 3
ADIDX
b7:b3
Address index bit
Not used
0 : USB function
1 : USB HUB
0
–
–
O O
O O
Write “0” when writing.
–
“0” is read when reading.
–: State remaining
Fig. 39 Structure of Endpoint index register
Rev.2.00 Oct 15, 2006 page 37 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(1) Endpoint 00
b0
b7
EP00 stage register (EP00STG) [address 001916
]
0
0
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
SETUP00
b7:b1
SETUP packet detection bit
This bit is set to “1” at reception of SETUP packet.
Writing “0” to this bit clears this bit if the next SETUP
token does not occur.
1
1
O O
Writing “1” to this bit causes no state change of the
status flags.
Not used
Write “0” when writing.
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 40 Structure of EP00 stage register
b0
b7
0
EP00 control register 1 (EP00CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID00 [1:0] Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 41 Structure of EP00 control register 1
b0
b7
0
0
0
0
0
0
0
EP00 control register 2 (EP00CON2) [address 001B16]
At reset
R W
Bit symbol
BVAL00
Function
Bit name
Buffer enable bit
H/W S/W
O O
0
–
0 : NAK transmission (SIE is disabled to read a buffer.)
1 : Transmitting/receiving data set state (SIE is possible
to read from/write to a buffer.)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
O O
b7:b1
Not used
–
–
“0” is read when reading.
–: State remaining
Fig. 42 Structure of EP00 control register 2
Rev.2.00 Oct 15, 2006 page 38 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
EP00 control register 3 (EP00CON3) [address 001C16
]
0
0
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
CTENDE00 Control transfer completion
enable bit
0
–
0 : NAK transmission in the status stage
1 : Control transfer completion enabled (SIE transmits
NULL/ACK.) (valid in PID00 = “012”)
At reception of SETUP token:
O O
This bit is cleared to “0” by the hardware.
Write “0” when writing.
b7:b1
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 43 Structure of EP00 control register 3
b0
b7
0
EP00 interrupt source register (EP00REQ) [address 001D16
]
0
0
At reset
R W
Bit symbol
BRDY00
Function
USB function/Endpoint 0 buffer 0: No interrupt request issued
Bit name
H/W S/W
0
0
O O
ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
CTEND00
CTSTS00
USB function/Endpoint 0 control 0: No interrupt request issued
transfer completion interrupt bit 1: Interrupt request issued
0
0
O O
This bit is set to “1” when control transfer is completed
(NULL/ACK transmission in the status stage) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 0 status 0: No interrupt request issued
0
0
O O
stage transition interrupt bit
1: Interrupt request issued
This bit is set to “1” when transition to status stage
occurs in CTENDE00 = “0” (control transfer completion
disabled) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
<Transition to status stage occurrence factor>
At transfer of control write:
When receiving IN-token in data stage (OUT)
At transfer of control read:
When receiving OUT-token in data stage (IN)
At no data transfer:
Nothing occurs.
BSRDY00
ERR00
USB function/Endpoint 0 SETUP 0: No interrupt request issued
0
0
0
0
O O
buffer ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the exclusive buffer for
SETUP is ready state (enabled to be read) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
USB function/Endpoint 0 error
interrupt bit
O O
1: Interrupt request issued
This bit is set to “1” when control transfer error occurs
on USB function/Endpoint 0.
This bit is cleared to “0” by the hardware when
receiving SETUP token.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
b7:b5
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 44 Structure of EP00 interrupt source register
Rev.2.00 Oct 15, 2006 page 39 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
EP00 byte number register (EP00BYT) [address 001E16
]
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BBYT00
[3:0]
OUT : The received byte number is automatically set.
IN : Set the transmitting byte number.
Write 0 when writing.
0
—
Transmit/receive byte number bit
Not used
O O
O O
b7:b4
—
—
0 is read when reading.
—: State remaining
Fig. 45 Structure of EP00 byte number register
b0
b7
0
EP00 buffer area set register (EP00BUF) [address 0FED16
]
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
BADD00
[4:0]
EP00 beginning address set bit Set the beginning address of EP00’s buffer area.
0
–
O O
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
b7:b5
Not used
Write “0” when writing.
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 46 Structure of EP00 buffer area set register
Rev.2.00 Oct 15, 2006 page 40 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(2) Endpoint 01
b0
b7
EP01 set register (EP01CFG) [address 001916
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BSIZ01
[1:0]
Double buffer beginning address set In double buffer mode set the beginning address of
0
–
O O
bit
buffer 1 area, using a relative value for the beginning
address of buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
DBLB01
SQCL01
Buffer mode select bit
0 : Single buffer mode
0
0
–
–
O O
O O
1 : Double buffer mode
Sequence toggle bit clear bit
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
ITMD01
DIR01
Interrupt toggle mode select bit 0 : Normal mode
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0
0
0
–
–
–
O O
O O
O O
Transfer direction bit
0 : OUT (Data is received from the host.)
1 : IN (Data is transmitted to the host.)
b7b6
TYP01
[1:0]
Transfer type bite
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
–: State remaining
Fig. 47 Structure of EP01 set register
b0
b7
0
EP01 control register 1 (EP01CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID01
[1:0]
Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 48 Structure of EP01 control register 1
Rev.2.00 Oct 15, 2006 page 41 of 130
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HARDWARE
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FUNCTIONAL DESCRIPTION
b0
b7
0
0
0
0
0
0
0
EP01 control register 2 (EP01CON2) [address 001B16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0VAL01
0
–
O O
Buffer 0 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
b7:b1
–
–
O O
Not used
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 49 Structure of EP01 control register 2
b0
b7
0
EP01 control register 3 (EP01CON3) [address 001C16
]
0
0
0
0 0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B1VAL01
0
–
O O
Buffer 1 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
Write “0” when writing.
b7:b1
–
–
O O
Not used
“0” is read when reading.
–: State remaining
Fig.50 Structure of EP01 control register 3
b0
b7
0
EP01 interrupt source register (EP01REQ) [address 001D16
]
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0RDY01
B1RDY01
0
0
USB function/Endpoint 1 buffer 0
ready interrupt bit
O O
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
0
0
USB function/Endpoint 1 buffer 1
ready interrupt bit
O O
1: Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 1
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
ERR01
b7:b3
0
0
USB function/Endpoint 1 error
interrupt bit
O O
O O
1: Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
–
–
Not used
“0” is read when reading.
Fig. 51 Structure of EP01 interrupt source register
Rev.2.00 Oct 15, 2006 page 42 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
EP01 byte number register 0 (EP01BYT0) [address 001E16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
0
–
IN : Transmit byte number bit
O O
B0BYT01
[6:0]
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
0
–
OUT : Receive byte number bit
O ꢀ
Single buffer mode : The received byte number is
automatically set.
Double buffer mode :The received byte number of buffer 0
is automatically set.
–
–
Not used
O O
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 52 Structure of EP01 byte number register 0
b0
b7
0
EP01 byte number register 1 (EP01BYT1) [address 001F16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
0
–
–
–
–
IN : Transmit byte number bit
O
O
O
O
ꢀ
O
B1BYT01
[6:0]
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
OUT : Receive byte number bit
Not used
Single buffer mode: These bits are invalid.
Double buffer mode :The received byte number of buffer 1
is automatically set.
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 53 Structure of EP01 byte number register 1
b0
b7
0
EP01 MAX. packet size register (EP01MAX) [address 0FEC16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
–
MXPS01
[6:0]
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
Max. packet size bit
O O
O O
–
–
b7
Not used
“0” is read when reading.
–: State remaining
Fig. 54 Structure of EP01 MAX. packet size register
Rev.2.00 Oct 15, 2006 page 43 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
EP01 buffer area set register (EP01BUF) [address 0FED16
]
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BADD01
[4:0]
EP01 beginning address set bit Set the beginning address of EP01’s buffer area.
0
–
O O
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 55 Structure of EP01 buffer area set register
Rev.2.00 Oct 15, 2006 page 44 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(3) Endpoint 02
b0
b7
EP02 set register (EP02CFG) [address 001916
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BSIZ02
[1:0]
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1
0
–
O O
bit
area, using a relative value for the beginning address of
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
DBLB02
SQCL02
Buffer mode select bit
0 : Single buffer mode
1 : Double buffer mode
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
0
0
–
–
O O
O O
Sequence toggle bit clear bit
“0” is always read when reading.
ITMD02
DIR02
Interrupt toggle mode select bit 0 : Normal mode
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0
0
0
–
–
–
O O
O O
O O
Transfer direction bit
0 : OUT (Data is received from the host.)
1 : IN (Data is transmitted to the host.)
b7b6
TYP02
[1:0]
Transfer type bite
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
–: State remaining
Fig. 56 Structure of EP02 set register
b0
b7
0
EP02 control register 1 (EP02CON1) [address 001A16
]
0
0
0
0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID02
[1: 0]
Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 57 Structure of EP02 control register 1
Rev.2.00 Oct 15, 2006 page 45 of 130
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HARDWARE
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FUNCTIONAL DESCRIPTION
b0
b7
EP02 control register 2 (EP02CON2) [address 001B16
]
0
0
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0VAL02
0
–
O O
Buffer 0 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
b7:b1
–
–
O O
Not used
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 58 Structure of EP02 control register 2
b0
b7
0
0
0
0
0
0
0
EP02 control register 3 (EP02CON3) [address 001C16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B1VAL02
0
–
O O
Buffer 1 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
Write “0” when writing.
b7:b1
–
–
O O
Not used
“0” is read when reading.
–: State remaining
Fig. 59 Structure of EP02 control register 3
b0
b7
0
EP02 interrupt source register (EP02REQ) [address 001D16
]
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0RDY02
B1RDY02
0
0
USB function/Endpoint 2 buffer 0
ready interrupt bit
O O
0 : No interrupt request issued
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
0
0
USB function/Endpoint 2 buffer 1
ready interrupt bit
O O
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 2
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
ERR02
0
0
USB function/Endpoint 2 error
interrupt bit
O O
O O
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
b7 to b3
–
–
Not used
“0” is read when reading.
Fig. 60 Structure of EP02 interrupt source register
Rev.2.00 Oct 15, 2006 page 46 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
EP02 byte number register 0 (EP02BYT0) [address 001E16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
0
–
IN : Transmit byte number bit
O O
B0BYT02
[6:0]
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
0
–
OUT : Receive byte number bit
O ꢀ
Single buffer mode: The received byte number is
automatically set.
Double buffer mode :The received byte number of buffer 0
is automatically set.
–
–
Not used
O O
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 61 Structure of EP02 byte number register 0
b0
b7
0
EP02 byte number register 1 (EP02BYT1) [address 001F16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
0
–
–
–
–
IN : Transmit byte number bit
O O
O ꢀ
O O
B1BYT02
[6:0]
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
OUT : Receive byte number bit
Not used
Single buffer mode: These bits are invalid.
Double buffer mode :The received byte number of buffer 1
is automatically set.
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 62 Structure of EP02 byte number register 1
b0
b7
0
EP02 MAX. packet size register (EP02MAX) [address 0FEC16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
–
MXPS02
[6:0]
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
Max. packet size bit
O O
O O
–
–
b7
Not used
“0” is read when reading.
–: State remaining
Fig. 63 Structure of EP02 MAX. packet size register
Rev.2.00 Oct 15, 2006 page 47 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
EP02 buffer area set register (EP02BUF) [address 0FED16
]
0
0
0
At reset
R W
H/W S/W
Bit symbol
Bit name
Function
BADD02
[4:0]
EP02 beginning address set bit
Set the beginning address of EP02’s buffer area.
(32-byte unit)
0
–
O O
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 64 Structure of EP02 buffer area set register
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(4) Endpoint 03
b0
b7
EP03 set register (EP03CFG) [address 001916
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BSIZ03
[1:0]
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1
0
–
O O
bit
area, using a relative value for the beginning address of
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
DBLB03
SQCL03
Buffer mode select bit
0 : Single buffer mode
1 : Double buffer mode
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
0
0
–
–
O O
O O
Sequence toggle bit clear bit
“0” is always read when reading.
ITMD03
DIR03
Interrupt toggle mode select bit 0 : Normal mode
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0
0
0
–
–
–
O O
O O
O O
Transfer direction bit
0 : OUT (Data is received from the host.)
1 : IN (Data is transmitted to the host.)
b7b6
TYP03
[1:0]
Transfer type bit
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
–: State remaining
Fig. 65 Structure of EP03 set register
b0
b7
0
EP03 control register 1 (EP03CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID03
[1:0]
Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 66 Structure of EP03 control register 1
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38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
0
0
0
0
0
0
EP03 control register 2 (EP03CON2) [address 001B16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0VAL03
0
–
O O
Buffer 0 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
b7:b1
–
–
O O
Not used
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 67 Structure of EP03 control register 2
b0
b7
0
EP03 control register 3 (EP03CON3) [address 001C16
]
0
0
0
0 0 0
At reset
R W
H/W S/W
Bit symbol
Bit name
Function
B1VAL03
0
–
O O
Buffer 1 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
Write “0” when writing.
b7:b1
–
–
O O
Not used
“0” is read when reading.
–: State remaining
Fig. 68 Structure of EP03 control register 3
b0
b7
0
EP03 interrupt source register (EP03REQ) [address 001D16
]
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0RDY03
B1RDY03
0
0
USB function/Endpoint 3 buffer 0
ready interrupt bit
O O
0 : No interrupt request issued
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
0
0
USB function/Endpoint 3 buffer 1
ready interrupt bit
O O
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 3
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
ERR03
b7:b3
0
0
USB function/Endpoint 3 error
interrupt bit
O O
O O
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
–
–
Not used
“0” is read when reading.
Fig. 69 Structure of EP03 interrupt source register
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
EP03 byte number register 0 (EP03BYT0) [address 001E16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
0
–
IN : Transmit byte number bit
O O
B0BYT03
[6:0]
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
0
–
OUT : Receive byte number bit
O ꢀ
Single buffer mode: The received byte number is
automatically set.
Double buffer mode :The received byte number of buffer 0
is automatically set.
–
–
Not used
O O
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 70 Structure of EP03 byte number register 0
b0
b7
0
EP03 byte number register 1 (EP03BYT1) [address 001F16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
0
–
–
–
–
IN : Transmit byte number bit
O O
O ꢀ
O O
B1BYT03
[6:0]
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
OUT : Receive byte number bit
Not used
Single buffer mode: These bits are invalid.
Double buffer mode :The received byte number of buffer 1
is automatically set.
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 71 Structure of EP03 byte number register 1
b0
b7
0
EP03 MAX. packet size register (EP03MAX) [address 0FEC16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
–
MXPS03
[6:0]
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
Max. packet size bit
O O
O O
–
–
b7
Not used
“0” is read when reading.
–: State remaining
Fig. 72 Structure of EP03 MAX. packet size register
Rev.2.00 Oct 15, 2006 page 51 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
EP03 buffer area set register (EP03BUF) [address 0FED16
]
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BADD03
[4:0]
EP03 beginning address set bit
Set the beginning address of EP03’s buffer area.
(32-byte unit)
0
–
O O
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 73 Structure of EP03 buffer area set register
Rev.2.00 Oct 15, 2006 page 52 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(5) Endpoint 10
b0
b7
EP10 stage register (EP10STG) [address 001916
]
0
0
0
0
0
0
0
At reset
R W
H/W S/W
Bit symbol
Bit name
Function
SETUP10
b7:b1
SETUP packet detection bit
This bit is set to “1” at reception of SETUP packet.
Writing “0” clears this bit if the next SETUP token does
not occur.
1
1
O O
Writing “1” causes no state change of the status flags.
This bit change is not for an interrupt source.
Write “0” when writing.
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 74 Structure of EP10 stage register
b0
b7
0
EP10 control register 1 (EP10CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID10 [1:0] Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 75 Structure of EP10 control register 1
b0
b7
0
0
0
0
0
0
0
EP10 control register 2 (EP10CON2) [address 001B16]
At reset
R W
Bit symbol
BVAL10
Function
Bit name
Buffer enable bit
H/W S/W
O O
0
–
0 : NAK transmission (SIE is disabled to read a buffer.)
1 : Transmitting/receiving data set state (SIE is possible to
read from/write to a buffer.) (Valid in PID10 = “012”)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
O O
b7:b1
Not used
–
–
“0” is read when reading.
–: State remaining
Fig. 76 Structure of EP10 control register 2
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38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
EP10 control register 3 (EP10CON3) [address 001C16
]
0
0
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
CTENDE10 Control transfer completion
enable bit
0
–
0 : NAK transmission in the status stage
1 : Control transfer completion enabled (SIE transmits
NULL/ACK.) (Valid in PID10 = “012”)
At reception of SETUP token:
O O
This bit is cleared to “0” by the hardware.
Write “0” when writing.
b7:b1
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 77 Structure of EP10 control register 3
b0
b7
0
EP10 interrupt source register (EP10REQ) [address 001D16
]
0
0
At reset
R W
Bit symbol
BRDY10
Function
Bit name
H/W S/W
USB HUB/Endpoint 10 buffer
ready interrupt bit
0: No interrupt request issued
0
0
O O
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
CTEND10
CTSTS10
USB HUB/Endpoint 10 control
0
0
O O
transfer completion interrupt bit 1: Interrupt request issued
This bit is set to “1” when control transfer is completed
(NULL/ACK transmission in the status stage) on USB
HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
USB HUB/Endpoint 10 status
stage transition interrupt bit
0
0
O O
1: Interrupt request issued
This bit is set to “1” when transition to status stage
occurs in CTENDE10 = “0” (control transfer completion
disabled) on USB HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
<Transition to status stage occurrence factor>
At transfer of control write:
When receiving IN-token in data stage (OUT)
At transfer of control read:
When receiving OUT-token in data stage (IN)
At no data transfer:
Nothing occurs.
BSRDY10
ERR10
USB HUB/Endpoint 10 SETUP 0: No interrupt request issued
0
0
0
0
O O
buffer ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the exclusive buffer for
SETUP is ready state (enabled to be read) on USB
HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
USB HUB/Endpoint 10 error
interrupt bit
O O
1: Interrupt request issued
This bit is set to “1” when control transfer error occurs
on USB HUB/Endpoint 10.
This bit is cleared to “0” by the hardware when
receiving SETUP token.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
b7:b5
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 78 Structure of EP10 interrupt source register
Rev.2.00 Oct 15, 2006 page 54 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
EP10 byte number register (EP10BYT) [address 001E16
]
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BBYT10
[3:0]
OUT : The received byte number is automatically set.
IN : Set the transmitting byte number.
Write 0 when writing.
0
—
Transmit/receive byte number bit
Not used
O O
O O
b7:b4
—
—
0 is read when reading.
—: State remaining
Fig. 79 Structure of EP10 byte number register
b0
b7
0
EP10 buffer area set register (EP10BUF) [address 0FED16
]
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
BADD10
[4:0]
EP10 beginning address set bit
Set the beginning address of EP10’s buffer area.
(32-byte unit)
0
–
O O
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 80 Structure of EP10 buffer area set register
Rev.2.00 Oct 15, 2006 page 55 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(6) Endpoint 11
b0
0
b7
0
0
0
0
EP11 set register (EP11CFG) [address 001916]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
–
–
O O
Write “0” when writing.
b2:b0
Not used
“0” is read when reading.
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
0
–
SQCL11
Sequence toggle bit clear bit
“0” is always read when reading.
Write “0” when writing.
–
0
–
0
–
–
–
–
O O
O O
O O
O O
b4
Not used
“0” is read when reading.
0 : IN transfer disabled
DIR11
b6
Transfer direction bit
Not used
1 : IN (Data is transmitted to the host.)
Write “0” when writing.
“0” is read when reading.
0 : Transfer disabled
TYP11
Transfer type bite
1 : Interrupt transfer
–: State remaining
Fig. 81 Structure of EP11 set register
b0
b7
0
EP11 control register 1 (EP11CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID11
[1:0]
Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (NAK, DATA0, DATA1)
X : STALL
b7:b2
Not used
–
–
Write “0” when writing.
O O
“0” is read when reading.
–: State remaining
Fig. 82 Structure of EP11 control register 1
b0
b7
0
0
0
0
0
0
0
EP11 control register 2 (EP11CON2) [address 001B16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0VAL11
b7:b1
0
–
O O
O O
This bit set to “1” shows the transmitting data is in a set
state (SIE is possible to read).
Buffer 0 status bit
Not used
–
–
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 83 Structure of EP11 control register 2
Rev.2.00 Oct 15, 2006 page 56 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
EP11 interrupt source register (EP11REQ) [address 001D16
]
0
0
0
0 0 0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0RDY11
b7:b1
USB HUB/Endpoint 1 buffer 0
ready interrupt bit
0: No interrupt request issued
0
0
O O
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB HUB/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 84 Structure of EP11 interrupt source register
b0
b7
0
EP11 byte number register (EP11BYT0) [address 001E16
]
0
0
0
0
0
0
At reset
R W
Bit symbol
B0BYT11
Function
Bit name
H/W S/W
IN : Set the transmitting byte number.
0
—
Transmit byte number bit
O O
O O
b7:b1
Write 0 when writing.
0 is read when reading.
—
—
Not used
—: State remaining
Fig. 85 Structure of EP11 byte number register
b0
b7
0
EP11 buffer area set register (EP11BUF) [address 0FED16
]
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
BADD11
[4:0]
EP11 beginning address set bit Set the beginning address of EP11’s buffer area.
0
–
O O
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
b7:b5
Not used
Write “0” when writing.
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 86 Structure of EP11 buffer area set register
Rev.2.00 Oct 15, 2006 page 57 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
HUB FUNCTION
Each down-port register can be controlled by USB commands us-
ing USB addresses for HUB functions or detecting changes in the
bus state of down-ports. The HUBFCC is also equipped with a re-
mote wakeup signal transfer function for use during global resume
as other special signals management. The HUBFCC generates an
interrupt to the CPU when detecting a down-port state change (1
vector, 10 sources).
The 38K2 Group has a HUB Function Control Circuit (HUBFCC)
that offers easy implementation of USB-hub functions (signal re-
peat and bus state detection). This circuit is in compliance with
USB Specification Version 2.0 Full-Speed/Low-Speed Transfer
Modes (12 Mbps/1.5 Mbps, equivalent to Version 1.1).
The HUBFCC operates with two external down-ports and one in-
ternal down-port, which is utilized by the USB addresses of the
built-in peripherals, enabling management of a total of three down-
ports independently.
The flexibility of the indispensable yet wide-ranging HUBFCC
structure and an external interrupt function and I/O ports imple-
mented in the standard features of this MCU enable the power
supply management essential for USB-HUB functions and also al-
low users to easily and effortlessly configure their optimum
system.
A dedicated circuit automatically performs the bus state change
detection and error detection needed for the sequence manage-
ment of the hub repeater circuit, data repeat function, and
down-port status management. This dedicated control circuit en-
sures the user easy development of a program or timing design.
38K2 Group
CPU
USB
Up-port
(USB host)
HUB
Internal down-
port
External down-port External down-port
(USB device)
(USB device)
Fig. 87 HUB functions
Rev.2.00 Oct 15, 2006 page 58 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
HUB Function Control Circuit Block Diagram
The HUB function control circuit, as show in the diagram below,
consists of the following blocks.
(1) HUB repeater block
(2) Down-port control block
(3) CPU interface block (CIF)
HUB Function Control Circuit
HUB repeater block
D0+
D0-
Down-port control block
USB down-port 1
transceiver
USB Down-port 2
transceiver
D1+
D1-
D2+
D2-
Fig. 88 HUB function control circuit block diagram
(1) HUB repeater block
(3) CPU interface block (CIF)
The HUB repeater block, consisting of the circuits listed below,
processes the HUB repeater function sequence. The HUB re-
peater is ready for operation after enabling the USB module
(USBE = “1”).
The CPU interface block performs the following processes.
•Control of repeater/down-port states through registers.
•Generates interrupt signal
•Controls internal bus interface
•Repeater circuit (detects SOP/EOP signal)
•Frame-time circuit (synchronizes to SOF signal and manages
frames in 1 ms)
•Receiver circuit (manages up-port states)
•Transmitter circuit (controls up-port outputs)
(2) Down-port control block
The down-port control block, consisting of the circuits listed below,
performs down-port controls under supervision of the HUB re-
peater state operation.
•Down-port sequencer circuit
•Down-port state change detect circuit
Rev.2.00 Oct 15, 2006 page 59 of 130
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
USB Down-port Peripheral Circuit Setting
The USB down-port peripheral circuits can be set with the down-
stream port control register (address 0FF916). Figures 89 and 90
show the circuit block diagrams.
Low
Speed
PCON11
PCON10
27 Ω
Full
Speed
D1+
PCON11
PCON11
PCON10
15 kΩ
PCON10
+
-
HUB Module
PCON11
PCON11
PCON10
27 Ω
D1-
Full
Speed
PCON11
PCON10
15 kΩ
Low
Speed
PCON11
PCON10
Fig. 89 Block diagram of USB down-port peripheral circuits (D1+, D1-)
Low
Speed
PCON21
PCON20
27 Ω
Full
Speed
D2+
PCON21
PCON21
15 kΩ
PCON20
PCON20
+
-
HUB Module
PCON21
PCON21
PCON20
D2-
27 Ω
Full
Speed
PCON21
PCON20
15 kΩ
Low
Speed
PCON21
PCON20
Fig. 90 Block diagram of USB down-port peripheral circuits (D2+, D2-)
Rev.2.00 Oct 15, 2006 page 60 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
HUB Interrupt Function
The HUB function control circuit has one interrupt request consist-
ing of 10 interrupt sources each of which can be determined
through the interrupt source register. Table 8 shows the HUB inter-
rupt sources.
Table 8 HUB interrupt sources
Interrupt request bit
HUB interrupt bit
Interrupt source
(IREQ2: Address 003D16
)
(HUBIREQ: Address 002916)
USB HUB
DP1
At HUB down-port 1 state change detected:
•Disconnected state detected
•Connected state detected
•Port error state detected
•Resume signal detected
•Bus state change detected
At HUB down-port 2 state change detected:
•Disconnected state detected
•Connected state detected
DP2
•Port error state detected
•Resume signal detected
•Bus state change detected
[DPXREG1]
[HUBIREQ]
[HUBICON]
[DP1REQ]
PTDIS1
PTCON1
PTERR1
PTRSM1
PTCHG1
USB HUB
interrupt request
DP1E
DP1
[DP2REQ]
PTDIS2
PTCON2
PTERR2
PTRSM2
PTCHG2
DP2E
DP2
Fig. 91 USB HUB interrupt control
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
HUB Register List
The HUB register list is shown below.
USB SFR
Register Name
SYMBOL
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
HRWUE
HRWU
002816
002916
002A16
002B16
002C16
002D16
HUB interrupt source enable register
HUB interrupt source register
HUB downstream port index register
HUB port field register 1
HUBICON
DP2E
DP2
DP1E
DP1
HUBIREQ
HUBINDEX
DPXREG1
DPXREG2
DPXREG3
DPIDX
HUB port field register 2
HUB port field register 3
(1) HUB port 1
002B16
002C16
002D16
DP1 interrupt source register
DP1 control register
DP1REQ
DP1CON
DP1STS
PTCHG1
PTRSM1
PTERR1
PTCON1
PTDIS1
DSLSPD1
DSLSPD2
DSRMOD1
DSRMOD2
DSRSMO1
DSRSMO2
DSRSTO1
DSDETE1
DSSUSP1
DSPTEN1
D1PLUS
DSCONN1
D1MINUS
DP1 status register
(2) HUB port 2
002B16
002C16
002D16
DP2 interrupt source register
DP2 control register
DP2REQ
DP2CON
DP2STS
PTCHG2
PTRSM2
PTERR2
PTCON2
PTDIS2
DSRSTO2
DSDETE2
DSSUSP2
DSPTEN2
D2PLUS
DSCONN2
D2MINUS
DP2 status register
PCON2[1:0]
PCON1[1:0]
0FF916
Downstream port control register
DPCTL
: Not used
Fig. 92 HUB related registers
Rev.2.00 Oct 15, 2006 page 62 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
HUB Related Registers
The HUB related registers are shown below.
b0
b7
0
0
0
0
0
HUB interrupt source enable register (HUBICON) [address 002816
]
At reset
R W
Bit symbol
DP1E
Function
Bit name
H/W S/W
HUB downstream port 1 interrupt 0 : Interrupt disabled
enable bit
HUB downstream port 2 interrupt 0 : Interrupt disabled
O O
O O
O O
O O
0
0
–
0
–
–
–
–
1 : Interrupt enabled
DP2E
enable bit
Not used
1 : Interrupt enabled
b6:b2
Write “0” when writing.
“0” is read when reading.
0 : Disabled
HUB upstream port remote-
wakeup output enable bit
HRWUE
1 : Enabled
–: State remaining
Fig. 93 Structure of HUB interrupt source enable register
b0
b7
0
0
0
0
0
HUB interrupt source register (HUBIREQ) [address 002916
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
DP1
DP2
0
–
This bit is set to “1” when any one of DP1 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing DP1 interrupt
source register to “0016”.
HUB downstream port 1
interrupt bit
O ꢀ
Writing to this bit causes no state change.
This bit is set to “1” when any one of DP2 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing DP2 interrupt
source register to “0016”.
0
–
HUB downstream port 1
interrupt bit
O ꢀ
Writing to this bit causes no state change.
Write “0” when writing.
b6:b2
–
–
–
Not used
O O
O O
“0” is read when reading.
HRWU
0
0 : Remote-wakeup being not output
HUB upstream port remote
-wakeup output enable bit
1 : Remote-wakeup being output
This bit change is not for a interrupt source.
When detecting 2.5 µs or more of K-signal on a
downstream port in Hub-suspended state, K-signal is
output on from
a upstream port and this bit is
simultaneously set to “1”.
“0” can be set by software, but “1” cannot be set.
–: State remaining
Fig. 94 Structure of HUB interrupt source register
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
0
0
0
0
0
0
HUB downstream port index register (HUBINDEX) [address 002A16
]
At reset
R W
Bit symbol
DPIDX
Function
Bit name
H/W S/W
HUB downstream port index bit 0 : HUB downstream port 1
1 : HUB downstream port 2
0
–
O O
O O
b7:b1
Not used
Write “0” when writing.
–
–
“0” is read when reading.
–: State remaining
Fig. 95 Structure of HUB downstream port index register
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(1) Downstream port 1
b0
b7
0
DP1 interrupt source register (DP1REQ) [address 002B16
]
0
0
At reset
R W
H/W S/W
Bit symbol
Bit name
Function
Downstream port 1 disconnect
detection interrupt bit
PTDIS1
0
–
0: No interrupt request issued
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-disconnect
state (2.5 µs or more of SE0) on a downstream port 1 in
DSCONN1 = “1”.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 1 connect
detection interrupt bit
PTCON1
0
–
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-connect
state (2.5 µs or more of J- or K- state) on a downstream
port 1 in DSCONN1 = “0”.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 1 port error
interrupt bit
PTERR1
PTRSM1
0
0
–
–
O O
O O
1: Interrupt request issued
This bit is set to “1” when an error occurs on a
downstream port 1.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 1 resume
interrupt bit
1: Interrupt request issued
This bit is set to “1” when detecting a resume signal
on a downstream port 1 in the condition of HUB
suspended or port suspended state.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 1 bus-change
detection interrupt bit
PTCHG1
0
–
–
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-change of a
downstream port 1 in the condition of HUB suspended
state. It is also “1” in the internal clock halted.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
Not used
b7:b5
–
O O
“0” is read when reading.
–: State remaining
Fig. 96 Structure of DP1 interrupt source register
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
DP1 control register (DP1CON) [address 002C16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
–
Downstream port 1 connect bit
Downstream port 1 enable bit
0
O O
O O
0 : Disconnect ; PTCON1 interrupt enabled
1 : Connect ; PTDIS1 interrupt enabled
0 : Downstream port 1 disabled
DSCONN1
DSPTEN1
–
0
1 : Downstream port 1 enabled ; This bit is cleared when
an interrupt of PTDIS1 or PTERR1 is generated.
0 : No port suspended
–
–
Downstream port 1 suspend bit
0
0
O O
O O
DSSUSP1
DSDETE1
1 : Port suspended; This bit is cleared when an interrupt
of PTDIS1 or PTRSM1 is generated.
0 : Connect/disconnect-state detection disabled ; PTCON1
and PTDIS1 interrupts disabled
Downstream port 1 connect-
state detection enable bit
1 : Connect/disconnect-state detection enabled ; This bit
is cleared when an interrupt of PTCON1, PTDIS1 or
PTERR1 is generated.
–
–
Downstream port 1 SE0 signal
transmit bit
0
0
O O
O O
0 : Being not output
DSRSTO1
DSRSMO1
1 : SE0 signal being output
Downstream port 1 resume
signal transmit bit
0 : Being not output
1 : K-signal being output ; When writing “0”, a low-speed
EOP is output and then a transition to being not
output occurs.
–
–
Downstream port 1 bus-state
read mode control bit
0
0
O O
O O
0 : Mode where a downstream port 1 bus-state is read,
using RD signal
DSRMOD1
DSLSPD1
1 : Mode where a downstream port 1 bus-state is read,
using EOF2 signal (internal signal)
0 : Full-speed mode (12MHz)
Downstream port 1 USB transfer
1 : Low-speed mode (1.5 MHz)
–: State remaining
Fig. 97 Structure of DP1 control register
b0
b7
0
DP1 status register (DP1STS) [address 002D16
]
0
0
0
0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
In-
In-
D1MINUS
D1PLUS
b7:b2
O ꢀ
O ꢀ
O O
D1- signal bit
D1+ signal bit
Not used
In DSRMOD1 = “0”, a downstream port 1 bus-state is
read, using RD signal.
definite definite
In DSRMOD1 = “1”, a downstream port 1 bus-state is
read, using EOF2 signal (internal signal).
In DSRMOD1 = “0”, a downstream port 1 bus-state is
read, using RD signal.
In-
In-
definite definite
In DSRMOD1 = “1”, a downstream port 1 bus-state is
read, using EOF2 signal (internal signal).
Write “0” when writing.
–
–
“0” is read when reading.
–: State remaining
Fig. 98 Structure of DP1 status register
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(2) Downstream port 2
b0
b7
0
DP2 interrupt source register (DP2REQ) [address 002B16
]
0
0
At reset
R W
H/W S/W
Bit symbol
Bit name
Function
Downstream port 2 disconnect
detection interrupt bit
PTDIS2
0
–
0: No interrupt request issued
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-disconnect
state (2.5 µs or more of SE0) on a downstream port 2 in
DSCONN2 = “1”.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 2 connect
detection interrupt bit
PTCON2
0
–
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-connect
state (2.5 µs or more of J- or K- state) on a downstream
port 2 in DSCONN2 = “0”.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 2 port error
interrupt bit
PTERR2
PTRSM2
0
0
–
–
O O
O O
1: Interrupt request issued
This bit is set to “1” when an error occurs on a
downstream port 2.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 2 resume
interrupt bit
1: Interrupt request issued
This bit is set to “1” when detecting a resume signal
on a downstream port 2 in the condition of HUB
suspended or port suspended state.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 2 bus-change
detection interrupt bit
PTCHG2
0
–
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-change of a
downstream port 2 in the condition of HUB suspended
state. It is also “1” in the internal clock halted.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
Not used
b7:b5
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 99 Structure of DP2 interrupt source register
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
DP2 control register (DP2CON) [address 002C16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
–
Downstream port 2 connect bit
Downstream port 2 enable bit
0
O O
O O
0 : Disconnect ; PTCON2 interrupt enabled
1 : Connect ; PTDIS2 interrupt enabled
0 : Downstream port 2 disabled
DSCONN2
DSPTEN2
–
0
1 : Downstream port 2 enabled ; This bit is cleared when
an interrupt of PTDIS2 or PTERR2 is generated.
0 : No port suspended
–
–
Downstream port 2 suspend bit
0
0
O O
O O
DSSUSP2
DSDETE2
1 : Port suspended; This bit is cleared when an interrupt
of PTDIS2 or PTRSM2 is generated.
0 : Connect-state detection disabled ; PTCON2 and PTDIS2
interrupts disabled
Downstream port 2 connect-
state detection enable bit
1 : Connect-state detection enabled ; This bit is cleared when an
interrupt of PTCON2, PTDIS2 or PTERR2 is generated.
0 : Being not output
–
–
Downstream port 2 SE0 signal
transmit bit
0
0
O O
O O
DSRSTO2
DSRSMO2
1 : SE0 signal being output
Downstream port 2 resume
signal transmit bit
0 : Being not output
1 : K-signal being output ; When writing “0”, a low-speed
EOP is output and then a transition to being not
output occurs.
–
–
Downstream port 2 bus-state
read mode control bit
0
0
O O
O O
0 : Mode where a downstream port 2 bus-state is read,
using RD signal
DSRMOD2
DSLSPD2
1 : Mode where a downstream port 2 bus-state is read,
using EOF2 signal (internal signal)
0 : Full-speed mode (12MHz)
Downstream port 2 USB transfer
speed select bit
1 : Low-speed mode (1.5 MHz)
–: State remaining
Fig. 100 Structure of DP2 control register
b0
b7
0
DP2 status register (DP2STS) [address 002D16
]
0
0
0
0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
In-
In-
D2MINUS
D2PLUS
b7:b2
O ꢀ
O ꢀ
O O
D2- signal bit
D2+ signal bit
Not used
In DSRMOD2 = “0”, a downstream port 2 bus-state is
read, using RD signal.
definite definite
In DSRMOD2 = “1”, a downstream port 2 bus-state is
read, using EOF2 signal (internal signal).
In DSRMOD2 = “0”, a downstream port 2 bus-state is
read, using RD signal.
In-
In-
definite definite
In DSRMOD2 = “1”, a downstream port 2 bus-state is
read, using EOF2 signal (internal signal).
Write “0” when writing.
–
–
“0” is read when reading.
–: State remaining
Fig. 101 Structure of DP2 status register
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
Downstream port control register (DPCTL) [address 0FF916
]
0
0
0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PCON1
[1:0]
Downstream port 1 function
select bit
b1b0
–
–
–
0
0
–
O O
O O
O O
0 0 : USB port (D1-, D1+) OFF,
USB difference amplifier OFF
0 1 : USB exclusive input port (D1-, D1+),
USB difference amplifier OFF
1 0 : Full-speed port (D1-, D1+),
USB difference amplifier ON
1 1 : Low-speed port (D1-, D1+),
USB difference amplifier ON
b3b2
PCON2
[1:0]
Downstream port 2 function
select bit
0 0 : USB port (D2-, D2+) OFF,
USB difference amplifier OFF
0 1 : USB exclusive input port (D2-, D2+),
USB difference amplifier OFF
1 0 : Full-speed port (D2-, D2+),
USB difference amplifier ON
1 1 : Low-speed port (D2-, D2+),
USB difference amplifier ON
Write “0” when writing.
b7:b4
Not used
“0” is read when reading.
–: State remaining
Fig. 102 Structure of Downstream port control register
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
EXTERNAL BUS INTERFACE (EXB)
The external bus interface (EXB) controls the data transfer be-
memory (multichannel RAM). The external bus interface is shown
below.
tween the external MCU and the 38K2 group’s CPU or its
38K2 group
CPU
Program ROM
Peripheral functions
CPU channel
[Interrupt type]
USB bus
External bus interface
(EXB)
Multichannel RAM
USB
(USB host)
Memory channel
[Direct RAM access type]
Fig. 103 External bus interface
ꢀCPU channel
ꢀData transfer of memory channel
It is a data transfer course by the interrupt processing between the
external MCU and the 38K2 group’s CPU.
When the burst mode is selected with the burst bit of the memory
channel operation mode register, data transfer can be carried out
at the highest speed. After the external bus interface detects a rise
of external read signal/write signal and synchronizes it with the in-
ternal clock φ, it completes the data transfer between the transmit/
receive buffer and the multichannel RAM in two clocks.
However, the waiting time of two clocks at a maximum is gener-
ated to access the multichannel RAM in USB being operating
because the USB has priority to access.
ꢀMemory channel
It is a data transfer course by direct RAM access of the memory
channel controller between the external MCU and the 38K2
group’s memory (multichannel RAM)
Therefore, it is necessary to set up the access interval which fills
the following timing with the external MCU bus side.
In φ = 8 MHz, data transfer at about 2 Mbytes/second is possible
at a maximum. When there is access simultaneously from the
USB, it is about 1.3 Mbytes/second.
In φ = 6 MHz, data transfer at about 1.5 Mbytes/second is possible
at a maximum. When there is access simultaneously from the
USB, it is about 1 Mbytes/second.
Address
CS, RD, WR,
DMA acknowledge
Access cycle time from externals:
•3 clocks or more of φ + Signal delay time + Data setup
time of external MCU in USB inactive
•5 clocks or more of φ + Signal delay time + Data setup
time of external MCU in USB active
Fig. 104 Data transfer timing of memory channel
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
EXB Pin Assignment
The external bus interface (EXB) pins are shown bellow.
The 38K2 group can transmit/receive a data to/from an external
MCU, using the following signals:
•Control input signal ................ 4 (ExCS, ExA0, ExRD, ExWR)
•Data input/output pin .............. 8 (DQ0 to DQ7)
•Interrupt output signal ............ 1 (ExINT)
Additionally, the DMA interface signal and the buffer status read
select signal of 38K2 group can be set up per one by the program.
•Control input signal ................ 3 (ExTC, ExDACK, ExRD, ExA1)
•Interrupt output signal ............ 1 (ExDREQ)
38K2 group
External bus interface
(EXB)
External pins
External chip select
External address
External read
P34
P37
P36
P35
P10
P33
/ExCS [ L ]
CPU
/ExA0 [address]
/ExRD [ L ]
External write
/ExWR [ L ]
8
External data
/DQ
0/AN0—P17/DQ7/AN7 [data]
External interrupt
/ExINT [ L ]
DMA request
Terminal count
P40
P42
P41
/ExDREQ/RxD [ L ]
/ExTC/SCLK [ L ]
DMA acknowledge
/ExDACK/TxD [ L ]
Multichannel RAM
Status read select
P43/ExA
1/SRDY [ H ]
: Functions as normal ports
just after reset.
Fig. 105 External bus interface (EXB) pin assignment
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
EXB Block Diagram
The block diagram of external bus interface (EXB) is shown below.
The external bus interface (EXB) consists of:
(1) External I/O interface part
(2) CPU interface part
(3) Internal memory interface part
(4) Transmit/Receive data buffer part
External I/O interface
Configuration
CPU interface
signal
Index register
External I/O
configuration
register
EXB interrupt
Cch_WR
source enable register
External MCU bus
Cch_RD
P34/ExCS
CPU channel
controller
Decoder data selector
TxB_RDY
RxB_RDY
P3
7
/ExA0
/ExRD
Memory channel
control
Memory channel
status
P36
P35/ExWR
Mch_RD
Mch_WR
Internal memory
Mch_TC
interface
P4
1
/ExDACK/TxD
mRX_enb
mTX_enb
Memory channel
operation mode register
P4
2
/ExTC/SCLK
/ExA1/SRDY
P4
3
Memory address
Memory address
counter
P33/ExINT
End address register
Mch_req
FIFO_stt
Request acknowledge
P40/ExDREQ/RxD
Memory channel
controller
MRDsel
Memory channel
transmit buffer control
stt_sel
Buf_WR
Transmit/Receive data
buffer
ExOE
Memory read data
Memory write data
P10/DQ
0/AN0–
Transmit buffer register
P17/DQ
7/AN
7
Receive buffer register
: Functions as normal ports just after reset.
Fig. 106 Block diagram of external bus interface (EXB)
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(1) External I/O Interface Part
(2) CPU Interface Part
The external I/O interface part consists of a command decoder
and an output selector. A command decoder generates the follow-
ing signals to each unit.
The CPU interface part consists of the decoder/data selector of
the CPU channel, the CPU write register and CPU channel con-
troller
ꢀCPU interface part
ꢀDecoder/data selector of CPU channel
•CPU channel read (Cch_RD)
•CPU channel write (Cch_WR)
A write operation to the CPU register is performed by generating a
write signal for each register with an address decode signal and a
write signal.
ꢀInternal memory interface part
•Memory channel read (Mch_RD)
•Memory channel write (Mch_WR)
•Memory channel terminal count (Mch_TC)
A read operation from the CPU register is performed by generat-
ing an output enable signal of the internal data bus with an module
select signal and a read signal and generating a select signal for
each register with an address decode signal.
ꢀTransmit/receive data buffer part
•Buffer write (Buf_WR)
ꢀCPU write register
There are three CPU write registers as follows:
•EXB interrupt source enable register
•Index register
ꢀExternal I/O interface part
•Status selection (stt_sel)
•Output enable (ExOE)
•External I/O configuration register
The EXB interrupt source register is a read-only register.
A status signal of the CPU channel controller and a status signal
of the memory channel controller in the internal memory interface
part are generated.
Access to the CPU channel can be controlled only by setup of
external signals.
Access to the memory channel can be controlled by the value of
the external I/O configuration register and the state (mRX_enb,
mTX_enb signals) of the internal memory interface part.
ꢀCPU channel controller
The CPU channel controller generates the following signals, using
bits 0 and 1 (RXB_ENB, TXB_ENB) of EXB interrupt source en-
able register.
The output selector has the function which selects from the state
of CPU channel (TxB_RDY and RxD_RDY) and the state of
memory channel (Mch_req) as the signal assigned to P33/
ExINT pin and P40/ExDREQ/RxD pin.
•Memory channel transmitting buffer control signal (MRD_sel),
generated in the internal memory interface part
•CPU channel command signal (Cch_RD, Cch_WR), generated
in the external I/O interface part
•Signals RxB_RDY/RxB_full and TxB_RDY/TxB_empty, gener-
ated with read/write signals from the CPU channel
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38K2 Group
FUNCTIONAL DESCRIPTION
(3) Internal Memory Interface Part
The internal memory interface part consists of the CPU register
and the memory channel controller.
(5) External Pin
The external bus interface has the following pins to connect with
an external MCU bus.
•Chip select ........................... P34/ExCS
•Address ................................ P37/ExA0
•Data...................................... P10/DQ0/AN0 to P17/DQ7/AN7
•Read .................................... P36/ExRD
•Write ..................................... P35/ExWR
•Interrupt request .................. P33/ExINT
ꢀCPU register
The CPU register consists of the follows:
•Memory channel operation mode register
•Memory address counter
•End address register
The CPU can set the beginning address into the memory address
counter when the memory channel operation enable bit
(MC_ENB) of EXB interrupt source enable register is “0”. When
this bit is “1”, the write operation from the CPU is invalid and each
access from the external bus causes count-up operation.
It also has the following pins to connect with an external DMAC.
Each pin can be programmed for an ordinary port function or a
DMA interface pin function.
•DMA request ........................ P40/ExDREQ/RxD
•DMA acknowledgment ......... P41/ExDACK/TxD
•Terminal count ..................... P42/ExTC/SCLK
ꢀMemory channel controller
The CPU register consists of the follows:
•Main sequencer
It also has the status read select pin (P43/ExA1/SRDY pin) to con-
firm a ready status of the data buffer from an external MCU bus
This pin functions as a port just after reset. The status read select
function can be set by a program.
•Internal memory request signal generating circuit
•External memory channel request signal generating circuit
•Address end detection circuit
•Terminal end input processing circuit
•Status read select ................ P43/ExA1/SRDY
(4) Transmit/Receive Data Buffer Part
The transmit/receive data buffer part consists of the 8-bit transmit
buffer register (TXBUF) and the 8-bit receive buffer register
(RXBUF).
ꢀCPU channel: Communication with 38K2 group CPU
When a read/write operation is performed from an external MCU
bus in address signal ExA0 = “H”, the interrupt is generated and
the 38K2 group CPU can confirm its access. The 38K2 group CPU
judges the interrupt source and it starts a data transmission/recep-
tion with an external MCU bus.
Both CPU channel and memory channel use the same transmit
buffer register/receive buffer register to transfer a data to an exter-
nal MCU bus.
ꢀMemory channel: Communication with 38K2 group memory
multichannel RAM
When a read/write operation is performed from an external MCU
bus in address signal ExA0 = “L”, access to the multichannel RAM
is performed. Then an address of the multichannel RAM is made
by the external bus interface and it is increased at each access
completion. Consequently, FIFO access is performed.
Even if a read/write operation is performed in DACK = “L” instead
of ExCS = “L” and ExA0 = “L”, FIFO access to the multichannel
RAM is performed.
The beginning address and the end address must be set by the
CPU in advance.
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38K2 Group
FUNCTIONAL DESCRIPTION
ꢀP33/ExINT pin
ꢀP42/ExTC/SCLK pin
Any one of the following signals for this pin can be selected:
•TxB_RDY (transmit buffer ready) output
•RxB_RDY (receive buffer ready) output
•Mch_req (memory channel request) output
This pin is a port at the initial state. The terminal count signal can
be set by program.
If the terminal count signal is set at one bus cycle while a memory
channel operation write is being performed, the 38K2 group con-
firms that its bus cycle is the write cycle of the last data and sets
the memory channel status bits to “112”, and the interrupt is gener-
ated and the memory channel operation ends even if the memory
address counter has not reached the end address.
The CPU can obtain the last address where the data is written by
reading out the value of memory address counter. (See Figure
126.)
Either TxB_RDY or RxB_RDY is normally selected. The memory
channel request is for an access request signal to the memory
channel.
In a small system, a data transfer processing to the internal
memory is performed in the interrupt routine. According to that
situation, the 38K2 group has the function automatically to switch
an interrupt factor attached on the interrupt pin by program.
ꢀP40/ExDREQ/RxD pin
This pin is a port at the initial state. Which signal can be set by
program.
•RxB_RDY (receive buffer ready) output
•Mch_req (memory channel request) output
Mch_req of DMAC is normally selected. The output method of the
memory channel request signal depends on the burst bit (BURST)
of memory channel operation mode register. When the burst bit is
“0”, this signal is periodically output at each 1-byte transfer. (See
Figures 124 and 127.)
When the burst bit is “1”, this signal is continuously output while
the memory address counter is counting from the beginning ad-
dress to the end address (See Figures 125 and 128.)
ꢀP41/ExDACK/TxD pin
This pin is a port at the initial state. The DMA acknowledge signal
can be set by program.
The DMA acknowledge signal DACK = “L” is the same state as
that of CS = “L” and A0 = “L”. Access to multichannel RAM is
started by a rise of read signal or write signal which is set during
this term.
Note: If the DMA acknowledge signal and the chip select signal
are simultaneously active (DACK = “L” and CS = “L”), also
set the address signal A0 to “L”. If A0 is “H”, the memory
channel and the CPU channel are activated simultaneously
and it might cause some error.
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38K2 Group
FUNCTIONAL DESCRIPTION
EXB Register List
The EXB register list is shown below.
EXB SFR
Address
SYMBOL
Register Name
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
003016
003116
EXB interrupt source enable register
EXB interrupt source register
TXB_ENB
RXB_EMB
RXB_FULL
EXBICON
MC_ENB
MC_STS[1:0]
TXB_EMPTY
EXBIREQ
003316
003416
003516
EXB index register
0
0
0
0
0
INDEX[2:0]
EXBINDEX
EXBREG1
EXBREG2
LOW_WIN[7:0]
HIGH_WIN[7:0]
Register window 1 (low)
Register window 2 (high)
:
Not used
0 : “0” fixed
Fig. 107 EXB related registers (1)
•EXB interrupt source enable register
•EXB index register/Register windows 1, 2
This register enables/disables access from an external bus and an
internal interrupt.
The accessible register is switched by treating addresses 003416
and 003516 as a register window depending on the value of EXB
index register at address 003316.
•EXB interrupt source register
This register indicates the state of CPU channel’s transmit/receive
buffer register and the memory channel. The same value can be
read out from the external MCU bus by using the buffer status
read select signal (A1 pin = “H”).
EXB SFR
low
high
Index
0016
Register Name
SYMBOL
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
External I/O configu-
ration register
low
EXBCFGL
EXBCFGH
A1_CTR
INT_CTR[2:0]
EXB_CTR
high
TC_CTR
DAK_CTR[1:0]
DRQ_CTR[1:0]
At CPU read : RXBUF[7:0]
At CPU write : TXBUF[7:0]
0116
0216
0316
0416
low Transmit/Receive
buffer register
RXBUF/TXBUF
—
high
low
BURST
MC_DIR[1:0]
Memory channel ope-
ration mode register
MCHMOD
—
high
low Memory address
counter
MEMADL
MEMADH
ENDADL
ENDADH
IM_A[7:0]
0
0
0
0
0
0
0
0
0
0
high
IM_A[10:8]
low
END_A[7:0]
End address
register
high
END_A[10:8]
: Not used
0 : “0” fixed
Fig. 108 EXB related registers (2)
•External I/O configuration register
•Memory address counter
This register selects the function of each pin.
This is a counter to set the beginning address which FIFO ac-
cesses. This register is increased by access from the external
MCU bus.
•Transmit/Receive buffer register
This register consists of the receive buffer register (RXBUF) and
the transmit buffer register (TXBUF)
•End address register
This register is to set the end address which FIFO accesses.
•Memory channel operation mode register
This register sets the operation mode of the memory channel.
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38K2 Group
FUNCTIONAL DESCRIPTION
EXB Related Registers
The EXB related registers are shown below.
b0
b7
0
EXB interrupt source enable register (EXBICON) [address 003016
]
0
0
0
0
(Note)
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
RXB_ENB CPU channel receive enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Receive buffer full interrupt enabled)
0
0
0
–
–
–
O O
O O
O O
TXB_ENB
CPU channel transmit enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Transmit buffer empty interrupt enabled)
MC_ENB
Memory channel operation
enable bit
0 : Operation disabled (Memory channel operation end
interrupt disabled)
1 : Operation enabled (Memory channel operation end
interrupt disabled)
b7:b3
Not used
Write “0” when writing.
–
–
O O
“0” is read when reading.
–: State remaining
Note: Do not set each bit simultaneously.
Fig. 109 Structure of EXB interrupt source enable register
b0
b7
0
0
0
0
EXB interrupt source register (EXBIREQ) [address 003116] (Note 1)
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0 : Receive buffer empty
1 : Receive buffer full
0 : Transmit buffer full
1 : Transmit buffer empty
b3b2
RXB_FULL Receive buffer full bit
0
0
0
0
(Note 3)
0
O –
O –
O –
TXB_EMPTY Transmit buffer empty bit
(Note 4)
MC_STS
[1:0]
Memory channel status bits
0
0 0 : Memory channel operation stopped
0 1 : Memory channel being operating;
No external access
(Note 2)
1 0 : Memory channel being operating;
External accessing
1 1 : Memory channel operation end; Memory
channel operation end interrupt generated
Write “0” when writing.
b7:b4
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Notes 1: When the the ExA1 pin control bit of external I/O configuration register is “1”, the external MCU bus can read this
register contents by setting the ExA1 pin to “H”.
2: The memory channel status bits indicate the status of memory channel. In MC_ENB = “0” these bits are always
“00
2”. When the memory channel operation ends, these bits are set to “112” and the memory channel operation
end interrupt is generated.
These bits can be read out during operation, so that it will show that whether the external MCU bus is accessing
or not.
3: This bit is cleared to “0” when reading the transmit/receive buffer register in the CPU channel receive enable bit =
“1” or when the CPU channel receive enable bit is “0”.
4: This bit is cleared to “0” when writing to the transmit/receive buffer register in the CPU channel transmit enable bit
= “1” or when the CPU channel transmit enable bit is “0”.
Fig. 110 Structure of EXB interrupt source register
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38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
EXB index register (EXBINDEX) [address 003316
]
0
0
0
0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
INDEX
[2:0]
The accessible register, using the register window,
depends on these index bits contents as follows:
b2b1b0
0
–
Index bits
O O
0 0 0 : External I/O configuration register
0 0 1 : Transmit/Receive buffer register
0 1 0 : Memory channel operation mode register
0 1 1 : Memory address counter
1 0 0 : End address register
1 0 1 : Do not set.
1 1 0 : Do not set.
1 1 1 : Do not set.
b7:b3
Write “0” when writing.
–
–
Not used
O O
“0” is read when reading.
–: State remaining
Fig. 111 Structure of EXB index register
b0
b7
Register window 1 (EXBREG1) [address 003416
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
LOW_WIN
[7:0]
The accessible register, using this register window, In-
In-
–
O O
depends on the EXB index register contents as definite definite
follows:
Index value
“0016
“0116
“0216
“0316
“0416
”
”
”
”
”
: External I/O configuration register
: Transmit/Receive buffer register
: Memory channel operation mode register
: Memory address counter
: End address register
Fig. 112 Structure of Register window 1
b0
b7
Register window 2 (EXBREG2) [address 003516
]
At reset
H/W S/W
R W
O O
Bit symbol
Bit name
Function
HIGH_WIN
[7:0]
The accessible register, using this register window, In-
In-
–
depends on the EXB index register contents as definite definite
follows:
Index value
“0016”
“0116”
“0216”
“0316”
“0416”
: External I/O configuration register
: Transmit/Receive buffer register
: Memory channel operation mode register
: Memory address counter
: End address register
Fig. 113 Structure of Register window 2
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
Index = 0016 : External I/O configuration register (EXBCFGL) [address 003416
]
0
0
0
At reset
H/W S/W
R W
O O
Bit symbol
EXB_CTR
Function
Bit name
0 : Port
EXB pin control bit
0
0
–
–
1 : EXB function pin
Selects a signal of P3
(Pins P1
0 to P17, P30 to P34)
3
/ExINT pin.
INT_CTR
[2:0]
P3 /ExINT pin control bit
3
O O
ON/OFF is programmed by each bit. An output logical
sum of P3 /ExINT pins set for ON are performed and it
3
is output as an “L” active signal.
b3b2b1
0 0 1 : RxB_RDY (RxBuf ready) output
0 1 0 : TxB_RDY (TxBuf ready) output
1 0 0 : Mch_req (Memory channel request) output
Others : Do not set.
0 : Port
A1_CTR
b7:b5
P4
3/ExA1 pin control bit
0
–
–
O O
O O
1 : A1 input (used to read status)
Write “0” when writing.
Not used
–
“0” is read when reading.
–: State remaining
Fig. 114 Index00[low]; Structure of External I/O configuration register
b0
b7
0
Index = 0016 : External I/O configuration register (EXBCFGH) [address 003516
]
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
b1b0
DRQ_CTR P4
0/ExDREQ/RxD pin control
0
–
O O
bit
0 0 : Port
0 1 : Do not set.
[1:0]
1 0 : ExDREQ function; RxB_RDY (RxBuf ready) output
1 1 : ExDREQ function; Mch_req (Memory channel
request) output
Specifies P41/ExDACK/TxD pin function.
DAK_CTR
[1:0]
P4
1/ExDACK/TxD pin control
0
–
O O
Selects which mode; requiring read or write signal, or
not requiring it for use of DMA acknowledge function.
bit
b3b2
0 0 : Port
0 1 : Do not set.
1 0 : ExDACK function; DMA acknowledge input
(Mode for read and write signals used together)
1 1 :ExDACK function; DMA acknowledge input
(Mode for read and write signals not required)
0 : Port
TC_CTR
b7:b5
P4
2
/ExTC/SCLK pin control bit
0
–
–
O O
O O
1 : ExTC (terminal count) input
Write “0” when writing.
Not used
–
“0” is read when reading.
–: State remaining
Fig. 115 Index00[high]; Structure of External I/O configuration register
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38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
Index =0116 : Transmit/Receive buffer register (RXBUF/TXBUF) [address 003416
]
At reset
H/W S/W
R W
O O
Bit symbol
Function
Bit name
RXBUF/
TXBUF
–
0
–
The data received from an external bus is written here
at the rise timing of external write signal.
The data transmitted to an external bus is written here
at the timing of internal CPU write or memory write.
The receive buffer register (RXBUF) contents can be read out by reading to this address with the CPU. The data which the
CPU has written to this address is stored in the transmit buffer register (TXBUF).
However, do not perform write operation with the CPU to this address if the memory channel direction control bits of
memory channel operation mode register is “102” (transmit mode) and the memory channel status bits of EXB interrupt
source register are “01 ” or “10 ” (memory channel being operating).
2
2
Fig. 116 Index01[low]; Structure of Transmit/Receive buffer register
b0
b7
0
Index =0216 : Memory channel operation mode register (MCHMOD) [address 003416
]
0
0
0
0
At reset
H/W S/W
R W
O O
Bit symbol
Function
Bit name
MC_DIR
[1:0]
Memory channel direction
control bit
b1b0
0
–
0 0 : Operation disabled
0 1 : Receive mode
1 0 : Transmit mode
1 1 : Do not set.
BURST
b7:b3
Burst bit
Not used
0 : Cycle mode (each byte transfer according to
assertion or negation)
0
–
–
O O
O O
1 : Burst mode (continuous transfer till the terminal
count)
Write “0” when writing.
–
“0” is read when reading.
–: State remaining
Fig. 117 Index02[low]; Structure of Memory channel operation mode register
b0
b7
Index = 0316 : Memory address counter (MEMADL) [address 003416
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
IM_A
[7:0]
Register to set the low-order address of memory
channel operation beginning.
0
–
–
This contents are increased each time one memory
access ends.
Fig. 118 Index03[low]; Structure of Memory address counter
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38K2 Group
FUNCTIONAL DESCRIPTION
b0
b7
Index = 0316 : Memory address counter (MEMADH) [address 003516
]
0
0
0
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
IM_A
[10:8]
Register to set the high-order address of memory
channel operation start.
0
–
–
This contents are increased each time one memory
access ends.
O O
b7:b3
Write “0” when writing.
–
–
Not used
“0” is read when reading.
–: State remaining
Fig. 119 Index03[high]; Structure of Memory address counter
b0
b7
Index = 0416 : End address register (ENDADL) [address 003416
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
END_A
[7:0]
Register to set the low-order address of memory
channel operation end.
0
–
–
–: State remaining
Fig. 120 Index04[low]; Structure of End address register
b0
b7
0
Index = 0416 : End address register (ENDADH) [address 003516
]
0
0
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
O O
END_A
[10:8]
Register to set the high-order address of memory
channel operation end.
0
–
–
b7:b3
Write “0” when writing.
–
–
Not used
“0” is read when reading.
–: State remaining
Fig. 121 Index04[high]; Structure of End address register
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38K2 Group
FUNCTIONAL DESCRIPTION
EXB Operation Timing Diagram
(1) CPU Channel Receiving Operation
CPU channel receiving operation is shown bellow.
ꢀ
ꢀ
ꢀ
ꢀ
Address ExA0
Chip select ExCS
Read ExRD
A0 = “1”
A0 = “1”
CS = “0”
CS = “0”
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
Interrupt request ExINT
[RxB_RDY]
RxB_RDY
RxB_RDY
Receive buffer full bit RXB_FULL
Receive buffer RXBUF
#0
#1
Transmit buffer TXBUF
ꢀ
CPU channel receive enable bit
RXB_ENB
Receive buffer read
ꢀ
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P3
3
/ExINT pin control) = 001
2
(RxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
RXB_ENB (CPU channel receive enable) = “1” (Receive buffer full interrupt enabled)
ꢀ
Writing the command for enabling operation makes RXB_RDY assertion and the P33/ExINT pin goes to “L”.
If the CPU channel receive enable bit (RXB_ENB) is “0”, both the receive buffer full bit (RXB_FULL) and the receive buffer ready signal (RxB_RDY) to an
external are inactive.
ꢀ
When a write operation is performed from an external MCU bus in the condition of ExCS = “L” and WxA0 = “H”, it will result in as follows:
• The data is written into the receive buffer (RXBUF)
• Negation of the receive buffer ready signal (RxB_RDY) to an external is made
• The RXB_FULL interrupt is generated.
ꢀ When the CPU reads out the receive buffer (RXBUF) with an interrupt processing program, the receive buffer full bit (RXB_FULL) is cleared to “0”.
Fig. 122 CPU channel receiving operation
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38K2 Group
FUNCTIONAL DESCRIPTION
(2) CPU Channel Transmitting Operation
CPU channel transmitting operation is shown bellow.
ꢀ
ꢀ
ꢀ
ꢀ’
Address ExA0
Chip select ExCS
Read ExRD
A0 = “1”
A0 = “1”
CS = “0”
CS = “0”
ꢀ
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
Interrupt request ExINT
[TxB_RDY]
TxB_RDY
TxB_RDY
Transmit buffer empty bit
TXB_EMPTY
Receive buffer RXBUF
Transmit buffer TXBUF
#0
#1
ꢀ
CPU channel transmit enable bit
TXB_ENB
Transmit data write
ꢀ’
ꢀ
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P33/ExINT pin control) = 0102 (TxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
TXB_ENB (CPU channel transmit enable) = “1” (Transmit buffer empty interrupt enabled)
ꢀ
Writing the command for enabling operation generates TXB_EMPTY interrupt.
If the CPU channel transmit enable bit (TXB_ENB) is “0”, both the transmit buffer empty bit (TXB_EMPTY) and the transmit buffer ready signal (TxB_RDY) to
an external are inactive.
ꢀ
When the CPU writes the data into the transmit buffer (TXBUF) with an interrupt processing program, the transmit buffer empty bit (TXB_EMPTY) is cleared
to “0” and assertion of the transmit buffer ready signal (TxB_RDY) to an external is made.
ꢀ
When a read operation is performed from an external MCU bus in the condition of ExCS = “L” and ExA0 = “H”, it will result in as follows:
• The contents of the transmit buffer (TXBUF) is read out
• The transmit buffer empty bit (TXB_EMPTY) is set to “1”
• Negation of the transmit buffer ready signal (TxB_RDY) to an external is made.
Fig. 123 CPU channel tranmitting operation
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38K2 Group
FUNCTIONAL DESCRIPTION
(3) Memory Channel Receiving Operation (1)-
Cycle Mode
Memory channel receiving operation (1) is shown bellow.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ’
ꢀ’
ꢀ
A0 = “0”
A0 = “0”
Address ExA0
CS = “0”
CS = “0”
Chip select ExCS
DMA acknowledge
ExDACK
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
DMA request
ExDREQ
Mch_req
Mch_req
mWR
mWR
detection
detection
Receive buffer RXBUF
#0
#1
ꢀ
Operation enabled
Main sequencer
0
1
2
3
5
Memory channel operation
end interrupt
Internal memory access
req
req
Memory address
Counter end
010016
010116
010216
Acknowledgment of
internal memory access
ack
ack
ꢀ
ꢀ
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “0” (Cycle mode)
Memory address counter
End address register
(Example) 010016
(Example) 010116
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
ꢀ
ꢀ
ꢀ
In the memory channel receive mode when the command for enabling operation is written, operation starts (main sequencer starts) and assertion of the
memory channel request which synchronized with a rise of φ is made.
When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExWR is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of φ is made.
When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
ꢀ The memory address counter is increased simultaneously at write completion and assertion of the next memory channel request is made.
ꢀ
When the write operation to the end address has been completed, the memory address counter is increased, but assertion of the next memory channel
request is not made and the memory channel operation end interrupt is generated.
Fig. 124 Memory channel receiving operation (1)
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(4) Memory Channel Receiving Operation (2)-
Burst Mode
Memory channel receiving operation (2) is shown bellow.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ’
ꢀ’
ꢀ
ꢀ
Address ExA0
A0 = “x”
A0 = “x”
A0 = “x”
CS = “1”
Dack = “0”
Chip select ExCS
CS = “1”
CS = “1”
Dack = “0”
DMA acknowledge
ExDACK
Dack = “0”
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
#2
Internal clock φ
DMA request
ExDREQ
Mch_req
mWR
mWR
detection
detection
Receive buffer RXBUF
#0
#1
#2
Operation enabled
Main sequencer
ꢀ
0
1
2
3
5
Memory channel operation
end interrupt
Internal memory access
req
req
req
Memory address
Counter end
Burst end
010016
010116
010216
010316
Acknowledgment of
internal memory access
ack
ack
ack
ꢀ
ꢀ
ꢀ
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
End address register
(Example) 010016
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
ꢀ
In the memory channel receive mode when the command for enabling operation is written, assertion of the memory channel request which synchronized
with a rise of φ is made.
ꢀ
When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
ꢀ The memory address counter is increased simultaneously at the former data write completion.
ꢀ
When the memory address counter reaches the end address, the detection circuit of external write signal (ExWR) operation is enabled and negation of the
memory channel request which synchronized with the following φ is made.
ꢀ
When the write operation to the end address has been completed, the memory address counter is increased and the memory channel operation end
interrupt is generated.
Fig. 125 Memory channel receiving operation (2)
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REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(5) Memory Channel Receiving Operation (3)-
Burst Mode (Terminal Count)
Memory channel receiving operation (3) is shown bellow.
ꢀ’
ꢀ’
ꢀ
ꢀ
ꢀ
A0 = “x”
A0 = “x”
CS = “1”
Address ExA0
Chip select ExCS
CS = “1”
DMA acknowledge
ExDACK
Dack = “0”
Dack = “0”
ꢀ’
Terminal count ExTC
Write ExWR
TC
Data DQ0 to DQ7
#0
#1
Internal clock φ
DMA request
ExDREQ
Mch_req
mWR
mWR
detection
detection
Receive buffer RxBuf
mTC detection
#0
#1
TC synchronizing
TC end
ꢀ
ꢀ’
ꢀ’
ꢀ’
Operation enabled
Main sequencer
0
1
2
3
(5)
5
Memory channel operation
end interrupt
req
Internal memory access
ꢀ
ꢀ’
Memory address
Counter end
Burst end
010016
010116
010216
Acknowledgment of
internal memory access
ack
ack
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
End address register
(Example) 010016
(Example) 010716
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
ꢀ When a rise of TC is detected, negation of the memory channel request which synchronized with a rise of φ is made.
ꢀ When the write operation to the end address has been completed, the memory channel operation end interrupt is generated.
Fig. 126 Memory channel receiving operation (3)
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REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(6) Memory Channel Transmitting Operation (1)-
Cycle Mode
Memory channel transmitting operation (1) is shown bellow.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ’
ꢀ
ꢀ
Address ExA0
A0 = “x”
CS = “1”
A0 = “x”
CS = “1”
Chip select ExCS
DMA acknowledge
ExDACK
Dack = “0”
Dack = “0”
ꢀ
ꢀ’
Read ExRD
Write ExWR
#0
#1
Data DQ0 to DQ7
Internal clock φ
DMA request
ExDREQ
Mch_req
Mch_req
mRD
mRD
detection
detection
Transmission completed
Transmit buffer TXBUF
#0
#1
4
ꢀ
Operation enabled
Main sequencer
0
1
2
3
5
Memory channel operation
end interrupt
req
req
Internal memory access
Memory address
Counter end
010016
010116
010216
Acknowledgment of
internal memory access
ack
ack
ꢀ
ꢀ
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “0” (Cycle mode)
Memory address counter
End address register
(Example) 010016
(Example) 010116
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
ꢀ
In the memory channel transmit mode when the command for enabling operation is written, operation starts (main sequencer starts) and an internal
memory access sequence which synchronized with a rise of φ is activated.
ꢀ
ꢀ
A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExRD is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of φ is made.
ꢀ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
ꢀ
A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
When the read operation from the end address has been completed, the transition to the status to wait the memory channel operation end occurs.
ꢀ When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Fig. 127 Memory channel tranmitting operation (1)
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REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
(7) Memory Channel Transmitting Operation (2)-
Burst Mode
Memory channel transmitting operation (2) is shown bellow.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ’
ꢀ’
ꢀ
ꢀ
ꢀ
Address ExA0
A0 = “x”
A0 = “x”
A0 = “x”
CS = “1”
Dack = “0”
CS = “1”
Dack = “0”
CS = “1”
Dack = “0”
Chip select ExCS
DMA acknowledge
ExDACK
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
#2
Internal clock φ
DMA request
ExDREQ
Mch_req
mRD
mRD
detection
detection
Transmission completed
Transmit buffer TXBUF
Operation enabled
Main sequencer
#0
#1
#2
4
ꢀ
0
1
2
3
5
Memory channel operation
end interrupt
Internal memory access
req
req
req
Memory address
Counter end
010016
010116
010216
010316
Burst end
Acknowledgment of
internal memory access
ack
ack
ack
ꢀ
ꢀ
ꢀ
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
End address register
(Example) 010016
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
ꢀ
ꢀ
In the memory channel transmit mode when the command for enabling operation is written, an internal memory access sequence which synchronized with
a rise of φ is activated.
A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
ꢀ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
ꢀ
A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased.
ꢀ
ꢀ
When the read operation from the end address has been completed, the detection circuit of external read signal (ExRD) operation is enabled and negation
of the memory channel request which synchronized with the following φ is made.
When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Fig. 128 Memory channel tranmitting operation (2)
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REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
MULTICHANNEL RAM
The one wait function (ONW function) of 38000 series CPU is
used internally to control access with the CPU. When receiving an
access request from the USB or the EXB, the multichannel RAM
outputs ONW signal to wait the CPU for one clock, and access of
the USB or the EXB is performed.
The 38K2 group has the built-in multichannel RAM including the
small logic circuit (RAM I/F) instead of ordinary RAM.
The multichannel RAM has the USB channel and the EXB channel
in addition to the CPU channel.
The multichannel RAM controls access from CPU, USB and EXB,
synchronizing control with φ. The USB transfer rate is about 1.5
Mbytes/second. Access to the multichannel RAM is performed at
every about 5.3 clocks in φ = 8 MHz, or at every about 4 clocks in
φ = 6 MHz. The USB’s access has priority to the EXB’s.
If the multichannel RAM is outputting ONW signal while the CPU
is in the state of reading/writing for the RAM area, the CPU read
cycle or write cycle is extended by 1 period of φ.
No wait
No wait
No wait
ONW = “H”
Except RAM
No RD/WR
φ
RAM area
Except RAM
RAM area
CPU AD
RD/WR
CPU bus cycle
USB REQ
EXB REQ
ONW
Multichannel RAM
CPU
USB
CPU
RAM access right
RAM RD/WR
RAM bus cycle
Fig. 129 Multichannel RAM timing diagram (no wait)
One wait
One wait
One wait
One wait
Prohibiting continuous access of
USB/EXB
USB having priority of USB/EXB
simultaneous access
CPU accessing RAM at the latter part
2-cycle wait (max.) for EXB
Prior CPU
Prior CPU
Prior USB
Prior CPU
φ
CPU AD
RD/WR
RAM area
RAM area
RAM area
RAM area
CPU bus cycle
USB REQ
EXB REQ
ONW
Multichannel RAM
EXB
CPU
USB
CPU
USB
CPU
EXB
CPU
RAM access right
RAM RD/WR
RAM bus cycle
Fig. 130 Multichannel RAM timing diagram (one wait)
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REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
Multichannel RAM Operation Example
The multichannel RAM operation example is shown below.
This example shows the case that an external MCU uses the
38K2 group as a peripheral LSI (USB controller).
The following explains that the external MCU reads out the data
which is received via the USB.
ꢀ The data which is received via the USB is written into the multi-
channel RAM.
ꢀ Receive completion is propagated to the CPU.
ꢀ The external bus interface is activated owing to the CPU.
ꢀ (1) The external bus interface sets the data which is read from
the multichannel RAM into the internal data buffer.
(2) The external MCU reads out the data bus buffer of the exter-
nal bus interface.
(3) The above operation is repeated by the number of the re-
ceived bytes. After that, the data transfer is completed.
Program ROM
Peripheral functions
CPU
ꢀ
Notice of receive completion
Multichannel RAM
ꢀ
Activating
External MCU bus
USB bus
External bus interface
USB
(USB host)
ꢀ
FIFO read of received data
by External bus interface
ꢀ
FIFO write of received data
by USB
Fig. 131 Multichannel RAM operation example
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REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
Comparator and Control Circuit
A/D CONVERTER
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, and then stores the result in the
AD conversion registers 1, 2. When an A/D conversion is com-
pleted, the control circuit sets the AD conversion completion bit
and the AD interrupt request bit to “1”.
The functional blocks of the A/D converter are described below.
[AD Conversion Register 1, 2 (AD1, AD2)]
003716, 003816
The AD conversion register is a read-only register that stores the
result of an A/D conversion. When reading this register during an
A/D conversion, the previous conversion result is read.
Bit 7 of the AD conversion register 2 must be set to “0”. Not only
10-bit reading but also only high-order 8-bit reading of conversion
result can be performed by selecting the reading procedure of the
AD conversion registers 1, 2 after A/D conversion is completed (in
Figure 133).
Note that because the comparator consists of a capacitor cou-
pling, set f(system clock) to 500 kHz or more during an A/D
conversion.
b7
b0
AD control register
(ADCON : address 003616
)
The 8-bit reading inclined to MSB is performed when reading the
AD converter register 1 after A/D conversion is started or reset;
and when the AD converter register 1 is read after reading the AD
converter register 2, the 8-bit reading inclined to LSB is per-
formed.
Analog input pin selection bits
0 0 0 : P1
0 0 1 : P1
0 1 0 : P1
0 1 1 : P1
1 0 0 : P1
1 0 1 : P1
1 1 0 : P1
1 1 1 : P1
0/DQ
1/DQ
2/DQ
3/DQ
4/DQ
5/DQ
6/DQ
7/DQ
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
[AD Control Register (ADCON)] 003616
The AD control register controls the A/D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 3 signals the comple-
tion of an A/D conversion. The value of this bit remains at “0”
during an A/D conversion, and changes to “1” when an A/D con-
version ends. Writing “0” to this bit starts the A/D conversion.
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (indefinite at read)
(These bits are write disabled bits.)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
VREF and AVSS into 1024, and that outputs the comparison volt-
age.
Fig. 132 Structure of AD control register
The A/D converter successively compares the comparison voltage
Vref in each mode, dividing the VREF voltage (see below), with the
input voltage.
10-bit reading
(Read address 003816 before 003716)
b7
b0
b9 b8
b0
• 10-bit reading
(address 003816)
(address 003716)
0
VREF
Vref =ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀn (n = 0–1023)
1024
b7
b7 b6 b5 b4 b3 b2 b1 b0
• 8-bit reading
Note : Bits 2 to 7 of address 003816 become “0”
VREF
Vref =ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀn (n = 0–255)
at reading.
256
8-bit reading
(Read only address 003716)
b7
Channel Selector
The channel selector selects one of the input ports P17/AN7–P10/
b0
b9 b8 b7 b6 b5 b4 b3 b2
(address 003716)
AN0.
Fig. 133 10-bit/8-bit reading
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
Data bus
b7
b0
A/D control register
(address 003616
)
3
A/D interrupt request
A/D control circuit
P1
P1
P1
P1
P1
P1
P1
P1
0
1
2
3
4
5
6
7
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
0/AN
1/AN
2/AN
3/AN
4/AN
5/AN
6/AN
7/AN
0
1
2
3
4
5
6
7
(address 003816
)
AD conversion register 2
AD conversion register 1
Comparator
(address 003716
)
10
Resistor ladder
VREF
V
SS
Fig. 134 A/D converter block diagram
Rev.2.00 Oct 15, 2006 page 92 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
WATCHDOG TIMER
ꢀWatchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) per-
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at sys-
tem clock 8 MHz frequency.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 003916) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watch-
dog timer H.
When this bit is set to “1”, the count source becomes the system
clock divided by 16. The detection time in this case is set to 512
µs at system clock 8 MHz frequency. This bit is cleared to “0” after
resetting.
ꢀOperation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003916) may be
started before an underflow. When the watchdog timer control reg-
ister (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit (bit 6), and
watchdog timer H count source selection bit (bit 7) are read.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
Once the STP instruction is executed, an internal reset occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L is set to “FF16.”
Data bus
“FF16” is set when
watchdog timer
control register is
written to.
“FF16” is set when
watchdog timer
control register is
written to.
“0”
Watchdog timer L (8)
System clock
Watchdog timer H (8)
1/16
“1”
Watchdog timer H count
source selection bit
STP instruction disable bit
STP instruction
Reset circuit
Internal reset
RESET
Fig. 135 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 003916
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: System clock/16
Fig. 136 Structure of Watchdog timer control register
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REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 16 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage should be between 3.0 V
and 5.25 V for L version, and the oscillation should be stable), re-
set is released. After the reset is completed, the program starts
from the address contained in address FFFD16 (high-order byte)
and address FFFC16 (low-order byte). Make sure that the reset in-
put voltage is under 0.6 V for VCC of 3.0 V (L version).
Poweron
(Note)
Power source
voltage
RESET
VCC
0 V
Reset input
0.2VCC
voltage
0 V
Note : Reset release voltage ;
Vcc = 3.0 V (L version)
RESET
VCC
Power source
voltage detection
circuit
Fig. 137 Example of reset circuit
X
IN
φ
RESET
Internal
reset
Address
AD
H L
,
?
?
?
?
FFFC
FFFD
Reset address from the vector table.
Data
AD
H
?
?
?
ADL
?
SYNC
XIN: 10.5 to 18.5 clock cycles
Notes
1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8
• f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 138 Reset sequence
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REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
PLL CIRCUIT (FREQUENCY SYNTHESIZER)
The PLL circuit generates fVCO (PLL output clock), which is re-
quired for fUSB (USB clock) and fSYN (fUSB division clock), from
f(XIN) (external input reference clock). Figure 139 shows the PLL
circuit block diagram.
It is possible to input 6 or 12 MHz clock from the externals as a
standard clock input. When using the USB function, set the PLL
operation mode selection bit so that fvco may be set to 48 MHz.
The PLL circuit operates by setting the PLL operation enable bit to
“1”. When supplying fVCO to the USB block, wait for the oscillation
stable time (1ms or less) of PLL before selecting fVCO with the
USB clock selection bit.
According to the setting of the USB clock division ratio selection
bit, the division clock of fUSB is supplied to fSYN. When using this
clock as system clock, set the USB clock division ratio selection
bit so that it may be set to 6 MHz, 8 MHz or 12 MHz. (However,
using it only when fUSB is 48MHz is recommended).
f
USB
f(XIN
)
f
VCO
PLL
Division circuit
f
SYN
PLLCON
USBCON
(address 0FF816
)
(address 001016)
Fig. 139 Block diagram of PLL circuit
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REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
b7
b0
PLL control register
(PLLCON: address 0FF816
)
Not used (return “0” when read)
USB clock division ratio selection bits
b4b3
0 0: Divided by 8 (fSYN = fUSB/8)
0 1: Divided by 6 (fSYN = fUSB/6)
1 0: Divided by 4 (fSYN = fUSB/4)
1 1: Not selected
PLL operation mode selection bits
b6b5
0 0: Not multiplied (fVCO = fXIN
)
0 1: Double (fVCO = fXIN ꢀ 2)
1 0: Quadruple (fVCO = fXIN ꢀ 4)
1 1: Multiplied by 8 (fVCO = fXIN ꢀ 8)
PLL Enable Bit
0: Disabled
1: Enabled
Fig. 140 Structure of PLL control register
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REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
Oscillation Control
(1) Stop mode
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT. Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No external
resistor is needed between XIN and XOUT since a feed-back resis-
tor exists on-chip. (An external feed-back resistor may be needed
depending on conditions.)
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and the XIN oscillator stops. When the oscillation stabi-
lizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1. XIN
divided by 16 is compulsorily connected to the input of the
prescaler 12. Oscillator restarts when an external interrupt (includ-
ing USB resume interrupt) is received, but the internal clock φ
remains at “H” until timer 1 underflows. The internal clock φ is not
supplied until timer 1 underflows. Because the sufficient time is re-
quired for the oscillation to stabilize when a ceramic resonator etc.
is used. When the oscillator is restarted by reset, apply “L” level to
the RESET pin until the oscillation is stable since a wait time will
not be generated automatically.
Frequency Control
Either fSYN or f(XIN) can be selected as an internal system clock.
Furthermore, the frequency of internal clock φ can be selected by
the system clock division ratio selection bit.
(1) fSYN clock
fSYN clock is generated by the PLL circuit. f(XIN) or fVCO can be
selected as an input clock. When using as an internal system
clock, there is restriction on use. Refer to the clause of “PLL CIR-
CUIT”.
(2) f(XIN) clock
The frequency applied to the XIN pin is used as an internal system
(2) Wait mode
clock frequency.
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before ex-
ecuting of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruc-
tion.
ꢀNote
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
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38K2 Group
FUNCTIONAL DESCRIPTION
b7
b0
MISRG
(MISRG: address 0FFB16)
X
IN
XOUT
Oscillation stabilizing time set after STP instruction
released bit
Rd (Note)
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
Not used (indefinite at read)
C
OUT
C
IN
Note : Insert a damping resistor if required.
Fig. 143 Structure of MISRG
The resistance will vary depending on the oscillator
and the oscillation drive capacity setting.
Use the value recommended by the maker of the
oscillator.
Also, if the oscillator manufacturer's data sheet
specifies that a feedback resistor be added external
to the chip though a feedback resistor exists on-chip,
insert a feedback resistor between XIN and XOUT
following the instruction.
Fig. 141 Ceramic resonator or quartz-crystal oscilltor circuit
X
IN
X
OUT
Open
External oscillation circuit
VCC
V
SS
Fig. 142 External clock input circuit
X
IN
XOUT
fvco
USB clock selection bit
PLL
f
USB
1/4
1/6
1/8
USB clock division
ration selection bits
f
SYN
System clock selection bit
f
sio
f
AD
1/2
1/4
1/2
1/2
1/2
1/2
Timer 1
Prescaler 12
FF16
Reset or STP
instruction
0116
1/1
1/8
System clock division
ration selection bits
Timing φ (internal clock)
Reset
Q
S
S
R
Q
Q
S
R
WIT
instruction
STP instruction
STP instruction
R
Reset
Interrupt disable flag l
Interrupt request
Fig. 144 System clock generating circuit block diagram (single-chip mode)
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38K2 Group
FUNCTIONAL DESCRIPTION
Reset
CM6
“0”←→“1”
X
IN 8-divide mode
X
IN 4-divide mode
f(φ) = 1.5 MHz
CM7 = 0
f(φ) = 0.75 MHz
CM7 = 0
CM6 = 0
CM5 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = 00
PLLCON [4:3] = xx
(arbitrary)
CM6
“0”←→“1”
X
IN 2-divide mode
f(φ) = 3.0 MHz
CM7 = 1
X
IN through mode
f(φ) = 1.5 MHz
CM7 = 0
CM6 = 0
CM5 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
PLLCON [4:3] = xx
(arbitrary)
Note:
Set PLLCON [4:3] = 10 before
switching the system clock from XIN
to fSYN
.
f(SYN) 2-divide mode
f(φ) = 6.0 MHz
CM7 = 1
CM6 = 0
CM5 = 1
PLLCON [4:3] = 10
CM5
“0”←→“1”
CM6
“0”←→“1”
f(SYN) through mode
f(φ) = 6.0 MHz
CM7 = 1
CM5
“0”←→“1”
CM6 = 1
CM5 = 1
PLLCON [4:3] = 00
Note:
Set PLLCON [4:3] = 00 before switching
Note:
Set PLLCON [4:3] = 00 before switching
the system clock from XIN to fSYN.
the system clock from XIN to fSYN
.
CM5
“0”←→“1”
CM6
“0”←→“1”
f(SYN) through mode
f(φ) = 8.0 MHz
CM7 = 1
CM5
“0”←→“1”
CM6 = 1
CM5 = 1
PLLCON [4:3] = 01
Note:
Note:
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN
.
.
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly
without an allow.)
2 : Set the USB clock (fUSB) to 48 MHz when switching the system clock to fSYN
.
3 : Do not change a division ratio of USB clock when using fSYN as the system clock.
4 : See section “PLL CIRCUIT” in details for enabling/disabling PLL operation and usage notes of fSYN
5 : Set the system clock to XIN when entering STOP mode.
.
6 : In all modes, switching to WAIT mode is possible. When it is released, the MCU returns to the original mode. In
WAIT mode the timers can operate.
Remarks : This diagram assumes that the 6 MHz signals are applied to XIN pin.
Fig. 145 State transitions of clock
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38K2 Group
FUNCTIONAL DESCRIPTION
FLASH MEMORY MODE
This flash memory version has some blocks on the flash memory
as shown in Figure 146 and each block can be erased. The flash
memory is divided into User ROM area and Boot ROM area.
In addition to the ordinary User ROM area to store the MCU op-
eration control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user’s application sys-
tem. This Boot ROM area can be rewritten in only parallel I/O
mode.
The 38K2 group’s flash memory version has an internal new
DINOR (DIvided bit line NOR) flash memory that can be rewritten
with a single power source when VCC is 4.5 to 5.25 V, and 2 power
sources when VCC is 3.0 to 4.5 V.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
Summary
Table 9 lists the summary of the 38K2 group’s flash memory ver-
sion.
Table 9 Summary of 38K2 group’s flash memory version
Item
Specifications
Power source voltage (Vcc)
3.00 – 5.25 V (L version) (Program and erase in 4.00 to 5.25 V of Vcc.)
3.00 – 4.00 V (L version) (Program and erase in 3.00 to 5.25 V of Vcc.)
Program/Erase VPP voltage (VPP)
Flash memory mode
4.50 – 5.25 V
3 modes; Flash memory can be manipulated as follows:
•CPU rewrite mode: Manipulated by the Central Processing Unit (CPU).
•Parallel I/O mode: Manipulated using an external programmer (Note 1)
•Standard serial I/O mode: Manipulated using an external programmer (Note 1)
Erase block division
User ROM area
Boot ROM area
1 block (32 Kbytes)
1 block (4 Kbytes) (Note 2)
Program method
Erase method
Byte program
Batch erasing
Program/Erase control method
Number of commands
Program/Erase control by software command
6 commands
Number of program/Erase times
Data retention period
100 times
10 years
ROM code protection
Available in parallel I/O mode and standard serial I/O mode
Notes 1: In the parallel I/O mode or the standard serial I/O mode, use the exclusive external equipment flash programmer which supports the 38K2 Group
(flash memory version).
2: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be re-
written in only parallel I/O mode.
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38K2 Group
FUNCTIONAL DESCRIPTION
(1) CPU Rewrite Mode
Microcomputer Mode and Boot Mode
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central Process-
ing Unit (CPU).
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode beforehand.
(If the control program is written into the Boot ROM area, the stan-
dard serial I/O mode becomes unusable.)
In CPU rewrite mode, only the User ROM area shown in Figure
146 can be rewritten; the Boot ROM area cannot be rewritten.
Make sure the program and block erase commands are issued for
only the User ROM area and each block area.
See Figure 146 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer
is reset with pulling CNVSS pin low. In this case, the CPU starts
operating using the control program in the User ROM area.
When the microcomputer is reset by pulling the P16 (CE) pin high,
the CNVSS pin high, the CPU starts operating using the control
program in the Boot ROM area. This mode is called the “Boot”
mode.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite con-
trol program must be transferred to internal RAM area to be
executed before it can be executed.
Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command.
User ROM area
800016
Block 1 : 32 Kbytes
Boot ROM area
F00016
4 Kbytes
FFFF16
FFFF16
Notes 1: The Boot ROM area can be rewritten in only parallel I/O mode. (Access to any other
areas is inhibited.)
2: To specify a block, use the maximum address in the block.
Fig. 146 Block diagram of built-in flash memory
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38K2 Group
FUNCTIONAL DESCRIPTION
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten in CPU rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory as instructed by software commands. This
rewrite control program must be transferred to a memory such as
the internal RAM before it can be executed.
CPU becomes unable to access the internal flash memory directly.
Therefore, use the control program in a memory other than inter-
nal flash memory for write to bit 1. To set this bit to “1”, it is
necessary to write “0” and then write “1” in succession. The bit can
be set to “0” by only writing “0”.
Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in
CPU rewrite mode, so that reading this flag can check whether
CPU rewrite mode has been entered or not.
The MCU enters CPU rewrite mode by applying 4.50 V to 5.25 V
to the CNVSS pin and setting “1” to the CPU Rewrite Mode Select
Bit (bit 1 of address 0FFE16). Software commands are accepted
once the mode is entered.
Bit 3 is the flash memory reset bit used to reset the control circuit
of internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the
control circuit. To set this bit to “1”, it is necessary to write “0” and
then write “1” in succession. To release the reset, it is necessary
to set this bit to “0”.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 147 shows the flash memory control register.
Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In Boot mode, this bit is set to “1” auto-
matically. Reprogramming of this bit must be in a memory other
than internal flash memory.
Bit 0 is the RY/BY status flag used exclusively to read the operat-
ing status of the flash memory. During programming and erase
operations, it is “0” (busy). Otherwise, it is “1” (ready). This is
equivalent to the RY/BY pin function in parallel I/O mode.
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
“1”, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
Figure 148 shows a flowchart for setting/releasing CPU rewrite
mode.
b7
b0
Flash memory control register (address 0FFE16)
FMCR (Note 1)
RY/BY status flag
0: Busy (being written or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode (Software commands invalid)
1: CPU rewrite mode
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User area / Boot area select bit (Note 4)
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (indefinite at read/ “0” at write)
Notes 1: The contents of flash memory control register are “XXX00001” just after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not
this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt
will be generated during that interval.
Use the control program in the area except the built-in flash memory for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after
setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory for write to this bit.
Fig. 147 Structure of flash memory control register
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
Start
Single-chip mode or Boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control program to
memory other than internal flash memory
Jump to control program transferred in memory
other than internal flash memory
(Subsequent operations are executed by control
program in this memory)
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
Write “0” to CPU rewrite mode select bit
End
Notes 1: When starting the MCU in the single-chip mode or memory expansion mode, supply
4.5 V to 5.25 V to the CNVss pin until checking the CPU rewrite mode entry flag.
2: Set the system clock division ration selection bits of CPU mode register (bits 6 and
7 at address 003B16).
3: Before exiting the CPU rewrite mode after completing erase or program operation,
always be sure to execute the read array command or reset the flash memory.
Fig. 148 CPU rewrite mode set/release flowchart
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HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION
Notes on CPU Rewrite Mode
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
ꢀOperation speed
During CPU rewrite mode, set the internal clock φ to 1.5 MHz or
less using the system clock division ratio selection bits (bits 6 and
7 of address 003B16).
ꢀInstructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
ꢀInterrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
ꢀWatchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely cleared during program or erase.
ꢀReset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNVss = “H”, so that the pro-
gram will begin at the address which is stored in addresses
FFFC16 and FFFD16 of the boot ROM area.
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38K2 Group
FUNCTIONAL DESCRIPTION
____
Software Commands
During the program movement, The RY/BY Status Flag of flash
Table 10 lists the software commands.
memory control register is set to “0”. When the program com-
pletes, it becomes “1”.
After setting the CPU Rewrite Mode Select Bit to “1”, write a soft-
ware command to specify an erase or program operation.
Each software command is explained below.
At program end, program results can be checked by reading the
status register.
ꢀRead Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified ad-
dress are read out at the data bus (D0 to D7).
Start
Write 4016
The read array mode is retained intact until another command is
written.
Write address
Write
ꢀRead Status Register Command (7016)
Write data
When the command code “7016” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D0
to D7) by a read in the second bus cycle.
Status register
read
The status register is explained in the next section.
SR7 = 1 ?
NO
ꢀClear Status Register Command (5016)
or
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that opera-
tion has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
RY/BY = 1 ?
YES
NO
Program
error
SR4 = 0 ?
YES
ꢀProgram Command (4016)
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, the control circuit of flash memory
(data programming and verification) will start a program.
Program
completed
Whether the write operation is completed can be confirmed by
_____
reading the status register or the RY/BY Status Flag. When the
program starts, the read status register mode is entered automati-
cally and the contents of the status register is read at the data bus
(DB0 to DB7). The status register bit 7 (SR7) is set to “0” at the
same time the write operation starts and is returned to “1” upon
completion of the write operation. In this case, the read status reg-
ister mode remains active until the read array command (FF16) is
written.
Fig. 149 Program flowchart
Table 10 List of software commands (CPU rewrite mode)
First bus cycle
Data
Second bus cycle
Cycle number
Command
Data
(D0 to D7)
Mode
Address
Mode
Write
Address
(D0 to D7)
(Note 4)
Read array
1
2
1
X
FF16
(Note 1)
Read status register
Clear status register
X
X
Write
Write
7016
5016
Read
X
SRD
(Note 2)
(Note 2)
Program
Write
Write
Write
Write
Write
Write
WA
WD
2
2
2
X
X
X
4016
2016
2016
Erase all blocks
2016
D016
X
(Note 3)
Block erase
BA
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address to be erased (Input the maximum address of each block.)
4: X denotes a given address in the User ROM area .
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38K2 Group
FUNCTIONAL DESCRIPTION
ꢀErase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that
follows, the operation of erase all blocks (erase and erase verify)
starts.
Start
Whether the erase all blocks command is terminated can be con-
Write 2016
____
firmed by reading the status register or the RY/BY Status Flag of
flash memory control register. When the erase all blocks operation
starts, the read status register mode is entered automatically and
the contents of the status register can be read out at the data bus
(D0 to D7). The status register bit 7 (SR7) is set to “0” at the same
time the erase operation starts and is returned to “1” upon comple-
tion of the erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is writ-
2016/D016
Block address
2016:Erase all blocks
D016:Block erase
Write
Status register
read
ten.
____
The RY/BY Status Flag is “0” during erase operation and “1” when
the erase operation is completed as is the status register bit 7.
After the erase all blocks end, erase results can be checked by
reading the status register. For details, refer to the section where
the status register is detailed.
SR7 = 1 ?
or
RY/BY = 1 ?
NO
YES
NO
Erase error
SR5 = 0 ?
ꢀBlock Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the block address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
YES
Erase completed
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY Status Flag of flash
memory control register. At the same time the block erase opera-
tion starts, the read status register mode is automatically entered,
so that the contents of the status register can be read out. The
status register bit 7 (SR7) is set to “0” at the same time the block
erase operation starts and is returned to “1” upon completion of
the block erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is writ-
Fig. 150 Erase flowchart
ten.
____
The RY/BY Status Flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status reg-
ister bit 7.
After the block erase ends, erase results can be checked by read-
ing the status register. For details, refer to the section where the
status register is detailed.
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38K2 Group
FUNCTIONAL DESCRIPTION
Status Register (SRD)
•Erase status (SR5)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to “1”.
The program status is set to “0” when it is cleared.
Also, the status register can be cleared by writing the clear status
register command (5016).
If “1” is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status regis-
ter command (5016) and clear the status register.
After reset, the status register is set to “8016”.
Table 11 shows the status register. Each bit in this register is ex-
plained below.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
Table 11 Definition of each bit in status register
Definition
Each bit of
SRD0 bits
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
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38K2 Group
FUNCTIONAL DESCRIPTION
Full Status Check
By performing full status check, it is possible to know the execu-
tion results of erase and program operations. Figure 151 shows a
full status check flowchart and the action to be taken when each
error occurs.
Read status register
YES
SR4 = 1 and
SR5 = 1 ?
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
operation one more time after confirming that the
command is entered correctly.
NO
NO
NO
Should an erase error occur, the block in error
cannot be used.
Erase error
SR5 = 0 ?
YES
Should a program error occur, the block in error
cannot be used.
Program error
SR4 = 0 ?
YES
End (block erase, program)
Note: When one of SR5 and SR4 is set to “1”, none of the program, erase all blocks,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 151 Full status check flowchart and remedial procedure for errors
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38K2 Group
FUNCTIONAL DESCRIPTION
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check func-
tion for use in standard serial I/O mode.
If one or both of the pair of ROM Code Protect Bits is set to “0”,
the ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is se-
lected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM Code Protect Reset Bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be read out or modified. Once the ROM code
protect is turned on, the contents of the ROM Code Protect Reset
Bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM Code Pro-
tect Reset Bits.
ꢀROM Code Protect Function
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control register (address FFDB16) in paral-
lel I/O mode. Figure 152 shows the ROM code protect control
register (address FFDB16). (This address exists in the User ROM
area.)
b7
b0
ROM code protect control register (address FFDB16
)
ROMCP
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (Note 3)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 1)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
Notes 1: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite
mode.
Fig. 152 Structure of ROM code protect control register
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38K2 Group
FUNCTIONAL DESCRIPTION
ID Code Check Function
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the pro-
grammer is compared with the ID code written in the flash memory
to see if they match. If the ID codes do not match, the commands
sent from the programmer are not accepted. The ID code consists
of 8-bit data, and its areas are FFD416 to FFDA16. Write a pro-
gram which has had the ID code preset at these addresses to the
flash memory.
Address
FFD416
FFD516
FFD616
ID1
ID2
ID3
ID4
ID5
ID6
FFD716
FFD816
FFD916
ID7
FFDA16
FFDB16
ROM cord protect control
Interrupt vector area
Fig. 153 ID code store addresses
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FUNCTIONAL DESCRIPTION
(2) Parallel I/O Mode
Parallel I/O mode is the mode which parallel output and input soft-
ware command, address, and data required for the operations
(read, program, erase, etc.) to a built-in flash memory. Use the ex-
clusive external equipment flash programmer which supports the
38K2 Group (flash memory version). Refer to each programmer
maker’s handling manual for the details of the usage.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Fig-
ure 146 can be rewritten. Both areas of flash memory can be operated
on in the same way.
The boot ROM area is 4 Kbytes in size. It is located at addresses
F00016 through FFFF16. Make sure program and block erase opera-
tions are always performed within this address range. (Access to any
location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block.
The boot ROM area has had a standard serial I/O mode control pro-
gram stored in it when shipped from the Mitsubishi factory. There-
fore, using the device in standard serial I/O mode, you must perform
program and block erase in the user ROM area.
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FUNCTIONAL DESCRIPTION
(3) Standard Serial I/O Mode
Outline Performance (Standard Serial I/O Mode)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programer, etc.) using 4-wire clock-synchronized serial I/O.
In reception, software commands, addresses and program data
are synchronized with the rise of the transfer clock that is input to
the SCLK pin, and are then input to the MCU via the RxD pin. In
transmission, the read data and status are synchronized with the
fall of the transfer clock, and output from the TxD pin.
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, pro-
gram, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires a purpose-specific pe-
ripheral unit.The standard serial I/O mode is different from the
parallel I/O mode in that the CPU controls flash memory rewrite
(uses the CPU rewrite mode), rewrite data input and so forth. The
standard serial I/O mode is started by connecting “H” to the P16
(CE) pin and “H” to the P42 (SCLK) pin and “H” to the CNVSS (VPP)
pin (apply 4.5 V to 5.25 V to Vpp from an external source), and re-
leasing the reset operation. (In the ordinary microcomputer mode,
set CNVss pin to “L” level.)
The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB
first.
When busy, such as during transmission, reception, erasing or
program execution, the SRDY (BUSY) pin is “H” level. Accordingly,
always start the next transfer after the SRDY (BUSY) pin is “L”
level.
This control program is written in the Boot ROM area when the
product is shipped from Renesas Technology Corp.. Accordingly,
make note of the fact that the standard serial I/O mode cannot be
used if the Boot ROM area is rewritten in parallel I/O mode. Figure
154 shows the pin connections for the standard serial I/O mode.
In standard serial I/O mode, serial data I/O uses the four serial I/O
pins SCLK, RxD, TxD and SRDY (BUSY). The SCLK pin is the trans-
fer clock input pin through which an external transfer clock is
input. The TxD pin is for CMOS output. The SRDY (BUSY) pin out-
puts “L” level when ready for reception and “H” level when
reception starts.
Also, data and status registers in a memory can be read after in-
putting software commands. Status, such as the operating state of
the flash memory or whether a program or erase operation ended
successfully or not, can be checked by reading the status register.
Here following explains software commands, status registers, etc.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in
Figure 146 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, commands sent from the peripheral
unit (programmer) are not accepted unless the ID code matches.
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FUNCTIONAL DESCRIPTION
Table 12 Description of pin function (Standard Serial I/O Mode)
Pin name
VCC,VSS
VCCE
Signal name
Power supply
I/O
Function
Apply 3.00 to 5.25 V (L version) to the Vcc pin and 0 V to the Vss pin.
Connect this pin to Vcc.
Power supply
VPP
CNVSS
I
I
I
Connect this pin to VPP (VPP = 4.50 to 5.25 V).
Connect this pin to Vss.
CNVSS2
VREF
CNVSS2
Analog reference voltage
Analog power supply
Analog power supply
Reset input
Connect this pin to Vcc when not using.
Connect this pin to Vcc.
DVCC, PVCC
PVSS
Connect this pin to Vss.
RESET
I
To reset, input “L” level for 20 cycles or longer clocks of φ.
XIN
XOUT
Clock input
Clock output
I
O
Connect a ceramic or crystal resonator between the XIN and XOUT pins. When
entering an externally drived clock, enter it from XIN and leave XOUT open.
USBVREF
TrON
USB reference voltage input
USB reference voltage output
USB upstream input
USB downstream input
USB downstream input
Input port P0
I
Connect this pin to Vcc when not using.
Leave this pin open when not using.
Input “L” level when not using.
O
D0+,D0-
D1+,D1-
D2+,D2-
P00 to P07
P10 to P15
P16
I/O
I/O
Input “L” level when not using.
I/O
Input “L” level when not using.
I
I
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.Input “H” level only at release of reset.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
This is a serial data input pin.
Input port P1
Input port P1
I
P17
Input port P1
I
P20 to P24
P30 to P37
P40
Input port P2
I
Input port P3
I
RxD input
I
P41
TxD output
O
I
This is a serial data output pin.
P42
SCLK input
This is a serial clock input pin.Input “H” level only at release of reset.
This is a BUSY output pin.
P43
BUSY output
O
I
P50 to P57
P60 to P63
Input port P5
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input port P6
I
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FUNCTIONAL DESCRIPTION
Vcc
Vss
32
31
30
29
28
P2
5
49
50
51
52
53
54
55
56
57
58
59
60
P0
P0
6
7
P24
D2+
D2-
D1+
D1-
D0-
D0+
TrON
RXD
P4
P4
P4
P4
0
/E
/E
2
X
DREQ/R
DACK/T
/E TC/SCLK
/E
XD
TXD
1
X
XD
S
CLK
X
27
26
25
24
23
22
21
20
BUSY
3
X
A
1
/SRDY
P30
P31
P32
M38K29F8LFP/HP
USBVREF
DVCC
PVCC
P3
3/E
X
INT
CS
WR
RD
A0
/AN
/AN
P3
4
/E
/E
/E
/E
/DQ
/DQ
X
P3
P3
P3
0
5
X
61
62
63
64
PVSS
6
X
19
18
17
7
X
P6
3
(LED
(LED
3)
P6
2
2)
P1
P1
0
0
P61(LED1)
1
1
1
Mode setup method
Signal
Value
Connect to oscillator circuit.
CNVss
4.5 to 5.25 V
Vcc (Note 2)
Vss → Vcc
(Note 1)
S
CLK
RESET
CE
Vcc (Note 2)
Notes 1: Connect to Vcc in the case of Vcc = 4.5 V to 5.25 V.
Connect to VPP (= 4.5 V to 5.25 V) in the case of Vcc = 3.0 V to 4.5 V.
2: Supply Vcc at releasimg Reset.
Package outline: PLQP0064GA-A, PLQP0064KB-A
Fig. 154 Pin connection diagram in standard serial I/O mode
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38K2 Group
FUNCTIONAL DESCRIPTION
Software Commands
here below. Basically, the software commands of the standard se-
rial I/O mode are the same as that of the parallel I/O mode, but the
block erase function is excluded, and 4 commands are added: ID
check, download, version data output and Boot ROM area output
functions.
Table 13 lists software commands. In standard serial I/O mode,
erase, program and read are controlled by transferring software
commands via the RxD pin. Software commands are explained
Table 13 Software commands (Standard serial I/O mode)
Control command
1st byte 2nd byte
transfer
3rd byte
4th byte
5th byte
6th byte
.....
When ID is
not verified
FF16
1
Page read
Address
(middle)
Address
(high)
Data
Data
Data
Data
output to
259th byte
Not
acceptable
output
output
output
Data input
to 259th
byte
2
3
Page program
4116
A716
Address
(middle)
Address
(high)
Data
input
Data
input
Data
input
Not
acceptable
Erase all blocks
D016
Not
acceptable
SRD1
output
Acceptable
SRD
output
4
5
Read status register
Clear status register
7016
5016
Not
acceptable
6
7
ID check function
Download function
F516
FA16
Address
(low)
Address
(middle)
Address
(high)
ID size
ID1
To ID7
Acceptable
Check-
sum
Size
(low)
Size
(high)
Data
input
To
Not
acceptable
required
number
of times
8
9
Version data output function
FB16
FC16
Version
data
output
Version
data
output
Version
data
output
Version
data
output
Version
data
output
Version
data output
to 9th byte
Acceptable
Address
(middle)
Address
(high)
Data
Data
Data
Data
output to
259th byte
Boot ROM area output
function
Not
acceptable
output
output
output
Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from a programmer to the in-
ternal flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted when the flash memory is totally blank.
4: Address low is A0 to A7; Address middle is A8 to A15; Address high is A16 to A23. Address-high A16 to A23 are always “0016”.
Rev.2.00 Oct 15, 2006 page 115 of 130
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FUNCTIONAL DESCRIPTION
The contents of software commands are explained as follows.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
ꢀPage Read Command
This command reads the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page read
command as explained here following.
(3) From the 4th byte onward, data (D0 to D7) for the page (256
bytes) specified with addresses A8 to A23 will be output se-
quentially from the smallest address first synchronized with the
fall of the clock.
SCLK
A8 to
A15
A16 to
A23
RxD
TxD
FF16
data0
data255
SRDY (BUSY)
Fig. 155 Timing for page read
ꢀRead Status Register Command
This command reads status information. When the “7016” com-
mand code is transferred with the 1st byte, the contents of the
status register (SRD) with the 2nd byte and the contents of status
register 1 (SRD1) with the 3rd byte are read.
S
CLK
RxD
TxD
7016
SRD
output
SRD1
output
S
RDY (BUSY)
Fig. 156 Timing for reading status register
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FUNCTIONAL DESCRIPTION
ꢀClear Status Register Command
This command clears the bits (SR3 to SR5) which are set when
the status register operation ends in error. When the “5016” com-
mand code is sent with the 1st byte, the aforementioned bits are
cleared. When the clear status register operation ends, the SRDY
(BUSY) signal changes from “H” to “L” level.
S
CLK
5016
RxD
TxD
S
RDY (BUSY)
Fig. 157 Timing for clear status register
ꢀPage Program Command
(3) From the 4th byte onward, as write data (D0 to D7) for the
page (256 bytes) specified with addresses A8 to A23 is input
sequentially from the smallest address first, that page is auto-
matically written.
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page pro-
gram command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
When reception setup for the next 256 bytes ends, the SRDY
(BUSY) signal changes from “H” to “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
S
CLK
A
8
A
to
15
A16 to
A23
4116
data0
RxD
TxD
data255
S
RDY (BUSY)
Fig. 158 Timing for page program
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FUNCTIONAL DESCRIPTION
ꢀErase All Blocks Command
When erase all blocks end, the SRDY (BUSY) signal changes from
“H” to “L” level. The result of the erase operation can be known by
reading the status register.
This command erases the contents of all blocks. Execute the
erase all blocks command as explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte.
With the verify command code, the erase operation will start
and continue for all blocks in the flash memory.
S
CLK
A716
D016
RxD
TxD
S
RDY (BUSY)
Fig. 159 Timing for erase all blocks
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FUNCTIONAL DESCRIPTION
ꢀDownload Command
This command downloads a program to the RAM for execution.
Execute the download command as explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is
added to all data sent with the 5th byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches,
the downloaded program is executed. The size of the program will
vary according to the internal RAM.
S
CLK
Data size Data size
(low) (high)
Program
data
Check
sum
RxD
TxD
FA16
Program
data
S
RDY (BUSY)
Fig. 160 Timing for download
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FUNCTIONAL DESCRIPTION
(1) Transfer the “FB16” command code with the 1st byte.
ꢀVersion Information Output Command
(2) The version information will be output from the 2nd byte on-
ward.
This command outputs the version information of the control pro-
gram stored in the Boot ROM area. Execute the version
information output command as explained here following.
This data is composed of 8 ASCII code characters.
S
CLK
RxD
TxD
FB16
‘V’
‘E’
‘R’
‘X’
S
RDY (BUSY)
Fig. 161 Timing for version information output
ꢀBoot ROM Area Output Command
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
This command reads the control program stored in the Boot ROM
area in page (256 bytes) unit. Execute the Boot ROM area output
command as explained here following.
(3) From the 4th byte onward, data (D0 to D7) for the page (256
bytes) specified with addresses A8 to A23 will be output se-
quentially from the smallest address first synchronized with the
fall of the clock.
S
CLK
RxD
TxD
FC16
A8
to A15
A16 to A23
data0
data255
S
RDY (BUSY)
Fig. 162 Timing for Boot ROM area output
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FUNCTIONAL DESCRIPTION
(1) Transfer the “F516” command code with the 1st byte.
ꢀID Check
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”)
This command checks the ID code. Execute the boot ID check
command as explained here following.
of the 1st byte of the ID code with the 2nd, 3rd and 4th respec-
tively.
(3) Transfer the number of data sets of the ID code with the 5th
byte.
(4) Transfer the ID code with the 6th byte onward, starting with the
1st byte of the code.
S
CLK
ID size
ID1
ID7
RxD
TxD
F516
D416
FF16
0016
S
RDY (BUSY)
Fig. 163 Timing for ID check
ꢀID Code
When the flash memory is not blank, the ID code sent from the se-
rial programmer and the ID code written in the flash memory are
compared to see if they match. If the codes do not match, the
command sent from the serial programmer is not accepted. An ID
code contains 8 bits of data. Area is, from the 1st byte, addresses
FFD416 to FFDA16. Write a program into the flash memory, which
already has the ID code set for these addresses.
Address
FFD416
ID1
ID2
ID3
ID4
ID5
ID6
ID7
FFD516
FFD616
FFD716
FFD816
FFD916
FFDA16
ROM code protect control
Interrupt vector area
FFDB16
Fig. 164 ID code storage addresses
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FUNCTIONAL DESCRIPTION
ꢀStatus Register (SRD)
•Sequencer status (SR7)
The status register indicates operating status of the flash memory
and status such as whether an erase operation or a program
ended successfully or in error. It can be read by writing the read
status register command (7016). Also, the status register is
cleared by writing the clear status register command (5016).
Table 14 lists the definition of each status register bit. After releas-
ing the reset, the status register becomes “8016”.
The sequencer status indicates the operating status of the the
flash memory.
After power-on and recover from deep power down mode, the se-
quencer status is set to “1” (ready).
This status bit is set to “0” (busy) during write or erase operation
and is set to “1” upon completion of these operations.
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write opera-
tion. If a write error occurs, it is set to “1”. When the program
status is cleared, it is set to “0”.
Table 14 Status register (SRD)
Definition
SRD0 bits
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
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FUNCTIONAL DESCRIPTION
•Boot update completed bit (SR15)
ꢀStatus Register 1 (SRD1)
This flag indicates whether the control program was downloaded
to the RAM or not, using the download function.
The status register 1 indicates the status of serial communica-
tions, results from ID checks and results from check sum
comparisons. It can be read after the SRD by writing the read sta-
tus register command (7016). Also, status register 1 is cleared by
writing the clear status register command (5016).
•Check sum consistency bit (SR12)
This flag indicates whether the check sum matches or not when a
program, is downloaded for execution using the download func-
tion.
Table 15 lists the definition of each status register 1 bit. This regis-
ter becomes “0016” when power is turned on and the flag status is
maintained even after the reset.
•ID check completed bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands
cannot be accepted without an ID check.
•Data reception time out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the re-
ceived data is discarded and the MCU returns to the command
wait state.
Table 15 Status register 1 (SRD1)
Definition
SRD1 bits
Status name
“1”
“0”
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
Boot update completed bit
Reserved
Update completed
Not Update
-
-
-
Reserved
-
Checksum match bit
ID check completed bits
Match
00
Mismatch
Not verified
01
Verification mismatch
Reserved
10
11
Verified
SR9 (bit1)
SR8 (bit0)
Data reception time out
Reserved
Time out
-
Normal operation
-
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FUNCTIONAL DESCRIPTION
Full Status Check
Results from executed erase and program operations can be
known by running a full status check. Figure 165 shows a flow-
chart of the full status check and explains how to remedy errors
which occur.
Read status register
YES
SR4 = 1 and
SR5 = 1 ?
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
operation one more time after confirming that the
command is entered correctly.
NO
NO
NO
Should an erase error occur, the block in error
cannot be used.
Erase error
SR5 = 0 ?
YES
Should a program error occur, the block in error
cannot be used.
Program error
SR4 = 0 ?
YES
End (Erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 165 Full status check flowchart and remedial procedure for errors
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FUNCTIONAL DESCRIPTION
Example Circuit Application for Standard Serial I/
O Mode
Figure 166 shows a circuit application for the standard serial I/O
mode. Control pins will vary according to a programmer, therefore
see a programmer manual for more information.
V
CC
VCC
S
CLK
Clock input
BUSY output
Data input
P16 (CE)
SRDY (BUSY)
RxD
TxD
Data output
M38K29F8L
V
PP power
CNVss
source input
Notes 1: Control pins and external circuitry will vary according to a programmer. For more
information, see the programmer manual.
2: In this example, the VPP power supply is supplied from an external source (programmer).
To use the user’s power source, connect to 4.5 V to 5.25 V.
Fig. 166 Example circuit application for standard serial I/O mode
Rev.2.00 Oct 15, 2006 page 125 of 130
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NOTES ON PROGRAMMING
NOTES ON PROGRAMMING
Instruction Execution Time
Processor Status Register
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction. However, When using the USB function or
EXB function, an occurrence of one-wait due to the multichannel
RAM will double an internal clock φ cycle.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
• When n (0 to 255) is written to a timer latch, the frequency divi-
sion ratio is 1/(n+1).
• When a count source of timer X is switched, stop a count of timer
X.
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
• The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
A/D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(system clock) in the middle/high-
speed mode is at least on 500 kHz during an A/D conversion.
Do not execute the STP or WIT instruction during an A/D conver-
sion.
Rev.2.00 Oct 15, 2006 page 126 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
NOTES ON PROGRAMMING
Definition of A/D Conversion Accuracy
The A/D conversion accuracy is defined below (refer to Figure
167).
ꢀ Non-linearity error
This means a deviation from the line between VOT and VFST of
a converted value between VOT and VFST.
ꢀ Differential non-linearity error
•Relative accuracy
This means a deviation from the input potential difference re-
quired to change a converted value between VOT and VFST by 1
LSB of the 1 LSB at the relative accuracy.
ꢀ Zero transition voltage (VOT)
This means an analog input voltage when the actual A/D con-
version output data changes from “0” to “1.”
ꢀ Full-scale transition voltage (VFST)
•Absolute accuracy
This means an analog input voltage when the actual A/D con-
version output data changes from “1023” to “1022.”
This means a deviation from the ideal characteristics between 0 to
VREF of actual A/D conversion characteristics.
Output data
Full-scale transition voltage (VFST
)
1023
1022
b-a
Differential non-linearity error=
c
[LSB]
a
Non-linearity error=
[
b
a
a
LSB]
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB at relative accuracy
b: Vn+1-V
n
c: Difference between
the ideal Vn and actual Vn
Ideal line of A/D
conversion between
V0 to V1022
1
0
V0
V1
Vn
Vn+1
VREF
V
1022
Analog voltage
Zero transition voltage (V0T
)
Fig. 167 Definition of A/D conversion accuracy
Vn: Analog input voltage when the output data changes from “n” to “n + 1” (n = 0 to 1022)
V
FST – VOT
1022
• 1 LSB at relative accuracy →
• 1 LSB at absolute accuracy →
(V)
(V)
V
REF
1024
Rev.2.00 Oct 15, 2006 page 127 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
NOTES ON USAGE/DATA REQUIRED FOR MASK ORDERS
NOTES ON USAGE
USB Communication
Power Source Voltage
In applications requiring high-reliability, we recommend providing
the system with protective measures such as USB function initial-
ization by software or USB reset by the host to prevent USB
communication from being terminated unexpectedly, for example
due to external causes such as noise.
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less than
the recommended operating conditions and design a system not
to cause errors to the system by this unstable operation.
Flash Memory Version
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational in-
terference even if it is connected to Vss pin or Vcc pin via a
resistor.
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ce-
ramic or electrolytic capacitor of 1.0 µF is recommended.
Electric Characteristic Differences Between
Mask ROM and Flash Memory Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between Mask ROM and
Flash Memory version MCUs due to the difference in the manufac-
turing processes.
USB Port Pins (D0+, D0-, D1+, D1-, D2+, D2-)
Treatment
•The USB specification requires a driver-impedance 28 to 44 Ω. In
order to meet the USB specification impedance requirements,
connect a resistor (27 Ω recommended) in series to the USB port
pins.
When manufacturing an application system with the Flash
Memory version and then switching to use of the Mask ROM ver-
sion, please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
In addition, in order to reduce the ringing and control the falling/
rising timing and a crossover point, connect a capacitor between
the USB port pins and the Vss pin if necessary.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
The values and structure of those peripheral elements depend on
the impedance characteristics and the layout of the printed circuit
board. Accordingly, evaluate your system and observe waveforms
before actual use and decide use of elements and the values of
resistors and capacitors.
ꢀ
1. Mask ROM Order Confirmation Form
ꢀ
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
•Make sure the USB D+/D- lines do not cross any other wires.
Keep a large GND area to protect the USB lines. Also, make sure
you use a USB specification compliant connecter for the connec-
tion.
ꢀ For the mask ROM confirmation and the mark specifications, re-
fer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com).
USBVREF pin Treatment (Noise Elimination)
•Connect a capacitor between the USBVREF pin and the Vss pin.
The capacitor should have a 2.2 µF capacitor (electrolytic capaci-
tor) and a 0.1 µF capacitor (ceramic type capacitor) connected in
parallel.
•In Vcc = 3.0 to 3.6 V operation, connect the USBVREF pin directly
to the Vcc pin in order to supply power to the USB port circuit. In
addition, you will need to disable the built-in USB reference volt-
age circuit in this operation (set bit 4 of the USB control register
to “0”.) If you are using the bus powered supply in this condition,
the DC-DC converter must be placed outside the MCU.
•In Vcc = 4.00 to 5.25 V operation, do not connect the external
DC-DC converter to the USBVREF pin. Use the built-in USB refer-
ence voltage circuit.
Rev.2.00 Oct 15, 2006 page 128 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
A/D Converter
A/D conversion is started by setting AD conversion completion bit to
“0.” During A/D conversion, internal operations are performed as fol-
lows.
By repeating the above operations up to the lowest-order bit of the
AD conversion register, an analog value converts into a digital
value.
A/D conversion completes at 122 clock cycles (15.25 µs at system
clock = 8 MHz, Through mode) after it is started, and the result of
the conversion is stored into the AD conversion register.
Concurrently with the completion of A/D conversion, A/D conversion
interrupt request occurs, so that the AD conversion interrupt request
bit is set to “1.”
1. After the start of A/D conversion, AD conversion register goes to
“0016.”
2. The highest-order bit of AD conversion register is set to “1,” and
the comparison voltage Vref is input to the comparator. Then, Vref
is compared with analog input voltage VIN.
3. As a result of comparison, when Vref < VIN, the highest-order bit
of AD conversion register becomes “1.” When Vref > VIN, the
highest-order bit becomes “0.”
Table 16 Relative formula for a reference voltage VREF of A/D
converter and Vref
When n = 0
Vref = 0
VREF
1024
When n = 1 to 1023
Vref =
ꢀ n
n: Value of A/D converter (decimal numeral)
Table 17 Change of AD conversion register during A/D conversion
Change of AD conversion register
Value of comparison voltage (Vref)
At start of conversion
First comparison
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VREF
2
VREF
2
VREF
±
Second comparison
Third comparison
0
0
0
0
ꢀ1
4
VREF
2
VREF
8
VREF
4
±
±
±
ꢀ1 ꢀ2
0
0
1
After completion of tenth
comparison
A result of A/D conversion
ꢀ1 ꢀ2 ꢀ3 ꢀ4 ꢀ5 ꢀ6 ꢀ7 ꢀ8
VREF
2
VREF
1024
VREF
4
±
±
ꢀ9 ꢀ10
• • • •
ꢀ1–ꢀ10: A result of the first comparison to the tenth comparison
Rev.2.00 Oct 15, 2006 page 129 of 130
REJ09B0338-0200
HARDWARE
38K2 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 168 shows the A/D conversion equivalent circuit, and Fig-
ure 169 shows the A/D conversion timing chart.
V
CC
V
CC
VSS
VSS
About 2 kW
VIN
AN0
Sampling
clock
AN
1
2
C
AN
Chopper
amplifier
AN
AN
AN
3
4
AD conversion register 2
5
AN
6
7
AN
AD conversion register 1
b2 b1
b0
AD control register
AD conversion interrupt request
V
ref
VREF
Reference
clock
Built-in
D/A converter
VSS
Fig. 168 A/D conversion equivalent circuit
φ
Write signal for AD
control register
61 cycles
AD conversion
completion bit
Sampling clock
Fig. 169 A/D conversion timing chart
Rev.2.00 Oct 15, 2006 page 130 of 130
REJ09B0338-0200
CHAPTER 2
APPLICATION
2.1 I/O port
2.2 Interrupt
2.3 Timer
2.4 Serial I/O
2.5 USB function
2.6 HUB function
2.7 External bus interface (EXB)
2.8 A/D converter
2.9 Watchdog timer
2.10 Reset
2.11 Frequency synthesizer (PLL)
2.12 Clock generating circuit
2.13 Standby function
2.14 Flash memory
APPLICATION
2.1 I/O port
38K2 Group
2.1 I/O port
This paragraph explains the registers setting method and the notes related to the I/O ports.
2.1.1 Memory map
Port P0 (P0)
000016
Port P0 direction register (P0D)
000116
Port P1 (P1)
000216
Port P1 direction register (P1D)
000316
Port P2 (P2)
000416
000516
000616
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
000716
000816
000916
000A16
000B16
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
000C16
000D16
Port P6 direction register (P6D)
0FF016
0FF216
Port P0 pull-up control register (PULL0)
Port P5 pull-up control register (PULL5)
Fig. 2.1.1 Memory map of registers related to I/O port
Rev.2.00 Oct 15, 2006 page 2 of 112
REJ09B0338-0200
APPLICATION
2.1 I/O port
38K2 Group
2.1.2 Related registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6) (Note)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16
]
At reset
B
0
Name
Function
R W
?
?
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
1
2
3
4
5
6
7
ꢀ
ꢀ
In output mode
Write
Read
Port latch
1
2
3
4
5
6
7
In input mode
Write : Port latch
Read : Value of pins
?
?
?
?
?
?
Note: Since the following ports are not allocated, the corrrsponding bits can not be used.
• P2
• P4
• P6
0
4
4
to P2
to P4
to P6
3
7
7
Fig. 2.1.2 Structure of Port Pi (i = 0 to 6)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6) (Note)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16
]
Name
Function
input mode
output mode
At reset
B
0
R W
0 : Port Pi
1 : Port Pi
0
0
Port Pi direction register
0
ꢀ
0 : Port Pi
1 : Port Pi
1
1
input mode
output mode
1
2
3
4
5
6
7
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
0 : Port Pi
1 : Port Pi
3
3
input mode
output mode
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
input mode
output mode
0 : Port Pi
1 : Port Pi
7
7
input mode
output mode
Note: Since the following ports are not allocated, the corrrsponding bits can not be used.
• P2
• P4
• P6
0
4
4
to P2
to P4
to P6
3
7
7
Do not set bits of the direction register corresponding to ports P2
register (address 0516)) to output mode (“1”).
If writing to these bits, write “0”.
0
–P2
3
(bits 0–3 of port P2 direction
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6)
Rev.2.00 Oct 15, 2006 page 3 of 112
REJ09B0338-0200
APPLICATION
2.1 I/O port
38K2 Group
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 pull-up control register (PULL0)
[Address : 0FF016
]
At reset R W
Name
B
0
Function
0 : No pull-up
1 : Pull-up
0
P00
pul l-up control bit
0 : No pull-up
1 : Pull-up
1
2
0
0
P0
0
0
pul l-up control bit
pul l-up control bit
0 : No pull-up
1 : Pull-up
P0
0 : No pull-up
1 : Pull-up
3
4
5
0
0
0
P0
0
pul l-up control bit
pul l-up control bit
0 : No pull-up
1 : Pull-up
P0
0
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
P0
0
0
pul l-up control bit
pul l-up control bit
pul l-up control bit
6
7
0
0
P0
0 : No pull-up
1 : Pull-up
P0
0
Fig. 2.1.4 Structure of Port P0 pull-up control register
Port P5 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P5 pull-up control register (PULL5)
[Address : 0FF216
]
At reset
R
W
Function
0 : No pull-up
1 : Pull-up
Name
B
0
P50
pul l-up control bit
0
Nothing is arranged for this bit. This is a write disabled bit.
When this bit is read out, the contents are “0”.
1
2
0
0
0 : No pull-up
1 : Pull-up
P52 pul l-up control bit
Nothing is arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0”.
3
4
5
0
0
0
6
7
0
0
Fig. 2.1.5 Structure of Port P5 pull-up control register
Rev.2.00 Oct 15, 2006 page 4 of 112
REJ09B0338-0200
APPLICATION
2.1 I/O port
38K2 Group
2.1.3 Handling of unused pins
Table 2.1.1 Handling of unused pins
Handling
Pins/Ports name
P0, P1, P2, P3, P4, •Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kΩ
P5, P6
to 10 kΩ.
•Set to the output mode and open at “L” or “H” level.
•Connect to Vss (GND).
V
X
REF
OUT
•Open, only when using an external clock.
•Connect to VCC
USBVREF
TrON
•Open
D0+, D0-,
D1+, D1-,
D2+, D2-
•Connect each to Vss through a resistor of 1 kΩ to 10 kΩ.
Rev.2.00 Oct 15, 2006 page 5 of 112
REJ09B0338-0200
APPLICATION
2.1 I/O port
38K2 Group
2.1.4 Notes on input and output pins
(1) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*1, the value of the
unspecified bit may be changed.
ꢀ Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
*1 bit managing instructions : SEB, and CLB instructions
Rev.2.00 Oct 15, 2006 page 6 of 112
REJ09B0338-0200
APPLICATION
2.1 I/O port
38K2 Group
2.1.5 Termination of unused pins
(1) Terminate unused pins
ꢀ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ. With regard to ports which can select the built-in pull-up resistor, the built-in pull-
up resistor can be used.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the mode
of the ports is switched over to the output mode by the program after reset. Thus, the potential
at these pins is undefined and the power source current may increase in the input mode. With
regard to an effects on the system, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
ꢀ I/O ports :
Do not open in the input mode.
ꢀ Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination shown
in (1).
ꢀ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
ꢀ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and VCC (or VSS).
ꢀ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
ꢀ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
Rev.2.00 Oct 15, 2006 page 7 of 112
REJ09B0338-0200
APPLICATION
2.2 Interrupt
38K2 Group
2.2 Interrupt
This paragraph explains the registers setting method and the notes related to the interrupt.
2.2.1 Memory map
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
003E16 Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
003F16
0FF316
Interrupt edge selection register (INTEDGE)
Fig. 2.2.1 Memory map of registers related to interrupt
2.2.2 Related registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1)
[Address : 3C16
]
At reset R W
Name
USB bus reset
interrupt request bit
B
0
Function
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
USB SOF interrupt
request bit
1
2
0 : No interrupt request issued
1 : Interrupt request issued
USB device interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
EXB interrupt
request bit
3
4
5
0
0
0
INT
0
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
Timer X interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
7
0
0
Timer 2 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
ꢀꢀ “0” can be set by software, but “1” cannot be set.
Fig. 2.2.2 Structure of Interrupt request register 1
Rev.2.00 Oct 15, 2006 page 8 of 112
REJ09B0338-0200
APPLICATION
2.2 Interrupt
38K2 Group
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2)
[Address : 3D16
]
At reset R W
Name
interrupt
request bit
B
0
Function
0 : No interrupt request issued
1 : Interrupt request issued
INT
1
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
USB HUB interrupt
request bit
1
2
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O receive
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O transmit
interrupt request bit
3
4
5
0
0
0
CNTR
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Key-on wake-up
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
A/D conversion
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
7
0
0
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
ꢀꢀ “0” can be set by software, but “1” cannot be set.
Fig. 2.2.3 Structure of Interrupt request register 2
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1)
[Address : 3E16
]
At reset R W
Name
USB bus reset
interrupt enable bit
Function
B
0
0 : Interrupt disabled
1 : Interrupt enabled
0
USB SOF interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1
2
0
0
USB device interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
EXB interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
3
4
5
0
0
0
INT0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6
7
0
0
Timer 2 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.2.4 Structure of Interrupt control register 1
Rev.2.00 Oct 15, 2006 page 9 of 112
REJ09B0338-0200
APPLICATION
2.2 Interrupt
38K2 Group
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2)
[Address : 3F16
]
At reset R W
Name
interrupt
enable bit
B
0
Function
0 : Interrupt disabled
1 : Interrupt enabled
INT
1
0
USB HUB interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1
2
0
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O receive
interrupt enable bit
Serial I/O transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
3
4
5
0
0
0
0
0
CNTR0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Key-on wake-up
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
A/D conversion
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6
7
Fix this bit to “0”.
Fig. 2.2.5 Structure of Interrupt control register 2
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE)
[Address : 0FF316
]
Function
0 : Falling edge active
1 : Rising edge active
At reset R W
Name
interrupt edge
selection bit
B
0
INT
0
0
0
0
Nothing is arranged for this bits. This is a write disabled bit.
1
2
When this bit is read out, the contents are “0”.
INT
1
interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are “0”.
3
4
5
0
0
0
6
7
0
0
Fig. 2.2.6 Structure of Interrupt edge selection register
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APPLICATION
2.2 Interrupt
38K2 Group
2.2.3 Interrupt source
The 38K2 group permits interrupts of 16 sources. These are vector interrupts with a fixed priority system.
Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority
interrupt is accepted first. This priority is determined by hardware, but a variety of priority processing can
be performed by software, using an interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to Table 2.2.1.
Table 2.2.1 Interrupt sources, vector addresses and priority of 38K2 group
Interrupt Request
Vector Addresses (Note 1)
Interrupt Source
Remarks
Priority
Generating Conditions
High
Low
1
2
At reset
Reset (Note 2)
FFFD16
FFFB16
FFFC16
FFFA16
Non-maskable
At detection of USB bus reset
signal (2.5 µs interval SE0)
USB bus reset
Valid when USB is selected
3
4
At detection of USB SOF signal
USB SOF
FFF916
FFF716
FFF816
FFF616
Valid when USB is selected
Valid when USB is selected
At detection of resume signal (K
state or SE0) or suspend signal
(3 ms interval bus idle), or at
completion of transaction
USB device
Valid when external bus is selected
5
6
At completion of reception or
transmission or at completion of
DMA transmission
External bus
INT0
FFF516
FFF316
FFF416
FFF216
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT0 input
7
8
At timer X underflow
At timer 1 underflow
At timer 2 underflow
Timer X
Timer 1
Timer 2
INT1
FFF116
FFEF16
FFED16
FFEB16
FFF016
FFEE16
FFEC16
FFEA16
STP release timer underflow
9
External interrupt
(active edge selectable)
10
At detection of either rising or
falling edge of INT1 input
Valid when USB HUB is selected
Valid when serial I/O is selected
Valid when serial I/O is selected
11
12
13
14
15
16
17
At detection of status change of
USB HUB down ports
USB HUB
FFE916
FFE716
FFE516
FFE316
FFE116
FFE816
FFE616
FFE416
FFE216
FFE016
At completion of serial I/O data
reception
Serial I/O
reception
At completion of serial I/O data
transmission
Serial I/O
transmission
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR0 input
CNTR0
External interrupt
(active edge selectable)
At falling of conjunction of input
level for port P0 (at input mode)
Key-on wake up
A/D conversion
BRK instruction
At completion of A/D conversion
FFDF16
FFDD16
FFDE16
FFDC16
Non-maskable software interrupt
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
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APPLICATION
2.2 Interrupt
38K2 Group
2.2.4 Interrupt operation
When an interrupt request is accepted, the contents of the following registers just before acceptance of the
interrupt requests is automatically pushed onto the stack area in the order of ꢀ, ꢀ and ꢀ.
ꢀHigh-order contents of program counter (PC
H
)
ꢀLow-order contents of program counter (PC
ꢀContents of processor status register (PS)
L
)
After the contents of the above registers are pushed onto the stack area, the accepted interrupt vector
address enters the program counter and consequently the interrupt processing routine is executed.
When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the
above registers pushed onto the stack area are restored to the respective registers in the order of ꢀ, ꢀ
and ꢀ; and the microcomputer resumes the processing executed just before acceptance of the interrupts.
Figure 2.2.7 shows an interrupt operation diagram.
Executing routine
·······
Interrupt occurs
(Accepting interrupt request)
Contents of program counter (high-order) are pushed onto stack
Suspended
operation
Contents of program counter (low-order) are pushed onto stack
Resume processing
Contents of processor status register are pushed onto stack
·······
Interrupt
processing
routine
RTI instruction
Contents of processor status register are popped from stack
Contents of program counter (low-order) are popped from stack
Contents of program counter (high-order) are popped from stack
: Operation commanded by software
: Internal operation performed automatically
Fig. 2.2.7 Interrupt operation diagram
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APPLICATION
2.2 Interrupt
38K2 Group
(1) Processing upon acceptance of interrupt request
Upon acceptance of an interrupt request, the following operations are automatically performed.
ꢀThe processing being executed is stopped.
ꢀThe contents of the program counter and the processor status register are pushed onto the stack
area. Figure 2.2.8 shows the changes of the stack pointer and the program counter upon acceptance
of an interrupt request.
ꢀConcurrently with the push operation, the jump destination address (the beginning address of the
interrupt processing routine) of the occurring interrupt stored in the vector address is set in the
program counter, then the interrupt processing routine is executed.
ꢀAfter the interrupt processing routine is started, the corresponding interrupt request bit is automatically
cleared to “0”. The interrupt disable flag is set to “1” so that multiple interrupts are disabled.
Accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination
address in the vector area corresponding to each interrupt.
Stack area
Program counter
PCL Program counter (low-order)
Interrupt disable flag = “0”
PCH Program counter (high-order)
Stack pointer
(S)
S
(S)
Interrupt
request is
accepted
Program counter
Stack area
PCL
PCH
Vector address
Interrupt disable flag = “1”
(from Interrupt vector area)
(s) – 3
Processor status register
Program counter (low-order)
(S) Program counter (high-order)
Stack pointer
S
(S) – 3
Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
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APPLICATION
2.2 Interrupt
38K2 Group
(2) Timing after acceptance of interrupt request
The interrupt processing routine begins with the machine cycle following the completion of the
instruction that is currently being executed.
Figure 2.2.9 shows the time up to execution of interrupt processing routine and Figure 2.2.10 shows
the timing chart after acceptance of interrupt request.
Interrupt request generated
Main routine
Start of interrupt processing
Waiting time for
post-processing of
pipeline
Stack push and
Interrupt processing routine
Vector fetch
0 to 16ꢀcycles
2 cycles
5 cycles
7 to 23 cycles
(When f(XIN) = 6 MHz; system clock 8 MHz
/through mode (8 MHz), 0.875 µs to 2.875 µs)
ꢀ When executing DIV instruction
Fig. 2.2.9 Time up to execution of interrupt processing routine
Waiting time for pipeline
Push onto stack
Interrupt operation starts
post-processing
Vector fetch
φ
SYNC
RD
WR
S, SPS S-1, SPS S-2, SPS
Address bus
Data bus
BL
BH AL, AH
AL AH
PC
Not used
PCH PCL PS
: CPU operation code fetch cycle
SYNC
(This is an internal signal that cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
: “0016” or “0116”
SPS
Fig. 2.2.10 Timing chart after acceptance of interrupt request
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2.2 Interrupt
38K2 Group
2.2.5 Interrupt control
The acceptance of all interrupts, excluding the BRK instruction interrupt, can be controlled by the interrupt
request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. Figure 2.2.11
shows an interrupt control diagram.
Interrupt request bit
Interrupt enable bit
Interrupt request
Interrupt disable flag
BRK instruction
Reset
Fig. 2.2.11 Interrupt control diagram
The interrupt request bit, interrupt enable bit and interrupt disable flag function independently and do not
affect each other. An interrupt is accepted when all the following conditions are satisfied.
ꢀInterrupt request bit .......... “1”
ꢀInterrupt enable bit ........... “1”
ꢀInterrupt disable flag ........ “0”
Though the interrupt priority is determined by hardware, a variety of priority processing can be performed
by software using the above bits and flag. Table 2.2.2 shows a list of interrupt control bits according to the
interrupt source.
(1) Interrupt request bits
The interrupt request bits are allocated to the interrupt request register 1 (address 3C16) and interrupt
request register 2 (address 3D16).
The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to
“1”. The interrupt request bit is held in the “1” state until the interrupt is accepted. When the interrupt
is accepted, this bit is automatically cleared to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software.
(2) Interrupt enable bits
The interrupt enable bits are allocated to the interrupt control register 1 (address 003E16) and the
interrupt control register 2 (address 3F16).
The interrupt enable bits control the acceptance of the corresponding interrupt request.
When an interrupt enable bit is “0”, the corresponding interrupt request is disabled. If an interrupt
request occurs when this bit is “0”, the corresponding interrupt request bit is set to “1” but the
interrupt is not accepted. In this case, unless the interrupt request bit is set to “0” by software, the
interrupt request bit remains in the “1” state.
When an interrupt enable bit is “1”, the corresponding interrupt is enabled. If an interrupt request
occurs when this bit is “1”, the interrupt is accepted (when interrupt disable flag = “0”).
Each interrupt enable bit can be set to “0” or “1” by software.
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2.2 Interrupt
38K2 Group
(3) Interrupt disable flag
The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable
flag controls the acceptance of interrupt request except BRK instruction.
When this flag is “1”, the acceptance of interrupt requests is disabled. When the flag is “0”, the
acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set
to “0” with the CLI instruction.
When a main routine branches to an interrupt processing routine, this flag is automatically set to “1”,
so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine. Figure 2.2.12 shows an example of multiple interrupts.
Table 2.2.2 List of interrupt bits according to interrupt source
Interrupt enable bit
Interrupt request bit
Interrupt source
Address
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
Address
003C16
003C16
003C16
003C16
003C16
003C16
003C16
003C16
003D16
003D16
003D16
003D16
003D16
003D16
003D16
USB bus reset
USB SOF
USB device
External bus
003E16
003E16
003E16
003E16
003E16
003E16
003E16
003E16
003F16
003F16
003F16
003F16
003F16
003F16
003F16
INT
0
Timer X
Timer 1
Timer 2
INT
1
USB HUB
Serial I/O receive
Serial I/O transmit
CNTR
0
Key-on wake-up
A/D converter
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2.2 Interrupt
38K2 Group
Interrupt request
Nesting
Reset
Time
Main routine
I = 1
C1 = 0, C2 = 0
Interrupt
request 1
C1 = 1
I = 0
Interrupt 1
I = 1
Interrupt
request 2
Multiple interrupt
C2 = 1
I = 0
Interrupt 2
I = 1
RTI
I = 0
RTI
I = 0
I
: Interrupt disable flag
C1 : Interrupt enable bit of interrupt 1
C2 : Interrupt enable bit of interrupt 2
: Set automatically.
: Set by software.
Fig. 2.2.12 Example of multiple interrupts
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2.2 Interrupt
38K2 Group
2.2.6 INT interrupt
The INT interrupt requests is generated when the microcomputer detects a level change of each INT pin
(INT , INT ).
0
1
(1) Active edge selection
INT and INT can be selected from either a falling edge or rising edge detection as an active edge
0
1
by the interrupt edge selection register. In the “0” state, the falling edge of the corresponding pin is
detected. In the “1” state, the rising edge of the corresponding pin is detected.
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2.2 Interrupt
38K2 Group
2.2.7 Key input interrupt
A key input interrupt request is generated by applying “L” level to any port P0 pin that has been set to the
input mode. In other words, it is generated when AND of the input level goes from “1” to “0”.
(1) Connection example when Key input interrupt is used
When using the Key input interrupt, compose an active-low key matrix which inputs to port P0. Figure
2.2.13 shows a connection example and the port P0 block diagram when using a key input interrupt.
In the connection example in Figure 2.2.13, a key input interrupt request is generated by pressing
one of the keys corresponding to ports P0
0
to P0 .
3
Port PXx
“L” level output
PULL 0 register
Port P0
direction register = “1”
7
Key input interrupt request
Bit 7 = “0”
ꢀ
ꢀ
ꢀꢀꢀ
Port P0
latch
7
6
5
4
P0
7
output
output
PULL 0 register
Port P0
direction register = “1”
6
Bit 6 = “0”
ꢀ
ꢀ
ꢀꢀꢀ
Port P0
latch
P0
6
PULL 0 register
Bit 5 = “0”
Port P0
direction register = “1”
5
ꢀ
ꢀꢀꢀ
Port P0
latch
P0
P0
5
output
output
PULL 0 register
Bit 4 = “0”
Port P0
direction register = “1”
4
ꢀ
ꢀꢀꢀ
Port P0
latch
4
PULL 0 register
Bit 3 = “1”
Port P0
direction register = “0”
3
ꢀ
Port P0
Input reading circuit
ꢀ
ꢀꢀꢀ
Port P0
latch
3
P0
3
input
input
input
input
PULL 0 register
Bit 2 = “1”
Port P0
direction register = “0”
2
ꢀ
ꢀ
ꢀꢀꢀ
Port P0
latch
2
P0
2
PULL 0 register
Bit 1 = “1”
Port P0
1
direction register = “0”
ꢀ
ꢀ
ꢀꢀꢀ
Port P0
latch
1
P0
P0
1
PULL 0 register
Bit 0 = “1”
Port P0
0
direction register = “0”
ꢀ
ꢀ
ꢀꢀꢀ
Port P0
latch
0
0
ꢀ
P-channel transistor for pull-up
ꢀꢀꢀ CMOS output buffer
Fig. 2.2.13 Connection example and port P0 block diagram when using key input interrupt
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2.2 Interrupt
38K2 Group
(2) Related registers setting
Figure 2.2.14 shows the related registers setting (corresponding to Figure 2.2.13).
Port P0 direction register (address 0116
)
b7
b0
P0D
1
1
1 1 0 0 0
0
Bits corresponding to P07 to P00
0: Input port
1: Output port
Port P0 pull-up control register (address 0FF016
)
b7
b0
PULL0
1
1 1
1
P00 to P03 pull-up
Interrupt request register 2 (address 3D16
)
b7
b0
0
IREQ2
ICON2
Key-on wake-up interrupt request
Interrupt control register 2 (address 3F16
)
b7
b0
0
1
Key-on wake-up interrupt: Enabled
Fig. 2.2.14 Registers setting related to key input interrupt (corresponding to Figure 2.2.13)
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2.2 Interrupt
38K2 Group
2.2.8 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 0FF316
•Timer X mode register (address 2316
)
)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active edge switch
bit) or the interrupt (source) select bit to “1”.
↓
NOP (One or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 2.2.15 Sequence of changing relevant register
ꢀ Reason
When setting the following, the interrupt request bit may be set to “1”.
•When setting external interrupt active edge
Concerned register: Interrupt edge selection register (address 0FF316
Timer X mode register (address 2316
)
)
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APPLICATION
2.2 Interrupt
38K2 Group
(2) Check of interrupt request bit
ꢀ When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one or
more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 2.2.16 Sequence of check of interrupt request bit
ꢀ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
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2.3 Timer
38K2 Group
2.3 Timer
This paragraph explains the registers setting method and the notes related to the timers.
2.3.1 Memory map
002016
Prescaler 12 (PRE12)
Timer 1 (T1)
002116
002216
002316
002416
002516
Timer 2 (T2)
Timer X mode register (TM)
Prescaler X (PREX)
Timer X (TX)
003C16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
003D16
003E16
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
003F16
Fig. 2.3.1 Memory map of registers related to timers
2.3.2 Related registers
Prescaler 12, Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12) [Address : 2016
]
Prescaler X (PREX) [Address : 2416
]
B
At reset
Name
R W
Function
0
1
2
1
1
1
•Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres-
ponding prescaler is read out.
3
4
1
1
1
5
6
7
1
1
Fig. 2.3.2 Structure of Prescaler 12, Prescaler X
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2.3 Timer
38K2 Group
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2116
]
B
At reset
Name
R W
Function
0
1
2
1
0
0
•Set a count value of timer 1.
•The value set in this register is written to both timer 1 and timer 1
latch at the same time.
•When this register is read out, the timer 1’s count value is read
out.
3
4
0
0
0
5
6
7
0
0
Fig. 2.3.3 Structure of Timer 1
Timer 2, Timer X
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address : 2216
]
Timer X (TX) [Address : 2516
]
At reset
Name
•Set a count value of each timer.
R W
B
0
Function
1
•The value set in this register is written to both each timer and
each timer latch at the same time.
•When this register is read out, each timer’s count value is read
out.
1
2
1
1
1
1
3
4
5
6
7
1
1
1
Fig. 2.3.4 Structure of Timer 2, Timer X
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2.3 Timer
38K2 Group
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register (TM) [Address : 2316
]
At reset
Function
B
Name
R W
b1 b0
Timer X operating mode bits
0
0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement
mode
1
2
0
0
The function depends on the
operating mode of Timer X.
(Refer to Table 2.3.1)
CNTR
bit
0
active edge selection
0 : Count start
1 : Count stop
Timer X count stop bit
3
4
0
0
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are “0”.
5
6
0
0
0
7
Fig. 2.3.5 Structure of Timer X mode register
Table 2.3.1 CNTR0 active edge selection bit function
Timer X operation modes
CNTR0 active edge selection bit
(bits 2 of address 2316) contents
Timer mode
“0” CNTR0 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR0 interrupt request occurrence: Rising edge
; No influence to timer count
“0” Pulse output start: Beginning at “H” level
Pulse output mode
CNTR0 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR0 interrupt request occurrence: Rising edge
“0” Timer X: Rising edge count
Event counter mode
Pulse width measurement mode
CNTR0 interrupt request occurrence: Falling edge
“1” Timer X: Falling edge count
CNTR0 interrupt request occurrence: Rising edge
“0” Timer X: “H” level width measurement
CNTR0 interrupt request occurrence: Falling edge
“1” Timer X: “L” level width measurement
CNTR0 interrupt request occurrence: Rising edge
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2.3 Timer
38K2 Group
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1)
[Address : 3C16
]
At reset R W
Name
USB bus reset
interrupt request bit
B
0
Function
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
USB SOF interrupt
request bit
1
2
0 : No interrupt request issued
1 : Interrupt request issued
USB device interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
EXB interrupt
request bit
3
4
5
0
0
0
INT
0
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
Timer X interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
7
0
0
Timer 2 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
ꢀꢀ “0” can be set by software, but “1” cannot be set.
Fig. 2.3.6 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2)
[Address : 3D16
]
At reset R W
Name
interrupt
request bit
B
0
Function
0 : No interrupt request issued
1 : Interrupt request issued
INT
1
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
USB HUB interrupt
request bit
1
2
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O receive
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O transmit
interrupt request bit
3
4
5
0
0
0
CNTR
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Key-on wake-up
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
A/D conversion
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
7
0
0
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
ꢀꢀ “0” can be set by software, but “1” cannot be set.
Fig. 2.3.7 Structure of Interrupt request register 2
Rev.2.00 Oct 15, 2006 page 26 of 112
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APPLICATION
2.3 Timer
38K2 Group
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1)
[Address : 3E16
]
At reset R W
Name
USB bus reset
interrupt enable bit
Function
B
0
0 : Interrupt disabled
1 : Interrupt enabled
0
USB SOF interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1
2
0
0
USB device interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
EXB interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
3
4
5
0
0
0
INT0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6
7
0
0
Timer 2 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.3.8 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2)
[Address : 3F16
0
]
At reset R W
Name
interrupt
enable bit
B
0
Function
0 : Interrupt disabled
1 : Interrupt enabled
INT
1
0
0 : Interrupt disabled
1 : Interrupt enabled
USB HUB interrupt
enable bit
1
2
0
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O receive
interrupt enable bit
Serial I/O transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
3
4
5
0
0
0
0
0
CNTR0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Key-on wake-up
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
A/D conversion
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6
7
Fix this bit to “0”.
Fig. 2.3.9 Structure of Interrupt control register 2
Rev.2.00 Oct 15, 2006 page 27 of 112
REJ09B0338-0200
APPLICATION
2.3 Timer
38K2 Group
2.3.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer 1, Timer 2)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request
occurs.
<Use>
•Generation of an output signal timing
•Generation of a wait time
[Function 2] Control of Cyclic operation (Timer X, Timer 1, Timer 2)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generation of cyclic interrupts
•Clock function (measurement of 10 ms); see Application example 1
•Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X)
The output level of the CNTR pin is inverted each time the timer underflows (in the pulse output
0
mode).
<Use>
•Piezoelectric buzzer output; see Application example 2
•Generation of the remote control carrier waveforms
[Function 4] Count of External pulses (Timer X)
External pulses input to the CNTR pin are counted as the timer count source (in the event counter
0
mode).
<Use>
•Frequency measurement; see Application example 3
•Division of external pulses
•Generation of interrupts due to a cycle using external pulses as the count source; count of a
reel pulse
[Function 5] Measurement of External pulse width (Timer X)
The “H” or “L” level width of external pulses input to CNTR pin is measured (in the pulse width
0
measurement mode).
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulseꢀ for a
motor); see Application example 4
•Measurement of external pulse duty (when the frequency is fixed)
FG pulseꢀ: Pulse used for detecting the motor speed to control the motor speed.
Rev.2.00 Oct 15, 2006 page 28 of 112
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APPLICATION
2.3 Timer
38K2 Group
(2) Timer application example 1: Clock function (measurement of 10 ms)
Outline: The input clock is divided by the timer so that the clock can count up at 10 ms intervals.
Specifications: •The clock f(XIN) = 6 MHz is divided by the timer.
•The clock is counted up in the process routine of the timer X interrupt which occurs
at 10 ms intervals.
Figure 2.3.10 shows the timers connection and setting of division ratios; Figure 2.3.11 shows the
related registers setting; Figure 2.3.12 shows the control procedure.
Dividing by 100 with software
Timer X interrupt
request bit
Fixed
1/16
Prescaler X
1/30
Timer X
1/125
f(XIN) = 6 MHz
0 or 1
1/100
1 second
10 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.3.10 Timers connection and setting of division ratios
Timer X mode register (address 2316)
b7
b0
1
0
0
TM
Timer X operating mode: Timer mode
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 2416)
b7
b0
PREX
29
Set “division ratio – 1”
Timer X (address 2516)
b7
b0
TX
124
Interrupt request register 1 (address 3C16)
b0
b7
IREQ1
0
Timer X interrupt request
(becomes “1” at 10 ms intervals)
Interrupt control register 1 (address 3E16)
b7
b0
1
ICON1
Timer X interrupt: Enabled
Fig. 2.3.11 Related registers setting
Rev.2.00 Oct 15, 2006 page 29 of 112
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APPLICATION
2.3 Timer
38K2 Group
RESET
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
•All interrupts disabled
SEI
TM
•Timer X operating mode : Timer mode
•Timer X interrupt request bit cleared
•Timer X interrupt enabled
(address 2316) ← xxxx1x00
2
IREQ1 (address 3C16) ← xx0xxxxx
ICON1 (address 3E16), bit5 ← 1
2
•“Division ratio – 1” set to Prescaler X and Timer X
PREX
TX
(address 2416
(address 2516
)
)
← 30 – 1
← 125 – 1
TM
CLI
(address 2316), bit3 ← 0
•Timer X count start
•Interrupts enabled
Main processing
<Procedure for completion of clock set>
(Note 1)
TM
(address 2316), bit3 ← 1
•Timer X count stop
PREX
TX
(address 2416
(address 2516
)
)
← 30 – 1
← 125 – 1
•Timer reset to restart count from 0 second after completion of
clock set
IREQ1 (address 3C16), bit5 ← 0
TM (address 2316), bit3 ← 0
•Timer X count start
Note 1: Perform procedure for completion of clock set only
when completing clock set.
Timer X interrupt process routine
Note 2: When using Index X mode flag (T)
Note 3: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
CLT (Note 2)
CLD (Note 3)
Push registers to stack
Y
•Judgment whether clock stops
Clock stop ?
N
Clock count up (1/100 second to year)
•Clock counted up
Pop registers
RTI
•Pop registers pushed to stack
Fig. 2.3.12 Control procedure
Rev.2.00 Oct 15, 2006 page 30 of 112
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APPLICATION
2.3 Timer
38K2 Group
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 6 MHz into about 2 kHz (2038
Hz), is output from the P5
1
/CNTR
0
pin.
•The level of the P5
1
/CNTR
0
pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.3.13 shows a peripheral circuit example, and Figure 2.3.14 shows the timers connection and
setting of division ratios. Figures 2.3.15 shows the related registers setting, and Figure 2.3.16 shows
the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
CNTR
0
output
P5
1
/CNTR
0
PiPiPi.....
245 µs 245 µs
Set a division ratio so that the
underflow output period of the timer X
can be 245 s.
38K2 Group
µ
Fig. 2.3.13 Peripheral circuit example
Fixed
1/16
Prescaler X
1
Timer X
1/92
Fixed
1/2
f(XIN) = 6 MHz
CNTR
0
Fig. 2.3.14 Timers connection and setting of division ratios
Rev.2.00 Oct 15, 2006 page 31 of 112
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APPLICATION
2.3 Timer
38K2 Group
Timer X mode register (address 2316
)
b7
b0
TM
1
0 0
1
Timer X operating mode: Pulse output mode
CNTR0 active edge selection: Output starting at “H” level
Timer X count: Stop
Clear to “0” when starting count.
Timer X (address 2516
)
b7
b0
91
TX
Set “division ratio – 1”.
Prescaler X (address 2416
)
b0
b7
PREX
0
Fig. 2.3.15 Related registers setting
RESET
Initialization
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
1
P5
P5D
(address 0A16), bit1
(address 0B16
XXXxXX1X2
)
(address 3E16), bit4
•Timer X interrupt disabled
•CNTR output stop; Piezoelectric buzzer output stop
•“Division ratio – 1” set to Timer X and Prescaler X
ICON1
TM
TX
0
(address 2316
(address 2516
(address 2416
)
)
)
0
XXXX1001
92 – 1
1 – 1
2
PREX
Main processing
Output unit
•Processing piezoelectric buzzer request, generated during
main processing, in output unit
Yes
Piezoelectric buzzer request ?
No
TM (address 2316), bit3
0
TM (address 2316), bit3
TX (address 2516
1
)
92 – 1
Piezoelectric buzzer output start
Stop piezoelectric buzzer output
Fig. 2.3.16 Control procedure
Rev.2.00 Oct 15, 2006 page 32 of 112
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APPLICATION
2.3 Timer
38K2 Group
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P5
•A reference value
1
/CNTR
0
pin with the timer.
Specifications: •The pulse is input to the P5
1
/CNTR
0
pin and counted by the timer X.
•A count value is read out at about 2 ms intervals, the timer 1 interrupt interval.
When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid value.
Figure 2.3.17 shows the judgment method of valid/invalid of input pulses; Figure 2.3.18 shows the
related registers setting; Figure 2.3.19 shows the control procedure.
......
......
......
Input pulse
71.4 µs or more
(14 kHz or less)
Invalid
71.4 µs
(14 kHz)
50 µs
(20 kHz)
50 µs or less
(20 kHz or more)
Invalid
Valid
2 ms
2 ms
= 28 counts
= 40 counts
50 µs
71.4 µs
Fig. 2.3.17 Judgment method of valid/invalid of input pulses
Rev.2.00 Oct 15, 2006 page 33 of 112
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APPLICATION
2.3 Timer
38K2 Group
Timer X mode register (address 2316)
b7
b0
TM
1
1 1
0
Timer X operating mode: Event counter mode
CNTR0 active edge selection: Falling edge count
Timer X count: Stop
Clear to “0” when starting count.
Prescaler 12 (address 2016)
b7
b0
PRE12
2
Timer 1 (address 2116)
b7
b0
T1
249
Set “division ratio – 1”.
Prescaler X (address 2416)
b7
b0
PREX
0
Timer X (address 2516)
b7
b0
Set 255 just before counting pulses.
(After a certain time has passed, the number of input
pulses is decreased from this value.)
TX
255
Interrupt control register 1 (address 3E16)
b7
b0
1
0
ICON1
Timer X interrupt: Disabled
Timer 1 interrupt: Enabled
Interrupt request register 1 (address 3C16)
b7
b0
0
IREQ1
Judge Timer X interrupt request bit.
( “1” of this bit when reading the count value indicates the 256 or more
pulses input in the condition of Timer X = 255)
Fig. 2.3.18 Related registers setting
Rev.2.00 Oct 15, 2006 page 34 of 112
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APPLICATION
2.3 Timer
38K2 Group
RESET
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrary.
•All interrupts disabled
Initialization
SEI
TM
(address 2316) ← XXXX11102
•Timer X operating mode : Event counter mode
PRE12 (address 2016) ← 3 – 1
(Count a falling edge of pulses input from CNTR0 pin.)
T1
(address 2116) ← 250 – 1
•Division ratio set so that Timer 1 interrupt will occur at
PREX
TX
(address 2416
(address 2516
)
)
← 1 – 1
← 256 – 1
2 ms intervals.
ICON1 (address 3E16), bit6 ← 1
•Timer 1 interrupt enabled
•Timer X count start
TM
CLI
(address 2316), bit3 ← 0
•Interrupts enabled
Timer 1 interrupt process routine
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
1
•Processing as out of range when the count value is 256 or more
IREQ1(address 3C16), bit5 ?
0
•Count value read
•Count value into Accumulator (A) stored
(A)
← TX (address 2516
)
In range
•Read value with reference value
compared
214 < (A) < 228
•Comparison result to flag Fpulse
stored
Out of range
Fpulse ← 0
Fpulse ← 1
•Counter value initialized
•Timer X interrupt request bit cleared
TX
(address 2516
)
← 256 – 1
IREQ1 (address 3C16), bit5 ← 0
Process judgment result
Pop registers
•Pop registers pushed to stack
RTI
Fig. 2.3.19 Control procedure
Rev.2.00 Oct 15, 2006 page 35 of 112
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APPLICATION
2.3 Timer
38K2 Group
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the P5
1
/CNTR pin. An
0
underflow is detected by the timer X interrupt and an end of the input pulse “H” level is
detected by the CNTR interrupt.
0
Specifications: •The timer X counts the “H” level width of the FG pulse input to the P5
1
/CNTR pin.
0
<Example>
When the clock frequency is 6 MHz, the count source is 2.67 µs, which is obtained by dividing the
clock frequency by 16. Measurement can be performed to 175 ms in the range of FFFF16 to 000016
.
Figure 2.3.20 shows the timers connection and setting of division ratio; Figure 2.3.21 shows the
related registers setting; Figure 2.3.22 shows the control procedure.
Timer X interrupt
request bit
Prescaler X
1/256
Timer X
1/256
Fixed
1/16
0 or 1
f(XIN) = 6 MHz
175 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.3.20 Timers connection and setting of division ratios
Rev.2.00 Oct 15, 2006 page 36 of 112
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APPLICATION
2.3 Timer
38K2 Group
Timer X mode register (address 2316
)
b7
b0
1
0 1
1
TM
Timer X operating mode: Pulse width measurement mode
CNTR0 active edge selection: “H” level width measurement
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 2416
)
b7
b0
PREX
255
Set “division ratio – 1”.
Timer X (address 2516
)
b7
b0
TX
255
Interrupt control register 1 (address 3E16
)
b0
b7
ICON1
1
Timer X interrupt: Enabled
Interrupt request register 1 (address 3C16
)
b7
b0
IREQ1
0
Timer X interrupt request
(Set to “1” automatically when Timer X underflows)
Interrupt control register 2 (address 3F16
)
b0
b7
ICON2
1
CNTR
0
interrupt: Enabled
Interrupt request register 2 (address 3D16
)
b0
b7
IREQ2
0
CNTR
0
interrupt request
(Set to “1” automatically when “H” level input came to the end)
Fig. 2.3.21 Related registers setting
Rev.2.00 Oct 15, 2006 page 37 of 112
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APPLICATION
2.3 Timer
38K2 Group
RESET
ꢀꢀx: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
•All interrupts disabled
•Timer X operating mode : Pulse width measurement mode
(Measure “H” level of pulses input from CNTR0 pin.)
•Set division ratio so that Timer X interrupt will occur at
175 ms intervals.
•Timer X interrupt request bit cleared
•Timer X interrupt enabled
TM
PREX
TX
(address 2316) ← XXXX1011
(address 2416) ← 256 – 1
(address 2516) ← 256 – 1
2
IREQ1 (address 3C16), bit5 ← 0
ICON1 (address 3E16), bit5 ← 1
IREQ2 (address 3D16), bit4 ← 0
ICON2 (address 3F16), bit4 ← 1
•CNTR
0
interrupt request bit cleared
interrupt enabled
•CNTR
0
•Timer X count start
•Interrupts enabled
TM
CLI
(address 2316), bit3 ← 0
Timer X interrupt process routine
•Error occurs
Process errors
RTI
CNTR0 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
•Read the count value and store it to RAM
(A)
← PREX
Low-order 8-bit result of ← Inverted (A)
pulse width measurement
(A)
← TX
High-order 8-bit result of ← Inverted (A)
pulse width measurement
•Division ratio set so that Timer X interrupt will occur at
PREX (address 2416) ← 256 – 1
175 ms intervals.
TX
(address 2516) ← 256 – 1
•Pop registers pushed to stack
Pop registers
RTI
Fig. 2.3.22 Control procedure
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APPLICATION
2.3 Timer
38K2 Group
2.3.4 Notes on timer
ꢀ If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
ꢀ When switching the count source by the timer X count source selection bit, the value of timer count
is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
Rev.2.00 Oct 15, 2006 page 39 of 112
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APPLICATION
2.4 Serial I/O
38K2 Group
2.4 Serial I/O
This paragraph explains the registers setting method and the notes related to the Serial I/O.
2.4.1 Memory map
~
~
~
~
002616 Transmit/Receive buffer register (TB/RB)
002716 Serial I/O status register (SIOSTS)
~
~
~
~
003D16 Interrupt request register 2 (IREQ2)
~
~
~
~
003F16
Interrupt control register 2 (ICON2)
~
~
~
~
Serial I/O control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
0FE016
0FE116
0FE216
~
~
~
~
Interrupt edge selection register (INTEDGE)
0FF316
~
~
~
~
Fig. 2.4.1 Memory map of registers related to Serial I/O
Rev.2.00 Oct 15, 2006 page 40 of 112
REJ09B0338-0200
APPLICATION
2.4 Serial I/O
38K2 Group
2.4.2 Related registers
Transmit/Receive buffer register
b1
b7 b6 b5 b4 b3 b2
b0
Transmit/Receive buffer register (TB/RB) [Address : 2616]
B
At reset
Name
R W
Function
0
1
2
?
?
?
The transmission data is written to or the receive data is read out
from this buffer register.
• At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
out.
3
4
?
?
?
5
6
7
?
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 2.4.2 Structure of Transmit/Receive buffer register
Serial I/O status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O status register (SIOSTS) [Address : 2716
]
At reset
Function
0 : Buffer full
1 : Buffer empty
B
0
Name
Transmit buffer empty flag
R W
ꢀ
0
(TBE)
0 : Buffer empty
1 : Buffer full
1
2
Receive buffer full flag (RBF)
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : Transmit shift in progress
1 : Transmit shift completed
Transmit shift register shift
completion flag (TSC)
0 : No error
1 : Overrun error
Overrun error flag (OE)
3
4
5
0
0
0
0 : No error
1 : Parity error
Parity error flag (PE)
0 : No error
1 : Framing error
Framing error flag (FE)
Summing error flag (SE)
0 : (OE) U (PE) U (FE) = 0
1 : (OE) U (PE) U (FE) = 1
6
7
0
1
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the contents are “1”.
Fig. 2.4.3 Structure of Serial I/O status register
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APPLICATION
2.4 Serial I/O
38K2 Group
Serial I/O control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address : 0FE016
]
At reset
Name
B
0
Function
R W
BRG count source
selection bit (CSS)
Serial I/O synchronous
clock selection bit (SCS)
0 : System clock
1 : System clock/4
0
0
1
• In clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
• In UART
0 : BRG output divided by 16
1 : External clock input divided by 16
0 : P4
1 : P4
3
3
pin operates as ordinary I/O pin
pin operates as SRDY output pin
2
3
0
0
S
RDY output enable bit
(SRDY)
Transmit interrupt
source selection bit (TIC)
0 : Interrupt when transmit buffer has emptied
1 : Interrupt when transmit shift operation is
completed
0
0
0
Transmit enable bit (TE)
Receive enable bit (RE)
0 : Transmit disabled
1 : Transmit enabled
4
0 : Receive disabled
1 : Receive enabled
5
6
Serial I/O mode selection bit
(SIOM)
0 : Clock asynchronous(UART) serial I/O
1 : Clock synchronous serial I/O
Serial I/O enable bit
(SIOE)
0 : Serial I/O disabled
0
7
(pins P4
1 : Serial I/O enabled
(pins P4 to P4 operate as serial I/O pins)
0 to P43 operate as ordinary I/O pins)
0
3
Fig. 2.4.4 Structure of Serial I/O control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 0FE116
]
At reset
Name
R W
Function
B
0
Character length selection bit
(CHAS)
0 : 8 bits
1 : 7 bits
0
Parity enable bit
(PARE)
0 : Parity checking disabled
1 : Parity checking enabled
1
2
0
0
Parity selection bit
(PARS)
0 : Even parity
1 : Odd parity
Stop bit length selection bit
(STPS)
0 : 1 stop bit
1 : 2 stop bits
3
4
0
0
Nothing is allocated for this bit. This is a write disabled bit.
ꢀ
When this bit is read out, the contents are “0”.
5
6
7
1
1
1
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the contents are “1”.
ꢀ
ꢀ
ꢀ
Fig. 2.4.5 Structure of UART control register
Rev.2.00 Oct 15, 2006 page 42 of 112
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APPLICATION
2.4 Serial I/O
38K2 Group
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 0FE216
]
At reset
Function
B
0
R W
Set a count value of baud rate generator.
?
?
?
1
2
3
4
?
?
?
5
6
7
?
?
Fig. 2.4.6 Structure of Baud rate generator
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE)
[Address : 0FF316
]
Function
0 : Falling edge active
1 : Rising edge active
At reset R W
Name
interrupt edge
selection bit
B
0
INT
0
0
0
0
Nothing is arranged for this bits. This is a write disabled bit.
1
2
When this bit is read out, the contents are “0”.
INT
1
interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
3
4
5
0
0
0
6
7
0
0
Fig. 2.4.7 Structure of Interrupt edge selection register
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2.4 Serial I/O
38K2 Group
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2)
[Address : 3D16
]
At reset R W
Name
interrupt
request bit
B
0
Function
0 : No interrupt request issued
1 : Interrupt request issued
INT
1
0
0
0
ꢀ
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
USB HUB interrupt
request bit
1
2
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O receive
interrupt request bit
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O transmit
interrupt request bit
3
4
5
0
0
0
CNTR
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Key-on wake-up
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
A/D conversion
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
7
0
0
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
ꢀꢀ “0” can be set by software, but “1” cannot be set.
Fig. 2.4.8 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2)
[Address : 3F16
0
]
At reset R W
Name
interrupt
enable bit
B
0
Function
0 : Interrupt disabled
1 : Interrupt enabled
INT
1
0
USB HUB interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1
2
0
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O receive
interrupt enable bit
Serial I/O transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
3
4
5
0
0
0
0
0
CNTR0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Key-on wake-up
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
A/D conversion
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6
7
Fix this bit to “0”.
Fig. 2.4.9 Structure of Interrupt control register 2
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APPLICATION
2.4 Serial I/O
38K2 Group
2.4.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.4.10 shows connection examples of a peripheral IC equipped with the CS pin.
There are connection examples using a clock synchronous serial I/O mode.
(1) Only transmission
(2) Transmission and reception
(Using the RXD pin as an I/O port)
Port
SCLK
CS
CLK
IN
Port
SCLK
CS
CLK
DATA
TXD
RXD
TXD
OUT
38K2 group
Peripheral IC
(OSD controller etc.)
Peripheral IC
(E2 PROM etc.)
38K2 group
(4) Connection of plural IC
(3) Transmission and reception
(When connecting RXD with TXD
(When connecting IN with OUT in
peripheral IC)
Port
SCLK
TXD
CS
CLK
IN
Port
SCLK
CS
CLK
IN
RXD
Port
OUT
TXD
RXD
Peripheral IC 1
OUT
38K2 group ꢀ1 Peripheral ICꢀ2
38K2 group
(E2 PROM etc.)
CS
CLK
IN
ꢀ1: Select an N-channel open-drain output for TXD pin output control.
ꢀ2: Use the OUT pin of peripheral IC which is an N-channel open-
drain output and becomes high impedance during receiving data.
OUT
Peripheral IC 2
Notes: “Port” means an output port controlled by software.
Fig. 2.4.10 Serial I/O connection examples (1)
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2.4 Serial I/O
38K2 Group
(2) Connection with microcomputer
Figure 2.4.11 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
SCLK
CLK
SCLK
CLK
IN
TXD
D
TX
D
D
IN
RX
RX
OUT
OUT
38K2 group
Microcomputer
Microcomputer
38K2 group
(3) Using
SRDY signal output function
(4) In UART
(Selecting an external clock)
S
RDY
RDY
CLK
IN
T
X
D
D
R
X
D
SCLK
RX
T
X
D
T
X
D
D
OUT
R
X
38K2 group Microcomputer
38K2 group
Microcomputer
Fig. 2.4.11 Serial I/O connection examples (2)
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2.4 Serial I/O
38K2 Group
2.4.4 Setting of serial I/O transfer data format
A clock synchronous or clock asynchronous (UART) can be selected as a data format of Serial I/O.
Figure 2.4.12 shows the serial I/O transfer data format.
1ST-8DATA-1SP
ST
LSB
MSB
SP
SP
1ST-7DATA-1SP
ST
LSB
MSB
MSB
MSB
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
MSB
2SP
PAR SP
1ST-7DATA-1PAR-1SP
ST
LSB
SP
UART
1ST-8DATA-2SP
ST
LSB
2SP
1ST-7DATA-2SP
ST
LSB
Serial I/O
1ST-8DATA-1PAR-2SP
ST
LSB
MSB PAR
2SP
1ST-7DATA-1PAR-2SP
ST
LSB
MSB PAR
2SP
Clock synchronous
Serial I/O
LSB first
ST : Start bit
SP : Stop bit
PAR : Parity bit
Fig. 2.4.12 Serial I/O transfer data format
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2.4 Serial I/O
38K2 Group
2.4.5 Serial I/O application examples
(1) Communication using clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O.
________
The SRDY signal is used for communication control.
Figure 2.4.13 shows a connection diagram, and Figure 2.4.14 shows a timing chart.
Figure 2.4.15 shows a registers setting related to the transmitting side, and Figure 2.4.16 shows
registers setting related to the receiving side.
Transmitting side
Receiving side
P52/INT
1
S
RDY
SCLK
SCLK
RXD
TXD
38K2 group
38K2 group
Fig. 2.4.13 Connection diagram
Specifications : • The Serial I/O is used (clock synchronous serial I/O is selected.)
• Synchronous clock frequency : 125 kHz (f(XIN) = 6 MHz is divided by 48)
• The SRDY (receivable signal) is used.
• The receiving side outputs the SRDY signal at intervals of 2 ms (generated by timer),
and 2-byte data is transferred from the transmitting side to the receiving side.
• • • •
SRDY
• • • •
SCLK
TX
D
• • • •
D0
D1
D2
D3
D4
D5
D6
D7
D
0
D1
D2
D3
D4
D
5
D6
D7
D0
D1
2 ms
Fig. 2.4.14 Timing chart
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2.4 Serial I/O
38K2 Group
Transmitting side
Serial I/O status register (Address : 2716
)
b7
b0
SIOSTS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O control register (Address : 0FE016
)
b7
b0
SIOCON
1
1
1
0 0
0
BRG counter source selection bit : f(XIN
)
Serial I/O synchronous clock selection bit : BRG/4
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O mode selection bit : Clock synchronous serial I/O
Serial I/O enable bit : Serial I/O enabled
Baud rate generator (Address : 0FE216
)
b7
b0
Set “division ratio – 1”.
BRG
11
Interrupt edge selection register (Address : 0FF316
)
b7
b0
0
INTEDGE
INT
1
interrupt edge selection bit : Falling edge active
Fig. 2.4.15 Registers setting related to transmitting side
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Receiving side
Serial I/O status register (Address : 2716)
b7
b0
SIOSTS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : At completing reception
“0” : At reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing.
Summing error flag
“1” : when any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O control register (Address : 0FE016)
b7
b0
SIOCON 1 1 1 1
1 1
Serial I/O synchronous clock selection bit : External clock
SRDY output enable bit : SRDY output enabled
Transmit enable bit : Transmit enabled
Set this bit to “1”, using SRDY output.
Receive enable bit : Receive enabled
Serial I/O mode selection bit : Clock synchronous serial I/O
Serial I/O enable bit : Serial I/O enabled
Fig. 2.4.16 Registers setting related to receiving side
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Figure 2.4.17 shows a control procedure of the transmitting side, and Figure 2.4.18 shows a control
procedure of the receiving side.
RESET
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SIOCON (Address : 0FE016) ← 1101xx00
2
BRG
(Address : 0FE216) ← 12 – 1
INTEDGE (Address : 0FF316), bit2 ← 0
0
IREQ2 (Address:3D16), bit0?
• Detection of INT1 falling edge
1
IREQ2 (Address : 3D16), bit0 ← 0
The first byte of a
transmission data
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
TB/RB (Address : 2616
)
0
SIOSTS (Address : 2716), bit0?
1
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
The second byte of a
transmission data
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
TB/RB (Address : 2616
)
0
0
SIOSTS (Address : 2716), bit0?
1
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
SIOSTS (Address : 2716), bit2?
1
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
Fig. 2.4.17 Control procedure of transmitting side
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RESET
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SIOCON (Address : 0FE016
)
1111x11x
2
N
Pass 2 ms?
Y
• An interval of 2 ms generated by Timer
TB/RB (Address : 2616
)
Dummy data
•
S
RDY output
RDY signal is output by writing data to the TB/RB.
Using the RDY, set Transmit enable bit
(bit4) of the SIOCON to “1.”
S
S
0
SIOSTS (Address : 2716), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Read out reception data from
Receive buffer full flag is set to “0” by reading data.
TB/RB (Address : 2616
)
0
SIOSTS (Address : 2716), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
Read out reception data from
• Reception of the second byte data.
Receive buffer full flag is set to “0” by reading data.
TB/RB (Address : 2616
)
Fig. 2.4.18 Control procedure of receiving side
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38K2 Group
(2) Output of serial data (control of peripheral IC)
Outline : 4-byte data is transmitted and received, using the clock synchronous serial I/O.
The CS signal is output to a peripheral IC through port P5
3
.
The example for using Serial I/O is shown.
Figure 2.4.19 shows a connection diagram, and Figure 2.4.20 shows a timing chart.
CS
P53
CS
CLK
DATA
S
CLK
CLK
DATA
TXD
38K2 group
Peripheral IC
Example for using Serial I/O
Fig. 2.4.19 Connection diagram
Specifications : • The Serial I/O is used (clock synchronous serial I/O is selected.)
• Synchronous clock frequency : 125 kHz (f(XIN) = 6 MHz is divided by 48)
• Transfer direction : LSB first
• The Serial I/O interrupt is not used.
• Port P5
3
is connected to the CS pin (“L” active) of the peripheral IC for transmission
is controlled by software.
control; the output level of port P5
3
CS
CLK
DATA
DO0
DO1
DO2
DO3
Fig. 2.4.20 Timing chart
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Figure 2.4.21 shows registers setting related to Serial I/O, and Figure 2.4.22 shows a setting of serial
I/O transmission data.
Serial I/O control register (Address : 0FE016
b7 b0
)
SIOCON
1 1 0 1 1 0 0 0
BRG count source selection bit : f(XIN
)
Serial I/O synchronous clock selection bit : BRG/4
S
RDY output enable bit : RDY output disabled
S
Transmit interrupt source selection bit : Transmit shift operating
completion
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O mode selection bit : Clock synchronous serial I/O
Serial I/O enable bit : Serial I/O enabled
Baud rate generator (Address : 0FE216
b7 b0
)
11
BRG
Set “division ratio – 1”.
Interrupt control register 2 (Address : 3F16
b7 b0
)
ICON2
0
Serial I/O transmit interrupt enable bit : Interrupt disabled
Interrupt request register 2 (Address : 3D16
b7 b0
)
IREQ2
0
Serial I/O transmit interrupt request bit
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Fig. 2.4.21 Registers setting related to Serial I/O
Transmit/Receive buffer register (Address : 2616
)
b7
b0
Set a transmission data.
TB/RB
Confirm that transmission of the previous data is
completed (bit 3 of the Interrupt request register 2
is “1”) before writing data.
Fig. 2.4.22 Setting of serial I/O transmission data
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2.4 Serial I/O
38K2 Group
When the registers are set as shown in Fig. 2.4.21, the Serial I/O can transmit 1-byte data by writing
data to the transmit buffer register.
Thus, after setting the CS signal to “L”, write the transmission data to the transmit buffer register by
each 1 byte, and return the CS signal to “H” when the target number of bytes has been transmitted.
Figure 2.4.23 shows a control procedure of Serial I/O.
ꢀꢀx: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
•Serial I/O set
SIOCON (Address : 0FE016)← 11011000
UARTCON (Address : 0FE116), bit4 ← 0
2
BRG
ICON2
P5
(Address : 0FE216
)
← 12–1
(Address : 3F16), bit3
(Address : 0A16), bit3
← 0
← 1
•Serial I/O transmit interrupt : Disabled
P5D
(Address : 0B16)← xxxx1xxx
2
•CS signal output port set
(“H” level output)
P5 (Address : 0A16), bit3
←
0
•CS signal output level to “L” set
•Serial I/O transmit interrupt
request bit set to “0”
IREQ2 (Address : 3D16), bit3 ← 0
•
Transmission data write
(Start of transmit 1-byte data)
a transmission
data
TB/RB (Address : 2616
)
0
•Judgment of completion of transmitting
1-byte data
IREQ2 (Address : 3D16), bit3?
1
•Use any of RAM area as a counter for counting
the number of transmitted bytes
•Judgment of completion of transmitting the target
number of bytes
N
Complete to transmit data?
Y
•Return the CS signal output level to “H”
when transmission of the target number
of bytes is completed
P5 (Address : 0A16), bit3 ← 1
Fig. 2.4.23 Control procedure of Serial I/O
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2.4 Serial I/O
38K2 Group
(3) Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.4.24 shows a connection diagram.
S
CLK
S
CLK
T
X
D
D
R
X
D
D
RX
T
X
Master unit
Slave
Fig. 2.4.24 Connection diagram
Specifications :
• The serial I/O is used (clock synchronous serial I/O is selected).
• Synchronous clock frequency : 125 kHz (f(XIN) = 6 MHz is divided by 48)
• Byte cycle: 488 µs
• Number of bytes for transmission or reception : 8 byte/block
• Block transfer cycle : 16 ms
• Block transfer term : 3.5 ms
• Interval between blocks : 12.5 ms
• Heading adjustment time : 8 ms
Limitations of specifications :
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O receive
interrupt request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
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2.4 Serial I/O
38K2 Group
The communication is performed according to the timing shown in Figure 2.4.25. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjustment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.4.26 shows related registers setting.
D0
D1
D2
D7
D0
Byte cycle
Interval between blocks
Block transfer term
Block transfer cycle
Heading adjustment time
Processing for heading adjustment
Fig. 2.4.25 Timing chart
Master unit
Slave unit
Serial I/O control register (Address : 0FE016
)
Serial I/O control register (Address : 0FE016
)
b7 b0
b7
b0
1 1 1 1 1 0 0 0
1 1
0 1
SIOCON 1 1
SIOCON
BRG count source : f(XIN
)
Not affected by external clock
Synchronous clock : BRG/4
RDY output disabled
Synchronous clock : External clock
S
SRDY output disabled
Transmit interrupt source :
Transmit shift operating completion
Transmit enabled
Not use the serial I/O transmit interrupt
Transmit enabled
Receive enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O enabled
Clock synchronous serial I/O
Serial I/O enabled
Both of units
Baud rate generator (Address : 0FE216
)
b7 b0
BRG
Set “division ratio – 1”.
11
Fig. 2.4.26 Related registers setting
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2.4 Serial I/O
38K2 Group
Control procedure :
ꢀ Control in the master unit
After setting the related registers shown in Figure 2.4.26, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the transmit buffer register.
To perform the communication in the timing shown in Figure 2.4.25, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the transmit
buffer register.
Figure 2.4.27 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 488 µs
CLT (Note 1)
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
•Push the register used in the interrupt
CLD (Note 2)
Push register to stack
processing routine into the stack
N
Within a block
transfer term?
•Generation of a certain block interval
by using a timer or other functions
Y
•Check the block interval counter and
determine to start a block transfer
Count a block interval counter
Read a reception data
N
Y
Complete to transfer a
block?
Start a block transfer?
Y
N
Write the first transmission data
(first byte) in a block
Write a transmission data
Pop registers
RTI
•Pop registers which is pushed to stack
Fig. 2.4.27 Control procedure of master unit
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38K2 Group
ꢀ Control in the slave unit
After setting the related registers as shown in Figure 2.4.26, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O receive interrupt
request bit is set to “1” each time an 8-bit synchronous clock is received.
In the serial I/O receive interrupt processing routine, the data to be transmitted next is written to
the transmit buffer register after the received data is read out.
However, if no serial I/O receive interrupt occurs for a certain time (heading adjustment time or
more), the following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.4.28 shows a control procedure of the slave unit using the serial I/O receive interrupt and
any timer interrupt (for heading adjustment).
Timer interrupt processing
routine
Serial I/O receive interrupt
processing routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
CLT (Note 1)
CLD (Note 2)
Push register to stack
•Push the register used in the
interrupt processing routine into
the stack
•Confirmation of the received
•Push the register used in
the interrupt processing
routine into the stack
byte counter to judge the
block transfer term
Heading adjustment counter – 1
N
Within a block
transfer term?
Y
N
Heading adjustment
counter = 0?
Read a reception data
Y
Write the first transmission
data (first byte) in a block
A received byte counter +1
A received byte counter
0
Y
A received byte
counter ≥ 8?
N
•Pop registers which is
pushed to stack
Pop registers
RTI
Write a transmission data
Write dummy data (FF16)
Heading
adjustment
counter
Initial
value
(Note 3)
Pop registers
•Pop registers which is pushed to stack
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
RTI
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set 8
as the initial value.
Fig. 2.4.28 Control procedure of slave unit
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(4) Communication (transmit/receive) using asynchronous serial I/O (UART)
Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O.
Port P2
4
is used for communication control.
Figure 2.4.29 shows a connection diagram, and Figure 2.4.30 shows a timing chart.
Transmitting side
Receiving side
P24
P24
T
XD
R
XD
38K2 group
38K2 group
Fig. 2.4.29 Connection diagram (Communication using UART)
Specifications : • The Serial I/O is used (UART is selected).
• Transfer bit rate : 9600 bps (f(XIN) = 6 MHz is divided by 624)
• Communication control using port P2
(The output level of port P2 is controlled by software.)
4
4
• 2-byte data is transferred from the transmitting side to the receiving side at intervals
of 10 ms generated by the timer.
P2
4
.
.....
.....
TXD
.
D0
D1
D2
D3
D4
D5
D6
D7
D
0
D1
D2
D3
D4
D5
D6
D7
D0
ST
ST
ST
SP(2)
SP(2)
10 ms
Fig. 2.4.30 Timing chart (using UART)
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38K2 Group
Table 2.4.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate
values; Figure 2.4.31 shows registers setting related to the transmitting side; Figure 2.4.32 shows
registers setting related to the receiving side.
Table 2.4.1 Setting examples of Baud rate generator values and transfer bit rate values
Transfer bit rate
(bps) (Note 3)
600
At f(XIN) = 8 MHZ
BRG setting value (Note 2)
BRG count source
(Note 1)
At f(XIN) = 6 MHZ
BRG setting value (Note 2)
207
103
207
103
51
34
25
12
8
f(XIN)/4
f(XIN)/4
155
77
155
77
38
25
19
9
1200
2400
4800
9600
14400
19200
38400
57600
f(XIN
f(XIN
f(XIN
f(XIN
f(XIN
f(XIN
f(XIN
)
)
)
)
)
)
)
–
Notes 1: Select the BRG count source with bit 0 of the serial I/O control register (Address : 0FE016).
2: These are setting values with small errors.
3: Equation of transfer bit rate:
f(XIN)
Transfer bit rate (bps) =
(BRG setting value + 1) ꢀ 16 ꢀꢀmꢀ
ꢀm: When bit 0 of the serial I/O control register (Address : 0FE016) is set to “0”, a value of m
is 1.
When bit 0 of the serial I/O control register (Address : 0FE016) is set to “1”, a value of
m is 4.
Rev.2.00 Oct 15, 2006 page 61 of 112
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APPLICATION
2.4 Serial I/O
38K2 Group
Transmitting side
Serial I/O status register (Address : 2716
)
b7
b0
SIOSTS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O control register (Address : 0FE016
)
b7
b0
1 0 0 1
0 0 0
SIOCON
BRG count source selection bit : f(XIN
)
Serial I/O synchronous clock selection bit : BRG/16
RDY output enable bit : RDY out disabled
S
S
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O mode selection bit : Asynchronous serial I/O(UART)
Serial I/O enable bit : Serial I/O enabled
UART control register (Address : 0FE116
)
b7
b0
UARTCON
1
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 0FE216
)
b7
b0
f(XIN
)
–1
Set
38
BRG
ꢀ
Transfer bit rate ꢀ 16 ꢀ m
ꢀ
When bit 0 of the Serial I/O control register (Address : 0FE016) is set to “0,”
a value of m is 1.
When bit 0 of the Serial I/O control register (Address : 0FE016) is set to “1,”
a value of m is 4.
Fig. 2.4.31 Registers setting related to transmitting side
Rev.2.00 Oct 15, 2006 page 62 of 112
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APPLICATION
2.4 Serial I/O
38K2 Group
Receiving side
Serial I/O status register (Address : 2716
)
b7
b0
SIOSTS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : At completing reception
“0” : At reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing.
Summing error flag
“1” : When any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O control register (Address : 0FE016
)
b7
b0
1 0 1 0
0 0 0
SIOCON
BRG count source selection bit : f(XIN
)
Serial I/O synchronous clock selection bit : BRG/16
RDY output enable bit : RDY out disabled
S
S
Transmit enable bit : Transmit disabled
Receive enable bit : Receive enabled
Serial I/O mode selection bit : Asynchronous serial I/O(UART)
Serial I/O enable bit : Serial I/O enabled
UART control register (Address : 0FE116
)
b7
b0
UARTCON
1
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 0FE216
)
b7
b0
f(XIN
)
–1
Set
BRG
38
Transfer bit rate ꢀ 16 ꢀ mꢀ
ꢀ
When bit 0 of the Serial I/O control register (Address : 0FE016) is set to “0,”
a value of m is 1.
When bit 0 of the Serial I/O control register (Address : 0FE016) is set to “1,”
a value of m is 4.
Fig. 2.4.32 Registers setting related to receiving side
Rev.2.00 Oct 15, 2006 page 63 of 112
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APPLICATION
2.4 Serial I/O
38K2 Group
Figure 2.4.33 shows a control procedure of the transmitting side, and Figure 2.4.34 shows a control
procedure of the receiving side.
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SIOCON (Address : 0FE016)←1001x000
2
UARTCON (Address : 0FE116)← 00001000
2
BRG
P2
(Address : 0FE216)← 39–1
(Address : 0416), bit4← 0
P2D
(Address : 0516
)
← xxx1xxxx
2
• Port P2 set for communication control
4
N
Pass 10 ms?
Y
• An interval of 10 ms generated by Timer
• Communication start
P2 (Address : 0416), bit4 ← 1
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
TB/RB (Address : 2616
)
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
SIOSTS (Address : 2716), bit0?
1
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
The second byte of
a transmission data
TB/RB (Address : 2616
)
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
SIOSTS (Address : 2716), bit0?
1
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
SIOSTS (Address : 2716), bit2?
1
• Communication completion
P2 (Address : 0416), bit4 ← 0
Fig. 2.4.33 Control procedure of transmitting side
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APPLICATION
2.4 Serial I/O
38K2 Group
RESET
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SIOCON (Address : 0FE016) ← 1010x000
2
UARTCON (Address : 0FE116)← 00001000
2
BRG
P2D
(Address : 0FE216) ← 39–1
(Address : 0516 ← xxx0xxxx
)
2
0
SIOSTS (Address : 2716), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 2616
)
• Judgment of an error flag
1
0
SIOSTS (Address : 2716), bit6?
0
• Judgment of completion of
receiving
SIOSTS (Address : 2716), bit1?
(Receive buffer full flag)
1
• Reception of the second byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 2616
)
• Judgment of an error flag
1
SIOSTS (Address : 2716), bit6?
0
Processing for error
1
P2 (Address : 0416), bit4?
0
Fig. 2.4.34 Control procedure of receiving side
Rev.2.00 Oct 15, 2006 page 65 of 112
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APPLICATION
2.4 Serial I/O
38K2 Group
2.4.6 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O (Serial I/O)
ꢀ Stop of transmission operation
Clear the serial I/O enable bit and the transmit enable bit to “0” (Serial I/O and transmit disabled).
ꢀ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
ꢀ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (Serial
I/O disabled).
ꢀ Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive
disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
ꢀ Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O enable bit to “0”
(Serial I/O disabled) (refer to (1) ꢀ).
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APPLICATION
2.4 Serial I/O
38K2 Group
(2) Notes when selecting clock asynchronous serial I/O (Serial I/O)
ꢀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
ꢀ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
ꢀ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
ꢀ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
ꢀ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) SRDY output of reception side (Serial I/O)
When signals are output from the SRDY pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O control register again (Serial I/O)
Set the serial I/O control register again after the transmission and the reception circuits are reset by
clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
Can be set with the LDM instruction at the same time
↓
Set both the transmit enable bit (TE) and
the receive enable bit (RE), or one of
them to “1”
Fig. 2.4.35 Sequence of setting serial I/O control register again
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APPLICATION
2.4 Serial I/O
38K2 Group
(5) Data transmission control with referring to transmit shift register completion flag (Serial I/O)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected (Serial I/O)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the SCLK input level. Also, write the transmit data to the transmit buffer
register (serial I/O shift register) at “H” of the SCLK input level.
(7) Transmit interrupt request when transmit enable bit is set (Serial I/O)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
ꢀ Set the interrupt enable bit to “0” (disabled) with CLB instruction.
ꢀ Prepare serial I/O for transmission/reception.
ꢀ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
ꢀ Set the interrupt enable bit to “1” (enabled).
ꢀ Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt bit is set regardless of which of the two timings listed below is selected as the timing for
the transmission interrupt to be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
Rev.2.00 Oct 15, 2006 page 68 of 112
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APPLICATION
38K2 Group
2.5 USB function
2.5 USB function
Some application notes are available on the Web site: “Renesas Technology Corp.” Homepage
USB Device
(http://www.renesas.com/en/usb)
Please refer to them for explanation and application of USB function.
Rev.2.00 Oct 15, 2006 page 69 of 112
REJ09B0338-0200
APPLICATION
38K2 Group
2.6 HUB function
2.6 HUB function
Some application notes are available on the Web site: “Renesas Technology Corp.” Homepage
USB Device
(http://www.renesas.com/en/usb)
Please refer to them for explanation and application of HUB function.
Rev.2.00 Oct 15, 2006 page 70 of 112
REJ09B0338-0200
APPLICATION
38K2 Group
2.7 External bus interface(EXB)
2.7 External bus interface(EXB)
Some application notes are available on the Web site: “Renesas Technology Corp.” Homepage
USB Device
(http://www.renesas.com/en/usb)
Please refer to them for explanation and application of external bus interface.
Rev.2.00 Oct 15, 2006 page 71 of 112
REJ09B0338-0200
APPLICATION
38K2 Group
2.8 A/D converter
2.8 A/D converter
This paragraph explains the registers setting method and the notes related to the A/D converter.
2.8.1 Memory map
003616 AD control register (ADCON)
003716 AD conversion register 1 (AD1)
003816 AD conversion register 2 (AD2)
003D16 Interrupt request register 2 (IREQ2)
003F16 Interrupt control register 2 (ICON2)
Fig. 2.8.1 Memory map of registers related to A/D converter
2.8.2 Related registers
AD control register
b7 b6 b5 b4 b3 b2 b1 b0
AD control register (ADCON) [Address : 3616
]
B
Name
R W
Function
At reset
b2 b1 b0
0
1
2
0
Analog input pin selection bits
0 0 0 : P1
0 0 1 : P1
0 1 0 : P1
0 1 1 : P1
1 0 0 : P1
1 0 1 : P1
1 1 0 : P1
1 1 1 : P1
0
1
2
3
4
5
6
7
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
0 : Conversion in progress
1 : Conversion completed
AD conversion completion bit
1
3
4
5
6
7
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are indefinite.
?
?
?
?
Fig. 2.8.2 Structure of AD control register
Rev.2.00 Oct 15, 2006 page 72 of 112
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APPLICATION
38K2 Group
2.8 A/D converter
AD conversion register 1
b7 b6 b5 b4 b3 b2 b1 b0
AD conversion register 1 (AD1) [Address : 3716
]
B
At reset
R W
Function
0
?
?
?
?
?
?
ꢀ
The read-only register in which the AD conversion’s results are
stored.
1
2
ꢀ
< 8-bit read>
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
b7
b0
b9 b8 b7 b6 b5 b4 b3 b2
3
4
< 10-bit read>
b7
b0
5
6
7
b7 b6 b5 b4 b3 b2 b1 b0
?
?
Fig. 2.8.3 Structure of AD conversion register 1
AD conversion register 2
b7 b6
b4 b3 b2 b1 b0
b5
AD conversion register 2 (AD2) [Address : 38
]
16
0
B
0
At reset
Name
R W
Function
?
ꢀ
The read-only register in which the AD conversion’s results are
stored.
< 10-bit read>
b7
0
b0
ꢀ
?
1
b9 b8
ꢀ
0
0
0
2
3
4
5
6
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the contents are “0”.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
Fix this bit to “0”.
7
Fig. 2.8.4 Structure of AD conversion register 2
Rev.2.00 Oct 15, 2006 page 73 of 112
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APPLICATION
38K2 Group
2.8 A/D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2)
[Address : 3D16
]
At reset R W
Name
interrupt
request bit
B
0
Function
0 : No interrupt request issued
1 : Interrupt request issued
INT
1
0
0
0
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
USB HUB interrupt
request bit
ꢀ
1
2
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O receive
interrupt request bit
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O transmit
interrupt request bit
3
4
5
0
0
0
CNTR
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Key-on wake-up
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
A/D conversion
interrupt request bit
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0 : No interrupt request issued
1 : Interrupt request issued
6
7
0
0
ꢀꢀ “0” can be set by software, but “1” cannot be set.
Fig. 2.8.5 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2)
[Address : 3F16
0
]
At reset R W
Name
interrupt
enable bit
B
0
Function
0 : Interrupt disabled
1 : Interrupt enabled
INT
1
0
0 : Interrupt disabled
1 : Interrupt enabled
USB HUB interrupt
enable bit
1
2
0
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O receive
interrupt enable bit
Serial I/O transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
3
4
5
0
0
0
0
0
CNTR0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Key-on wake-up
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
A/D conversion
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6
7
Fix this bit to “0”.
Fig. 2.8.6 Structure of Interrupt control register 2
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APPLICATION
38K2 Group
2.8 A/D converter
2.8.3 A/D converter application examples
(1) Conversion of analog input voltage
Outline : The analog input voltage input from a sensor is converted to digital values.
Figure 2.8.7 shows a connection diagram, and Figure 2.8.8 shows the related registers setting.
P1
0/DQ
0
/AN
0
Sensor
38K2 Group
Fig. 2.8.7 Connection diagram
Specifications : •The analog input voltage input from a sensor is converted to digital values.
•P1 /DQ /AN pin is used as an analog input pin.
0
0
0
AD control register (address 3616
)
b7
b0
0 0
ADCON
0
0
Analog input pin : P1
A/D conversion start
0/DQ0/AN0 selected
AD conversion register 2 (address 3816
)
b7
b0
(Read-only)
AD2
AD1
0
AD conversion register 1 (address 3716
)
b7 b0
(Read-only)
A result of A/D conversion is stored (Note).
Note: After bit 3 of ADCON is set to “1”, read out that contents.
When reading 10-bit data, read address 003816 before address 003716
when reading 8-bit data, read address 003716 only.
;
When reading 10-bit data, bits 2 to 6 of address 003816 are “0”.
Fig. 2.8.8 Related registers setting
Rev.2.00 Oct 15, 2006 page 75 of 112
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APPLICATION
38K2 Group
2.8 A/D converter
An analog input signal from a sensor is converted to the digital value according to the related
registers setting shown by Figure 2.8.8. Figure 2.8.9 shows the control procedure for 8-bit read, and
Figure 2.8.10 shows the control procedure for 10-bit read.
ꢀ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
•P10/DQ0/AN0 pin selected as analog input pin
•A/D conversion start
ADCON (address 3616) ← XXXX0000
2
0
•Judgment of A/D conversion completion
•Read out of conversion result
ADCON (address 3616), bit3 ?
1
Read out AD1 (address 3716
)
Fig. 2.8.9 Control procedure for 8-bit read
ꢀ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
•P10/DQ0/AN0 pin selected as analog input pin
•A/D conversion start
ADCON (address 3616) ← XXXX0000
2
0
•Judgment of A/D conversion completion
ADCON (address 3616), bit3 ?
1
•Read out of high-order digit (b9, b8) of conversion result
•Read out of low-order digit (b7 – b0) of conversion result
Read out AD2 (address 3816
)
Read out AD1 (address 3716
)
Fig. 2.8.10 Control procedure for 10-bit read
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APPLICATION
38K2 Group
2.8 A/D converter
2.8.4 Notes on A/D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
ꢀ Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion precision to be worse.
(2) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(XIN) is 500 kHz or more
• Do not execute the STP instruction
Rev.2.00 Oct 15, 2006 page 77 of 112
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APPLICATION
38K2 Group
2.9 Watchdog timer
2.9 Watchdog timer
This paragraph explains the registers setting method and the notes related to the watchdog timer.
2.9.1 Memory map
Watchdog timer control register (WDTCON)
003916
003B16 CPU mode register (CPUM)
Fig. 2.9.1 Memory map of registers related to watchdog timer
2.9.2 Related registers
Watchdog timer control register
b5
b7 b6
b4 b3 b2
b0
b1
Watchdog timer control register (WDTCON) [Address : 3916
]
Function
At reset
B
0
Name
R W
ꢀ
1
Watchdog timer H (for read-out of high-order 6 bits)
1
2
ꢀ
1
1
1
1
1
0
0
ꢀ
ꢀ
3
4
ꢀ
ꢀ
5
6
7
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count
source selection bit
0 : Watchdog timer L underflow
1 : System clock/16
Fig. 2.9.2 Structure of Watchdog timer control register
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APPLICATION
38K2 Group
2.9 Watchdog timer
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM: address 3B16
0
1
)
W
At reset
0
R
B
Function
Name
b1 b0
0
Processor mode bits
0 0 : Single-chip mode
0 1 : Not available
1 0 : Not available
1 1 : Not available
1
2
3
*
0 : 0 page
1 : 1 page
0
Stack page selection bit
Fix this bit to “1”.
1
0
0
4
Fix this bit to “0”.
5
6
0 : Main clock f(XIN)
System clock selection bit
1 : fSYN
b7 b6
System clock division ratio
selection bits
0
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
7
*
: The initial value of bit 1 depends on the CNVss level.
Fig. 2.9.3 Structure of CPU mode register
Rev.2.00 Oct 15, 2006 page 79 of 112
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APPLICATION
38K2 Group
2.9 Watchdog timer
2.9.3 Watchdog timer application examples
(1) Detection of program runaway
Outline: If program runaway occurs, let the microcomputer reset, using the internal timer for detection
of program runaway.
Specifications: •An underflow of watchdog timer H is judged to be program runaway, and the
microcomputer is returned to the reset status.
•Before the watchdog timer H underflows, “0” is set into bit 7 of the watchdog timer
control register at every cycle in a main routine.
•Through mode is used as a system clock division ratio.
•An underflow signal of the watchdog timer L is supplied as the count source of
watchdog timer H.
Figure 2.9.4 shows a watchdog timer connection and division ratio setting; Figure 2.9.5 shows the
related registers setting; Figure 2.9.6 shows the control procedure.
Fixed
1/16
Watchdog timer L Watchdog timer H
1/256 1/256
f(XIN) = 6 MHz
Reset
circuit
Internal reset
RESET
STP instruction disable bit
STP instruction
Fig. 2.9.4 Watchdog timer connection and division ratio setting
Rev.2.00 Oct 15, 2006 page 80 of 112
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APPLICATION
38K2 Group
2.9 Watchdog timer
CPU mode register (address 3B16
)
b7
b0
0
0
0
0
1
1
1
CPUM
Processor mode: Single-chip mode
System clock: Main clock
System clock division ratio: f(system clock) (Through mode)
Watchdog timer control register (address 3916
)
b7
b0
0
0
1
WDTCON
Watchdog timer H (for read-out of high-order 6 bits)
Enable STP instruction
Watchdog timer H count source: Watchdog timer L underflow
Fig. 2.9.5 Related registers setting
RESET
Initialization
SEI
•All interrupts disabled
CLT
CLD
•Processor mode: Single-chip mode
•Main clock f(XIN): Operating
•Through mode selected as main clock division ratio
CPUM (address 3B16
:
:
) ← 11001X002
CLI
•Interrupts enabled
•Watchdog timer L underflow selected as Watchdog
timer H count source
•STP instruction enabled
WDTCON (address 3916), bit7,bit6
002
Main processing
:
:
Fig. 2.9.6 Control procedure
2.9.4 Notes on watchdog timer
ꢀMake sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog
timer keeps counting during that term.
ꢀWhen the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.
Rev.2.00 Oct 15, 2006 page 81 of 112
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APPLICATION
2.10 Reset
38K2 Group
2.10 Reset
2.10.1 Connection example of reset IC
1
VCC
Power source
General-purpose
Output
5
4
reset IC
RESET
Delay capacity
GND
3
0.1 µF
VSS
38K2 Group
Fig. 2.10.1 Example of poweron reset circuit
Figure 2.10.2 shows the system example which switches to the RAM backup mode by detecting a drop of
the system power source voltage with the INT interrupt.
System power
source voltage
+5 V
VCC
+
7
VCC1
5
3
RESET
RESET
2
1
VCC2
V1
INT
Cd
INT
VSS
6
38K2 Group
GND
4
M62009L, M62009P, M62009FP
Fig. 2.10.2 RAM backup system
Rev.2.00 Oct 15, 2006 page 82 of 112
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APPLICATION
2.10 Reset
38K2 Group
____________
2.10.2 Notes on RESET pin
Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
ꢀ Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
Rev.2.00 Oct 15, 2006 page 83 of 112
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APPLICATION
38K2 Group
2.11 Frequency synthesizer (PLL)
2.11 Frequency synthesizer (PLL)
This paragraph explains the registers setting method and the notes related to the frequency synthesizer
(PLL circuit).
2.11.1 Memory map
001016 USB control register (USBCON)
003B16 CPU mode register (CPUM)
0FF816
PLL control register (PLLCON)
Fig. 2.11.1 Memory map of registers related to PLL
2.11.2 Related registers
USB control register
b7 b6 b5 b4 b3 b2 b1 b0
USB control register (USBCON)
[Address 1016
]
Function
At reset R W
Name
B
0
0 : Returning to BUS idle state by writing “1” first
and then “0”. (Remote wakeup signal)
1 : K-state output
Remote wakeup bit
0
0 : “L” output mode (valid in TRONE = “1”)
1 : “H” output mode (valid in TRONE = “1”)
0
0
0
0
0
0
0
TrON output control bit
TrON output enable bit
1
2
3
0 : TrON port output disabled (Hi-Z state)
1 : TrON port output enabled
USB reference voltage
control bit
0 : Normal mode (valid in VREFE = “1”)
1 : Low current mode (valid in VREFE = “1”)
USB reference voltage
enable bit
0 : USB reference voltage circuit operation disabled
1 : USB reference voltage circuit operation enabled
4
5
USB difference input
enable bit
0 : Upstream-port difference input circuit operation disabled
1 : Upstream--port difference input circuit operation enabled
0 : External oscillating clock f(XIN
1 : PLL circuit output clock fVCO
)
6
7
USB clock select bit
USB module operation
enable bit
0 : USB module reset
1 : USB module operation enabled
Fig. 2.11.2 Structure of USB control register
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38K2 Group
2.11 Frequency synthesizer (PLL)
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM: address 3B16
0
1
)
W
At reset
0
R
B
Function
Name
b1 b0
0
Processor mode bits
0 0 : Single-chip mode
0 1 : Not available
1 0 : Not available
1 1 : Not available
1
2
3
*
0 : 0 page
1 : 1 page
0
Stack page selection bit
Fix this bit to “1”.
1
0
0
4
Fix this bit to “0”.
5
6
0 : Main clock f(XIN)
System clock selection bit
1 : fSYN
b7 b6
System clock division ratio
selection bits
0
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
7
*
: The initial value of bit 1 depends on the CNVss level.
Fig. 2.11.3 Structure of CPU mode register
PLL control register
b7 b6 b5 b4 b3 b2 b1 b0
PLL control register (PLLCON)
[Address : 0FF816
Name
Nothing is arranged for these bit. These are write disabled bits.
When these bits are read out, the contents are “0”.
]
At reset R W
B
0
1
2
Function
0
b4 b3
3
USB clock division
0
0
0 0 : Divided by 8 (fSYN = fUSB/8)
ratio selection bits
0 1 : Divided by 6 (fSYN = fUSB/6)
4
1 0 : Divided by 4 (fSYN = fUSB/4)
1 1 : Not selected
b6 b5
5
6
PLL operation mode
selection bits
0 0 : Not multiplied (fVCO = fXIN
0 1 : Double (fVCO = fXIN ꢀ 2)
1 0 : Quadruple (fVCO = fXIN ꢀ 4)
)
1 1 : Multiplied by 8 (fVCO = fXIN ꢀ 8)
7
PLL enable bit
0 : Disabled
1 : Enabled
0
Fig. 2.11.4 Structure of PLL control register
Rev.2.00 Oct 15, 2006 page 85 of 112
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APPLICATION
38K2 Group
2.11 Frequency synthesizer (PLL)
2.11.3 Functional description
The frequency synthesizer generates the 48 MHz clock which is multiples of the external input reference
f(XIN) and is needed for operating USB function. When using the USB function, set PLL enable bit of PLL
control register (PLLCON: address 0FF816) to “1” (enabled) to send the 48 MHz PLL output clock (fVCO) into
USB function control unit. Figure 2.11.5 shows the block diagram for the frequency synthesizer circuit.
f
USB
SYN
f(XIN
)
f
VCO
PLL
Division circuit
f
PLLCON
USBCON
(address 0FF816
)
(address 001016)
Fig. 2.11.5 Block diagram for frequency synthesizer circuit
ꢀ fVCO (PLL output clock)
f
VCO is generated by multiplying PLL input clock according to the contents of PLL operation mode
selection bits (bits 6, 5 of PLLCON), where
VCO =f(XIN) ꢀ n, n:value selected by PLL operation mode selection bits
f
Set PLL operation mode selection bits so that fVCO may be set to 48 MHz.
While the PLL enable bit is “0” (disabled), fVCO retains “L” level (except when PLL operation mode
selection bits are set to “00 ”).
2
Table 2.11.1 shows the example of PLL operation mode selection bits setting.
Table 2.11.1 PLL operation mode selection bits setting example
PLL operation mode
f
VCO
f(XIN
6 MH
12 MH
)
selection bits *
Z
48 MH
48 MH
Z
Z
11
10
Z
*: PLL control register (bits 6,5)
Furthermore, when PLL operation mode selection bits are set to “00
2
”, the clock input into PLL is
used as fVCO, which is not multiplied, regardless of PLL operation enabled or disabled.
ꢀ fUSB (USB clock)
Either f(XIN) (main clock) or fVCO (PLL output clock) can be selected for fUSB by USB clock select bit
of USB control register (bit6 of USBCON: address 001016), and it is supplied to the USB function
control circuit. When supplying fVCO to the USB function control circuit, after setting PLL enable bit
to “1” (enabled) and then set USB clock select bit to “1” (USB clock).
Rev.2.00 Oct 15, 2006 page 86 of 112
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38K2 Group
2.11 Frequency synthesizer (PLL)
ꢀ fSYN (fUSB division clock)
According to the setting of the USB clock division ratio selection bits (bits 4, 3 of PLLCON), the
division clock of fUSB is supplied to fSYN
SYN =fUSB / m, m:value selected by USB clock division ratio selection bits
.
f
Set the USB clock division ratio selection bits so that fSYN may be set to 6 MHz, 8 MHz or 12 MHz.
When using fSYN as internal system clock, set the system clock selection bit of CPU mode register
(bit 5 of CPUM: address 003B16) to “1” (fSYN).
Table 2.11.2 shows the example of USB clock division ratio selection bits setting.
Table 2.11.2 USB clock division ratio selection bits setting example
USB clock division
ratio selection bits *
f
SYN
f
USB
6 MH
8 MH
Z
Z
Z
00
01
10
48 MH
Z
12 MH
*: PLL control register (bit4,3)
ꢀ Setting for starting up PLL circuit when hardware reset
Figure 2.11.6 shows the example of related registers setting.
ꢀ X: This bit is not used here.
Set it to “0” or “1” arbitrarily.
CPUM (address: 3B16) ← 11001X00
2
•Select main clock f(XIN) as a system clock
•Select main clock f(XIN) as a USB clock
USBCON (address: 1016) ← X0XXXXXX
2
•PLL operation mode (bit6,5): Multiplied by 8
•USB division mode (bit4,3): Divided by 6
•Enable PLL operation (bit7)
PLLCON (address: 0FF816) ← 11101000
2
•Wait for oscillation stabilization
When multiplying oscillation by PLL, wait for oscillation
stabilization.
Wait (approximately 1 ms)
USBCON (address: 1016) ← X1XXXXXX
2
•Select PLL circuit output clock fVCO as a USB clock
CPUM (address: 3B16) ← 11101X00
2
•Select fSYN as a system clock
Note: The above setting example assumes the operation when the external oscillating clock is 6 MH
Z and
the internal system clock is fSYN
.
Fig. 2.11.6 Related registers setting when hardware reset
Rev.2.00 Oct 15, 2006 page 87 of 112
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APPLICATION
38K2 Group
2.11 Frequency synthesizer (PLL)
ꢀ Procedure for stop and return of PLL circuit when stop mode
Figure 2.11.7 shows the stop procedure of PLL circuit, and figure 2.11.8 shows the return procedure
of PLL circuit.
PLL circuit operation enabled
(Supply PLL circuit output clock fVCO as USB clock)
ꢀ X: This bit is not used here.
Set it to “0” or “1” arbitrarily.
•Select main clock f(XIN) as a system clock
CPUM (address: 3B16) ← 11001X00
2
•Select PLL circuit output clock fVCO as a USB clock
USBCON (address: 1016) ← X1XXXXXX
2
and does not change this setting
•Disable PLL operation (bit7)
(fVCO is fixed to “L”.)
PLLCON (address: 0FF816) ← 0XXXX000
2
•Stop mode
STP instruction (stop mode)
Note: The above setting example assumes the operation when the external oscillating clock is 6 MH
Z and
the internal system clock is fSYN
.
Fig. 2.11.7 Related registers setting when stop mode
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38K2 Group
2.11 Frequency synthesizer (PLL)
After recovery from stop mode
ꢀ X: This bit is not used here.
Set it to “0” or “1” arbitrarily.
•PLL operation mode (bit6,5): Not multiplied
(Change PLL circuit output clock fVCO to f(XIN))
PLLCON (address: 0FF816) bit6,5 ← 00
2
•Select main clock f(XIN) as a USB clock
USBCON (address: 1016) ← X0XXXXXX
2
•PLL operation mode (bit6,5): Multiplied by 8
•USB division mode (bit4,3): Divided by 6
•Enable PLL operation (bit7)
PLLCON (address: 0FF816) ← 11101000
2
•Wait for oscillation stabilization
When multiplying oscillation by PLL, wait for oscillation
stabilization.
Wait (approximately 1 ms)
USBCON (address: 1016) ← X1XXXXXX
2
•Select PLL circuit output clock fVCO as a USB clock
•Select fSYN (8MH ) as a system clock
Z
CPUM (address: 3B16) ← 11101X00
2
Same setting procedure when hardware reset
Note: The above setting example assumes the operation when the external oscillating clock is 6 MH
the internal system clock is fSYN
Z
and
.
Fig. 2.11.8 Related registers setting when recovery from stop mode
2.11.4 Notes on PLL
ꢀ6 MH
Z
or 12 MH external oscillator can be connected as an input reference clock (f(XIN)). When using
Z
the frequency synthesized clock function, we recommend using the fastest frequency possible of f(XIN
as an input clock reference for the PLL.
)
ꢀWhen enabling PLL operation from PLL disabled status (disabled when reset), set the USB clock select
bit of USBCON to “0” (f(XIN)) to operate with the main clock (f(XIN)).
ꢀWhen supplying fVCO to the USB block after setting PLL operation enable bit to “1” (PLL enabled), wait
for the oscillation stable time (1 ms or less) of PLL to avoid any instability caused by the clock, then set
USB clock select bit to “1” (USB clock).
ꢀWhen selecting fSYN as an internal system clock, fUSB must be 48 MHz.
ꢀWhen selecting fSYN as an internal system clock, change the system clock selection bit to main clock
(f(XIN)) before executing STP instruction. It is because the following are needed for the low-power consumption:
•fUSB must be stopped by disabling PLL operation in Stop mode.
•The taimer 1 for waiting oscillation stabilization when returning from Stop mode will require the input
count source.
Rev.2.00 Oct 15, 2006 page 89 of 112
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APPLICATION
38K2 Group
2.12 Clock generating circuit
2.12 Clock generating circuit
This paragraph explains the registers setting method and the notes related to the clock generating circuit.
2.12.1 Memory map
001016 USB control register (USBCON)
003B16 CPU mode register (CPUM)
0FF816
PLL control register (PLLCON)
Fig. 2.12.1 Memory map of registers related to clock generating circuit
2.12.2 Related registers
USB control register
b7 b6 b5 b4 b3 b2 b1 b0
USB control register (USBCON)
[Address 1016
]
Function
At reset R W
Name
B
0
0 : Returning to BUS idle state by writing “1” first
and then “0”. (Remote wakeup signal)
1 : K-state output
Remote wakeup bit
0
0 : “L” output mode (valid in TRONE = “1”)
1 : “H” output mode (valid in TRONE = “1”)
0
0
0
0
0
0
0
TrON output control bit
TrON output enable bit
1
2
3
0 : TrON port output disabled (Hi-Z state)
1 : TrON port output enabled
USB reference voltage
control bit
0 : Normal mode (valid in VREFE = “1”)
1 : Low current mode (valid in VREFE = “1”)
USB reference voltage
enable bit
0 : USB reference voltage circuit operation disabled
1 : USB reference voltage circuit operation enabled
4
5
USB difference input
enable bit
0 : Upstream-port difference input circuit operation disabled
1 : Upstream--port difference input circuit operation enabled
0 : External oscillating clock f(XIN
1 : PLL circuit output clock fVCO
)
6
7
USB clock select bit
USB module operation
enable bit
0 : USB module reset
1 : USB module operation enabled
Fig. 2.12.2 Structure of USB control register
Rev.2.00 Oct 15, 2006 page 90 of 112
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38K2 Group
2.12 Clock generating circuit
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM: address 3B16
0
1
)
W
At reset
0
R
B
Function
Name
b1 b0
0
Processor mode bits
0 0 : Single-chip mode
0 1 : Not available
1 0 : Not available
1 1 : Not available
1
2
3
*
0 : 0 page
1 : 1 page
0
Stack page selection bit
Fix this bit to “1”.
1
0
0
4
Fix this bit to “0”.
5
6
0 : Main clock f(XIN)
System clock selection bit
1 : fSYN
b7 b6
System clock division ratio
selection bits
0
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
7
*
: The initial value of bit 1 depends on the CNVss level.
Fig. 2.12.3 Structure of CPU mode register
PLL control register
b7 b6 b5 b4 b3 b2 b1 b0
PLL control register (PLLCON)
[Address : 0FF816
Name
Nothing is arranged for these bit. These are write disabled bits.
When these bits are read out, the contents are “0”.
]
At reset R W
B
0
1
2
Function
0
b4 b3
USB clock division
3
0
0
0 0 : Divided by 8 (fSYN = fUSB/8)
ratio selection bits
0 1 : Divided by 6 (fSYN = fUSB/6)
1 0 : Divided by 4 (fSYN = fUSB/4)
1 1 : Not selected
4
b6 b5
5
6
PLL operation mode
selection bits
0 0 : Not multiplied (fVCO = fXIN
0 1 : Double (fVCO = fXIN ꢀ 2)
)
1 0 : Quadruple (fVCO = fXIN ꢀ 4)
1 1 : Multiplied by 8 (fVCO = fXIN ꢀ 8)
7
PLL enable bit
0 : Disabled
1 : Enabled
0
Fig. 2.12.4 Structure of PLL control register
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APPLICATION
38K2 Group
2.12 Clock generating circuit
2.12.3 Oscillation control
Either can be selected as an internal system clock between the following two by system clock selection
bit.
ꢀ Main clock f(XIN
)
ꢀꢀꢀ fSYN (fUSB division clock)
Any one can be selected as an internal clock φ among the following four by system clock division ratio
selection bits.
ꢀ f(XIN) or fSYN/8 (8-divide mode)
ꢀ f(XIN) or fSYN/4 (4-divide mode)
ꢀ f(XIN) or fSYN/2 (2-divide mode)
ꢀ f(XIN) or fSYN (Through mode)
(1) Generation of internal clock f(φ) using main clock f(XIN
)
Table 2.12.1 shows the example of internal clock f(φ) generation using main clock f(XIN); Figure
2.12.5 shows the related registers setting.
Table 2.12.1 Example of internal clock f(φ) generation using main clock f(XIN
)
System clock division
ratio selection bits *
Power source voltage
f(φ)
System clock
V
CC [V]
0.75 MH
1.5 MH
3 MH
6 MH
1 MH
2 MH
4 MH
8 MH
1.5 MH
3 MH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
6 MH
8 MH
Z
3.00 to 5.25
4.00 to 5.25
Z
12 MH
Z
6 MH
*: CPU mode register (bits 7,6)
ꢀ Select main clock f(XIN) as system clock and set clock division mode
b7
b0
0
CPU mode register
(CPUM: address 3B16
0
0
1
0
)
0 : Main clock f(XIN
)
b7 b6
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
Fig. 2.12.5 Related registers setting
Rev.2.00 Oct 15, 2006 page 92 of 112
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APPLICATION
38K2 Group
2.12 Clock generating circuit
(2) Generation of internal clock f(φ) using fSYN (fUSB division clock)
Table 2.12.2 shows the example of internal clock f(φ) generation using fSYN; Figure 2.12.6 shows the
related registers setting.
Table 2.12.2 Example of internal clock f(φ) generation using fSYN
System clock division
ratio selection bits *2
Power source voltage
USB clock division
ratio selection bits *1
f
USB
f(φ)
f
SYN
V
CC [V]
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
0.75 MH
1.5 MH
3 MH
6 MH
1 MH
2 MH
4 MH
8 MH
1.5 MH
3 MH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0 0
6 MH
Z
3.00 to 5.25
48 MH
Z
0 1
1 1
8 MH
Z
4.00 to 5.25
12 MH
Z
6 MH
*1: PLL control register (bits 4,3)
*2: CPU mode register (bits 7,6)
Rev.2.00 Oct 15, 2006 page 93 of 112
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38K2 Group
2.12 Clock generating circuit
1. Select main clock f(XIN) as system clock and set clock division mode.
b7
b0
0
CPU mode register
(CPUM: address 3B16
0
0
1
0
)
0 : Main clock f(XIN
)
b7 b6
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
2. Select main clock f(XIN) as USB clock.
b7
b0
USB control register
(USBCON: address 1016
0
)
0 : Main clock f(XIN
3. Enable PLL circuit, and generating PLL output clock (fVCO) 48 MHZ and fSYN.
)
b7
1
b0
0
PLL control register
(PLLCON: address 0FF816
0
0
)
b4 b3
0 0 : Divided by 8 (fSYN = fUSB/8)
0 1 : Divided by 6 (fSYN = fUSB/6)
1 0 : Divided by 4 (fSYN = fUSB/4)
1 1 : Not selected
b6 b5
0 0 : Not multiplied (fVCO = fXIN
)
0 1 : Double (fVCO = fXIN ꢀ 2)
1 0 : Quadruple (fVCO = fXIN ꢀ 4)
1 1 : Multiplied by 8 (fVCO = fXIN ꢀ 8)
1 : PLL enabled
4. Select PLL output clock (fVCO) as USB clock.
b7
b0
USB control register
(USBCON: address 1016
1
)
1 : fVCO
5. Select fSYN as system clock.
b7 b0
CPU mode register
(CPUM: address 3B16
1
)
1 : fSYN
Fig. 2.12.6 Related registers setting
Note: When selecting fSYN as an internal system clock, refer to “2.11 Frequency synthesizer (PLL)” for details
concerning how to generate fUSB (USB clock) from f(XIN) and the notes on PLL circuit.
Rev.2.00 Oct 15, 2006 page 94 of 112
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APPLICATION
38K2 Group
2.13 Standby function
2.13 Standby function
The 38K2 group is provided with standby functions to stop the CPU by software and put the CPU into the
low-power operation.
The following two types of standby functions are available.
•Stop mode using STP instruction
•Wait mode using WIT instruction
2.13.1 Memory map
0FFB16
MISRG (MISRG)
Fig. 2.13.1 Memory map of registers related to standby function
2.13.2 Related registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG
(MISRG: address 0FFB16
)
W
At reset
0
R
B
Functions
Name
0
0 : Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1 : Automatically set nothing
Oscillation stabilizing time
set after STP instruction
released bit
1
2
3
4
5
6
7
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are indefinite.
?
Fig. 2.13.2 Structure of MISRG
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2.13 Standby function
2.13.3 Stop mode
The stop mode is set by executing the STP instruction. In the stop mode, the oscillation of clock (XIN–XOUT
)
stops and the internal clock φ stops at the “H” level. The CPU stops and peripheral units stop operating.
As a result, power dissipation is reduced.
(1) State in stop mode
Table 2.13.1 shows the state in the stop mode.
Table 2.13.1 State in stop mode
Item
State in stop mode
Oscillation
CPU
Stopped.
Stopped.
Stopped at “H” level.
Internal clock φ
I/O ports P0–P6
Timer
Retains the state at the STP instruction execution.
Stopped. (Timers 1, 2, X)
However, Timers X can be operated in the event counter mode.
Watchdog timer
Serial I/O
Stopped.
Stopped.
However, these can be operated only when an external clock
is selected.
Stopped.
Stopped.
Stopped.
Stopped.
Stopped.
USB function
HUB function
External BUS interface
A/D converter
Comparator
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2.13 Standby function
(2) Release of stop mode
The stop mode is released by a reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
ꢀRestoration by reset input
The stop mode is released by holding the RESET pin to the “L” input level during the stop mode.
Oscillation is started when all ports are in the input state and the stop mode of the main clock (XIN
OUT) is released.
-
X
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) is required. The input of the RESET pin should be held at the “L” level until oscillation
stabilizes.
When the RESET pin is held at the “L” level for 16 cycles or more of XIN after the oscillation has
stabilized, the microcomputer will go to the reset state. After the input level of the RESET pin is
returned to “H”, the reset state is released in approximately 10.5 to 18.5 cycles of the XIN input.
Figure 2.13.3 shows the oscillation stabilizing time at restoration by reset input.
At release of the stop mode by reset input, the internal RAM retains its contents previous to the
reset. However, the previous contents of the CPU register and SFR are not retained.
For more details concerning reset, refer to “2.10 Reset”.
Oscillation
16 cycles or
stabilizing time more of XIN
Stop mode
Operating mode
Vcc
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
RESET
XIN
Execute Stop instruction
Fig. 2.13.3 Oscillation stabilizing time at restoration by reset input
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2.13 Standby function
ꢀRestoration by interrupt request
The occurrence of an interrupt request in the stop mode releases the stop mode. As a result,
oscillation is resumed. The interrupts available for restoration are:
•INT
0
, INT
1
•CNTR
0
•Serial I/O using an external clock
•Timer X using an external event count
•Key input (key-on wake-up)
•USB function (resume)
However, when using any of these interrupt requests for restoration from the stop mode, in order to
enable the selected interrupt, you must execute the STP instruction after setting the following conditions.
[Necessary register setting]
ꢀ Interrupt disable flag I = “0” (interrupt enabled)
ꢀ Timer 1 interrupt enable bit = “0” (interrupt disabled)
ꢀ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request
issued)
ꢀ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) is required. For restoration by an interrupt request, waiting time prior to supplying
internal clock φ to the CPU is automatically generatedꢀ2 by Prescaler 12 and Timer 1ꢀ1. This waiting
time is reserved as the oscillation stabilizing time on the system clock side. The supply of internal
clock φ to the CPU is started at the Timer 1 underflow.
Figure 2.13.4 shows an execution sequence example at restoration by the occurrence of an INT
interrupt request.
0
ꢀ1: If the STP instruction is executed when the oscillation stabilizing time set after STP instruction
released bit is “0”, “FF16” and “0116” are automatically set in the Prescaler 12 counter/latch and
Timer 1 counter/latch, respectively. When the oscillation stabilizing time set after STP instruction
released bit is “1”, nothing is automatically set to either Prescaler 12 or Timer 1. For this reason,
any suitable value can be set to Prescaler 12 and Timer 1 for the oscillation stabilizing time.
ꢀ2: Immediately after the oscillation is started, the count source is supplied to the prescaler 12 so
that a count operation is started.
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2.13 Standby function
ꢀWhen restoring microcomputer from stop mode by INT
Stop mode
0
interrupt (rising edge selected)
Oscillation stabilizing time
X
IN
X
IN; H
(System clock)
INT pin
0
512 counts
FF16
0116
Prescaler 12 counter
Timer 1 counter
INT
0
interrupt request bit
Peripheral device
CPU
Operating
Operating
Operating
Stopped
Stopped
Operating
Execute STP INT
0
interrupt signal
interrupt
512 counts down by
prescaler 12
Start supplying internal
clock φ to CPU
instruction
input (INT
0
request occurs)
Oscillation start
Prescaler 12 count start
Accept INT
request
0
interrupt
Note: f(XIN)/16 is input as the prescaler 12 count source.
Fig. 2.13.4 Execution sequence example at restoration by occurrence of INT
0
interrupt request
(3) Notes on using stop mode
ꢀRegister setting
Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the
stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP
instruction released bit is “0”)
ꢀClock restoration
When the main clock side is set as a system clock, the oscillation stabilizing time for approximately
8,000 cycles of the XIN input is reserved at restoration from the stop mode.
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2.13 Standby function
2.13.4 Wait mode
The wait mode is set by execution of the WIT instruction. In the wait mode, oscillation continues, but the
internal clock φ stops at the “H” level.
The CPU stops, but most of the peripheral units continue operating.
(1) State in wait mode
The continuation of oscillation permits clock supply to the peripheral units. Table 2.13.2 shows the
state in the wait mode.
Table 2.13.2 State in wait mode
State in wait mode
Item
Operating.
Oscillation
Stopped.
CPU
Stopped at “H” level.
Internal clock φ
I/O ports P0–P6
Timer
Retains the state at the WIT instruction execution.
Operating.
Operating.
Operating.
Operating.
Operating.
Stopped.
Watchdog timer
Serial I/O
USB function
HUB function
External BUS interface
A/D converter
Operating.
Operating.
Comparator
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2.13 Standby function
(2) Release of wait mode
The wait mode is released by reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
In the wait mode, oscillation is continued, so an instruction can be executed immediately after the
wait mode is released.
ꢀRestoration by reset input
The wait mode is released by holding the input level of the RESET pin at “L” in the wait mode.
Upon release of the wait mode, all ports are in the input state, and supply of the internal clock
φ to the CPU is started. To reset the microcomputer, the RESET pin should be held at an “L” level
for 16 cycles or more of XIN. The reset state is released in approximately 10.5 cycles to 18.5 cycles
of the XIN input after the input of the RESET pin is returned to the “H” level.
At release of wait mode, the internal RAM retains its contents previous to the reset. However, the
previous contents of the CPU register and SFR are not retained.
Figure 2.13.5 shows the reset input time.
For more details concerning reset, refer to “2.10 Reset”.
Operating mode
Wait mode
Vcc
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
16 cycles of XIN
RESET
X
IN
Execute WIT instruction
Fig. 2.13.5 Reset input time
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2.13 Standby function
ꢀRestoration by interrupt request
In the wait mode, the occurrence of an interrupt request releases the wait mode and supply of the
internal clock φ to the CPU is started. At the same time, the interrupt request used for restoration
is accepted, so the interrupt processing routine is executed.
However, when using an interrupt request for restoration from the wait mode, in order to enable the
selected interrupt, you must execute the STP instruction after setting the following conditions.
[Necessary register setting]
ꢀ Interrupt disable flag I = “0” (interrupt enabled)
ꢀ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued)
ꢀ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
2.13.5 Notes on stand-by function
In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O port
“undefined”.
Pull-up (connect the port to VCC) these ports through a resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values.
• When setting as an input port: Fix its input level
• When setting as an output port: Prevent current from flowing out to external
ꢀꢀReason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of an input port and an I/O port are “undefined”. This may cause power source current.
*1 stand-by state :
the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
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2.14 Flash memory
2.14 Flash memory
This paragraph explains the registers setting method and the notes related to the flash memory version.
2.14.1 Overview
The functions of the flash memory version are similar to those of the mask ROM version except that the
flash memory is built-in and some of the SFR area differ from that of the mask ROM version (refer to
“2.14.2 Memory map”).
In the flash memory version, the built-in flash memory can be programmed or erased by using the following
three modes.
• CPU rewrite mode
• Parallel I/O mode
• Standard serial I/O mode
2.14.2 Memory map
38K2 group flash memory version has 32 Kbytes of built-in flash memory.
Figure 2.14.1 shows the memory map of the flash memory version.
000016
SFR area
004016
Internal RAM
area
RAM
(2 Kbyte)
083F16
084016
User ROM area
800016
Not used
SFR area
0FE016
0FFF16
100016
Not used
32 Kbytes
800016
808016
Reserved ROM area
Built-in flash memory
area
(32 Kbytes)
FFFF16
FFFF16
Boot ROM area
4 Kbytes
F00016
FFFF16
Note: Access to boot ROM area
Pararell I/O mode
Read/Write avilable
Read only available
Read only available
CPU rewrite mode
Standard serial mode
Fig. 2.14.1 Memory map of flash memory version for 38K2 Group
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2.14 Flash memory
2.14.3 Related registers
Address
0FFE16 Flash memory control register (FMCR)
Fig. 2.14.2 Memory map of registers related to flash memory
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register
(FMCR : address 0FFE16
) (Note 1)
b
Name
Functions
At reset R W
1
0 : Busy (being written or
erased)
0 RY/BY status flag
1 : Ready
0
1
CPU rewrite mode 0 : Normal mode (Software
select bit (Note 2)
commands invalid)
1 : CPU rewrite mode
(Software commands
acceptable)
2
CPU rewrite mode
entry flag
0: Normal mode
1: CPU rewrite mode
0
Flash memory reset
bit (Note 3)
User area/Boot area
selection bit (Note 4)
3
4
0: Normal operation
1: Reset
0: User ROM area
1: Boot ROM area
0
0
5
6
7
Nothing is arranged for these bits. If writing,
set “0”. When these bits are read out,
the contents are undefined.
Undefined
Undefined
Undefined
Notes 1: The contents of flash memory control register are “XXX00001” just
after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1”
to it in succession. If it is not this procedure, this bit will not be set to
“1”. Additionally, it is required to ensure that no interrupt will be
generated during that interval.
Use the control program in the area except the built-in flash memory
for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”.
Set this bit 3 to “0” subsequently after setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory
for write to this bit.
Fig. 2.14.3 Structure of Flash memory control register
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2.14 Flash memory
2.14.4 Parallel I/O mode
In the parallel I/O mode, program/erase to the built-in flash memory can be performed by a flash programmer
(MFW-1).
The memory area of program/erase is from 0F00016 to 0FFFF16 (boot ROM area) or from 0800016 to
0FFFF16 (user ROM area). Be especially careful when erasing; if the memory area is not set correctly, the
products will be damaged eternally.
Table 2.14.1 shows the setting of programmers when programming in the parallel I/O mode.
•MFW-1 provided by Sunny Giken Inc. (http://www.sunnygiken.co.jp/english/index.html)
Table 2.14.1 Setting of programmers when parallel programming
Parallel adapter
MFW-S18
Products
Boot ROM area
User ROM area
M38K29F8HP/LHP
M38K29F8FP/LFP
0F00016 to 0FFFF16
0800016 to 0FFFF16
MFW-S19
2.14.5 Standard serial I/O mode
Table 2.14.2 shows a pin connection example (4 wires) between the programmer (MFW-1) and the
microcomputer when programming in the standard serial I/O mode.
•MFW-1 provided by Sunny Giken Inc. (http://www.sunnygiken.co.jp/english/index.html)
Table 2.14.2 Connection example to flash programmer when serial programming (4 wires)
38K2 Group flash memory version
MFW-1
MFW-1 side connector
Signal name
CLK
Function
Pin name
Pin number
Line number
3
10
4
Transfer clock input
Serial data input
P4
P4
P4
P4
2
0
1
3
/E
/E
/E
/E
X
X
X
X
TC/SCLK
53
R
X
D
DREQ/R D
X
51
T
X
D
Serial data output
DACK/TxD
52
______
2
BUSY
CNVSS
Transmit/Receive enable output
A1/SRDY
54
1
V
PP input
CNVSS
7
8
____________
8
RESET
Reset input
RESET
1
V
CC (Note 2)
Target board power source monitor input
GND
V
CC, PVCC, DVCC (Note 2)
14, 21, 22
11, 20
7
GND (Note 1)
V
SS, PVSS (Note 1)
Notes 1: When connecting a serial programmer, first connect both GNDs to the same GND level.
2: VCC power of MFW-1 is supplied from a target board. Power consumption of MFW-1 is Max. 200
mA when serial programming. Therefore, when the current capacity of target borad is short,
connect AC adapter and supply power source to MFW-1.
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2.14 Flash memory
2.14.6 CPU rewrite mode
In the CPU rewrite mode, issuing software commands through the Central Processing Unit (CPU) can
rewrite the built-in flash memory. Accordingly, the contents of the built-in flash memory can be rewritten
with the microcomputer itself mounted on board, without using the programmer.
Store the rewrite control program to the built-in flash memory in advance. The built-in flash memory cannot
be read in the CPU rewrite mode. Accordingly, after transferring the rewrite control program to the internal
RAM, execute it on the RAM.
The following commands can be used in the CPU rewrite mode: read array, read status register, clear
status register, program, erase all block, and block erase. For details concerning each command, refer to
“CHAPTER 1 Flash memory mode (CPU rewrite mode)”.
(1) CPU rewrite mode beginning/release procedures
Operation procedure in the CPU rewrite mode for the built-in flash memory is described below.
As for the control example, refer to “2.14.7 (2) Control example in the CPU rewrite mode.”
[Beginning procedure]
ꢀ Apply 4.50 to 5.25 V to the CNVSS/VPP pin (at selecting boot ROM area).
ꢀ Release reset.
ꢀ Set bits 6 and 7 (main clock division ratio selection bits) of the CPU mode register.
ꢀ After CPU rewrite mode control program is transferred to internal RAM, jump to this control
program on RAM. (The following operations are controlled by this control program).
ꢀ Apply 4.50 to 5.25 to the CNVSS/VPP pin (in single-chip mode).
ꢀ Set “1” to the CPU rewrite mode select bit (bit 1 of address 0FFE16).
ꢀ Read the CPU rewrite mode entry flag (bit 2 of address 0FFE16) to confirm that the CPU rewrite
mode is set to “1”.
ꢀ Flash memory operations are executed by using software commands.
Note: The following procedures are also necessary.
• Control for data which is input from the external (serial I/O etc.) and to be programmed
to the flash memory.
• Initial setting for ports, etc.
• Writing to the watchdog timer
[Release procedure]
ꢀ Execute the read command or set the flash memory reset bit (bit 3 of address 0FFE16).
ꢀ Set the CPU rewrite mode select bit (bit 0 of address 0FFE16) to “0”.
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2.14 Flash memory
2.14.7 Flash memory mode application examples
The control pin processing example on the system board in the standard serial I/O mode and the control
example in the CPU rewrite mode are described below.
(1) Control pin connection example on the system board in standard serial I/O mode
As shown in Figure 2.14.4, in the standard serial I/O mode, the built-in flash memory can be rewritten
with the microcomputer mounted on board. Connection examples of control pins (P4
0
/E
X
DREQ/R D,
X
______
____________
P4
1
/E
X
DACK/T
X
D, P4
2
/E
X
TC/SCLK, P4
3
/E
X
A1/SRDY, P1
6
, CNVSS, and RESET pin) in the standard serial
I/O mode are described below.
RS-232C
Serial programmer
Fig. 2.14.4 Rewrite example of built-in flash memory in standard serial I/O mode
Table 2.14.3 shows the setting condition in the standard serial I/O mode.
Table 2.14.3 Setting condition in serial I/O mode
38K2 Group flash memory version
Value
Pin name
Pin number
4.50 to 5.25 V
CNVSS/VPP (Note)
7
5
V
V
CC
P1
P4
6
CC
2
/E
X
TC/SCLK
53
8
____________
Edge from VSS to VCC
RESET
Note: CNVSS/VPP is not VCC but a voltage when programming.
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2.14 Flash memory
ꢀ When control signals are not affected to user system circuit
When the control signals in the standard serial I/O mode are not used or not affected to the user
system circuit, they can be connected as shown in Figure 2.14.5.
Target board
ꢀ1
Not used or to user system circuit
M38K29F8FP/HP
M38K29F8LFP/LHP
TXD(P41/ExDACK)
SCLK(P42/ExTC)
DVCC
PVCC
VCC
ꢀ2
RXD(P40/ExDREQ)
BUSY(P43/ExA1)
(P16)
PVSS
VSS
VPP(CNVSS)
RESET
XIN XOUT
User reset signal (Low active)
ꢀ1: When not used, set to input mode and pull up or pull down, or set to output mode and open.
ꢀ2: It is necessary to apply Vcc to SCLK (P42/ExTC) pin only when reset is released in the standard serial I/O mode.
Fig. 2.14.5 Connection example in standard serial I/O mode (1)
ꢀ When control signals are affected to user system circuit-1
Figure 2.14.6 shows an example that the jumper switch cut-off the control signals not to supply
to the user system circuit in the standard serial I/O mode.
Target board
To user system circuit
M38K29F8FP/HP
M38K29F8LFP/LHP
TXD(P41/ExDACK)
ꢀ
DVCC
PVCC
S
CLK(P42/ExTC)
R
X
D(P40/ExDREQ)
VCC
BUSY(P43/ExA1)
(P16)
PVSS
V
SS
VPP(CNVSS)
RESET
XIN
XOUT
User reset signal (Low active)
ꢀ: It is necessary to apply Vcc to SCLK (P42/ExTC) pin only when reset is released in the standard serial I/O mode.
Fig. 2.14.6 Connection example in standard serial I/O mode (2)
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2.14 Flash memory
ꢀ When control signals are affected to user system circuit-2
Figure 2.14.7 shows an example that the analog switch (74HC4066) cut-off the control signals not
to supply to the user system circuit in the standard serial I/O mode.
Target board
74HC4066
To user system circuit
M38K29F8FP/HP
M38K29F8LFP/LHP
T
S
R
X
D(P4
1
/ExDACK)
/ExTC)
/ExDREQ)
/ExA1)
DVCC
PVCC
ꢀ
CLK(P4
X
2
D(P40
VCC
B
USY(P43
(P16)
PVSS
VPP(CNVss)
VSS
RESET
X
IN
XOUT
User reset signal (Low active)
ꢀ: It is necessary to apply Vcc to SCLK (P42/ExTC) pin only when reset is released in the standard serial I/O mode.
Fig. 2.14.7 Connection example in standard serial I/O mode (3)
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2.14 Flash memory
(2) Control example in CPU rewrite mode
In this example, data is received by using serial I/O, and the data is programmed to the built-in flash
memory in the CPU rewrite mode.
Figure 2.14.8 shows an example of the reprogramming system for the built-in flash memory in the
CPU rewrite mode. Figure 2.14.9 shows the CPU rewrite mode beginning/release flowchart.
M38K29F8FP/HP
M38K29F8LFP/LHP
DVCC
PVCC
P1 (CE)
6
V
CC
Clock input
BUSY output
Data input
S
CLK
S
RDY(BUSY
)
PVSS
R
X
D
VSS
Data output
T
X
D
RESET
CNVSS
V
PP power source input
User reset signal
(Note 1)
Note 1: Apply 4.50 to 5.25 V to the VPP power source.
Fig. 2.14.8 Example of rewrite system for built-in flash memory in CPU rewrite mode
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2.14 Flash memory
START
Single-chip mode or boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control
program to built-in RAM
Jump to transferred control program on RAM
(The following operations are controlled by
the control program on this RAM)
Set “1” to CPU rewrite mode select bit
(by writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read command or set flash
memory reset bit (by writing “0” and then “
1” in succession) (Note 3)
Set “0” to CPU rewrite mode select bit
END
Notes 1: When MCU starts in the single-chip mode, it is necessary to apply
4.50 to 5.25 V to dhe CNVss pin until confirming of the CPU
rewrite mode entry flag.
2: Set bits 6 and 7 (system clock division ratio selection bits) of the
CPU mode register (address 003B16).
3: Before releasing the CPU rewrite mode after completing erase or
program operation, always be sure to execute the read array
command or reset the flash memory.
Fig. 2.14.9 CPU rewrite mode beginning/release flowchart
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2.14 Flash memory
2.14.8 Notes on CPU rewrite mode
(1) Operation speed
During CPU rewrite mode, set the internal clock φ 1.5 MHz or less using the system clock division
ratio selection bits (bits 6 and 7 of address 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during the CPU
rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data
of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog
timer underflow does not happen, because of watchdog timer is always clearing during program or
erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = “H” when reset is released, boot mode is active. So the
program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area.
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CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Notes on use
3.3 Countermeasures against noise
3.4 List of registers
3.5 Package outline
3.6 List of instruction code
3.7 Machine instructions
3.8 SFR memory map
3.9 Pin configurations
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Parameter
Unit
V
Symbol
VCC
Conditions
Ratings
–0.3 to 6.5
Power source voltage
AVCC
Analog power source voltage VCCE, VREF, PVCC, DVCC,
USBVREF
–0.3 to VCC + 0.3
V
All voltages are
based on VSS.
Output transistors
are cut off.
VI
Input voltage
P00–P07, P10–P17, P24–P27, P30–
P37, P40–P43, P50–P57, P60–P63
–0.3 to VCC + 0.3
V
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to 6.5
V
V
V
V
V
Input voltage
Input voltage
RESET, XIN, CNVSS2
VI
VI
CNVSS
Mask ROM version
Flash memory version
–0.5 to 3.8
Input voltage
D0+, D0-, D1+, D1-, D2+, D2-
VI
–0.3 to VCC + 0.3
Output voltage
P00–P07, P10–P17, P24–P27, P30–
P37, P40–P43, P50–P57, P60–P63,
XOUT
VO
–0.5 to 3.8
500
Output voltage
D0+, D0-, D1+, D1-, D2+, D2-, TrON
V
mW
°C
VO
Pd
Ta = 25°C
Power dissipation
(Note)
–20 to 85
25±5
Topr
MCU operating
Operating temperature
°C
In flash memory mode
(For flash memory ver-
sion)
°C
Tstg
–40 to 125
Storage temperature
Note: The maximum rating value depends on not only the MCU’s power dissipation but the heat consumption characteristics of the package.
Rev.2.00 Oct 15, 2006 page 2 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
3.1.2 Recommended operating conditions (L.Ver)
Table 3.1.2 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
V
Min.
4.00
Typ.
5.00
Max.
5.25
VCC
Power source voltage
VCC
System clock 12 MHz
(2-/4-/8-divide mode)
System clock 8 MHz
System clock 6 MHz
4.00
3.00
5.00
5.00
VCC
VCC
5.25
5.25
V
V
V
V
V
V
V
V
V
AVCC
AVCC
VREF
VREF
Analog power source voltage PVCC, DVCC
Analog power source voltage VCCE
Analog reference voltage
Analog reference voltage
VREF
VCC
3.6
2.0
3.0
3.0
USBVREF
Vcc = 3.6 to 4.0 V
Vcc = 3.0 to 3.6 V
VCC
VSS
AVSS
VIH
Power source voltage
VSS
0
0
Analog power source voltage PVSS
“H” input voltage
P00–P07, P24–P27, P50–P57,
P60–P63
VCC
V
V
0.8VCC
VCCE
VCC
V
V
V
V
VIH
VIH
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P10–P17, P30–P37, P40–P43
RESET, XIN, CNVSS, CNVSS2
D0+, D0-, D1+, D1-, D2+, D2-
0.8VCCE
0.8VCC
2.0
3.6
VIH
VIL
P00–P07, P24–P27, P50–P57,
P60–P63
0.2VCC
0
VIL
VIL
VIL
“L” input voltage
“L” input voltage
“L” input voltage
P10–P17, P30–P37, P40–P43
RESET, XIN, CNVSS, CNVSS2
D0+, D0-, D1+, D1-, D2+, D2-
V
V
V
0
0
0
0.2VCCE
0.2VCC
0.8
Rev.2.00 Oct 15, 2006 page 3 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.3 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
“H” total peak output current (Note 1)
Unit
mA
Min.
Typ.
Max.
–80
∑IOH(peak)
P00–P07, P24–P27, P50–P57,
P60–P63
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
“H” total peak output current (Note 1)
“L” total peak output current (Note 1)
“L” total peak output current (Note 1)
“L” total peak output current (Note 1)
“H” total average output current (Note 1)
P10–P17, P30–P37, P40–P43
P00–P07, P24–P27, P50–P57
P60–P63
–80
80
mA
mA
mA
mA
mA
80
80
P10–P17, P30–P37, P40–P43
–40
P00–P07, P24–P27, P50–P57,
P60–P63
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
∑IOL(avg)
IOH(peak)
–40
40
mA
mA
mA
mA
mA
“H” total average output current (Note 1)
“L” total average output current (Note 1)
“L” total average output current (Note 1)
“L” total average output current (Note 1)
“H” peak output current (Note 2)
P10–P17, P30–P37, P40–P43
P00–P07, P24–P27, P50–P57
P60–P63
40
40
P10–P17, P30–P37, P40–P43
–10
P00–P07, P24–P27, P50–P57,
P60–P63
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
mA
mA
mA
mA
mA
–10
10
20
10
–5
“H” peak output current (Note 2)
“L” peak output current (Note 2)
“L” peak output current (Note 2)
“L” peak output current (Note 2)
“H” average output current (Note 3)
P10–P17, P30–P37, P40–P43
P00–P07, P24–P27, P50–P57
P60–P63
P10–P17, P30–P37, P40–P43
P00–P07, P24–P27, P50–P57,
P60–P63
IOH(avg)
IOL(avg)
IOL(avg)
IOL(avg)
f(XIN)
mA
mA
–5
5
“H” average output current (Note 3)
“L” average output current (Note 3)
“L” average output current (Note 3)
“L” average output current (Note 3)
Main clock input oscillation frequency
(Note 4)
P10–P17, P30–P37, P40–P43
P00–P07, P24–P27, P50–P57
P60–P63
10
5
mA
mA
P10–P17, P30–P37, P40–P43
Vcc = 4.00 to 5.25 V
Vcc = 3.00 to 4.00 V
Vcc = 4.00 to 5.25 V
Vcc = 3.00 to 4.00 V
Vcc = 4.00 to 5.25 V
Vcc = 3.00 to 4.00 V
12
6
MHz
MHz
MHz
MHz
MHz
MHz
6
6
6
6
f(XIN) or
f(SYN)
f(φ)
12
6
System clock frequency
8
φ frequency
6
Notes 1: The total peak output current is the absolute value of the peak currents flowing through all the applicable ports. The total average output current is
the average value of the absolute value of the currents measured over 100 ms flowing through all the applicable ports.
2: The peak output current is the absolute value of the peak current flowing in each port.
3: The average output current is the average value of the absolute value of the currents measured over 100 ms.
4: The duty of oscillation frequency is 50 %. 6 MHz or 12 MHz is usable.
Rev.2.00 Oct 15, 2006 page 4 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
3.1.3 Electrical characteristics (L.Ver)
Table 3.1.4 Electrical characteristics (1) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
IOH = –10 mA
Unit
V
Min.
Typ.
Max.
“H” output voltage
VCC–2.0
VOH
P00–P07, P24–P27, P50–P57, P60–P63
(Vcc = 4.00 to 5.25 V)
VCC–1.0
VCCE–2.0
V
V
IOH = –1 mA
“H” output voltage
IOH = –10 mA (VCCE =
4.00 to 5.25 V)
VOH
VOH
VOL
P10–P17, P30–P37, P40–P43
VCCE–1.0
2.8
V
V
IOH = –1 mA
D+ and D- pins pull-
down with 0 V via a
resistor of 15 kΩ ± 5 %
“H” output voltage
3.6
2.0
D0+, D0-, D1+, D1-, D2+, D2-
IOL = 10 mA
(Vcc = 4.00 to 5.25 V)
V
“L” output voltage
P00–P07, P24–P27, P50–P57
IOL = 1 mA
V
V
1.0
2.0
IOL = 20 mA
(Vcc = 4.00 to 5.25 V)
VOL
VOL
“L” output voltage
P60–P63
IOL = 1 mA
V
V
1.0
2.0
IOL = 10 mA (VCCE =
4.00 to 5.25 V)
“L” output voltage
P10–P17, P30–P37, P40–P43
IOL = 1 mA (VCCE =
3.00 to 5.25 V)
1.0
0.3
V
V
VOL
0
“L” output voltage
D+ and D- pins pull-up
with 3.6 V via a resistor
of 1.5 kΩ ± 5 %
D0+, D0-, D1+, D1-, D2+, D2-
Hysteresis
VT+–VT-
VT+–VT-
0.6
0.6
V
V
CNTR0, INT0, INT1
Hysteresis
P10/DQ0–P17/DQ7, P30–P32, P33/ExINT,
P34/ExCS, P35/ExWR, P36/ExRD, P37/
ExA0, P40/ExDREQ/RxD, P41/ExDACK/
TxD, P42/ExTC/SCLK, P43/ExA1/SRDY
VT+–VT
0.25
0.5
Hysteresis
V
D0+, D0-, D1+, D1-, D2+, D2-
Hysteresis RESET
VT+–VT-
IIH
V
“H” input current
VI = VCC (Pull-ups “off”)
VI = VCCE
5.0
µA
P00–P07, P24–P27, P50–P57, P60–P63
“H” input current
µA
IIH
5.0
5.0
P10–P17, P30–P37, P40–P43
“H” input current RESET, CNVSS
“H” input current XIN
µA
µA
µA
IIH
IIH
IIL
VI = VCC
4.0
VI = VCC
“L” input current
VI = VSS (Pull-ups “off”)
–5.0
–5.0
P00–P07, P24–P27, P50–P57, P60–P63
“L” input current
IIL
VI = VSS
µA
P10–P17, P30–P37, P40–P43
“L” input current RESET, CNVSS, CNVSS2
“L” input current XIN
µA
µA
µA
VI = VSS
VI = VSS
–5.0
IIL
IIL
IIL
–4.0
“L” input current P00–P07, P50, P52
(Pull-ups “on”)
VI = VSS
(Vcc = 4.00 to 5.25 V)
–60.0
–20.0
–120.0
VI = VSS
–10.0
2.00
µA
RAM hold voltage
When clock is stopped
5.25
V
VRAM
Rev.2.00 Oct 15, 2006 page 5 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.5 Electrical characteristics (2) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Test conditions
Parameter
Unit
mA
Max.
60
Min.
f(XIN) = system clock = 12 MHz,
φ = 6 MHz,
USB reference voltage circuit enabled
Normal
mode
(Note 1)
21.0
ICC
Vcc = 4.00
to 5.25 V
Power source current
(Output transistor is
isolated.)
f(XIN) = 12 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
22.5
22.0
21.0
60
60
mA
mA
f(XIN) = 6 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit enabled
60
35
30
mA
mA
mA
mA
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
Vcc = 3.00
to 4.00 V
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
9.0
6.0
Vcc = 3.00
to 3.60 V
f(XIN) = 12 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
Vcc = 4.00
to 5.25 V
Wait
mode
(Note 2)
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
Vcc = 3.00
to 4.00 V
2.0
125.0
0.1
mA
µA
µA
µA
Stop
mode
(Note 3)
USB reference voltage circuit enabled
Low current mode
Vcc = 4.00
to 5.25 V
250
10
USB reference voltage circuit disabled
Ta = 25 °C
Vcc = 3.00
to 5.25 V
USB reference voltage circuit disabled
Ta = 85 °C
<Test conditions>
Notes 1: Operating in single-chip mode
Clock input from XIN pin (XOUT oscillator stopped)
fUSB = 48 MHz
All USB difference-input circuits enabled
Leaving I/O pins open
Operating functions: PLL circuit, CPU, Timers
2: Operating in single-chip mode with Wait mode
Clock input from XIN pin (XOUT oscillator stopped)
fUSB = 48 MHz
All USB difference-input circuits enabled
Leaving I/O pins open
Operating functions: PLL circuit, Timers, USB receiving
Disabled functions: CPU
3: Operating in single-chip mode with Stop mode
Oscillation stopped
All USB difference-input circuits disabled
Leaving I/O pins open
Rev.2.00 Oct 15, 2006 page 6 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
3.1.4 A/D converter characteristics (L.Ver)
Table 3.1.6 A/D Converter characteristics (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Bits
Min.
Typ.
Max.
10
—
—
—
Resolution
Linearity error
±3
LSB
LSB
Ta = 25 °C
±1.5
Ta = 25 °C
Differential nonlinear error
Zero transition voltage
Full scale transition voltage
Conversion time
0
15
35
mV
mV
VOT
VCC = VREF = 5.12 V
VCC = VREF = 5.12 V
VFST
5105
5125
5150
122
tCONV
tc(XIN)
or
tc(fSYN)
RLADDER
IVREF
35
kΩ
Ladder resistor
A/D converter operating; VREF = 5.0 V
A/D converter not operating; VREF = 5.0 V
µA
150
200
50
Reference power source input current
5
5.0
A/D port input current
II(AD)
µA
Rev.2.00 Oct 15, 2006 page 7 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
3.1.5 Timing Requirements (L.Ver)
Table 3.1.7 Timing requirements (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2
Typ.
Max.
Reset input “L” pulse width
Main clock input cycle time
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tW(RESET)
83
tC(XIN)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0 input cycle time
35
tWH(XIN)
35
tWL(XIN)
200
80
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
CNTR0 input “H” pulse width
CNTR0 input “L” pulse width
80
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
80
80
tWL(INT)
800
370
370
220
100
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(RxD–SCLK)
th(SCLK–RxD)
Serial I/O input hold time
Note: These limits are the rating values in the clock synchronous mode, bit 6 of address 0FE016 = “1”. In the UART mode, bit 6 of address 0FE016 = “0”; the
rating values are set to one fourth.
Table 3.1.8 Timing requirements (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2
Typ.
Max.
Reset input “L” pulse width
Main clock input cycle time
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tW(RESET)
166
70
tC(XIN)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0 input cycle time
tWH(XIN)
70
tWL(XIN)
500
230
230
230
230
2000
950
950
400
200
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
CNTR0 input “H” pulse width
CNTR0 input “L” pulse width
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
tWL(INT)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(RxD–SCLK)
th(SCLK–RxD)
Serial I/O input hold time
Note: These limits are the rating values in the clock synchronous mode, bit 6 of address 0FE016 = “1”. In the UART mode, bit 6 of address 0FE016 = “0”; the
rating values are set to one fourth.
Rev.2.00 Oct 15, 2006 page 8 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.9 Timing requirements of external bus interface (EXB) (1)
(VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
tsu(S-R)
Parameter
Min.
Typ.
Max.
ExCS setup time for read
ExCS setup time for write
ExCS hold time for read
ExCS hold time for write
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
tsu(S-W)
th(R-S)
0
0
th(W-S)
ExA0, ExA1 setup time for read
ExA0, ExA1 setup time for write
ExA0, ExA1 hold time for read
ExA0, ExA1 hold time for write
ExDACK setup time for read
ExDACK setup time for write
ExDACK hold time for read
ExDACK hold time for write
Read “H” pulse width
10
tsu(A-R)
tsu(A-W)
th(R-A)
10
0
0
th(W-A)
10
tsu(ACK-R)
tsu(ACK-W)
th(R-ACK)
th(W-ACK)
tWH(R)
10
0
0
80
Read “L” pulse width
80
tWL(R)
Write “H” pulse width
80
tWH(W)
Write “L” pulse width
80
tWL(W)
ExDACK “H” pulse width
120
tWH(ACK)
tWL(ACK)
tsu(D-W)
th(W-D)
ExDACK “L” pulse width
120
Data input setup time before write
Data input hold time after write
Data input setup time before ExDACK
Data input hold time after ExDACK
CPU clock cycle time
40
0
60
tsu(D-ACK)
th(ACK-W)
tC(φ)
5
125
Burst mode access cycle time
USB function not operating tC(φ)•3+10
tW(cycle)
USB function operating
tC(φ)•5+10
Rev.2.00 Oct 15, 2006 page 9 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.10 Timing requirements of external bus interface (EXB) (2)
(VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
tsu(S-R)
Parameter
Min.
Typ.
Max.
ExCS setup time for read
ExCS setup time for write
ExCS hold time for read
ExCS hold time for write
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
tsu(S-W)
th(R-S)
0
0
th(W-S)
ExA0, ExA1 setup time for read
ExA0, ExA1 setup time for write
ExA0, ExA1 hold time for read
ExA0, ExA1 hold time for write
ExDACK setup time for read
ExDACK setup time for write
ExDACK hold time for read
ExDACK hold time for write
Read “H” pulse width
30
tsu(A-R)
tsu(A-W)
th(R-A)
30
0
0
th(W-A)
30
tsu(ACK-R)
tsu(ACK-W)
th(R-ACK)
th(W-ACK)
tWH(R)
30
0
0
120
Read “L” pulse width
120
tWL(R)
Write “H” pulse width
120
tWH(W)
Write “L” pulse width
120
tWL(W)
ExDACK “H” pulse width
160
tWH(ACK)
tWL(ACK)
tsu(D-W)
th(W-D)
ExDACK “L” pulse width
160
Data input setup time before write
Data input hold time after write
Data input setup time before ExDACK
Data input hold time after ExDACK
CPU clock cycle time
60
0
80
tsu(D-ACK)
th(ACK-W)
tC(φ)
10
166
Burst mode access cycle time
USB function not operating tC(φ)•3+30
tW(cycle)
USB function operating
tC(φ)•5+30
Rev.2.00 Oct 15, 2006 page 10 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
3.1.6 Switching Characteristics (L.Ver)
Table 3.1.11 Switching characteristics (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
140
ns
ns
ns
ns
ns
ns
ns
ns
tWH(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tC(SCLK)/2–30
tC(SCLK)/2–30
tWL(SCLK)
td(SCLK–TxD)
tv(SCLK–TxD)
tr(SCLK)
–30
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note)
CMOS output falling time (Note)
30
30
30
30
tf(SCLK)
tr(CMOS)
tf(CMOS)
Notes: Pins XOUT, D0+, D0-, D1+, D2-, D2+, D2- are excluded.
Table 3.1.12 Switching characteristics (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
tWH(SCLK)
Parameter
Unit
Min.
Typ.
Max.
350
ns
ns
ns
ns
ns
ns
ns
ns
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
tC(SCLK)/2–50
tC(SCLK)/2–50
tWL(SCLK)
td(SCLK–TxD)
tv(SCLK–TxD)
tr(SCLK)
–30
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note)
CMOS output falling time (Note)
50
50
50
50
tf(SCLK)
tr(CMOS)
tf(CMOS)
Notes: Pins XOUT, D0+, D0-, D1+, D2-, D2+, D2- are excluded.
Measured output pin
100 pF
CMOS output
Fig. 3.1.1 Output switching characteristics measurement circuit
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APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.13 Switching characteristics of external bus interface (EXB) (1)
(VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Data output enable time after read
Max.
60
Min.
0
Typ.
ns
ns
ns
ns
ns
ta(R-D)
Data output disable time after read
Data output enable time after ExDACK
Data output disable time after ExDACK
tv(R-D)
ta(ACK-D)
tv(ACK-D)
td(R-Mdis)
80
0
In cycle mode
Mch_req disable output delay time after read
tC(φ)+10
In cycle mode
Mch_req disable output delay time after write
td(W-Mdis)
td(R-Men)
td(W-Men)
ns
tC(φ)+10
ns
ns
USB function not operating
tC(φ)•3+10
tC(φ)•5+10
In cycle mode
Mch_req enable output delay time after read
USB function operating
USB function not operating
ns
ns
In cycle mode
Mch_req enable output delay time after write
tC(φ)•3+10
tC(φ)•5+10
USB function operating
Table 3.1.14 Switching characteristics of external bus interface (EXB) (2)
(VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Data output enable time after read
Unit
Max.
80
Min.
0
ns
ns
ns
ns
ns
ta(R-D)
Data output disable time after read
Data output enable time after ExDACK
Data output disable time after ExDACK
tv(R-D)
ta(ACK-D)
tv(ACK-D)
td(R-Mdis)
120
0
In cycle mode
Mch_req disable output delay time after read
tC(φ)+30
In cycle mode
Mch_req disable output delay time after write
td(W-Mdis)
td(R-Men)
td(W-Men)
ns
tC(φ)+30
ns
ns
ns
ns
USB function not operating
tC(φ)•3+30
tC(φ)•5+30
In cycle mode
Mch_req enable output delay time after read
USB function operating
USB function not operating
In cycle mode
Mch_req enable output delay time after write
tC(φ)•3+30
tC(φ)•5+30
USB function operating
Rev.2.00 Oct 15, 2006 page 12 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.15 Switching characteristics (USB ports) (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
USB full-speed output rising time
Unit
Typ.
Min.
4
Max.
20
ns
ns
ns
tfr(D+/D-)
CL = 50 pF
tff(D+/D-)
tlr(D+/D-)
USB full-speed output rising time
USB low-speed output rising time
CL = 50 pF
4
20
CL = 200 to 600 pF
Ta = 0 to 85 °C
75
300
ns
ns
ns
ns
ns
CL = 250 to 600 pF
Ta = –20 to 85 °C
CL = 200 to 600 pF
Ta = –20 to 85 °C
CL = 200 to 600 pF
Ta = 0 to 85 °C
300
300
300
300
300
75
65
75
75
65
tlf(D+/D-)
USB low-speed output falling time
CL = 250 to 600 pF
Ta = –20 to 85 °C
CL = 200 to 600 pF
Ta = –20 to 85 °C
tfr(D+/D-)/tff(D+/D-)
tlr(D+/D-)/tff(D+/D-)
%
%
V
tfrfm(D+/D-)
tlrfm(D+/D-)
Vcrs(D+/D-)
USB full-speed ports rising/falling ratio
USB low-speed ports rising/falling ratio
USB output signal cross-over voltage
90
80
111.11
125
1.3
2.0
TrON
RL = 27 Ω
R
L
= 1.5 kΩ
Measured output pin
RL = 27 Ω
Measured output pin
C
L
RL = 15 kΩ
CL
RL = 15 kΩ
USB port output
USB port output
Fig. 3.1.2 USB output switching characteristics measurement cir-
cuit (1) for D0-, D1+/D2+ (low-speed), D1-/D2- (full-speed)
Fig. 3.1.3 USB output switching characteristics measurement cir-
cuit (2) for D0+, D1+/D2+ (full-speed), D1-/D2- (low-speed)
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APPENDIX
38K2 Group
3.1 Electrical characteristics
tC(CNTR)
t
WL(CNTR)
t
WH(CNTR)
0.8VCC
CNTR
0
0.2VCC
t
WL(INT)
t
WH(INT)
0.8VCC
INT
0/INT
1
0.2VCC
tW(RESET)
0.8
RESET
0.2VCC
VCC
t
C
(XIN)
t
WL(XIN)
t
WH(XIN)
0.8VCC
XIN
0.2VCC
[Serial I/O]
t
C
(SCLK
)
tr
tf
t
WL(SCLK
)
tWH(SCLK)
0.8VCC
E
S
CLK
0.2VCC
E
t
su(RxD-SCLK
)
th(SCLK-RxD)
0.8VCC
E
E
RxD(at receive)
0.2VCC
td(SCLK-TxD)
tv(SCLK-TxD)
TxD (at transmit)
Fig. 3.1.4 Timing chart (1)
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APPENDIX
38K2 Group
3.1 Electrical characteristics
ꢀꢀTiming chart
[ EXB <CPU channel mode> ]
< Read >
t
su(A-R)
t
h(R-A)
0.8VCC
0.2VCC
ExA0, ExA1
t
su(S-R)
t
h(R-S)
0.2VCC
ExCS
ExRD
t
wL(R)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ
7
t
a(R-D)
t
v(R-D)
< Write >
t
su(A-W)
t
h(W-A)
0.8VCC
0.2VCC
ExA0, ExA1
t
su(S-W)
t
h(W-S)
0.2VCC
ExCS
t
wL(W)
0.8VCC
0.2VCC
ExWR
t
h(W-D)
t
su(D-W)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ
7
Fig. 3.1.5 Timing chart (2)
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APPENDIX
38K2 Group
3.1 Electrical characteristics
ꢀꢀTiming chart
[ EXB <Memory channel mode, Normal port function> ]
< Read >
t
su(A-R)
t
h(R-A)
0.8VCC
0.2VCC
ExA0, ExA1
t
su(S-R)
t
h(R-S)
0.2VCC
ExCS
ExRD
t
wL(R)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ
7
t
a(R-D)
t
v(R-D)
td(R-Men)
t
d(R-Mdis)
ExINT(Mch_req)
0.2VCC
0.2VCC
< Write >
t
su(A-W)
t
h(W-A)
0.8VCC
0.2VCC
ExA0, ExA1
t
su(S-W)
t
h(W-S)
0.2VCC
ExCS
t
wL(W)
0.8VCC
0.2VCC
ExWR
t
h(W-D)
t
su(D-W)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ
7
td(W-Men)
td(W-Mdis)
0.2VCC
ExINT(Mch_req)
0.2VCC
Fig. 3.1.6 Timing chart (3)
Rev.2.00 Oct 15, 2006 page 16 of 99
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APPENDIX
38K2 Group
3.1 Electrical characteristics
ꢀ Timing chart
[ EXB <Memory channel mode, DMA interface pin function,
Read and write signals used together mode> ]
< Read >
tsu(ACK-R)
th(R-ACK)
ExDACK
ExRD
0.2VCC
twL(R)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(R-D)
tv(R-D)
td(R-Mdis)
td(R-Men)
ExDREQ(Mch_req)
0.2VCC
0.2VCC
< Write >
ExDACK
tsu(ACK-W)
th(W-ACK)
0.2VCC
twL(W)
0.8VCC
0.2VCC
ExWR
th(W-D)
tsu(D-W)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
td(W-Mdis)
td(W-Men)
0.2VCC
ExDREQ(Mch_req)
0.2VCC
Fig. 3.1.7 Timing chart (4)
Rev.2.00 Oct 15, 2006 page 17 of 99
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APPENDIX
38K2 Group
3.1 Electrical characteristics
ꢀ Timing chart
[ EXB <Memory channel mode, DMA interface pin function,
Read and write signals not required mode> ]
< Read >
twL(ACK)
0.8VCC
0.2VCC
ExDACK
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(ACK-D)
tv(ACK-D)
td(ACK-Mdis)
td(ACK-Men)
ExDREQ(Mch_req)
0.2VCC
0.2VCC
twL(ACK)
< Write >
ExDACK
0.8VCC
0.2VCC
th(ACK-D)
tsu(D-ACK)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
td(ACK-Mdis)
td(ACK-Men)
0.2VCC
ExDREQ(Mch_req)
0.2VCC
Fig. 3.1.8 Timing chart (5)
Rev.2.00 Oct 15, 2006 page 18 of 99
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APPENDIX
38K2 Group
3.1 Electrical characteristics
ꢀ Timing chart
[ EXB <Memory channel mode, Burst transfer> ]
< Read >
ExDACK
twH(R)
0.8VCC
twL(R)
ExRD
0.2VCC
tw(cycle)
DQ0 to DQ7
tv(R-D)
ta(R-D)
td(R-Mdis)
ExDREQ(Mch_req)
0.2VCC
< Write >
ExDACK
twH(W)
0.8VCC
twL(W)
ExWR
0.2VCC
tw(cycle)
DQ0 to DQ7
th(W-D)
tsu(D-W)
td(W-Mdis)
ExDREQ(Mch_req)
0.2VCC
Fig. 3.1.9 Timing chart (6)
Rev.2.00 Oct 15, 2006 page 19 of 99
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APPENDIX
38K2 Group
3.2 Notes on use
3.2 Notes on use
3.2.1 Notes on input and output ports
(1) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instructionꢀ1, the value of the
unspecified bit may be changed.
ꢀ Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
•As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
ꢀ1
Bit managing instructions: SEB and CLB instructions
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APPENDIX
38K2 Group
3.2 Notes on use
3.2.2 Termination of unused pins
(1) Terminate unused pins
ꢀ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
ꢀ I/O ports :
Do not open in the input mode.
ꢀ Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination shown
on the above.
ꢀ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
ꢀ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and VCC (or VSS).
ꢀ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
ꢀ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
Rev.2.00 Oct 15, 2006 page 21 of 99
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APPENDIX
38K2 Group
3.2 Notes on use
3.2.3 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 0FF316
•Timer X mode register (address 2316
)
)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active edge switch
bit) or the interrupt (source) select bit to “1”.
↓
NOP (one or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 3.2.1 Sequence of changing relevant register
ꢀ Reason
When setting the following, the interrupt request bit may be set to “1”.
•When setting external interrupt active edge
Concerned register: Interrupt edge selection register (address 0FF316
Timer X mode register (address 2316
)
)
Rev.2.00 Oct 15, 2006 page 22 of 99
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APPENDIX
38K2 Group
3.2 Notes on use
(2) Check of interrupt request bit
ꢀ When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one
or more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.2.2 Sequence of check of interrupt request bit
ꢀ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
3.2.4 Notes on timer
ꢀ If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
ꢀ When switching the count source by the timer 12 and X count source selection bits, the value of
timer count is altered in unconsiderable amount owing to generating of thin pulses in the count
input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
Rev.2.00 Oct 15, 2006 page 23 of 99
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APPENDIX
38K2 Group
3.2 Notes on use
3.2.5 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O (Serial I/O)
ꢀ Stop of transmission operation
Clear the serial I/O enable bit and the transmit enable bit to “0” (Serial I/O and transmit disabled).
ꢀ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
ꢀ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (Serial
I/O disabled).
ꢀ Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive
disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
ꢀ Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O enable bit to “0”
(Serial I/O disabled) (refer to (1) ꢀ).
Rev.2.00 Oct 15, 2006 page 24 of 99
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APPENDIX
38K2 Group
3.2 Notes on use
(2) Notes when selecting clock asynchronous serial I/O (Serial I/O)
ꢀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
ꢀ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
ꢀ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
ꢀ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
ꢀ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) SRDY output of reception side (Serial I/O)
When signals are output from the SRDY pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O control register again (Serial I/O)
Set the serial I/O control register again after the transmission and the reception circuits are reset by
clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
Can be set with the LDM instruction at the same time
↓
Set both the transmit enable bit (TE) and
the receive enable bit (RE), or one of
them to “1”
Fig. 3.2.3 Sequence of setting serial I/O control register again
Rev.2.00 Oct 15, 2006 page 25 of 99
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APPENDIX
38K2 Group
3.2 Notes on use
(5) Data transmission control with referring to transmit shift register completion flag (Serial I/O)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected (Serial I/O)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the SCLK input level. Also, write the transmit data to the transmit buffer
register (serial I/O shift register) at “H” of the SCLK input level.
(7) Transmit interrupt request when transmit enable bit is set (Serial I/O)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
ꢀ Set the interrupt enable bit to “0” (disabled) with CLB instruction.
ꢀ Prepare serial I/O for transmission/reception.
ꢀ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
ꢀ Set the interrupt enable bit to “1” (enabled).
ꢀ Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt bit is set regardless of which of the two timings listed below is selected as the timing for
the transmission interrupt to be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
3.2.6 Notes on USB function
(1) Port pins (D0+, D0-, D1+, D1-, D2+, D2-) treatment
•The USB specification requires a driver-impedance 28 to 44 Ω. In order to meet the USB specification
impedance requirements, connect a resistor (27 W recommended) in series to the USB port pins.
In addition, in order to reduce the ringing and control the falling/rising timing and a crossover point,
connect a capacitor between the USB port pins and the Vss pin if necessary.
The values and structure of those peripheral elements depend on the impedance characteristics
and the layout of the printed circuit board. Accordingly, evaluate your system and observe waveforms
before actual use and decide use of elements and the values of resistors and capacitors.
•Make sure the USB D+/D- lines do not cross any other wires. Keep a large GND area to protect the
USB lines. Also, make sure you use a USB specification compliant connecter for the connection.
(2) USBVREF pin treatment (Noise Elimination)
•Connect a capacitor between the USBVREF pin and the Vss pin. The capacitor should have a 2.2 µF
capacitor (electrolytic capacitor) and a 0.1 µF capacitor (ceramic type capacitor) connected in parallel.
•In Vcc = 3.0 to 3.6 V operation, connect the USBVREF pin directly to the Vcc pin in order to supply
power to the USB port circuit. In addition, you will need to disable the built-in USB reference voltage
circuit in this operation (set bit 4 of the USB control register to “0”.) If you are using the bus powered
supply in this condition, the DC-DC converter must be placed outside the MCU.
•In Vcc = 4.00 to 5.25 V operation, do not connect the external DC-DC converter to the USBVREF pin.
Use the built-in USB reference voltage circuit.
(3) USB Communication
•In applications requiring high-reliability, we recommend providing the system with protective measures
such as USB function initialization by software or USB reset by the host to prevent USB communication
from being terminated unexpectedly, for example due to external causes such as noise.
Rev.2.00 Oct 15, 2006 page 26 of 99
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APPENDIX
38K2 Group
3.2 Notes on use
3.2.7 Notes on A/D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
ꢀ Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion precision to be worse.
(2) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(XIN) is 500 kHz or more
• Do not execute the STP instruction
3.2.8 Notes on watchdog timer
ꢀMake sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog
timer keeps counting during that term.
ꢀWhen the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program
____________
3.2.9 Notes on RESET pin
Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
ꢀ Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.2.10 Notes on PLL
ꢀ6 MH
Z
or 12 MH external oscillator can be connected as an input reference clock (f(XIN)). When using
Z
the frequency synthesized clock function, we recommend using the fastest frequency possible of f(XIN
as an input clock reference for the PLL.
)
ꢀWhen enabling PLL operation from PLL disabled status (disabled when reset), set the USB clock select
bit of USBCON to “0” (f(XIN)) to operate with the main clock (f(XIN)).
ꢀWhen supplying fVCO to the USB block after setting PLL operation enable bit to “1” (PLL enabled), wait
for the oscillation stable time (1 ms or less) of PLL to avoid any instability caused by the clock, then set
USB clock select bit to “1” (USB clock).
ꢀWhen selecting fSYN as an internal system clock, fUSB must be 48 MHz.
ꢀWhen selecting fSYN as an internal system clock, change the system clock selection bit to main clock
(f(XIN)) before executing STP instruction. It is because the following are needed for the low-power consumption:
•fUSB must be stopped by disabling PLL operation in Stop mode.
•The taimer 1 for waiting oscillation stabilization when returning from Stop mode will require the input
count source.
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APPENDIX
38K2 Group
3.2 Notes on use
3.2.11 Notes on stand-by function
(1) Notes on using stop mode
ꢀRegister setting
Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the
stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP
instruction released bit is “0”)
ꢀClock restoration
When the main clock side is set as a system clock, the oscillation stabilizing time for approximately
8,000 cycles of the XIN input is reserved at restoration from the stop mode.
(2) Notes on stand-by function
In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”.
Pull-up (connect the port to VCC) these ports through a resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values.
• When setting as an input port: Fix its input level
• When setting as an output port: Prevent current from flowing out to external
ꢀꢀReason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of an input port and an I/O port are “undefined”. This may cause power source current.
*1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
3.2.12 Notes on CPU rewrite mode
(1) Operation speed
During CPU rewrite mode, set the internal clock φ 1.5 MHz or less using the system clock division
ratio selection bits (bits 6 and 7 of address 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during the CPU
rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data
of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog
timer underflow does not happen, because of watchdog timer is always clearing during program or
erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = “H” when reset is released, boot mode is active. So the
program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area.
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APPENDIX
38K2 Group
3.2 Notes on use
3.2.13 Notes on programming
(1) Processor status register
ꢀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
ꢀ Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.2.4 Initialization of processor status register
ꢀ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
(S)
↓
(S)+1
Stored PS
NOP
Fig. 3.2.5 Sequence of PLP instruction execution
Fig. 3.2.6 Stack memory contents after PHP
instruction execution
(2) BRK instruction
ꢀ Interrupt priority level
When the BRK instruction is executed with the following conditions satisfied, the interrupt execution
is started from the address of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
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APPENDIX
38K2 Group
3.2 Notes on use
(3) Decimal calculations
ꢀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
ꢀ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.2.7 Status flag at decimal calculations
(4) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a page
as an indirect address.
(5) Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
(6) Ports
The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
(7) Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock f by the number
of cycles needed to execute an instruction.
The number of cycles required to execute an instruction is shown in the list of machine instructions.
The frequency of the internal clock f is half of the XIN frequency in high-speed mode.
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APPENDIX
38K2 Group
3.2 Notes on use
3.2.14 Notes on flash memory version
The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has
the multiplexed function to be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10
kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss
pin or Vcc pin via a resistor.
3.2.15 Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation
between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes.
When manufacturing an application system with the Flash Memory version and then switching to use of the
Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM
version.
Rev.2.00 Oct 15, 2006 page 31 of 99
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APPENDIX
38K2 Group
3.3 Countermeasures against noise
3.3 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.3.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Package
Select the smallest possible package to make the total wiring length short.
ꢀ Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.3.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
ꢀ Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
Reset
circuit
RESET
RESET
V
SS
V
SS
V
SS
V
SS
N.G.
O.K.
Fig. 3.3.2 Wiring for the RESET pin
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APPENDIX
38K2 Group
3.3 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is
connected to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
ꢀ Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the VSS
level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
X
X
V
IN
X
X
V
IN
OUT
SS
OUT
SS
O.K.
N.G.
Fig. 3.3.3 Wiring for clock I/O pins
(4) Wiring to CNVSS pin
Connect the CNVSS pin to the VSS pin with the shortest possible wiring.
ꢀ Reason
The processor mode of a microcomputer is influenced by a potential at the CNVSS pin. If a
potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may
become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
CNVSS
CNVSS
V
SS
V
SS
O.K.
N.G.
Fig. 3.3.4 Wiring for CNVSS pin
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APPENDIX
38K2 Group
3.3 Countermeasures against noise
(5) Wiring to VPP pin of Flash memory version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the
VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the
VSS pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
ꢀ Reason
The VPP pin of the flash memory version is the power source input pin for the built-in flash
memory. When programming in the built-in flash memory, the impedance of the VPP pin is low to
allow the electric current for writing flow into the flash memory. Because of this, noise can enter
easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in
flash memory, which may cause a program runaway.
Approximately
5kΩ
CNVSS/VPP
V
SS
In the shortest
distance
Fig. 3.3.5 Wiring for the VPP pin of the flash memory version
3.3.2 Connection of bypass capacitor across VSS line and VCC line
Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin.
V
CC
V
CC
V
SS
V
SS
N.G.
O.K.
Fig. 3.3.6 Bypass capacitor across the VSS line and the VCC line
Rev.2.00 Oct 15, 2006 page 34 of 99
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APPENDIX
38K2 Group
3.3 Countermeasures against noise
3.3.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the VSS pin at equal length.
ꢀ Reason
Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from
the VSS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
O.K.
N.G.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.3.7 Analog signal line and a resistor and a capacitor
Rev.2.00 Oct 15, 2006 page 35 of 99
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APPENDIX
38K2 Group
3.3 Countermeasures against noise
3.3.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
ꢀ Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
inductance
M
X
X
IN
Large
current
OUT
V
SS
GND
Fig. 3.3.8 Wiring for a large current signal line
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
ꢀ Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
CNTR
Do not cross
X
X
V
IN
OUT
SS
Fig. 3.3.9 Wiring of RESET pin
Rev.2.00 Oct 15, 2006 page 36 of 99
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APPENDIX
38K2 Group
3.3 Countermeasures against noise
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides,
separate this VSS pattern from other VSS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
X
X
V
IN
OUT
SS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.3.10 VSS pattern on the underside of an oscillator
3.3.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
Noise
O.K.
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.3.11 Setup for I/O ports
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APPENDIX
38K2 Group
3.3 Countermeasures against noise
3.3.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
Interrupt processing routine
(SWDT) ← (SWDT)—1
Interrupt processing
Main routine
(SWDT)← N
CLI
Main processing
>0
(SWDT)
≤0?
RTI
≠N
≤0
(SWDT)
=N?
Return
N
Interrupt processing
routine errors
Main routine
errors
Fig. 3.3.12 Watchdog timer by software
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APPENDIX
38K2 Group
3.4 List of registers
3.4 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6) (Note)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16
]
At reset
B
Name
Function
R W
?
?
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
ꢀ
ꢀ
In output mode
Write
Read
Port latch
In input mode
Write : Port latch
Read : Value of pins
?
?
?
?
?
?
Note: Since the following ports are not allocated, the corrrsponding bits can not be used.
• P2
• P4
• P6
0
4
4
to P2
to P4
to P6
3
7
7
Fig. 3.4.1 Structure of Port Pi
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6) (Note)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16
]
Name
Function
input mode
output mode
At reset
B
0
R W
0 : Port Pi
1 : Port Pi
0
0
Port Pi direction register
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : Port Pi
1 : Port Pi
1
1
input mode
output mode
1
2
3
4
5
6
7
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
0 : Port Pi
1 : Port Pi
3
3
input mode
output mode
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
input mode
output mode
0 : Port Pi
1 : Port Pi
7
7
input mode
output mode
Note: Since the following ports are not allocated, the corrrsponding bits can not be used.
• P2
• P4
• P6
0
4
4
to P2
to P4
to P6
3
7
7
Do not set bits of the direction register corresponding to ports P2
register (address 0516)) to output mode (“1”).
If writing to these bits, write “0”.
0–P23 (bits 0–3 of port P2 direction
Fig. 3.4.2 Structure of Port Pi direction register
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
USB control register (USBCON) [address 001016
]
At reset
R W
Bit name
Function
Bit symbol
WKUP
H/W S/W
Remote wakeup bit
0 : Returning to BUS idle state by writing “1” first and
then “0”. (Remote wakeup signal)
0
–
O O
1 : K-state output
TRONCON TrON output control bit
TRONE TrON output enable bit
0 : “L” output mode (valid in TRONE = “1”)
1 : “H” output mode (valid in TRONE = “1”)
0 : TrON port output disabled (Hi-Z state)
1 : TrON port output enabled
0
0
0
0
0
0
0
–
–
–
–
–
–
–
O O
O O
O O
O O
O O
O O
O O
VREFCON USB reference voltage control bit 0 : Normal mode (valid in VREFE = “1”)
1 : Low current mode (valid in VREFE = “1”)
VREFE
USB reference voltage enable bit 0 : USB reference voltage circuit operation disabled
1 : USB reference voltage circuit operation enabled
USBDIFE
USB difference input enable bit 0 : Upstream-port difference input circuit operation disabled
1 : Upstream--port difference input circuit operation enabled
UCLKCON USB clock select bit
0 : External oscillating clock f(XIN
)
1 : PLL circuit output clock fVCO
USBE
USB module operation enable bit 0 : USB module reset
1 : USB module operation enabled
–: State remaining
Fig. 3.4.3 Structure of USB control register
b0
b7
0
USB function/HUB enable register (USBAE) [address 001116
]
0
0
0 0 0
At reset
Bit symbol
AD0E
Function
Bit name
R W
H/W S/W
USB function enable bit
0: USB function address register invalidated
1: USB function address register validated
0: USB HUB address register invalidated
1: USB HUB address register validated
Write “0” when writing.
0
0
–
–
–
–
O O
O O
O O
AD1E
b7:b2
USB HUB enable bit
Not used
“0” is read when reading.
–: State remaining
Fig. 3.4.4 Structure of USB function/HUB enable register
b0
b7
0
USB function address register (USBA0) [address 001216
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
USBADD0 USB function address bit
[6:0]
In AD0E = “0”, this value changes after writing.
In AD0E = “1”, this value changes after completion of
SET_ADDRESS control transferring.
Write “0” when writing.
0
0
O O
b7
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.5 Structure of USB function address register
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
0
USB HUB address register (USBA1) [address 001316
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
USBADD1 USB HUB address bit
[6:0]
In AD1E = “0”, this value changes after writing.
In AD1E = “1”, this value changes after completion of
SET_ADDRESS control transferring.
Write “0” when writing.
0
0
O O
b7
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.6 Structure of USB HUB address register
b0
b7
Frame number register Low (FNUML) [address 001416
]
At reset
R W
Bit symbol
Function
The frame number is updated at SOF reception.
Bit name
H/W S/W
FNUM
[7:0]
Frame number low bit
In-
In-
O ꢀ
definite definite
Fig. 3.4.7 Structure of Frame number register Low
b0
b7
0
0
0
0
0
Frame number register High (FNUMH) [address 001516]
At reset
H/W S/W
Bit symbol
Function
R W
Bit name
In-
In-
FNUM
[10:8]
b7:b3
Frame number high bit
The frame number is updated at SOF reception.
O
ꢀ
definite definite
–
–
Not used
Write “0” when writing.
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.8 Structure of Frame number register High
b0
b7
USB interrupt source enable register (USBICON) [address 001616
]
At reset
R W
Bit symbol
EP00E
Function
Bit name
H/W S/W
USB function/Endpoint 0 interrupt 0 : Interrupt disabled
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O O
O O
O O
O O
O O
O O
O O
O O
enable bit
USB function/Endpoint 1 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
USB function/Endpoint 2 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
USB function/Endpoint 3 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
USB HUB/Endpoint 0 interrupt 0 : Interrupt disabled
enable bit
1 : Interrupt enabled
USB HUB/Endpoint 1 interrupt 0 : Interrupt disabled
1 : Interrupt enabled
EP01E
EP02E
EP03E
EP10E
EP11E
SUSE
enable bit
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Suspend interrupt enable bit
RSME
Resume interrupt enable bit
Fig. 3.4.9 Structure of USB interrupt source enable register
Rev.2.00 Oct 15, 2006 page 41 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
b0
b7
USB interrupt source register (USBIREQ) [address 001716
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
EP00
EP01
EP02
EP03
EP10
EP11
SUS
USB function/Endpoint 0
interrupt bit
This bit is set to “1” when any one of EP00 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP00 interrupt
source register to “0016”.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
O
O
O
O
O
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP01 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP01 interrupt
source register to “0016”.
USB function/Endpoint 1
interrupt bit
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP02 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP02 interrupt
source register to “0016”.
USB function/Endpoint 2
interrupt bit
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP03 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP03 interrupt
source register to “0016”.
USB function/Endpoint 3
interrupt bit
Writing to this bit causes no state change.
USB HUB/Endpoint 0 interrupt This bit is set to “1” when any one of EP10 interrupt
bit
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP10 interrupt
source register to “0016”.
Writing to this bit causes no state change.
USB HUB/Endpoint 1 interrupt This bit is set to “1” when any one of EP11 interrupt
bit
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP11 interrupt
source register to “0016”.
Writing to this bit causes no state change.
0 : No interrupt request issued
Suspend interrupt bit
O O
1 : Interrupt request issued
This bit is set to “1” when detecting 3 ms or more of J-
state, using USB clock (fUSB) at 48 MHz.
“0” can be set by software, but “1” cannot be set.
This bit is set to “1” when the USB bus state changes
from J-state to K-state or SE0 in the resume interrupt
enable bit = “1”. It is also “1” in the condition of internal
clock stopped.
RSM
Resume interrupt bit
O
ꢀ
This bit is cleared to “0” by clearing the resume
interrupt enable bit.
Writing to this bit causes no state change.
Fig. 3.4.10 Structure of USB interrupt source register
b0
b7
0
Endpoint index register (USBINDEX) [address 001816
]
0
0
0
0
At reset
Bit symbol
Bit name
Function
R W
O O
H/W S/W
EPIDX [1:0] Endpoint index bit
b1 b0
0
–
0
0
1
1
0 : Endpoint 0
1 : Endpoint 1
0 : Endpoint 2
1 : Endpoint 3
ADIDX
b7:b3
Address index bit
Not used
0 : USB function
1 : USB HUB
0
–
–
O O
O O
Write “0” when writing.
–
“0” is read when reading.
–: State remaining
Fig. 3.4.11 Structure of Endpoint index register
Rev.2.00 Oct 15, 2006 page 42 of 99
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP00 stage register (EP00STG) [address 001916
]
0
0
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
SETUP00
b7:b1
SETUP packet detection bit
This bit is set to “1” at reception of SETUP packet.
Writing “0” to this bit clears this bit if the next SETUP
token does not occur.
1
1
O O
Writing “1” to this bit causes no state change of the
status flags.
Not used
Write “0” when writing.
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.12 Structure of EP00 stage register
b0
b7
EP01 set register (EP01CFG) [address 001916
]
At reset
R W
Bit symbol
Function
Double buffer beginning address set In double buffer mode set the beginning address of
Bit name
H/W S/W
BSIZ01
[1:0]
0
–
O O
bit
buffer 1 area, using a relative value for the beginning
address of buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
DBLB01
SQCL01
Buffer mode select bit
0 : Single buffer mode
0
0
–
–
O O
O O
1 : Double buffer mode
Sequence toggle bit clear bit
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
ITMD01
DIR01
Interrupt toggle mode select bit 0 : Normal mode
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0
0
0
–
–
–
O O
O O
O O
Transfer direction bit
0 : OUT (Data is received from the host.)
1 : IN (Data is transmitted to the host.)
b7b6
TYP01
[1:0]
Transfer type bite
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
–: State remaining
Fig. 3.4.13 Structure of EP01 set register
Rev.2.00 Oct 15, 2006 page 43 of 99
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP02 set register (EP02CFG) [address 001916
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BSIZ02
[1:0]
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1
0
–
O O
bit
area, using a relative value for the beginning address of
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
DBLB02
SQCL02
Buffer mode select bit
0 : Single buffer mode
1 : Double buffer mode
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
0
0
–
–
O O
O O
Sequence toggle bit clear bit
“0” is always read when reading.
ITMD02
DIR02
Interrupt toggle mode select bit 0 : Normal mode
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0
0
0
–
–
–
O O
O O
O O
Transfer direction bit
0 : OUT (Data is received from the host.)
1 : IN (Data is transmitted to the host.)
b7b6
TYP02
[1:0]
Transfer type bite
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
–: State remaining
Fig. 3.4.14 Structure of EP02 set register
b0
b7
EP03 set register (EP03CFG) [address 001916
]
At reset
R W
Bit symbol
Function
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1
Bit name
H/W S/W
BSIZ03
[1:0]
0
–
O O
bit
area, using a relative value for the beginning address of
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
DBLB03
SQCL03
Buffer mode select bit
0 : Single buffer mode
1 : Double buffer mode
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
0
0
–
–
O O
O O
Sequence toggle bit clear bit
“0” is always read when reading.
ITMD03
DIR03
Interrupt toggle mode select bit 0 : Normal mode
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0
0
0
–
–
–
O O
O O
O O
Transfer direction bit
0 : OUT (Data is received from the host.)
1 : IN (Data is transmitted to the host.)
b7b6
TYP03
[1:0]
Transfer type bit
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
–: State remaining
Fig. 3.4.15 Structure of EP03 set register
Rev.2.00 Oct 15, 2006 page 44 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP10 stage register (EP10STG) [address 001916
]
0
0
0
0
0
0
0
At reset
R W
H/W S/W
Bit symbol
Bit name
Function
SETUP10
b7:b1
SETUP packet detection bit
This bit is set to “1” at reception of SETUP packet.
Writing “0” clears this bit if the next SETUP token does
not occur.
1
1
O O
Writing “1” causes no state change of the status flags.
This bit change is not for an interrupt source.
Write “0” when writing.
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.16 Structure of EP10 stage register
b0
0
b7
0
0
0
0
EP11 set register (EP11CFG) [address 001916
]
At reset
Bit symbol
b2:b0
Function
Bit name
R W
H/W S/W
–
–
O O
Write “0” when writing.
Not used
“0” is read when reading.
0 : Toggle bit clear disabled
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
0
–
SQCL11
Sequence toggle bit clear bit
“0” is always read when reading.
Write “0” when writing.
–
0
–
0
–
–
–
–
O O
O O
O O
O O
b4
Not used
“0” is read when reading.
0 : IN transfer disabled
DIR11
b6
Transfer direction bit
Not used
1 : IN (Data is transmitted to the host.)
Write “0” when writing.
“0” is read when reading.
0 : Transfer disabled
TYP11
Transfer type bite
1 : Interrupt transfer
–: State remaining
Fig. 3.4.17 Structure of EP11 set register
b0
b7
0
EP00 control register 1 (EP00CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
PID00 [1:0] Response PID bit
Function
Bit name
H/W S/W
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.18 Structure of EP00 control register 1
Rev.2.00 Oct 15, 2006 page 45 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP01 control register 1 (EP01CON1) [address 001A16
]
0
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID01
[1:0]
Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.19 Structure of EP01 control register 1
b0
b7
0
EP02 control register 1 (EP02CON1) [address 001A16
]
0
0
0
0 0
At reset
R W
Bit symbol
Function
Bit name
Response PID bit
H/W S/W
PID02
[1: 0]
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.20 Structure of EP02 control register 1
b0
b7
0
EP03 control register 1 (EP03CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
Function
Bit name
Response PID bit
H/W S/W
PID03
[1:0]
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.21 Structure of EP03 control register 1
Rev.2.00 Oct 15, 2006 page 46 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP10 control register 1 (EP10CON1) [address 001A16
]
0
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
PID10 [1:0] Response PID bit
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (ACK, NAK, DATA0, DATA1)
X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
b7:b2
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.22 Structure of EP10 control register 1
b0
b7
0
EP11 control register 1 (EP11CON1) [address 001A16
]
0
0
0
0
0
At reset
R W
Bit symbol
Function
Bit name
Response PID bit
H/W S/W
PID11
[1:0]
0
–
b1 b0
O O
0
0
1
0 : NAK
1 : Automatic response (NAK, DATA0, DATA1)
X : STALL
b7:b2
Not used
–
–
Write “0” when writing.
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.23 Structure of EP11 control register 1
b0
b7
0
0
0
0
0
0
0
EP00 control register 2 (EP00CON2) [address 001B16]
At reset
R W
Bit symbol
BVAL00
Function
Bit name
Buffer enable bit
H/W S/W
O O
0
–
0 : NAK transmission (SIE is disabled to read a buffer.)
1 : Transmitting/receiving data set state (SIE is possible
to read from/write to a buffer.)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
O O
b7:b1
Not used
–
–
“0” is read when reading.
–: State remaining
Fig. 3.4.24 Structure of EP00 control register 2
Rev.2.00 Oct 15, 2006 page 47 of 99
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
0
0
0
0
0
0
0
EP01 control register 2 (EP01CON2) [address 001B16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0VAL01
0
–
O O
Buffer 0 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
b7:b1
–
–
O O
Not used
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 3.4.25 Structure of EP01 control register 2
b0
b7
0
EP02 control register 2 (EP02CON2) [address 001B16
]
0
0
0
0
0
0
At reset
R W
Bit symbol
B0VAL02
Function
Bit name
Buffer 0 enable bit
H/W S/W
0
–
O O
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
b7:b1
–
–
O O
Not used
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 3.4.26 Structure of EP02 control register 2
b0
b7
0
0
0
0
0
0
0
EP03 control register 2 (EP03CON2) [address 001B16
]
At reset
R W
Bit symbol
B0VAL03
Function
Bit name
Buffer 0 enable bit
H/W S/W
0
–
O O
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
b7:b1
–
–
O O
Not used
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 3.4.27 Structure of EP03 control register 2
Rev.2.00 Oct 15, 2006 page 48 of 99
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
0
0
0
0
0
0
0
EP10 control register 2 (EP10CON2) [address 001B16]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
O O
BVAL10
b7:b1
Buffer enable bit
Not used
0
–
0 : NAK transmission (SIE is disabled to read a buffer.)
1 : Transmitting/receiving data set state (SIE is possible to
read from/write to a buffer.) (Valid in PID10 = “012”)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
O O
–
–
“0” is read when reading.
–: State remaining
Fig. 3.4.28 Structure of EP10 control register 2
b0
b7
0
0
0
0
0
0
0
EP11 control register 2 (EP11CON2) [address 001B16
]
At reset
R W
Bit symbol
B0VAL11
Function
Bit name
Buffer 0 status bit
H/W S/W
0
–
O O
O O
This bit set to “1” shows the transmitting data is in a set
state (SIE is possible to read).
b7:b1
–
–
Write “0” when writing.
Not used
“0” is read when reading.
–: State remaining
Fig. 3.4.29 Structure of EP11 control register 2
b0
b7
0
EP00 control register 3 (EP00CON3) [address 001C16
]
0
0
0
0
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
CTENDE00 Control transfer completion
enable bit
0
–
0 : NAK transmission in the status stage
O O
1 : Control transfer completion enabled (SIE transmits
NULL/ACK.) (valid in PID00 = “012”)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
b7:b1
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.30 Structure of EP00 control register 3
Rev.2.00 Oct 15, 2006 page 49 of 99
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP01 control register 3 (EP01CON3) [address 001C16
]
0
0
0
0
0 0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B1VAL01
0
–
O O
Buffer 1 enable bit
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
Write “0” when writing.
b7:b1
–
–
O O
Not used
“0” is read when reading.
–: State remaining
Fig. 3.4.31 Structure of EP01 control register 3
b0
b7
0
0
0
0
0
0
0
EP02 control register 3 (EP02CON3) [address 001C16
]
At reset
R W
Bit symbol
B1VAL02
Function
Bit name
Buffer 1 enable bit
H/W S/W
0
–
O O
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
Write “0” when writing.
b7:b1
–
–
O O
Not used
“0” is read when reading.
–: State remaining
Fig. 3.4.32 Structure of EP02 control register 3
b0
b7
0
EP03 control register 3 (EP03CON3) [address 001C16
]
0
0
0
0 0 0
At reset
R W
Bit symbol
B1VAL03
Function
Bit name
Buffer 1 enable bit
H/W S/W
0
–
O O
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
Write “0” when writing.
b7:b1
–
–
O O
Not used
“0” is read when reading.
–: State remaining
Fig. 3.4.33 Structure of EP03 control register 3
Rev.2.00 Oct 15, 2006 page 50 of 99
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP10 control register 3 (EP10CON3) [address 001C16
]
0
0
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
CTENDE10 Control transfer completion
enable bit
0
–
0 : NAK transmission in the status stage
1 : Control transfer completion enabled (SIE transmits
NULL/ACK.) (Valid in PID10 = “012”)
At reception of SETUP token:
O O
This bit is cleared to “0” by the hardware.
Write “0” when writing.
b7:b1
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.34 Structure of EP10 control register 3
b0
b7
0
EP00 interrupt source register (EP00REQ) [address 001D16]
0
0
At reset
R W
Bit symbol
BRDY00
Function
USB function/Endpoint 0 buffer 0: No interrupt request issued
Bit name
H/W S/W
0
0
O O
ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
CTEND00
CTSTS00
USB function/Endpoint 0 control 0: No interrupt request issued
transfer completion interrupt bit 1: Interrupt request issued
0
0
O O
This bit is set to “1” when control transfer is completed
(NULL/ACK transmission in the status stage) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 0 status 0: No interrupt request issued
0
0
O O
stage transition interrupt bit
1: Interrupt request issued
This bit is set to “1” when transition to status stage
occurs in CTENDE00 = “0” (control transfer completion
disabled) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
<Transition to status stage occurrence factor>
At transfer of control write:
When receiving IN-token in data stage (OUT)
At transfer of control read:
When receiving OUT-token in data stage (IN)
At no data transfer:
Nothing occurs.
BSRDY00
ERR00
USB function/Endpoint 0 SETUP 0: No interrupt request issued
0
0
0
0
O O
buffer ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the exclusive buffer for
SETUP is ready state (enabled to be read) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
USB function/Endpoint 0 error
interrupt bit
O O
1: Interrupt request issued
This bit is set to “1” when control transfer error occurs
on USB function/Endpoint 0.
This bit is cleared to “0” by the hardware when
receiving SETUP token.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
b7:b5
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.35 Structure of EP00 interrupt source register
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP01 interrupt source register (EP01REQ) [address 001D16
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0RDY01
B1RDY01
0
0
USB function/Endpoint 1 buffer 0
ready interrupt bit
O O
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
0
0
USB function/Endpoint 1 buffer 1
ready interrupt bit
O O
1: Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 1
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
ERR01
b7:b3
0
0
USB function/Endpoint 1 error
interrupt bit
O O
O O
1: Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
–
–
Not used
“0” is read when reading.
Fig. 3.4.36 Structure of EP01 interrupt source register
b0
b7
0
EP02 interrupt source register (EP02REQ) [address 001D16
]
0
0
0
0
At reset
H/W S/W
Bit symbol
Bit name
R W
O O
Function
B0RDY02
B1RDY02
0
0
USB function/Endpoint 2 buffer 0
ready interrupt bit
0 : No interrupt request issued
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
0
0
USB function/Endpoint 2 buffer 1
ready interrupt bit
O O
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 2
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
ERR02
0
0
USB function/Endpoint 2 error
interrupt bit
O O
O O
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
b7 to b3
–
–
Not used
“0” is read when reading.
Fig. 3.4.37 Structure of EP02 interrupt source register
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP03 interrupt source register (EP03REQ) [address 001D16
]
0
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0RDY03
B1RDY03
0
0
USB function/Endpoint 3 buffer 0
ready interrupt bit
O O
0 : No interrupt request issued
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
0
0
USB function/Endpoint 3 buffer 1
ready interrupt bit
O O
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 3
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
0 : No interrupt request issued
ERR03
b7:b3
0
0
USB function/Endpoint 3 error
interrupt bit
O O
O O
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
–
–
Not used
“0” is read when reading.
Fig. 3.4.38 Structure of EP03 interrupt source register
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP10 interrupt source register (EP10REQ) [address 001D16
]
0
0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BRDY10
USB HUB/Endpoint 10 buffer
ready interrupt bit
0: No interrupt request issued
0
0
O O
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
CTEND10
USB HUB/Endpoint 10 control
0
0
O O
transfer completion interrupt bit 1: Interrupt request issued
This bit is set to “1” when control transfer is completed
(NULL/ACK transmission in the status stage) on USB
HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
CTSTS10
USB HUB/Endpoint 10 status
stage transition interrupt bit
0
0
O O
1: Interrupt request issued
This bit is set to “1” when transition to status stage
occurs in CTENDE10 = “0” (control transfer completion
disabled) on USB HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
<Transition to status stage occurrence factor>
At transfer of control write:
When receiving IN-token in data stage (OUT)
At transfer of control read:
When receiving OUT-token in data stage (IN)
At no data transfer:
Nothing occurs.
BSRDY10
ERR10
USB HUB/Endpoint 10 SETUP 0: No interrupt request issued
0
0
0
0
O O
buffer ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the exclusive buffer for
SETUP is ready state (enabled to be read) on USB
HUB/Endpoint 10.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
USB HUB/Endpoint 10 error
interrupt bit
O O
1: Interrupt request issued
This bit is set to “1” when control transfer error occurs
on USB HUB/Endpoint 10.
This bit is cleared to “0” by the hardware when
receiving SETUP token.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
b7:b5
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.39 Structure of EP10 interrupt source register
b0
b7
0
EP11 interrupt source register (EP11REQ) [address 001D16
]
0
0
0 0 0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
B0RDY11
b7:b1
USB HUB/Endpoint 1 buffer 0
ready interrupt bit
0: No interrupt request issued
0
0
O O
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB HUB/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.40 Structure of EP11 interrupt source register
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP00 byte number register (EP00BYT) [address 001E16
]
0
0
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BBYT00
[3:0]
OUT : The received byte number is automatically set.
IN : Set the transmitting byte number.
Write 0 when writing.
0
—
Transmit/receive byte number bit
Not used
O O
O O
b7:b4
—
—
0 is read when reading.
—: State remaining
Fig. 3.4.41 Structure of EP00 byte number register
b0
b7
0
EP01 byte number register 0 (EP01BYT0) [address 001E16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
–
IN : Transmit byte number bit
O O
B0BYT01
[6:0]
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
0
–
OUT : Receive byte number bit
O ꢀ
Single buffer mode : The received byte number is
automatically set.
Double buffer mode :The received byte number of buffer 0
is automatically set.
–
–
Not used
O O
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 3.4.42 Structure of EP01 byte number register 0
b0
b7
0
EP02 byte number register 0 (EP02BYT0) [address 001E16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
–
IN : Transmit byte number bit
O O
B0BYT02
[6:0]
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
0
–
OUT : Receive byte number bit
O ꢀ
Single buffer mode: The received byte number is
automatically set.
Double buffer mode :The received byte number of buffer 0
is automatically set.
–
–
Not used
O O
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 3.4.43 Structure of EP02 byte number register 0
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
0
EP03 byte number register 0 (EP03BYT0) [address 001E16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
0
–
IN : Transmit byte number bit
O O
B0BYT03
[6:0]
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
0
–
OUT : Receive byte number bit
O ꢀ
Single buffer mode: The received byte number is
automatically set.
Double buffer mode :The received byte number of buffer 0
is automatically set.
–
–
Not used
O O
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 3.4.44 Structure of EP03 byte number register 0
b0
b7
0
EP10 byte number register (EP10BYT) [address 001E16
]
0
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
BBYT10
[3:0]
OUT : The received byte number is automatically set.
IN : Set the transmitting byte number.
Write 0 when writing.
0
—
Transmit/receive byte number bit
O O
O O
b7:b4
—
—
Not used
0 is read when reading.
—: State remaining
Fig. 3.4.45 Structure of EP10 byte number register
b0
b7
0
EP11 byte number register (EP11BYT0) [address 001E16
]
0
0
0
0
0
0
At reset
R W
Bit symbol
B0BYT11
Function
Bit name
H/W S/W
IN : Set the transmitting byte number.
0
—
Transmit byte number bit
O O
O O
b7:b1
Write 0 when writing.
0 is read when reading.
—
—
Not used
—: State remaining
Fig. 3.4.46 Structure of EP11 byte number register 0
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
0
EP01 byte number register 1 (EP01BYT1) [address 001F16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
0
0
–
–
–
–
IN : Transmit byte number bit
OUT : Receive byte number bit
Not used
O
O
O
O
ꢀ
O
B1BYT01
[6:0]
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode :The received byte number of buffer 1
is automatically set.
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 3.4.47 Structure of EP01 byte number register 1
b0
b7
0
EP02 byte number register 1 (EP02BYT1) [address 001F16
]
At reset
Bit symbol
Bit name
Function
R W
H/W S/W
0
0
–
–
–
–
IN : Transmit byte number bit
OUT : Receive byte number bit
Not used
O O
O ꢀ
O O
B1BYT02
[6:0]
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode :The received byte number of buffer 1
is automatically set.
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 3.4.48 Structure of EP02 byte number register 1
b0
b7
0
EP03 byte number register 1 (EP03BYT1) [address 001F16
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0
0
–
–
–
–
IN : Transmit byte number bit
O O
O ꢀ
O O
B1BYT03
[6:0]
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
OUT : Receive byte number bit
Not used
Single buffer mode: These bits are invalid.
Double buffer mode :The received byte number of buffer 1
is automatically set.
b7
Write “0” when writing.
“0” is read when reading.
–: State remaining
Fig. 3.4.49 Structure of EP03 byte number register 1
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APPENDIX
38K2 Group
3.4 List of registers
Prescaler 12, Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12) [Address : 2016
]
Prescaler X (PREX) [Address : 2416
]
B
At reset
Name
R W
Function
0
1
2
1
1
1
•Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres-
ponding prescaler is read out.
3
4
1
1
1
5
6
7
1
1
Fig. 3.4.50 Structure of Prescaler12, Prescaler X
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2116
]
B
At reset
Name
R W
Function
0
1
2
1
0
0
•Set a count value of timer 1.
•The value set in this register is written to both timer 1 and timer 1
latch at the same time.
•When this register is read out, the timer 1’s count value is read
out.
3
4
0
0
0
5
6
7
0
0
Fig. 3.4.51 Structure of Timer 1
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APPENDIX
38K2 Group
3.4 List of registers
Timer 2, Timer X
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address : 2216
]
Timer X (TX) [Address : 2516
]
At reset
Name
R W
B
0
Function
1
1
•Set a count value of each timer.
•The value set in this register is written to both each timer and
each timer latch at the same time.
•When this register is read out, each timer’s count value is read
out.
1
2
1
1
1
3
4
5
6
7
1
1
1
Fig. 3.4.52 Structure of Timer 2, Timer X
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register (TM) [Address : 2316
]
At reset
Function
B
0
Name
R W
b1 b0
Timer X operating mode bits
0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement
mode
1
2
0
0
The function depends on the
operating mode of Timer X.
(Refer to Table 2.3.1)
CNTR
bit
0
active edge selection
0 : Count start
1 : Count stop
Timer X count stop bit
3
4
0
0
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are “0”.
0
0
0
5
6
7
Fig. 3.4.53 Structure of Timer X mode register
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APPENDIX
38K2 Group
3.4 List of registers
Transmit/Receive buffer register
b1
b7 b6 b5 b4 b3 b2
b0
Transmit/Receive buffer register (TB/RB) [Address : 2616]
B
At reset
Name
R W
Function
0
1
2
?
?
?
The transmission data is written to or the receive data is read out
from this buffer register.
• At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
out.
3
4
?
?
?
5
6
7
?
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 3.4.54 Structure of Transmit/Receive buffer register
Serial I/O status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O status register (SIOSTS) [Address : 2716
]
At reset
Function
0 : Buffer full
1 : Buffer empty
B
0
Name
Transmit buffer empty flag
R W
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
(TBE)
0 : Buffer empty
1 : Buffer full
1
2
Receive buffer full flag (RBF)
0 : Transmit shift in progress
1 : Transmit shift completed
Transmit shift register shift
completion flag (TSC)
0 : No error
Overrun error flag (OE)
3
4
5
0
0
0
1 : Overrun error
0 : No error
Parity error flag (PE)
1 : Parity error
0 : No error
Framing error flag (FE)
Summing error flag (SE)
1 : Framing error
0 : (OE) U (PE) U (FE) = 0
1 : (OE) U (PE) U (FE) = 1
6
7
0
1
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the contents are “1”.
Fig. 3.4.55 Structure of Serial I/O status register
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
0
0
0
0
0
HUB interrupt source enable register (HUBICON) [address 002816
]
At reset
R W
Bit symbol
DP1E
Function
Bit name
H/W S/W
HUB downstream port 1 interrupt 0 : Interrupt disabled
enable bit
HUB downstream port 2 interrupt 0 : Interrupt disabled
O O
O O
O O
O O
0
0
–
0
–
–
–
–
1 : Interrupt enabled
DP2E
enable bit
Not used
1 : Interrupt enabled
b6:b2
Write “0” when writing.
“0” is read when reading.
0 : Disabled
HUB upstream port remote-
wakeup output enable bit
HRWUE
1 : Enabled
–: State remaining
Fig. 3.4.56 Structure of HUB interrupt source enable register
b0
b7
0
0
0
0
0
HUB interrupt source register (HUBIREQ) [address 002916
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
DP1
DP2
0
–
This bit is set to “1” when any one of DP1 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing DP1 interrupt
source register to “0016”.
HUB downstream port 1
interrupt bit
O ꢀ
Writing to this bit causes no state change.
This bit is set to “1” when any one of DP2 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing DP2 interrupt
source register to “0016”.
0
–
HUB downstream port 1
interrupt bit
O ꢀ
Writing to this bit causes no state change.
Write “0” when writing.
b6:b2
–
–
–
Not used
O O
O O
“0” is read when reading.
HRWU
0
0 : Remote-wakeup being not output
HUB upstream port remote
-wakeup output enable bit
1 : Remote-wakeup being output
This bit change is not for a interrupt source.
When detecting 2.5 µs or more of K-signal on a
downstream port in Hub-suspended state, K-signal is
output on from
a upstream port and this bit is
simultaneously set to “1”.
“0” can be set by software, but “1” cannot be set.
–: State remaining
Fig. 3.4.57 Structure of HUB interrupt source register
b0
b7
0
0
0
0
0
0
0
HUB downstream port index register (HUBINDEX) [address 002A16
]
At reset
R W
Bit symbol
DPIDX
Function
Bit name
H/W S/W
HUB downstream port index bit 0 : HUB downstream port 1
1 : HUB downstream port 2
0
–
O O
O O
b7:b1
Not used
Write “0” when writing.
–
–
“0” is read when reading.
–: State remaining
Fig. 3.4.58 Structure of HUB downstream port index register
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
DP1 interrupt source register (DP1REQ) [address 002B16
]
0
0 0
At reset
R W
H/W S/W
Bit symbol
Bit name
Function
Downstream port 1 disconnect
detection interrupt bit
PTDIS1
0
–
0: No interrupt request issued
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-disconnect
state (2.5 µs or more of SE0) on a downstream port 1 in
DSCONN1 = “1”.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 1 connect
detection interrupt bit
PTCON1
0
–
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-connect
state (2.5 µs or more of J- or K- state) on a downstream
port 1 in DSCONN1 = “0”.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 1 port error
interrupt bit
PTERR1
PTRSM1
0
0
–
–
O O
O O
1: Interrupt request issued
This bit is set to “1” when an error occurs on a
downstream port 1.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 1 resume
interrupt bit
1: Interrupt request issued
This bit is set to “1” when detecting a resume signal
on a downstream port 1 in the condition of HUB
suspended or port suspended state.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 1 bus-change
detection interrupt bit
PTCHG1
0
–
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-change of a
downstream port 1 in the condition of HUB suspended
state. It is also “1” in the internal clock halted.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
Not used
b7:b5
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.59 Structure of DP1 interrupt source register
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
DP2 interrupt source register (DP2REQ) [address 002B16
]
0
0 0
At reset
R W
H/W S/W
Bit symbol
Bit name
Function
Downstream port 2 disconnect
detection interrupt bit
PTDIS2
0
–
0: No interrupt request issued
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-disconnect
state (2.5 µs or more of SE0) on a downstream port 2 in
DSCONN2 = “1”.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 2 connect
detection interrupt bit
PTCON2
0
–
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-connect
state (2.5 µs or more of J- or K- state) on a downstream
port 2 in DSCONN2 = “0”.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 2 port error
interrupt bit
PTERR2
PTRSM2
0
0
–
–
O O
O O
1: Interrupt request issued
This bit is set to “1” when an error occurs on a
downstream port 2.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 2 resume
interrupt bit
1: Interrupt request issued
This bit is set to “1” when detecting a resume signal
on a downstream port 2 in the condition of HUB
suspended or port suspended state.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
Downstream port 2 bus-change
detection interrupt bit
PTCHG2
0
–
–
O O
1: Interrupt request issued
This bit is set to “1” when detecting a bus-change of a
downstream port 2 in the condition of HUB suspended
state. It is also “1” in the internal clock halted.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
Not used
b7:b5
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.60 Structure of DP2 interrupt source register
Rev.2.00 Oct 15, 2006 page 63 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
b0
b7
DP1 control register (DP1CON) [address 002C16]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
–
Downstream port 1 connect bit
Downstream port 1 enable bit
0
O O
O O
0 : Disconnect ; PTCON1 interrupt enabled
1 : Connect ; PTDIS1 interrupt enabled
0 : Downstream port 1 disabled
DSCONN1
DSPTEN1
–
0
1 : Downstream port 1 enabled ; This bit is cleared when
an interrupt of PTDIS1 or PTERR1 is generated.
0 : No port suspended
–
–
Downstream port 1 suspend bit
0
0
O O
O O
DSSUSP1
DSDETE1
1 : Port suspended; This bit is cleared when an interrupt
of PTDIS1 or PTRSM1 is generated.
0 : Connect/disconnect-state detection disabled ; PTCON1
and PTDIS1 interrupts disabled
Downstream port 1 connect-
state detection enable bit
1 : Connect/disconnect-state detection enabled ; This bit
is cleared when an interrupt of PTCON1, PTDIS1 or
PTERR1 is generated.
–
–
Downstream port 1 SE0 signal
transmit bit
0
0
O O
O O
0 : Being not output
DSRSTO1
DSRSMO1
1 : SE0 signal being output
Downstream port 1 resume
signal transmit bit
0 : Being not output
1 : K-signal being output ; When writing “0”, a low-speed
EOP is output and then a transition to being not
output occurs.
–
–
Downstream port 1 bus-state
read mode control bit
0
0
O O
O O
0 : Mode where a downstream port 1 bus-state is read,
using RD signal
DSRMOD1
DSLSPD1
1 : Mode where a downstream port 1 bus-state is read,
using EOF2 signal (internal signal)
0 : Full-speed mode (12MHz)
Downstream port 1 USB transfer
1 : Low-speed mode (1.5 MHz)
–: State remaining
Fig. 3.4.61 Structure of DP1 control register
b0
b7
DP2 control register (DP2CON) [address 002C16
]
At reset
R W
Bit symbol
DSCONN2
Function
Bit name
H/W S/W
–
Downstream port 2 connect bit
0
O O
O O
0 : Disconnect ; PTCON2 interrupt enabled
1 : Connect ; PTDIS2 interrupt enabled
0 : Downstream port 2 disabled
–
Downstream port 2 enable bit
Downstream port 2 suspend bit
0
DSPTEN2
DSSUSP2
DSDETE2
1 : Downstream port 2 enabled ; This bit is cleared when
an interrupt of PTDIS2 or PTERR2 is generated.
0 : No port suspended
–
–
0
0
O O
O O
1 : Port suspended; This bit is cleared when an interrupt
of PTDIS2 or PTRSM2 is generated.
0 : Connect-state detection disabled ; PTCON2 and PTDIS2
interrupts disabled
Downstream port 2 connect-
state detection enable bit
1 : Connect-state detection enabled ; This bit is cleared when an
interrupt of PTCON2, PTDIS2 or PTERR2 is generated.
0 : Being not output
–
–
Downstream port 2 SE0 signal
transmit bit
0
0
O O
O O
DSRSTO2
DSRSMO2
1 : SE0 signal being output
Downstream port 2 resume
signal transmit bit
0 : Being not output
1 : K-signal being output ; When writing “0”, a low-speed
EOP is output and then a transition to being not
output occurs.
–
–
Downstream port 2 bus-state
read mode control bit
0
0
O O
O O
0 : Mode where a downstream port 2 bus-state is read,
using RD signal
DSRMOD2
DSLSPD2
1 : Mode where a downstream port 2 bus-state is read,
using EOF2 signal (internal signal)
0 : Full-speed mode (12MHz)
Downstream port 2 USB transfer
speed select bit
1 : Low-speed mode (1.5 MHz)
–: State remaining
Fig. 3.4.62 Structure of DP2 control register
Rev.2.00 Oct 15, 2006 page 64 of 99
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
DP1 status register (DP1STS) [address 002D16
]
0
0
0
0
0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
In-
In-
D1MINUS
D1PLUS
b7:b2
O ꢀ
O ꢀ
O O
D1- signal bit
D1+ signal bit
Not used
In DSRMOD1 = “0”, a downstream port 1 bus-state is
read, using RD signal.
definite definite
In DSRMOD1 = “1”, a downstream port 1 bus-state is
read, using EOF2 signal (internal signal).
In DSRMOD1 = “0”, a downstream port 1 bus-state is
read, using RD signal.
In-
In-
definite definite
In DSRMOD1 = “1”, a downstream port 1 bus-state is
read, using EOF2 signal (internal signal).
Write “0” when writing.
–
–
“0” is read when reading.
–: State remaining
Fig. 3.4.63 Structure of DP1 status register
b0
b7
0
DP2 status register (DP2STS) [address 002D16
]
0
0
0
0 0
At reset
R W
Bit symbol
D2MINUS
Function
Bit name
D2- signal bit
H/W S/W
In-
In-
O ꢀ
O ꢀ
O O
In DSRMOD2 = “0”, a downstream port 2 bus-state is
read, using RD signal.
definite definite
In DSRMOD2 = “1”, a downstream port 2 bus-state is
read, using EOF2 signal (internal signal).
In DSRMOD2 = “0”, a downstream port 2 bus-state is
read, using RD signal.
In-
In-
D2PLUS
b7:b2
D2+ signal bit
Not used
definite definite
In DSRMOD2 = “1”, a downstream port 2 bus-state is
read, using EOF2 signal (internal signal).
Write “0” when writing.
–
–
“0” is read when reading.
–: State remaining
Fig. 3.4.64 Structure of DP2 status register
b0
b7
0
EXB interrupt source enable register (EXBICON) [address 003016
]
0
0
0
0
(Note)
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
RXB_ENB CPU channel receive enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Receive buffer full interrupt enabled)
0
0
0
–
–
–
O O
O O
O O
TXB_ENB
CPU channel transmit enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Transmit buffer empty interrupt enabled)
MC_ENB
Memory channel operation
enable bit
0 : Operation disabled (Memory channel operation end
interrupt disabled)
1 : Operation enabled (Memory channel operation end
interrupt disabled)
b7:b3
Not used
Write “0” when writing.
–
–
O O
“0” is read when reading.
–: State remaining
Note: Do not set each bit simultaneously.
Fig. 3.4.65 Structure of EXB interrupt source enable register
Rev.2.00 Oct 15, 2006 page 65 of 99
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
0
0
0
0
EXB interrupt source register (EXBIREQ) [address 003116] (Note 1)
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
0 : Receive buffer empty
1 : Receive buffer full
0 : Transmit buffer full
1 : Transmit buffer empty
b3b2
RXB_FULL Receive buffer full bit
0
0
0
0
(Note 3)
0
O –
O –
O –
TXB_EMPTY Transmit buffer empty bit
(Note 4)
MC_STS
[1:0]
Memory channel status bits
0
0 0 : Memory channel operation stopped
0 1 : Memory channel being operating;
No external access
(Note 2)
1 0 : Memory channel being operating;
External accessing
1 1 : Memory channel operation end; Memory
channel operation end interrupt generated
Write “0” when writing.
b7:b4
Not used
–
–
O O
“0” is read when reading.
–: State remaining
Notes 1: When the the ExA1 pin control bit of external I/O configuration register is “1”, the external MCU bus can read this
register contents by setting the ExA1 pin to “H”.
2: The memory channel status bits indicate the status of memory channel. In MC_ENB = “0” these bits are always
“00
2”. When the memory channel operation ends, these bits are set to “112” and the memory channel operation
end interrupt is generated.
These bits can be read out during operation, so that it will show that whether the external MCU bus is accessing
or not.
3: This bit is cleared to “0” when reading the transmit/receive buffer register in the CPU channel receive enable bit =
“1” or when the CPU channel receive enable bit is “0”.
4: This bit is cleared to “0” when writing to the transmit/receive buffer register in the CPU channel transmit enable bit
= “1” or when the CPU channel transmit enable bit is “0”.
Fig. 3.4.66 Structure of EXB interrupt source register
b0
b7
0
EXB index register (EXBINDEX) [address 003316
]
0
0
0 0
At reset
H/W S/W
R W
O O
Bit symbol
Bit name
Function
INDEX
[2:0]
The accessible register, using the register window,
depends on these index bits contents as follows:
b2b1b0
0
–
Index bits
0 0 0 : External I/O configuration register
0 0 1 : Transmit/Receive buffer register
0 1 0 : Memory channel operation mode register
0 1 1 : Memory address counter
1 0 0 : End address register
1 0 1 : Do not set.
1 1 0 : Do not set.
1 1 1 : Do not set.
b7:b3
Write “0” when writing.
–
–
Not used
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.67 Structure of EXB index register
Rev.2.00 Oct 15, 2006 page 66 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
b0
b7
Register window 1 (EXBREG1) [address 003416
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
LOW_WIN
[7:0]
The accessible register, using this register window, In-
In-
–
O O
depends on the EXB index register contents as definite definite
follows:
Index value
“0016
“0116
“0216
“0316
“0416
”
”
”
”
”
: External I/O configuration register
: Transmit/Receive buffer register
: Memory channel operation mode register
: Memory address counter
: End address register
Fig. 3.4.68 Structure of Register window 1
b0
b7
0
Index = 0016 : External I/O configuration register (EXBCFGL) [address 003416
]
0
0
At reset
H/W S/W
R W
Bit symbol
EXB_CTR
Function
Bit name
0 : Port
EXB pin control bit
0
0
–
–
O O
O O
1 : EXB function pin
Selects a signal of P3
(Pins P1
0 to P17, P30 to P34)
3
/ExINT pin.
INT_CTR
[2:0]
P3 /ExINT pin control bit
3
ON/OFF is programmed by each bit. An output logical
sum of P3 /ExINT pins set for ON are performed and it
3
is output as an “L” active signal.
b3b2b1
0 0 1 : RxB_RDY (RxBuf ready) output
0 1 0 : TxB_RDY (TxBuf ready) output
1 0 0 : Mch_req (Memory channel request) output
Others : Do not set.
0 : Port
A1_CTR
b7:b5
P4
3/ExA1 pin control bit
0
–
–
O O
O O
1 : A1 input (used to read status)
Write “0” when writing.
Not used
–
“0” is read when reading.
–: State remaining
Fig. 3.4.69 Index00[low]; Structure of External I/O configuration register
Rev.2.00 Oct 15, 2006 page 67 of 99
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
Index =0116 : Transmit/Receive buffer register (RXBUF/TXBUF) [address 003416
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
RXBUF/
TXBUF
–
0
–
O O
The data received from an external bus is written here
at the rise timing of external write signal.
The data transmitted to an external bus is written here
at the timing of internal CPU write or memory write.
The receive buffer register (RXBUF) contents can be read out by reading to this address with the CPU. The data which the
CPU has written to this address is stored in the transmit buffer register (TXBUF).
However, do not perform write operation with the CPU to this address if the memory channel direction control bits of
memory channel operation mode register is “10
2” (transmit mode) and the memory channel status bits of EXB interrupt
source register are “01 ” or “10 ” (memory channel being operating).
2
2
Fig. 3.4.70 Index01[low]; Structure of Transmit/Receive buffer register
b0
b7
0
Index =0216 : Memory channel operation mode register (MCHMOD) [address 003416
]
0
0
0
0
At reset
H/W S/W
R W
O O
Bit symbol
Function
Bit name
MC_DIR
[1:0]
Memory channel direction
control bit
b1b0
0
–
0 0 : Operation disabled
0 1 : Receive mode
1 0 : Transmit mode
1 1 : Do not set.
BURST
b7:b3
Burst bit
Not used
0 : Cycle mode (each byte transfer according to
assertion or negation)
0
–
–
O O
O O
1 : Burst mode (continuous transfer till the terminal
count)
Write “0” when writing.
–
“0” is read when reading.
–: State remaining
Fig. 3.4.71 Index02[low]; Structure of Memory channel operation mode register
b0
b7
Index = 0316 : Memory address counter (MEMADL) [address 003416
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
IM_A
[7:0]
Register to set the low-order address of memory
channel operation beginning.
0
–
–
This contents are increased each time one memory
access ends.
Fig. 3.4.72 Index03[low]; Structure of Memory address counter
Rev.2.00 Oct 15, 2006 page 68 of 99
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APPENDIX
38K2 Group
3.4 List of registers
b0
b7
Index = 0416 : End address register (ENDADL) [address 003416
]
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
END_A
[7:0]
Register to set the low-order address of memory
channel operation end.
0
–
–
–: State remaining
Fig. 3.4.73 Index04[low]; Structure of End address register
b0
b7
Register window 2 (EXBREG2) [address 003516
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
HIGH_WIN
[7:0]
The accessible register, using this register window, In-
In-
–
O O
depends on the EXB index register contents as definite definite
follows:
Index value
“0016
“0116
“0216
“0316
“0416
”
”
”
”
”
: External I/O configuration register
: Transmit/Receive buffer register
: Memory channel operation mode register
: Memory address counter
: End address register
Fig. 3.4.74 Structure of Register window 2
b0
b7
0
Index = 0016 : External I/O configuration register (EXBCFGH) [address 003516
]
0
0
At reset
H/W S/W
R W
O O
Bit symbol
Function
Bit name
b1b0
DRQ_CTR P4
0
/ExDREQ/RxD pin control
0
–
bit
0 0 : Port
0 1 : Do not set.
[1:0]
1 0 : ExDREQ function; RxB_RDY (RxBuf ready) output
1 1 : ExDREQ function; Mch_req (Memory channel
request) output
Specifies P41/ExDACK/TxD pin function.
DAK_CTR
[1:0]
P4
1/ExDACK/TxD pin control
0
–
O O
Selects which mode; requiring read or write signal, or
not requiring it for use of DMA acknowledge function.
bit
b3b2
0 0 : Port
0 1 : Do not set.
1 0 : ExDACK function; DMA acknowledge input
(Mode for read and write signals used together)
1 1 :ExDACK function; DMA acknowledge input
(Mode for read and write signals not required)
0 : Port
TC_CTR
b7:b5
P4
2
/ExTC/SCLK pin control bit
0
–
–
O O
O O
1 : ExTC (terminal count) input
Write “0” when writing.
Not used
–
“0” is read when reading.
–: State remaining
Fig. 3.4.75 Index00[high]; Structure of External I/O configuration register
Rev.2.00 Oct 15, 2006 page 69 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
b0
b7
Index = 0316 : Memory address counter (MEMADH) [address 003516]
0
0
0
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
IM_A
[10:8]
Register to set the high-order address of memory
channel operation start.
0
–
–
This contents are increased each time one memory
access ends.
O O
b7:b3
Write “0” when writing.
–
–
Not used
“0” is read when reading.
–: State remaining
Fig. 3.4.76 Index03[high]; Structure of Memory address counter
b0
b7
0
Index = 0416 : End address register (ENDADH) [address 003516
]
0
0
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
O O
O O
END_A
[10:8]
Register to set the high-order address of memory
channel operation end.
0
–
–
b7:b3
Write “0” when writing.
–
–
Not used
“0” is read when reading.
–: State remaining
Fig. 3.4.77 Index04[high]; Structure of End address register
AD control register
b7 b6 b5 b4 b3 b2 b1 b0
AD control register (ADCON) [Address : 3616
]
B
0
Name
R W
Function
At reset
b2 b1 b0
0
Analog input pin selection bits
0 0 0 : P1
0 0 1 : P1
0 1 0 : P1
0 1 1 : P1
1 0 0 : P1
1 0 1 : P1
1 1 0 : P1
1 1 1 : P1
0
1
2
3
4
5
6
7
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
/DQ
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
1
2
0 : Conversion in progress
1 : Conversion completed
AD conversion completion bit
1
?
?
?
?
3
4
5
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are indefinite.
6
7
Fig. 3.4.78 Structure of AD control register
Rev.2.00 Oct 15, 2006 page 70 of 99
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APPENDIX
38K2 Group
3.4 List of registers
AD conversion register 1
b7 b6 b5 b4 b3 b2 b1 b0
AD conversion register 1 (AD1) [Address : 3716]
B
At reset
R W
Function
0
?
ꢀ
The read-only register in which the A/D conversion’s results are
stored.
1
ꢀ
?
?
?
?
?
< 8-bit read>
2
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
b7
b0
b9 b8 b7 b6 b5 b4 b3 b2
3
4
< 10-bit read>
b7
b0
5
6
7
b7 b6 b5 b4 b3 b2 b1 b0
?
?
Fig. 3.4.79 Structure of AD conversion register 1
AD conversion register 2
b7 b6
b4 b3 b2 b1 b0
b5
AD conversion register 2 (AD2) [Address : 38
]
16
0
B
0
At reset
Name
R W
Function
?
ꢀ
The read-only register in which the A/D conversion’s results are
stored.
< 10-bit read>
b7
0
b0
ꢀ
?
1
b9 b8
ꢀ
0
0
0
2
3
4
5
6
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the contents are “0”.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
Fix this bit to “0”.
7
Fig. 3.4.80 Structure of AD conversion register 2
Rev.2.00 Oct 15, 2006 page 71 of 99
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APPENDIX
38K2 Group
3.4 List of registers
Watchdog timer control register
b5
b7 b6
b4 b3 b2
b0
b1
Watchdog timer control register (WDTCON) [Address : 3916
]
Function
At reset
B
0
Name
R W
ꢀ
1
1
1
1
1
1
0
0
Watchdog timer H (for read-out of high-order 6 bits)
1
2
ꢀ
ꢀ
ꢀ
3
4
ꢀ
ꢀ
5
6
7
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count
source selection bit
0 : Watchdog timer L underflow
1 : System clock/16
Fig. 3.4.81 Structure of Watchdog timer control register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
0
1
(CPUM: address 3B16
)
W
At reset
0
R
B
Function
Name
b1 b0
0
Processor mode bits
0 0 : Single-chip mode
0 1 : Not available
1 0 : Not available
1 1 : Not available
1
2
3
*
0 : 0 page
1 : 1 page
0
Stack page selection bit
Fix this bit to “1”.
1
0
0
4
Fix this bit to “0”.
5
6
0 : Main clock f(XIN)
System clock selection bit
1 : fSYN
b7 b6
System clock division ratio
selection bits
0
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
7
*
: The initial value of bit 1 depends on the CNVss level.
Fig. 3.4.82 Structure of CPU mode register
Rev.2.00 Oct 15, 2006 page 72 of 99
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APPENDIX
38K2 Group
3.4 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1)
[Address : 3C16
]
At reset R W
Name
USB bus reset
interrupt request bit
B
0
Function
0 : No interrupt request issued
1 : Interrupt request issued
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
USB SOF interrupt
request bit
1
2
0 : No interrupt request issued
1 : Interrupt request issued
USB device interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
EXB interrupt
request bit
3
4
5
0
0
0
INT
0
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
Timer X interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
7
0
0
Timer 2 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
ꢀꢀ “0” can be set by software, but “1” cannot be set.
Fig. 3.4.83 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2)
[Address : 3D16
]
At reset R W
Name
interrupt
request bit
B
0
Function
0 : No interrupt request issued
1 : Interrupt request issued
INT
1
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0 : No interrupt request issued
1 : Interrupt request issued
USB HUB interrupt
request bit
1
2
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O receive
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
Serial I/O transmit
interrupt request bit
3
4
5
0
0
0
CNTR
0
interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Key-on wake-up
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
A/D conversion
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
7
0
0
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
ꢀꢀ “0” can be set by software, but “1” cannot be set.
Fig. 3.4.84 Structure of Interrupt request register 2
Rev.2.00 Oct 15, 2006 page 73 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1)
[Address : 3E16]
At reset R W
Name
USB bus reset
interrupt enable bit
Function
B
0
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
USB SOF interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1
2
USB device interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
EXB interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
3
4
5
0
0
0
INT0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6
7
0
0
Timer 2 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 3.4.85 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2)
[Address : 3F16
0
]
At reset R W
Name
interrupt
enable bit
B
0
Function
0 : Interrupt disabled
1 : Interrupt enabled
INT
1
0
USB HUB interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1
2
0
0
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O receive
interrupt enable bit
Serial I/O transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
3
4
5
0
0
0
0
0
CNTR0 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Key-on wake-up
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
A/D conversion
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
6
7
Fix this bit to “0”.
Fig. 3.4.86 Structure of Interrupt control register 2
Rev.2.00 Oct 15, 2006 page 74 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
Serial I/O control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address : 0FE016
]
At reset
Name
B
0
Function
R W
BRG count source
selection bit (CSS)
Serial I/O synchronous
clock selection bit (SCS)
0 : System clock
1 : System clock/4
0
0
1
• In clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
• In UART
0 : BRG output divided by 16
1 : External clock input divided by 16
0 : P4
1 : P4
3
3
pin operates as ordinary I/O pin
pin operates as SRDY output pin
2
3
0
0
S
RDY output enable bit
(SRDY)
Transmit interrupt
source selection bit (TIC)
0 : Interrupt when transmit buffer has emptied
1 : Interrupt when transmit shift operation is
completed
0
0
0
Transmit enable bit (TE)
Receive enable bit (RE)
0 : Transmit disabled
1 : Transmit enabled
4
0 : Receive disabled
1 : Receive enabled
5
6
Serial I/O mode selection bit
(SIOM)
0 : Clock asynchronous(UART) serial I/O
1 : Clock synchronous serial I/O
Serial I/O enable bit
(SIOE)
0 : Serial I/O disabled
0
7
(pins P4
1 : Serial I/O enabled
(pins P4 to P4 operate as serial I/O pins)
0 to P43 operate as ordinary I/O pins)
0
3
Fig. 3.4.87 Structure of Serial I/O control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 0FE116
]
At reset
Name
R W
Function
B
0
Character length selection bit
(CHAS)
0 : 8 bits
1 : 7 bits
0
0
0
Parity enable bit
(PARE)
0 : Parity checking disabled
1 : Parity checking enabled
1
2
Parity selection bit
(PARS)
0 : Even parity
1 : Odd parity
Stop bit length selection bit
(STPS)
0 : 1 stop bit
1 : 2 stop bits
3
4
0
Nothing is allocated for this bit. This is a write disabled bit.
0
ꢀ
When this bit is read out, the contents are “0”.
5
6
7
1
1
1
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the contents are “1”.
ꢀ
ꢀ
ꢀ
Fig. 3.4.88 Structure of UART control register
Rev.2.00 Oct 15, 2006 page 75 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 0FE216
]
At reset
Function
B
0
R W
Set a count value of baud rate generator.
?
?
?
1
2
3
4
?
?
?
5
6
7
?
?
Fig. 3.4.89 Structure of Baud rate generator
b0
b7
0
EP01 MAX. packet size register (EP01MAX) [address 0FEC16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
0
–
MXPS01
[6:0]
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
Max. packet size bit
Not used
O O
O O
–
–
b7
“0” is read when reading.
–: State remaining
Fig. 3.4.90 Structure of EP01 MAX. packet size register
b0
b7
0
EP02 MAX. packet size register (EP02MAX) [address 0FEC16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
0
–
MXPS02
[6:0]
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
Max. packet size bit
Not used
O O
O O
–
–
b7
“0” is read when reading.
–: State remaining
Fig. 3.4.91 Structure of EP02 MAX. packet size register
Rev.2.00 Oct 15, 2006 page 76 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
b0
b7
0
EP03 MAX. packet size register (EP03MAX) [address 0FEC16
]
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
0
–
MXPS03
[6:0]
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
Max. packet size bit
Not used
O O
O O
–
–
b7
“0” is read when reading.
–: State remaining
Fig. 3.4.92 Structure of EP03 MAX. packet size register
b0
b7
0
EP00 buffer area set register (EP00BUF) [address 0FED16
]
0
0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BADD00
[4:0]
EP00 beginning address set bit Set the beginning address of EP00’s buffer area.
0
–
O O
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 3.4.93 Structure of EP00 buffer area set register
b0
b7
0
EP01 buffer area set register (EP01BUF) [address 0FED16
]
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
BADD01
[4:0]
EP01 beginning address set bit Set the beginning address of EP01’s buffer area.
0
–
O O
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
b7:b5
Not used
Write “0” when writing.
–
–
O O
“0” is read when reading.
–: State remaining
Fig. 3.4.94 Structure of EP01 buffer area set register
Rev.2.00 Oct 15, 2006 page 77 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP02 buffer area set register (EP02BUF) [address 0FED16
]
0
0
0
At reset
R W
H/W S/W
Bit symbol
Bit name
Function
BADD02
[4:0]
EP02 beginning address set bit
Set the beginning address of EP02’s buffer area.
(32-byte unit)
0
–
O O
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 3.4.95 Structure of EP02 buffer area set register
b0
b7
0
EP03 buffer area set register (EP03BUF) [address 0FED16
]
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
BADD03
[4:0]
EP03 beginning address set bit
Set the beginning address of EP03’s buffer area.
(32-byte unit)
0
–
O O
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 3.4.96 Structure of EP03 buffer area set register
b0
b7
0
EP10 buffer area set register (EP10BUF) [address 0FED16
]
0
0
At reset
R W
Bit symbol
Function
Bit name
H/W S/W
BADD10
[4:0]
EP10 beginning address set bit
Set the beginning address of EP10’s buffer area.
(32-byte unit)
0
–
O O
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 3.4.97 Structure of EP10 buffer area set register
Rev.2.00 Oct 15, 2006 page 78 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
b0
b7
EP11 buffer area set register (EP11BUF) [address 0FED16
]
0
0 0
At reset
R W
Bit symbol
Bit name
Function
H/W S/W
BADD11
[4:0]
EP11 beginning address set bit Set the beginning address of EP11’s buffer area.
0
–
O O
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
b7:b5
Not used
–
–
O O
–: State remaining
Fig. 3.4.98 Structure of EP11 buffer area set register
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 pull-up control register (PULL0)
[Address : 0FF016
]
At reset R W
Name
B
0
Function
0 : No pull-up
1 : Pull-up
0
P00
pul l-up control bit
0 : No pull-up
1 : Pull-up
1
2
0
0
P0
0
0
pul l-up control bit
pul l-up control bit
0 : No pull-up
1 : Pull-up
P0
0 : No pull-up
1 : Pull-up
3
4
5
0
0
0
P0
0
pul l-up control bit
pul l-up control bit
0 : No pull-up
1 : Pull-up
P0
0
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
P0
0
0
pul l-up control bit
pul l-up control bit
pul l-up control bit
6
7
0
0
P0
0 : No pull-up
1 : Pull-up
P0
0
Fig. 3.4.99 Structure of Port P0 pull-up control register
Rev.2.00 Oct 15, 2006 page 79 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
Port P5 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P5 pull-up control register (PULL5)
[Address : 0FF216
]
At reset
R
Function
0 : No pull-up
1 : Pull-up
W
Name
B
0
P50
pul l-up control bit
0
Nothing is arranged for this bit. This is a write disabled bit.
When this bit is read out, the contents are “0”.
1
2
0
0
0 : No pull-up
1 : Pull-up
P52 pul l-up control bit
Nothing is arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0”.
3
4
5
0
0
0
6
7
0
0
Fig. 3.4.100 Structure of Port P5 pull-up control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE)
[Address : 0FF316]
Function
0 : Falling edge active
1 : Rising edge active
At reset R W
Name
INT0 interrupt edge
selection bit
B
0
0
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
1
2
0
0
INT1 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are “0”.
3
4
5
0
0
0
6
7
0
0
Fig. 3.4.101 Structure of Interrupt edge selection register
Rev.2.00 Oct 15, 2006 page 80 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
PLL control register
b7 b6 b5 b4 b3 b2 b1 b0
PLL control register (PLLCON)
[Address : 0FF816
]
At reset R W
Name
B
0
1
2
Function
Nothing is arranged for these bit. These are write disabled bits.
When these bits are read out, the contents are “0”.
0
b4 b3
3
USB clock division
0
0 0 : Divided by 8 (fSYN = fUSB/8)
ratio selection bits
0 1 : Divided by 6 (fSYN = fUSB/6)
4
1 0 : Divided by 4 (fSYN = fUSB/4)
1 1 : Not selected
b6 b5
5
6
PLL operation mode
0
0
0 0 : Not multiplied (fVCO = fXIN
0 1 : Double (fVCO = fXIN ꢀ 2)
1 0 : Quadruple (fVCO = fXIN ꢀ 4)
1 1 : Multiplied by 8 (fVCO = fXIN ꢀ 8)
)
selection bits
7
PLL enable bit
0 : Disabled
1 : Enabled
Fig. 3.4.102 Structure of PLL control register
b0
b7
0
Downstream port control register (DPCTL) [address 0FF916
]
0
0 0
At reset
H/W S/W
Bit symbol
R W
O O
Function
Bit name
PCON1
[1:0]
Downstream port 1 function
select bit
b1b0
–
–
–
0
0
–
0 0 : USB port (D1-, D1+) OFF,
USB difference amplifier OFF
0 1 : USB exclusive input port (D1-, D1+),
USB difference amplifier OFF
1 0 : Full-speed port (D1-, D1+),
USB difference amplifier ON
1 1 : Low-speed port (D1-, D1+),
USB difference amplifier ON
b3b2
PCON2
[1:0]
Downstream port 2 function
select bit
O O
0 0 : USB port (D2-, D2+) OFF,
USB difference amplifier OFF
0 1 : USB exclusive input port (D2-, D2+),
USB difference amplifier OFF
1 0 : Full-speed port (D2-, D2+),
USB difference amplifier ON
1 1 : Low-speed port (D2-, D2+),
USB difference amplifier ON
Write “0” when writing.
b7:b4
Not used
O O
–: State remaining
“0” is read when reading.
Fig. 3.4.103 Structure of Downstream port control register
Rev.2.00 Oct 15, 2006 page 81 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.4 List of registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG
(MISRG: address 0FFB16
)
W
At reset
0
R
B
Functions
Name
0
0 : Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1 : Automatically set nothing
Oscillation stabilizing time
set after STP instruction
released bit
1
2
3
4
5
6
7
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are indefinite.
?
Fig. 3.4.104 Structure of MISRG
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register
(FMCR : address 0FFE16) (Note 1)
b
Name
Functions
At reset R W
1
0 : Busy (being written or
erased)
0 RY/BY status flag
1 : Ready
0
1
CPU rewrite mode 0 : Normal mode (Software
select bit (Note 2)
commands invalid)
1 : CPU rewrite mode
(Software commands
acceptable)
2
CPU rewrite mode
entry flag
0: Normal mode
1: CPU rewrite mode
0
Flash memory reset
bit (Note 3)
User area/Boot area
selection bit (Note 4)
3
4
0: Normal operation
1: Reset
0: User ROM area
1: Boot ROM area
0
0
5
6
7
Nothing is arranged for these bits. If writing,
set “0”. When these bits are read out,
the contents are undefined.
Undefined
Undefined
Undefined
Notes 1: The contents of flash memory control register are “XXX00001” just
after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1”
to it in succession. If it is not this procedure, this bit will not be set to
“1”. Additionally, it is required to ensure that no interrupt will be
generated during that interval.
Use the control program in the area except the built-in flash memory
for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”.
Set this bit 3 to “0” subsequently after setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory
for write to this bit.
Fig. 3.4.105 Structure of Flash memory control register
Rev.2.00 Oct 15, 2006 page 82 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.5 Package outline
3.5 Package outline
PLQP0064GA-A
JEITA Package Code
RENESAS Code
Previous Code
64P6U-A
MASS[Typ.]
0.7g
P-LQFP64-14x14-0.80
PLQP0064GA-A
HD
*1
D
33
48
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
49
32
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
Terminal cross section
D
E
13.9 14.0 14.1
13.9 14.0 14.1
1.4
A2
HD
HE
A
15.8 16.0 16.2
15.8 16.0 16.2
1.7
64
17
A1
bp
b1
c
0.1 0.2
0
1
16
ZD
0.32 0.37 0.42
0.35
Index mark
F
0.145
0.125
0.09
0.20
c1
L
L1
0°
8°
e
x
0.8
y
Detail F
0.20
0.10
*3
e
bp
y
x
ZD
ZE
L
1.0
1.0
0.3 0.5 0.7
1.0
L1
Rev.2.00 Oct 15, 2006 page 83 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.5 Package outline
PLQP0064KB-A
JEITA Package Code
RENESAS Code
PLQP0064KB-A
Previous Code
MASS[Typ.]
0.3g
P-LQFP64-10x10-0.50
64P6Q-A / FP-64K / FP-64KV
HD
D
*1
48
33
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
49
32
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
10.0 10.1
10.0 10.1
1.4
9.9
9.9
64
17
Terminal cross section
A2
HD
HE
A
11.8 12.0 12.2
11.8 12.0 12.2
1.7
1
16
Index mark
ZD
A1
bp
b1
c
0.05
0.15
0.1
0.15 0.20 0.25
0.18
F
0.09
0.20
0.145
0.125
c1
0°
8°
y
e
0.5
*3
L
bp
e
x
0.08
0.08
x
L1
y
Detail F
ZD
ZE
L
1.25
1.25
0.5
0.35
0.65
L1
1.0
Rev.2.00 Oct 15, 2006 page 84 of 99
REJ09B0338-0200
THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
APPENDIX
APPENDIX
38K2 Group
3.6 Machine instructions
38K2 Group
3.6 Machine instructions
3.6 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
OP
69
A
n
BIT,A, R
ZP
n
BIT,ZP, R
ZP, X
ZP, Y
OP
ABS
ABS, X
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
#
n
# OP
2
#
OP
n
# OP
65
#
2
OP
n
#
OP
75
n
4
#
2
n
#
OP
6D
n
4
#
3
OP
7D
n
5
#
OP
79
n
5
#
3
OP
#
n
#
OP
61
n
6
#
OP
71
n
6
#
OP
#
OP
#
N
N
V
V
ADC
(Note 1)
(Note 5)
When T = 0
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A re-
main unchanged, but the contents of status
flags are changed.
2
3
3
2
2
•
←
A
A + M + C
When T = 1
←
M(X)
M(X) + M + C
M(X) represents the contents of memory
where is indicated by X.
AND
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the con-
tents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1 the contents of A re-
main unchanged, but status flags are
changed.
29
2
2
25
3
2
35
4
2
2D
4
3
3D
5
3
39
5
3
21
6
2
31
6
2
N
•
•
•
•
•
Z
•
V
←
A
A
M
When T = 1
V
←
M(X)
M(X)
M
M(X) represents the contents of memory
where is indicated by X.
7
0
ASL
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A
2
1
06
5
2
16
6
2
0E
6
3
1E
7
3
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
C
•
←
←
0
C
BBC
(Note 4)
Ai or Mi = 0?
Ai or Mi = 1?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative ad-
dress. If the bit is 1, next instruction is
executed.
13
+
4
2
17
+
5
5
3
3
20i
20i
BBS
(Note 4)
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative ad-
dress. If the bit is 0, next instruction is
executed.
03
+
4
2
07
+
•
•
•
•
•
•
•
•
20i
20i
C = 0?
C = 1?
BCC
(Note 4)
This instruction takes a branch to the ap-
pointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
2
2
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90
B0
F0
BCS
(Note 4)
This instruction takes a branch to the ap-
pointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
Z = 1?
BEQ
(Note 4)
This instruction takes a branch to the ap-
pointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
•
V
A
M
BIT
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
24
3
2
M7 M6
Z
2C
4
3
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
N = 1?
Z = 0?
30
2
2
2
2
BMI
(Note 4)
This instruction takes a branch to the ap-
pointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D0
BNE
(Note 4)
This instruction takes a branch to the ap-
pointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
Rev.2.00 Oct 15, 2006 page 86 of 99
REJ09B0338-0200
Rev.2.00 Oct 15, 2006 page 87 of 99
REJ09B0338-0200
APPENDIX
APPENDIX
38K2 Group
3.6 Machine instructions
38K2 Group
3.6 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n
ZP, X
ZP, Y
OP
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
#
n
# OP
#
n
# OP
#
#
OP
n
#
n
#
OP
#
OP
n
#
OP
#
n
#
#
#
OP
10
#
2
OP
#
N
•
V
•
T
•
B
•
D
•
I
Z
•
C
•
BPL
(Note 4)
N = 0?
This instruction takes a branch to the ap-
pointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
2
•
←
80
BRA
BRK
PC
PC ± offset
This instruction branches to the appointed ad-
dress. The branch address is specified by a
relative address.
4
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
←
B
1
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
1
1
00
7
1
←
←
(PC)
M(S)
(PC) + 2
PCH
←
S
S – 1
←
M(S)
PCL
←
S
S – 1
←
PS
S – 1
M(S)
←
S
←
I
1
←
←
PCL
PCH
ADL
ADH
50
70
2
2
2
2
BVC
(Note 4)
V = 0?
V = 1?
Ai or Mi
This instruction takes a branch to the ap-
pointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
BVS
(Note 4)
This instruction takes a branch to the ap-
pointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
1B
+
2
1
1F
+
5
2
←
CLB
CLC
CLD
CLI
0
This instruction clears the designated bit i of A
or M.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
20i
20i
18
D8
58
12
B8
2
2
2
2
2
1
1
1
1
1
←
←
C
D
0
0
This instruction clears C.
This instruction clears D.
This instruction clears I.
This instruction clears T.
This instruction clears V.
•
•
•
0
•
•
•
←
I
0
•
•
•
0
•
•
•
←
←
CLT
CLV
T
V
0
0
•
•
0
•
•
•
•
•
0
•
•
•
•
•
C9
2
2
C5
3
2
D5
4
2
CD
4
3
DD
5
3
D9
5
3
C1
6
2
D1
6
2
CMP
(Note 3)
When T = 0
A – M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the con-
tents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
N
•
•
•
Z
C
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
__
M
44
E4
5
3
2
2
←
COM
CPX
M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
E0
C0
2
2
2
EC
CC
CE
4
4
6
3
3
3
X – M
Y – M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
C
2
C4
C6
3
5
2
2
CPY
DEC
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
C
•
1A
2
1
←
←
D6
6
2
DE
7
3
A
M
A – 1 or
M – 1
This instruction subtracts 1 from the contents
of A or M.
Rev.2.00 Oct 15, 2006 page 88 of 99
REJ09B0338-0200
Rev.2.00 Oct 15, 2006 page 89 of 99
REJ09B0338-0200
APPENDIX
APPENDIX
38K2 Group
3.6 Machine instructions
38K2 Group
3.6 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
OP n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP
ZP, X
ZP, Y
OP n
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
CA
#
1
# OP
#
n
# OP
#
n
#
OP
n
#
#
OP
#
OP
n
#
OP
#
OP
n
#
#
#
OP
#
OP
#
N
N
V
•
T
•
B
•
D
•
I
Z
Z
C
•
←
←
←
2
•
DEX
DEY
DIV
X
Y
A
X – 1
This instruction subtracts one from the current
contents of X.
88
1
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
2
Y – 1
This instruction subtracts one from the current
contents of Y.
(M(zz + X + 1),
M(zz + X )) / A
Divides the 16-bit data in M(zz+(X)) (low-order
byte) and M(zz+(X)+1) (high-order byte) by the
contents of A. The quotient is stored in A and
the one's complement of the remainder is
pushed onto the stack.
E2 16
2
2
←
M(S)
one's comple-
ment of Remainder
←
S
S – 1
2
2
45
3
2
4
55
4D
4
3
5D
5
3
59
5
3
41
6
2
51
6
2
49
N
•
•
•
•
•
Z
•
EOR
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bit-
wise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
–
←
A
A V M
When T = 1
–
←
M(X)
M(X) V M
M(X) represents the contents of memory
where is indicated by X.
E6
5
2
6
EE
4C
6
3
3
FE
7
3
F6
2
←
←
3A
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
•
2
1
INC
INX
A
M
A + 1 or
M + 1
This instruction adds one to the contents of A
or M.
E8
C8
1
1
←
2
2
X
X + 1
Y + 1
This instruction adds one to the contents of X.
This instruction adds one to the contents of Y.
←
N
•
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
INY
Y
3
6C
5
3
B2
4
2
JMP
If addressing mode is ABS
PCL
PCH
This instruction jumps to the address desig-
nated by the following three addressing
modes:
←
←
ADL
ADH
If addressing mode is IND
Absolute
←
←
PCL
PC
M (ADH, ADL)
M (AD , AD + 1)
Indirect Absolute
Zero Page Indirect Absolute
H
H
L
If addressing mode is ZP, IND
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
←
20
6
3
02
7
2
22
5
2
•
•
•
•
•
•
•
•
JSR
M(S)
PCH
S – 1
This instruction stores the contents of the PC
in the stack, then jumps to the address desig-
nated by the following addressing modes:
Absolute
←
S
←
PCL
S – 1
M(S)
←
S
After executing the above,
Special Page
if addressing mode is ABS,
Zero Page Indirect Absolute
←
←
PCL
PCH
ADL
ADH
if addressing mode is SP,
←
←
PCL
PCH
ADL
FF
If addressing mode is ZP, IND,
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
A9
2
2
A5
3C
3
4
2
3
B5
4
2
AD
4
3
BD
5
3
B9
5
3
A1
6
2
B1
6
2
N
•
•
•
•
•
•
•
•
•
•
Z
•
•
LDA
(Note 2)
When T = 0
When T = 0, this instruction transfers the con-
tents of M to A.
←
A
M
When T = 1
When T = 1, this instruction transfers the con-
tents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
←
M(X)
M
←
•
•
LDM
M
nn
This instruction loads the immediate value in
M.
←
←
A2
A0
2
2
2
2
A6
A4
3
3
2
2
B6
4
2
AE
AC
4
4
3
3
BE
5
3
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
•
LDX
LDY
X
Y
M
M
This instruction loads the contents of M in X.
This instruction loads the contents of M in Y.
B4
4
2
BC
5
3
Rev.2.00 Oct 15, 2006 page 90 of 99
REJ09B0338-0200
Rev.2.00 Oct 15, 2006 page 91 of 99
REJ09B0338-0200
APPENDIX
APPENDIX
38K2 Group
3.6 Machine instructions
38K2 Group
3.6 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
LSR
Function
Details
IMP
n
IMM
OP n
A
n
2
BIT, A
OP
ZP
n
BIT, ZP
OP
ZP, X
ZP, Y
OP
ABS
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
#
# OP
4A
#
1
n
# OP
46
#
2
n
#
OP
56
n
6
#
2
n
#
OP
4E
n
6
#
3
OP
5E
n
7
#
OP
#
n
#
#
#
OP
#
OP
#
N
0
V
•
T
•
B
•
D
•
I
Z
Z
C
C
5
3
•
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
7
0
→
C
→
0
←
S – 1
MUL
NOP
M(S) • A A M(zz + X) Multiplies Accumulator with the memory speci-
62 15
2
•
•
•
•
•
•
•
•
←
S
fied by the Zero Page X address mode and
stores the high-order byte of the result on the
Stack and the low-order byte in A.
←
PC
PC + 1
This instruction adds one to the PC but does
no otheroperation.
EA
2
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
09
2
2
3
2
01
6
2
11
6
2
N
Z
ORA
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the con-
tents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
05
15
4
2
0D
4
3
1D
5
3
5
3
19
←
A
A V M
When T = 1
←
M(X)
M(X) V M
M(X) represents the contents of memory
where is indicated by X.
←
PHA
PHP
PLA
PLP
ROL
S
S – 1
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
48
08
68
28
3
3
4
4
1
1
1
1
←
M(S)
←
PS
This instruction pushes the contents of PS to
the memory location designated by S and dec-
rements the contents of S by one.
S
S – 1
←
←
S
A
S + 1
M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
N
Z
←
S
S + 1
M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
(Value saved in stack)
←
PS
2A
6A
2
2
1
1
26
66
82
5
5
8
2
2
2
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
•
C
C
•
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
7
0
←
36
76
6
6
2
2
2E
6E
6
6
3
3
3E
7E
7
7
3
3
←
←
C
ROR
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
7
0
→
→
C
RRF
RTI
This instruction rotates 4 bits of the M content
to the right.
7
→
0
→
←
S
S + 1
M(S)
S + 1
←
M(S)
S + 1
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PCL. S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
(Value saved in stack)
40
60
6
6
1
1
←
PS
←
PCL
←
PCH
S
S
←
M(S)
←
PCL
RTS
S
S + 1
This instruction increments S by one and
stores the contents of the memory location
•
•
•
•
•
•
•
•
←
M(S)
←
S
S + 1
designated by S in PCL. S is again
←
←
PCH
(PC)
M(S)
(PC) + 1
incremented by one and the contents of the
memory location is stored in PCH. PC is
incremented by 1.
Rev.2.00 Oct 15, 2006 page 92 of 99
REJ09B0338-0200
Rev.2.00 Oct 15, 2006 page 93 of 99
REJ09B0338-0200
APPENDIX
APPENDIX
38K2 Group
3.6 Machine instructions
38K2 Group
3.6 Machine instructions
Addressing mode
Addressing mode
Processor status register
Symbol
Function
Details
IMP
n
IMM
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n
ZP, X
ZP, Y
OP n
ABS
ABS, X
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
#
OP
E9
n
2
# OP
2
#
n
# OP
E5
#
2
#
OP
F5
n
4
#
2
#
OP
ED
n
4
#
3
OP
FD
n
5
#
OP
F9
n
5
#
3
OP
#
n
#
OP
n
#
OP
F1
n
6
#
OP
#
OP
#
N
N
V
V
T
•
B
•
D
•
I
Z
Z
C
C
SBC
(Note 1)
(Note 5)
When T = 0
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the con-
tents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
3
3
E1 6
2
2
•
_
←
A
A – M – C
When T = 1
_
←
M(X)
M(X) – M – C
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
←
SEB
SEC
SED
SEI
Ai or Mi
1
This instruction sets the designated bit i of A
or M.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
0B
+
2
1
0F
+
5
2
20i
20i
←
←
C
D
1
1
This instruction sets C.
This instruction set D.
This instruction set I.
This instruction set T.
38
F8
78
32
2
2
2
2
1
1
1
1
•
1
•
•
←
I
1
•
1
•
•
←
←
SET
STA
STP
T
M
1
1
•
•
•
A
This instruction stores the contents of A in M.
The contents of A does not change.
85
4
2
95
5
2
8D
5
3
9D
6
3
99
6
3
81
7
2
91
7
2
•
•
•
This instruction resets the oscillation control F/ 42
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
2
1
•
•
•
•
←
←
←
←
5
2
STX
STY
TAX
TAY
TST
TSX
TXA
TXS
TYA
WIT
M
M
X
X
Y
This instruction stores the contents of X in M.
The contents of X does not change.
86
84
4
4
2
2
96
8E
8C
5
5
3
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
This instruction stores the contents of Y in M.
The contents of Y does not change.
94
5
2
•
A
This instruction stores the contents of A in X. AA
The contents of A does not change.
2
2
1
1
N
N
N
N
N
•
Z
Z
Z
Z
Z
•
Y
A
This instruction stores the contents of A in Y. A8
The contents of A does not change.
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
64
3
2
←
←
←
←
X
A
S
A
S
X
X
Y
This instruction transfers the contents of S in BA
X.
2
2
2
2
2
1
1
1
1
1
This instruction stores the contents of X in A.
This instruction stores the contents of X in S.
This instruction stores the contents of Y in A.
8A
9A
98
N
•
Z
•
The WIT instruction stops the internal clock C2
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All regis-
ters or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : N, V, and Z flags are invalid in decimal operation mode.
Rev.2.00 Oct 15, 2006 page 94 of 99
REJ09B0338-0200
Rev.2.00 Oct 15, 2006 page 95 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.6 Machine instructions
Symbol
Contents
Implied addressing mode
Symbol
Contents
IMP
+
Addition
IMM
A
Immediate addressing mode
–
✽
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
/
V
V
–
V
–
←
X
Y
ABS, X
ABS, Y
IND
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
S
Stack pointer
Program counter
PC
PS
PCH
PCL
ADH
ADL
FF
nn
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any ad-
dressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
zz
M
Z
Zero flag
I
D
B
T
V
N
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
M(X)
M(S)
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-or-
der bits.
M(ADH, ADL)
Negative flag
M(00, ADL)
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Ai
Mi
OP
n
Number of cycles
#
Number of bytes
Rev.2.00 Oct 15, 2006 page 96 of 107
REJ09B0338-0200
APPENDIX
38K2 Group
3.7 List of instruction code
3.7 List of instruction code
D3 – D0
0000
0001
0010
0011
0100
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
C
1101
D
1110
1111
F
Hexadecimal
notation
0
1
2
3
4
E
D7 – D4
ORA
JSR
BBS
ORA
ZP
ASL
ZP
BBS
0, ZP
ORA
IMM
ASL
A
SEB
0, A
ORA
ABS
ASL
ABS
SEB
0, ZP
BRK
—
PHP
CLC
PLP
SEC
PHA
CLI
—
0000
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IND, X ZP, IND 0, A
ORA
IND, Y
BBC
0, A
ORA
ASL
BBC
ORA
ABS, Y
DEC
A
CLB
0, A
ORA
ASL
CLB
BPL
JSR
CLT
—
—
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ZP, X ZP, X 0, ZP
ABS, X ABS, X 0, ZP
AND
ABS IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
AND
ABS
ROL
ABS
SEB
1, ZP
AND
BMI
BBC
1, A
AND
ROL
BBC
AND
ABS, Y
INC
A
CLB
1, A
LDM
AND
ROL
CLB
SET
STP
—
IND, Y
ZP, X ZP, X 1, ZP
ZP ABS, X ABS, X 1, ZP
EOR
RTI
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
EOR
ABS
LSR
ABS
SEB
2, ZP
IND, X
EOR
BVC
BBC
2, A
EOR
LSR
BBC
EOR
ABS, Y
CLB
2, A
EOR
LSR
CLB
—
—
—
—
IND, Y
ZP, X ZP, X 2, ZP
ABS, X ABS, X 2, ZP
ADC
RTS
MUL
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
ADC
ABS
ROR
ABS
SEB
3, ZP
PLA
SEI
IND, X ZP, X
ADC
—
BBC
3, A
ADC
ROR
BBC
ADC
ABS, Y
CLB
3, A
ADC
ROR
CLB
BVS
BRA
—
—
TXA
TXS
TAX
TSX
DEX
—
—
IND, Y
ZP, X ZP, X 3, ZP
ABS, X ABS, X 3, ZP
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
DEY
TYA
TAY
CLV
INY
—
STA
IND, Y
BBC
4, A
STY
STA
STX
BBC
STA
ABS, Y
CLB
4, A
STA
ABS, X
CLB
4, ZP
BCC
LDY
—
—
—
ZP, X ZP, X ZP, Y 4, ZP
LDA
LDX
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
LDA
IMM
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
IMM IND, X IMM
LDA
JMP
BBC
LDY
LDA
LDX
BBC
LDA
ABS, Y
CLB
LDY
LDA
LDX
CLB
BCS
IND, Y ZP, IND 5, A
ZP, X ZP, X ZP, Y 5, ZP
5, A ABS, X ABS, X ABS, Y 5, ZP
CPY
CMP
IMM IND, X
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
CMP
IMM
SEB
6, A
CPY
ABS
CMP
ABS
DEC
ABS
SEB
6, ZP
WIT
CMP
BNE
BBC
6, A
CMP
DEC
BBC
CMP
ABS, Y
CLB
6, A
CMP
DEC
CLB
—
—
CLD
INX
—
IND, Y
ZP, X ZP, X 6, ZP
ABS, X ABS, X 6, ZP
CPX
SBC
DIV
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
SBC
IMM
SEB
7, A
CPX
ABS
SBC
ABS
INC
ABS
SEB
7, ZP
NOP
—
IMM IND, X ZP, X
SBC
IND, Y
BBC
7, A
SBC
INC
BBC
SBC
ABS, Y
CLB
7, A
SBC
INC
CLB
BEQ
—
—
SED
—
ZP, X ZP, X 7, ZP
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
Rev.2.00 Oct 15, 2006 page 97 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.8 SFR memory map
3.8 SFR memory map
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
Port P0 (P0)
Prescaler 12 (PRE12)
Timer 1 (T1)
Port P0 direction register (P0D)
Timer 2 (T2)
Port P1 (P1)
Timer X mode register (TM)
Prescaler X (PREX)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Timer X (TX)
Transmit/Receive buffer register (TB/RB)
Serial I/O status register (SIOSTS)
Port P3 direction register (P3D)
Port P4 (P4)
HUB interrupt source enable register (HUBICON)
HUB interrupt source register (HUBIREQ)
HUB down stream port index register (HUBINDEX)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
002B16
002C16
002D16
HUB port field register 1 (DPXREG1)
HUB port field register 2 (DPXREG2)
HUB port field register 3 (DPXREG3)
Port P6 direction register (P6D)
Reserved (Note)
002E16 Reserved (Note)
Reserved (Note)
002F16
003016
003116
Reserved (Note)
EXB interrupt source enable register (EXBICON)
USB control register (USBCON)
USB function/Hub enable register (USBAE)
EXB interrupt source register (EXBIREQ)
Reserved (Note)
003216
003316
003416
USB function address register (USBA0)
EXB index register (EXBINDEX)
Register window 1 (EXBREG1)
USB HUB address register (USBA1)
Frame number register Low (FNUML)
Frame number register High (FNUMH)
USB interrupt source enable register (USBICON)
003516
003616
003716
Register window 2 (EXBREG2)
AD control register (ADCON)
AD conversion register 1 (AD1)
AD conversion register 2 (AD2)
USB interrupt source register (USBIREQ)
Endpoint index register (USBINDEX)
Endpoint field register 1 (EPXXREG1)
Endpoint field register 2 (EPXXREG2)
Endpoint field register 3 (EPXXREG3)
Endpoint field register 4 (EPXXREG4)
Endpoint field register 5 (EPXXREG5)
Endpoint field register 6 (EPXXREG6)
Endpoint field register 7 (EPXXREG7)
003816
003916 Watchdog timer control register (WDTCON)
003A16
003B16
Reserved (Note)
CPU mode register (CPUM)
003C16 Interrupt request register 1(IREQ1)
003D16 Interrupt request register 2(IREQ2)
003E16
003F16
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
Serial I/O control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
Reserved (Note)
Port P0 pull-up control register (PULL0)
Reserved (Note)
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
Port P5 pull-up control register (PULL5)
Interrupt edge selection register (INTEDGE)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
0FE616 Reserved (Note)
Reserved (Note)
0FE716
Reserved (Note)
Reserved (Note)
0FE816
0FE916
0FEA16
Reserved (Note)
PLL control register (PLLCON)
Downstream port control register (DPCTL)
Reserved (Note)
Reserved (Note)
0FFA16 Reserved (Note)
Reserved (Note)
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FFB16 MISRG
Endpoint field register 8 (EPXXREG8)
Endpoint field register 9 (EPXXREG9)
Reserved (Note)
0FFC16
Reserved (Note)
0FFD16
0FFE16
Flash memory control register (FMCR)
Reserved (Note)
Reserved (Note)
Reserved (Note)
0FFF16
Note: Do not write any data to these addresses, because these areas are reserved.
Rev.2.00 Oct 15, 2006 page 98 of 99
REJ09B0338-0200
APPENDIX
38K2 Group
3.9 Pin configurations
3.9 Pin configurations
P0
6
7
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
P2
5
4
P0
P2
P4
0
/E
/E
P4
P4
X
DREQ/R
X
D
D2+
P4
1
X
DACK/T
X
D
D2-
29
28
27
D1+
2
/E
X
TC/SCLK
D1-
3
/E
X
A1/SRDY
26
25
24
23
22
21
20
19
18
17
D0-
P3
P3
P3
0
1
2
M38K27M4L-XXXFP/HP
M38K29F8LFP/HP
D0+
TrON
USBVREF
DVCC
PVCC
PVSS
P3
P3
3
/E
/E
/E
/E
/E
X
INT
4
X
CS
P3
5
X
WR
P3
6
XRD
P6
P6
P6
3
2
1
(LED
(LED
(LED
3
2
1
)
)
)
P3
7
X
A0
P1
0
/DQ
0
/AN
/AN
0
1
P1
1
/DQ
1
Rev.2.00 Oct 15, 2006 page 99 of 99
REJ09B0338-0200
REVISION HISTORY
38K2 GROUP USER’S MANUAL
Rev.
Date
Description
Summary
Page
1.0
2.0
2/13/03
First Edition
10/15/06 All pages Package names “64P6U-A” → “PLQP0064GA-A” revised
Package names “64P6Q-A” → “PLQP0064KB-A” revised
38K2 group (Standard) deleted
Chapter 1
94
97
Fig. 137 revised
CLOCK GENERATING CIRCUIT; “No external resistor is needed .... resistor exists
on-chip.” → “No external resistor is needed .... depending on conditions.)
Fig. 141; Pulled up added, NOTE added
98
Fig. 144 revised
128
NOTES ON USAGE; Power Source Voltage, USB Communication added
Chapter2
3
Fig. 2.1.3; “Do not set bits of .... If writing to these bits, write “0”.” added
Chapter3
20
35
48
3.2 deleted
3.3.6 (3) USB Communication added
Fig. 3.5.2; “Do not set bits of .... If writing to these bits, write “0”.” added
92, 93 3.6 Package outline revised
(1/1)
RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER
USER’S MANUAL
38K2 Group
Publication Data : Rev.1.00 Feb 13, 2003
Rev.2.00 Oct 15, 2006
Published by :
Sales Strategic Planning Div.
Renesas Technology Corp.
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
38K2 Group
User's Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
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