M5M5256DFP-70G [RENESAS]
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM; 262144 - BIT （ 32768 -字×8位）的CMOS静态RAM
| 型号： | M5M5256DFP-70G |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M5256DFP,VP is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is f abricated using
high-perf ormance 3 poly silicon CMOS technology . The use of
resistiv e load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough f or battery back-up application. It is ideal f or the memory
sy stems which require simple interf ace.
28
1
2
A14
A12
Vcc
/W
27
26
25
3
A13
A8
A7
A6
A5
A4
4
24
23
22
21
20
19
18
17
16
15
5
A9
A11
/OE
6
Especially the M5M5256DVP are packaged in a 28-pin thin small
outline package.
7
A3
A2
A1
A0
8
A10
/S
DQ8
DQ7
DQ6
DQ5
9
10
DQ1 11
DQ2
12
13
14
FEATURE
DQ3
GND
Power supply current
Access
Oprating
DQ4
Ty pe
time
(max)
Activ e
(max)
Stand-by
(max)
Temperature
Outline 28P2W-C (FP)
20µA
(Vcc=5.5V)
M5M5256DFP,VP
-70G
70ns
70ns
0~70°C
22
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
/S
DQ8
DQ7
DQ6
DQ5
/OE
A11
12µA
(Vcc=3.6V)
23
24 A9
25
45mA
A8
(Vcc=5.5V)
40µA
(Vcc=5.5V)
26
A13
/W
Vcc
A14
A12
A7
M5M5256DFP,VP
-70GI
27
28
1
-40~85°C
0~70°C
24µA
(Vcc=3.6V)
DQ4
GND
M5M5256DVP
25mA
(Vcc=3.6V)
2
DQ3
DQ2
DQ1
A0
A1
A2
5µA
(Vcc=5.5V)
3
M5M5256DFP,VP
-70XG
2.4µA
4
70ns
A6
A5
A4
A3
(Vcc=3.6V)
5
0.05µA
(Vcc=3.0V Typical)
6
8
7
•Single 3.0~5.5V power supply
•No clocks, no ref resh
Outline 28P2C-A (VP)
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prev ents data contention in the I/O bus
•Common Data I/O
•Battery backup capability
•Low stand-by current .......... 0.05µA(ty p.)
PACKAGE
M5M5256DFP
M5M5256DVP
: 28 pin 450 mil SOP
: 28pin 8 X 13.4 mm TSOP
2
APPLICATION
Small capacity memory units
1
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
The operation mode of the M5M5256DFP,VP is
A read cy cle is executed by setting /W at a high lev el
determined by a combination of the dev ice control inputs
/S, /W and /OE. Each mode is summarized in the f unction
table.
and /OE at a low lev el while /S are in an activ e state.
When setting /S at a high lev el, the chip is in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specif ied
as Icc3 or Icc4, and the memory data can be held at
+2V power supply , enabling battery back-up operation
during power f ailure or power-down operation in the non-
selected mode.
A write cy cle is executed whenev er the low lev el /W
ov erlaps with the low lev el /S. The address must be set
up bef ore the write cy cle and must be stable during the
entire cy cle. The data is latched into a cell on the trailing
edge of /W, /S, whichev er occurs f irst, requiring the set-
up and hold time relativ e to these edge to be maintained.
The output enable /OE directly controls the output stage.
Setting the /OE at a high lev el,the output stage is in a
high-impedance state, and the data bus contention
problem in the write cy cle is eliminated.
FUNCTION TABLE
DQ
/S
H
L
/OE
X
Mode
Icc
/W
High-impedance
Stand-by
Activ e
Activ e
Activ e
Non selection
Write
X
L
DIN
X
L
Read
DOUT
L
L
H
H
High-impedance
H
Note • "H" and "L" in this table mean VIH and VIL, respectiv ely .
• "X" in this table should be "H" or "L".
BLOCK DIAGRAM
A 8
25
26
1
11
DQ1
DQ2
DQ3
32768 WORD
X 8BIT
A 13
A 14
12
13
2
A 12
A 7
15
16
DQ4
DQ5
DQ6
DATA I/O
3
4
5
6
7
(512 ROWS X
A 6
17
18
A 5
A 4
512 COLUMNS)
DQ7
DQ8
19
ADDRESS
INPUT
A 3
A 2
A 1
A 0
A 10
A 11
A 9
8
9
10
21
23
24
CLOCK
GENERATOR
WRITE CONTROL
INPUT /W
27
20
22
VCC
(5V)
28
CHIP SELECT
INPUT
/S
14 GND
(0V)
OUTPUT ENABLE
INPUT
/OE
2
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Conditions
Ratings
-0.3*~7.0
Unit
V
Symbol
Vcc
Parameter
Supply voltage
-0.3*~Vcc+0.3
VI
Input voltage
V
With respect to GND
(Max 7.0)
Output voltage
Power dissipation
V
mW
VO
Pd
0~Vcc
700
0~70
-40~85
-65~150
Ta=25°C
-G,-XG
-GI
Operating temperature
Topr
°C
°C
Storage temperature
* -3.0V in case of AC ( Pulse width < 30ns )
Tstg
_
DC ELECTRICAL CHARACTERISTICS
Limits2
(Vcc=5.0±0.5V)
Unit
Limits1
Symbol Parameter
Test conditions
(Vcc=5.0±0.5V)
(Vcc=3.3±0.3V)
Min Typ Max Min Typ Max
Vcc
+0.3
Vcc
+0.3
VIH
2.0
2.2
High-level input voltage
V
V
Low-level input voltage
VIL
-0.3*
0.6 -0.3*
2.4
0.8
IOH=-1mA
IOH=-0.5mA
IOH=-0.1mA
2.4
V
High-level output voltage 1
VOH1
(Vcc=3.3±0.3V)
(Vcc=5.0±0.5V)
Vcc
-0.5
Vcc
-0.5
High-level output voltage 2
Low-level output voltage
VOH2
VOL
V
V
IOH=-0.05mA (Vcc=3.3±0.3V)
IOL=2mA
IOL=1mA
(Vcc=5.0±0.5V)
(Vcc=3.3±0.3V)
0.4
0.4
II
±1
±1
±1
±1
Input current
VI=0~Vcc
µA
µA
IO
Output current in off-state
/S=VIH or or /OE=VIH, VI/O=0~Vcc
_
/S<0.2V, Output-open
Other inputs<0.2V
70ns
13 25
1.5
14 25
25 40
Active supply current
(AC, MOS lev el )
Icc1
Icc2
mA
mA
1MHz
70ns
1MHz
-G,-GI
-XG
3
2
4
or >Vcc-0.2V
25 45
/S=VIL, Output-open
other inputs=VIH or VIL
Active supply current
(AC, TTL lev el )
1.5
3
4
8
2
1.2
0.3
3.6
0.8
12
~25°C
~40°C
0.05
0.1
0.4
6
-G,-GI
-XG
_
/S>Vcc-0.2V,
Stand-by current
Stand-by current
1.2
20
Icc3
Icc4
µA
other inputs =0~Vcc
-G,-GI
-XG
~70°C
~85°C
2.4
24
5
-GI
40
/S=VIH,other inputs=0~Vcc
0.33
3
mA
_
* -3.0V in case of AC ( Pulse width < 30ns )
CAPACITANCE
Limits
Min Typ Max
Unit
Symbol
Parameter
Test conditions
pF
pF
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
CI
CO
6
8
Note 0: Direction f or current f lowing into an IC is positiv e (no mark).
1: Ty pical v alue is one at Ta = 25°C.
2: CI, CO are periodically sampled and are not 100% tested.
3
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
Limits1
Vcc=3.3±0.3V
Limits2
Vcc=5.0±0.5V
Unit
Symbol
Parameter
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after /S high
Min Max Min Max
tCR
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
ta(A)
ta(S)
ta(OE)
70
70
35
25
25
70
70
35
25
25
tdis(S)
tdis(OE) Output disable time after /OE high
ten(S)
ten(OE)
tV(A)
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
5
5
5
5
10
10
(2) WRITE CYCLE
Limits1
Vcc=3.3±0.3V
Limits2
Vcc=5.0±0.5V
Symbol
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to /W high
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
Output enable time from /OE low
Unit
Min Max Min Max
70
55
0
70
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S)
65
65
30
65
65
30
tsu(D)
th(D)
0
0
0
0
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
25
25
25
25
5
5
5
5
4
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
(3) TIMING DIAGRAMS
Read cycle
tCR
A0~14
ta(A)
tv (A)
ta (S)
/S
(Note 3)
(Note 3)
ta (OE)
(Note 3)
(Note 3)
tdis(S)
ten (OE)
/OE
tdis (OE)
ten (S)
DATA VALID
DQ1~8
/W = "H" lev el
Write cycle (/W control mode)
tCW
A0~14
tsu (S)
/S
(Note 3)
(Note 3)
tsu (A-WH)
/OE
/W
tsu (A)
tw (W)
trec (W)
ten (W)
tdis (W)
ten(OE)
tdis (OE)
DATA IN
STABLE
DQ1~8
(Note 3)
(Note 3)
tsu (D)
th (D)
5
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( /S control mode)
tCW
A0~14
tsu (A)
tsu (S)
trec (W)
/S
(Note 5)
/W
(Note 4)
tsu (D)
(Note 3)
(Note 3)
th (D)
DATA IN
STABLE
DQ1~8
(4) MEASUREMENT CONDITIONS
DQ
Limits1:Vcc=3.3±0.3V
Input pulse level .............. VIH=2.4V,VIL=0.4V
Input rise and fall time ..... 5ns
L
C
(Including
scope and JIG)
Reference level ................ VOH=VOL=1.5V
Output load ...................... Fig.1, CL=30pF
CL=5pF (for ten,tdis)
Fig.1 Output load
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Limits2:Vcc=5.0±0.5V
Vcc
1.8kW
Input pulse level .............. VIH=2.4V,VIL=0.6V
Input rise and fall time ..... 5ns
Reference level ................ VOH=VOL=1.5V
Output load ...................... Fig.2, CL=100pF
DQ
L
C
990W
CL=5pF (for ten,tdis)
(Including
scope and JIG)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Fig.2 Output load
Note 3 : Hatching indicates the state is "don't care".
4 : Writing is executed in ov erlap of /S and /W low.
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inv erted phase signal externally when DQ pin is output mode.
7 : ten, tdis are periodically sampled and are not 100% tested.
6
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Min Typ Max
2
Symbol
Parameter
Test conditions
Unit
Vcc (PD)
Power down supply v oltage
V
V
V
_
2.2V < VCC(PD)
2.2
VI (/S)
Chip select input /S
_
_
2V< VCC(PD) < 2.2V
VCC(PD)
-G,-GI
1
~25°C
0.05
0.2
3
-XG
-G,-GI
_
Vcc = 3V,/S > Vcc-0.2V,
~40°C
Icc (PD)
Power down supply current
0.6
10
2
µA
-XG
-G,-GI
Other inputs=0~Vcc
~70°C
~85°C
-XG
-GI
20
(2) TIMING REQUIREMENTS
Limits
Min Typ Max
Symbol
Unit
Parameter
Test conditions
tsu (PD)
trec (PD)
Power down set up time
Power down recov ery time
ns
ns
0
tCR
(3) POWER DOWN CHARACTERISTICS
/S control mode
Vcc
3.0V
3.0V
tsu (PD)
trec (PD)
2.2V
2.2V
_
/S
/S > Vcc-0.2V
7
RENESAS LSIs
M5M5256DFP,VP -70G,-70GI,-70XG
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
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REJ03C0054 © 2003 Renesas Technology Corp.
New publication, effective Feb 2004.
Specifications subject to change without notice
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