M5M5V5A36GP-85#A0 [RENESAS]
Network Search Engine, LQFP, /Embossed Tape;
| 型号： | M5M5V5A36GP-85#A0 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Network Search Engine, LQFP, /Embossed Tape 时钟 静态存储器 内存集成电路 |
| 文件： | 总21页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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1.
2.
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Renesas LSIs
Preliminary
M5M5V5A36GP-75,85
Notice: This is not final specification.
Some parametric limits are subject to change.
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
FEATURES
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
• Flow-Through Read mode, Single Late Write mode
• Fast access time: 7.5 ns and 8.5 ns
• Single 3.3V -5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V I/O
• Individual byte write (BWa# - BWd#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• CKE# pin to enable clock and suspend operations
• Internally self-timed, registers outputs eliminate the need
to control G#
BWd#) and Read/Write (W#).
Write operations are controlled by the four Byte Write Enables
(BWa# - BWd#) and Read/Write(W#) inputs. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ).
The HIGH input of ZZ pin puts the SRAM in the power-down
state.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
• Snooze mode (ZZ) for power down
• Three chip enables for simple depth expansion
Package
100pin TQFP
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
PART NAME TABLE
Active Current
(max.)
Standby Current
(max.)
Part Name
Access
7.5ns
8.5ns
Cycle
8.5ns
10ns
M5M5V5A36GP-75
M5M5V5A36GP-85
280mA
260mA
30mA
30mA
1/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
PIN CONFIGURATION(TOP VIEW)
100pin TQFP
A9 81
A8 82
A17 83
A18 84
ADV 85
G# 86
50 A10
49 A11
48 A12
47 A13
46 A14
45 A15
44 A16
43 NC
42 NC
41 VDD
CKE# 87
W# 88
CLK 89
VSS 90
VDD 91
E3# 92
BWa# 93
BWb# 94
BWc# 95
BWd# 96
E2 97
40 VSS
M5M5V5A36GP
39 NC
38 NC
37 A0
36 A1
35 A2
34 A3
33 A4
32 A5
31 LBO#
E1# 98
A7 99
A6 100
Note1. MCH means "Must Connect High". MCH should be connected to HIGH.
Note2. MCL means "Must Connect Low". MCL should be connected to LOW.
2/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
BLOCK DIAGRAM
VDD
VDDQ
A0
A1
19
19
17
ADDRESS
REGISTER
A2~18
A1
A0
A1'
A0'
D1
D0
Q1
Q0
LINEAR/
INTERLEAVED
BURST
COUNTER
19
19
CLK
CKE#
WRITE ADDRESS
REGISTER
ZZ
ADV
DQa
DQPa
DQb
BYTE1
WRITE
DRIVERS
BWa#
BWb#
BWc#
BWd#
BYTE2
WRITE
DRIVERS
256Kx36
WRITE REGISTRY
AND
DQPb
DQc
DATA COHERENCY
CONTROL LOGIC
MEMORY
ARRAY
BYTE3
WRITE
DRIVERS
DQPc
DQd
BYTE4
WRITE
DRIVERS
W#
DQPd
INPUT
36
REGISTER
READ
LOGIC
G#
E1#
E2
E3#
VSS
Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
3/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
PIN FUNCTION
Pin
Name
Function
Synchronous
Address
Inputs
These inputs are registered and must meet the setup and hold times around the rising edge of
CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal
burst counter if burst is desired.
A0~A18
These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be
asserted on the same cycle as the address. BWs are associated with addresses and apply to
subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc#
controls DQc, DQPc pins; BWd# controls DQd, DQPd pins.
Synchronous
Byte Write
Enables
BWa#, BWb#,
BWc#, BWd#
This signal registers the address, data, chip enables, byte write enables
and burst control inputs on its rising edge. All synchronous inputs must
meet setup and hold times around the clock's rising edge.
CLK
E1#
E2
Clock Input
Synchronous
Chip Enable
This active LOW input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW).
Synchronous
Chip Enable
This active High input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
Synchronous
Chip Enable
This active Low input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
E3#
G#
Output Enable
This active LOW asynchronous input enable the data I/O output drivers.
Synchronous
Address
Advance/Load
When HIGH, this input is used to advance the internal burst counter, controlling burst access after
the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new
address to be loaded at CLK rising edge.
ADV
This active LOW input permits CLK to propagate throughout the device. When HIGH, the device
ignores the CLK input and effectively internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is
HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input
leak current to this pin.
This active HIGH asynchronous input causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When active, all other inputs are ignored. When this
pin is LOW or NC, the SRAM normally operates.
Synchronous
Clock Enable
CKE#
LBO#
ZZ
Burst Mode
Control
Snooze
Enable
This active input determines the cycle type when ADV is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice
versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
Synchronous
Read/Write
W#
DQa,DQPa,DQb,DQPb Synchronous
DQc,DQPc,DQd,DQPd Data I/O
Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is
DQd,DQPd pins. Input data must meet setup and hold times around CLK rising edge.
VDD
VSS
VDD
Core Power Supply
VSS
Core Ground
VDDQ
VSSQ
MCH
MCL
NC
VDDQ
I/O buffer Power supply
VSSQ
I/O buffer Ground
Must Connect High
Must Connect Low
No Connect
These pins should be connected to HIGH
These pins should be connected to LOW
These pins are not internally connected and may be connected to ground.
4/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
Read Operations
Flow-Through Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and
E3#) are active, the write enable input signal (W#) is deasserted high, and ADV is asserted low.
CLK
E1#
ADV
W#
A
B
C
D
E
Q(B)
Q(C)
Q(D)
Read E
Q(A)
Read A
Deselect
Read B
Read C
Read D
Write Operation Single Late Write
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3#)
are active, the write enable input signal (W#) is asserted low, and ADV is asserted low.
In Single Late Write the RAM requires Data in one rising clock edge later than the edge used to load Address and Control.
#0
#1
#2
#3
#4
E1#
ADV
W#
BWx#
ADD
DQ
A
B
C
D
E
D(C)
D(A)
Deselect
D(B)
D(D)
Write A
Write B
Write C
Write D
Write E
5/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
Single Late Write with Flow-Through Read
#0
#1
#2
#3
#4
#5
#6
CLK
E1#
ADV
W#
BWx#
ADD
DQ
A
B
C
D
E
F
D(A)
Q(B)
Deselect
D(C)
Q(D
D(E
Write A
Read B
Write C
Read D
Write E
Read F
6/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
DC OPERATED TRUTH TABLE
Name
Input Status
HIGH or NC
LOW
Operation
Interleaved Burst Sequence
Linear Burst Sequence
LBO#
Note4. LBO# is DC operated pin.
Note5. NC means No Connection.
Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation
A18~A2
A1,A0
0 , 1
0 , 0
1 , 1
1 , 0
1 , 0
1 , 1
0 , 0
0 , 1
First access, latch external address
Second access(first burst address)
Third access(second burst address)
Fourth access(third burst address)
A18~A2
0 , 0
0 , 1
1 , 0
1 , 1
1 , 1
1 , 0
0 , 1
0 , 0
latched A18~A2
latched A18~A2
latched A18~A2
Linear Burst Sequence
Operation
A18~A2
A1,A0
0 , 1
First access, latch external address
Second access(first burst address)
Third access(second burst address)
Fourth access(third burst address)
A18~A2
0 , 0
1 , 0
1 , 1
0 , 0
0 , 1
1 , 1
latched A18~A2
latched A18~A2
latched A18~A2
0 , 1
1 , 0
1 , 1
1 , 0
1 , 1
0 , 0
0 , 0
0 , 1
1 , 0
Note7. The burst sequence wraps around to its initial state upon completion.
TRUTH TABLE
Address
E1#
E2
E3#
ZZ
ADV
W#
BWx#
G#
CKE#
CLK
DQ
Operation
used
None
None
None
None
H
X
X
X
L
X
L
X
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L->H
L->H
L->H
L->H
L->H
L->H
L->H
L->H
L->H
L->H
L->H
L->H
L->H
X
High-Z
High-Z
High-Z
High-Z
Q
Deselect Cycle
Deselect Cycle
X
X
H
X
H
X
H
X
H
X
X
X
L
Deselect Cycle
H
L
Continue Deselect Cycle
External Read Cycle, Begin Burst
Next Read Cycle, Continue Burst
External NOP/Dummy Read, Begin Burst
Next
Dummy Read, Continue Burst
External Write Cycle, Begin Burst
X
L
X
L
H
L
L
Q
H
H
X
X
X
X
X
X
High-Z
High-Z
D
X
L
X
L
H
L
X
L
X
L
H
L
X
L
L
D
Next
None
Next
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
H
H
X
X
High-Z
High-Z
-
X
X
X
X
X
X
H
X
X
X
X
X
Current Ignore Clock edge, Stall
None Snooze Mode
High-Z
Note8. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL.
Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more
Synchronous Byte Write Enables are LOW.
Note10. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
STATE DIAGRAM
F , L , X
Deselect
F , L , X
T , L , L
T , L , H
F , L , X
X , H , X
T , L , L
T , L , H
Write
Begin
Burst
Read
Begin
Burst
T , L , H
T , L , L
X , H , X
X , H , X
T , L , L
T , L , H
T , L , L
T , L , H
Read
Continue
Burst
Write
Continue
Burst
X , H , X
X , H , X
Key
Input Command Code
Transition
f
Current State
Next State
Note11. The notation "x , x , x" controlling the state transitions above indicate the state of inputs E, ADV and W# respectively.
Note12. If (E1# = L and E2 = H and E3# = L) then E="T" else E="F".
Note13. "H" = input VIH; "L" = input VIL; "X" = input VIH or VIL; "T" = input "true"; "F" = input "false".
8/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
WRITE TRUTH TABLE
W#
H
L
BWa#
BWb#
BWc#
BWd#
Function
Read
X
L
X
H
L
X
H
H
L
X
H
H
H
L
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write Abort/NOP
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Note14. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL.
Note15. All inputs except G# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Power Supply Voltage
I/O Buffer Power Supply Voltage
Input Voltage
Conditions
Ratings
-1.0*~4.6
-1.0*~4.6
-1.0~VDDQ+1.0**
-1.0~VDDQ+1.0**
1180
Unit
V
VDDQ
VI
V
With respect to VSS
V
VO
Output Voltage
V
PD
Maximum Power Dissipation (VDD)
Operating Temperature
Storage Temperature(bias)
Storage Temperature
mW
°C
°C
°C
TOPR
TSTG(bias)
TSTG
0~70
-10~85
-65~150
Note16.* This is –1.0V when pulse width≤2ns, and –0.5V in case of DC.
** This is –1.0V~VDDQ+1.0V when pulse width≤2ns, and –0.5V~VDDQ+0.5V in case of DC.
CAPACITANCE
Symbol
Limits
Typ
Parameter
Conditions
Unit
Min
Max
6
CI
CO
Input Capacitance
Input / Output(DQ) Capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND, VO=25mVrms, f=1MHz
pF
pF
8
Note19.This parameter is sampled.
THERMAL RESISTANCE
4-Layer PC board mounted (70x70x1.6mmT)
Limits
Typ
28
Symbol
Parameter
Conditions
Unit
Min
Max
θJA
Thermal Resistance Junction Ambient
Air velocity=0m/sec
Air velocity=2m/sec
°C/W
°C/W
°C/W
20
θJC
Thermal Resistance Junction to Case
6.6
Note20.This parameter is sampled.
9/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=3.135~3.465V, unless otherwise noted)
Limits
Symbol
Parameter
Condition
Unit
V
Min
3.135
3.135
2.375
2.0
Max
VDD
Power Supply Voltage
3.465
3.465
2.625
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ I/O Buffer Power Supply Voltage
V
VDDQ = 3.135~3.465V
VDDQ = 2.375~2.625V
VDDQ = 3.135~3.465V
VDDQ = 2.375~2.625V
IOH = -2.0mA
VIH
VIL
High-level Input Voltage
Low-level Input Voltage
VDDQ+0.3*
V
V
1.7
0.8
0.7
-0.3*
VOH
VOL
High-level Output Voltage
Low-level Output Voltage
VDDQ-0.4
V
V
IOL = 2.0mA
0.4
10
Input Current except ZZ and LBO# VI = 0V ~ VDDQ
ILI
µA
µA
Input Current of LBO#
Input Current of ZZ
VI = 0V ~ VDDQ
100
100
10
VI = 0V ~ VDDQ
ILO
ICC1
Off-state Output Current
VI (G#) ≥ VIH, VO = 0V ~ VDDQ
Device selected;
-75(Cycle time=8.5ns)
280
260
90
Output Open
VI≤VIL or VI≥VIH
ZZ≤VIL
Power Supply Current : Operating
Power Supply Current : Deselected
mA
-85(Cycle time=10ns)
-75(Cycle time=8.5ns)
-85(Cycle time=10ns)
Device
deselected
VI≤VIL or VI≥VIH
ZZ≤VIL
ICC2
mA
80
Device deselected; Output Open
VI≤VSS+0.2V or VI≥VDDQ-0.2V
CLK frequency=0Hz, All inputs static
Snooze mode
CMOS Standby Current
(CLK stopped standby mode)
ICC3
ICC4
30
30
80
mA
mA
Snooze Mode Standby Current
Stall Current
ZZ≥VDDQ-0.2V
Device selected;
Output Open
CKE#≥VIH
-75(Cycle time=8.5ns)
ICC5
mA
VI≤VSS+0.2V or
VI≥VDDQ-0.2V
-85(Cycle time=10ns)
70
Note17.*VILmin is –1.0V and VIH max is VDDQ+1.0V in case of AC(Pulse width≤2ns).
Note18."Device Deselected" means device is in power-down mode as defined in the truth table.
10/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=3.135~3.465V, unless otherwise noted)
(1)MEASUREMENT CONDITION
Input pulse levels ········································ VIH=VDDQ, VIL=0V
Input rise and fall times ······························· faster than or equal to 1V/ns
Input timing reference levels ······················· VIH=VIL=0.5*VDDQ
Output reference levels ·······························VIH=VIL=0.5*VDDQ
Output load ·················································· Fig.1
30pF
Q
(Including wiring and JIG)
50Ω
VT=0.5*VDDQ
ZO=50Ω
Fig.1 Output load
Input
Waveform
VDDQ / 2
Input
Waveform
VDDQ / 2
toff
ton
tplh
tphl
Vh
Vl
Vh-(0.2(Vh-Vz)) Vz+(0.2(Vh-Vz))
Vz
Output
Waveform
Output
Waveform
VDDQ / 2
(toff)
(ton)
0.2(Vz-Vl)
Vz-(0.2(Vz-Vl))
Fig.2 Tdly measurement
Fig.3 Tri-State measurement
Note21.Valid Delay Measurement is made from the VDDQ/2 on the input waveform to the VDDQ/2 on the output waveform.
Input waveform should have a slew rate of faster than or equal to 1V/ns.
Note22.Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20%
from its initial to final Value VDDQ/2.
Note:the initial value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table.
Note23. Tri-state ton measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20%
from its initial Value VDDQ/2 to its final Value.
Note:the final value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table.
Note24.Clocks,Data,Address and control signals will be tested with a minimum input slew rate of faster than or equal to 1V/ns.
11/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
(2)TIMING CHARACTERISTICS
Symbol Parameter
Clock
Limits
Unit
-75
-85
Min
Max
Min
Max
tKHKH
tKHKL
tKLKH
Clock Cycle time
Clock HIGH time
Clock LOW time
8.5
2.8
2.8
10
3.0
3.0
ns
ns
ns
Output times
tKHQV
tKHQX
tKHQX1
tKHQZ
Clock HIGH to output valid
Clock HIGH to output invalid
Clock HIGH to output in LOW-Z
Clock HIGH to output in High-Z
G# to output valid
7.5
8.5
ns
ns
ns
ns
ns
ns
ns
2.5
2.5
2.5
2.5
4.0
3.5
5.0
4.0
tGLQV
tGLQX1
tGHQZ
Setup times
tAVKH
tckeVKH
tadvVKH
tWVKH
tBVKH
G# to output in Low-Z
0.0
0.0
G# to output in High-Z
3.5
4.0
Address valid to clock HIGH
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
CKE# valid to clock HIGH
ADV valid to clock HIGH
Write valid to clock HIGH
Byte write valid to clock HIGH (BWa#~BWd#)
Enable valid to clock HIGH (E1#,E2,E3#)
Data In valid to clock HIGH
tEVKH
tDVKH
Hold times
tKHAX
tKHckeX
tKHadvX
tKHWX
tKHBX
Clock HIGH to Address don’t care
Clock HIGH to CKE# don’t care
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
Clock HIGH to ADV don’t care
Clock HIGH to Write don’t care
Clock HIGH to Byte Write don’t care (BWa#~BWb#)
Clock HIGH to Enable don’t care (E1#,E2,E3#)
Clock HIGH to Data In don’t care
tKHEX
tKHDX
ZZ
tZZS
tZZREC
ZZ standby
ZZ recovery
2*tKHKH
2*tKHKH
2*tKHKH
2*tKHKH
ns
ns
Note25.All parameter except tZZS, tZZREC in this table are measured on condition that ZZ=LOW fix.
Note26.Test conditions is specified with the output loading shown in Fig.1 unless otherwise noted.
Note27. tKHQX1, tKHQZ, tGLQX1, tGHQZ are sampled.
Note28.LBO# is static and must not change during normal operation.
12/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
(3)READ TIMING
tKHKH
CLK
tckeVKH
CKE#
tEVKH
tKHKL
tKLKH
tKHckeX
tKHEX
E#
tadvVKH
ADV
tKHadvX
tWVKH
tKHWX
W#
BWx#
tAVKH
tKHAX
A1
A2
A3
ADD
tKHQX1
tGLQV
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A3)
Q(A3+1)
Q(A3+1)
DQ
G#
tGHQZ
tKHQV
tKHQX
tKHQZ
tGLQX1
Read A1
Read A2 Burst Read
A2+1
Stall
Burst Read Burst Read Burst Read Deselect
A2+2 A2+3 A2
Continue
Deselect
Read A3 Burst Read Burst Read Burst Read
A3+1
A3+2
A3+3
DON’T CARE
UNDEFINED
Note29.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note30. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note31.ZZ is fixed LOW.
13/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
(4)WRITE TIMING
tKHKH
CLK
tKHKL
tKLKH
tckeVKH
CKE#
tKHckeX
tEVKH
tKHEX
E#
tadvVKH
ADV
tKHadvX
tWVKH
tKHWX
tKHBX
W#
tBVKH
BWx#
tAVKH
tKHAX
A1
A2
A3
A4
ADD
DQ
G#
tDVKH
tKHDX
D(A1)
D(A2)
D(A2+1)
D(A2+3)
D(A2)
D(A3)
D(A4)
D(A4+1
D(A4+2)
Write A4
Write A1
Write A2 Burst Write
A2+1
NOP
Burst Write Write A2
A2+3
Write A3
NOP
Burst Write
A4+1
Stall
Burst Write Burst Write
A4+2
A4+3
DON'T CARE
UNDEFINED
Note32.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note33. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note34.ZZ is fixed LOW.
14/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
(5)READ/WRITE TIMING
tKHKH
CLK
tKHKL
tKLKH
tckeVKH
tKHckeX
CKE#
tEVKH
tKHEX
E#
tadvVKH
tKHadvX
ADV
tWVKH
tKHWX
W#
tBVKH
tKHBX
BWx#
tAVKH
tKHAX
A1
A2
A3
A3
A4
A4
ADD
DQ
G#
tDVKH
tKHQX1
tKHDX
D(A1)
Q(A2)
Q(A3)
Q(A3+1)
D(A4)
D(A4+1)
Q(A4)
Q(A4+1)
D(A3)
D(A3+1)
tKHQV
tKHQV
Write A1
Read A2
Deselect
Write A3 Burst Write Read A3 Burst Read Deselect
A3+1 A3+1
Write A4 Burst Write Read A4 Burst Read Deselect
A4+1 A4+1
DON'T CARE
UNDEFINED
Note35.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note36. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note37.ZZ is fixed LOW.
15/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
(6)SNOOZE MODE TIMING
CLK
tZZS
tZZREC
ZZ
All Inputs
DESELECT or READ only
(except ZZ)
Q
Snooze Mode
16/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
PACKAGE OUTLINE
Plastic 100pin 14x20 mm body
22±0.2
*2 20±0.1
0.125+0.05
80
51
-0.02
50
81
100
31
1
30
A
*3 0.32+0.06
-0.07
0.65 Nom
0.1
0.13 M
0°~7°
0.5±0.15
Detail A
Note38. Dimensions *1 and *2 don't include mold flash.
Note39 Dimension *3 doesn't include trim off set.
Note40.All dimensions in millimeters.
17/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
REVISION HISTORY
Rev. No. History
Date
0.0
First revision
November 20, 2002
Preliminary
Preliminary
DC ELECTRICAL CHARACTERISTICS
Changed ILI limit from 10uA to 100uA
(Input Leakage Current of ZZ and LBO#)
Changed Icc3 and Icc4 limit from 20mA to 30mA
(Standby Current)
0.1
January 31, 2003
The semiconductor operations of HITACHI and MITSUBISHI
Electric were transferred to RENESAS Technology
Corporation on April 1st 2003.
1.0
August 1, 2003
Preliminary
18/19
Preliminary
M5M5V5A36GP-75,85 REV.1.0
Renesas LSIs
M5M5V5A36GP-75,85
18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
Nippon Bldg.,6-2,Oteamchi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
Keep safety first in your circuit designs!
•
Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage.Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
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•
These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual
property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application
examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
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Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology
Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular,
medical, aerospace, nuclear, or undersea repeater use.
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
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Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
REJ03C0073
© 2003 Renesas Technology Corp.
New publication, effective August 2003.
Specifications subject to change without notice.
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