M62332FP#DF1R [RENESAS]

IC,D/A CONVERTER,DUAL,8-BIT,CMOS,SOP,8PIN;
M62332FP#DF1R
型号: M62332FP#DF1R
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

IC,D/A CONVERTER,DUAL,8-BIT,CMOS,SOP,8PIN

光电二极管 转换器
文件: 总10页 (文件大小:120K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Preliminary Datasheet  
M62332P/FP, M62337P/FP  
R03DS0037EJ0500  
Rev.5.00  
8-bit 2ch I2C BUS D/A Converter with Buffer Amplifiers  
Jun 03, 2011  
Description  
The M62332/M62337 is an integrated circuit semiconductor of CMOS structure with 2 channels of built in D/A  
converters with output buffer operational amplifiers.  
The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a  
microcomputer with minimum wiring.  
The output buffer operational amplifier employs AB class output circuit with sync and source drive capacity of 1.0 mA  
or more, and it operates in the whole voltage range from VCC to ground.  
The M62332 and the M62337 differ only in their slave address.  
Features  
Digital data transfer format: I2C BUS serial data method  
Output buffer operational amplifier: It operates in the whole voltage range from VCC to ground.  
High output current drive capacity: 1.0 mA over  
Application  
Conversion from digital data to analog control data for home-use and industrial equipment.  
Signal gain control or automatic adjustment of display-monitor or CTV.  
Block Diagram  
VCC  
8
SCL  
7
SDA  
6
GND  
5
I2C BUS transceiver  
Power on  
reset  
Channel  
decoder  
8
8-bit latch  
8-bit latch  
8-bit upper  
segment R-2R  
8-bit upper  
segment R-2R  
+
+ −  
1
2
AO1  
AO2  
R03DS0037EJ0500 Rev.5.00  
Jun 03, 2011  
Page 1 of 9  
M62332P/FP, M62337P/FP  
Preliminary  
Pin Arrangement  
M62332P/FP  
M62337P/FP  
AO1  
AO2  
NC  
NC  
VCC  
1
2
3
4
8
7
6
5
SCL  
SDA  
GND  
(Top view)  
NC: No connection  
Outline: PRDP0008AA-A (8P4) [P] (not recommend for new design)  
PRSP0008DE-C [FP] (recommend)  
PRSP0008DA-A (8P2S-A) [FP] (not recommend for new design)  
Pin Description  
Pin No.  
Pin Name  
Function  
6
7
1
2
8
5
SDA  
SCL  
AO1  
Serial data input terminal  
Serial clock input terminal  
8-bit resolution D/A converter output terminal  
AO2  
VCC  
Power supply terminal  
GND terminal  
GND  
R03DS0037EJ0500 Rev.5.00  
Jun 03, 2011  
Page 2 of 9  
M62332P/FP, M62337P/FP  
Preliminary  
Absolute Maximum Ratings  
Item  
Supply voltage  
Symbol  
Ratings  
–0.3 to +7.0  
Unit  
V
VCC  
Vin  
Input voltage  
–0.3 to VCC + 0.3  
–0.3 to VCC + 0.3  
417 (P) / 272 (FP)  
–20 to +85  
V
Output voltage  
VO  
V
Power dissipation  
Operating temperature  
Storage temperature  
Pd  
mW  
C  
C  
Topr  
Tstg  
–40 to +125  
Electrical Characteristics  
(VCC = +5 V 10%, GND = 0 V, Ta = –20 to +85°C unless otherwise noted)  
Limits  
Item  
Supply voltage  
Supply current  
Symbol  
VCC  
Unit  
V
Test Conditions  
Min  
2.7  
0
Typ  
5.0  
0.6  
Max  
5.5  
ICC  
2.5  
mA  
CLK = 500 kHz operation, IAO = 0 A  
Data: 6Ah (at maximum current)  
0
0.4  
1.6  
0.4  
mA  
V
SDA = SCL = GND, IAO = 0 A  
Isink = 3 mA  
Output low voltage (SDA)  
Input leak current  
Input low voltage  
VOL  
IILK  
VIL  
–10  
10  
A  
V
VIN = 0 to VCC  
0.2 VCC  
Input high voltage  
VIH  
VAO  
0.8 VCC  
0.1  
V
Buffer amplifier output  
voltage range  
VCC – 0.1  
VCC – 0.2  
1.0  
V
IAO = 100 A  
0.2  
V
IAO = 500 A  
Buffer amplifier output  
drive range  
IAO  
–1.0  
mA  
Upper side saturation voltage = 0.3 V  
Lower side saturation voltage = 0.2 V  
Differential nonlinearity  
Nonlinearity  
SDL  
SL  
–1.0  
–1.5  
–2.0  
–2.0  
5.0  
1.0  
1.5  
2.0  
2.0  
0.1  
LSB  
LSB  
LSB  
LSB  
F  
VCC = 5.12 V (20 mV/LSB)  
without load (IAO = 0)  
Zero code error  
SZERO  
SFULL  
CO  
Full scale error  
Output capacitate load  
Buffer amplifier output  
impedance  
RO  
R03DS0037EJ0500 Rev.5.00  
Jun 03, 2011  
Page 3 of 9  
M62332P/FP, M62337P/FP  
Preliminary  
I2C BUS Line Characteristics  
Item  
Symbol  
Min  
0
Max  
100  
Unit  
kHz  
s  
SCL clock frequency  
fSCL  
tBUF  
Time the bus must be free before a new transmission can  
start  
4.7  
Hold time START condition  
tHD:STA  
4.0  
s  
(After this period, the first clock pulse is generated)  
Low period of the clock  
High period of the clock  
tLOW  
4.7  
4.0  
4.7  
s  
s  
s  
tHIGH  
tSU:STA  
Set-up time for START condition  
(Only relevant for a repeated START condition)  
Hold time DATA  
tHD:DAT  
tSU:DAT  
tR  
0
s  
s  
ns  
ns  
s  
Set-up time DATA  
250  
Rise time of both SDA and SCL lines  
Fall time of both SDA and SCL lines  
Set-up time for STOP condition  
1000  
300  
tF  
tSU:STO  
4.0  
Note: Transmitter must internal provide at least a hold time to bridge the undefined region (300 ns Max) of the falling  
edge of SCL.  
Timing Chart  
tR  
, tF  
tBUF  
VIH  
SDA  
VIL  
tSU:STA  
tHD:STA  
tSU:DAT  
tHD:DAT  
tSU:STO  
V
IH  
SCL  
VIL  
tLOW  
tHIGH  
Start  
Start  
Stop  
Start  
R03DS0037EJ0500 Rev.5.00  
Jun 03, 2011  
Page 4 of 9  
M62332P/FP, M62337P/FP  
Preliminary  
I2C BUS Format  
STA  
Slave address  
W
A
Sub address  
A
DAC data  
A
STP  
Note: STA: start condition, A: affirmation bit, W: write (SDA = Low), STP: stop condition  
Slave address  
M62332  
First  
M62337  
First  
Last  
0
Last  
1
1
0
0
1
1
1
1
0
0
1
1
0
Sub address  
First  
Last  
S0  
Channel select data  
S0  
Channel Selection  
ch1 selection  
ch2 selection  
X
X
X
X
X
X
X
0
1
Don't care  
Channel  
select data  
DAC data  
First  
MSB  
Last  
LSB  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
First  
MSB  
Last  
LSB  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
DAC output  
VCC / 256 × 1  
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
1
1
:
0
1
0
1
:
VCC / 256 × 2  
VCC / 256 × 3  
VCC / 256 × 4  
:
VCC / 256 × 255  
VCC  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
R03DS0037EJ0500 Rev.5.00  
Jun 03, 2011  
Page 5 of 9  
M62332P/FP, M62337P/FP  
Preliminary  
Timing Chart (Model)  
<Start condition to slave address bit>  
SDA  
SCL  
1
2
3
4
5
6
7
W
A
D/A  
output  
Start condition  
<Sub address bit>  
SDA  
1
2
3
4
5
6
7
8
A
SCL  
D/A  
output  
<DAC data bit to stop condition>  
A
SDA  
SCL  
1
2
3
4
5
6
7
8
D/A  
output  
Stop  
condition  
Start condition  
Stop condition  
With SCL at High, SDA line goes from High to Low  
With SCL at High, SDA line goes from Low to High  
(Under normal circumstances, SDA is changed when SCL is Low)  
Acknowledge bit  
The receiving IC has to pull down SDA line whenever receive slave data.  
(The transmitting IC releases the SDA line just then transmit 8-bit data.)  
Digital Data Formats  
STA  
Slave address  
W
A
Sub address 1  
A
DAC data 1  
A
…………  
Sub address 2  
A
DAC data 2  
A
Sub address n  
A
DAC data n  
A
STP  
R03DS0037EJ0500 Rev.5.00  
Jun 03, 2011  
Page 6 of 9  
M62332P/FP, M62337P/FP  
Preliminary  
Precaution for Use  
Supply voltage terminal (VCC) is also used for D/A converter upper reference voltage setting. If ripple or spike is  
input this terminal, accuracy of D/A conversion is down. So, when use this device, please connect capacitor among  
CC to GND for stable D/A conversion.  
V
This IC’s output amplifier has an advantage to capacitive load. So it’s no problem at device action when connect  
capacitor (0.1 F Max) among output to GND for every noise eliminate.  
Purchase of Renesas’s I2C components conveys a license under the Philips I2C Patent Rights to use these  
components an I2C system, provided that the system conforms to I2C Standard Specification as defined by Philips.  
Application Example  
VCC  
AO1  
8
1
+
5 V  
10 μF  
Analog output  
terminals  
AO2  
2
3
5 V  
SCL 7  
SDA 6  
GND 5  
MCU  
4
R03DS0037EJ0500 Rev.5.00  
Jun 03, 2011  
Page 7 of 9  
M62332P/FP, M62337P/FP  
Preliminary  
Package Dimensions  
JEITA Package Code  
P-DIP8-6.3x8.84-2.54  
RENESAS Code  
Previous Code  
8P4  
MASS[Typ.]  
0.5g  
PRDP0008AA-A  
8
5
1
4
NOTE)  
1. DIMENSIONS "*1" AND "*2"  
DO NOT INCLUDE MOLD FLASH.  
2. DIMENSION "*3" DOES NOT  
INCLUDE TRIM OFFSET.  
*2  
D
Dimension in Millimeters  
Reference  
Symbol  
Min Nom Max  
e1  
D
7.32 7.62 7.92  
8.7 8.9 9.1  
E
6.3  
6.15  
6.45  
4.5  
A
SEATING PLANE  
A1  
A2  
bp  
b2  
b3  
c
0.51  
*3  
b3  
3.3  
*3  
bp  
b2  
0.4 0.5 0.6  
0.9 1.0 1.3  
1.4 1.5 1.8  
0.22 0.27 0.34  
e
0°  
15°  
e
L
2.29 2.54 2.79  
3.0  
JEITA Package Code  
P-SOP8-4.4x4.85-1.27  
RENESAS Code  
PRSP0008DE-C  
Previous Code  
MASS[Typ.]  
0.1g  
F
*1  
D
NOTE)  
8
5
1. DIMENSIONS"*1 (Nom)"AND"*2"  
DO NOT INCLUDE MOLD FLASH.  
2. DIMENSION"*3"DOES NOT  
INCLUDE TRIM OFFSET.  
bp  
Index mark  
Terminal cross section  
( Ni/Pd/Au plating )  
Dimension in Millimeters  
Reference  
Symbol  
1
4
Min Nom Max  
*3  
e
bp  
Z
D
E
A2  
4.65 4.85 5.05  
4.4 4.6  
1.85  
x
M
4.2  
L1  
A1 0.00 0.1 0.20  
2.03  
A
bp 0.34 0.4 0.46  
b1  
c
c1  
0.15 0.20 0.25  
L
θ
0° 8°  
HE 5.7 6.2 6.5  
y
Detail F  
e
1.12 1.27 1.42  
0.12  
x
y
Z
L
0.10  
0.75  
0.25 0.45 0.65  
0.90  
L1  
R03DS0037EJ0500 Rev.5.00  
Jun 03, 2011  
Page 8 of 9  
M62332P/FP, M62337P/FP  
Preliminary  
JEITA Package Code  
P-SOP8-4.4x5-1.27  
RENESAS Code  
Previous Code  
8P2S-A  
MASS[Typ.]  
0.07g  
PRSP0008DA-A  
8
5
F
NOTE)  
1. DIMENSIONS "*1" AND "*2"  
DO NOT INCLUDE MOLD FLASH.  
2. DIMENSION "*3" DOES NOT  
INCLUDE TRIM OFFSET.  
1
4
Index mark  
c
A2  
A1  
*2  
D
Dimension in Millimeters  
Reference  
Symbol  
Min Nom Max  
D
E
4.8 5.0 5.2  
4.2 4.4 4.6  
1.5  
A2  
A1  
A
0.05  
*3  
bp  
e
1.9  
0.35 0.4 0.5  
0.13 0.15 0.2  
y
bp  
c
Detail F  
0°  
10°  
HE  
e
5.9 6.2 6.5  
1.12 1.27 1.42  
0.1  
y
L
0.2 0.4 0.6  
R03DS0037EJ0500 Rev.5.00  
Jun 03, 2011  
Page 9 of 9  
Notice  
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas  
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to  
be disclosed by Renesas Electronics such as that disclosed through our website.  
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© 2011 Renesas Electronics Corporation. All rights reserved.  
Colophon 1.1  

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