M62352FP#CG1J [RENESAS]
IC,D/A CONVERTER,12-CHANNEL,8-BIT,CMOS,SOP,20PIN;
| 型号： | M62352FP#CG1J |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,D/A CONVERTER,12-CHANNEL,8-BIT,CMOS,SOP,20PIN 光电二极管 转换器 |
| 文件： | 总10页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Datasheet
M62352P/FP/GP
8-bit 12ch D/A Converter with Buffer Amplifiers
Description
R03DS0041EJ0400
Rev.4.00
Jun 03, 2011
The M62352 is an integrated circuit semiconductor of CMOS structure with 12 channels of built-in D/A converters with
output buffer operational amplifiers.
The 3-wire serial interface method is used for the transfer format of digital data to allow connection with
microcomputer with minimum wiring.
It is able to cascading serial use with DO terminal.
The output buffer operational amplifier operates in the whole voltage range from power supply to ground for both
input/output.
Features
12-bit serial data input (3-wire serial data transfer method)
Highly stable output buffer operational amplifier allow operation in the all voltage range from power supply to
ground.
Application
Adjustment/control of industrial or home-use electronic equipment, such as VTR camera, VTR set, TV, and CRT
display.
Block Diagram
GND
20
AO2
19
AO1
18
DI
CLK
16
LD
15
DO
14
AO12
13
AO11
12
VCC
11
17
12-bit shift register
D0 1
2
3
4
5
6 D7 D8 9 10 D11
8-bit R-2R
+ segment
D/A converter
D/A
L
D/A
L
D/A
Address
decoder
Ch2
1
12
11
8-bit
latch
(8)
L
L
........
....
(12)
L
(12)
(12)
8-bit
latch
L
L
L
L
L
Ch3
4
5
6
7
8
9
10
8-bit R-2R
+ segment
D/A converter
D/A
D/A
D/A
D/A
D/A
D/A
D/A
Buffer
OP AMP
1
2
3
4
5
6
7
8
9
10
VSS
(VrefL)
AO3
AO4
AO5
AO6
AO7
AO8
AO9
AO10
VDD
(VrefU)
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 1 of 9
M62352P/FP/GP
Preliminary
Pin Arrangement
M62352P/FP/GP
VSS
1
2
20 GND
(VrefL)
AO3
AO4
AO5
AO6
AO7
AO8
AO9
AO10
AO2
AO1
19
18
17
16
15
14
13
12
11
3
4
DI
5
CLK
LD
6
7
DO
AO12
8
AO11
VCC
9
VDD
10
(VrefU)
(Top view)
Outline: PRDP0020BA-A (20P4B) [P] (not recommend for new design)
PRSP0020DA-A (20P2N-A) [FP]
20P2E-A [GP]
Pin Description
Pin No.
17
14
16
15
18
19
2
Pin Name
Function
DI
Serial data input terminal
Serial data output terminal
Serial clock input terminal
DO
CLK
LD
LD terminal input high level then latch circuit data load
8-bit D/A converter output terminal
AO1
AO2
AO3
AO4
AO5
AO6
AO7
AO8
AO9
AO10
AO11
AO12
VCC
GND
VDD
VSS
3
4
5
6
7
8
9
12
13
11
20
10
1
Power supply terminal
Digital and analog common GND
D/A converter upper reference voltage input terminal
D/A converter lower reference voltage input terminal
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 2 of 9
M62352P/FP/GP
Preliminary
Block Diagram for Explanation of Terminals
VCC
GND
20
11
17
DI
12-bit shift register
D6
14
15
DO
16
D0
D1
D2
D3
D4
D5
D7
D8
D9
D10
D11
CLK
Address decoder
LD
(8)
1
2 3 4 5 6 7 8 9 10 11 12
(12)
.....
.....
D0
D7
D0
D7
8-bit latch
8-bit latch
...............................
...............................
12
8-bit
R-2R D/A
8-bit
R-2R D/A
.........................................
18
1
13
10
VDD
(VrefU)
AO1
AO12
VSS
(VrefL)
Absolute Maximum Ratings
Item
Supply voltage
Symbol
Ratings
Unit
V
VCC
VDD
VIN
–0.3 to +7.0
–0.3 to +7.0
D/A converter upper reference voltage
Input voltage
V
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
V
Output voltage
VO
V
Power dissipation
Pd
350 (P) / 300 (FP) / 150 (GP)
–20 to +85
mW
C
C
Operating temperature
Storage temperature
Topr
Tstg
–40 to +125
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 3 of 9
M62352P/FP/GP
Preliminary
Electrical Characteristics
Digital Part
(VCC, VrefU = +5 V 10%, VCC VrefU, GND, VrefL = 0 V, Ta = –20°C to +85°C, unless otherwise noted)
Limits
Item
Supply voltage
Circuit current
Symbol
VCC
Unit
V
Test Conditions
Min
4.5
—
Typ
5.0
1.6
Max
5.5
ICC
3.2
mA
CLK = 1 MHz operation
IOA = 0 A
Input leak current
Input low voltage
Input high voltage
Output low voltage
Output high voltage
IILK
VIL
–10
—
—
—
—
—
—
10
0.2 VCC
—
A
V
VIN = 0 to VCC
VIH
VOL
VOH
0.8 VCC
—
V
0.4
V
IOL = 2.5 mA
VCC – 0.4
—
V
IOH = –400 A
Analog Part
(VCC, VrefU = +5 V 10%, VCC VrefU, Ta = –20°C to +85°C, unless otherwise noted)
Limits
Item
Symbol
IDD
Unit
Test Conditions
Min
Typ
Max
Current dissipation
—
1.5
3.5
mA
VrefU = 5 V, VrefL = 0 V, IAO = 0 A
Data condition; at maximum current
D/A converter upper
reference voltage range
VDD
VSS
3.5
—
—
VCC
V
V
The output dose not necessarily be
the value within the reference voltage
setting range. The output value is
determined by the buffer amplifier
D/A converter lower
reference voltage range
GND
VCC – 3.5
output voltage range (VAO
IOA = 100 A
)
Buffer amplifier output
voltage range
VAO
IAO
0.1
0.2
–1
—
—
—
VCC – 0.1
VCC – 0.2
1
V
IOA = 500 A
Buffer amplifier output
drive range
mA
Upper side saturation voltage = 0.3 V
Lower side saturation voltage = 0.2 V
Differential nonlinearity
error
SDL
–1.0
—
1.0
LSB VrefU = 4.79 V
VrefL = 0.95 V
Nonlinearity error
Zero code error
SL
–1.5
–2
—
—
—
—
5
1.5
2
LSB
VCC = 5.5 V (15 mV/LSB)
SZERO
SFULL
CO
LSB Without load (IOA = 0 A)
Full scale error
–2
2
LSB
F
Output capacitive load
—
0.1
—
Buffer amplifier output
impedance
RO
—
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 4 of 9
M62352P/FP/GP
Preliminary
AC Characteristics
(VCC, VrefU = +5 V 10%, VCC VrefU, GND, VrefL = 0 V, Ta = –20 to +85C, unless otherwise noted)
Limits
Item
Clock "L" pulse width
Clock "H" pulse width
Clock rise time
Symbol
tCKL
tCKH
tCR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Test Conditions
Min
200
200
—
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
200
200
—
Clock fall time
tCF
—
Data setup time
tDCH
tCHD
tCHL
tLDC
tLDH
tDO
30
Data hold time
60
—
LD setup time
200
100
100
70
—
LD hold time
—
LD "H" pulse width
Data output delay time
D/A output setting time
—
350
300
CL 100 pF
tLDD
—
CL 100 pF VAO: 0.5 4.5 V
The time until the output becomes
the final value of 1/2 LSB
Timing Chart
tCR
tCKH
tCF
CLK
tCKL
tLDC
DI
tLDH
tDCH
tCHD
tCHL
LD
tLDD
D/A
output
tDO
DO
output
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 5 of 9
M62352P/FP/GP
Preliminary
Digital Data Format
First
MSB
Last
LSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11
DAC data
DAC
select data
DAC Data
D0
0
1
0
1
:
D1
0
0
1
1
:
D2
D3
D4
0
0
0
0
:
D5
D6
0
0
0
0
:
D7
0
0
0
0
:
D/A Output
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
(VrefU – VrefL) / 256 1 + VrefL
(VrefU – VrefL) / 256 2 + VrefL
(VrefU – VrefL) / 256 3 + VrefL
(VrefU – VrefL) / 256 4 + VrefL
:
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(VrefU – VrefL) / 256 255 + VrefL
VrefU
Note: VrefU = VDD, VrefL = VSS
DAC Select Data
D8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D10
0
D11
DAC Selection
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Don’t care
AO1 select
AO2 select
AO3 select
AO4 select
AO5 select
AO6 select
AO7 select
AO8 select
AO9 select
AO10 select
AO11 select
AO12 select
Don’t care
Don’t care
Don’t care
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Timing Chart (Model)
MSB
LSB
D0
.............
DI
CLK
LD
D11
D10
D9
D8
D2
D1
..................
D/A
output
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 6 of 9
M62352P/FP/GP
Preliminary
Typical Characteristics
Upper Side Saturation Voltage vs.
Output Source Current
Lower Side Saturation Voltage vs.
Output Sink Current
150
100
50
150
100
50
0
0
0
200
400
600
800
1000
0
200
400
600
800
1000
Output Source Current IAOD (µA)
Output Sink Current IAOS (µA)
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 7 of 9
M62352P/FP/GP
Preliminary
Package Dimensions
JEITA Package Code
P-SDIP20-6.3x19-1.78
RENESAS Code
PRDP0020BA-A
Previous Code
20P4B
MASS[Typ.]
1.0g
20
11
1
10
c
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*2
D
Dimension in Millimeters
Reference
Symbol
Min Nom Max
e1
D
7.32 7.62 7.92
18.8 19.0 19.2
6.15 6.3 6.45
4.5
E
A
A1
A2
bp
b3
c
0.51
*3
b3
bp
e
3.3
SEATING PLANE
0.38 0.48 0.58
0.9 1.0 1.3
0.22 0.27 0.34
0°
15°
e
L
1.528 1.778 2.028
3.0
JEITA Package Code
RENESAS Code
PRSP0020DA-A
Previous Code
20P2N-A
MASS[Typ.]
0.3g
P-SOP20-5.3x12.6-1.27
20
11
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
10
c
Index mark
*2
A2
A1
D
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
12.5 12.6 12.7
5.2 5.3 5.4
1.8
A2
A1
A
*3
bp
0
0.1 0.2
2.1
e
y
Detail F
bp
c
0.35 0.4 0.5
0.18 0.2 0.25
0°
8°
HE
e
7.5 7.8 8.1
1.12 1.27 1.42
0.1
y
L
0.4 0.6 0.8
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 8 of 9
M62352P/FP/GP
Preliminary
20P2E-A
EIAJ Package Code
SSOP20-P-225-0.65
Plastic 20pin 225mil SSOP
Weight(g)
0.08
Lead Material
Alloy 42
JEDEC Code
—
e
b2
20
11
F
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
—
Nom
—
Max
1.45
0.2
—
1
10
A
A
A
1
2
0
0.1
1.15
0.22
0.15
6.5
4.4
0.65
6.4
0.5
1.0
0.325
—
A
—
D
G
b
0.17
0.13
6.4
4.3
—
0.32
0.2
6.6
4.5
—
c
D
E
e
A2
A1
b
x
M
e
HE
6.2
0.3
—
6.6
0.7
—
y
L
L1
z
—
—
—
Z1
0.475
0.13
0.1
10°
—
x
y
—
—
—
—
c
0°
—
—
z
b2
0.35
5.8
—
Z1
Detail G
Detail F
e1
—
1.0
—
—
I2
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 9 of 9
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