M62353FP#DF1G [RENESAS]
IC,D/A CONVERTER,OCTAL,8-BIT,CMOS,SOP,16PIN;型号: | M62353FP#DF1G |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | IC,D/A CONVERTER,OCTAL,8-BIT,CMOS,SOP,16PIN 光电二极管 转换器 |
文件: | 总10页 (文件大小:113K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Preliminary Datasheet
M62353P/FP/GP
8-bit 8ch D/A Converter with Buffer Amplifiers
Description
R03DS0042EJ0400
Rev.4.00
Jun 03, 2011
The M62353 is an integrated circuit semiconductor of CMOS structure with 8 channels of built-in D/A converters with
output buffer operational amplifiers.
The 3-wire serial interface method is used for the transfer format of digital data to allow connection with
microcomputer with minimum wiring.
It is able to cascading serial use with DO terminal.
The output buffer operational amplifier operates in the whole voltage range from power supply to ground for both
input/output.
Features
12-bit serial data input (3-wire serial data transfer method)
Highly stable output buffer operational amplifier allow operation in the all voltage range from power supply to
ground.
Application
Adjustment/control of industrial or home-use electronic equipment, such as VTR camera, VTR set, TV, and CRT
display.
Block Diagram
GND
16
AO1
15
DI
CLK
13
LD
12
DO
11
AO8
10
VCC
9
14
12-bit shift register
D0 1
2
3
4
5
6 D7 D8 9 10 D11
Ch1
8-bit R-2R
+ segment
8
D/A
L
D/A converter
Address
decoder
8-bit
latch
....
(8)
........
(8)
L
(8)
(8)
8-bit
latch
L
L
L
L
Ch2
3
4
5
6
7
8-bit R-2R
+ segment
D/A converter
D/A
D/A
D/A
D/A
D/A
Buffer
OP AMP
1
2
3
4
5
6
7
8
VSS
(VrefL)
AO2
AO3
AO4
AO5
AO6
AO7
VDD
(VrefU)
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 1 of 9
M62353P/FP/GP
Preliminary
Pin Arrangement
M62353P/FP/GP
VSS
(VrefL)
1
2
3
4
5
6
7
8
16 GND
15
14
13
12
11
10
9
AO2
AO3
AO4
AO5
AO6
AO7
AO1
DI
CLK
LD
DO
AO8
VCC
VDD
(VrefU)
(Top view)
Outline: PRDP0016AA-A (16P4) [P] (not recommend for new design)
PRSP0016DE-A (16P2N-A) [FP]
PLSP0016JA-A (16P2E-A) [GP]
Pin Description
Pin No.
Pin Name
Dl
Function
Serial data input terminal
14
11
13
12
15
2
DO
CLK
LD
Serial data output terminal
Serial clock input terminal
LD terminal input high level then latch circuit data load
8-bit D/A converter output terminal
AO1
AO2
AO3
AO4
AO5
AO6
AO7
AO8
VCC
GND
VDD
VSS
3
4
5
6
7
10
9
Power supply terminal
16
8
Digital and analog common GND
D/A converter upper reference voltage input terminal
D/A converter lower reference voltage input terminal
1
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 2 of 9
M62353P/FP/GP
Preliminary
Block Diagram for Explanation of Terminals
VCC
GND
16
9
14
DI
12-bit shift register
D6
11
12
DO
LD
13
D0
D1
D2
D3
D4
D5
D7
D8
D9
D10
D11
CLK
Address decoder
(8)
1
2
3
4
5 6 7 8
(8)
.....
8-bit latch
.....
D0
D7
D0
D7
1
8
8-bit latch
...............................
...............................
8-bit R-2R
+ segment
D/A converter
8-bit R-2R
+ segment
D/A converter
.........................................
A1
A8
15
1
10
8
VDD
(VrefU)
AO1
AO8
VSS
(VrefL)
Absolute Maximum Ratings
Item
Supply voltage
Symbol
Ratings
Unit
V
VCC
VDD
VIN
–0.3 to +7.0
–0.3 to +7.0
D/A converter upper reference voltage
Input voltage
V
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
V
Output voltage
VO
V
Power dissipation
Pd
450 (P) / 300 (FP) / 150 (GP)
–20 to +85
mV
C
C
Operating temperature
Storage temperature
Topr
Tstg
–40 to +125
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 3 of 9
M62353P/FP/GP
Preliminary
Electrical Characteristics
Digital Part
(VCC, VrefU = +5 V 10%, VCC VrefU, GND, VrefL = 0 V, Ta = –20C to +85°C, unless otherwise noted.)
Limits
Item
Supply voltage
Circuit current
Symbol
VCC
Unit
V
Test Conditions
Min
4.5
—
Typ
5.0
1.0
Max
5.5
ICC
2.5
mA
CLK = 1 MHz operation
IOA = 0 A
Input leak current
Input low voltage
Input high voltage
Output low voltage
Output high voltage
IILK
VIL
–10
—
—
—
—
—
—
10
0.2 VCC
—
A
V
VIN = 0 to VCC
VIH
VOL
VOH
0.8 VCC
—
V
0.4
V
IOL = 2.5 mA
VCC – 0.4
—
V
IOH = –400 A
Analog Part
(VCC, VrefU = + 5 V 10%, VCC VrefU, Ta = –20C to +85°C, unless otherwise noted.)
Limits
Item
Symbol
Unit
Test Conditions
VrefU = 5 V, VrefL = 0 V
Min
Typ
Max
Current dissipation
IDD
—
0.9
1.7
mA
Data condition; at maximum current
D/A converter upper
reference voltage range
VDD
VSS
3.5
—
—
VCC
V
V
The output dose not necessarily be
the value within the reference voltage
setting range. The output value is
determined by the buffer amplifier
D/A converter lower
reference voltage range
GND
VCC – 3.5
output voltage range (VAO
IOA = 100 A
)
Buffer amplifier output
voltage range
VAO
IAO
0.1
0.2
–1
—
—
—
VCC – 0.1
VCC – 0.2
1
V
IOA = 500 A
Buffer amplifier output
drive range
mA
LSB
Upper side saturation voltage = 0.3 V
Lower side saturation voltage = 0.2 V
VrefU = 4.79 V
Differential nonlinearity
error
SDL
–1.0
—
1.0
VrefL = 0.95 V
Nonlinearity error
Zero code error
SL
–1.5
–2
—
—
—
—
5
1.5
2
LSB
LSB
LSB
F
VCC = 5.5 V (15 mV/LSB)
Without load (IAO = 0 A)
SZERO
SFULL
CO
Full scale error
–2
2
Output capacitive load
—
0.1
—
Buffer amplifier output
impedance
RO
—
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 4 of 9
M62353P/FP/GP
Preliminary
AC Characteristics
(VCC, VrefU = +5 V 10%, VCC VrefU, GND, VrefL = 0 V, Ta = –20 to +85C, unless otherwise noted.)
Limits
Item
Symbol
tCKL
tCKH
tCR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Test Conditions
Min
200
200
—
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
—
Clock "L" pulse width
Clock "H" pulse width
Clock rise time
—
200
200
—
Clock fall time
tCF
—
Data setup time
Data hold time
tDCH
tCHD
tCHL
tLDC
tLDH
tDO
30
60
—
LD setup time
200
100
100
70
—
LD hold time
—
LD "H" pulse width
Data output delay time
D/A output setting time
—
350
300
CL 100 pF
tLDD
—
CL 100 pF VAO: 0.5 4.5 V
The time until the output becomes
the final value of 1/2 LSB
Timing Chart
tCR
tCKH
tCF
CLK
tCKL
tLDC
DI
tLDH
tDCH
tCHD
tCHL
LD
tLDD
D/A
output
tDO
DO
output
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 5 of 9
M62353P/FP/GP
Preliminary
Digital Data Format
First
MSB
Last
LSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11
DAC data
DAC
select data
DAC Data
D0
0
1
0
1
:
D1
0
0
1
1
:
D2
D3
D4
0
0
0
0
:
D5
D6
0
0
0
0
:
D7
0
0
0
0
:
D/A Output
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
(VrefU – VrefL) / 256 1 + VrefL
(VrefU – VrefL) / 256 2 + VrefL
(VrefU – VrefL) / 256 3 + VrefL
(VrefU – VrefL) / 256 4 + VrefL
:
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(VrefU – VrefL) / 256 255 + VrefL
VrefU
Note: VrefU = VDD, VrefL = VSS
DAC Select Data
D8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D10
0
D11
DAC Selection
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Don’t care
AO1 select
AO2 select
AO3 select
AO4 select
AO5 select
AO6 select
AO7 select
AO8 select
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Timing Chart (Model)
MSB
LSB
D0
.............
DI
CLK
LD
D11
D10
D9
D8
D2
D1
..................
D/A
output
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 6 of 9
M62353P/FP/GP
Preliminary
Typical Characteristics
Upper Side Saturation Voltage vs.
Output Source Current
Lower Side Saturation Voltage vs.
Output Sink Current
150
100
50
150
100
50
0
0
0
200
400
600
800
1000
0
200
400
600
800
1000
Output Source Current IAOD (µA)
Output Sink Current IAOS (µA)
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 7 of 9
M62353P/FP/GP
Preliminary
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19-2.54
RENESAS Code
PRDP0016AA-A
Previous Code
16P4
MASS[Typ.]
1.0g
16
9
1
8
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*2
D
Dimension in Millimeters
Reference
Symbol
Min Nom Max
e1
D
7.32 7.62 7.92
18.8 19.0 19.2
E
6.15
6.3
6.45
4.5
A
A1
A2
bp
b2
b3
c
0.51
3.3
0.5
1.0
1.5
*3
*3
0.4
0.9
1.4
0.6
1.3
1.8
bp
b3
b2
e
SEATING PLANE
0.22 0.27 0.34
0° 15°
e
L
2.29 2.54 2.79
3.0
JEITA Package Code
RENESAS Code
PRSP0016DE-A
Previous Code
16P2N-A
MASS[Typ.]
0.2g
P-SOP16-5.3x10.1-1.27
16
9
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
8
Index mark
A2
A1
c
*2
D
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
10.0 10.1 10.2
5.2 5.3 5.4
1.8
A2
A1
A
0.1 0.2
2.1
0.4 0.5
0
*3
bp
c
bp
0.35
0.18
0°
e
y
Detail F
0.2
0.25
8°
HE
e
7.5 7.8 8.1
1.12 1.27 1.42
0.1
y
L
0.4 0.6 0.8
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 8 of 9
M62353P/FP/GP
Preliminary
JEITA Package Code
P-LSSOP16-4.4x5-0.65
RENESAS Code
PLSP0016JA-A
Previous Code
16P2E-A
MASS[Typ.]
0.06g
9
16
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
F
1
8
Index mark
c
A2
A1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
*2
D
D
E
4.9 5.0 5.1
4.3 4.4 4.5
1.15
A2
A
1.45
A1
bp
c
0
0.1 0.2
0.17 0.22 0.32
*3
bp
e
0.13 0.15
0°
0.2
10°
Detail F
y
HE
e
6.2 6.4 6.6
0.53 0.65 0.77
0.10
y
L
0.3 0.5 0.7
R03DS0042EJ0400 Rev.4.00
Jun 03, 2011
Page 9 of 9
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