M64110WG [RENESAS]
SPECIALTY TELECOM CIRCUIT, PBGA100, 9 X 9 MM, 0.80 MM PITCH, FBGA-100;
| 型号： | M64110WG |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SPECIALTY TELECOM CIRCUIT, PBGA100, 9 X 9 MM, 0.80 MM PITCH, FBGA-100 电信 电信集成电路 |
| 文件： | 总11页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
M64110WG
REJ03F0002-0110Z
Rev.1.10
BLUETOOTH BASEBAND LSI
2003.05.20
Description
Features
The Renesas Bluetooth Baseband provides the full
functionality of HCI, Link Manager and Baseband,
compliant with Bluetooth specification V1.1. ACL links
support DM1, DH1, DM3, DH3, DM5, DH5 and AUX
packets, whereas SCO links for voice channels sup-
port HV1, HV2, HV3 and DV packets. Flexible con-
nections can be configured by switch of master slave
role and piconet. The baseband operates at 16MHz
and reduces power dissipation using low frequency
oscillator at 32.768kHz in Sniff, Hold and Park modes.
On the transceiver side the Renesas radio IC is sup-
ported.
● Bluetooth V1.1 compliant
● HCI, Link Manager and Baseband functions
● Inquiry and Paging
● ACL link for command and data transfer
● SCO link for voice transfer (one channel)
● CRC, FEC, whitening and ARQ
● Authentication and Encryption
● Switch of master slave role
● Piconet (up to 7 devices)
● Sniff, Hold and Park mode operations
● Power control with low frequency oscillator
at 32.768kHz
The host interface is built based on HCI-UART and
has some vendor-specific commands for selecting
Radio IC type, 79-hop or 23-hop system,
● Bluetooth test mode
● Radio interface for Renesas Radio IC
● Supports 79-hop and 23-hop systems
● 14-bit linear PCM interface for voice
● CVSD, µlaw and Alaw voice codecs
● Internal microprocessor running at 16MHz
● UART for HCI interface
Write_BD_ADDR and so on.
● 100-pin FBGA 0.8mm ball pitch, 9mm x 9mm
● Operating Temperature Range -40 to 85 °C
● Digital supply voltage 1.8 to 2.0V for internal circuit
Digital supply voltage 2.7 to 3.3V for I/O ports
Analog supply voltage 2.7 to 3.3V
CPU
DMA
Reset / Clock
Interrupt Cont.
Timer
Mode / Interrupt
Reset/Clock
Mode/Int. IF
SRAM
MaskROM
Renesas
HCI-UART
UART
Bluetooth
Baseband
Baseband
Hardware
Voice PCM
RF IF
RF IC
CVSD, µ law,Alaw
Functional Block Diagram
Bluetooth and Bluetooth logos are owned by its proprietor and used by Renesas Technology Corporation under license.
This is not a final specification. Some parameters limits are Subject to change.
Rev.1.10 2003.4.18 page 1 of 10
M64110WG
Device Pinout Diagram (100-pin FBGA)
Orientation from top of device
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
NU
MODE[0]
MODE[1]
NU
VUDATA
VDDATA
NU
VBITCLK
DVSS3
EXIREQ
UCTS
URTS
DVDD3
NU
NU
DVSS18
NU
MODE[2]
AVSS3
AVDD3
RXDATA
NU
AVSS3
AVDD3
AVSS3
NU
AVDD3
AVSS3
PLLON
NU
RSSIA
AVDD3
TXGATE
RXON
NU
NU
URXD
DVDD3
INTOUT
DVDD3
V8KFP
NU
UTXD
DVSS3
DVDD18
NU
DVSS18
CLK16MSEL DVDD18
TXON
RXANT
SERDATA
NU
DVDD18
TXANT
DVSS18
DVSS3
CLK16MXIN CLK16MXOUT DVSS3
CLK16MOUT CLK16MREQ RSTIN
NU
DVDD3
DVSS3
NU
DVDD3
NU
TXDATA
SERLE
NU
G
H
J
SERCLK TXDBASE
CLK16MIN
XRDY
CLKTHR
NU
NU
NU
NU
NU
NU
NU
NU
RXDBASE
NU
CLK32KSEL
NU
DVSS18
DVDD18
NU
NU
K
CLK32KXIN CLK32KXOUT
NU
NU
NU
NU
NU
TOP VIEW
Rev.1.10 2003.4.18 page 2 of 10
M64110WG
Pin Description for 100-pin FBGA
Type
Dir
Description
Pin Name for 100-pin
HCI-UART
UTXD
URXD
URTS
UCTS
VBITCLK
V8KFP
VDDATA
VUDATA
TXDATA
TXGATE
RXDATA
PLLON
TXANT
TXON
RXANT
RXON
SERCLK
SERLE
Dig
Dig
Dig
Dig
Dig
Dig
Dig
Dig
Dig
Dig
Ana
Dig
Dig
Dig
Dig
Dig
Dig
Dig
Dig
Ana
Dig
Dig
Dig
Dig
Dig
Dig
Dig
Dig
Dig
Out Transmit data
In
Out Request to send
In Clear to send
In/Out Voice bit clock
In/Out Voice 8kHz frame pulse
In Voice downstream data
Receive data
Voice
Interface
Out Voice upstream data
Out Transmit data
Out Transmit gate
RF
Interface
In
Receive data
Out PLL power on
Out Transmitter antenna select
Out Transmitter power on
Out Receiver antenna select
Out Receiver power on
Out Serial interface clock
Out Serial interface control
Out Serial interface data in
SERDATA
RSSIA
In
RSSI(Reserved)
TXDBASE
RXDBASE
MODE[2:0]
EXIREQ
INTOUT
RSTIN
XRDY
CLKTHR
CLK16MSEL
Out Transmit data for Baseband connection(for Test/Debug)
In
In
In
Receive data for Baseband connection(for Test/Debug)
Mode select
External interrupt request in
Mode
Interrupt
Out Interrupt out
Reset
Clock
In
In
In
In
External reset in
Oscillator circuit ready
16MHz clock source select
16MHz clock source select(TCXO or Oscillator)
CLK16MREQ Dig
Out External 16MHz clock request
CLK16MIN
Dig
Xin
In
In
External 16MHz clock in
16MHz crystal in
CLK16MXIN
CLK16MXOUT Xout
CLK16MOUT Dig
Out 16MHz crystal out
Out External 16MHz clock out
CLK32KSEL
CLK32KXIN
Dig
Xin
In
In
32.768KHz clock source select
32.768kHz crystal in
CLK32KXOUT Xout
Out 32.768kHz crystal out
Rev.1.10 2003.4.18 page 3 of 10
M64110WG
Type
VDD
GND
VDD
GND
VDD
GND
Dir
Description
Digital power supply for I/O ports
Digital ground for I/O ports
Digital power supply for internal logic
Digital ground for internal logic
Analog Power Supply
Pin Name for 100-pin
Power
DVDD3
DVSS3
DVDD18
DVSS18
AVDD3
AVSS3
-
-
-
-
-
-
Ground
Analog Ground
(Note1) NU pins should be opened.
Rev.1.10 2003.4.18 page 4 of 10
M64110WG
Absolute Maximum Ratings
Symbol
VDD3
(Note1)
VDD18
(Note2)
VI
Item
Condition
Rating
Unit
V
Supply Voltage
-0.3 to 4.2
Supply Voltage
-0.3 to 2.5
V
Input Voltage
Input Voltage
CLK16MIN
Except
-0.3 to VDD18+0.3
-0.3 to VDD3+0.3
V
V
VI
CLK16MIN
VO
Output Voltage
-0.3 to VDD3+0.3
-55 to +125
V
Tstg
Storage Temperature
°C
(Note1) DVDD3, AVDD3
(Note2) DVDD18
Recommended Operating Condition
Symbol
Item
Condition
Rating
Unit
V
Min
2.7
Typ
3.0
Max
VDD3
(Note1)
VDD18
(Note2)
VIH
Supply Voltage
Supply Voltage
3.3
1.8
1.9
2.0
V
‘H’ Level Input Voltage
‘L’ Level Input Voltage
Except
0.7 x VDD3
V
V
CLK16MIN
VIL
0.8
85
Topr
Operating Temperature range
-40
°C
(Note1) DVDD3, AVDD3
(Note2) DVDD18
Rev.1.10 2003.4.18 page 5 of 10
M64110WG
Electrical Characteristics (Unless otherwise stated: VDD3=2.7 to 3.3V,VDD18=1.8 to 2.0V,Topr=-40°C to +85°C)
Measurement
Symbol
Item
Rating
Typ
Unit
V
Condition
Min
VDD3-0.4
Max
VOH1
‘H’ Level Output Voltage
IOH=-1mA
UTXD,URTS,VBITCLK
V8KFP,VUDATA,PLLON
TXGATE,TXON,RXON
SERLE,SERCLK
VOL1
‘L’ Level Output Voltage
IOL=+1mA
0.4
V
SERDATA,TXDBASE
CLK16MREQ,INTOUT
MODE[2:0]
TESTOUT[11:0]
CLK16MOUT
VDD3-0.4
VDD3-0.4
VOH2
VOL2
VOH3
VOL3
IIH1
‘H’ Level Output Voltage
‘L’ Level Output Voltage
‘H’ Level Output Voltage
‘L’ Level Output Voltage
High State Input Current
(Note 1)
IOH=-2mA
IOL=+2mA
IOH=-4mA
IOL=+4mA
VIH=VDD3
V
V
0.4
TXDATA,TXANT,RXANT
V
0.4
1
V
URXD,UCTS,VBITCLK
V8KFP,VDDATA,RSTIN
XRDY,CLKTHR
µA
CLK16MSEL,INTOUT
CLK32KSEL
IIL1
IIH2
IIL2
Low State Input Current
VIL=0V
-1
µA
µA
µA
(Note 1)
EXIREQ
High State Input Current
Low State Input Current
VIH=VDD3
1
VDD3=3V
VIL=0V
-30
-15
15
-10
30
RXDBASE,
IIH3
IIL3
High State Input Current
(Note 1)
VDD3=3V
10
-1
µA
µA
TSTMODE[5:1]
TESTOUT[11:0]
VIH=VDD3
Low State Input Current
VIH=0V
(Note 1)
(Note 1) In/Out pins were measured with Output off.
Timing Requirements (Unless otherwise stated: VDD3=2.7 to 3.3V,VDD18=1.8 to 2.0V)
Condition
Symbol
Item
Rating
Typ
Unit
Min
40
Max
CLK16MIN Within +/-20ppm
CLK32XIN
CLK16MIN
CLK32XIN
CLK16MIN
CLK16MIN
RSTIN
fCLK16MIN
fCLK32KIN
fDUTY
16MHz Clock Input Frequency
32kHz Clock Input Frequency
Clock Input Duty
16
MHz
kHz
%
32.768
60
tr
tf
Clock Input Rise Time
Clock Input Fall Time
5
5
ns
ns
tw(RSTIN)
(Note1)
Reset Input ‘L’ Pulse width
2
ms
(Note1) When power on, sufficient reset period is needed.
Rev.1.10 2003.4.18 page 6 of 10
M64110WG
Example of UART Interface behavior
Transmit Timing
1 data Transmitting
1 data Transmitting
Basic Transmit Clock
UCTS
UTXD
Notes)
• If the UCTS input pin changes to ‘H’ during the transmission of data byte and active
UCTS function, the transmission stops after finishing the current transmission.
• Start and stop of transmission and UCTS function are executed by internal process-
ing of Baseband.
• Basic clock is determined by the value set by internal baud rate.
Receive Timing
1data receiving
1data receiving
1datareceiving
URXD
URTS
*1
*2
*1
Notes)
• The above timing chart shows the status when 2 bytes data are received, 1 of 2 bytes received data is read, and
then the next receiving are executed.
• If the most significant bit of the new data is received before reading received data from the received data register,
the URTS pin becomes ‘H’
• When the URTS pin is ‘H’, the UART becomes receive data storage status. Although receive operation is com-
pleted, the contents of receive shift buffer is not stored in the received data register. (*1)
• When the URTS pin is ‘H’, if the received data register is read, then the data of receive shift buffer in receive data
storage status is stored in the received data register, and then each receive error flag and receive buffer flag for
receive data stored at that time are set cumulatively, and then the URTS pin becomes ‘L’ (*2).
• If negative edge (level sense) is fed into the URXD input pin, receive control circuit judge that it is start bit and
then sampling is executed around center of start bit. If the sampling input is ‘L’, receive sequence is started.
Rev.1.10 2003.4.18 page 7 of 10
M64110WG
Example of Voice Interface’s behavior
Timing Diagram
125µs
V8KFP
(8kHz)
VBITCLK
(128kHz-256kHz)
MSB 15
0
0
LSB
LSB
MSB 15
MSB 15
VDDATA(in)
MSB 15
VUDATA(out)
Last2 bits shall be discarded
Notes)
• VBITCLK can use the frequencies between 128Hz and 8kHz in steps of 8kHz.
• Last 2 bits of VDDATA and VUDATA will be discarded.
Rev.1.10 2003.4.18 page 8 of 10
M64110WG
Package Diagram (100FHE)
Rev.1.10 2003.4.18 page 9 of 10
M64110WG
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
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Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Rev.1.10 2003.4.18 page 10 of 10
REVISION HISTORY
M64110WG Data Sheet
Rev.
Date
Description
Summary
Page
−
1.00
1.10
Apr. 1,2002
Feb.11.2003
First Edition
1,5,6
1,5,6
Digital supply voltage for I/O ports and analog supply voltage 2.7 to 3.3V
Operating Temperature Range -40 to 85 °C
(1/1)
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